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nor flash memory k8p5615uqa revision 1.1 july 2007 1 256mb a-die page nor specification * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure couldresult in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
nor flash memory k8p5615uqa revision 1.1 july 2007 2 document title 256m bit (16m x16) pa ge mode / multi-bank nor flash memory revision history revision no. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 1.1 remark target information target information target information target information target information target information history initial draft change vih min. from 2.0 to vcc x0.8 change vil max. from 0.8v to vcc x 0.2 change isb max from 40ua to 55ua mcp product voltage information is added tsop1 description is added in ordering information package demension information is added change isb2 max. from 40ua to 55ua change isb3 max. from 40ua to 55ua specification is finalized change isb1 max. from 55ua to 60ua change isb2 max. from 55ua to 60ua change isb3 max. from 55ua to 60ua draft date october 02, 2006 october 25, 2006 november 06, 2006 november 13,2006 november 19, 2006 january 11, 2007 may 08, 2007 july 27, 2007
nor flash memory k8p5615uqa revision 1.1 july 2007 3 256m bit (16m x16) page mode / multi-bank nor flash memory ? endurance : 100,000 program/erase cycles minimum ? data retention : 10 years ? package options - 84 ball fine-pitch bga (11.6x8mm) - 56 pin tsop (20x14mm) the k8p5615uqa featuring single 3.0v power supply, is an 256mbit nor-type flash memory organized as 16m x16. the memory architecture of the dev ice is designed to divide its memory arrays into 134 blocks with independent hardware pro- tection. this block architecture provides highly flexible erase and program capability. the k8 p5615uqa nor flash consists of four banks. this device is capable of reading data from one bank while programming or erasing in the other banks. the k8p5615uqa offers fast page access time of 30ns with random access time of 70ns. the device s fast access times allow high speed microprocessors to operate without wait states. the device performs a program operation in unit of 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed within typically 1.6 sec. the device requires 15ma as program/ erase current in the commercial and extended temperature ranges. the k8p5615uqa nor flash memory is created by using samsung's advanced cmos process technology. this device is available in 84 ball fbga and 56 pin tsop. the device is com- patible with eprom applicati ons to require high-density and cost-effective nonvolatile read/write storage solutions. features ? single voltage, 2.7v to 3.6v for read and write operations voltage range of 2.7v to 3.1v valid for mcp product ? organization 16m x16 bit (word mode only) ? fast read access time : 70ns ? page mode operation 8 words page access allows fast asychronous read page read access time : 30ns ? read while program/erase operation ? multiple bank architectures (4 banks) bank 0: 32mbit (32kw x 4 and 128kw x 15) bank 1: 96mbit (128kw x 48) bank 2: 96mbit (128kw x 48) bank 3: 32mbit (32kw x 4 and 128kw x 15) ? otp block : extra 256 word - 128word for factory and 128word for customer otp ? power consumption (typical value) - active read current : 30ma (@5mhz) - program/erase current : 25ma - read while program or read while erase current : 65ma - standby mode/auto sleep mode : 20ua ? support single & 32word buffer program ? wp /acc input pin - allows special protection of two outermost boot blocks on both ends of flash array at v il , regardless of block protect status - removes special protection at v ih, the two outermost blocks on both ends of flash array return to normal block protect status - reduce program time at v hh : 6us/word at write buffer ? erase suspend/resume ? program suspend/resume ? unlock bypass program ? hardware reset pin ? command register operation ? supports common flash memory interface ? industrial temperature : -40 c to 85 c ? extended temperature : -25 c to 85 c general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description pin name pin function a0 - a23 address inputs dq0 - dq15 data inputs / outputs ce chip enable oe output enable reset hardware reset pin ry/by ready/busy output we write enable wp /acc hardware write protection/program acceleration vcc power supply v ss ground nc no connection
nor flash memory k8p5615uqa revision 1.1 july 2007 4 84 ball fbga top view (ball down) dnu a b c d e f g h j k l m 123 45678 910 dnu dnu dnu rfu rfu rfu rfu rfu rfu rfu rfu rfu a7 rfu wp / acc we a8 a11 rfu a3 a6 rfu reset a19 a12 a15 rfu a2 a5 a18 ry/by a9 a13 a21 a20 a1 a4 a17 a10 a14 a22 a23 rfu a0 vss dq1 dq6 rfu a16 rfu rfu ce oe dq9 dq13 dq15 rfu dq4 dq3 dq0 dq10 dq12 dq7 vss rfu vcc rfu dq8 dq2 dq5 dq14 rfu rfu dq11 rfu rfu rfu vcc rfu rfu rfu rfu rfu
nor flash memory k8p5615uqa revision 1.1 july 2007 5 tsop pin configuration 56-pin tsop1 standard type 14mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc a1 a2 a3 a23 a6 a22 a4 a5 a10 a11 a12 a14 nc nc a16 nc vss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq10 dq2 dq9 dq1 dq8 dq0 oe vss ce 25 26 27 a13 a15 32 31 30 a0 nc vccq a9 a8 a19 a20 we reset a21 rd/by a18 wp /acc a17 a7 28 29 dq3
nor flash memory k8p5615uqa revision 1.1 july 2007 6 functional block diagram interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank 1 cell array bank 0 address bank 1 address bank 0 cell array x dec y dec latch & control bank 3 cell array block inform bank 3 address i/o vcc vss ce oe we reset ry/by a0~a23 dq0~dq15 wp /acc
nor flash memory k8p5615uqa revision 1.1 july 2007 7 table 1. product line-up 4d vcc 2.7v~3. 6 v vio 2.7v~3. 6 v max. address access time (ns) 70ns max. ce access time (ns) 70ns max. oe access time (ns) 30ns max. page access time (ns) 30ns ordering information k 8 p 56 15 u q a - p i 4d samsung nor flash memory device type page mode density & bank architecture 256 mbits & 16 mbits x 16 operating temperature range c = commercial temp. (0 c to 70 c) e = extended temp. (-25 c to 85 c) i = industrial temp. (-40 c to 85 c) block architecture q = top and bottom boot block version 2th generation access time 4d = 70ns/30ns operating voltage range 2.7v to 3.6v package d = fbga(lead free) , f = fbga, p = tsop1(lead free) organization x16 selectable table 2. k8p5615uqa device bank divisions bank 0, bank 3 bank 1, bank 2 mbit block sizes mbit block sizes 32 mbit 32 kw x 4 and 128 kw x 15 96 mbit 128 kw x 48 table 3. otp block after entering otp block, any issued addresses should be in the range of otp block address otp block address a23~a8 area block size address range 0000h factory-locked area 128 words 000000h-00007fh customer-locked area 128 words 000080h-0000ffh
nor flash memory k8p5615uqa revision 1.1 july 2007 8 product introduction the k8p5615uqa is an 256mbit nor-type flas h memory. the device features single voltage power supply operating within the range of 2.7v to 3. 6 v. the device is programmed by using the channel ho t electron (che) injection mechanism which is used to program eproms. the device is erased elec trically by using fowler-n ordheim tunneling mechanism. to provide highly flexible erase and program capability, the device adapts a block memory ar chitecture that divides its me mory array into 134 blocks (32 k w x 8, 128 kw x 126). programming is done in units of 16 bits (word). all bits of data in one or multiple blocks can be erased simu lta- neously when the device executes the erase oper ation. the device offers fast page access time of 30ns with random access time o f 70ns supporting high speed microprocessors to operate without any wait states. the command set of k8p5615uqa is fully compatible with stan dard flash devices. the device is controlled by chip enable (ce ), out- put enable (oe ) and write enable (we ). device operations are executed by sele ctive command codes. the command codes to be combined with addresses and data are sequentially written to the command registers using microproc essor write timing. the com- mand codes serve as inputs to an internal state machine which c ontrols the program/erase circuitr y. register contents also inte rnally latch addresses and data necessary to execute the program and eras e operations. the k8p5615uqa is implemented with internal program/erase algorithms to execute the program/erase operations . the internal program/erase algorithms are invoked by pro- gram/erase command sequences. the internal program algorithm aut omatically programs and verifies data at specified addresses. the internal erase algorithm automatically pre-programs the me mory cell which is not progra mmed and then executes the erase operation. the k8p5615uqa has means to indicate the status of completion of program/erase operations. the status can be indi- cated via the ry/by pin, data polling of dq7, or the toggle bit (dq6). once the operations have been completed, the device auto- matically resets itself to the read mode. table 4. operations table operation ce oe we wp /acc a0 ~ 23 dq0 ~ dq15 reset read l l h x a in d out h stand-by h x x x a in high-z h output disable l h h x a in high-z h reset x x x x a in high-z l write l h l x (note 1) a in d in h notes : l = v il (low), h = v ih (high), d in = data in, d out = data out, x = don't care. 1. wp /acc must be v ih when writing to upper two and lower two blocks (ba0, ba1, ba132, and ba133)
nor flash memory k8p5615uqa revision 1.1 july 2007 9 command definitions the k8p5615uqa operates by selecting and executing its operat ional modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. the defined valid register command sequences are stated in table 5. table 5. command sequences command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle read addr 1 r a data rd reset addr 1 xxxh data f0h autoselect manufacturer id (note 1, 2) addr 4 555h 2aah da/555h da/x00h data aah 55h 90h ech autoselect device id (note 1, 2, 3) addr 6 555h 2aah da/555h da/x01h da/x0eh da/x0fh data aah 55h 90h 227eh 2263h 2260h autoselect block protect verify (note 1, 2) addr 4 555h 2aah da/555h ba / x02h data aah 55h 90h (see table 6) autoselect indicator bit (note 1, 2) addr 4 555h 2aah da/555h x03h data aah 55h 90h (see table 6) program addr 4 555h 2aah 555h pa data aah 55h a0h pd write to buffer (note 4) addr 6 555h 2aah ba ba pa wbl data aah 55h 25h wc pd pd program buffer to flash addr 1 ba data 29h write to buffer abort reset (note 4) addr 3 555h 2aah 555h data aah 55h f0h unlock bypass addr 3 555h 2aah 555h data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass block erase addr 2 xxxh ba data 80h 30h unlock bypass chip erase addr 2 xxxh xxxh data 80h 10h unlock bypass reset addr 2 xxxh xxxh data 90h 00h unlock bypass cfi addr 1 dah data 98h chip erase addr 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase addr 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h block erase suspend (note 5, 6) addr 1 xxxh data b0h block erase resume addr 1 xxxh data 30h
nor flash memory k8p5615uqa revision 1.1 july 2007 10 table 5. command sequences (continued) command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle program suspend (note 7 ,8) addr 1 xxxh data b0h program resume addr 1 xxxh data 30h cfi query (note 9) addr 1 da/x55h data 98h enter otp block region addr 3 555h 2aah 555h data aah 55h 88h otp block program addr 4 555h 2aah 555h pa data aah 55h a0h pd otp block read addr 1 ra data rd exit otp block region addr 4 555h 2aah 555h xxxh data aah 55h 90h 00h enter otp block lock register region addr 3 555h 2aah 555h data aah 55h 40h otp block lock register bit program addr 2 xxxh 00h data a0h (note 10) exit otp block lock register region addr 2 xxxh xxxh data 90h 00h notes : ? ra : read address, pa : program address, rd : read data, pd : program data, wbl : write buffer location ? da : bank address (a21 - a23), ba : block address (a15 - a23) , abp : address of the block to be protected or unprotected, x = don?t care . ? dq8 - dq15 are don?t care in command sequence, except for rd and pd ? a14 - a23 are also don?t care, except for the case of special notice. 1. to terminate the autoselect mode, it is necessary to write reset command to the register. 2. the 4th cycle data of autoselect mode is output data. the 3rd and 4th cycle bank addresses of autoselect mode must be same. 3. device id must be read across cycles 4, 5 and 6. device id data : x0eh = "2263h", x0fh = "2260h" for 256mb top and boot block device 4. command sequence resets device for next command after write-to-buffer operation. 5. the read / program operations at non- erasing blocks and the autoselect mode are allowed in the erase suspend mode. 6. the erase suspend co mmand is applicable only to the block erase operation. 7. the read operation is allowed in the program suspend mode. 8. the program suspend command is applicable to program and erase suspend - program operation. 9. command is valid w hen the device is in read mode or autoselect mode. 10. programming dq0 (setting to zero), non-volatile bit locks the otp block region permanently. table 6. k8p5615uqa autoselect codes notes : 1. l=logic low=v il , h=logic high=v ih , da= bank address, ba=block address, x=don?t care . description ce oe we a22 - a12 a10 - a4 a3 a2 a1 a0 dq15 - dq8 dq7 - dq0 manufacturer id l l h da x l l l l x ech device id read cycle1 l l h da x l l l h 22h 7eh read cycle2 l l h da x h h h l 22h 63h read cycle3 l l h da x h h h h 22h 60h block protection verification llh ba x llhl x 01h : (proected) 00h : (unproteced) indicator bit l l h da x l l h h x dq15~8 : v il dq7 : factory lock bit dq6 : customer lock bit dq5 : handshake bit dq4~3 : wp protection code dq2~0 : v il
nor flash memory k8p5615uqa revision 1.1 july 2007 11 device operation read mode the k8p5615uqa is controlled by chip enable (ce ), output enable (oe ) and write enable (we ). when ce and oe are low and we is high, the data stored at the specified address location,wi ll be the output of the device. the outputs are in high impedance state whenever ce or oe is high. the k8p5615uqa is available for 8-word page mode. page m ode provides fast access time for high performance system. after address access time(taa), eight data words are loaded into an internal page buffer. a0~a2 bits determine which page word is output during a read operation. a3~a23 bits must be stable throughout the page read access. figure 11 shows the asynchronous page read more timing. standby mode the k8p5615uqa features stand-by mode to reduce power consum ption. this mode puts the device on hold when the device is deselected by making ce high (ce = v ih ). refer to the dc characteristics for more details on stand-by modes. output disable the device outputs are disabled when oe is high (oe = v ih ). the output pins are in high impedance state. automatic sleep mode the k8p5615uqa features automatic sleep mode to minimize t he device power consumption. when addresses remain steady for t aa +30ns, the device automatically activates t he automatic sleep mode. in the sleep mode, output data is latched and always avail- able to the system. when addresses are changed, the device provides new data without wait time. data outputs t aa + 30ns data auto sleep mode address data data data data figure 1. auto sleep mode operation autoselect mode the k8p5615uqa offers the autoselect mode to identify manufactu rer, device type and block protec tion verification by reading a binary code. the autoselect mode allows programming equipment to automatically match the device to be programmed with its cor- responding programming algorithm. the manufacturer, device code ,blo ck protection verification and indicator bit can be read vi a the command register. the command sequence is shown in table 6 and figur e 2. in addition, below table 7 shows indicator bit in deta il. the autoselect operation of block protection verification is initiated by first writin g two unlock cycle. the third cycle must contain the bank address and autoselect command (90h). if block address while (a6, a1, a0) = (0,1,0 ) is finally asserted on the address pin , it will produce a logical "1" at the device output dq0 to indicate a write protected block or a logical "0" at the device output d q0 to indi- cate a write unprotected block. to terminate the autoselect oper ation, write reset command (f0h) into the command register. table 7. indicator bit codes . description dq15 to dq8 dq7 dq6 dq5 dq4 to dq3 dq2 to dq0 indicator bit l 1=factory-locked 0=not locked 1=customer-locked 0=not locked 1=reserved 0=standard handshake 00=wp protects both top & bottom boot sector 11=no wp protection l
nor flash memory k8p5615uqa revision 1.1 july 2007 12 figure 2. autoselect operation ( by command sequence method ) we 555h 2aah 555h aah 55h 90h 00h 01h ech manufacturer id device id address dq15 dq0 write (program/erase) mode the k8p5615uqa executes its program/erase op erations by writing commands into the command register. in order to write the com- mands to the register, ce and we must be low and oe must be high. addresses are latched on the falling edge of ce or we (which- ever occurs last) and the data are latched on the rising edge of ce or we (whichever occurs first) . the device uses standard microprocessor write timing. program the k8p5615uqa can be programmed in units of a word. programming is writing 0's into the memory array by executing the inter- nal program routine. in order to perform the internal program routine, a four-cycle command s equence is necessary. the first tw o cycles are unlock cycles. the third cycle is assigned for the program setup command. in the last cycle, the address of the memo ry location and the data to be programmed at that location are wri tten. the device automatically generates adequate program pulses and verifies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not required to provide further controls or timings. during the internal program routine, commands written to the devi ce will be ignored. note that a hardware reset during a progra m operation will cause data corruptio n at the corresponding location. figure 3. program command sequence we 555h 2aah 555h aah 55h a0h program program program start dq15-dq0 address data ry/by note : the 3rd cycle and 4th cycle address must include the sa me bank address. please refer to table 6 for device code. ( k8p5615uqa ) address 227eh 0eh 2263h 0fh 2260h
nor flash memory k8p5615uqa revision 1.1 july 2007 13 in accross block boundaries and any sequence pr ogramming is allowed. a bit cannot be programmed from ?0? back to ?1?. if attemp t- ing to do, it may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful . however, a succeeding read will show that the data is stil l ?0?. only erase operations can convert a ?0? to a ?1?. writer buffer programming write buffer programming allows the system write to a maximu m of 32 words in one programming operation. this results in faster effective programming time than the standard programming algorit hms. the write buffer programming command sequence is initi- ated by first writing two unlock cycles. th is is followed by a third write cycle containing the write buffer load command writt en at the block address in which programming will occu r. the fourth cycle writes the block address and the number of word locations, minu s one, to be programmed. for example, if the system will pr ogram 19 unique address locations, then 12h should be written to the device. this tells the device how many wr ite buffer addresses will be loaded with data. the number of locations to program cann ot exceed the size of the write buffer or the operation will abor t. the fifth cycle writes the fi rst address location and data to be pro- grammed. the write-buffer-page is selected by address bits a23(max.) ~ a5 entered at fifth cycle . all subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit a23(max.) ~ a5 as those entered at fifth cycle. write buffer locations may be loaded in any order. once the specified number of write buffer locations have been loaded, the system must then write the "program buffer to flash" com mand at the block address. any other command address/data comb ination aborts the write buffer programming operation. the device then begins programming. data polling should be used while m onitoring the last address location loaded into the write bu ffer. dq7, dq6, dq5, and dq1 can be monitored to determine the device status during write buffer programming. the write-buffer pro- gramming operation can be suspended using the standard program su spend/resume commands. upon su ccessful completion of the write buffer programming operation, the devic e is ready to execute the next command. note also that an address loaction cannot be loaded more than once into the write-buffer-page. figure 4. write buffer program command sequence we 555h 2aah aah 55h 25h program start dq15-dq0 pa 12h pd 29h ry/by address block address block address block address wbl pd accelerated program operation accelerated program operation reduces the program time through th e acc function. this is one of two functions provided by the wp /acc pin. when the wp /acc pin is asserted as v hh , the device automatically enters t he unlock bypass mode, temporarily unprotecting any protected bl ocks, and reduces the program operation time. removing v hh from the wp /acc pin returns the device to normal operation. recommend that the wp /acc pin must not be asserted at v hh except on accelerated program operation, or the device may be damaged. in addition, the wp /acc pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. single word accelerated program operation the system would use two-cycle program sequence (one-cycle (xxx - a0h) is fo r single word program command, and next one- cycle (pa - pd) is for program address and data ). accelerated write buffer programming in accelerated write buffer program mode, the system must enter "write to buffer" and "program buffer to flash" command sequence to be same as them of normal write buffer programming and only can reduce the program time. note that the third cycle of "write to buffer abort reset" command sequence is required in an accelerated mode. note that read while accelerated write buffer program and program suspend mode are not guaranteed. ? program/erase cycling must be limite d below 100cycles for optimum performance. ? ambient temperature requirements : t a = 30 c10 c ? the device automatically generates adequate program pu lses and ignores other command after program command ? program/erase cycling must be limited below 100cycles for optimum performance
nor flash memory k8p5615uqa revision 1.1 july 2007 14 unlock bypass the k8p5615uqa provides the unlock bypass mode to save its operat ion time. this mode is possible for program, cfi, block erase and chip erase operation. there are two methods to enter the unlock bypass mode. the mode is invoked by the unlock bypass com- mand sequence. unlike the standard program/erase command sequence that contains four to six bus cycles, the unlock bypass pro- gram/erase command sequence comprises only two bus cycles. the unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. writing fi rst two unlock cycles is follow ed by a third cycle containin g the unlock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. the unlock bypass program command sequenc e is comprised of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the program addr ess and data. this command sequence is the only valid one for programming the device in the unlock bypass mode. the unlock bypass cfi command sequenc e is comprised of only one bus cycle; writing the unlock bypass program command (98h). this command sequence is the only valid one for programming the device in the unlock bypass mode. also, the unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80h-30h) or writing the unlock bypass chip erase command(80h-10h). this command sequences are the only valid ones for erasing the device in the unlock bypass mode. the unlock by pass reset command sequence is the only valid command sequence to exit the unlock bypass mode. the unlock bypass reset command s equence consists of two bus cycles. the first cycle must contain the data (90h). t he second cycle contains only the data (00h). then, the device returns to the read mo de. chip erase to erase a chip is to write 1 s into the entire memory array by executing the inte rnal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is wr itten after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the internal erase routine automatica lly pre-programs and verifies t he entire memory for an all zero data pattern prior to erasing. the automatic erase begins on the rising edge of the last we or ce pulse in the command sequence and terminates when dq7 is "1 ". after that the device returns to the read mode. figure 5. chip erase command sequence we 555h 2aah 555h aah 55h 80h 555h chip erase start dq15-dq0 2aah aah 55h 10h ry/by 555h address block erase to erase a block is to write 1 s into the desired memory block by executing the in ternal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 5. afte r the first two "unlock" cycles, the erase setup command (80h) i s written at the third cycle. then there ar e two more "unlock" cycles followed by the block erase command. the internal erase rou tine automatically pre-programs and verifies the entire memory prio r to erasing it. the block addres s is latched on the falling edge of we or ce , while the block erase command is latched on the rising edge of we or ce . multiple blocks can be erased sequentially by writing the six bus-cycle. upon completion of the last cycle for the block erase, addi- tional block address and the block erase command (30h) can be writt en to perform the multi-block erase. an 50us (typical) "time window" is required between the block eras e command writes. the block erase command must be written within the 50us "time window", otherwise the block erase command will be ignored. t he 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time window" to latch the block er ase command. during the 50us of "time window", any command other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50 us of "time window", the block erase command will initiate the internal erase routine to erase the selected blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command.
nor flash memory k8p5615uqa revision 1.1 july 2007 15 we dq15-dq0 figure 7. erase suspend/resume command sequence erase suspend / resume the erase suspend command interrupts the block erase to read or program data in a block that is not being erased. the erase sus - pend command is only valid during the block erase operation including the time window of 50us. the erase suspend command is not valid while the chip erase or the in ternal program routine sequence is running. when the erase suspend command is written during a block eras e operation, the device requires a maximum of 20us to suspend the erase operation. but, when the erase suspend command is writt en during the block erase time window (50us) , the device imme - diately terminates the block erase time window and suspends the erase operation. after the erase operation has been suspended, the device is availble for reading or programming data in a block that is not bei ng erased. the system may also write the autoselect comm and sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase oper ation will resume. when the erase suspend or erase resume command is executed, the addresses are in don't care state. address 555h block address aah 30h xxxh erase resume xxxh b0h 30h erase suspend block erase start block erase command sequence program suspend / resume the program suspend command interrupts the program operation. also the program suspend command interrupts the program operation during erase suspend mode. the read operation is av ailable only during program sus pend. when the program suspend command is written during a program operation, the device requi res a maximum of 10us to suspend the program operation. the system may also write the autoselect command sequence when the device is in the program suspend mode. when the program resume command is executed, the program operation will resu me. when the program suspend or program resume command is executed, the addresses are in don't care state. we 555h 2aah 555h aah 55h 80h 555h block erase start dq15-dq0 2aah block address aah 55h 30h ry/by figure 6. block erase command sequence address
nor flash memory k8p5615uqa revision 1.1 july 2007 16 read while write the k8p5615uqa provides multi-bank memory architecture that di vides the memory array into four banks. the device is capable of reading data from one bank and writing data to the other bank simu ltaneously. this is so called the read while write operation with multi-bank architecture; this feature provides the capability of executing the read operation du ring program/erase or erase-sus pend- program operation. the read while write operation is prohibited du ring the chip erase operation. it is also allowed during eras e operation when either single block or mu ltiple blocks from same bank are loaded to be erased. it means that the read while writ e operation is prohibited when blo cks from one bank and another blocks from the other bank are loaded all together for the multi- block erase operation. write protect (wp ) the wp /acc pin has two useful functions. the one is that certain boot block is protecte d by the hardware method not to use v id . the other is that program operation is accelerated to reduce the program time (refer to accelerated program operation paragraph ). when the wp /acc pin is asserted at v il , the device can not perform program and erase operation in the two "outermost" 32 kword boot blocks on both ends of the flash array independently of whet her those blocks were protected or unprotected. (ba133, ba132, ba1 and ba0) the write protected blocks can only be read. this is useful method to preserve an important program data. when the wp /acc pin is asserted at v ih , the device reverts the two outermost 32kword boot blocks on both ends to default protec- tion state. note that the wp /acc pin must not be at vhh for operations other than accelerated programming, or device damage may result. software reset the reset command provides that the bank is reseted to read mode or erase-suspend-read mode. the addresses are in don't care state. the reset command is vaild between the sequence cycles in an erase command s equence before erasing begins, or in a pro- gram command sequence before programming begins. this resets the b ank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. also, the reset command is valid between the sequence cycles in an autoselect command sequence. in the autosel ect mode, the reset command returns the bank to read mode. if a bank entered the autoselect mode in the erase suspend mode, the reset command returns the bank to erase-suspend-read mode. if dq5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the erase suspend state. hardware reset the k8p5615uqa offers a reset feature by driving the reset pin to v il . when the reset pin is held low(v il ) for at least a period of t rp , the device immediatley terminat es any operation in progress, tristates all ou tputs, and ignores all read/write commands for duration of the reset pulse. the device also resets the internal state machine to asynchronous read mode. if a hardware reset occurs during a program operation, the data at that particular location will be lost. once the reset pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. also, note that all the data output pins are tri-stated for the duration of the reset pulse. the reset pin may be tied to the system reset pin. if a system reset occurs during the internal pro- gram and erase routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor t o read the boot-up firmware from the flash memory.
nor flash memory k8p5615uqa revision 1.1 july 2007 17 power-up protection to avoid initiation of a write cycle during vcc power-up, reset low must be asserted during power-up. after reset goes high, the device is reset to the read mode. low vcc write inhibit to avoid initiation of a write cycle duri ng vcc power-up and power-down, a write cycle is locked out for vcc less than 2.3v. if vcc < v lko (lock-out voltage), the command register and all internal program /erase circuits are disabled. under this condition the device will reset itself to the read mode. subsequent writes will be ignored until the vcc level is greater than v lko . it is the user s responsi- bility to ensure that the control pins are logically correct to prevent unint entional writes when vcc is above 2.3v. write pulse glitch protection noise pulses of less than 5ns(typical) on ce , oe , or we will not initiate a write cycle. logical inhibit writing is inhibited under any one of the following conditions : oe = v il , ce = v ih or we = v ih . to initiate a write, ce and we must be "0", while oe is "1". commom flash memory interface common flash momory interface is contrived to increase the compatibility of host system software. it provides the specific inf orma- tion of the device, such as memory size, word configuration, and electrical featur es. once this information has been obtained, the system software will know which command sets to use to enabl e flash writes, block erases, a nd control the flash component. when the system writes the cfi command(98h) to address 55h in wo rd mode, the device enters the cfi mode. and then if the sys- tem writes the address shown in table 8, the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in word(x16) mode, the upper data output s(dq8-15) is 00h. to terminate this operation, the system mu st write the reset command. otp block region the otp block feature provides a 256-word flash memory region that enables permanent pa rt identification through an electronic serial number (esn). the otp block is customer lockable and sh ipped with itself unlocked, allo wing customers to untilize the th at block in any manner they choose. indicator bits dq6 and dq7 are used to indicate the fa ctory-locked and customer locked status of the part. the data is dq6 = "1" for customer locked and dq7 = "1" for factory locked. the system accesses the otp block through a command sequenc e (see "enter otp block / exit otp block command sequence" at table 5). after the system has written the "enter otp bl ock" command sequence, it may read the otp block by using the addresses (000000h~0000ffh) normally and may check the protection veri fy bit (dq7,dq6) by using t he "autoselect indicator bit" command sequence with otp block address. this mode of operation continues until the system iss ues the "exit otp block" com- mand suquence, a hardware reset or until power is removed from t he device. on power-up, or following a hardware reset, the devi ce reverts to sending commands to main blocks. note that the ac celerated function and unlock bypa ss modes are not available when the otp block is enabled. ? after enter otp block command sequence is written, read while write operation are disabled until exiting this mode and any issu ed addresses should be in the range of otp block address. otp block protection in a customer lockable device, the otp block is one-time programmable and can be locked onl y once. locking operation to the otp block is started by writing the "e nter otp block lock register region" command sequence, and then the "otp block lock register bit program" command sqeunce (table 5) with data that ha ve zero(setting to 0) in dq0. note that the other dqs except dq0 will be ignored. the locking operation has to be above 100us. after that timing, "exi t otp block lock register region" com- mand sequence or hardware reset must be issued in order to exit otp block mode and revert the device to read mode in main array. ? the otp block lock operation must be used with caution since, once locked, there is no procedure available for unlocking and n one of the bits in the otp block space can be modified in any way. ? suspend and resume operation are not supported during otp protec t, nor is otp protect supported during any suspend operation. ? after enter otp block lock register region command sequence is written, read while write operation are disabled until exiting t his mode.
nor flash memory k8p5615uqa revision 1.1 july 2007 18 table 8. common flash memory interface code description addresses (word mode) data query unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h primary oem command set 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 0000h 0000h address for alternate oem ex tended table (00h = none exists) 19h 1ah 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 0027h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0031h vpp min. voltage(00h = no vpp pin present) 1dh 0000h vpp max. voltage(00h = no vpp pin present) 1eh 0000h typical timeout per single word write 2 n us 1fh 0006h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 0009h typical timeout per individual block erase 2 n ms 21h 000bh typical timeout for full chip erase 2 n ms(00h = not supported) 22h 00cch max. timeout for word write 2 n times typical 23h 0003h max. timeout for buffer write 2 n times typical 24h 0003h max. timeout per individual block erase 2 n times typical 25h 0002h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 0002h device size = 2 n byte 27h 0019h flash device interface description 28h 29h 0001h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0006h 0000h number of erase block r egions within device 2ch 0003h erase block region 1 information 2dh 2eh 2fh 30h 0003h 0000h 0000h 0001h erase block region 2 information 31h 32h 33h 34h 007dh 0000h 0000h 0004h erase block region 3 information 35h 36h 37h 38h 0003h 0000h 0000h 0001h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h
nor flash memory k8p5615uqa revision 1.1 july 2007 19 table 8. common flash memory interface code description addresses (word mode) data query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0030h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 0002h block protect 00 = not supported, 01 = supported 47h 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 0000h block protect/unprotect scheme, 00 = not supported, 01 = supported 49h 0001h simultaneous operation 00 = not supported, xx = number of blocks except bank 0 4ah 0073h burst mode type 00 = not supported, 01 = supported 4bh 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4ch 0002h acc(acceleration) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4dh 0085h acc(acceleration) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4eh 0095h top/bottom boot block flag 00h = no boot, 01h = dual boot device 02h = bottom boot device, 03h = top boot device 4fh 0001h
nor flash memory k8p5615uqa revision 1.1 july 2007 20 device status flags the k8p5615uqa has means to indicate its status of operation in the bank where a program or erase operation is in processes. address must include bank address being excuted internal routine operation. the status is indicated by raising the device statu s flag via corresponding dq pins or the ry/ by pin. the corresponding dq pins are dq7, dq6, dq5, dq3 and dq2. the statuses are as follows : table 9. hardware sequence flags notes : 1. dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. 3. note that dq7 during write-to-buffer-programming indicates the data-bar for dq7 for the last loaded write-buffer address location. status dq7 dq6 dq5 dq3 dq2 dq1 in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1100 to g g l e (note 1) 0 erase suspend read non-erase sus- pended block data data data data data data erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 0 program suspend read program sus- pended block dq7100 to g g l e (note 1) 0 program suspend read non-program sus- pended block data data data data data data exceeded time limits programming dq7 toggle 1 0 no to g g l e 0 block erase or chip erase 0 toggle 1 1 (note 2) 0 erase suspend program dq7 toggle 1 0 no toggle 0 write to buffer (note 3) busy state dq7 toggle 0 0 no toggle 0 exceeded timing limits dq7 toggle 1 0 no toggle 0 abort state dq7 toggle 0 0 no toggle 1 dq7 : data polling when an attempt to read the device is made while executing the in ternal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is co mpleted an attempt to access to the device will produce the tru e data written to dq7. when a user attempts to read the block being er ased, dq7 will be low. if the dev ice is placed in the erase/prog ram suspend mode, the status can be detected via the dq7 pin. if the system tries to read an address which belongs to a block that is being erase suspended, dq7 will be high. and, if the system tries to read an address which belongs to a block that is being pro gram suspended, the output will be the true data of dq7 itself. if a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement dat a in approximately 100us and the device then returns to the read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop after the device completes its internal routine. if the device is in the erase/program suspend mode, an attempt to read an address that belongs to a block that is being erased or programmed w ill produce a high output of dq 6. if an address belongs to a block that is not being erased or progr ammed, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected bl ock, dq6 toggles for approxim ately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing the data in the block.
nor flash memory k8p5615uqa revision 1.1 july 2007 21 ry/by : ready/busy the k8p5615uqa has a ready / busy output that indicates either the completion of an operation or the status of internal algorithms. if the output is low, the device is busy wi th either a program or an erase operation. if the output is high, the device is read y to accept any read/write or erase operation. when the ry/ by pin is low, the device will not acce pt any additional program or erase commands with the exception of the erase suspend command. if the k8 p5615uqa is placed in an erase suspend mode, the ry/ by output will be high. for programming, the ry/ by is valid (ry/ by = 0) after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, ry/ by is also valid after the rising edge of we pulse in the six write pul se sequence. for block erase, ry/ by is also valid after the rising edge of the sixth we pulse. the pin is an open drain output, allowing two or more ready/ busy outputs to be or-tied. an appropriate pull-up resistor is required for proper operation. rp = v cc ready / busy open drain output device gnd vcc (max.) - v ol (max.) i ol + i l = 3.5 v 2.1ma + i l where i l is the sum of the input currents of all devices tied to the ready / busy pin. rp dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time win- dow expires. in this case, the internal erase routine will init iate the erase operation.therefore, the device will not accept f urther write commands until the erase operation is complete d. dq3 is low if the block erase time wi ndow is not expired. within the block era se time window, an additional block erase comm and (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq 2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase routine, dq2 toggles onl y if an erasing bank is read. although the internal erase routin e is in the exceeded time limits, dq2 toggles on ly if an erasing block in the exceeded time limits is read. when the device is in th e erase/program suspend mode, dq2 toggles only if an address in t he erasing or programming block is read. if a non-erasing or non - programmed block address is read during the erase/program suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend blo ck while the device is in the erase suspend mode. dq1 : buffer program abort indicator dq1 indicates whether a write-to-buffer operation was aborted. u nder these conditions dq1 produces a "1". the system must issue the write-to-buffer-abort-reset command sequence to return the device to reading array data.
nor flash memory k8p5615uqa revision 1.1 july 2007 22 start dq7 = data ? no dq5 = 1 ? fail pass yes figure 8. data polling algorithms dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address yes figure 9. toggle bit algorithms start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes read(dq0~dq7) valid address
nor flash memory k8p5615uqa revision 1.1 july 2007 23 dc characteristics recommended operating conditions ( voltage reference to gnd ) parameter symbol min typ. max unit supply voltage v cc 2.7 3.0 3. 6 v supply voltage v ss 000v absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during tr ansitions, this level may fall to -2.0v for periods <20ns. maxim um dc voltage on input / output pins is vcc+0.5v which, during tr ansitions, may overshoot to vcc+2.0v for periods <20ns. 2. minimum dc voltage is -0.5v on wp /acc pins. during transitions, this level ma y fall to -2.0v for periods <20ns. maximum dc voltage on wp /acc pins is 9.5v which, during transition s, may overshoot to 10.5v for periods <20ns. 3. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +4.0 v wp /acc v in -0.5 to +9.5 all other pins -0.5 to vcc+0.5 temperature under bias commercial t bias -10 to +125 c extended -25 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma operating temperature t a (industrial temp.) -40 to +85 c t a (extended temp.) -25 to + 85 c parameter sym- bol test conditions min typ max uni t input leakage current i li v in =v ss to v cc , v cc =v ccmax ? 1.0 - + 1.0 a wp /acc input leakage current i liw v cc =v ccmax , wp /acc=9.5v - - 35 a output leakage current i lo v out =v ss to v cc ,v cc =v ccmax ,oe =v ih ? 1.0 - + 1.0 a active read current (1) i cc 1oe =v ih , v cc =v ccmax 5mhz - 30 45 ma active write current (2) i cc 2ce =v il , oe =v ih, we =v il -2550ma read while program current (3) i cc 3ce =v il , oe =v ih (@5mhz) -3550ma read while erase current (3) i cc 4ce =v il , oe =v ih (@10mhz) -3550ma program while erase suspend current i cc 5ce =v il , oe =v ih -2755ma page read current i cc 6 oe =vih, 8-word page read 40mhz - 10 15 ma acc accelerated program current i acc ce =v il , oe =v ih -1530ma standby current i sb 1 ce , reset , wp /acc= v cc 0.3 -2060 a standby current during reset i sb 2 reset = vss 0.3 -2060 a automatic sleep mode i sb 3 v ih =vcc 0.3v, v il =v ss 0.2v -2060 a input low level v il vcc=2.7~3. 6 v -0.5 - vcc x 0.2 v input high level v ih vcc=2.7~3. 6 v vcc x 0.8 - vcc+0.3 v voltage for wp /acc block tempo- rarily unprotect and program acceler- ation (4) v hh vcc = 2.7~3. 6 v 8.5 - 9.5 v
nor flash memory k8p5615uqa revision 1.1 july 2007 24 ac test condition parameter value input pulse levels 0v to vcc input rise and fall times(vio=1.8,3.0v) 5ns input and output timing levels vcc/2 output load c l = 30pf 0v vcc vcc/2 vcc/2 input pulse and test point input & output test point notes : 1. the i cc current listed includes both the dc operating current and the frequency dependent component(at 5 mhz). 2. i cc active during internal routine(program or erase) is in progress. 3. i cc active during read while write is in progress. 4. the high voltage (v hh ) must be used in the range of vcc = 2.7v ~ 3. 6 v 5. not 100% tested. capacitance (t a = 25 c, v cc = 3.0v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 10 pf output capacitance c out v out =0v - 10 pf control pin capacitance c in2 v in =0v - 10 pf parameter symbol test conditions min typ max unit output low level v ol iol =100ua,vcc=vccmin - - 0.1 v output high level v oh ioh = -100ua, vcc=vccmin vcc - 0.2 - - v low vcc lock-out voltage (5) v lko 2.3 - 2.5 v output load * cl= 30pf including scope c l device and jig capacitance ac characteristics read operations note : 1. not 100% tested. parameter symbol v cc = 2.7v~3. 6 v unit 4d min max read cycle time (1) t rc 70 - ns address access time t aa -70ns chip enable access time t ce -70ns output enable time t oe -30ns page address access time t pa -30ns ce & oe disable time (1) t df -16ns output hold time from address, ce or oe (1) t oh 5-ns
nor flash memory k8p5615uqa revision 1.1 july 2007 25 conventional read operations switching waveforms oe address t ce t oeh ce outputs we high-z output valid t rc address stable t aa t oe t oh high-z t df ry/by high figure 10. conventional read operation timings ce a3 to a23 a0 to a2 output oe t rc same page addresses we aa ab t prc t aa t ce t oe t oeh t pa t oh t df high-z page read operations figure 11. page read operation timings da db dc dd de df dg dh t pa t oh ac ad ae af ag ah t oh
nor flash memory k8p5615uqa revision 1.1 july 2007 26 hardware reset/read operations switching waveforms reset address ce outputs high-z t rc address stable t aa t ce t oh t rh t rh t rp output valid parameter symbol 4d unit min max read cycle time t rc 70 - ns address access time t aa -70ns chip enable access time t ce -70ns output hold time from address, ce or oe t oh 5-ns reset pulse width t rp 30 - s reset high time before read t rh 200 - ns figure 12. hardware reset/read operation timings
nor flash memory k8p5615uqa revision 1.1 july 2007 27 notes : 1. not 100% tested. 2. the duration of the program or erase operation va ries and is calculated in the internal algorithms. parameter symbol v cc = 2.7v ~ 3. 6 v unit 4d min max write cycle time (1) t wc 70 - ns address setup time t as 0-ns address hold time t ah 35 - ns t aht 0-ns data setup time t ds 30 - ns data hold time t dh 0-ns output enable setup time (1) t oes 0-ns output enable hold read (1) t oeh1 0-ns toggle and data polling (1) t oeh2 10 - ns ce setup time t cs 0-ns ce hold time t ch 0-ns write pulse width t wp 40 - ns write pulse width high t wph 25 - ns programming operation (2) t pgm 40(typ.) s accelerated programming operation (2) t accpgm 24(typ.) s sector erase operation (2) t bers 1.6(typ) sec v cc set up time t vcs 250 - s v hh set up time t vhh 250 ns write recovery time from ry/ by t rb 0-ns program/erase valid to ry/by delay t busy -90ns read recovery time before write t ghwl 0-ns ce high during toggling bit polling t ceph 20 - ns oe high during toggling bit polling t oeph 10 - ns ac characteristics write(erase/program)operations
nor flash memory k8p5615uqa revision 1.1 july 2007 28 erase and program performance notes : 1. 25 c, v cc = 3.0v 100,000 cycles, typical pattern . 2. system-level overhead is defined as the time required to execute the four bus cycle command necessary to program each word . in the preprogramming step of the internal erase routine, all words are programmed to 00h before erasure. parameter condition limits unit comments min typ max block erase time 128 kword v cc -1.67 sec excludes 00h programming prior to erasure acc 1.6 7 32 kword v cc 0.5 4 acc - 0.5 4 chip erase time v cc - 206 900 sec acc 130 512 word programming time v cc - 40 400 s excludes system-level overhead acc 24 240 word programming time with 32-words buffer v cc -9.494 s acc 6 60 total 32-words buffer program- ming time v cc - 300 3000 s excludes system-level overhead acc 192 1920 chip programming time with 32-word buffer v cc - 157.3 315 sec excludes system-level overhead acc 100 200 erase/program endurance 100,000 - - cycles minimum 100,000 cycles guaran- teed
nor flash memory k8p5615uqa revision 1.1 july 2007 29 program operations switching waveforms notes : 1. dq7 is the output of the complement of the data written to the device. 2. d out is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address t cs ce data we t ah t oh t df t as t rc t oe t ce t ds t dh t wp t oes t pgm status dout 555h pa pa a0h data polling t ch pd t wph ry/by t busy t rb t wc figure 13. program operation timings wp /acc t vhh v il or v ih v hh t vhh v il or v ih figure 14. accelerated program timings
nor flash memory k8p5615uqa revision 1.1 july 2007 30 switching waveforms chip/block erase operations oe address t cs ce data we t ah t as t rc t ds t dh 80h aah aah 55h 30h 10h for chip erase 555h 2aah 555h 555h 2aah ba 555h for chip erase t wph t wp t oes 55h ry/by t wc t vcs vcc note : ba : block address figure 15. chip/block erase operation timings read while write operations note : this is an example in the program-case of the read while write function. da1 : address of bank1, da2 : address of b ank 2, pa = program address at one bank , ra = read address at the oth er bank, pd = program data in , rd = read data out oe ce dq we t rc read command command read read read t ah t aa t ce t as t as t oe t oes t wp t oeh t df t ds t dh t df da1 da2 da1 da1 da2 da2 (555h) (pa) (pa) valid output valid output valid input valid output valid input status address (a0h) (pd) t rc t rc t rc t wc t wc figure 16. read while write operation timings t ceph
nor flash memory k8p5615uqa revision 1.1 july 2007 31 oe data polling during internal routine operation t ce t oeh ce dq7 we switching waveforms t oe high-z t df note : *dq7=vaild data (the device has completed the internal operation). dq7 *dq7 = valid data t oh t pgm or t bers parameter symbol 4d unit min max program/erase valid to ry/by delay t busy -90ns chip enable access time t ce -70ns output enable time t oe -20ns ce & oe disable time t df -16ns output hold time from address, ce or oe t oh 5-ns oe hold time t oeh 10 - ns high-z valid data dq0-dq6 data in data in we ry/by timing diagram during program/erase operation the rising edge of the last we signal ce ry/by t busy entire progrming or erase operation status data figure 17. data polling during internal routine operation timings figure 18. ry/by timing diagram during program/erase operation timings
nor flash memory k8p5615uqa revision 1.1 july 2007 32 t dh toggle bit during intern al routine operation switching waveforms ce address* oe dq6/dq2 we ry/by data in t aht t aht t aa t as t ceph t oeh t oeph status data t o e status data status data array data out note : address for the write operation must include a bank address (a19~a22) where the data is written. dq 6 we dq 2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase resume erase erase suspend read erase erase complete erase suspend read note : dq2 is read from the erase-suspended block. toggle dq 2 and dq 6 with oe or ce figure 19. toggle bit during internal routine operation timings
nor flash memory k8p5615uqa revision 1.1 july 2007 33 reset timing diagram switching waveforms power-up and reset timing diagram parameter sym- bol 4d unit min max reset pulse width t rp 30 - s reset high time before read t rh 200 - ns reset low set-up time t rsts 250 - s reset ce or oe t rh t rp reset t aa vcc address data t rsts figure 20. power-up and reset timing diagram
nor flash memory k8p5615uqa revision 1.1 july 2007 34 switching waveforms figure 22. unlock bypass operation timings ce oe address wp /acc we dq0-dq15 1us t vps v il or v ih v hh t vhh pa don?t care a0h pd don?t care ce oe address wp /acc we dq0-dq15 1us t vps v il or v ih v hh t vhh ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase unlock bypass program operations(accelerated program) unlock bypass block erase operations(accelerated program) notes: 1. v hh can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operations. 3. unlock bypass program/erase commands can be used when the v hh is applied to wp /acc don?t care don?t care
nor flash memory k8p5615uqa revision 1.1 july 2007 35 table 10. block architecture (k8p5615uqa) bank block block size (x16) address range bank 3 ba133 32 kwords ff8000h-ffffffh ba132 32 kwords ff0000h-ff7fffh ba131 32 kwords fe8000h-feffffh ba130 32 kwords fe0000h-fe7fffh ba129 128 kwords fc0000h-fdffffh ba128 128 kwords fa0000h-fbffffh ba127 128 kwords f80000h-f9ffffh ba126 128 kwords f60000h-f7ffffh ba125 128 kwords f40000h-f5ffffh ba124 128 kwords f20000h-f3ffffh ba123 128 kwords f00000h-f1ffffh ba122 128 kwords ee0000h-efffffh ba121 128 kwords ec0000h-edffffh ba120 128 kwords ea0000h-ebffffh ba119 128 kwords e80000h-e9ffffh ba118 128 kwords e60000h-e7ffffh ba117 128 kwords e40000h-e5ffffh ba116 128 kwords e20000h-e3ffffh ba115 128 kwords e00000h-e1ffffh bank 2 ba114 128 kwords de0000h-dfffffh ba113 128 kwords dc0000h-ddffffh ba112 128 kwords da0000h-dbffffh ba111 128 kwords d80000h-d9ffffh ba110 128 kwords d60000h-d7ffffh ba109 128 kwords d40000h-d5ffffh ba108 128 kwords d20000h-d3ffffh ba107 128 kwords d00000h-d1ffffh ba106 128 kwords ce0000h-cfffffh ba105 128 kwords cc0000h-cdffffh ba104 128 kwords ca0000h-cbffffh ba103 128 kwords c80000h-c9ffffh ba102 128 kwords c60000h-c7ffffh ba101 128 kwords c40000h-c5ffffh ba100 128 kwords c20000h-c3ffffh ba99 128 kwords c00000h-c1ffffh ba98 128 kwords be0000h-bfffffh ba97 128 kwords bc0000h-bdffffh ba96 128 kwords ba0000h-bbffffh ba95 128 kwords b80000h-b9ffffh ba94 128 kwords b60000h-b7ffffh ba93 128 kwords b40000h-b5ffffh ba92 128 kwords b20000h-b3ffffh
nor flash memory k8p5615uqa revision 1.1 july 2007 36 table 10. block architecture (k8p5615uqa) bank block block size (x16) address range bank 2 ba91 128 kwords b00000h-b1ffffh ba90 128 kwords ae0000h-afffffh ba89 128 kwords ac0000h-adffffh ba88 128 kwords aa0000h-abffffh ba87 128 kwords a80000h-a9ffffh ba86 128 kwords a60000h-a7ffffh ba85 128 kwords a40000h-a5ffffh ba84 128 kwords a20000h-a3ffffh ba83 128 kwords a00000h-a1ffffh ba82 128 kwords 9e0000h-9fffffh ba81 128 kwords 9c0000h-9dffffh ba80 128 kwords 9a0000h-9bffffh ba79 128 kwords 980000h-99ffffh ba78 128 kwords 960000h-97ffffh ba77 128 kwords 940000h-95ffffh ba76 128 kwords 920000h-93ffffh ba75 128 kwords 900000h-91ffffh ba74 128 kwords 8e0000h-8fffffh ba73 128 kwords 8c0000h-8dffffh ba72 128 kwords 8a0000h-8bffffh ba71 128 kwords 880000h-89ffffh ba70 128 kwords 860000h-87ffffh ba69 128 kwords 840000h-85ffffh ba68 128 kwords 820000h-83ffffh ba67 128 kwords 800000h-81ffffh bank 1 ba66 128 kwords 7e0000h-7fffffh ba65 128 kwords 7c0000h-7dffffh ba64 128 kwords 7a0000h-7bffffh ba63 128 kwords 780000h-79ffffh ba62 128 kwords 760000h-77ffffh ba61 128 kwords 740000h-75ffffh ba60 128 kwords 720000h-73ffffh ba59 128 kwords 700000h-71ffffh ba58 128 kwords 6e0000h-6fffffh ba57 128 kwords 6c0000h-6dffffh ba56 128 kwords 6a0000h-6bffffh ba55 128 kwords 680000h-69ffffh ba54 128 kwords 660000h-67ffffh ba53 128 kwords 640000h-65ffffh ba52 128 kwords 620000h-63ffffh ba51 128 kwords 600000h-61ffffh ba50 128 kwords 5e0000h-5fffffh ba49 128 kwords 5c0000h-5dffffh ba48 128 kwords 5a0000h-5bffffh ba47 128 kwords 580000h-59ffffh
nor flash memory k8p5615uqa revision 1.1 july 2007 37 table 10. block architecture (k8p5615uqa) bank block block size (x16) address range bank 1 ba46 128 kwords 560000h-57ffffh ba45 128 kwords 540000h-55ffffh ba44 128 kwords 520000h-53ffffh ba43 128 kwords 500000h-51ffffh ba42 128 kwords 4e0000h-4fffffh ba41 128 kwords 4c0000h-4dffffh ba40 128 kwords 4a0000h-4bffffh ba39 128 kwords 480000h-49ffffh ba38 128 kwords 460000h-47ffffh ba37 128 kwords 440000h-45ffffh ba36 128 kwords 420000h-43ffffh ba35 128 kwords 400000h-41ffffh ba34 128 kwords 3e0000h-3fffffh ba33 128 kwords 3c0000h-3dffffh ba32 128 kwords 3a0000h-3bffffh ba31 128 kwords 380000h-39ffffh ba30 128 kwords 360000h-37ffffh ba29 128 kwords 340000h-35ffffh ba28 128 kwords 320000h-33ffffh ba27 128 kwords 300000h-31ffffh ba26 128 kwords 2e0000h-2fffffh ba25 128 kwords 2c0000h-2dffffh ba24 128 kwords 2a0000h-2bffffh ba23 128 kwords 280000h-29ffffh ba22 128 kwords 260000h-27ffffh ba21 128 kwords 240000h-25ffffh ba20 128 kwords 220000h-23ffffh ba19 128 kwords 200000h-21ffffh bank 0 ba18 128 kwords 1e0000h-1fffffh ba17 128 kwords 1c0000h-1dffffh ba16 128 kwords 1a0000h-1bffffh ba15 128 kwords 180000h-19ffffh ba14 128 kwords 160000h-17ffffh ba13 128 kwords 140000h-15ffffh ba12 128 kwords 120000h-13ffffh ba11 128 kwords 100000h-11ffffh ba10 128 kwords 0e0000h-0fffffh ba9 128 kwords 0c0000h-0dffffh ba8 128 kwords 0a0000h-0bffffh ba7 128 kwords 080000h-09ffffh ba6 128 kwords 060000h-07ffffh ba5 128 kwords 040000h-05ffffh ba4 128 kwords 020000h-03ffffh ba3 32 kwords 018000h-01ffffh ba2 32 kwords 010000h-017fffh ba1 32 kwords 008000h-00ffffh ba0 32 kwords 000000h-007fffh
nor flash memory k8p5615uqa revision 1.1 july 2007 38 package dimensions 56-pin lead plastic thin sm all out-line package type 56 - tsop unit :mm/inch 18.40 0.10 #28 0.20 +0.07 -0.03 0.50typ [0.50 0.06] #56 #29 14.00 0.10 0.10 max 1.00 0.05 0.05 min 1.20 max (18.80) 0.4375 0.05 0.125 +0.075 -0.035 0.45~0.75 0 ~8 0.25 typ (0.50) ( r 0 .2 5 ) ( r 0 . 2 5 ) (1.00) (1.00) (2- 1.20 dp 0 ~0.05) 0.16 +0.03 -0.01 (13 ) (10 ) 0.4375 0.05 ( f 0 . 1 5 ) ( r 0 . 1 5 ) (19.00) 20.00 0.20 ( 1 3 ) ( 1 0 ) ( r 0 . 1 5 ) ( r 0 . 1 5 ) 0.075 max [ [ note ( ) is reference. [ ] is assambly out quality .

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