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47 48 49 50 51 52 33 32 31 29 30 28 27 26 25 24 23 22 21 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 10 9 8 34 35 36 37 38 39 40 41 42 43 44 45 46 1 a package (52-pin plcc) i 11 i 12 i 10 i 13 i 14 i 15 i 16 i 17 i 9 i 8 i 7 i 6 i 5 v cc i 4 i 3 i 2 i 1 i 0 b 3 b 2 b 1 b 0 x 7 x 6 gnd gnd x 5 x 4 x 3 x 2 x 1 x 0 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 b 7 b 6 b 5 b 4 i 23 i 22 i 21 i 20 i 19 i 18 v cc philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? 1 october 22, 1993 8531207 11164 features ? programmable macro logic device ? full connectivity ? ttl compatible ? snap development system: supports third-party schematic entry formats macro library versatile netlist format for design portability logic, timing, and fault simulation ? delay per internal nand function = 6.5ns (typ) ? t estable in unprogrammed state ? security fuse allows protection of proprietary designs structure ? nand gate based architecture 72 foldback nand terms ? 136 input-wide logic terms ? 44 additional logic terms ? 24 dedicated inputs (i 0 i 23 ) ? 8 bidirectional i/os with individual 3-state enable: 4 active-high (b 4 b 7 ) 4 active-low (b 0 b 3 ) ? 16 dedicated outputs: 4 active-high outputs o 0 , o 1 with common 3-state enable o 2 , o 3 with common 3-state enable 4 active-low outputs: o 4 , o 5 with common 3-state enable o 6 , o 7 with common 3-state enable 8 exclusive-or outputs: x 0 , x 1 with common 3-state enable x 2 , x 3 with common 3-state enable x 4 , x 5 with common 3-state enable x 6 , x 7 with common 3-state enable pin configuration description the plhs501 is a high-density bipolar programmable macro logic device. pml incorporates a programmable nand structure. the nand architecture is an ef ficient method for implementing any logic function. the snap software development system provides a user friendly environment for design entry. snap eliminates the need for a detailed understanding of the plhs501 architecture and makes it transparent to the user. plhs501 is also supported on the philips semiconductors snap software development systems. the plhs501 is ideal for a wide range of microprocessor support functions, including bus interface and control applications. the plhs501 is also processed to industrial requirements for operation over an extended temperature range of 40 c to +85 c and supply voltage of 4.5v to 5.5v. architecture the core of the plhs501 is a programmable fuse array of 72 nand gates. the output of each gate folds back upon itself and all other nand gates. in this manner, full connectivity of all logic functions is achieved in the plhs501. any logic function can be created within the core of the device without wasting valuable i/o pins. furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the i/o buffers. pml is a trademark of philips semiconductors
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 2 ordering information description operating conditions order code drawing number 52-pin plastic leaded chip carrier commercial temperature range 5% power supply plhs501a 0397e 52-pin plastic leaded chip carrier industrial temperature range 10% power supply plhs501 i a 0397e design development tools snap the snap software development system provides the necessary tools for designing with pml. snap provides the following: ? schematic entry netlist generation from third-party schematic design packages such as orcad/sdt iii ? and futurenet ? . ? macro library for standard ttl functions and user defined functions ? boolean equation entry ? state equation entry ? syntax and design entry checking ? simulator includes logic simulation, fault simulation and timing simulation. snap operates on an ibm ? pc/xt, pc/at, ps/2, or any compatible system with dos 2.1 or higher. the minimum system configuration for snap is 640k bytes of ram and a hard disk. snap provides primitive pml function libraries for third-party schematic design packages. custom macro function libraries can be defined in schematic or equation form. after the completion of a design, the software compiles the design for syntax and completeness. complete simulation can be carried out using the different simulation tools available. the programming data is generated in jedec format. using the device programmer interface (dpi) module of snap , the jedec fusemap is sent from the host computer to the device programmer . design security the plhs501 has a programmable security fuse that controls the access to the data programmed in the device. by using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. programming/software support refer to section 9 (development software) and section 10 (third-party programmer/ software support) of this data handbook for additional information. futurenet is a trademark of futurenet corporation. orcad/sdt is a trademark of orcad, inc. ibm is a registered trademark of international business machines corporation.
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 3 plhs501 functional block diagram i n t e r c o n n e c t 24 dedicated inputs nand array 16 dedicated outputs 8 bidirectional i/os
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 4 functional diagram i 0 i 23 71 0 x4 x4 x4 x2 x2 b 0 b 3 b 4 b 7 x 0 , x 2 , x 4 , x 6 x 1 , x 3 , x 5 , x 7 o 0 , o 2 o 1 , o 3 o 4 , o 6 o 5 , o 7 x4 x2 x2 x4 x4 x4 x4 x4 x4 x4 x2 x2 x2 x2 x2 x2 x4 detail a
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 5 detail a 40 39 38 37 15 16 17 18 28 29 30 31 32 33 35 36 19 21 22 23 24 25 26 27 b 3 b 2 b 0 b 1 b 4 b 5 b 7 b 6 x 0 x 1 x 2 x 3 x 4 x 5 x 7 x 6 o 0 o 1 o 2 o 3 o 4 o 5 o 7 o 6
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 6 absolute maximum ratings 1 ratings symbol parameter min max unit v cc supply voltage +7 v dc v in input voltage +5.5 v dc v out output voltage +5.5 v dc i in input currents 30 +30 ma i out output currents +100 ma t amb operating temperature range 0 +75 c t stg storage temperature range 65 +150 c note: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only . functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. thermal ratings temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise ambient to junction 75 c virgin state a factory shipped virgin device contains all fusible links open, such that: 1. all product terms are enabled. 2. all bidirectional (b) pins are outputs. 3. all outputs are enabled. 4. all outputs are active-high except b 0 b 3 (fusible i/o) and o 4 o 7 which are active-low.
+5v c l r 1 r 2 s 1 gnd b z b y inputs i 0 i 10 b w b x outputs c 2 c 1 dut note: c 1 and c 2 are to bypass v cc to gnd. v cc o x philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 7 dc electrical characteristics commercial= 0 c t amb +75 c, 4.75v v cc 5.25v industrial = 40 c t amb +85 c, 4.5v v cc 5.5v limits symbol parameter test condition min typ 1 max unit input voltage 2 v il low v cc = min 0.8 v v ih high v cc = max 2.0 v v ic clamp 2, 3 v cc = min, i in = 12ma 0.8 1.2 v output voltage v cc = min v ol low 2, 4 i ol = 10ma 0.45 v v oh high 2, 5 i oh = 2ma 2.4 v input current v cc = max i il low v in = 0.45v 100 m a i ih high v in = 5.5v 40 m a output current v cc = max i o(off) hi-z state 9 v out = 5.5v 80 m a v out = 0.45v 140 i os short circuit 3, 5, 6 v out = 0v 15 70 ma i cc v cc supply current 8 v cc = max 225 295 ma capacitance v cc = 5v c in input v in = 2.0v 8 pf c b i/o v out = 2.0v 15 pf notes: 1. all typical values are at v cc = 5v, t amb = +25 c. 2. all voltage values are with respect to network ground terminal. 3. test one at a time. 4. for pins 15 19, 21 27 and 37 40, v ol is measured with pins 5 and 41 = 8,75v , pin 43 = 0v and pins 42 and 44 = 4.5v . for pins 28 33 and 35 36, v ol is measured under same conditions except pin 44 = 0v . 5. v oh is measured with pins 5 and 41 = 8.75v , pins 42 and 43 = 4.5v and pin 44 = 0v . 6. duration of short circuit should not exceed 1 second. 7. i cc is measured with all dedicated inputs at 0v and bidirectional and output pins open. 8. measured at v t = v ol + 0.5v. 9. leakage values are a combination of input and output leakage. test load circuits voltage waveforms measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses 90% 10% 2.5ns 90% 10% +3.0v +3.0v 0v 0v t r t f 2.5ns 2.5ns 2.5ns
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 8 snap resource summary designations i 0 i 23 71 0 x4 x4 x4 x2 x2 b 0 b 3 b 4 b 7 x 0 , x 2 , x 4 , x 6 x 1 , x 3 , x 5 , x 7 o 0 , o 2 o 1 , o 3 o 4 , o 6 o 5 , o 7 x4 x2 x2 x4 x4 x4 x4 x4 x4 x4 x2 x2 x2 x2 x2 x2 x4 din501 nin501 fbnand nand out501 nou501 exo501 nou501 tou501
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 9 macro cell specifications 1 (snap resource summary designations in parantheses) commercial:t amb = 0 c to +75 c, 4.75v v cc 5.25v, c l = 30pf, r 2 = 1000 w , r 1 = 470 w industrial: t amb = 40 c to +85 c, 4.5v v cc 5.5v, c l = 30pf, r 2 = 1000 w , r 1 = 470 w input buffer (din501 [non-inverting], nin501 [inverting]) i x y limits symbol min typ max unit d t hl 0.05 0.1 0.15 ns/p-term d t lh 0.02 0.05 0.08 ns/p-term parameter limits symbol to (output) from (input) min typ max unit notes t phl t plh x x i i 4.5 5 5.5 6 6.5 7.5 ns ns with 0 p-terms load t phl t plh y y i i 2.5 4 3 4 3.5 4.5 ns ns with 0 p-terms load input pins: 1 7, 9 14, 41 45, 48 52. bidirectional pins: 15 18, 37 40. maximum internal fan-out: 16 p-terms on x or y . nand output buffer with 3-state control (tou501) trictrl in out parameter limits symbol to (output) from (input) min typ max unit t phl t plh out out in in 8.5 8.5 14.0 14.0 17.5 16 ns ns t oe 2 t od 2 out out tri-ctrl tri-ctrl 8.5 8.5 15 12.5 18.5 17.0 ns ns output pins: 24 27. internal foldback nand (fbnand) output input limits symbol min typ max unit d t phl 0.05 0.1 0.15 ns/p-term d t plh 0.0 0.05 0.1 ns/p-term parameter limits symbol to (output) from (input) min typ max unit notes t phl t plh out any 4.0 5.5 4.5 6.5 6.8 8 ns ns with 0 p-terms load maximum internal loading of 16 terms. notes are on following page.
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 10 macro cell specifications 1 (continued) (snap resource summary designations in parantheses) commercial:t amb = 0 c to +75 c, 4.75v v cc 5.25v, c l = 30pf, r 2 = 1000 w , r 1 = 470 w industrial: t amb = 40 c to +85 c, 4.5v v cc 5.5v, c l = 30pf, r 2 = 1000 w , r 1 = 470 w and output buffer with 3-state control (nou501) trictrl in out parameter limits symbol to (output) from (input) min typ max unit t phl t plh output output in in 8.0 8.0 11 11 13 13 ns ns t oe 2 t od 2 out out tri-ctrl tri-ctrl 8.5 8.5 15 12.5 18.5 17.0 ns ns bidirectional and output pins: 19, 21, 22, 23, 15 18. nand output buffer (out501) in out parameter limits symbol to (output) from (input) min typ max unit t phl t plh out out in in 8.5 8.5 14 14 17.5 16.0 ns ns bidirectional pins: 37 40. exor output buffer (exo501) out a b trictrl parameter limits symbol to (output) from (input) min typ max unit t phl t plh out out a or b a or b 8.5 8.5 14 14 17.5 16.0 ns ns t oe 2 t od 2 out out tri-ctrl tri-ctrl 8.5 8.5 15 12.5 18.5 17.0 ns ns ex-or output pins: 28 33. notes: 1. limits are guaranteed with internal feedback buf fers simultaneously switching cumulative maximum of eight outputs. 2. for 3-state output; output enable times are tested with c l = 30pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf . high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed.
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 11 plhs501 gate and speed estimate table function internal nand equvalent typical t pd f max comments gates nands 1 6.5ns for 1 to 32 input variables ands 1 6.5ns for 1 to 32 input variables nors 1 6.5ns for 1 to 32 input variables ors 1 6.5ns for 1 to 32 input variables decoders 3-to-8 8 11ns inverted inputs available 4-to-16 16 11ns inverted inputs available 5-to-32 32 11ns inverted inputs available (24 chip outputs only) encoders 8-to-3 15 11ns inverted inputs, 2 logic levels 16-to-4 32 11ns inverted inputs, 2 logic levels 32-to-5 41 11ns inverted inputs, 2 logic levels, factored solution. multiplexers 4-to-1 5 11ns inverted inputs available 8-to-1 9 11ns 16-to-1 17 11ns 27-to-1 28 11ns can address only 27 external inputs - more if internal flip-flops d-type flip-flop 6 30mhz with asynchronous s-r t-type flip-flop 6 30mhz with asynchronous s-r j-k-type flip-flop 10 30mhz with asynchronous s-r adders 8-bit 45 15.5ns full carry-lookahead (four levels of logic) barrel shifters 8-bit 72 11ns 2 levels of logic latches d-latch 3 2 levels of logic with one shared gate
philips semiconductors programmable logic devices product specification plhs501/plhs501 i programmable macro logic pml ? october 22, 1993 12 applications master slave module specific module specific bus control plhs501 clock address, data, control and parity arbitration arbitration clock origination n u b u s slot id slot id simplified n u b us ? diagram (10mhz operating frequency) adl cdsetup m/io s1 s0 a2 a1 a0 cmd d07 | d00 chreset 7-bit latch 8-bit latch pos byte 2 card i.d. pos byte 1 card i.d. pos byte 0 octal 3 to 1 multiplexer 3-state driver transceiver control bufen dir pos byte 2 data output 8 8 8 8 8 8 7 block diagram of basic pos implementation in plhs501 nubus is a trademark of texas instruments, inc.

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