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document no. u15836ej2v1ud00 (2nd edition) date published july 2002 n cp(k) printed in japan ? 2001 pd780101 pd780102 pd780103 pd78f0103 78k0/kb1 8-bit single-chip microcontrollers preliminary user?s manual
preliminary user?s manual u15836ej2v1ud 2 [memo]
preliminary user?s manual u15836ej2v1ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. ethernet is a trademark of xerox corp. osf/motif is a trademark of opensoftware foundation, inc. tron stands for the realtime operating system nucleus. itron is an abbreviation of industrial tron.
preliminary user ? s manual u15836ej2v1ud 4 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: pd78f0103 the customer must judge the need for a license: pd780101, 780102, and 780103 ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
preliminary user ? s manual u15836ej2v1ud 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
preliminary user?s manual u15836ej2v1ud 6 major revisions in this edition (1/2) page description major revisions from u15836ej1v0ud00 to u15836ej2v0ud00 throughout x1 input clock oscillation stabilization time 2 12 /f x , 2 14 /f x , 2 15 /f x , 2 16 /f x , 2 17 /f x 2 11 /f x , 2 13 /f x , 2 14 /f x , 2 15 /f x , 2 16 /f x p.78 modification of figure 4-5 block diagram of p10 p.89 modification of table 4-3 settings of port mode register and output latch when alternate-function is used p.98 modification of figure 5-6 format of oscillation stabilization time counter status register (ostc) p.99 modification of figure 5-7 format of oscillation stabilization time select register (osts) p.108 addition of 5.7 clock selection flowchart and register settings p.216 addition of remark to 12.1 functions of serial interface uart6 p.273 addition of reset to table 14-1 interrupt source list p.290 modification of figure 15-2 format of oscillation stabilization time counter status register (ostc) p.291 modification of figure 15-3 format of oscillation stabilization time select register (osts) p.368 addition of chapter 25 retry major revisions from u15836ej2v0ud00 to u15836ej2v1ud00 (1/2) p.59 modification of reset value of the following register in table 3-5 special function register list ? serial i/o shift register 10 (sio10) p.60 p.61 p.61 p.61 modification of manipulatable bit unit of the following registers in table 3-5 special function register list ? oscillation stabilization time counter status register (ostc) ? interrupt request flag register 1l (if1l) ? interrupt mask flag register 1l (mk1l) ? priority specification flag register 1l (pr1l) p.98 modification of manipulatable bit unit in 5.3 (5) oscillation stabilization time counter status register (ostc) pp.104, 105 modification of figure 5-11 status transition diagram p.106 modification of table 5-3 relationship between operation clocks in each operation status p.106 modification of table 5-4 oscillation control flags and clock oscillation status p.110 modification of table 5-6 clock and register settings p.114 modification of reset value in 6.2 (2) 16-bit timer capture/compare register 000 (cr000) and (3) 16-bit timer capture/compare register 010 (cr010) p.119 modification of manipulatable bit unit in 6.3 (4) prescaler mode register 00 (prm00) p.168 modification of caution in 9.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option pp.169 to 171 modification of 9.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) p.171 addition of 9.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask option) p.191 addition of (11) a/d converter sampling time and a/d conversion start delay time in 10.6 cautions for a/d converter p.259 modification of reset value in 13.2 (2) serial i/o shift register 10 (sio10) the mark shows major revised points.
preliminary user?s manual u15836ej2v1ud 7 major revisions in this edition (2/2) page description major revisions from u15836ej2v0ud00 to u15836ej2v1ud00 (2/2) p.290 modification of manipulatable bit unit in 15.1.2 (1) oscillation stabilization time counter status register (ostc) p.292 modification of a/d converter item in table 15-2 operating statuses in halt mode pp.312, 313 addition of 18.4 cautions for power-on-clear circuit p.317 modification of figure 19-3 format of low-voltage detection level selection register (lvis) pp.322 to 325 addition of 19.5 cautions for low-voltage detector p.351 p.353 pp.354 to 356 p.363 p.363 p.364 p.364 p.364 pp.365, 366 modification of the following contents in chapter 23 electrical specifications (target values) ? absolute maximum ratings ? x1 oscillator characteristics ? dc characteristics ? a/d converter characteristics ? poc circuit characteristics ? lvi circuit characteristics ? data memory stop mode low supply voltage data retention characteristics (deletion of data retention supply current) ? deletion of ring-osc characteristics ? flash memory programming characteristics pp.368 to 370 modification from chapter 25 retry to chapter 25 cautions for wait the mark shows major revised points.
preliminary user?s manual u15836ej2v1ud 8 introduction readers this manual is intended for user engineers who wish to understand the functions of the 78k0/kb1 series and design and develop application systems and programs for these devices. the target products are as follows. 78k0/kb1 series: pd780101, 780102, 780103, and 78f0103 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0/kb1 series manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). 78k0/kb1 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? when using this manual as the manual for (a) products, (a1) products, and (a2) products: only the quality grade differs between standard products and (a), (a1), and (a2) products. read the part number as follows. ? pd780101 pd780101(a), 780101(a1), 780101(a2) ? pd780102 pd780102(a), 780102(a1), 780102(a2) ? pd780103 pd780103(a), 780103(a1), 780103(a2) ? pd78f0103 pd78f0103(a), 78f0103(a1) ? to gain a general understanding of functions: read this manual in the order of the contents . ? how to interpret the register format: for a bit number enclosed in square, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the c compiler. ? to check the details of a register when you know the register name. refer to appendix c register index .
preliminary user?s manual u15836ej2v1ud 9 ? to know details of the 78k/0 series instructions. refer to the separate document 78k/0 series instructions user?s manual (u12326e) . caution examples in this manual employ the ?standard? quality grade for general electronics. when using examples in this manual for the ?special? quality grade, review the quality grade of each part and/or circuit actually used. conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text. caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/kb1 user?s manual this manual 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u14445e language u14446e ra78k0 assembler package structured assembly language u11789e operation u14297e cc78k0 c compiler language u14298e sm78k0s, sm78k0 system simulator ver. 2.10 or later operation (windows tm based) u14611e sm78k series system simulator ver. 2.10 or later external part user open interface specifications u15006e id78k0-ns integrated debugger ver. 2.00 or later operation (windows based) u14379e reference u11539e id78k0 integrated debugger windows based guide u11649e fundamentals u11537e rx78k0 real-time os installation u11536e project manager ver. 3.12 or later (windows based) u14610e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
preliminary user?s manual u15836ej2v1ud 10 documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-780148-ns-em1 emulation board to be prepared documents related to flash memory programming document name document no. pg-fp3 flash memory programmer user?s manual u13502e other documents document name document no. semiconductor selection guide ? product & packages ? x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
preliminary user?s manual u15836ej2v1ud 11 contents chapter 1 outline ........................................................................................................... ..................25 1.1 features .................................................................................................................... ...................25 1.2 applications................................................................................................................ .................26 1.3 ordering information ........................................................................................................ ..........27 1.4 quality grade............................................................................................................... ................29 1.5 pin configuration (top view)................................................................................................ .....30 1.6 78k0/kxx series lineup ...................................................................................................... .......32 1.7 block diagram ............................................................................................................... ..............33 1.8 outline of functions ........................................................................................................ ...........34 chapter 2 pin functions .................................................................................................... ............36 2.1 pin function list ........................................................................................................... ..............36 2.2 description of pin functions ................................................................................................ .....38 2.2.1 p00 to p03 (port 0)....................................................................................................... ...................38 2.2.2 p10 to p17 (port 1)....................................................................................................... ...................38 2.2.3 p20 to p23 (port 2)....................................................................................................... ...................39 2.2.4 p30 to p33 (port 3)....................................................................................................... ...................39 2.2.5 p120 (port 12) ............................................................................................................ .....................39 2.2.6 p130 (port 13) ............................................................................................................ .....................39 2.2.7 av ref .............................................................................................................................. ...............40 2.2.8 av ss .............................................................................................................................. .................40 2.2.9 reset..................................................................................................................... .......................40 2.2.10 x1 and x2 ................................................................................................................ .......................40 2.2.11 v dd .............................................................................................................................. ...................40 2.2.12 v ss .............................................................................................................................. ...................40 2.2.13 v pp (flash memory versions only).................................................................................................. ..40 2.2.14 ic (mask rom versions only) .............................................................................................. ...........40 2.3 pin i/o circuits and recommended connection of unused pins..........................................41 chapter 3 cpu architecture ................................................................................................. ......43 3.1 memory space ................................................................................................................ .............43 3.1.1 internal program memory space ............................................................................................. ........48 3.1.2 internal data memory space ................................................................................................ ...........49 3.1.3 special function register (sfr) area ...................................................................................... .........49 3.1.4 data memory addressing.................................................................................................... ............50 3.2 processor registers ......................................................................................................... ..........54 3.2.1 control registers......................................................................................................... .....................54 3.2.2 general-purpose registers ................................................................................................. .............57 3.2.3 special function registers (sfrs) ......................................................................................... ........58 3.3 instruction address addressing .............................................................................................. .62 3.3.1 relative addressing ....................................................................................................... .................62 3.3.2 immediate addressing...................................................................................................... ...............63 3.3.3 table indirect addressing................................................................................................. ...............64 3.3.4 register addressing ....................................................................................................... .................64 3.4 operand address addressing .................................................................................................. .65
preliminary user?s manual u15836ej2v1ud 12 3.4.1 implied addressing ........................................................................................................ ................. 65 3.4.2 register addressing ....................................................................................................... ................ 66 3.4.3 direct addressing ......................................................................................................... .................. 67 3.4.4 short direct addressing ................................................................................................... ............... 68 3.4.5 special function register (sfr) addressing................................................................................ .... 69 3.4.6 register indirect addressing.............................................................................................. ............. 70 3.4.7 based addressing .......................................................................................................... ................ 71 3.4.8 based indexed addressing.................................................................................................. ........... 72 3.4.9 stack addressing.......................................................................................................... .................. 72 chapter 4 port functions ................................................................................................... ........ 73 4.1 port functions .............................................................................................................. .............. 73 4.2 port configuration.......................................................................................................... ............ 74 4.2.1 port 0 .................................................................................................................... ......................... 75 4.2.2 port 1 .................................................................................................................... ......................... 78 4.2.3 port 2 .................................................................................................................... ......................... 84 4.2.4 port 3 .................................................................................................................... ......................... 85 4.2.5 port 12 ................................................................................................................... ........................ 86 4.2.6 port 13 ................................................................................................................... ........................ 87 4.3 registers controlling port function ........................................................................................ 8 7 4.4 port function operations .................................................................................................... ...... 92 4.4.1 writing to i/o port ....................................................................................................... .................... 92 4.4.2 reading from i/o port..................................................................................................... ................ 92 4.4.3 operations on i/o port.................................................................................................... ................ 92 chapter 5 clock generator .................................................................................................. .... 93 5.1 functions of clock generator................................................................................................ ... 93 5.2 configuration of clock generator ............................................................................................ 93 5.3 registers controlling clock generator.................................................................................... 95 5.4 system clock oscillator ..................................................................................................... ..... 100 5.4.1 x1 oscillator............................................................................................................. ..................... 100 5.4.2 ring-osc oscillator....................................................................................................... ............... 102 5.4.3 prescaler................................................................................................................. ..................... 102 5.5 clock generator operation ................................................................................................... .. 102 5.6 time required to switch between ring-osc clock and x1 input clock ........................... 107 5.7 clock selection flowchart and register settings ................................................................ 108 5.7.1 changing to x1 input clock from ring-osc clock ........................................................................ 108 5.7.2 changing from x1 input clock to ring-osc clock ........................................................................ 109 5.7.3 register settings ......................................................................................................... ................. 110 chapter 6 16-bit timer/event counter 00 ............................................................................ 111 6.1 functions of 16-bit timer/event counter 00 ......................................................................... 111 6.2 configuration of 16-bit timer/event counter 00................................................................... 112 6.3 registers controlling 16-bit timer/event counter 00 .......................................................... 115 6.4 operation of 16-bit timer/event counter 00 ......................................................................... 121 6.4.1 interval timer operation .................................................................................................. .............. 121 6.4.2 ppg output operations..................................................................................................... ............ 122 6.4.3 pulse width measurement operations ........................................................................................ .. 124
preliminary user?s manual u15836ej2v1ud 13 6.4.4 external event counter operation .......................................................................................... ........131 6.4.5 square-wave output operation.............................................................................................. ........132 6.5 cautions on 16-bit timer/event counter 00...........................................................................134 chapter 7 8-bit timer/event counter 50..............................................................................137 7.1 functions of 8-bit timer/event counter 50 ............................................................................137 7.2 configuration of 8-bit timer/event counter 50......................................................................138 7.3 registers controlling 8-bit timer/event counter 50 .............................................................139 7.4 operations of 8-bit timer/event counter 50 ..........................................................................142 7.4.1 operation as interval timer............................................................................................... .............142 7.4.2 operation as external event counter ....................................................................................... ......144 7.4.3 operation as square-wave output ........................................................................................... ......145 7.4.4 operation as pwm output................................................................................................... ..........146 7.5 cautions on 8-bit timer/event counter 50.............................................................................148 chapter 8 8-bit timers h0 and h1 ........................................................................................ ...149 8.1 functions of 8-bit timers h0 and h1 ......................................................................................149 8.2 configuration of 8-bit timers h0 and h1................................................................................149 8.3 registers controlling 8-bit timers h0 and h1 .......................................................................151 8.4 operation of 8-bit timers h0 and h1 ......................................................................................154 8.4.1 operation as interval timer............................................................................................... .............154 8.4.2 operation as pwm pulse generator.......................................................................................... ....157 chapter 9 watchdog timer ................................................................................................... .....163 9.1 functions of watchdog timer ................................................................................................. 163 9.2 configuration of watchdog timer ...........................................................................................16 4 9.3 registers controlling watchdog timer ..................................................................................165 9.4 operation of watchdog timer................................................................................................. .167 9.4.1 watchdog timer operation when ?ring-osc cannot be stopped? is selected by mask option ......167 9.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option..................................................................................................... .......168 9.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option)................................169 9.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask option)................................171 chapter 10 a/d converter ................................................................................................... .......172 10.1 function of a/d converter .................................................................................................. .....172 10.2 a/d converter configuration ................................................................................................ ...174 10.3 registers controlling a/d converter ......................................................................................17 6 10.4 a/d converter operations ................................................................................................... .....179 10.4.1 basic operations of a/d converter........................................................................................ .........179 10.4.2 input voltage and conversion results..................................................................................... ........181 10.4.3 a/d converter operation mode ............................................................................................. .........182 10.5 how to read a/d converter characteristics table................................................................185 10.6 cautions for a/d converter................................................................................................. .....187 chapter 11 serial interface uart0 ( pd780102, 780103, and 78f0103 only) ..........192
preliminary user?s manual u15836ej2v1ud 14 11.1 functions of serial interface uart0 ...................................................................................... 19 2 11.2 configuration of serial interface uart0................................................................................ 193 11.3 registers controlling serial interface uart0....................................................................... 196 11.4 operation of serial interface uart0 ...................................................................................... 20 0 11.4.1 operation stop mode...................................................................................................... .............. 200 11.4.2 asynchronous serial interface (uart) mode ............................................................................... 2 01 11.4.3 dedicated baud rate generator............................................................................................ ......... 209 chapter 12 serial interface uart6 ...................................................................................... 215 12.1 functions of serial interface uart6 ...................................................................................... 21 5 12.2 configuration of serial interface uart6................................................................................ 219 12.3 registers controlling serial interface uart6....................................................................... 222 12.4 operation of serial interface uart6 ...................................................................................... 23 0 12.4.1 operation stop mode...................................................................................................... .............. 230 12.4.2 asynchronous serial interface (uart) mode ............................................................................... 2 31 12.4.3 dedicated baud rate generator............................................................................................ ......... 249 chapter 13 serial interface csi10 ........................................................................................ 2 58 13.1 functions of serial interface csi10 ........................................................................................ 258 13.2 configuration of serial interface csi10.................................................................................. 25 8 13.3 registers controlling serial interface csi10......................................................................... 260 13.4 operation of serial interface csi10 ........................................................................................ 262 13.4.1 operation stop mode...................................................................................................... .............. 262 13.4.2 3-wire serial i/o mode ................................................................................................... ............... 262 chapter 14 interrupt functions............................................................................................. 272 14.1 interrupt function types ................................................................................................... ...... 272 14.2 interrupt sources and configuration ..................................................................................... 272 14.3 registers controlling interrupt function............................................................................... 275 14.4 interrupt servicing operations ............................................................................................. .. 281 14.4.1 maskable interrupt acknowledgement....................................................................................... ... 281 14.4.2 software interrupt request acknowledgement .............................................................................. 2 83 14.4.3 multiple interrupt servicing ............................................................................................. .............. 284 14.4.4 interrupt request hold ................................................................................................... ................ 287 chapter 15 standby function ................................................................................................ .. 288 15.1 standby function and configuration ..................................................................................... 288 15.1.1 standby function ......................................................................................................... ................. 288 15.1.2 registers controlling standby function................................................................................... ....... 290 15.2 standby function operation ................................................................................................. .. 292 15.2.1 halt mode ................................................................................................................ .................. 292 15.2.2 stop mode ................................................................................................................ ................. 295 chapter 16 reset function.................................................................................................. ...... 298 16.1 register for confirming reset source ................................................................................... 303 chapter 17 clock monitor ................................................................................................... ..... 304 17.1 functions of clock monitor................................................................................................. .... 304
preliminary user?s manual u15836ej2v1ud 15 17.2 configuration of clock monitor ............................................................................................. ..304 17.3 registers controlling clock monitor.......................................................................................3 05 17.4 operation of clock monitor................................................................................................. .....306 chapter 18 power-on-clear circuit ......................................................................................310 18.1 functions of power-on-clear circuit.......................................................................................3 10 18.2 configuration of power-on-clear circuit ................................................................................311 18.3 operation of power-on-clear circuit.......................................................................................3 11 18.4 cautions for power-on-clear circuit .......................................................................................3 12 chapter 19 low-voltage detector ........................................................................................314 19.1 functions of low-voltage detector.........................................................................................3 14 19.2 configuration of low-voltage detector ..................................................................................314 19.3 registers controlling low-voltage detector .........................................................................315 19.4 operation of low-voltage detector.........................................................................................3 18 19.5 cautions for low-voltage detector .........................................................................................3 22 chapter 20 mask options .................................................................................................... ........326 chapter 21 pd78f0103.....................................................................................................................3 27 21.1 internal memory size switching register...............................................................................328 21.2 flash memory programming................................................................................................... .329 21.2.1 selection of communication mode .......................................................................................... ......329 21.2.2 flash memory programming function........................................................................................ ....330 21.2.3 connecting flashpro iii.................................................................................................. ...............331 21.2.4 connection on adapter for flash memory writing........................................................................... 333 chapter 22 instruction set ................................................................................................. ......338 22.1 conventions used in operation list .......................................................................................33 8 22.1.1 operand identifiers and specification methods ............................................................................ .338 22.1.2 description of operation column.......................................................................................... ..........339 22.1.3 description of flag operation column..................................................................................... ........339 22.2 operation list ............................................................................................................. ...............340 22.3 instructions listed by addressing type ................................................................................348 chapter 23 electrical specifications (target values)..............................................351 chapter 24 package drawing ................................................................................................. ..367 chapter 25 cautions for wait .............................................................................................. ...368 25.1 cautions for wait.......................................................................................................... .............368 25.2 peripheral hardware that generates wait .............................................................................369 25.3 example of wait occurrence ................................................................................................. ..370 appendix a development tools ............................................................................................... 371 a.1 software package............................................................................................................ ..........373 a.2 language processing software...............................................................................................3 74 a.3 flash memory writing tools .................................................................................................. ..375
preliminary user?s manual u15836ej2v1ud 16 a.4 debugging tools ............................................................................................................. ......... 376 a.4.1 hardware .................................................................................................................. ................... 376 a.4.2 software.................................................................................................................. ..................... 377 appendix b embedded software ............................................................................................. 37 8 appendix c register index .................................................................................................. ....... 379 c.1 register index (in alphabetical order with respect to register names)........................... 379 c.2 register index (in alphabetical order with respect to register symbol) ......................... 382 appendix d revision history ................................................................................................ ..... 385
preliminary user?s manual u15836ej2v1ud 17 list of figures (1/6) figure no. title page 2-1 pin i/o circuit list ........................................................................................................ ..............................42 3-1 memory map ( pd780101)...................................................................................................................... ..44 3-2 memory map ( pd780102)...................................................................................................................... ..45 3-3 memory map ( pd780103)...................................................................................................................... ..46 3-4 memory map ( pd78f0103) ..................................................................................................................... 47 3-5 data memory addressing ( pd780101) ....................................................................................................50 3-6 data memory addressing ( pd780102) ....................................................................................................51 3-7 data memory addressing ( pd780103) ....................................................................................................52 3-8 data memory addressing ( pd78f0103) ..................................................................................................53 3-9 format of program counter ................................................................................................... ....................54 3-10 format of program status word .............................................................................................. ..................54 3-11 stack pointer format ....................................................................................................... ..........................56 3-12 data to be saved to stack memory ........................................................................................... ................56 3-13 data to be restored from stack memory ...................................................................................... ............56 3-14 configuration of general-purpose registers ................................................................................. ............57 4-1 port types .................................................................................................................. ...............................73 4-2 block diagram of p00 ........................................................................................................ ........................75 4-3 block diagram of p01 ........................................................................................................ ........................76 4-4 block diagram of p02 and p03................................................................................................ ..................77 4-5 block diagram of p10 ........................................................................................................ ........................78 4-6 block diagram of p11 and p14................................................................................................ ..................79 4-7 block diagram of p12 ........................................................................................................ ........................80 4-8 block diagram of p13 ........................................................................................................ ........................81 4-9 block diagram of p15 ........................................................................................................ ........................82 4-10 block diagram of p16 and p17............................................................................................... ...................83 4-11 block diagram of p20 to p23................................................................................................ .....................84 4-12 block diagram of p30 to p33................................................................................................ .....................85 4-13 block diagram of p120 ...................................................................................................... ........................86 4-14 block diagram of p130 ...................................................................................................... ........................87 4-15 format of port mode register............................................................................................... .....................88 4-16 format of pull-up resistor option register ................................................................................. ..............90 4-17 format of input switch control register (isc).............................................................................. .............91 5-1 block diagram of clock generator ............................................................................................ ................94 5-2 format of processor clock control register (pcc)............................................................................ .......95 5-3 format of ring-osc mode register (rcm) ...................................................................................... ........96 5-4 format of main clock mode register (mcm).................................................................................... .........97 5-5 format of main osc control register (moc) ................................................................................... ........98 5-6 format of oscillation stabilization time counter status register (ostc) ................................................98 5-7 format of oscillation stabilization time select register (osts) ............................................................. .99 5-8 external circuit of x1 oscillator ........................................................................................... ....................100 5-9 examples of incorrect resonator connection.................................................................................. ........101
preliminary user?s manual u15836ej2v1ud 18 list of figures (2/6) figure no. title page 5-10 timing diagram of cpu default start using ring-osc ......................................................................... . 103 5-11 status transition diagram.................................................................................................. ..................... 104 5-12 changing to x1 input clock from ring-osc clock (flowchart) .............................................................. 108 5-13 changing from x1 input clock to ring-osc clock (flowchart) .............................................................. 109 6-1 block diagram of 16-bit timer/event counter 00 .............................................................................. ..... 112 6-2 format of 16-bit timer mode control register 00 (tmc00) ................................................................... 11 6 6-3 format of capture/compare control register 00 (crc00) .................................................................... 117 6-4 format of 16-bit timer output control register 00 (toc00).................................................................. 1 18 6-5 format of prescaler mode register 00 (prm00) ................................................................................ .... 119 6-6 format of port mode register 0 (pm0) ........................................................................................ ........... 120 6-7 control register settings for interval timer operation...................................................................... ...... 121 6-8 interval timer configuration diagram ........................................................................................ ............. 122 6-9 timing of interval timer operation.......................................................................................... ................ 122 6-10 control register settings for ppg output operation ......................................................................... ..... 123 6-11 control register settings for pulse width measurement with free-running counter and one capture register ......................................................................... 124 6-12 configuration diagram for pulse width measurement by free-running counter................................... 125 6-13 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) ......................................................................... 12 5 6-14 control register settings for measurement of two pulse widths with free-running counter............... 126 6-15 cr010 capture operation with rising edge specified ......................................................................... .. 127 6-16 timing of pulse width measurement operation with free-running counter (with both edges specified) .................................................................................................... ................ 127 6-17 control register settings for pulse width measurement with free-running counter and two capture registers .......................................................................................................... ................. 128 6-18 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified)....................................................................... 12 9 6-19 control register settings for pulse width measurement by means of restart ....................................... 130 6-20 timing of pulse width measurement operation by means of restart (with rising edge specified) ...... 130 6-21 control register settings in external event counter mode................................................................... .. 131 6-22 configuration diagram of external event counter ............................................................................ ...... 132 6-23 external event counter operation timing (with rising edge specified) ................................................. 132 6-24 control register settings in square-wave output mode ....................................................................... . 133 6-25 square-wave output operation timing ........................................................................................ .......... 133 6-26 start timing of 16-bit timer counter 00 (tm00) ............................................................................. ........ 134 6-27 timings after change of compare register during timer count operation........................................... 134 6-28 capture register data retention timing ..................................................................................... ........... 135 6-29 operation timing of ovf00 flag ............................................................................................. ............... 135 7-1 block diagram of 8-bit timer/event counter 50 ............................................................................... ...... 137 7-2 format of timer clock selection register 50 (tcl50)......................................................................... ... 139 7-3 format of 8-bit timer mode control register 50 (tmc50) ..................................................................... 1 40 7-4 format of port mode register 1 (pm1) ........................................................................................ ........... 141
preliminary user?s manual u15836ej2v1ud 19 list of figures (3/6) figure no. title page 7-5 interval timer operation timing ............................................................................................. .................142 7-6 external event counter operation timing (with rising edge specified)..................................................144 7-7 square-wave output operation timing......................................................................................... ..........145 7-8 pwm output operation timing................................................................................................. ...............147 7-9 timing of operation with cr50 changed ....................................................................................... .........148 7-10 8-bit timer counter 50 start timing ........................................................................................ ................148 8-1 block diagram of 8-bit timer h0 ............................................................................................. ................149 8-2 block diagram of 8-bit timer h1 ............................................................................................. ................150 8-3 format of 8-bit timer h mode register 0 (tmhmd0)............................................................................ ..152 8-4 format of 8-bit timer h mode register 1 (tmhmd1)............................................................................ ..153 8-5 register setting in interval timer mode..................................................................................... ..............154 8-6 timing of interval timer operation .......................................................................................... ................155 8-7 register setting in pwm pulse generator mode................................................................................ .....157 8-8 operation timing in pwm pulse generator mode................................................................................ ...159 9-1 block diagram of watchdog timer ............................................................................................. .............165 9-2 format of watchdog timer mode register (wdtm)............................................................................... .166 9-3 format of watchdog timer enable register (wdte) ............................................................................. .167 9-4 operation in stop mode (cpu clock and wdt operation clock: x1 input clock)................................169 9-5 operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock).........169 9-6 operation in stop mode (cpu clock: ring-osc clock, wdt operation clock: x1 input clock)..........170 9-7 operation in stop mode (cpu clock and wdt operation clock: ring-osc clock).............................171 9-8 operation in halt mode ...................................................................................................... ...................171 10-1 block diagram of a/d converter............................................................................................. .................173 10-2 block diagram of power-fail detection function............................................................................. ........173 10-3 format of a/d conversion register (adcr)................................................................................... .........174 10-4 format of a/d converter mode register (adm) ................................................................................ ......176 10-5 timing chart when boost reference voltage generator is used ...........................................................177 10-6 format of analog input channel specification register (ads)................................................................ 178 10-7 format of power-fail comparison mode register (pfm) ........................................................................ 178 10-8 format of power-fail comparison threshold register (pft)..................................................................1 79 10-9 basic operation of a/d converter........................................................................................... .................180 10-10 relationship between analog input voltage and a/d conversion result ................................................181 10-11 a/d conversion operation .................................................................................................. .....................182 10-12 power-fail detection (when pfen = 1 and pfcm = 0) ......................................................................... .183 10-13 overall error ............................................................................................................. ...............................185 10-14 quantization error........................................................................................................ ............................185 10-15 zero-scale error .......................................................................................................... ............................186 10-16 full-scale error.......................................................................................................... ..............................186 10-17 integral linearity error .................................................................................................. ...........................186 10-18 differential linearity error .............................................................................................. ..........................186 10-19 example of method of reducing current consumption in standby mode ...............................................187
preliminary user?s manual u15836ej2v1ud 20 list of figures (4/6) figure no. title page 10-20 storing conversion result in adcr and timing of data read from adcr............................................ 188 10-21 analog input pin connection............................................................................................... .................... 189 10-22 timing of a/d conversion end interrupt request generation................................................................. 190 10-23 timing of a/d converter sampling and a/d conversion start delay ...................................................... 191 11-1 block diagram of serial interface uart0 .................................................................................... ........... 194 11-2 format of asynchronous serial interface operation mode register 0 (asim0) ...................................... 196 11-3 format of asynchronous serial interface reception error status register 0 (asis0) ............................ 198 11-4 format of baud rate generator control register 0 (brgc0) ................................................................ 199 11-5 format of normal uart transmit/receive data ................................................................................ .... 204 11-6 example of normal uart transmit/receive data format ..................................................................... 204 11-7 normal transmission completion interrupt request timing................................................................... 2 06 11-8 reception completion interrupt request timing .............................................................................. ...... 207 11-9 noise filter circuit....................................................................................................... ............................ 208 11-10 configuration of baud rate generator...................................................................................... .............. 209 11-11 permissible baud rate range during reception .............................................................................. ..... 213 12-1 lin transmission operation ................................................................................................. .................. 216 12-2 lin reception operation.................................................................................................... ..................... 217 12-3 port configuration for lin reception operation............................................................................. ......... 218 12-4 block diagram of serial interface uart6 .................................................................................... ........... 220 12-5 format of asynchronous serial interface operation mode register 6 (asim6) ...................................... 222 12-6 format of asynchronous serial interface reception error status register 6 (asis6) ............................ 224 12-7 format of asynchronous serial interface transmission status register 6 (asif6) ................................ 225 12-8 format of clock selection register 6 (cksr6) ............................................................................... ....... 226 12-9 format of baud rate generator control register 6 (brgc6) ................................................................ 227 12-10 format of asynchronous serial interface control register 6 (asicl6)................................................... 228 12-11 format of normal uart transmit/receive data ............................................................................... ..... 237 12-12 example of normal uart transmit/receive data format ..................................................................... 23 8 12-13 normal transmission completion interrupt request timing................................................................... 240 12-14 processing flow of continuous transmission ................................................................................ ........ 242 12-15 timing of starting continuous transmission................................................................................ ........... 243 12-16 timing of ending continuous transmission.................................................................................. .......... 244 12-17 reception completion interrupt request timing ............................................................................. ....... 245 12-18 reception error interrupt................................................................................................. ........................ 246 12-19 noise filter circuit...................................................................................................... ............................. 247 12-20 sbf transmission.......................................................................................................... ......................... 247 12-21 sbf reception ............................................................................................................. ........................... 248 12-22 configuration of baud rate generator...................................................................................... .............. 250 12-23 permissible baud rate range during reception .............................................................................. ..... 255 12-24 transfer rate during continuous transmission .............................................................................. ....... 257 13-1 block diagram of serial interface csi10.................................................................................... ............. 259 13-2 format of serial operation mode register 10 (csim10) ....................................................................... . 260
preliminary user?s manual u15836ej2v1ud 21 list of figures (5/6) figure no. title page 13-3 format of serial clock selection register 10 (csic10)...................................................................... .....261 13-4 timing in 3-wire serial i/o mode........................................................................................... ..................266 13-5 timing of clock/data phase ................................................................................................. ...................268 13-6 output operation of first bit .............................................................................................. ......................269 13-7 output value of so10 pin (last bit) ........................................................................................ ................270 14-1 basic configuration of interrupt function.................................................................................. ...............274 14-2 format of interrupt request flag register (if0l, if0h, if1l) ............................................................... ..276 14-3 format of interrupt mask flag register (mk0l, mk0h, mk1l) ...............................................................277 14-4 format of priority specification flag register (pr0l, pr0h, pr1l) .......................................................278 14-5 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ....................................................................27 9 14-6 format of program status word .............................................................................................. ................280 14-7 interrupt request acknowledgement processing algorithm ....................................................................2 82 14-8 interrupt request acknowledgement timing (minimum time) ................................................................283 14-9 interrupt request acknowledgement timing (maximum time) ...............................................................283 14-10 examples of multiple interrupt servicing.................................................................................. ................285 14-11 interrupt request hold.................................................................................................... .........................287 15-1 operation timing when stop mode is released ................................................................................ ..289 15-2 format of oscillation stabilization time counter status register (ostc) ..............................................290 15-3 format of oscillation stabilization time select register (osts) ............................................................ 291 15-4 halt mode release by interrupt request generation.......................................................................... ..293 15-5 halt mode release by reset input ........................................................................................... ..........294 15-6 stop mode release by interrupt request generation .......................................................................... .296 15-7 stop mode release by reset input ........................................................................................... .........297 16-1 block diagram of reset function ............................................................................................ ................299 16-2 timing of reset by reset input ............................................................................................. ................300 16-3 timing of reset due to watchdog timer overflow............................................................................. .....300 16-4 timing of reset in stop mode by reset input................................................................................ .....300 16-5 format of reset control flag register (resf) ............................................................................... ........303 17-1 block diagram of clock monitor............................................................................................. ..................304 17-2 format of clock monitor mode register (clm) ................................................................................ .......305 17-3 timing of clock monitor .................................................................................................... .......................307 18-1 block diagram of power-on-clear circuit .................................................................................... ............311 18-2 timing of internal reset signal generation in power-on-clear circuit ....................................................311 18-3 example of software processing after release of reset ...................................................................... ..312 19-1 block diagram of low-voltage detector ...................................................................................... ............314 19-2 format of low-voltage detection register (lvim) ............................................................................ ......316 19-3 format of low-voltage detection level selection register (lvis)..........................................................31 7
preliminary user?s manual u15836ej2v1ud 22 list of figures (6/6) figure no. title page 19-4 timing of low-voltage detector internal reset signal generation ......................................................... 319 19-5 timing of low-voltage detector interrupt signal generation ................................................................. . 321 19-6 example of software processing after release of reset ...................................................................... . 323 19-7 example of software processing of lvi interrupt............................................................................ ........ 325 21-1 format of internal memory size switching register (ims).................................................................... .. 328 21-2 communication mode selection format ........................................................................................ ......... 330 21-3 connection of flashpro iii in 3-wire serial i/o mode ....................................................................... ....... 331 21-4 connection of flashpro iii in 3-wire serial i/o mode (using handshake) .............................................. 331 21-5 connection of flashpro iii in uart (uart0) mode............................................................................ .... 332 21-6 connection of flashpro iii in uart (uart0) mode (using handshake) ................................................ 332 21-7 connection of flashpro iii in uart (uart6) mode............................................................................ .... 332 21-8 example of wiring adapter for flash memory writing in 3-wire serial i/o mode ................................... 333 21-9 example of wiring adapter for flash memory writing in 3-wire serial i/o mode (using handshake) .... 334 21-10 example of wiring adapter for flash memory writing in uart mode (uart0) ..................................... 335 21-11 example of wiring adapter for flash memory writing in uart mode (uart0) (using handshake) ..... 336 21-12 example of wiring adapter for flash memory writing in uart mode (uart6) ..................................... 337 a-1 development tool configuration.............................................................................................. ............... 372
preliminary user?s manual u15836ej2v1ud 23 list of tables (1/2) table no. title page 1-1 flash memory versions corresponding to mask options of mask rom versions ....................................28 2-1 pin i/o circuit types ....................................................................................................... ...........................41 3-1 internal memory size switching register (ims) set value ..................................................................... ...43 3-2 internal memory capacity .................................................................................................... ......................48 3-3 vector table ................................................................................................................ ..............................48 3-4 internal high-speed ram capacity ............................................................................................ ...............49 3-5 special function register list .............................................................................................. .....................59 4-1 port functions.............................................................................................................. ..............................74 4-2 port configuration .......................................................................................................... ............................74 4-3 settings of port mode register and output latch when alternate-function is used ................................89 5-1 configuration of clock generator ............................................................................................ ..................93 5-2 relationship between cpu clock and minimum instruction execution time ............................................96 5-3 relationship between operation clocks in each operation status .........................................................106 5-4 oscillation control flags and clock oscillation status...................................................................... .......106 5-5 maximum time required to switch between ring-osc clock and x1 input clock ................................107 5-6 clock and register settings................................................................................................. ....................110 6-1 configuration of 16-bit timer/event counter 00 .............................................................................. ........112 6-2 ti000/p00 pin valid edge and cr000, cr010 capture trigger..............................................................113 6-3 ti010/to00/p01 pin valid edge and cr000 capture trigger.................................................................113 7-1 configuration of 8-bit timer/event counter 50 ............................................................................... .........138 8-1 configuration of 8-bit timers h0 and h1 ..................................................................................... ............149 9-1 loop detection time of watchdog timer....................................................................................... ..........163 9-2 mask option setting and watchdog timer operation mode....................................................................164 9-3 configuration of watchdog timer ............................................................................................. ...............164 10-1 configuration of a/d converter............................................................................................. ...................174 10-2 settings of adcs and adce .................................................................................................. .................177 10-3 a/d converter sampling time and a/d conversion start delay time (adm set value) .........................191 11-1 configuration of serial interface uart0.................................................................................... ..............193 11-2 cause of reception error ................................................................................................... .....................208 11-3 set data of baud rate generator............................................................................................ ................212 11-4 maximum/minimum permissible baud rate error ................................................................................ ...214 12-1 configuration of serial interface uart6.................................................................................... ..............219 12-2 write processing and writing to txb6 during execution of continuous transmission ...........................241
preliminary user?s manual u15836ej2v1ud 24 list of tables (2/2) table no. title page 12-3 cause of reception error................................................................................................... ..................... 246 12-4 set data of baud rate generator ............................................................................................ ............... 254 12-5 maximum/minimum permissible baud rate error................................................................................ ... 256 13-1 configuration of serial interface csi10.................................................................................... ............... 258 13-2 so10 pin status ............................................................................................................ ......................... 271 14-1 interrupt source list...................................................................................................... .......................... 273 14-2 flags corresponding to interrupt request sources ........................................................................... ..... 275 14-3 time from generation of maskable interrupt until servicing................................................................. .. 281 14-4 interrupt request enabled for multiple interrupt during interrupt servicing ............................................ 284 15-1 relationship between halt and stop modes and clock ..................................................................... 288 15-2 operating statuses in halt mode............................................................................................ .............. 292 15-3 operation after halt mode release.......................................................................................... ............ 294 15-4 operating statuses in stop mode ............................................................................................ ............. 295 15-5 operation after stop mode release .......................................................................................... ........... 297 16-1 hardware statuses after reset.............................................................................................. ................. 301 16-2 resf status when reset request is generated................................................................................ ... 303 17-1 configuration of clock monitor............................................................................................. ................... 304 17-2 operation status of clock monitor (when clme =1)........................................................................... ... 306 20-1 flash memory versions supporting mask options of mask rom versions............................................ 326 21-1 differences between pd78f0103 and mask rom versions ................................................................ 327 21-2 internal memory size switching register settings........................................................................... ....... 328 21-3 communication mode list.................................................................................................... ................... 329 21-4 main functions of flash memory programming................................................................................. ..... 330 22-1 operand identifiers and specification methods.............................................................................. ......... 338 25-1 registers that generate wait and number of cpu wait clocks............................................................ 369 25-2 number of wait clocks and number of execution clocks on occurrence of wait (a/d converter)........ 370
preliminary user?s manual u15836ej2v1ud 25 chapter 1 outline 1.1 features { rom, ram capacities data memory part number item program memory (rom) (internal high-speed ram) pd780101 8 kb 512 bytes pd780102 16 kb pd780103 mask rom 24 kb pd78f0103 flash memory 24 kb note 768 bytes note the internal flash memory and internal high-speed ram capacities can be changed using the internal memory size switching register (ims). { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { short startup is possible via the cpu default start using the on-chip ring-osc { on-chip clock monitor function using on-chip ring-osc { on-chip watchdog timer (operable with ring-osc clock) { on-chip uart supporting lin (local interconnect network) bus { minimum instruction execution time can be changed from high speed (0.2 s: @ 10 mhz operation with x1 input clock) to low-speed (3.2 s: @ 10 mhz operation with x1 input clock) { i/o ports: 22 { timer: 5 channels { serial interface uart: 1 channel csi1/uart note : 1 channel ( pd780101 only, csi1: 1 channel) { 10-bit resolution a/d converter: 4 channels { supply voltage: v dd = 2.7 to 5.5 v note select either of the functions of these alternate-function pins.
chapter 1 outline preliminary user?s manual u15836ej2v1ud 26 1.2 applications { automotive equipment ? system control for body electricals (power windows, keyless entry reception, etc.) ? sub-microcontrollers for control { home audio, car audio { av equipment { pc peripheral equipment (keyboards, etc.) { household electrical appliances ? outdoor air conditioner units ? microwave ovens, electric rice cookers { industrial equipment ? pumps ? vending machines ? fa
chapter 1 outline preliminary user?s manual u15836ej2v1ud 27 1.3 ordering information part number package internal rom pd780101mc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780102mc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780103mc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780101mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780102mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780103mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780101mc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780102mc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780103mc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780101mc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780102mc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd780103mc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f0103m1mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m2mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m3mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m4mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m5mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m6mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m1mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m2mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m3mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m4mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m5mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m6mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m1mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m2mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m3mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m4mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m5mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f0103m6mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory remark indicates rom code suffix.
chapter 1 outline preliminary user?s manual u15836ej2v1ud 28 mask rom versions ( pd780101, 780102, and 780103) include a mask options. when ordering, it is possible to select ?power-on-clear (poc) circuit can be used/cannot be used? and ?ring-osc clock can be stopped/cannot be stopped by software?. flash memory versions corresponding to the mask options of the mask rom versions are as follows. table 1-1. flash memory versions corresponding to mask options of mask rom versions mask option poc circuit ring-osc flash memory versions (part number) cannot be stopped pd78f0103m1mc-5a4 pd78f0103m1mc(a)-5a4 pd78f0103m1mc(a1)-5a4 poc cannot be used can be stopped by software pd78f0103m2mc-5a4 pd78f0103m2mc(a)-5a4 pd78f0103m2mc(a1)-5a4 cannot be stopped pd78f0103m3mc-5a4 pd78f0103m3mc(a)-5a4 pd78f0103m3mc(a1)-5a4 poc used (v poc = 2.85 v 0.15 v) can be stopped by software pd78f0103m4mc-5a4 pd78f0103m4mc(a)-5a4 pd78f0103m4mc(a1)-5a4 cannot be stopped pd78f0103m5mc-5a4 pd78f0103m5mc(a)-5a4 pd78f0103m5mc(a1)-5a4 poc used (v poc = 3.5 v 0.2 v) can be stopped by software pd78f0103m6mc-5a4 pd78f0103m6mc(a)-5a4 pd78f0103m6mc(a1)-5a4
chapter 1 outline preliminary user?s manual u15836ej2v1ud 29 1.4 quality grade part number package quality grade pd780101mc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd780102mc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd780103mc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd780101mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780102mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780103mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780101mc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780102mc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780103mc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780101mc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780102mc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd780103mc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m1mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f0103m2mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f0103m3mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f0103m4mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f0103m5mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f0103m6mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f0103m1mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m2mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m3mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m4mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m5mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m6mc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m1mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m2mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m3mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m4mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m5mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f0103m6mc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
chapter 1 outline preliminary user ? s manual u15836ej2v1ud 30 1.5 pin configuration (top view) ? 30-pin plastic ssop (7.62 mm (300)) pd780101mc- -5a4, 780102mc- -5a4, 780103mc- -5a4, pd780101mc(a)- -5a4, 780102mc(a)- -5a4, 780103mc(a)- -5a4, pd780101mc(a1)- -5a4, 780102mc(a1)- -5a4, 780103mc(a1)- -5a4, pd780101mc(a2)- -5a4, 780102mc(a2)- -5a4, 780103mc(a2)- -5a4, pd78f0103m1mc-5a4, 78f0103m2mc-5a4, 78f0103m3mc-5a4, 78f0103m4mc-5a4, pd78f0103m5mc-5a4, 78f0103m6mc-5a4, 78f0103m1mc(a)-5a4, 78f0103m2mc(a)-5a4, pd78f0103m3mc(a)-5a4, 78f0103m4mc(a)-5a4, 78f0103m5mc(a)-5a4, pd78f0103m6mc(a)-5a4, 78f0103m1mc(a1)-5a4, 78f0103m2mc(a1)-5a4, pd78f0103m3mc(a1)-5a4, 78f0103m4mc(a1)-5a4, 78f0103m5mc(a1)-5a4, pd78f0103m6mc(a1)-5a4 p33/intp4 p32/intp3 p31/intp2 p30/intp1 ic (v pp ) v ss v dd x1 x2 p03 reset p02 p01/ti010/to00 p00/ti000 p10/sck10/txd0 note 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p120/intp0 av ss av ref p20/ani0 p21/ani1 p22/ani2 p23/ani3 p130 p17/ti50/to50 p15/toh0 p16/toh1/intp5 p14/rxd6 p13/txd6 p12/so10 p11/si10/rxd0 note 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103. cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av ref pin to v dd . 3. connect the av ss pin to v ss . remark figures in parentheses apply only to the pd78f0103.
chapter 1 outline preliminary user ? s manual u15836ej2v1ud 31 pin identification ani0 to ani3: analog input av ref : analog reference voltage ic: internally connected intp0 to intp5: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p23: port 2 p30 to p33: port 3 p120: port 12 p130: port 13 reset: reset rxd0 note , rxd6: receive data sck10: serial clock input/output si10: serial data input so10: serial data output ti000, ti010, ti50: timer output to00, to50, toh0, toh1: timer output txd0 note , txd6: transmit data v dd : power supply v pp : programming power supply v ss : ground x1, x2: crystal (x1 input clock) note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103.
chapter 1 outline preliminary user ? s manual u15836ej2v1ud 32 1.6 78k0/kxx series lineup the lineup of products in the 78k0/kxx series (under development or in planning) is shown below. pd78f0103 flash memory: 24 kb, ram: 768 bytes mask rom: 24 kb, ram: 768 bytes mask rom: 16 kb, ram: 768 bytes mask rom: 8 kb, ram: 512 bytes pd780103 pd780102 pd780101 78k0/kb1 series: 30-pin (7.62 mm 0.65 mm pitch) pd78f0114 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780114 pd780113 pd780112 mask rom: 8 kb, ram: 512 bytes pd780111 78k0/kc1 series: 44-pin (10 10 mm 0.8 mm pitch) pd78f0124 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780124 pd780123 pd780122 mask rom: 8 kb, ram: 512 bytes pd780121 78k0/kd1 series: 52-pin (10 10 mm 0.65 mm pitch) pd78f0148 flash memory: 60 kb, ram: 2 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram: 2 kb mask rom: 32 kb, ram: 1 kb pd780148 pd780146 pd780144 mask rom: 24 kb, ram: 1 kb pd780143 78k0/kf1 series: 80-pin (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) pd78f0134 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780134 pd780133 pd780132 mask rom: 8 kb, ram: 512 bytes pd780131 pd78f0138 flash memory: 60 kb, ram: 2 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram : 2 kb pd780138 pd780136 78k0/ke1 series: 64-pin (10 10 mm 0.5 mm pitch, 12 12 mm 0.65 mm pitch, 14 14 mm 0.8 mm pitch)
chapter 1 outline preliminary user ? s manual u15836ej2v1ud 33 1.7 block diagram 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 serial interface csi10 si1/p11 so10/p12 sck10/p10 ani0/p20 to ani3/p23 interrupt control 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 4 a/d converter 78k/0 cpu core internal high-speed ram rom (flash memory) port 0 p00 to p03 4 port 1 p10 to p17 port 2 p20 to p23 4 port 3 p30 to p33 4 port 12 p120 port 13 p130 system control reset x1 x2 rxd0 note /p11 txd0 note /p10 serial interface uart0 note watchdog timer rxd6/p14 txd6/p13 serial interface uart6 v ss ic (v pp ) v dd av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 clock monitor power on clear/ low voltage indicator reset control ring-osc 8 note pd780102, 780103, and 78f0103 only. remark items in parentheses are available only in the pd78f0103.
chapter 1 outline preliminary user?s manual u15836ej2v1ud 34 1.8 outline of functions item pd780101 pd780102 pd780103 pd78f0103 rom 8 kb 16 kb 24 kb 24 kb (flash memory) internal memory high-speed ram 512 bytes 768 bytes memory space 64 kb x1 input clock (oscillation frequency) ceramic/crystal oscillation (10.0 mhz: v dd = 4.0 to 5.5 v, 8.38 mhz: v dd = 3.3 to 5.5 v, 5 mhz: v dd = 2.7 to 5.5 v) ring-osc clock (oscillation frequency) on-chip ring oscillation (240 khz (typ.)) general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (x1 input clock: @ f xp = 10 mhz operation) minimum instruction execution time 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (typ.) (ring-osc clock: @ f r = 240 khz (typ.) operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits 4 banks) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 22 cmos i/o 17 cmos input 4 cmos output 1 timers 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 1 channel 8-bit timer: 2 channels watchdog timer: 1 channel a/d converter 10-bit resolution 4 channels serial interface uart mode supporting lin-bus: 1 channel 3-wire serial i/o mode/uart mode note : 1 channel ( pd780101 only, 3-wire serial i/o mode: 1 channel) internal 10 12 vectored interrupt sources external 6 reset reset using reset pin internal reset by watchdog timer internal reset by clock monitor internal reset by power-on-reset internal reset by low-voltage detector supply voltage v dd = 2.7 to 5.5 v operating ambient temperature standard products, (a) products: t a = ? 40 to +85 c (a1) products: t a = ? 40 to +110 c (a2) products: t a = ? 40 to +125 c ( pd780101, 780102, and 780103 only) package 30-pin plastic ssop (7.62 mm (300)) note select either of the functions of these alternate-function pins.
chapter 1 outline preliminary user ? s manual u15836ej2v1ud 35 an outline of the timer is shown below. 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timers h0 and h1 watchdog timer interval timer 1 channel 1 channel 2 channels 1 channel operation mode external event counter 1 channel 1 channel ?? timer output 1 output 1 output 2 outputs ? ppg output 1 output ??? pwm output ? 1 output 2 outputs ? pulse width measurement 2 inputs ??? square-wave output 1 output 1 output ?? function interrupt source 2 1 2 ?
preliminary user?s manual u15836ej2v1ud 36 chapter 2 pin functions 2.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p10 sck10/txd0 note p11 si10/rxd0 note p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p23 input port 2. 4-bit input-only port. input ani0 to ani3 p30 to p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp1 to intp4 p120 i/o port 12. 1-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103.
chapter 2 pin functions preliminary user?s manual u15836ej2v1ud 37 (2) non-port pins pin name i/o function after reset alternate function intp0 p120 intp1 to intp4 p30 to p33 intp5 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p16/toh1 si10 input serial data input to serial interface input p11/rxd0 note so10 output serial data output from serial interface input p12 sck10 i/o clock input/output for serial interface input p10/txd0 note rxd0 note p11/si10 rxd6 input serial data input to asynchronous serial interface input p14 txd0 note p10/sck10 txd6 output serial data output from asynchronous serial interface input p13 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to capture registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input p01/to00 to00 output 16-bit timer/event counter 00 output input p01/ti010 ti50 input external count clock input to 8-bit timer/event counter 50 input p17/to50 to50 output 8-bit timer/event counter 50 output input p17/ti50 toh0 p15 toh1 output 8-bit timer h output input p16/intp5 ani0 to ani3 input a/d converter analog input input p20 to p23 av ref input a/d converter reference voltage input ?? av ss ? a/d converter ground potential. make the same potential as v ss . ?? reset input system reset input ?? x1 input ?? x2 ? connecting crystal resonator for x1 input clock oscillation ?? v dd ? positive power supply ?? v ss ? ground potential ?? ic ? internally connected. connect directly to v ss . ?? v pp ? flash memory programming mode setting. high-voltage application for program write/verify. connect directly to v ss in normal operation mode. ?? note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103.
chapter 2 pin functions preliminary user?s manual u15836ej2v1ud 38 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) p00 to p03 function as a 4-bit i/o port. these pins also function as timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p03 function as a 4-bit i/o port. p00 to p03 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p03 function as timer i/o. (a) ti000 this is the pins for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a capture trigger signal to the capture registers (cr000, cr010) of 16-bit timer/event counter 00. (b) ti010 this is the pin for inputting a capture trigger signal to the capture register (cr000) of 16-bit timer/event counter 00. (c) to00 this is a timer output pin. 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. these pins also function as pins for external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. (a) si10, so10 these are the serial data i/o pins of the serial interface. (b) sck10 this is the serial clock i/o pin of the serial interface. (c) rxd0 note , rxd6, txd0 note , and txd6 these are the serial data i/o pins of the asynchronous serial interface. note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103.
chapter 2 pin functions preliminary user?s manual u15836ej2v1ud 39 (d) ti50 this is the pin for inputting an external count clock to 8-bit timer/event counter 50. (e) to50, toh0, and toh1 these are timer output pins. (f) intp5 this is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 p20 to p23 (port 2) p20 to p23 function as a 4-bit input-only port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p23 function as a 4-bit input-only port. (2) control mode p20 to p23 function as a/d converter analog input pins (ani0 to ani3). 2.2.4 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also function as pins for external interrupt request input. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 can be set to input or output in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interrupt request input pins (intp1 to intp4) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.5 p120 (port 12) p120 functions as a 1-bit i/o port. this pin also functions as a pin for external interrupt request input. the following operation modes can be specified in 1-bit units. (1) port mode p120 functions as a 1-bit i/o port. p120 can be set to input or output in 1-bit units using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). (2) control mode p120 functions as an external interrupt request input pin (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 p130 (port 13) p130 functions as a 1-bit output-only port.
chapter 2 pin functions preliminary user?s manual u15836ej2v1ud 40 2.2.7 av ref this is the a/d converter reference voltage input pin. when a/d converter is not used, connect this pin to v dd . 2.2.8 av ss this is the a/d converter ground potential pin. even when the a/d converter is not used, always use this pin with the same potential as the v ss pin. 2.2.9 reset this is the active-low system reset input pin. 2.2.10 x1 and x2 these are the pins for connecting a crystal resonator for x1 input clock oscillation. when supplying an external clock, input a signal to the x1 pin and input the inverse signal to the x2 pin. 2.2.11 v dd this is the positive power supply pin. 2.2.12 v ss this is the ground potential pin. 2.2.13 v pp (flash memory versions only) this is a pin for flash memory programming mode setting and high-voltage application for program write/verify. connect directly to v ss in the normal operation mode. 2.2.14 ic (mask rom versions only) the ic (internally connected) pin is provided to set the test mode to check the 78k0/kb1 series at shipment. connect it directly to v ss with the shortest possible wire in the normal operation mode. when a potential difference is produced between the ic pin and the v ss pin because the wiring between these two pins is too long or external noise is input to the ic pin, the user?s program may not operate normally. ? connect the ic pin directly to v ss . as short as possible ic v ss
chapter 2 pin functions preliminary user ? s manual u15836ej2v1ud 41 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the types of pin i/o circuit and the recommended connections of unused pins. refer to figure 2-1 for the configuration of the i/o circuits of each type. table 2-1. pin i/o circuit types pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 p01/ti010/to00 p02 p03 p10/sck10/txd0 note p11/si10/rxd0 note 8-a p12/so10 p13/txd6 5-a p14/rxd6 8-a p15/toh0 5-a p16/toh1/intp5 p17/ti50/to50 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p20/ani0 to p23/ani3 9-c input connect to v dd or v ss . p30/intp1 to p33/intp4 input: independently connect to v ss via a resistor. output: leave open. p120/intp0 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p130 3-c output leave open. reset 2 input ? av ref ? input connect to v dd . av ss ?? connect to v ss . ic v pp ?? connect directly to v ss . note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103.
chapter 2 pin functions preliminary user ? s manual u15836ej2v1ud 42 figure 2-1. pin i/o circuit list type 3-c type 2 type 8-a type 5-a type 9-c schmitt-triggered input with hysteresis characteristics in pullup enable data output disable v dd p-ch v dd p-ch in/out n-ch v dd p-ch n-ch data out in comparator v ref (threshold voltage) av ss p-ch n-ch input enable + ? pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch
preliminary user?s manual u15836ej2v1ud 43 chapter 3 cpu architecture 3.1 memory space products in the 78k0/kb1 series can each access a 64 kb memory space. figures 3-1 to 3-4 show the memory maps. caution regardless of the internal memory capacity, the initial values of internal memory size switching register (ims) of all products in the 78k0/kb1 series are fixed (cfh). therefore, set the value corresponding to each product as indicated below. table 3-1. internal memory size switching register (ims) set value internal memory size switching register (ims) pd780101 42h pd780102 04h pd780103 06h pd78f0103 value corresponding to mask rom product
chapter 3 cpu architecture preliminary user?s manual u15836ej2v1ud 44 figure 3-1. memory map ( pd780101) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits general-purpose registers 32 8 bits reserved internal rom 8192 8 bits program memory space data memory space vector table area h callt table area program area callf entry area program area 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 1 h 0 0 0 0 h f f f 1 h 0 0 0 2 h f f c f h 0 0 d f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 45 figure 3-2. memory map ( pd780102) special function registers (sfr) 256 8 bits internal high-speed ram 768 8 bits general-purpose registers 32 8 bits reserved internal rom 16384 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area h 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 3 h 0 0 0 0 h f f f 3 h 0 0 0 4 h f f b f h 0 0 c f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 46 figure 3-3. memory map ( pd780103) special function registers (sfr) 256 8 bits internal high-speed ram 768 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area h 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 5 h 0 0 0 0 h f f f 5 h 0 0 0 6 h f f b f h 0 0 c f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 47 figure 3-4. memory map ( pd78f0103) special function registers (sfr) 256 8 bits internal high-speed ram 768 8 bits general-purpose registers 32 8 bits reserved flash memory 24576 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area h 0 0 0 0 h f 3 0 0 h 0 4 0 0 h f 7 0 0 h 0 8 0 0 h f f 7 0 h 0 0 8 0 h f f f 0 h 0 0 0 1 h f f f 5 h 0 0 0 0 h f f f 5 h 0 0 0 6 h f f b f h 0 0 c f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 48 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/kb1 series products incorporate internal rom (or flash memory), as shown below. table 3-2. internal memory capacity internal rom part number structure capacity pd780101 8192 8 bits (0000h to 1fffh) pd780102 16384 8 bits (0000h to 3fffh) pd780103 mask rom 24576 8 bits (0000h to 5fffh) pd78f0103 flash memory 24576 8 bits (0000h to 5fffh) the internal program memory space is divided into the following areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the program start addresses for branch upon reset input or generation of each interrupt request are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 3-3. vector table vector table address interrupt source vector table address interrupt source 0000h reset input 0016h intst6 0004h intlvi 0018h intcsi10/intst0 note 0006h intp0 001ah inttmh1 0008h intp1 001ch inttmh0 000ah intp2 001eh inttm50 000ch intp3 0020h inttm000 000eh intp4 0022h inttm010 0010h intp5 0024h intad 0012h intsre6 0026h intsr0 note 0014h intsr6 note available only in the pd780102, 780103, and 78f0103. (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf).
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 49 3.1.2 internal data memory space 78k0/kb1 series products incorporate the following internal high-speed ram. table 3-4. internal high-speed ram capacity part number internal high-speed ram pd780101 512 8 bits (fd00h to feffh) pd780102 pd780103 pd78f0103 768 8 bits (fc00h to feffh) the 32-byte area fee0h to feffh is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. the internal high-speed ram can also be used as a stack memory. 3.1.3 special function register (sfr) area on-chip peripheral hardware special function registers (sfrs) are allocated in the area ff00h to ffffh (refer to table 3-5 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned.
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 50 3.1.4 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. the address of the instruction to be executed next is addressed by the program counter (pc) (for details, refer to 3.3 instruction address addressing ). several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78k0/kb1 series, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. data memory addressing is illustrated in figures 3-5 to 3-8. for details of each addressing mode, refer to 3.4 operand address addressing . figure 3-5. data memory addressing ( pd780101) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 512 8 bits general-purpose registers 32 8 bits reserved internal rom 8192 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 1 h 0 0 0 2 h f f c f h 0 0 d f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 51 figure 3-6. data memory addressing ( pd780102) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 768 8 bits general-purpose registers 32 8 bits reserved internal rom 16384 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 3 h 0 0 0 4 h f f b f h 0 0 c f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 52 figure 3-7. data memory addressing ( pd780103) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 768 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing h 0 0 0 0 h f f f 5 h 0 0 0 6 h f f b f h 0 0 c f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 53 figure 3-8. data memory addressing ( pd78f0103) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 768 8 bits general-purpose registers 32 8 bits reserved register addressing direct addressing register indirect addressing based addressing based indexed addressing flash memory 24576 8 bits h 0 0 0 0 h f f f 5 h 0 0 0 6 h f f b f h 0 0 c f h f d e f h 0 e e f h f f e f h 0 0 f f h f f f f h f 1 e f h 0 2 e f h f 1 f f h 0 2 f f
chapter 3 cpu architecture preliminary user?s manual u15836ej2v1ud 54 3.2 processor registers the 78k0/kb1 series products incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-9. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-10. format of program status word 70 psw ie z rbs1 ac rbs0 0 isp cy
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 55 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to the interrupt disabled (di) state, and only non-maskable interrupt request becomes acknowledgeable. other interrupt requests are all disabled. when 1, the ie is set to the interrupt enabled (ei) state and interrupt request acknowledge enable is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupts request specified with a priority specification flag register (pr0l, pr0h, pr1l) (refer to 14.3 (3) priority specification flag registers (pr0l, pr0h, pr1l) ) are disabled for acknowledgement. when it is 1, all interrupts are acknowledgeable. actual request acknowledgement is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area.
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 56 figure 3-11. stack pointer format 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 3-12 and 3-13. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-12. data to be saved to stack memory interrupt and brk instructions psw pc15-pc8 pc15-pc8 pc7-pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7-pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 figure 3-13. data to be restored from stack memory reti and retb instructions psw pc15-pc8 pc15-pc8 pc7-pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7-pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 57 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each registers can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-14. configuration of general-purpose registers (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 58 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. sfrs are allocated in the ff00h to ffffh area. the special function registers can be manipulated like the general-purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-5 gives a list of the special function registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0, and is defined by the header file ? sfrbit.h ? in the cc78k0. when using the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special function register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset input.
chapter 3 cpu architecture preliminary user?s manual u15836ej2v1ud 59 table 3-5. special function register list (1/3) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 r/w ?? 00h ff01h port 1 p1 r/w ?? 00h ff02h port 2 p2 r ?? 00h ff03h port 3 p3 r/w ?? 00h ff08h ff09h a/d conversion result register adcr r ?? 0000h ff0ah receive buffer register 6 rxb6 r ?? ffh ff0bh transmit buffer register 6 txb6 r/w ?? ffh ff0ch port 12 p12 r/w ?? 00h ff0dh port 13 p13 r/w ?? 00h ff0fh serial i/o shift register 10 sio10 r ?? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ?? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ?? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ?? 0000h ff16h 8-bit timer counter 50 tm50 r ?? 00h ff17h 8-bit timer compare register 50 cr50 r/w ?? 00h ff18h 8-bit timer h compare register 00 cmp00 r/w ?? 00h ff19h 8-bit timer h compare register 10 cmp10 r/w ?? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ?? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ?? 00h ff20h port mode register 0 pm0 r/w ?? ffh ff21h port mode register 1 pm1 r/w ?? ffh ff23h port mode register 3 pm3 r/w ?? ffh ff28h a/d converter mode register adm r/w ?? 00h ff29h analog input channel specification register ads r/w ?? 00h ff2ah power-fail comparison mode register pfm r/w ?? 00h ff2bh power-fail comparison threshold register pft r/w ?? 00h ff2ch port mode register 12 pm12 r/w ?? ffh ff30h pull-up resistor option register 0 pu0 r/w ?? 00h ff31h pull-up resistor option register 1 pu1 r/w ?? 00h ff33h pull-up resistor option register 3 pu3 r/w ?? 00h ff3ch pull-up resistor option register 12 pu12 r/w ?? 00h ff48h external interrupt rising edge enable register egp r/w ?? 00h ff49h external interrupt falling edge enable register egn r/w ?? 00h ff4fh input switch control register isc r/w ?? 00h
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 60 table 3-5. special function register list (2/3) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff50h asynchronous serial interface operation mode register 6 asim6 r/w ?? 01h ff53h asynchronous serial interface reception error status register 6 asis6 r ?? 00h ff55h asynchronous serial interface transmission status register 6 asif6 r ?? 00h ff56h clock selection register 6 cksr6 r/w ?? 00h ff57h baud rate generator control register 6 brgc6 r/w ?? ffh ff58h asynchronous serial interface control register 6 asicl6 r/w ?? 16h ff69h 8-bit timer h mode register 0 tmhmd0 r/w ?? 00h ff6ah timer clock selection register 50 tcl50 r/w ?? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ?? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ?? 00h ff70h asynchronous serial interface operation mode register 0 note 1 asim0 r/w ?? 01h ff71h baud rate generator control register 0 note 1 brgc0 r/w ?? 1fh ff72h receive buffer register 0 note 1 rxb0 r ?? ffh ff73h asynchronous serial interface reception error status register 0 note 1 asis0 r ?? 00h ff74h transmit shift register 0 note 1 txs0 w ?? ffh ff80h serial operation mode register 10 csim10 r/w ?? 00h ff81h serial clock selection register 10 csic10 r/w ?? 00h ff84h transmit buffer register 10 sotb10 r/w ?? undefined ff98h watchdog timer mode register wdtm r/w ?? 67h ff99h watchdog timer enable register wdte r/w ?? 9ah ffa0h ring-osc mode register rcm r/w ?? 00h ffa1h main clock mode register mcm r/w ?? 00h ffa2h main osc control register moc r/w ?? 00h ffa3h oscillation stabilization time counter status register ostc r ?? 00h ffa4h oscillation stabilization time select register osts r/w ?? 05h ffa9h clock monitor mode register clm r/w ?? 00h ffach reset control flag register resf r ?? 00h note 2 ffbah 16-bit timer mode control register 00 tmc00 r/w ?? 00h ffbbh prescaler mode register 00 prm00 r/w ?? 00h notes 1. pd780102, 780103, and 78f0103 only. 2. this value varies depending on the reset source.
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 61 table 3-5. special function register list (3/3) manipulatable bit unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffbch capture/compare control register 00 crc00 r/w ?? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ?? 00h ffbeh low-voltage detection register lvim r/w ?? 00h ffbfh low-voltage detection level selection register lvis r/w ?? 00h ffe0h interrupt request flag register 0l if0 if0l r/w ?? 00h ffe1h interrupt request flag register 0h if0h r/w ? 00h ffe2h interrupt request flag register 1l 1f1l r/w ?? 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ?? ffh ffe5h interrupt mask flag register 0h mk0h r/w ? ffh ffe6h interrupt mask flag register 1l mk1l r/w ?? ffh ffe8h priority specification flag register 0l pr0 pr0l r/w ?? ffh ffe9h priority specification flag register 0h pr0h r/w ? ffh ffeah priority specification flag register 1l pr1l r/w ?? ffh fff0h internal memory size switching register note ims r/w ?? cfh fffbh processor clock control register pcc r/w ?? 00h note the default value of ims is fixed (cfh) in all products in the 78k0/kb1 series regardless of the internal memory capacity. therefore, set the following value to each product. internal memory size switching register (ims) pd780101 42h pd780102 04h pd780103 06h pd78f0103 value corresponding to mask rom version
chapter 3 cpu architecture preliminary user?s manual u15836ej2v1ud 62 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relative branching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ...
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 63 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10 ? 8 11 10 00001 643 callf fa 7 ? 0
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 64 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 ? 0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture preliminary user?s manual u15836ej2v1ud 65 3.4 operand address addressing the following various methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/kb1 series instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 66 3.4.2 register addressing [function] the general-purpose register to be specified is accessed as an operand with the register specify code (rn and rpn) of an instruction word in the registered bank specified with the register bank select flag (rbs0 to rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ? r ? and ? rp ? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 67 3.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 68 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing sfrs to be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] shown below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (s addr-offset) 01010000 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 69 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 70 3.4.6 register indirect addressing [function] register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory to be manipulated. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 71 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000
chapter 3 cpu architecture preliminary user ? s manual u15836ej2v1ud 72 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be addressed. [description example] in the case of push de operation code 10110101
preliminary user?s manual u15836ej2v1ud 73 chapter 4 port functions 4.1 port functions 78k0/kb1 series products are provided with the ports shown in figure 4-1, which enable variety of control operations. the functions of each port are shown in table 4-1. in addition to the function as digital i/o ports, these ports have several alternate functions. for details of the alternate functions, refer to chapter 2 pin functions . figure 4-1. port types p30 port 3 p33 p23 port 12 p120 port 2 p00 port 0 p03 p10 port 1 p17 p20 port 13 p130
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 74 table 4-1. port functions pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p10 sck10/txd0 note p11 si10/rxd0 note p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p23 input port 2. 4-bit input-only port. input ani0 to ani3 p30 to p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp1 to intp4 p120 i/o port 12. 1-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103. 4.2 port configuration a port consists of the following hardware. table 4-2. port configuration item configuration control registers port mode register (pm0, pm1, pm3, pm12) pull-up resistor option register (pu0, pu1, pu3, pu12) input switch control register (isc) port total: 22 (cmos i/o: 17, cmos input: 4, cmos output: 1) pull-up resistor total: 22 (software control only)
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 75 4.2.1 port 0 port 0 is a 4-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p03 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o. reset input sets port 0 to input mode. figures 4-2 to 4-4 show block diagrams of port 0. figure 4-2. block diagram of p00 p00/ti000 wr pu rd wr port wr pm pu00 alternate function output latch (p00) pm00 v dd p-ch selector internal bus pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 76 figure 4-3. block diagram of p01 p01/ti010/to00 wr pu rd wr port wr pm pu01 alternate function output latch (p01) pm01 alternate function v dd p-ch selector internal bus pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 77 figure 4-4. block diagram of p02 and p03 wr pu rd wr port wr pm pu02, pu03 output latch (p02, p03) pm02, pm03 v dd p-ch p02, p03 selector internal bus pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 78 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. reset input sets port 1 to input mode. figures 4-5 to 4-10 show block diagrams of port 1. caution when using p10/sck10 (/txd0 note ), p11/si10 (/rxd0 note ), and p12/so10 as general-purpose ports, do not write to serial clock selection register 10 (csic10). figure 4-5. block diagram of p10 p10/sck10 (/txd0 note ) wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 alternate function v dd p-ch selector internal bus note available only in the pd780102, 780103, and 78f0103. pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 79 figure 4-6. block diagram of p11 and p14 p11/si10 (/rxd0 note ), p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 v dd p-ch selector internal bus note available only in the pd780102, 780103, and 78f0103. pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 80 figure 4-7. block diagram of p12 p12/so10 wr pu rd wr port wr pm pu12 output latch (p12) pm12 alternate function v dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 81 figure 4-8. block diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 alternate function v dd p-ch internal bus selector pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 82 figure 4-9. block diagram of p15 p15/toh0 wr pu rd wr port wr pm pu15 output latch (p15) pm15 alternate function v dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 83 figure 4-10. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 alternate function v dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 84 4.2.3 port 2 port 2 is a 4-bit input-only port. this port can also be used for a/d converter analog input. figure 4-11 shows a block diagram of port 2. figure 4-11. block diagram of p20 to p23 v ref rd a/d converter p20/ani0 to p23/ani3 + ? internal bus rd: port 2 read signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 85 4.2.4 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p33 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input. reset input sets port 3 to input mode. figure 4-12 shows a block diagram of port 3. figure 4-12. block diagram of p30 to p33 p30/intp1 to p33/intp4 wr pu rd wr port wr pm pu30 to pu33 alternate function output latch (p30 to p33) pm30 to pm33 v dd p-ch selector internal bus pu3: pull-up resistor option register 3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 86 4.2.5 port 12 port 12 is a 1-bit i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when the p120 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used for external interrupt input. reset input sets port 12 to input mode. figure 4-13 shows a block diagram of port 12. figure 4-13. block diagram of p120 p120/intp0 wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 v dd p-ch selector internal bus pu12: pull-up resistor option register 12 pm: port mode register rd: port 12 read signal wr: port 12 write signal
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 87 4.2.6 port 13 port 13 is a 1-bit output-only port. figure 4-14 shows a block diagram of port 13. figure 4-14. block diagram of p130 rd output latch (p130) wr port p130 internal bus rd: port 13 read signal wr: port 13 write signal 4.3 registers controlling port function port functions are controlled by the following three types of registers. ? port mode registers (pm0, pm1, pm3, pm12) ? pull-up resistor option registers (pu0, pu1, pu3, pu12) ? input switch control register (isc) (1) port mode registers (pm0, pm1, pm3, and pm12) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch as shown in table 4-3. caution because p16, p30 to p33, and p120 can also be used as external interrupt input pins, when port function output mode is specified to change the output level, the interrupt request flag is set. therefore, when these pins are used in output mode, preset the interrupt mask flags (pmk0 to pmk5) to 1.
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 88 figure 4-15. format of port mode register symbol76543210addressafter resetr/w pm0 1 1 1 1 pm03 pm02 pm01 pm00 ff20h ffh r/w pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm121111111pm120ff2chffhr/w pmmn pmn pin i/o mode selection (m = 0, 1, 3, 12; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 89 table 4-3. settings of port mode register and output latch when alternate-function is used alternate function pin name name i/o pm p p00 ti000 input 1 ti010 input 1 p01 to00 output 0 0 input 1 sck10 output 0 1 p10 txd0 note output 0 1 si10 input 1 p11 rxd0 note input 1 p12 so10 output 0 0 p13 txd6 output 0 1 p14 rxd6 input 1 p15 toh0 output 0 0 toh1 output 0 0 p16 intp5 input 1 ti50 input 1 p17 to50 output 0 0 p30 to p33 intp1 to intp4 input 1 p120 intp0 input 1 note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103. remark :don ? t care pm : port mode register p : port output latch
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 90 (2) pull-up resistor option registers (pu0, pu1, pu3, and pu12) these registers specify whether the on-chip pull-up resistors of p00 to p03, p10 to p17, p30 to p33, or p120 is to be used or not. an on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. on-chip pull-up resistor cannot be used for bits set to output mode and bits used as alternate-function output pins, regardless of the settings of pu0, pu1, pu3 and pu12. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 4-16. format of pull-up resistor option register symbol76543210addressafter resetr/w pu0 0 0 0 0 pu03 pu02 pu01 pu00 ff30h 00h r/w 76543210 pu1 pu17 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 76543210 pu3 0 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w 76543210 pu120000000pu120ff3ch00hr/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 12; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
chapter 4 port functions preliminary user?s manual u15836ej2v1ud 91 (3) input switch control register (isc) this register is used to receive a status signal transmitted from the master during lin (local interconnect network) reception. the input signal is switched by setting isc. for the port configuration during lin reception, refer to figure 12-3 port configuration for lin reception operation in chapter 12 serial interface uart6 . this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 4-17. format of input switch control register (isc) address: ff4fh after reset: 00h r/w symbol76543210 isc 0 0 0 0 0 0 isc1 isc0 isc1 input signal selection 0 ti000/p00 input 1 rxd6/p14 input isc0 input signal selection 0 intp0/p120 input 1 rxd6/p14 input
chapter 4 port functions preliminary user ? s manual u15836ej2v1ud 92 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit. 4.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
preliminary user?s manual u15836ej2v1ud 93 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two system clock oscillators are available. ? x1 oscillator the x1 oscillator oscillates a clock of 2.0 to 10.0 mhz. oscillation can be stopped by executing the stop instruction or setting the main osc control register (moc). ? ring-osc oscillator the ring-osc oscillator oscillates a clock of 240 khz (typ.). oscillation can be stopped by setting the ring- osc mode register (rcm) when ?can be stopped by software? is set by a mask option and the x1 input clock is used as the cpu clock. 5.2 configuration of clock generator the clock generator consists of the following hardware. table 5-1. configuration of clock generator item configuration control registers processor clock control register (pcc) ring-osc mode register (rcm) main clock mode register (mcm) main osc control register (moc) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) oscillator x1 oscillator ring-osc oscillator
chapter 5 clock generator preliminary user?s manual u15836ej2v1ud 94 figure 5-1. block diagram of clock generator x1 x2 x1 oscillator f xp f x 2 2 internal bus ring-osc mode register (rcm) stop mstop main osc control register (moc) f x 2 3 f x 2 4 f x 2 3 internal bus ring-osc oscillator mask option 1: cannot be stopped 0. can be stopped rstop cpu clock (f cpu ) controller pcc1 pcc0 processor clock control register (pcc) pcc2 mcm0 mcs main clock mode register (mcm) osts1 osts0 osts2 x1 oscillation stabilization time counter oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 c p u oscillation stabilization time counter status register (ostc) f r clock to peripheral hardware prescaler operation clock switch f x 8-bit timer h1, watchdog timer prescaler prescaler selector
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 95 5.3 registers controlling clock generator the following six registers are used to control the clock generator. ? processor clock control register (pcc) ? ring-osc mode register (rcm) ? main clock mode register (mcm) ? main osc control register (moc) ? oscillation stabilization time counter status register (ostc) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) this register sets the division ratio of the cpu clock. pcc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-2. format of processor clock control register (pcc) address : fffbh after reset : 00h r/w symbol 76543210 pcc 0 0 0 0 0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 cpu clock selection (f cpu ) 000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 other setting prohibited
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 96 the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k0/kb1 series. therefore, the relationship between the cpu clock (f cpu ) and minimum instruction execution time is as shown in the table 5-2. table 5-2. relationship between cpu clock and minimum instruction execution time minimum instruction execution time: 2/f cpu cpu clock (f cpu ) note x1 input clock (at 10 mhz operation) ring-osc clock (at 240 khz (typ.) operation) f x 0.2 s8.3 s (typ.) f x /2 0.4 s 16.6 s (typ.) f x /2 2 0.8 s 33.2 s (typ.) f x /2 3 1.6 s 66.4 s (typ.) f x /2 4 3.2 s 132.8 s (typ.) note the main clock mode register (mcm) is used to set the cpu clock (x1 input clock/ring-osc clock) (see figure 5-4 ). (2) ring-osc mode register (rcm) this register sets the operation mode of ring-osc. this register is valid when ? can be stopped by software ? is set for ring-osc by a mask option, and the x1 input clock is input to the cpu clock. if ? cannot be stopped ? is selected for ring-osc by a mask option, settings for this register are invalid. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-3. format of ring-osc mode register (rcm) address : ffa0h after reset : 00h r/w symbol 76543210 rcm0000000rstop rstop ring-osc oscillating/stopped 0 ring-osc oscillating 1 ring-osc stopped caution make sure that the bit 1 (mcs) of the main clock mode register (mcm) is 1 before setting rstop.
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 97 (3) main clock mode register (mcm) this register sets the cpu clock. mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-4. format of main clock mode register (mcm) address : ffa1h after reset : 00h r/w symbol 76543210 mcm 0 0 0 0 0 0 mcs mcm0 mcs cpu clock status 0 operates with ring-osc clock 1 operates with x1 input clock mcm0 selection of clock supplied to cpu 0 ring-osc clock 1 x1 input clock caution when ring-osc clock is selected as the clock to be supplied to the cpu, the divided clock of the ring-osc clock oscillator output (f x ) is supplied to the peripheral hardware (f x = 240 khz (typ.)). operation of the peripheral hardware with ring-osc clock cannot be guaranteed. therefore, when ring-osc clock is selected as the clock supplied to the cpu, do not use peripheral hardware. in addition, stop the peripheral hardware before switching the clock supplied to the cpu from the x1 input clock to the ring-osc clock. note, however, that the following peripheral hardware can be used when the cpu operates on the ring-osc clock. ? ? ? ? watchdog timer ? ? ? ? clock monitor ? ? ? ? 8-bit timer h1 when f r /2 7 is selected as count clock ? ? ? ? peripheral hardware selecting external clock as the clock source
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 98 (4) main osc control register (moc) this register selects the operation mode of the x1 input clock. this register is used to stop the x1 input clock when the cpu is operating with the ring-osc clock. therefore, this register is valid only when the cpu is operating with the ring-osc clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-5. format of main osc control register (moc) address : ffa2h after reset : 00h r/w symbol 76543210 mocmstop0000000 mstop control of x1 input clock oscillation 0 x1 input clock oscillating 1 x1 input clock stopped caution make sure that the bit 1 (mcs) of the main clock mode register (mcm) is 0 before setting mstop. (5) oscillation stabilization time counter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. reset input, stop instruction, and mstop = 1 clear ostc to 00h. figure 5-6. format of oscillation stabilization time counter status register (ostc) address : ffa3h after reset : 00h r symbol 76543210 ostc 0 0 0 most11 most13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 100002 11 /f xp min. (204.8 s min.) 110002 13 /f xp min. (819.2 s min.) 111002 14 /f xp min. (1.64 ms min.) 111102 15 /f xp min. (3.27 ms min.) 111112 16 /f xp min. (6.55 ms min.) caution after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. remarks 1. values in parentheses are for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 99 (6) oscillation stabilization time select register (osts) this register is used to select the oscillation stabilization time of the x1 input clock when stop mode is released. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 5-7. format of oscillation stabilization time select register (osts) address : ffa4h after reset : 05h r/w symbol 76543210 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 0012 11 /f xp (204.8 s) 0102 13 /f xp (819.2 s) 0112 14 /f xp (1.64 ms) 1002 15 /f xp (3.27 ms) 1012 16 /f xp (6.55 ms) other setting prohibited cautions 1. if the stop mode is entered and then released while the ring-osc is being used as the cpu clock, set the oscillation stabilization time as follows. ? ? ? ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the setting value of osts can be initialized (to 05h) only by a reset. therefore, note that the x1 oscillation stabilization time counter counts up to the set value of osts after stop mode is released when the ring-osc is used as the cpu clock. 2. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. stop mode release x1 pin voltage waveform v ss a remarks 1. values in parentheses are for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 100 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates via a crystal resonator or ceramic resonator (standard: 10 mhz) connected to the x1 and x2 pins. an external clock can be input to the x1 oscillator. in this case, input the clock signal to the x1 pin and input the inverse signal to the x2 pin. figure 5-8 shows the external circuit of the x1 oscillator. figure 5-8. external circuit of x1 oscillator (a) crystal, ceramic oscillation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator external clock x1 x2
chapter 5 clock generator preliminary user?s manual u15836ej2v1ud 101 caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the figure 5-9 to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. figure 5-9 shows examples of incorrect resonator connection. figure 5-9. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 port (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 x2 p mn v dd ab c high current
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 102 figure 5-9. examples of incorrect resonator connection (2/2) (e) signals are fetched v ss x1 x2 5.4.2 ring-osc oscillator ring-osc is incorporated in the pd780101, 780102, 780103, and 78f0103. ? can be stopped by software ? or ? cannot be stopped ? can be selected by a mask option. the ring-osc clock always oscillates after reset release (240 khz (typ.)). 5.4.3 prescaler the prescaler generates various clocks by dividing the x1 oscillator output (f x ) when the x1 input clock is selected as the clock to be supplied to the cpu. caution when the ring-osc clock is selected as the clock supplied to the cpu, the prescaler generates various clocks by dividing the ring-osc oscillator (f x ) (f x = 240 khz (typ.)). 5.5 clock generator operation the clock generator generates the following clocks and controls the operation modes of the cpu, such as standby mode. ? x1 input clock f xp ? ring-osc clock f r ? cpu clock f cpu ? clock to peripheral hardware the ring-osc clock via the on-chip ring-osc oscillator is used as the cpu clock after reset release in the 78k0/kb1 series, thus enabling the following.
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 103 (1) enhancement of security function when the x1 input clock is set as the cpu clock by the default setting, the device cannot operate if the x1 input clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the on-chip ring-osc clock, so the device can be started by the ring-osc clock after reset release by the clock monitor (detection of x1 input clock stop). consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) improvement of performance because the cpu can be started without waiting for the x1 input clock oscillation stabilization time, the total performance can be improved. caution when writing to the flash memory while it is mounted on the board, the x1 input clock is selected as the default cpu clock. in this case, the oscillation stabilization time is 2 16 /f xp (s). a timing diagram of the cpu default start using ring-osc is shown in figure 5-10. figure 5-10. timing diagram of cpu default start using ring-osc ring-osc clock (f r ) cpu clock x1 input clock (f xp ) operation stopped: 17/f r x1 oscillation stabilization time: 2 11 /f xp to 2 16 /f xp note reset ring-osc clock x1 input clock switched by software note check using the oscillation stabilization time counter status register (ostc). (a) when the reset signal is generated, bit 0 of the main clock mode register (mcm) is set to 0 and the ring- osc clock is set as the cpu clock. however, the cpu clock is stopped for 17 clocks of the ring-osc clock after reset signal generation. while inputting a low level to the reset pin, oscillation of the x1 input clock and ring-osc clock is stopped. (b) after reset signal generation, the cpu clock can be switched from the ring-osc clock to the x1 input clock using bit 0 (mcm0) of the main clock mode register (mcm) after the x1 input clock oscillation stabilization time has elapsed. at this time, check the oscillation stabilization time using the oscillation stabilization time counter status register (ostc) before switching the cpu clock. the cpu clock status can be checked using bit 1 (mcs) of mcm. (c) ring-osc can be set to stopped/oscillating using the ring-osc mode register (rcm) when ? can be stopped by software ? is selected for the ring-osc by a mask option, if the x1 input is used as the cpu clock. make sure that mcs is 1 at this time.
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 104 (d) when ring-osc is used as the cpu clock, the x1 input clock can be set to stopped/oscillating using the main osc control register (moc). make sure that mcs is 0 at this time. (e) select the x1 input clock oscillation stabilization time (2 11 /f xp , 2 13 /f xp , 2 14 /f xp , 2 15 /f xp , 2 16 /f xp ) using the oscillation stabilization time select register (osts) when releasing stop mode while x1 input clock is being used as the cpu clock. in addition, when releasing stop mode while reset is released and ring-osc clock is being used as the cpu clock, check the x1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc). a status transition diagram of this product is shown in figure 5-11, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in tables 5-3 and 5-4, respectively. figure 5-11. status transition diagram (1/2) (1) when ? ring-osc can be stopped by software ? is selected by mask option status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt reset release interrupt interrupt halt instruction stop instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction halt instruction stop note 4 reset note 5 notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (ostc). 3. when shifting from status 2 to status 1, make sure that mcs is 0. 4. when ? ring-osc can be stopped by software ? is selected by a mask option, the watchdog timer stops operating in the halt and stop modes, regardless of the source clock of the watchdog timer. however, oscillation of ring-osc does not stop even in the halt and stop modes if rstop = 0. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 105 figure 5-11. status transition diagram (2/2) (2) when ? ring-osc cannot be stopped ? is selected by mask option status 3 cpu clock: f xp f xp : oscillating f r : oscillating halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 4 status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (ostc). 2. when shifting from status 2 to status 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ? ring-osc cannot be stopped ? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using the tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an internal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 5 clock generator preliminary user?s manual u15836ej2v1ud 106 table 5-3. relationship between operation clocks in each operation status ring-osc oscillator prescaler clock supplied to peripherals note 2 status operation mode x1 oscillator note 1 rstop = 0 rstop = 1 cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating oscillating oscillating stopped note 4 ring-osc x1 caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. notes 1. when ?cannot be stopped? is selected for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. remark rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) table 5-4. oscillation control flags and clock oscillation status x1 input clock ring-osc clock rstop = 0 stopped oscillating mstop = 1 rstop = 1 setting prohibited rstop = 0 oscillating mstop = 0 rstop = 1 oscillating stopped caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) rstop: bit 0 of the ring-osc mode register (rcm)
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 107 5.6 time required to switch between ring-osc clock and x1 input clock bit 0 (mcm0) of the main clock mode register (mcm) is used to switch between the ring-osc clock and x1 input clock. in the actual switching operation, switching does not occur immediately after mcm0 rewrite; several instructions are executed using the pre-switch clock after switching mcm0 (see table 5-5 ). bit 1 (mcs) of mcm is used to judge that operation is performed using either the ring-osc clock or x1 input clock. to stop the clock, wait for the number of clocks shown in table 5-5 before stopping. table 5-5. maximum time required to switch between ring-osc clock and x1 input clock pcc maximum time required for switching pcc2 pcc1 pcc0 x1 ring-osc ring-osc x1 000f xp /120,000 + 1 clock 001f xp /240,000 + 1 clock 010f xp /480,000 + 1 clock 011f xp /960,000 + 1 clock 100f xp /1,920,000 + 1 clock 2 clocks remarks 1. pcc: processor clock control register 2. f xp : x1 input clock oscillation frequency 3. f r : ring-osc clock oscillation frequency 4. the maximum time is the number of clocks of the cpu clock before switching.
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 108 5.7 clock selection flowchart and register settings 5.7.1 changing to x1 input clock from ring-osc clock figure 5-12. changing to x1 input clock from ring-osc clock (flowchart) after releasing reset processing pcc setting mcm.0 1 x1 input clock operation ostc check note ;checking x1 oscillation stabilization time status pcc = 00h rcm = 00h mcm = 00h moc = 00h ostc = 00h osts = 05h note ;f cpu = f r ;ring-osc oscillation ;ring-osc clock operation ;x1 oscillation ;oscillation stabilization time status register ;oscillation stabilization time fx/2 16 default value of register after reset ring-osc clock operation x1 input clock operation before lapse of x1 oscillation stabilization time lapse of x1 oscillation stabilization time ring-osc clock operation (division operation of set pcc) mcm.1 (mcs) changes from 0 to 1. note check the oscillation stabilization time of the x1 oscillation circuit using the ostc register after the reset signal has been released and select the x1 input clock operation after the lapse of specified oscillation stabilization time. setting the osts register is valid only when the stop mode has been released with the system operating on the x1 input clock.
chapter 5 clock generator preliminary user ? s manual u15836ej2v1ud 109 5.7.2 changing from x1 input clock to ring-osc clock figure 5-13. changing from x1 input clock to ring-osc clock (flowchart) mcm0 0 ring-osc clock operation ;ring-osc clock operation mcm = 03h ;x1 input clock operation rstop = 0 rcm.0 note (rstop) = 1? no:rstop = 0 x1 input clock operation ring-osc clock operation mcm.1 (mcs) changes from 1 to 0. register setting with x1 input clock yes:rstop = 1 ;ring-osc oscillation? note this is necessary only when ? clock can be stopped by software ? is selected for ring-osc by mask option.
chapter 5 clock generator preliminary user?s manual u15836ej2v1ud 110 5.7.3 register settings table 5-6. clock and register settings setting flag status flag mcm register moc register rcm register mcm register f cpu mode mcm0 mstop rstop note 1 mcs ring-osc oscillating 1 0 0 1 x1 input clock note 2 ring-osc stopped 1 0 1 1 x1 oscillating 0 0 0 0 ring-osc clock x1 stopped 0 1 0 0 notes 1. this is valid only when ?clock can be stopped by software? is selected for ring-osc by mask option. 2. do not set mstop to 1 during x1 input clock operation (oscillation of x1 is not stopped even when mstop = 1).
preliminary user?s manual u15836ej2v1ud 111 chapter 6 16-bit timer/event counter 00 6.1 functions of 16-bit timer/event counter 00 16-bit timer/event counter 00 has the following functions. ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square-wave output (1) interval timer tm00 generates an interrupt request at the preset time interval. (2) ppg output tm00 can output a rectangular wave whose frequency and output pulse width can be set freely. (3) pulse width measurement tm00 can measure the pulse width of an externally input signal. (4) external event counter tm00 can measure the number of pulses of an externally input signal. (5) square-wave output tm00 can output a square wave with any selected frequency.
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u15836ej2v1ud 112 6.2 configuration of 16-bit timer/event counter 00 16-bit timer/event counter 00 consists of the following hardware. table 6-1. configuration of 16-bit timer/event counter 00 item configuration timer counter 16 bits 1 (tm00) register 16-bit timer capture/compare register: 16 bits 2 (cr000, cr010) timer output 1 (to00) control registers 16-bit timer mode control register 00 (tmc00) capture/compare control register 00 (crc00) 16-bit timer output control register 00 (toc00) prescaler mode register 00 (prm00) port mode register 0 (pm0) note note see figure 4-2 block diagram of p00 and figure 4-3 block diagram of p01 . figure 6-1 shows the block diagram. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 f x f x /2 2 f x /2 8 f x ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p01 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 113 (1) 16-bit timer counter 00 (tm00) tm00 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmc003 and tmc002 are cleared <3> if the valid edge of ti000 is input in the clear & start mode entered by inputting the valid edge of ti000 <4> if tm00 and cr000 match in the clear & start mode entered on a match of tm00 and cr000 (2) 16-bit timer capture/compare register 000 (cr000) cr000 is a 16-bit register that has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc000) of capture/compare control register 00 (crc000). ? ? ? ? when cr000 is used as a compare register the value set in cr000 is constantly compared with the 16-bit timer counter 00 (tm00) count value, and an interrupt request (inttm000) is generated if they match. it can also be used as the register that holds the interval time when tm00 is set to interval timer operation. ? ? ? ? when cr000 is used as a capture register it is possible to select the valid edge of the ti000/p00 pin or the ti010/to00/p01 pin as the capture trigger. the ti000 or ti010 valid edge is set using prescaler mode register 00 (prm00). if the capture trigger is specified to be the valid edge of the ti000/p00 pin, the situation is as shown in table 6- 2. on the other hand, when the capture trigger is specified to be the valid edge of the ti010/to00/p01 pin, the situation is as shown in table 6-3. table 6-2. ti000/p00 pin valid edge and cr000, cr010 capture trigger es001 es000 ti000/p00 pin valid edge cr000 capture trigger cr010 capture trigger 0 0 falling edge rising edge falling edge 0 1 rising edge falling edge rising edge 1 0 setting prohibited setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation both rising and falling edges table 6-3. ti010/to00/p01 pin valid edge and cr000 capture trigger es101 es100 ti010/to00/p01 pin valid edge cr000 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u15836ej2v1ud 114 cr000 can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. cautions 1. set a value other than 0000h in cr000 in the clear & start made entered on a match of tm00 and cr000. however, in the free-running mode and in the clear mode using the valid edge of ti000, if cr000 is set to 0000h, an interrupt request (inttm000) is generated following overflow (ffffh). 2. if the changed value of cr000 is smaller than the value of 16-bit timer counter 00 (tm00), tm00 continues counting and starts counting again from 0 after overflow. therefore, if the value of cr000 after the change is smaller than before the change, the timer should be restarted after cr000 is changed. 3. when p01 is used as the valid edge of ti010, it cannot be used as the timer output (to00). moreover, when p01 is used as to00, it cannot be used as the valid edge of ti010. 4. when cr000 is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. 5. do not rewrite cr000 during tm00 operation. (3) 16-bit timer capture/compare register 010 (cr010) cr010 is a 16-bit register that has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc002) of capture/compare control register 00 (crc00). ? ? ? ? when cr010 is used as a compare register the value set in the cr010 is constantly compared with the 16-bit timer counter 00 (tm00) count value, and an interrupt request (inttm010) is generated if they match. ? ? ? ? when cr010 is used as a capture register it is possible to select the valid edge of the ti000/p00 pin as the capture trigger. the ti000/p00 valid edge is set by prescaler mode register 00 (prm00). cr010 can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. cautions 1. set cr010 to other than 0000h. this means a 1-pulse count operation cannot be performed when cr010 is used as the event counter. however, in the free-running mode and in the clear mode using the valid edge of ti000, if cr010 is set to 0000h, an interrupt request (inttm010) is generated following overflow (ffffh). 2. when cr010 is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. 3. cr010 can be rewritten during tm00 operation. for details, refer to remark 2 in figure 6-10.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 115 6.3 registers controlling 16-bit timer/event counter 00 the following five registers are used to control the 16-bit timer/event counter. ? 16-bit timer mode control register 00 (tmc00) ? capture/compare control register 00 (crc00) ? 16-bit timer output control register 00 (toc00) ? prescaler mode register 00 (prm00) ? port mode register 0 (pm0) (1) 16-bit timer mode control register 00 (tmc00) this register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (tm00) clear mode, and output timing, and detects an overflow. tmc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc00 to 00h. caution 16-bit timer counter 00 (tm00) starts operation at the moment tmc002 and tmc003 are set to values other than 0, 0 (operation stop mode), respectively. set tmc002 and tmc003 to 0, 0 to stop the operation.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 116 figure 6-2. format of 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 tmc001 0 ovf00 symbol tmc00 address ffbah after reset: 00h r/w tmc003 tmc002 tmc001 operating mode and clear mode selection to00 output timing selection interrupt request generation 000 001 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 011 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 100 101 clear & start entered on ti000 valid edge ? 1 1 0 clear & start entered on match between tm00 and cr000 match between tm00 and cr000 or match between tm00 and cr010 1 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge generated on match between tm00 and cr000, or match between tm00 and cr010 ovf00 16-bit timer counter 00 (tm00) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf00 flag. 2. set the valid edge of the ti000/p00 pin using prescaler mode register 00 (prm00). 3. if clear & start mode entered on match between tm00 and cr000 is selected, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. remark to00: 16-bit timer/event counter output pin ti000: 16-bit timer/event counter input pin tm00: 16-bit timer counter 00 cr000: 16-bit timer capture/compare register 000 cr010: 16-bit timer capture/compare register 010
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 117 (2) capture/compare control register 00 (crc00) this register controls the operation of the 16-bit capture/compare registers (cr000, cr010). crc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0 to 00h. figure 6-3. format of capture/compare control register 00 (crc00) address: ffbch after reset: 00h r/w symbol76543210 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 1 captures on valid edge of ti000 by reverse phase crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc00. 2. when clear & start mode entered on a match between tm00 and cr000 is selected with 16-bit timer mode control register 00 (tmc00), cr000 should not be specified as a capture register. 3. if both the rising and falling edges have been selected as the valid edges of ti000, capture is not performed. 4. to ensure that the capture operation is performed properly, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 00 (prm00).
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u15836ej2v1ud 118 (3) 16-bit timer output control register 00 (toc00) this register controls the operation of the 16-bit timer/event counter 00 output controller. it sets/resets the r-s type flip-flop (lv00), and enables/disables output inversion and 16-bit timer/event counter 00 timer output. toc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc00 to 00h. figure 6-4 shows the format of toc00. figure 6-4. format of 16-bit timer output control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol76543210 toc00 0 0 0 toc004 lvs00 lvr00 toc001 toe00 toc004 timer output f/f control by match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 16-bit timer/event counter timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control by match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 16-bit timer/event counter output control 0 disables output (output set to level 0) 1 enables output cautions 1. timer operation must be stopped before setting other than toc004. 2. if lvs00 and lvr00 are read after data is set, 0 is read. 3. be sure to set bits 5 and 6 to 0.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 119 (4) prescaler mode register 00 (prm00) this register is used to set the 16-bit timer counter 00 (tm00) count clock and ti000 and ti010 input valid edges. prm00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears prm00 to 00h. figure 6-5. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol76543210 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection 00f x (10 mhz) 01f x /2 2 (2.5 mhz) 10f x /2 8 (39.06 khz) 1 1 ti000 valid edge note note the external clock requires a pulse two times longer than internal clock (f x ). cautions 1. if the valid edge of ti000 is to be set for the count clock, do not set the clear & start mode and the capture trigger using the valid edge of ti000. 2. always set data to prm00 after stopping the timer operation. 3. if the ti000 or ti010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to enable the operation of 16-bit timer counter 00 (tm00). care is therefore required when pulling up the ti000 or ti010 pin. however, when re- enabling operation after the operation has been stopped once, the rising edge is not detected. 4. when p01 is used as the ti010 valid edge, it cannot be used as the timer output (to00), and when used as to00, it cannot be used as the ti010 valid edge. remarks 1 .f x : x1 input clock oscillation frequency 2. ti000, ti010: 16-bit timer/event counter input pin 3. figures in parentheses are for operation with f x = 10 mhz.
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u15836ej2v1ud 120 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 pin for timer output, set pm01 and the output latch of p01 to 0. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 to ffh. figure 6-6. format of port mode register 0 (pm0) 7 1 6 1 5 1 4 1 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 3) output mode (output buffer on) input mode (output buffer off)
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 121 6.4 operation of 16-bit timer/event counter 00 6.4.1 interval timer operation setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-7 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 000 (cr000) as the interval. when the count value of 16-bit timer counter 00 (tm00) matches the value set in cr000, counting continues with the tm00 value cleared to 0 and the interrupt request signal (inttm000) is generated. the count clock of the 16-bit timer/event counter can be selected with bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). see 6.5 cautions on 16-bit timer/event counter 0 (2) 16-bit compare register setting for details of the operation when the compare register value is changed during timer count operation. figure 6-7. control register settings for interval timer operation (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare control register 00 (crc00) 00000 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 as compare register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. for details, refer to figures 6-2 and 6-3 .
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u15836ej2v1ud 122 figure 6-8. interval timer configuration diagram 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) ovf00 clear circuit inttm000 f x f x /2 2 f x /2 8 ti000/p00 selector noise eliminator f x figure 6-9. timing of interval timer operation count clock t tm00 count value cr000 inttm000 to00 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n count start clear clear interrupt acknowledged interrupt acknowledged interval time interval time interval time remark interval time = (n + 1) t n = 0001h to ffffh 6.4.2 ppg output operations setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-10 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, rectangular waves are output from the to00/ti010/p01 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (cr010) and in 16- bit timer capture/compare register 000 (cr000), respectively.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 123 figure 6-10. control register settings for ppg output operation (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare control register 00 (crc00) 00000 crc002 0 crc001 crc000 0 crc00 cr000 as compare register cr010 as compare register (c) 16-bit timer output control register 00 (toc00) 000 toc004 1 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output reverses output on match between tm00 and cr000 specifies initial value of to00 output f/f reverse output on match between tm00 and cr010 cautions 1. values in the following range should be set in cr000 and cr010: 0000h < cr010 < cr000 ffffh 2. the cycle of the pulse generated through ppg output (cr000 setting value + 1) has a duty of (cr010 setting value + 1)/(cr000 setting value + 1). 3. cr000 cannot be rewritten during tm00 operation. remarks 1. : don ? t care 2. in the ppg output operation, change the pulse width (rewrite cr010) during tm00 operation using the following procedure. <1> disable the timer output inversion operation by match of tm00 and cr010 (toc004 = 0) <2> disable the inttm010 interrupt (tmmk010 = 1) <3> rewrite cr010 <4> wait for 1 cycle of the tm00 count clock <5> enable the timer output inversion operation by match of tm00 and cr010 (toc004 = 1) <6> clear the interrupt request flag of inttm010 (tmif010 = 0) <7> enable the inttm010 interrupt (tmmk010 = 0)
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 124 6.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti000/p00 pin and ti010/to00/p01 pin using 16-bit timer counter 00 (tm00). there are two measurement methods: measuring with tm00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti000/p00 pin. (1) pulse width measurement with free-running counter and one capture register when 16-bit timer counter 00 (tm00) is operated in free-running mode (see register settings in figure 6-11 ), and the edge specified by prescaler mode register 00 (prm00) is input to the ti000/p00 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an external interrupt request signal (inttm001) is set. any of three edges can be selected ? rising, falling, or both edges ? specified using bits 4 and 5 (es000 and es001) of prm00. for valid edge detection, sampling is performed using the count clock selected by prm00, and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 6-11. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare control register 00 (crc00) 00000 crc002 1 crc001 0/1 crc000 0 crc00 cr000 as compare register cr010 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 6-2 and 6-3 .
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 125 figure 6-12. configuration diagram for pulse width measurement by free-running counter f x f x /2 2 f x /2 8 ti000/p00 16-bit timer counter 00 (tm00) ovf00 16-bit timer capture/compare register 010 (cr010) internal bus inttm010 selector figure 6-13. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm00 count value ti000 pin input cr010 capture value inttm010 ovf00 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 126 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 00 (tm00) is operated in free-running mode (see figure 6-14 ), it is possible to simultaneously measure the pulse widths of the two signals input to the ti000/p00 pin and the ti010/to00/p01 pin. when the edge specified by bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00) is input to the ti000/p00 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the edge specified by bits 6 and 7 (es100 and es101) of prm00 is input to the ti010/to00/p01 pin, the value of tm00 is taken into 16-bit timer capture/compare register 000 (cr000) and an interrupt request signal (inttm000) is set. any of three edges can be selected ? rising, falling, or both edges ? as the valid edge of the ti000/p00 pin and the ti010/to00/p01 pin, specified using bits 4 and 5 (es000 and es001) and bits 6 and 7 (es100 and es101) of prm00, respectively. for valid edge detection of the ti000/p00 and ti010/to00/p01 pins, sampling is performed at the interval selected by prescaler mode register 00 (prm00), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 6-14. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare control register 00 (crc00) 00000 crc002 1 crc001 0 crc000 1 crc00 cr000 as capture register captures valid edge of ti010/to00/p01 pin to cr000 cr010 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figure 6-2 .
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 127 ? ? ? ? capture operation (free-running mode) capture register operation in capture trigger input is shown below. figure 6-15. cr010 capture operation with rising edge specified count clock tm00 ti000 rising edge detection cr010 inttm010 n ? 3n ? 2n ? 1 n n+1 n figure 6-16. timing of pulse width measurement operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti010 pin input cr000 capture value inttm010 inttm000 ovf00 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 count clock tm00 count value ti000 pin input cr010 capture value
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 128 (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 00 (tm00) is operated in free-running mode (see figure 6-17 ), it is possible to measure the pulse width of the signal input to the ti000/p00 pin. when the edge specified by bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00) is input to the ti000/p00 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the inverse edge to that of the capture operation is input into cr010, the value of tm00 is taken into 16-bit timer capture/compare register 000 (cr000). either of two edges can be selected ? rising or falling ? as the valid edge of the ti000/p00 pin specified using bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00). for ti000/p00 pin valid edge detection, sampling is performed at the interval selected by prescaler mode register 00 (prm00), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti000/p00 pin is specified as both the rising and falling edges, 16-bit timer capture/compare register 000 (cr000) cannot perform the capture operation. figure 6-17. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare control register 00 (crc00) 00000 crc002 1 crc001 1 crc000 1 crc00 cr000 as capture register captures to cr000 at inverse edge to valid edge of ti000/p00. cr010 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 129 figure 6-18. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm010 ovf00 d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (4) pulse width measurement by means of restart when input of a valid edge to the ti000/p00 pin is detected, the count value of 16-bit timer counter 00 (tm00) is taken into 16-bit timer capture/compare register 010 (cr010), and then the pulse width of the signal input to the ti000/p00 pin is measured by clearing tm00 and restarting the count (see figure 6-19 ). either of two edges can be selected ? rising or falling ? specified using bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00). in valid edge detection, sampling is performed using the count clock cycle selected by prescaler mode register 00 (prm00) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti000/p00 pin is specified as both the rising and falling edges, 16-bit timer capture/compare register 000 (cr000) cannot perform the capture operation.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 130 figure 6-19. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 1 tmc002 0 tmc001 0/1 ovf00 0 tmc00 clears and starts at valid edge of ti000/p00 pin. (b) capture/compare control register 00 (crc00) 00000 crc002 1 crc001 1 crc000 1 crc00 cr000 as capture register captures to cr000 at inverse edge to valid edge of ti000/p00. cr010 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. for details, see figure 6-2 . figure 6-20. timing of pulse width measurement operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm010 d1 t d2 t d2 d1 d2 d1 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 131 6.4.4 external event counter operation the external event counter counts the number of external clock pulses input to the ti000/p00 pin using 16-bit timer counter 00 (tm00). tm00 is incremented each time the valid edge specified by prescaler mode register 00 (prm00) is input. when the tm00 count value matches the 16-bit timer capture/compare register 000 (cr000) value, tm00 is cleared to 0 and the interrupt request signal (inttm000) is generated. input a value other than 0000h to cr000 (a count operation with 1-bit pulse cannot be carried out). any of three edges can be selected ? rising, falling, or both edges ? specified using bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00). because operation is carried out only after the valid edge is detected twice by sampling using the internal clock (f x /2 3 ), noise with short pulse widths can be removed. figure 6-21. control register settings in external event counter mode (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare control register 00 (crc00) 00000 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 as compare register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. for details, see figures 6-2 and 6-3 .
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 132 figure 6-22. configuration diagram of external event counter 16-bit timer capture/compare register 000 (cr000) internal bus match clear ovf00 inttm000 f x /2 2 f x /2 8 f x noise eliminator f x valid edge of ti000 16-bit timer/counter 00 (tm00) 16-bit timer capture/compare register 010 (cr010) selector noise eliminator figure 6-23. external event counter operation timing (with rising edge specified) ti000 pin input tm00 count value cr000 inttm000 0000h 0001h 0002h 0003h 0004h 0005h n ? 1n 0000h 0001h 0002h 0003h n caution when reading the external event counter count value, tm00 should be read. 6.4.5 square-wave output operation a square wave with any selected frequency can be output at intervals of the count value preset to 16-bit timer capture/compare register 000 (cr000). the to00 pin output status is reversed at intervals of the count value preset to cr00 by setting bit 0 (toe00) and bit 1 (toc001) of 16-bit timer output control register 00 (toc00) to 1. this enables a square wave with any selected frequency to be output.
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 133 figure 6-24. control register settings in square-wave output mode (a) 16-bit timer mode control register 00 (tmc00) 0000 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare control register 00 (crc00) 00000 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 as compare register (c) 16-bit timer output control register 00 (toc00) 000 toc004 0 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output. reverses output on match between tm00 and cr000. specifies initial value of to00 output f/f. does not reverse output on match between tm00 and cr010. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. for details, see figures 6-3 and 6-4 . figure 6-25. square-wave output operation timing count clock tm00 count value cr000 inttm000 to00 pin output 0000h 0001h 0002h n ? 1n 0000h 0001h 0002h n ? 1n 0000h n
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 134 6.5 cautions on 16-bit timer/event counter 00 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 00 (tm00) is started asynchronously to the count clock. figure 6-26. start timing of 16-bit timer counter 00 (tm00) tm00 count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture compare register setting (in clear & start mode entered on match between tm00 and cr000) set 16-bit timer capture/compare registers 000, 010 (cr000, cr010) to other than 0000h. this means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 00 is used as an event counter. (3) operation after compare register change during timer count operation if the value after 16-bit timer capture/compare register 000 (cr000) is changed is smaller than that of 16-bit timer counter 00 (tm00), tm00 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr000 changes is smaller than that (n) before the change, it is necessary to restart the timer after changing cr000. figure 6-27. timings after change of compare register during timer count operation cr000 nm count clock tm00 count value x ? 1 x ffffh 0000h 0001h 0002h remark n > x > m
chapter 6 16-bit timer/event counter 00 preliminary user ? s manual u15836ej2v1ud 135 (4) capture register data retention timing if the valid edge of the ti000/p00 pin is input during 16-bit timer capture/compare register 010 (cr010) read, cr010 performs a capture operation. however, the capture value at this time is not guaranteed. the interrupt request flag (tmif010) is set upon detection of the valid edge. figure 6-28. capture register data retention timing n n + 1 n + 2 m m + 1 m + 2 x n + 2 m + 1 count clock tm00 count edge input interrupt request flag capture read signal cr010 interrupt value capture operation performed, but capture value not guaranteed. capture operation (5) valid edge setting set the valid edge of the ti000/p00 pin after setting bits 2 and 3 (tmc002 and tmc003) of 16-bit timer mode control register 00 (tmc00) to 0, 0, respectively, and then stopping timer operation. the valid edge is set using bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00). (6) operation of ovf00 flag <1> the ovf00 flag is set to 1 in the following case. when the clear & start mode entered on a match between tm00 and cr000 or the free-running mode entered on a ti00 valid edge is selected cr000 is set to ffffh tm00 is counted up from ffffh to 0000h. figure 6-29. operation timing of ovf00 flag count clock cr000 tm00 ovf00 inttm000 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf00 flag is cleared before the next count clock (before tm00 becomes 0001h) after the occurrence of tm00 overflow, the ovf0 flag is re-set newly and clear is disabled.
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u15836ej2v1ud 136 (7) conflicting operations conflict between the read period of the 16-bit timer capture/compare register (cr000/cr010) and capture trigger input (cr000/cr010 used as capture register) capture trigger input has priority. the data read from cr000/cr010 is undefined. (8) timer operation <1> even if 16-bit timer counter 00 (tm00) is read, the value is not captured by 16-bit timer capture/compare register 010 (cr010). <2> regardless of the cpu?s operation mode, when the timer stops, the input signals to the ti000/ti010 pins are not acknowledged. (9) capture operation <1> if ti000 is specified as the valid edge of the count clock, a capture operation by the capture register specified as the trigger for ti000 is not possible. <2> to ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 00 (prm00). <3> the capture operation is performed at the fall of the count clock. an interrupt request input (inttm000/inttm010), however, is generated at the rise of the next count clock. (10) compare operation <1> when the 16-bit timer capture/compare register (cr000/cr010) is overwritten during timer operation, a match interrupt may be generated or a clear operation may not be performed normally if that value is close to or larger than the timer value. <2> a capture operation may not be performed for cr000/cr010 set in compare mode even if a capture trigger has been input. (11) edge detection <1> if the ti000 or ti010 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti000 or ti010 pin to enable the 16-bit timer counter 00 (tm00) operation, a rising edge is detected immediately after the operation is enabled. be careful therefore when pulling up the ti000 or ti010 pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to remove noise differs when the ti000 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x , and in the latter case the count clock is selected by prescaler mode register 00 (prm00). the capture operation is started only after a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
preliminary user?s manual u15836ej2v1ud 137 chapter 7 8-bit timer/event counter 50 7.1 functions of 8-bit timer/event counter 50 8-bit timer/event counter 50 (tm50) has the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output figure 7-1 shows the block diagram of 8-bit timer/event counter 50. figure 7-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p17 f x /2 2 f x /2 6 f x /2 8 f x /2 13 f x f x /2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p17 selector 8-bit timer counter 50 (tm50) selector
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 138 7.2 configuration of 8-bit timer/event counter 50 8-bit timer/event counter 50 consists of the following hardware. table 7-1. configuration of 8-bit timer/event counter 50 item configuration timer register 8-bit timer counter 50 (tm50) register 8-bit timer compare register 50 (cr50) timer output 1 (to50) control registers timer clock selection register 50 (tcl50) 8-bit timer mode control register 50 (tmc50) port mode register 1 (pm1) note note see figure 4-1 block diagram of p10 to p17 . (1) 8-bit timer counter 50 (tm50) tm50 is an 8-bit register that counts the count pulses and is read-only. the counter is incremented is synchronization with the rising edge of the count clock. when the count value is read during operation, count clock input is temporary stopped, and then the count value is read. in the following situations, the count value is cleared to 00h. <1> reset input <2> when tce50 is cleared <3> when tm50 and cr50 match in clear & start mode if this mode was entered upon a match of tm50 and cr50 values. (2) 8-bit timer compare register 50 (cr50) cr50 can be read and written by an 8-bit memory manipulation instruction. except in pwm mode, the value set in cr50 is constantly compared with the 8-bit timer counter 50 (tm50) count value, and an interrupt request (inttm50) is generated if they match. in pwm mode, when the to50 pin becomes high level due to a tm50 overflow and the values of tm50 and cr50 match, the to50 pin becomes inactive. the value of cr50 can be set within 00h to ffh. cautions 1. in the clear & start mode entered on a match of tm50 and cr50 (tmc506 = 0), do not write other values to cr50 during operation. 2. in pwm mode, make the cr50 rewrite period 3 count clocks of the count clock (clock selected by tcl50) or more.
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 139 7.3 registers controlling 8-bit timer/event counter 50 the following three registers are used to control 8-bit timer/event counter 50. ? timer clock selection register 50 (tcl50) ? 8-bit timer mode control register 50 (tmc50) ? port mode register 1 (pm1) (1) timer clock selection register 50 (tcl50) this register sets the count clock of 8-bit timer/event counter 50 and the valid edge of ti50 input. tcl50 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 7-2. format of timer clock selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol76543210 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 010f x (10 mhz) 011f x /2 (5 mhz) 100f x /2 2 (2.5 mhz) 101f x /2 6 (156.25 khz) 110f x /2 8 (39.06 khz) 111f x /2 13 (1.22 khz) cautions 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz.
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 140 (2) 8-bit timer mode control register 50 (tmc50) tmc50 is a register that performs the following five types of settings. <1> 8-bit timer counter 50 (tm50) count operation control <2> 8-bit timer counter 50 (tm50) operating mode selection <3> timer output f/f (flip-flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode <5> timer output control tmc50 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 7-3 shows the tmc50 format. figure 7-3. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w symbol76543210 tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 clear & start mode by match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe50 timer output control 0 output disabled (to50 pin outputs the low level) 1 output enabled
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 141 cautions 1. to clear tce50 to 0, set the interrupt mask flag (tmmk50) to 1 beforehand. otherwise, an interrupt may occur when tce50 is cleared. tce50 is cleared to 0 as follows. tmmk50 = 1; mask set tce50 = 0; timer clear tmif50 = 0; interrupt request flag clear tmmk50 = 0; mask clear tce50 = 1; timer start 2. the settings of lvs50 and lvr50 are valid in other than pwm mode. 3. do not rewrite tmc501 and toe50 simultaneously. 4. when switching to the pwm mode, do not rewrite tm506 and lvs50 or lvr50 simultaneously. 5. to rewrite tmc506, stop operation beforehand. remarks 1. in pwm mode, pwm output is made inactive by setting tce50 to 0. 2. if lvs50 and lvr50 are read after data is set, 0 is read. 3. the values of the tmc506, lvs50, lvr50, tmc501, and toe50 bits are reflected at the to50 pin regardless of the value of tce50. (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p17/to50/ti50 pin for timer output, set pm17 and the output latches of p17 to 0. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 7-4. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol76543210 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) ? ? ? ? ? ?
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 142 7.4 operations of 8-bit timer/event counter 50 7.4.1 operation as interval timer 8-bit timer/event counter 50 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 50 (cr50). when the count value of 8-bit timer counter 50 (tm50) matches the value set to cr50, counting continues with the tm50 value cleared to 0 and an interrupt request signal (inttm50) is generated. the count clock of tm50 can be selected with bits 0 to 2 (tcl500 to tcl502) of timer clock selection register 50 (tcl50). [setting] <1> set the registers. ? tcl50: select the count clock. ? cr50: compare value ? tmc50: stop the count operation, select clear & start mode entered on a match of tm50 and cr50. (tmc50 = 0000 0b = don ? t care) <2> after tce50 = 1 is set, the count operation starts. <3> if the values of tm50 and cr50 match, inttm50 is generated (tm50 is cleared to 00h). <4> inttm50 is generated repeatedly at the same interval. set tce50 to 0 to stop the count operation. caution do not write other values to cr50 during operation. figure 7-5. interval timer operation timing (1/2) (a) basic operation t count clock tm50 count value cr50 tce50 inttm50 to50 count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time interval time remark interval time = (n + 1) t n = 00h to ffh
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 143 figure 7-5. interval timer operation timing (2/2) (b) when cr50 = 00h t count clock tm50 cr50 tce50 inttm50 to50 interval time 00h 00h 00h 00h 00h (c) when cr50 = ffh t count clock tm50 cr50 tce50 inttm50 to50 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowledged interrupt acknowledged
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 144 7.4.2 operation as external event counter the external event counter counts the number of external clock pulses to be input to ti50 by 8-bit timer counter 50 (tm50). tm50 is incremented each time the valid edge specified by timer clock selection register 50 (tcl50) is input. either the rising or falling edge can be selected. when the tm50 count value matches the value of 8-bit timer compare register 50 (cr50), tm50 is cleared to 0 and an interrupt request signal (inttm50) is generated. whenever the tm50 count value matches the value of cr50, inttm50 is generated. [setting] <1> set each register. ? tcl50: select ti50 edge. ti50 falling edge tcl50 = 00h ti50 rising edge tcl50 = 01h ? cr50: compare value ? tmc50: stop the count operation, select clear & start mode entered on match of tm50 and cr50, disable the timer f/f inversion operation, disable timer output. (tmc50 = 0000 00b = don ? t care) <2> when tce50 = 1 is set, the number of pulses input from ti50 is counted. <3> when the values of tm50 and cr50 match, inttm50 is generated (tm50 is cleared to 00h). <4> after these settings, inttm50 is generated each time the values of tm50 and cr50 match. figure 7-6. external event counter operation timing (with rising edge specified) ti50 tm50 count value cr50 inttm50 00 01 02 03 04 05 n ? 1 n 00 01 02 03 n count start n = 00h to ffh
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 145 7.4.3 operation as square-wave output a square wave with any selected frequency is output at intervals of the value preset to 8-bit timer compare register 50 (cr50). the to50 pin output status is inverted at intervals of the count value preset to cr50 by setting bit 0 (toe50) of 8- bit timer mode control register 50 (tmc50) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). [setting] <1> set each register. ? set the port latch (p17) and port mode register 1 (pm17) to 0. ? tcl50: select the count clock. ? cr50: compare value ? tmc50: stop the count operation, select clear & start mode entered on a match of tm50 and cr50. lvs50 lvr50 timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f inversion enabled timer output enabled (tmc50 = 00001011b or 00000111b) <2> after tce50 = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm50 and cr50. after inttm50 is generated, tm50 is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to50. the frequency is as follows. frequency = f cnt /2 (n + 1) (n: 00h to ffh, f cnt : count clock) caution do not write other values to cr50 during operation. figure 7-7. square-wave output operation timing count clock tm0 count value cr50 to50 note count start 00h 01h 02h n ? 1n 00h 01h 02h n ? 1n 00h n note the initial value of to50 output can be set by bits 2 and 3 (lvr50, lvs50) of 8-bit timer mode control register 50 (tmc50).
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 146 7.4.4 operation as pwm output 8-bit timer/event counter 50 operates as a pwm output when bit 6 (tmc506) of 8-bit timer mode control register 50 (tmc50) is set to 1. the duty ratio pulse is determined by the value set to 8-bit timer compare register 50 (cr50). set the active level width of the pwm pulse to cr50; the active level can be selected with bit 1 of tmc50 (tmc501). the count clock can be selected with bits 0 to 2 (tcl500 to tcl502) of timer clock selection register 50 (tcl50). pwm output can be enabled/disabled with bit 0 of tmc50 (toe50). caution in pwm mode, make the cr50 rewrite period 3 count clocks of the count clock (clock selected by tcl50) or more. (1) pwm output basic operation [setting] <1> set each register. ? set the port latch (p17) and port mode register 1 (pm17) to 0. ? tcl50: select the count clock. ? cr50: compare value ? tmc50: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc501 active level selection 0 active-high 1active-low timer output enabled (tmc50 = 01000001b or 01000011b) <2> the count operation starts when tce50 = 1. set tce50 to 0 to stop the count operation. [pwm output operation] <1> pwm output (output from to50) outputs an inactive level after the count operation starts until an overflow occurs. <2> when an overflow occurs, the active level set in <1> above is output. the active level is output until cr50 matches the count value of 8-bit timer counter 50 (tm50). <3> after the cr50 matches the count value, the inactive level is output until an overflow occurs again. <4> operations <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped with tce50 = 0, pwm output becomes inactive.
chapter 7 8-bit timer/event counter 50 preliminary user ? s manual u15836ej2v1ud 147 figure 7-8. pwm output operation timing (a) basic operation (active level = h) count clock tm50 cr50 tce50 inttm50 to50 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n active level active level inactive level (b) cr50 = 00h count clock tm50 cr50 tce50 inttm50 to50 l inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 (c) cr50 = ffh tm50 cr50 tce50 inttm50 to50 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level
chapter 7 8-bit timer/event counter 50 preliminary user?s manual u15836ej2v1ud 148 (2) operation with cr50 changed figure 7-9. timing of operation with cr50 changed (a) cr50 value is changed from n to m before clock rising edge of ffh value is reloaded to cr50 at overflow immediately after change. count clock tm50 cr50 tce50 inttm50 to50 <1> cr50 change (n m) n n+1 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h m h <2> (b) cr50 value is changed from n to m after clock rising edge of ffh value is reloaded to cr50 at second overflow. count clock tm50 cr50 tce50 inttm50 to50 n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 <1> cr50 change (n m) <2> caution when reading from cr50 between <1> and <2> in figure 7-9, the value read differs from the actual value (read value: m, actual value of cr50: n). 7.5 cautions on 8-bit timer/event counter 50 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counter 50 (tm50) is started asynchronously to the count clock. figure 7-10. 8-bit timer counter 50 start timing count clock tm50 count value 00h 01h 02h 03h 04h timer start
preliminary user?s manual u15836ej2v1ud 149 chapter 8 8-bit timers h0 and h1 8.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? 8-bit-accuracy interval timer ? 8-bit-accuracy pwm pulse generator mode 8.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 consist of the following hardware. table 8-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn register 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output two outputs (tohn) control register 8-bit timer h mode register n (tmhmdn) remark n = 0, 1 figures 8-1 and 8-2 show the block diagrams. figure 8-1. block diagram of 8-bit timer h0 match internal bus tmhe0 cks02 cks01 cks00 tmmd01tmmd00 tolev0 toen0 8-bit timer h mode control register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder toh0/p15 inttmh0 selector f x f x /2 f x /2 2 f x /2 6 f x /2 10 to50/ti50/p17 interrupt generator output controller level inversion 1 0 f/f r 8-bit timer counter h0 pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register 00 (cmp00) selector
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 150 figure 8-2. block diagram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11tmmd10 tolev1 toen1 8-bit timer h mode control register 1 (tmhmd1) 8-bit timer h compare register 11 (cmp11) decoder toh1/ intp5/ p16 inttmh1 selector f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 interrupt generator output controller level inversion 1 0 f/f r pwm mode signal timer h enable signal 3 2 8-bit timer h compare register 01 (cmp01) 8-bit timer counter h1 clear selector (1) 8-bit timer h compare register 0n (cmp0n) this register can be read/written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. cmp0n after reset: 00h r/w address: ff18h, ff1ah 7 6 5 4 32 1 0 caution this register cannot be rewritten during timer count operation. (2) 8-bit timer h compare register 1n (cmp1n) this register can be read/written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. cmp1n after reset: 00h r/w address: ff19h, ff1bh 7 6 5 4 32 1 0 cmp1n register can be rewritten during timer count operation. if the cmp1n register value is rewritten during timer operation, reloading is performed at the timing at which the counter value and cmp1n register value match. if the transfer timing and writing from cpu to cmp1n register conflict, transfer is not performed. caution in the pwm pulse generator mode, be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). remark n = 0, 1
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 151 8.3 registers controlling 8-bit timers h0 and h1 8-bit timers h0 and h1 are controlled by 8-bit timer h mode registers 0 and 1 (tmhmd0, tmhmd1). (1) 8-bit timer h mode registers 0 and 1 (tmhmd0, tmhmd1) these registers control the mode of timer h. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h.
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 152 figure 8-3. format of 8-bit timer h mode register 0 (tmhmd0) tmhe0 stops timer count operation enables timer count operation (count operation started by inputting clock) tmhe0 0 1 enables timer operation tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w f x f x /2 f x /2 2 f x /2 6 f x /2 10 to50 cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 (10 mhz) (5 mhz) (2.5 mhz) (156.25 khz) (9.77 khz) count clock (f cnt ) selection setting prohibited other interval timer mode pwm pulse generator mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other 7 6 5 4 32 1 0 cautions 1. when tmhe0 = 1, setting the other bits of the tmhmd0 register is disabled. 2. in the pwm pulse generator mode, be sure to set 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to the cmp10 register). remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 153 figure 8-4. format of 8-bit timer h mode register 1 (tmhmd1) tmhe1 stops timer count operation enables timer count operation (count operation started by inputting clock) tmhe1 0 1 enables timer operation tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz) count clock (f cnt ) selection setting prohibited other interval timer mode pwm pulse generator mode setting prohibited tmmd11 0 1 tmmd10 0 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control other 7 6 5 4 32 1 0 cautions 1. when tmhe1 = 1, setting the other bits of the tmhmd1 register is disabled. 2. in the pwm pulse generator mode, be sure to set 8-bit timer h compare register 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). remarks 1. f x : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency 3. figures in parentheses apply to operation at f x = 10 mhz, f r = 240 khz (typ.).
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 154 8.4 operation of 8-bit timers h0 and h1 8.4.1 operation as interval timer when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. (1) usage generates the inttmhn signal repeatedly at the same interval. <1> set each register. figure 8-5. register setting in interval timer mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting ? ? ? ? compare value (n) <2> count operation starts when tmhen = 1. <3> when the values of 8-bit timer counter hn and cmp0n register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. interval timer = (n + 1)/f cnt <4> subsequently, the inttmhn signal is generated at the same interval. to stop the count operation, set tmhen to 0.
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 155 (2) timing chart the timing in interval timer mode is shown below. figure 8-6. timing of interval timer operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bit to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output level is inverted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive by setting the tmhen bit to 0 during timer hn operation. if these are inactive from the first, the level is retained. remark n = 0, 1 n = 00h to ffh
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 156 figure 8-6. timing of interval timer operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 157 8.4.2 operation as pwm pulse generator in pwm mode, a pulse with arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). rewriting the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the duty of timer output (tohn). rewriting the cmp1n register during timer operation is possible. the operation in pwm mode is as follows. tohn output becomes active and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. tohn output becomes inactive when 8-bit timer counter hn and the cmp1n register match. (1) usage in pwm mode, a pulse, to which an arbitrary duty and arbitrary cycle can be set, is output. <1> set each register. figure 8-7. register setting in pwm pulse generator mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled timer output level inversion setting pwm mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) < ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare register that is to be compared first after counter operation is enabled. when the values of 8-bit timer counter hn and the cmp0n register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and tohn output becomes active. at the same time, the compare register to be compared with 8-bit timer counter hn is changed from the cmp0n register to the cmp1n register.
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 158 <4> when 8-bit timer counter hn and the cmp1n register match, tohn output becomes inactive and the compare register to be compared with 8-bit timer counter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty ratio can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is (n), the setting value of cmp1n register is (m), and the count clock frequency is f cnt , the pwm pulse output cycle and duty ratio are as follows. pwm pulse output cycle = (n + 1)/f cnt duty ratio = inactive width: active width = (m + 1): (n ? m) cautions 1. in pwm mode, three operation clocks (signal selected using the cksn2 to cksn0 bits of the tmhmdn register) are required to transfer the cmp1n register value after rewriting the register. 2. be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). (2) timing chart the operation timing in pwm mode is shown below. caution make sure that the cmp1n register setting value (m) and cmp0n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) < ffh
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 159 figure 8-8. operation timing in pwm pulse generator mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, tohn output remains inactive (when tolevn = 0). <2> when the values of 8-bit timer counter hn and the cmp0n register match, tohn output level is inverted, the value of 8-bit timer counter hn is cleared, and inttmhn signal is output. <3> when the values of 8-bit timer counter hn and the cmp1n register match, the level of tohn output is returned. at this time, the 8-bit timer counter value is not cleared and the inttmhn signal is not output. <4> setting the tmhen bit to 0 during timer hn operation makes the inttmhn signal and tohn output inactive. remark n = 0, 1
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 160 figure 8-8. operation timing in pwm pulse generator mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 161 figure 8-8. operation timing in pwm pulse generator mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1
chapter 8 8-bit timers h0 and h1 preliminary user ? s manual u15836ej2v1ud 162 figure 8-8. operation timing in pwm pulse generator mode (4/4) (e) operation by changing cmp1n (cmp1n = 01h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h cmp1n 01h a5h 03h 01h (03h) <1> <3> <4> <2> <2>' <5> <6> <1> the count operation is enabled by setting tmhen = 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, tohn output remains inactive (when tolevn = 0). <2> the cmp1n register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, tohn output becomes active, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter hn and the cmp1n register before the change match, the value is transferred to the cmp1n register and the cmp1n register value is changed (<2> ? ). however, three count clocks or more are required from when the cmp1n register value is changed to when the value is transferred to the register. if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter hn and the cmp1n register after the change match, tohn output becomes inactive. 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <6> setting the tmhen bit to 0 during timer hn operation makes the inttmhn signal and tohn output inactive.
preliminary user?s manual u15836ej2v1ud 163 chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer detects an inadvertent program loop. if a program loop is detected, an internal reset signal (wdtres) is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, refer to chapter 16 reset function . table 9-1. loop detection time of watchdog timer loop detection time during ring-osc clock operation during x1 input clock operation f r /2 11 (8.53 ms) f xp /2 13 (819.2 s) f r /2 12 (17.07 ms) f xp /2 14 (1.64 ms) f r /2 13 (34.13 ms) f xp /2 15 (3.28 ms) f r /2 14 (68.27 ms) f xp /2 16 (6.55 ms) f r /2 15 (136.53 ms) f xp /2 17 (13.11 ms) f r /2 16 (273.07 ms) f xp /2 18 (26.21 ms) f r /2 17 (546.13 ms) f xp /2 19 (52.43 ms) f r /2 18 (1.09 s) f xp /2 20 (104.86 ms) remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. figures in parentheses apply to operation at f r = 240 khz (typ.), f xp = 10 mhz the operation mode of the watchdog timer (wdt) is switched according to the mask option setting of the on-chip ring-osc as shown in table 9-2.
chapter 9 watchdog timer preliminary user?s manual u15836ej2v1ud 164 table 9-2. mask option setting and watchdog timer operation mode mask option ring-osc cannot be stopped ring-osc can be stopped by software watchdog timer clock source fixed to f r note 1 . ? selectable by software (f xp , f r or stopped) ? when reset is released: f r operation after reset operation starts with the maximum interval. operation starts with maximum interval. operation mode selection the interval can be changed only once. the clock selection/interval can be changed only once. features ? the watchdog timer cannot be stopped. ? current in stop mode 10 a the watchdog timer can be stopped in standby mode note 2 . notes 1. as long as power is being supplied, ring-osc oscillation absolutely cannot be stopped (except during reset). 2. clock supply to the watchdog timer is stopped in accordance with the watchdog timer clock source as follows: <1> when the clock source is f xp clock supply to the watchdog timer is stopped while f xp is stopped and during the oscillation stabilization time. <2> when the clock source is f r clock supply to the watchdog timer is stopped if f r is stopped by software before stop instruction execution when the cpu clock is f xp . remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 9.2 configuration of watchdog timer the watchdog timer consists of following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) = . .
chapter 9 watchdog timer preliminary user ? s manual u15836ej2v1ud 165 figure 9-1. block diagram of watchdog timer f r /2 2 clock input controller output controller wdtres (internal reset signal) wdcs2 internal bus wdcs1 wdcs0 f xp /2 4 wdcs3 wdcs4 01 1 selector 16-bit counter f xp /2 13 to f xp /2 20 or f r /2 11 to f r /2 18 watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 3 2 clear mask option (to set "ring-osc cannot be stopped" or "ring-osc can be stopped by software") 9.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer mode register (wdtm) ? watchdog timer enable register (wdte) (1) watchdog timer mode register (wdtm) this register sets the overflow time and operation clock of the watchdog timer. this register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. reset input sets this register to 67h.
chapter 9 watchdog timer preliminary user ? s manual u15836ej2v1ud 166 figure 9-2. format of watchdog timer mode register (wdtm) 0 wdcs0 1 wdcs1 2 wdcs2 3 wdcs3 4 wdcs4 5 1 6 1 7 0 symbol wdtm address: ff98h after reset: 67h r/w wdcs4 note 1 wdcs3 note 1 operation clock selection 0 0 ring-osc clock (f r ) 0 1 x1 input clock (f xp ) 1 watchdog timer operation stopped overflow time setting wdcs2 note 2 wdcs1 note 2 wdcs0 note 2 during ring-osc clock operation during x1 input clock operation 000f r /2 11 (8.53 ms) f xp /2 13 (819.2 s) 001f r /2 12 (17.07 ms) f xp /2 14 (1.64 ms) 010f r /2 13 (34.13 ms) f xp /2 15 (3.28 ms) 011f r /2 14 (68.27 ms) f xp /2 16 (6.55 ms) 100f r /2 15 (136.53 ms) f xp /2 17 (13.11 ms) 101f r /2 16 (273.07 ms) f xp /2 18 (26.21 ms) 110f r /2 17 (546.13 ms) f xp /2 19 (52.43 ms) 111f r /2 18 (1.09 s) f xp /2 20 (104.86 ms) notes 1. if ? ring-osc cannot be stopped ? is specified by a mask option, this cannot be set. the ring- osc clock will be selected no matter what value is written. 2. reset is released at the maximum cycle (wdcs2, 1, 0 = 1, 1, 1). cautions 1. if data is written to wdtm, a wait cycle is generated. for details, refer to chapter 25 cautions for wait. 2. set bits 7, 6, and 5 to 0, 1, and 1, respectively (when ?ring-osc cannot be stopped? is selected by a mask option, other values are ignored). 3. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing attempted a second time, an internal reset signal is generated. 4. wdtm cannot be set by a 1-bit memory manipulation instruction. remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. : don ? t care 4. figures in parentheses apply to operation at f r = 240 khz (typ.), f xp = 10 mhz
chapter 9 watchdog timer preliminary user?s manual u15836ej2v1ud 167 (2) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 9ah. figure 9-3. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah r/w cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. 2. if a 1-bit memory manipulation instruction is executed for wdte, an internal reset signal is generated (an error occurs in the assembler). 3. the value read from wdte is 9ah (this differs from the written value (ach)). 9.4 operation of watchdog timer 9.4.1 watchdog timer operation when ?ring-osc cannot be stopped? is selected by mask option the operation clock of watchdog timer is fixed to the ring-osc. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, wdcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1). the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: ring-osc clock ? cycle: f r /2 18 (1.09 seconds: at operation with f r = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2 . ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are executed, writing ach to wdte clears the count to 0, enabling recounting. notes 1. the operation clock (ring-osc clock) cannot be changed. if any value is written to bits 3 and 4 (wdcs3, wdcs4) of wdtm, it is ignored. 2. as soon as wdtm is written, the counter of the watchdog timer is cleared. caution in this mode, operation of the watchdog timer absolutely cannot be stopped even in stop mode. for 8-bit timer h1 (tmh1), a division of the ring-osc can be selected as the count source, so clear the watchdog timer using the interrupt request of tmh1 before the watchdog timer overflows. if this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after stop instruction execution.
chapter 9 watchdog timer preliminary user ? s manual u15836ej2v1ud 168 9.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option the operation clock of the watchdog timer can be selected as either the ring-osc clock or the x1 input clock. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, wdcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1). the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: ring-osc clock oscillation frequency (f r ) ? cycle: f r /2 18 (1.09 seconds: at operation with f r = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2, 3 . ? operation clock: any of the following can be selected using bits 3 and 4 (wdcs3 and wdcs4). ring-osc clock (f r ) x1 input clock (f xp ) watchdog timer operation stopped ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are executed, writing ach to wdte clears the count to 0, enabling recounting. notes 1. as soon as wdtm is written, the counter of the watchdog timer is cleared. 2. set bits 7, 6, and 5 to 0, 1, 1, respectively. if other values are set, the watchdog timer cannot be operated (an error occurs in the assembler). 3. if the watchdog timer is stopped by setting wdcs4 and wdcs3 to 1 and , respectively, an internal reset signal is not generated even if the following processing is performed. ? wdtm is written a second time. ? a 1-bit memory manipulation instruction is executed to wdte. ? a value other than ach is written to wdte. caution in this mode, watchdog timer operation is stopped during halt/stop instruction execution. after halt/stop mode is released, counting is started again using the operation clock of the watchdog timer set before halt/stop instruction execution by wdtm. at this time, the counter is not cleared to 0. for the watchdog timer operation during stop mode and halt mode in each status, refer to 9.4.3 watchdog timer operation in stop mode and 9.4.4 watchdog timer operation in halt mode .
chapter 9 watchdog timer preliminary user?s manual u15836ej2v1ud 169 9.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during stop instruction execution regardless of whether the x1 input clock or ring-osc clock is being used. (1) when the cpu clock and the watchdog timer operation clock are the x1 input clock (f xp ) when the stop instruction is executed when stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (osts) and then counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 9-4. operation in stop mode (cpu clock and wdt operation clock: x1 input clock) watchdog timer operating operation stopped operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) (2) when the cpu clock is the x1 input clock (f xp ) and the watchdog timer operation clock is the ring-osc clock (f r ) when the stop instruction is executed when the stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 9-5. operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) operating operation stopped
chapter 9 watchdog timer preliminary user ? s manual u15836ej2v1ud 170 (3) when the cpu clock is the ring-osc clock (f r ) and the watchdog timer operation clock is the x1 input clock (f xp ) when the stop instruction is executed when the stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. <1> the oscillation stabilization time set by the oscillation stabilization time select register (osts) elapses. <2> the cpu clock is switched to the x1 input clock (f xp ). figure 9-6. operation in stop mode (cpu clock: ring-osc clock, wdt operation clock: x1 input clock) <1> timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register (osts) has elapsed watchdog timer operating operation stopped operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) <2> timing when counting is started after the cpu clock is switched to the x1 input clock (f xp ) operating operation stopped operating f r f xp f r f xp note cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) normal operation (x1 input clock) cpu clock oscillation stopped stop oscillation stabilization time (set by osts register) note confirm the oscillation stabilization time of f xp using the oscillation stabilization time counter status register (ostc).
chapter 9 watchdog timer preliminary user?s manual u15836ej2v1ud 171 (4) when cpu clock and watchdog timer operation clock are the ring-osc clocks (f r ) during stop instruction execution when the stop instruction is executed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 9-7. operation in stop mode (cpu clock and wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) operating operation stopped 9.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during halt instruction execution regardless of whether the cpu clock is the x1 input clock (f xp ) or ring-osc clock (f r ), or whether the operation clock of the watchdog timer is the x1 input clock (f xp ) or ring-osc clock (f r ). after halt mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0. figure 9-8. operation in halt mode watchdog timer operating f r f xp cpu operation normal operation operating halt operation stopped normal operation
preliminary user?s manual u15836ej2v1ud 172 chapter 10 a/d converter 10.1 function of a/d converter the a/d converter converts an analog input signal into a digital value, and consists of up to four channels (ani0 to ani3) with a resolution of 10 bits. the a/d converter has the following two functions. (1) 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani3. each time an a/d conversion operation ends, an interrupt request (intad) is generated. (2) power-fail detection function this function is to detect a voltage drop in a battery. the values of the a/d conversion result (adcr register value) and power-fail comparison threshold register (pft) are compared. intad is generated only when a comparative condition has been matched.
chapter 10 a/d converter preliminary user?s manual u15836ej2v1ud 173 figure 10-1. block diagram of a/d converter sample & hold circuit series resistor string successive approximation register (sar) adcs fr2 fr1 adce controller voltage comparator a/d conversion result register (adcr) av ref (can be used as analog power supply) av ss intad internal bus a/d converter mode register (adm) tap selector selector ani0/p20 ani1/p21 ani2/p22 ani3/p23 fr0 ads1 ads0 analog input channel specification register (ads) 2 figure 10-2. block diagram of power-fail detection function selector pfen pfcm internal bus a/d converter pfcm pfen comparator power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) intad selector ani0/p20 ani1/p21 ani2/p22 ani3/p23 ads1 ads0 analog input channel specification register (ads) 2
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 174 10.2 a/d converter configuration the a/d converter consists of the following hardware. table 10-1. configuration of a/d converter item configuration analog input 4 channels (ani0 to ani3) registers successive approximation register (sar) a/d conversion result register (adcr) control registers a/d converter mode register (adm) analog input channel specification register (ads) power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) (1) successive approximation register (sar) this register compares the analog input voltage value with the voltage tap (compare voltage) value applied from the series resistor string, and holds the result starting from the most significant bit (msb). when the result up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr) the adcr is 16-bit register that stores the a/d conversion result. the lower six bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register, and is stored in adcr in order starting from the most significant bit (msb). adcr can be read by a 16-bit memory manipulation instruction. reset input sets adcr to 0000h. figure 10-3. format of a/d conversion register (adcr) symbol address: ff08h, ff09h after reset: 0000h r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is generated. for details, refer to chapter 25 cautions for wait.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 175 (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input with the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared with the analog input. (6) ani0 to ani3 pins these four-channel analog input pins input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani3 are alternate-function pins that can also be used for digital input. cautions 1. observe the rated range of the ani0 to ani3 input voltage. if a voltage of av ref or higher or a voltage of av ss or lower (even if within the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. 2. the analog input pins (ani0 to ani3) are also used as input port pins (p20 to p23). when a/d conversion is performed with any of ani0 to ani3 selected, do not execute the input instruction to port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. if a digital pulse is applied to the pins adjacent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. (7) av ref pin the av ref pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani3 into digital signals based on a voltage between av ref and av ss . in a standby mode, the current flowing into series resistor strings can be reduced by changing the input voltage of the av ref pin to av ss level. it can also be used as the analog power supply. when the a/d converter is used, be sure to use the av ref pin for the power supply. caution a series resistor string of several tens of k ? ? ? ? is connected between the av ref and av ss pins. therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. (8) av ss pin the av ss pin is the gnd potential pin for the a/d converter. always use the av ss pin at the same potential as the v ss0 pin, even when the a/d converter is not used.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 176 10.3 registers controlling a/d converter the following four registers are used to control the a/d converter. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power-fail comparison mode register (pfm) ? power-fail comparison threshold register (pft) (1) a/d converter mode register (adm) this register sets the conversion time for analog input to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-4. format of a/d converter mode register (adm) adce 0 0 fr0 fr1 fr2 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 conversion time selection note 1 288/f x 240/f x 192/f x 144/f x 120/f x 96/f x setting prohibited fr2 0 0 0 1 1 1 other fr1 0 0 1 0 0 1 fr0 0 1 0 0 1 0 0 1 2 3 4 5 6 7 adm address: ff28h after reset: 00h r/w symbol 34.3 s 28.6 s 22.9 s 17.2 s 14.3 s 11.5 s note 1 28.8 s 24.0 s 19.2 s 14.4 s 12.0 s note 1 9.6 s note 1 f x = 8.38 mhz f x = 10 mhz boost reference voltage generator operation control note 2 stops operation of reference voltage generator enables operation of reference voltage generator adce 0 1 notes 1. set so that the a/d conversion time is 14 s or longer. 2. a booster circuit is incorporated to realize low-voltage operation. the operation of the circuit that generates the reference voltage for boosting is controlled by adce, and it takes 14 s from operation start to operation stabilization. therefore, when adcs is set to 1 after 14 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 177 table 10-2. settings of adcs and adce adcs adce a/d conversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only reference voltage generator consumes power) 1 0 conversion mode (reference voltage generator operation stopped note ) 1 1 conversion mode (reference voltage generator operates) note data of first conversion cannot be used. figure 10-5. timing chart when boost reference voltage generator is used adce boost reference voltage adcs conversion operation conversion operation conversion stopped conversion waiting boost reference voltage generator: operating note note 14 s or more is required for reference voltage stabilization. cautions 1. a/d conversion must be stopped before rewriting bits fr0 to fr2 to values other than the identical data. 2. for the a/d converter sampling time and a/d conversion start delay time, refer to 10.6 cautions for a/d converter (11). 3. if data is written to adm, a wait cycle is generated. for details, refer to chapter 25 cautions for wait. remark f x : x1 input clock oscillation frequency
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 178 (2) analog input channel specification register (ads) this register specifies the analog voltage input port to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-6. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ads0 0 1 0 1 ads1 0 0 1 1 ads2 0 0 0 0 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol cautions 1. be sure to set bits 2 to 7 of ads to 0. 2. if data is written to ads, a wait cycle is generated. for details, refer to chapter 25 cautions for wait. (3) power-fail comparison mode register (pfm) power-fail comparison mode register (pfm) is a register that controls the comparison operation. pfm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-7. format of power-fail comparison mode register (pfm) 0 0 0 0 0 0 pfcm pfen power-fail comparison enable stops power-fail comparison (used as a normal a/d converter) enables power-fail comparison (used for power-fail detection) pfen 0 1 power-fail comparison mode selection interrupt request signal (intad) generation no intad generation no intad generation intad generation adcr3 pft3 adcr3 < pft3 adcr3 pft3 adcr3 < pft3 pfcm 0 1 0 1 2 3 4 5 6 7 pfm address: ff2ah after reset: 00h r/w symbol caution if data is written to pfm, a wait cycle is generated. for details, refer to chapter 25 cautions for wait.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 179 (4) power-fail comparison threshold register (pft) the power-fail comparison threshold register (pft) is a register that sets the threshold value when comparing the values with the a/d conversion result. 8-bit data in pft is compared to the higher 8 bits (ff09h) of the 10-bit a/d conversion result. pft can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-8. format of power-fail comparison threshold register (pft) pft0 pft1 pft2 pft3 pft4 pft5 pft6 pft7 0 1 2 3 4 5 6 7 pft address: ff2bh after reset: 00h r/w symbol caution if data is written to pft, a wait cycle is generated. for details, refer to chapter 25 cautions for wait. 10.4 a/d converter operations 10.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with analog input channel specification register (ads). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <6> next, bit 8 of sar is automatically set to 1, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) v dd ? bit 9 = 0: (1/4) v dd the voltage tap and analog input voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion result register (adcr) and then latched. at the same time, the a/d conversion end interrupt request (intad) can also be generated. caution the first a/d conversion value immediately after a/d conversion operations start may not fall within the rating.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 180 figure 10-9. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to one of the adm, analog input channel specification register (ads), power-fail comparison mode register (pfm), or power-fail comparison threshold register (pft) during an a/d conversion operation, the conversion operation is initialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr) to 0000h.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 181 10.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani3) and the a/d conversion result (stored in the a/d conversion result register (adcr)) is shown by the following expression. adcr = int ( 1024 + 0.5) or (adcr ? 0.5) ? v in < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr: a/d conversion result register (adcr) value figure 10-11 shows the relationship between the analog input voltage and the a/d conversion result. figure 10-10. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref v in av ref av ref 1024 av ref 1024
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 182 10.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani3 by the analog input channel specification register (ads) and a/d conversion is executed. in addition, the following two functions can be selected by setting of bit 7 (pfen) of the power-fail comparison mode register (pfm). ? normal 10-bit a/d converter (pfen = 0) ? power-fail detection function (pfen = 1) (1) a/d conversion operation (when pfen = 0) by setting bit 7 (adcs) of the a/d converter mode register (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 0, the a/d conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once the a/d conversion has started and when one a/d conversion has been completed, the next a/d conversion operation is immediately started. the a/d conversion operations are repeated until new data is written to ads. if ads is rewritten during a/d conversion, the a/d conversion under execution is suspended, and the a/d conversion of the newly selected analog input channel is started. if 0 is written to adcs of adm during a/d conversion, the conversion operation is immediately stopped. figure 10-11. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped a/d conversion adcr intad (pfen = 0) conversion is stopped conversion result is not retained remarks 1. n = 0 to 3 2. m = 0 to 3
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 183 (2) power-fail detection function (when pfen = 1) by setting bit 7 (adcs) of the a/d converter mode register (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 1, the a/d conversion operation of the voltage, which applied to the analog input pin specified by the analog input channel specification register (ads), is started. when the a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr), the values are compared with power-fail comparison threshold register (pft), and an interrupt request signal (intad) is generated under the condition specified by bit 6 (pfcm) of pfm. <1> when pfen = 0 intad is generated at the end of each a/d conversion. <2> when pfen = 1 and pfcm = 0 the adcr and pft values are compared when a/d conversion ends and intad is only generated when adcr pft. <3> when pfen = 1 and pfcm = 1 the adcr and pft values are compared when a/d conversion ends and intad is only generated when adcr < pft. figure 10-12. power-fail detection (when pfen = 1 and pfcm = 0) a/d conversion adcr pft intad (pfen = 1) anin anin 80h 80h condition match first conversion note 7fh 80h anin anin note if the conversion result is not read before the end of the next conversion after intad is output, the result is replaced by the next conversion result. remark n = 0 to 3
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 184 the setting methods are described below. ? when used as a/d conversion operation <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> select the channel and conversion time using bits 1 and 0 (ads1, ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <3> set bit 7 (adcs) of adm to 1. <4> an interrupt request signal (intad) is generated. <5> transfer the a/d conversion data to the a/d conversion result register (adcr). <6> change the channel using bits 1 and 0 (ads1, ads0) of ads. <7> an interrupt request signal (intad) is generated. <8> transfer the a/d conversion data to the a/d conversion result register (adcr). <9> clear adcs to 0. <10> clear adce to 0. cautions 1. make sure the period of <1> to <3> is 14 s or more. 2. it is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. however, do not use the first conversion result after <3> in this case. 4. the period from <4> to <7> differs from the conversion time set using bits 5 to 3 (fr2 to fr0) of adm. the period from <6> to <7> is the conversion time set using fr2 to fr0. ? when used as power-fail function <1> set the bit 7 (pfen) of the power-fail comparison mode register (pfm). <2> set power-fail comparison condition using bit 6 (pfcm) of pfm. <3> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <4> select the channel and conversion time using bits 1 and 0 (ads1, ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <5> set a threshold value to the power-fail comparison threshold register (pft). <6> set bit 7 (adcs) of adm to 1. <7> transfer the a/d conversion data to the a/d conversion result register (adcr). <8> adcr and pft are compared and an interrupt request signal (intad) is generated if the conditions match. <9> change the channel using bits 1 and 0 (ads1, ads0) of ads. <10> transfer the a/d conversion data to the a/d conversion result register (adcr). <11> adcr and the power-fail comparison threshold register (pft) are compared and an interrupt request signal (intad) is generated if the conditions match. <12> clear adcs to 0. <13> clear adce to 0. cautions 1. make sure the period of <3> to <6> is 14 s or more. 2. it is no problem if order of <3>, <4>, and <5> is changed. 3. <3> can be omitted. however, do not use the first conversion result after <6> in this case. 4. the period from <7> to <11> differs from the conversion time set using bits 5 to 3 (fr2 to fr0) of adm. the period from <9> to <11> is the conversion time set using fr2 to fr0.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 185 10.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 10-13. overall error figure 10-14. quantization error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 186 (4) zero-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 0 ?? 000 to 0 ?? 010. (5) full-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale ? 3/2lsb) when the digital output changes from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indicates the difference between the actual measurement value and the ideal value. figure 10-15. zero-scale error figure 10-16. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref av ref ? 1 av ref ? 2 av ref ? 3 digital output (lower 3 bits) analog input (lsb) ideal line full-scale error figure 10-17. integral linearity error figure 10-18. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 187 (8) conversion time this expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. the sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time 10.6 cautions for a/d converter (1) current consumption in standby mode the a/d converter stops operating in the standby mode. at this time, the current consumption can be reduced by stopping the conversion operation (by setting bit 7 (adcs) of the a/d converter mode register (adm) to 0). figure 10-20 shows how to reduce the current consumption in the standby mode. figure 10-19. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs (2) input range of ani0 to ani3 observe the rated range of the ani0 to ani3 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 188 (3) conflicting operations <1> conflict between a/d conversion result register (adcr) write and adcr read by instruction upon the end of conversion adcr read has priority. after the read operation, the new conversion result is written to adcr. old data can be read from adcr at the timing of (1) and new data can be read from adcr at the timing of (2) as shown in figure 10-21. a master-slave configuration is employed for transferring the a/d conversion result to adcr. figure 10-20. storing conversion result in adcr and timing of data read from adcr (1) timing to read old data internal clock intad master write signal a/d conversion (master) slave write signal adcr (slave) read data conversion end conversion result n conversion result n conversion result n conversion result n + 1 (2) timing to read new data internal clock intad master write signal a/d conversion (master) slave write signal adcr (slave) read data conversion end conversion result n conversion result n + 1 conversion result n + 1 conversion result n + 1 <2> contention between adcr write and a/d converter mode register (adm) write or analog input channel specification register (ads) write adm or ads write has priority. adcr write is not performed, nor is the conversion end interrupt signal (intad) generated.
chapter 10 a/d converter preliminary user?s manual u15836ej2v1ud 189 (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani3. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 10-21, to reduce noise. figure 10-21. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani3 (5) ani0/p20 to ani3/p23 the analog input pins (ani0 to ani3) are also used as input port pins (p20 to p23). when a/d conversion is performed with any of ani0 to ani3 selected, do not execute the input instruction to port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. if a digital pulse is applied to the pins adjacent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani3 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth of the conversion time. since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani3 pins (see figure 10-21 ). (7) av ref pin input impedance a series resistor string of several tens of 10 k ? is connected between the av ref and av ss pins. therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error.
chapter 10 a/d converter preliminary user?s manual u15836ej2v1ud 190 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrite. caution is therefore required since, at this time, when adif is read immediately after the ads rewrite, adif is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. figure 10-22. timing of a/d conversion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr intad anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 3 2. m = 0 to 3 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conversion starts may not fall within the rating. poll the a/d conversion end interrupt request (intad) and take measures such as removing the first conversion result. (10) a/d conversion result register (adcr) read operation when a write operation is performed to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read.
chapter 10 a/d converter preliminary user ? s manual u15836ej2v1ud 191 (11) a/d converter sampling time and a/d conversion start delay time the a/d converter sampling time differs depending on the set value of the a/d converter mode register (adm). the delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 10-23 and table 10-3. figure 10-23. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time a/d conversion start delay time sampling time sampling timing intad adcs 1 or ads rewrite table 10-3. a/d converter sampling time and a/d conversion start delay time (adm set value) a/d conversion start delay time note fr2 fr1 fr0 conversion time sampling time min. max. 0 0 0 288/f x 40/f x 32/f x 36/f x 0 0 1 240/f x 32/f x 28/f x 32/f x 0 1 0 192/f x 24/f x 24/f x 28/f x 1 0 0 144/f x 20/f x 16/f x 18/f x 1 0 1 120/f x 16/f x 14/f x 16/f x 1 1 0 96/f x 12/f x 12/f x 14/f x other than above setting prohibited ??? note the a/d conversion start delay time is the time after wait period. for the wait function, refer to chapter 25 cautions for wait . remark f x : x1 clock oscillation frequency
preliminary user?s manual u15836ej2v1ud 192 chapter 11 serial interface uart0 ( pd780102, 780103, and 78f0103 only) 11.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial transfer is not executed and can enable a reduction in the power consumption. for details, refer to 11.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. ? two-pin configuration t x d0: transmit data output pin r x b0: receive data input pin ? length of transfer data can be selected from 7 or 8 bits. ? dedicated internal 5-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? four operating clock inputs selectable ? fixed to lsb-first transfer cautions 1. the default value of the t x d0 pin is high level. exercise care when using the t x d0 pin as a port pin. 2. if clock supply to serial interface uart0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart0 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before clock supply was stopped. the t x d0 pin also holds the value immediately before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power0 = 0, rxe0 = 0, and txe0 = 0. 3. set power0 = 1 and then set txe0 = 1 (transmission) or rxe0 = 1 (reception) to start communication. 4. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set.
chapter 11 serial interface uart0 preliminary user?s manual u15836ej2v1ud 193 11.2 configuration of serial interface uart0 serial interface uart0 consists of the following hardware. table 11-1. configuration of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface operation mode register 0 (asim0) asynchronous serial interface reception error status register 0 (asis0) baud rate generator control register 0 (brgc0)
chapter 11 serial interface uart0 preliminary user?s manual u15836ej2v1ud 194 t x d0/sck10/p10 intst0 r x d0/si10/p11 intsr0 f x /2 5 f x /2 3 f x /2 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) to50/ti50/p17 (tm50 output) registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit figure 11-1. block diagram of serial interface uart0
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 195 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data converted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the receive data is not transferred to rxb0. reset input or power0 = 0 sets this register to ffh. rxb0 can be read by an 8-bit memory manipulation instruction. no data can be written to this register. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. reset input, powr0 = 0, or txe0 = 0 sets this register to ffh. txs0 can be written by an 8-bit memory manipulation instruction. this register cannot be read. caution do not write the next transmit data to txs0 before the transmission completion interrupt signal (intst0) is generated.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 196 11.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following three registers. ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface reception error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) (1) asynchronous serial interface operation mode register 0 (asim0) this 8-bit register controls the serial transfer operations of serial interface uart0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. figure 11-2. format of asynchronous serial interface operation mode register 0 (asim0) (1/2) address: ff70h after reset: 01h r/w symbol76543210 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operation of internal operation clock 0 note disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception. note the input from the r x d0 pin is fixed to high level when power0 = 0. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. clear txe0 to 0 first, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. clear rxe0 to 0 first, and then clear power0 to 0. 3. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set. 4. be sure to set bit 0 to 1.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 197 figure 11-2. format of asynchronous serial interface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. clear the txe0 and rxe0 bits to 0 before rewriting the ps01, ps00, and cl0 bits. 2. make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 198 (2) asynchronous serial interface reception error status register 0 (asis0) this register indicates an error status on completion of reception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power0) and bit 5 (rxe0) of asim0 = 0. 00h is read when this register is read. figure 11-3. format of asynchronous serial interface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol76543210 asis000000pe0fe0ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. for details, refer to chapter 25 cautions for wait.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 199 (3) baud rate generator control register 0 (brgc0) this register selects the base clock of serial interface uart0 and controls the baud rate. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. figure 11-4. format of baud rate generator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol76543210 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk ) selection 0 0 tm50 output (to50) 01f x /2 (5 mhz) 10f x /2 3 (1.25 mhz) 11f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 00 setting prohibited 010008f xclk /8 010019f xclk /9 0101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1101026f xclk /26 1101127f xclk /27 1110028f xclk /28 1111030f xclk /30 1111131f xclk /31 cautions 1. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 2. the baud rate is the output clock of the 5-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to mdl00 bits (k = 8, 9, 10, ..., 31) 4. :don ? t care 5. figures in parentheses apply to operation at f x = 10 mhz
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 200 11.4 operation of serial interface uart0 this section explains the two modes of serial interface uart0. 11.4.1 operation stop mode in this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. in addition, the pins can be used as ordinary port pins in this mode. (1) register setting the operation stop mode is set by asynchronous serial interface operation mode register 0 (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff70h after reset: 01h r/w symbol76543210 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operation of internal operation clock 0 note disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception. note the input from the r x d0 pin is fixed to high level when power0 = 0. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. clear txe0 to 0 first, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. clear rxe0 to 0 first, and then clear power0 to 0. 3. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 201 11.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) register setting the uart mode is set by asynchronous serial interface operation mode register 0 (asim0), asynchronous serial interface reception error status register 0 (asis0), and baud rate generator control register 0 (brgc0). (a) asynchronous serial interface operation mode register 0 (asim0) this 8-bit register controls the serial transfer operations of serial interface uart0. asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff70h after reset: 01h r/w symbol76543210 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operation of internal operation clock 0 note disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception note the input from the r x d0 pin is fixed to high level when power0 = 0. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. clear txe0 to 0 first, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. clear rxe0 to 0 first, and then clear power0 to 0. 3. txe0 and rxe0 are synchronized with the base clock (f xclk ) set by brgc0. therefore, the transmission unit may not be initialized if txe0 = 1 is not set again 2 clocks after txe0 = 0 is set. similarly, the reception unit may not be initialized if rxe0 = 1 is not set again 2 clocks after rxe0 = 0 is set. 4. be sure to set bit 0 to 1.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 202 ps01 ps00 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. clear the txe0 and rxe0 bits to 0 before rewriting the ps01, ps00, and cl0 bits. 2. make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the sl0 bit.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 203 (b) asynchronous serial interface reception error status register 0 (asis0) this register indicates an error status on completion of reception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power0) and bit 5 (rxe0) of asim0 = 0. 00h is read when this register is read. address: ff73h after reset: 00h r symbol76543210 asis000000pe0fe0ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. for details, refer to chapter 25 cautions for wait.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 204 (2) communication operation (a) normal transmit/receive data format figure 11-5 shows the format of the transmit/receive data. figure 11-5. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits (lsb first) ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface mode register 0 (asim0). figure 11-6. example of normal uart transmit/receive data format 1. data length: 8 bits, parity: even parity, stop bit: 1 bit, transfer data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 7 bits, parity: odd parity, stop bit: 2 bits, transfer data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. data length: 8 bits, parity: none, stop bit: 1 bit, transfer data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 205 (b) parity types and operation the parity bit is used to detect a bit error in communication data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ? 1 ? : 1 if transmit data has an even number of bits that are ? 1 ? : 0 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ? 1 ? is odd. if transmit data has an odd number of bits that are ? 1 ? : 0 if transmit data has an even number of bits that are ? 1 ? : 1 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ? 0 ? or ? 1 ? . (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no parity bit when data is received. because there is no parity bit, a parity error does not occur.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 206 (c) transmission the t x d0 pin outputs a high level when bit 7 (power0) of asynchronous serial interface mode register 0 (asim0) is set to 1. if bit 6 (txe0) of asim0 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to transmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the start bit is output from the t x d0 pin, followed by the rest of the data in order starting from the lsb. when transmission is completed, the parity and stop bits set by asim0 are appended and a transmission completion interrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 11-7 shows the timing of the transmission completion interrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 11-7. normal transmission completion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 207 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator starts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 11-8). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the stop bit has been received, the reception completion interrupt (intsr0) is generated and the data of rxs0 is written to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) or a framing error (fe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr0) is generated after completion of reception. figure 11-8. reception completion interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. be sure to read receive buffer register 0 (rxb0) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchronous serial interface reception error status register 0 (asis0) before reading rxb0.
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 208 (e) reception error three types of errors may occur during reception: a parity error, framing error, or overrun error. if the error flag of asynchronous serial interface reception error status register 0 (asis0) is set as a result of data reception, a reception error interrupt request (intsr0) is generated. which error has occurred during reception can be identified by reading the contents of asis0 in the reception error interrupt servicing (intsr0) (refer to table 11-2 ). the contents of asis0 are reset to 0 when asis0 is read. table 11-2. cause of reception error reception error cause value of asis0 parity error the parity specified for transmission does not match the parity of the receive data. 04h framing error stop bit is not detected. 02h overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). 01h (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 11-9, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 11-9. noise filter circuit internal signal b internal signal a match detector in base clock r x d0/si10/p11 q in ld_en q
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 209 11.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of baud rate generator ? base clock (clock) the clock selected by bits 7 and 6 (tps01 and tps00) of baud rate generator control register 0 (brgc0) is supplied to each module when bit 7 (power0) of asynchronous serial interface mode register 0 (asim0) is 1. this clock is called the base clock ? clock ? and its frequency is called f xclk . ? clock ? is fixed to low level when power0 = 0. ? transmission counter this counter stops, cleared to 0, when bit 7 (power0) or bit 6 (txe0) of asynchronous serial interface mode register 0 (asim0) is 0. it starts counting when power0 = 1 and txe0 = 1. the counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (txs0). ? reception counter this counter stops operation, cleared to 0, when bit 7 (power0) or bit 5 (rxe0) of asynchronous serial interface mode register 0 (asim0) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. figure 11-10. configuration of baud rate generator clock (f xclk ) selector power0 5-bit counter match detector baud rate brgc0: mdl04 to mdl00 1/2 power0, txe0 (or rxe0) brgc0: tps01, tps00 to50/ti50/p17 (tm50 output) f x /2 5 f x /2 f x /2 3 remark power0: bit 7 of asynchronous serial interface mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 brgc0: baud rate generator control register 0
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 210 (2) generation of serial clock a serial clock can be generated by using baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value of the 5-bit counter. (a) baud rate generator control register 0 (brgc0) this register selects the base clock of serial interface uart0 and controls the baud rate. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. address: ff71h after reset: 1fh r/w symbol76543210 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk ) selection 0 0 tm50 output (to50) 01f x /2 (5 mhz) 10f x /2 3 (1.25 mhz) 11f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 00 setting prohibited 010008f xclk /8 010019f xclk /9 0101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1101026f xclk /26 1101127f xclk /27 1110028f xclk /28 1111030f xclk /30 1111131f xclk /31 cautions 1. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 2. the baud rate value is the output clock of the 5-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to mdl00 bits (k = 8, 9, 10, ..., 31) 4. :don ? t care 5. figures in parentheses apply to operation with f x = 10 mhz
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 211 (b) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk : frequency of base clock (clock) selected by the tps01 and tps00 bits of the brgc0 register k: value set by the mdl04 to mdl00 bits of the brgc0 register (k = 8, 9, 10, ..., 31) (c) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error during reception satisfies the range shown in (4) permissible baud rate range during reception. example: frequency of base clock (clock) = 2.5 mhz = 2,500,000 hz set value of mdl04 to mdl00 bits of brgc0 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78,125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] f xclk 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate)
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 212 (3) example of setting baud rate table 11-3. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] 2400 ?? ? ? ?? ? ? 3 27 2425 1.03 4800 ?? ? ? 3 16 4883 1.73 3 14 4676 ? 2.58 9600 3 16 9766 1.73 3 8 9766 1.73 2 27 9699 1.03 10400 3 15 10417 0.16 2 30 10417 0.16 2 25 10475 0.72 19200 3 8 19531 1.73 2 16 19531 1.73 2 14 18705 ? 2.58 31250 2 20 31250 0 2 10 31250 0 ?? ? ? 38400 2 16 39063 1.73 2 8 39063 1.73 1 27 38796 1.03 76800 2 8 78125 1.73 1 16 78125 1.73 1 14 74821 ? 2.58 115200 1 22 113636 ? 1.36 1 11 113636 ? 1.36 1 9 116389 1.03 153600 1 16 156250 1.73 1 8 156250 1.73 ?? ? ? 230400 1 11 227273 ? 1.36 ?? ? ? ?? ? ? remark tps01, tps00: bits 7 and 6 of baud rate generator control register 0 (brgc0) (setting of base clock (f xclk )) k: value set by the mdl04 to mdl00 bits of brgc0 (k = 8, 9, 10, ..., 31) f x : x1 input clock oscillation frequency err: baud rate error
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 213 (4) permissible baud rate range during reception the permissible error from the baud rate at the transmission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 11-11. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax transfer rate of uart0 start bit bit 0 bit 1 bit 7 parity bit minimum permissible transfer rate maximum permissible transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 11-11, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (brgc0) after the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart0 k: set value of brgc0 fl: 1-bit data length margin of latch timing: 2 clocks
chapter 11 serial interface uart0 preliminary user ? s manual u15836ej2v1ud 214 minimum permissible transfer rate: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible transfer rate can be calculated as follows. 10 k + 2 21k ? 2 11 2 k2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 11-4. maximum/minimum permissible baud rate error division ratio (k) maximum permissible baud rate error minimum permissible baud rate error 8 +3.53% ? 3.61% 16 +4.14% ? 4.19% 24 +4.34% ? 4.38% 31 +4.44% ? 4.47% remarks 1. the accuracy of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the accuracy. 2. k: set value of brgc0 k ? 2 2k 21k + 2 2k 22k 21k + 2 flmax = 11 fl ? fl = fl 21k 2 20k 20k 21k ? 2
preliminary user?s manual u15836ej2v1ud 215 chapter 12 serial interface uart6 12.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial transfer is not executed and can enable a reduction in the power consumption. for details, refer to 12.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) bus. the functions of this mode are outlined below. ? two-pin configuration t x d6: transmit data output pin r x b6: receive data input pin ? data length of transfer data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? twelve operating clock inputs selectable ? msb- or lsb-first transfer selectable ? inverted transmission operation ? tuning break field transmission from 13 to 20 bits ? more than 11 bits can be identified for tuning break field reception (sbf reception flag provided). cautions 1. the default value of the t x d6 pin is the high level. exercise care when using the t x d6 pin as a port pin. 2. the t x d6 output inversion function inverts only the transmission side and not the reception side. to use this function, the reception side must be ready for reception of inverted data (it must be able to recognize a low-level start bit). 3. if clock supply to serial interface uart6 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before clock supply was stopped. the t x d6 pin also holds the value immediately before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power6 = 0, rxe6 = 0, and txe6 = 0. 4. if data is continuously transmitted, the transfer rate from the stop bit to the next start bit is extended two clocks. however, this does not affect the result of transfer because the reception side initializes the timing when it has detected a start bit. do not use the continuous transmission function if the interface is incorporated in lin.
chapter 12 serial interface uart6 preliminary user?s manual u15836ej2v1ud 216 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. lin uses single-master communication, and up to 15 slaves can be connected to one master. a lin slave is used to control switches, actuators, and sensors, which are connected to the lin master via the lin. the lin master is usually connected to a network such as can (controller area network). the lin bus is a single-wire type and each node is connected to the bus via a transceiver conforming to iso9141. the lin protocol defines that the master transmits frames that include baud rate information, and a slave receives this information and corrects the baud rate error to that of the master. therefore, communication is enabled if the baud rate error of the slave is within 15%. figures 12-1 and 12-2 outline the transmission and reception operations of lin. figure 12-1. lin transmission operation sleep bus tx6 intst6 note 4 wakeup signal frame tuning break field tuning field match field data field checksum field data field 8 bits note 3 note 1 13-bit note 2 sbf transmission 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. the tuning break field is output by hardware. the output width is equal to the bit length set by bits 5 to 3 (sbl62 to sbl60) of the asynchronous serial interface control register 6 (acicl6). if the output width needs to be adjusted more accurately, use baud rate generator control register 6 (brgc6). 3. the wakeup signal frame is substituted by 80h transfer in the 8-bit mode. 4. intst6 is output on completion of each transmission. it is also output when sbf is transmitted.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 217 figure 12-2. lin reception operation sleep bus rx6 reception interrupt (intsr6) edge detection (intp0) capture timer data reception wakeup signal frame tuning break field tuning field match field data filed data filed checksum field disable enable disable enable note 1 note 3 note 4 13 bits note 2 sbf reception id reception sf reception data reception data reception note 5 notes 1. the wakeup signal is detected at the edge of the pin, and enables uart6 and sets the sbf reception mode. 2. reception continues until the stop bit is detected. when 11 bits or more of sbf have been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if less than 11 bits of sbf have been detected, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. 3. if sbf reception has been completed correctly, an interrupt signal is output. this sbf reception completion interrupt enables the capture timer. detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of uart communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. 4. calculate the baud rate error from the value obtained from the capture timer, disable uart6 after sf reception, and then re-set baud rate generator control register 6 (brgc6). 5. distinguish the checksum field by software. also perform processing by software to initialize uart6 after reception of the checksum field and to set the sbf reception mode again.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 218 figure 12-3. port configuration for lin reception operation mpx rxd input intp0 input ti000 input p14/r x d6 p120/intp0 p00/ti000 port input selection control (isc0) 0: a output 1: b output a b q mpx port mode (pm14) a b q port latch (p14) mpx port mode (pm120) a b q port latch (p120) mpx port input selection control (isc1) 0: a output 1: b output a b q mpx port mode (pm00) a b q port latch (p00)
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 219 12.2 configuration of serial interface uart6 serial interface uart6 consists of the following hardware. table 12-1. configuration of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface transmission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6)
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 220 asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/p13 intst6 asynchronous serial interface control register 6 (asicl6) receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/p14 intsr6 intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) f x -f x /2 10 clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) to50/ti50/p17 (tm50 output) registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit figure 12-4. block diagram of serial interface uart6
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 221 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data converted by the receive shift register. each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (rxs6). if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the receive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation instruction. no data can be written to this register. reset input sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. transmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset input sets this register to ffh. cautions 1. do not write data to txb6 when bit 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of the asynchronous serial interface operation mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). however, if the same value is continuously transmitted in the transmission mode (power6 = 1 and txe6 = 1), the same value can be written. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first transmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. data is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the internal clock. txs6 cannot be directly manipulated by a program.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 222 12.3 registers controlling serial interface uart6 serial interface uart6 is controlled by the following six registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface reception error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) (1) asynchronous serial interface operation mode register 6 (asim6) this 8-bit register controls the serial transfer operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 12-5. format of asynchronous serial interface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol76543210 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operation of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 note 2 enables operation of the internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. operation of the internal operation clock is enabled at the second input clock after 1 is written to the power6 bit. caution at startup, set power6 to 1 and then set txe6 to 1. clear txe6 to 0 first, and then clear power6 to 0.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 223 figure 12-5. format of asynchronous serial interface operation mode register 6 (asim6) (2/2) rxe6 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception ps61 ps60 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurrence of reception completion interrupt in case of error 0 ? intsre6 ? occurs in case of error (at this time, intsr6 does not occur). 1 ? intsr6 ? occurs in case of error (at this time, intsre6 does not occur). note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set rxe6 to 1. clear rxe6 to 0 first, and then clear power6 to 0. 2. clear the txe6 and rxe6 bits to 0 before rewriting the ps61, ps60, and cl6 bits. 3. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 4. make sure that txe6 = 0 when rewriting the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 5. make sure that rxe6 = 0 when rewriting the isrm6 bit.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 224 (2) asynchronous serial interface reception error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. figure 12-6. format of asynchronous serial interface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol76543210 asis600000pe6fe6ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. for details, refer to chapter 25 cautions for wait.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 225 (3) asynchronous serial interface transmission status register 6 (asif6) this register indicates the status of transmission by serial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register can be set by an 8-bit memory manipulation instruction, and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. figure 12-7. format of asynchronous serial interface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol76543210 asif6000000txbf6txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is transferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer register 6 (txb6) (if data transmission is in progress) cautions 1. to continuously transmit data, write the data of the first byte to txb6, check that the value of the txbf6 flag is 0, and then write the data of the second byte to txb6. the operation is not guaranteed if data is written to txb6 while the txbf6 flag is 1. 2. while continuous transmission is being executed, check the value of the txsf6 flag after the transmission completion interrupt to determine the subsequent write processing to txb6. ? ? ? ? if txsf6 is 1: continuous transmission is in progress. data of 1 byte can be written. ? ? ? ? if txsf6 is 0: continuous transmission is complete. data of 2 bytes can be written. when doing so, observe caution 1 above. 3. while continuous transmission is in progress, check that txsf6 is 0 after the transmission completion interrupt, and then execute clearing (power6 = 0 or txe6 = 0). if clearing is executed while the txsf6 flag is 1, the transmit data cannot be guaranteed.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 226 (4) clock selection register 6 (cksr6) this register selects the base clock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 12-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol76543210 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk ) 0000f x (10 mhz) 0001f x /2 (5 mhz) 0010f x /2 2 (2.5 mhz) 0011f x /2 3 (1.25 mhz) 0100f x /2 4 (625 khz) 0101f x /2 5 (312.5 khz) 0110f x /2 6 (156.25 khz) 0111f x /2 7 (78.13 khz) 1000f x /2 8 (39.06 khz) 1001f x /2 9 (19.53 khz) 1010f x /2 10 (9.77 khz) 1 0 1 1 tm50 output other setting prohibited caution make sure power6 = 0 when rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 227 (5) baud rate generator control register 6 (brgc6) this register selects the base clock of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 12-9. format of baud rate generator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol76543210 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 00000 setting prohibited 000010008f xclk /8 000010019f xclk /9 0000101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11111100252f xclk /252 11111101253f xclk /253 11111110254f xclk /254 11111111255f xclk /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clock of the 8-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don't care
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 228 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial transfer operations of serial interface uart6. asicl6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. reset input sets this register to16h. remark asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). however, transfer is started by refresh because bit 6 (sbrt6) and bit 5 (sbtt6) of asicl6 are cleared to 0 when communication is complete (when an interrupt signal is generated). figure 12-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff58h after reset: 16h r/w symbol76543210 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger cautions 1. in the case of an sbf reception error, return the mode to the sbf reception mode and hold the status of the sbrf6 flag. 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. 3. the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (power6) and bit 6 (txe6) of asim6 = 1. 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 229 figure 12-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 msb/lsb-first transfer 0 msb-first transfer 1 lsb-first transfer txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 caution before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 230 12.4 operation of serial interface uart6 this section explains the two modes of serial interface uart6. 12.4.1 operation stop mode in this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. in addition, the pins can be used as ordinary port pins in this mode. (1) register setting the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff50h after reset: 01h r/w symbol76543210 asim6 power6 txe6 rxe6 ps61 ps60 cl sl6 isrm6 power6 enables/disables operation of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 note 2 enables operation of the internal operation clock. txe6 enables/disables transmission 0 disables transmission operation (synchronously resets the transmission circuit). 1 enables transmission rxe6 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. operation of the internal operation clock is enabled at the second input clock after 1 is written to the power6 bit. cautions 1. at startup, set power6 to 1 and then set txe6 to 1. clear txe6 to 0 first, and then clear power6 to 0. 2. at startup, set power6 to 1 and then set rxe6 to 1. clear rxe6 to 0 first, and then clear power6 to 0.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 231 12.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) register setting the uart mode is set by asynchronous serial interface operation mode register 6 (asim6), asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), clock selection register 6 (cksr6), baud rate generator control register 6 (brgc6), and asynchronous serial interface control register 6 (asicl6). (a) asynchronous serial interface operation mode register 6 (asim6) this 8-bit register controls the serial transfer operations of serial interface uart6. asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff50h after reset: 01h r/w symbol76543210 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operation of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit. 1 note 2 enables operation of the internal operation clock. txe6 enables/disables transmission 0 disables transmission (synchronously resets the transmission circuit). 1 enables transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. operation of the internal operation clock is enabled at the second input clock after 1 is written to the power6 bit. caution at startup, set power6 to 1 and then set txe6 to 1. clear txe6 to 0 first, and then clear power6 to 0.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 232 rxe6 enables/disables reception 0 disables reception (synchronously resets the reception circuit). 1 enables reception ps61 ps60 transmission operation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurrence of reception completion interrupt in case of error 0 ? intsre6 ? occurs in case of error (at this time, intsr6 does not occur). 1 ? intsr6 ? occurs in case of error (at this time, intsre6 does not occur). note if ? reception as 0 parity ? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set rxe6 to 1. clear rxe6 to 0 first, and then clear power6 to 0. 2. clear the txe6 and rxe6 bits to 0 before rewriting the ps61, ps60, and cl6 bits. 3. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 4. make sure that txe6 = 0 when rewriting the sl6 bit. reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the sl6 bit. 5. make sure that rxe6 = 0 when rewriting the isrm6 bit.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 233 (b) asynchronous serial interface reception error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register can be set by an 8-bit memory manipulation instruction and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. address: ff53h after reset: 00h r symbol76543210 asis600000pe6fe6ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. for details, refer to chapter 25 cautions for wait.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 234 (c) asynchronous serial interface transmission status register 6 (asif6) this register indicates the status of transmission by serial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register can be set by an 8-bit memory manipulation instruction, and is read-only. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. address: ff55h after reset: 00h r symbol76543210 asif6000000txbf6txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is transferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer register 6 (txb6) (if data transmission is in progress) cautions 1. to continuously transmit data, write the data of the first byte to txb6, check that the value of the txbf6 flag is 0, and then write the data of the second byte to txb6. the operation is not guaranteed if data is written to txb6 while the txbf6 flag is 1. 2. while continuous transmission is being executed, check the value of the txsf6 flag after the transmission completion interrupt to determine the subsequent write processing to txb6. ? ? ? ? if txsf6 is 1: continuous transmission is in progress. data of 1 byte can be written. ? ? ? ? if txsf6 is 0: continuous transmission is complete. data of 2 bytes can be written. when doing so, observe caution 1 above. 3. while continuous transmission is in progress, check that txsf6 is 0 after the transmission completion interrupt, and then execute clearing (power6 = 0 or txe6 = 0). if clearing is executed while the txsf6 flag is 1, the transmit data cannot be guaranteed.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 235 (d) asynchronous serial interface control register 6 (asicl6) this register controls the serial transfer operations of serial interface uart6. asicl6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. reset input sets this register to16h. remark asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). however, transfer is started by refresh because bit 6 (sbrt6) and bit 5 (sbtt6) of asicl6 are cleared to 0 when communication is complete (when an interrupt signal is generated). address: ff58h after reset: 16h r/w symbol76543210 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger cautions 1. in the case of an sbf reception error, return the mode to the sbf reception mode and hold the status of the sbrf6 flag. 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. 3. the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (power6) and bit 6 (txe6) of asim6 = 1. 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 236 sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 msb/lsb-first transfer 0 msb-first transfer 1 lsb-first transfer txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 caution before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 237 (2) communication operation (a) normal transmit/receive data format figure 12-11 shows the format of the transmit/receive data. figure 12-11. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface mode register 6 (asim6). whether data is transferred with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is specified by bit 0 (txdlv6) of asicl6.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 238 figure 12-12. example of normal uart transmit/receive data format 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, transfer data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, transfer data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, transfer data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: odd parity, stop bit: 2 bits, transfer data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, transfer data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 239 (b) parity types and operation the parity bit is used to detect a bit error in communication data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 when the device is incorporated in lin. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ? 1 ? : 1 if transmit data has an even number of bits that are ? 1 ? : 0 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ? 1 ? is odd. if transmit data has an odd number of bits that are ? 1 ? : 0 if transmit data has an even number of bits that are ? 1 ? : 1 ? reception the number of bits that are ? 1 ? in the receive data, including the parity bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ? 0 ? or ? 1 ? . (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no parity bit when data is received. because there is no parity bit, a parity error does not occur.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 240 (c) normal transmission the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1. if bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to transmit buffer register 6 (txb6). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb6 is transferred to transmit shift register 6 (txs6). after that, the data is sequentially output from txs6 to the t x d6 pin, starting from the lsb. when transmission is completed, a transmission completion interrupt request (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 12-13 shows the timing of the transmission completion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 12-13. normal transmission completion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 241 (d) continuous transmission when transmit shift register 6 (txs6) has started the shift operation, the next transmit data can be written to transmit buffer register 6 (txb6). as a result, data can be transmitted without intermission even while an interrupt that has occurred after transmission of one data frame is being serviced, thus an efficient communication rate is realized. to transmit data continuously, however, transmission processing must be executed while referencing bits 1 (txbf6) and 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6). caution when the device is incorporated in to lin, the continuous transmission function cannot be used. make sure that asynchronous serial interface transmission status register 6 (asif6) is 00h before writing transmit data to transmit buffer register 6 (txb6). table 12-2. write processing and writing to txb6 during execution of continuous transmission txbf6 txsf6 write processing during execution of continuous transmission writing to txb6 during execution of continuous transmission 0 0 enables writing 2 bytes or transmission completion processing enables writing 0 1 enables writing 1 byte enables writing 1 0 enables writing 2 bytes or transmission completion processing disables writing 1 1 enables writing 1 byte disables writing cautions 1. to continuously transmit data, write the data of the first byte to txb6, check that the value of the txbf6 flag is 0, and then write the data of the second byte to txb6. the operation is not guaranteed if data is written to txb6 while the txbf6 flag is 1. 2. while continuous transmission is being executed, check the value of the txsf6 flag after the transmission completion interrupt to determine the subsequent write processing to txb6. ? ? ? ? if txsf6 is 1: continuous transmission is in progress. data of 1 byte can be written. ? ? ? ? if txsf6 is 0: continuous transmission is completed. data of 2 bytes can be written. to do so, observe caution 1 above. 3. while continuous transmission is in progress, check that txsf6 is 0 after the transmission completion interrupt, and then execute clearing (power6 = 0 or txe6 = 0). if clearing is executed while the txsf6 flag is 1, the transmit data cannot be guaranteed.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 242 figure 12-14 shows the processing flow of continuous transmission. figure 12-14. processing flow of continuous transmission set registers. interrupt occurs. wait for interrupt. transfer executed necessary number of times? write transmit data to txb6 register. write transmit data to txb6 register. read asif6 register. txbf6 = 0? read asif6 register. txsf6 = 1? read asif6 register. txsf6 = 0? no no no no yes yes yes yes completion of transmission processing remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (transmit shift register data flag)
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 243 figure 12-15 shows the timing of starting continuous transmission, and figure 12-16 shows the timing of ending continuous transmission. figure 12-15. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which txbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 244 figure 12-16. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface mode register (asim6) txe6: bit 6 of asynchronous serial interface mode register (asim6)
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 245 (e) normal reception reception is enabled and the rxd6 pin input is sampled when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator starts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 12-17). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (rxs6) at the set baud rate. when the stop bit has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receive data is not written to rxb6. even if a parity error (pe6) or a framing error (fe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6/intsre6) is generated on completion of reception. figure 12-17. reception completion interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb6 cautions 1. be sure to read receive buffer register 6 (rxb6) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1 ? . the second stop bit is ignored. 3. be sure to read asynchronous serial interface reception error status register 6 (asis6) before reading rxb6.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 246 (f) reception error three types of errors may occur during reception: a parity error, framing error, or overrun error. if the error flag of asynchronous serial interface reception error status register 6 (asis6) is set as a result of data reception, a reception error interrupt request (intsr6/intsre6) is generated. which error has occurred during reception can be identified by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (refer to table 12-3 ). the contents of asis6 are reset to 0 when asis6 is read. table 12-3. cause of reception error reception error cause value of asis6 parity error the parity specified for transmission does not match the parity of the receive data. 04h framing error stop bit is not detected. 02h overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). 01h the error interrupt can be separated into intsr6 and intsre6 by clearing bit 0 (isrm6) of asynchronous serial interface mode register 6 (asim6) to 0. figure 12-18. reception error interrupt 1. if isrm6 is cleared to 0 (intsr6 and intsre6 are separated) (a) no error during reception (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during reception (b) error during reception intsre6 intsr6 intsre6 intsr6
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 247 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 12-19, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 12-19. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is incorporated in lin, the sbf (synchronous break field) transmission control function is used for transmission. for the transmission operation of lin, refer to figure 12-1 lin transmission operation . the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1. transmission is enabled when bit 6 (txe6) of asim6 is set to 1 next time, and sbf transmission operation is started when bit 5 (sbtt6) of asynchronous serial interface control register 6 (asicl6) is set to 1. after transmission has been started, the low levels of bits 13 to 20 (set by bits 4 to 2 (sbl62 to sbl60) of asicl6) are output. when sbf transmission has been completed, a transmission completion interrupt request (intst6) is generated, and sbtt6 is automatically cleared. after sbf transmission has been completed, the normal transmission mode is restored. transmission is stopped until the data to be transmitted next is written to transmit buffer register 6 (txb6) or sbtt6 is set to 1. figure 12-20. sbf transmission t x d6 intst6 sbtt6 12 34 56 78910111213stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6)
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 248 (i) sbf reception when the device is incorporated in lin, the sbf (synchronous break field) reception control function is used for reception. for the reception operation of lin, refer to figure 12-2 lin reception operation . reception is enabled when bit 7 (power6) of asynchronous serial interface mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. when the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt request (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatically cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 12-21. sbf reception 1. normal sbf reception (stop bit is detected with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detected with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ? 0 ? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 249 12.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of baud rate generator ? base clock (clock) the clock selected by bits 3 to 0 (tps63 to tps60) of clock selection register 6 (cksr6) is supplied to each module when bit 7 (power6) of the asynchronous serial interface mode register 6 (asim6) is 1. this clock is called the base clock (clock) and its frequency is called f xclk . clock is fixed to the low level when power6 = 0. ? transmission counter this counter stops, cleared to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. if there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, cleared to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected.
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 250 figure 12-22. configuration of baud rate generator clock (f xclk ) selector power6 8-bit counter match detector baud rate brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 to50/ti50/p17 (tm50 output) remark power6: bit 7 of asynchronous serial interface mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 251 (2) generation of serial clock a serial clock can be generated by using clock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) clock selection register 6 (cksr6) this register selects the base clock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff56h after reset: 00h r/w symbol76543210 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk ) 0000f x (10 mhz) 0001f x /2 (5 mhz) 0010f x /2 2 (2.5 mhz) 0011f x /2 3 (1.25 mhz) 0100f x /2 4 (625 khz) 0101f x /2 5 (312.5 khz) 0110f x /2 6 (156.25 khz) 0111f x /2 7 (78.13 khz) 1000f x /2 8 (39.06 khz) 1001f x /2 9 (19.53 khz) 1010f x /2 10 (9.77 khz) 1 0 1 1 tm50 output other setting prohibited caution make sure power6 = 0 when rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 252 (b) baud rate generator control register 6 (brgc6) this register selects the base clock of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). address: ff57h after reset: ffh r/w symbol76543210 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 00000 setting prohibited 000010008f xclk /8 000010019f xclk /9 0000101010f xclk /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11111100252f xclk /252 11111101253f xclk /253 11111110254f xclk /254 11111111255f xclk /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clock of the 8-bit counter divided by 2. remarks 1. f xclk : frequency of base clock (clock) selected by the tps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don't care
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 253 (c) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk : frequency of base clock (clock) selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of brgc6 register (k = 8, 9, 10, ..., 255) (d) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error during reception satisfies the range shown in (4) permissible baud rate range during reception. example: frequency of base clock (clock) = 20 mhz = 20,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 01000001b (k = 65) target baud rate = 153600 bps baud rate = 20 m/(2 65) = 20000000/(2 65) = 153,846 [bps] error = (153846/153600 ? 1) 100 = 0.160 [%] f xclk 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate)
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 254 (3) example of setting baud rate table 12-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 109 601 0.11 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 109 1201 0.11 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 109 2403 0.11 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 109 4805 0.11 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 109 9610 0.11 1h 109 9610 0.11 10400 2h 120 10417 0.16 2h 101 10371 0.28 1h 101 10475 ? 0.28 19200 1h 130 19231 0.16 1h 109 19200 0.11 0h 109 19220 0.11 31250 1h 80 31250 0.00 0h 134 31268 0.06 0h 67 31268 0.06 38400 0h 130 38462 0.16 0h 109 38440 0.11 0h 55 38090 ? 0.80 76800 0h 65 76923 0.16 0h 55 76182 ? 0.80 0h 27 77593 1.03 115200 0h 43 116279 0.94 0h 36 116388 1.03 0h 18 116389 1.03 153600 0h 33 151515 ? 1.36 0h 27 155185 1.03 0h 14 149643 ? 2.58 230400 0h 22 227272 ? 1.36 0h 18 232777 1.03 0h 9 232778 1.03 caution the maximum permissible frequency (f xclk ) of the base clock is 25 mhz. remark tps63 to tps60: bits 3 to 0 of clock selection register 6 (cksr6) (setting of base clock (f xclk )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 8, 9, 10, ..., 255) f x : x1 input clock oscillation frequency err: baud rate error
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 255 (4) permissible baud rate range during reception the permissible error from the baud rate at the transmission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 12-23. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax transfer rate of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible transfer rate maximum permissible transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 12-23, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (brgc6) after the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks minimum permissible transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 256 therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible transfer rate can be calculated as follows. 10 k + 2 21k ? 2 11 2 k2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 12-5. maximum/minimum permissible baud rate error division ratio (k) maximum permissible baud rate error minimum permissible baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the accuracy of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the accuracy. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k 2 20k 20k 21k ? 2
chapter 12 serial interface uart6 preliminary user ? s manual u15836ej2v1ud 257 (5) transfer rate during continuous transmission when data is continuously transmitted, the transfer rate from a stop bit to the next start bit is extended by two clocks from the normal value. however, the result of transfer is not affected because the timing is initialized on the reception side when the start bit is detected. figure 12-24. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk , the following expression is satisfied. flstp = fl + 2/f xclk therefore, the transfer rate during continuous transmission is: transfer rate = 11 fl + 2/f xclk
preliminary user?s manual u15836ej2v1ud 258 chapter 13 serial interface csi10 13.1 functions of serial interface csi10 serial interface csi10 has the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial i/o mode (msb/lsb-first selectable) this mode is used to transfer 8-bit data using three lines: a serial clock line (sck10) and two serial data lines (si10 and so10). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is useful for connecting peripheral i/os and display controllers having a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. 13.2 configuration of serial interface csi10 serial interface csi10 consists of the following hardware. table 13-1. configuration of serial interface csi10 item configuration registers transmit buffer register 10 (sotb10) serial i/o shift register 10 (sio10) control registers serial operation mode register 10 (csim10) serial clock selection register 10 (csic10)
chapter 13 serial interface csi10 preliminary user?s manual u15836ej2v1ud 259 figure 13-1. block diagram of serial interface csi10 8 8 so10/p12 intcsi10 si10/p11(/r x d0 note ) output selector f x /2 to f x /2 7 sck10/p10(/t x d0 note ) internal bus serial i/o shift register 10 (sio10) transmit buffer register 10 (sotb10) output latch transmit controller clock start/stop controller & clock phase controller selector transmit data controller note pd780102, 780103, and 78f0103 only (1) transmit buffer register 10 (sotb10) this register sets the transmit data. transmission/reception is started by writing data to sotb10 when bit 6 (trmd10) of serial operation mode register 10 (csim10) is 1. the data written to sotb10 is converted from parallel data into serial data by serial i/o shift register 10, and output to the serial output pin (so10). sotb10 can be written or read by an 8-bit memory manipulation instruction. reset input makes this register undefined. caution do not access sotb10 when csot10 = 1 (during serial communication). (2) serial i/o shift register 10 (sio10) this is an 8-bit register that converts data from parallel data into serial data or vice versa. this register can be read by an 8-bit memory manipulation instruction. reception is started by reading data from sio10 if bit 6 (trmd10) of serial operation mode register 10 (csim10) is 0. during reception, the data is read from the serial input pin (si10) to sio10. reset input clears this register to 00h. caution do not access sio10 when csot10 = 1 (during serial communication).
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 260 13.3 registers controlling serial interface csi10 the serial interface csi10 is controlled by the following two registers. ? serial operation mode register 10 (csim10) ? serial clock selection register 10 (csic10) (1) serial operation mode register 10 (csim10) this register is used to select the operation mode and enable or disable operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 13-2. format of serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol76543210 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 stops operation (si10/p11(/r x d0 note 2 ), so10/p12, and sck10/p10(/t x d0 note 2 ) pins can be used as general-purpose port pins). 1 enables operation (si10/p11(/r x d0 note 2 ), so10/p12, and sck10/p10(/t x d0 note 2 ) pins are at active level). trmd10 note 3 transmit/receive mode control 0 note 4 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 5 first bit specification 0msb 1lsb csot10 note 6 operation mode flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. pd780102, 780103, and 78f0103 only 3. do not rewrite trmd10 when csot10 = 1 (during serial communication). 4. the so10 pin is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 5. do not rewrite dir10 when csot10 = 1 (during serial communication). 6. csot10 is cleared if csie10 is set to 0 (operation stopped). caution be sure to set bit 5 to 0.
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 261 (2) serial clock selection register 10 (csic10) this register is used to select the phase of the data clock and set the count clock. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 13-3. format of serial clock selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol76543210 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 data clock phase selection type 00 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 01 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 10 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 11 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 cks102 cks101 cks100 csi10 count clock selection 000f x /2 (5 mhz) 001f x /2 2 (2.5 mhz) 010f x /2 3 (1.25 mhz) 011f x /2 4 (625 khz) 100f x /2 5 (312.5 khz) 101f x /2 6 (156.25 khz) 110f x /2 7 (78.13 khz) 1 1 1 external clock cautions 1. do not write to csic10 during communication or when p10/sck10 (/txd0 note ), p11/si10 (/rxd0 note ), and p12/so10 are used as general-purpose ports. 2. the phase type of the data clock is type 1 after reset. note pd780102, 780103, and 78f0103 only. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 262 13.4 operation of serial interface csi10 serial interface csi10 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 13.4.1 operation stop mode serial transfer is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p10/sck10(/t x d0 note ), p11/si10(/r x d0 note ), and p12/so10 pins can be used as ordinary i/o port pins in this mode. note pd780102, 780103, and 78f0103 only (1) register setting the operation stop mode is set by serial operation mode register 10 (csim10). (a) serial operation mode register 10 (csim10) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. address: ff80h after reset: 00h r/w symbol76543210 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 stops operation (si10/p11(/r x d0 note ), so10/p12, and sck10/p10(/t x d0 note ) pins can be used as general-purpose port pins). 1 enables operation (si10/p11(/r x d0 note ), so10/p12, and sck10/p10(/t x d0 note ) pins are at active level). note pd780102, 780103, and 78f0103 only 13.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connecting peripheral i/os and display controllers having a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. in this mode, communication is executed by using three lines: serial clock (sck10), serial output (so10), and serial input (si10) lines. (1) register setting the 3-wire serial i/o mode is set by serial operation mode register 10 (csim10) and serial clock selection register10 (csic10).
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 263 (a) serial operation mode register 10 (csim10) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. address: ff80h after reset: 00h r/w note 1 symbol76543210 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 stops operation (si10/p11(/r x d0 note 2 ), so10/p12, and sck10/p10(/t x d0 note 2 ) pins can be used as general-purpose port pins). 1 enables operation (si10/p11(/r x d0 note 2 ), so10/p12, and sck10/p10(/t x d0 note 2 ) pins are at active level). trmd10 note 3 transmit/receive mode control 0 note 4 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 5 first bit specification 0msb 1lsb csot10 note 6 operation mode flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. pd780102, 780103, and 78f0103 only 3. do not rewrite trmd10 when csot10 = 1 (during serial communication). 4. the so10 pin is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 5. do not rewrite dir10 when csot10 = 1 (during serial communication). 6. csot10 is cleared if csie10 is cleared to 0 (operation stopped). caution be sure to set bit 5 to 0.
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 264 (b) serial clock selection register 10 (csic10) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. address: ff81h after reset: 00h r/w symbol76543210 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 data clock phase selection type 00 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 01 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 10 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 11 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 cks102 cks101 cks100 csi10 count clock selection 000f x /2 (5 mhz) 001f x /2 2 (2.5 mhz) 010f x /2 3 (1.25 mhz) 011f x /2 4 (625 khz) 100f x /2 5 (312.5 khz) 101f x /2 6 (156.25 khz) 110f x /2 7 (78.13 khz) 1 1 1 external clock cautions 1. do not write to csic10 during communication or when p10/sck10 (/txd0 note ), p11/si10 (/rxd0 note ), and p12/so10 are used as general-purpose ports. 2. the phase type of the data clock is type 1 after reset. note pd780102, 780103, and 78f0103 only. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 265 (2) setting of ports <1> transmit/receive mode (a) to use externally input clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 2 (pm12) of port mode register 1: cleared to 0 bit 0 (pm10) of port mode register 1: set to 1 bit 2 (p12) of port 1: cleared to 0 (b) to use internal clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 2 (pm12) of port mode register 1: cleared to 0 bit 0 (pm10) of port mode register 1: cleared to 0 bit 2 (p12) of port 1: cleared to 0 bit 0 (p10) of port 1: set to 1 <2> receive mode (with transmission disabled) (a) to use externally input clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 0 (pm10) of port mode register 1: set to 1 (b) to use internal clock as system clock (sck10) bit 1 (pm11) of port mode register 1: set to 1 bit 0 (pm10) of port mode register 1: cleared to 0 bit 0 (p10) of port 1: set to 1 remark the transmit/receive mode or receive mode is selected by using bit 6 (trmd10) of serial operation mode register 10 (csim10).
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 266 (3) communication operation in the 3-wire serial i/o mode, data is transmitted or received in 8-bit units. each bit of the data is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd10) of serial operation mode register 10 (csim10) is 1. transmission/reception is started when a value is written to transmit buffer register 10 (sotb10). in addition, data can be received when bit 6 (trmd10) of serial operation mode register 10 (csim10) is 0. reception is started when data is read from serial i/o shift register 10 (sio10). after communication has been started, bit 0 (csot10) of csim10 is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif10) is set, and csot10 is cleared to 0. then the next communication is enabled. caution do not access the control register and data register when csot10 = 1 (during serial communication). figure 13-4. timing in 3-wire serial i/o mode (1/2) (1) transmission/reception timing (type 1; trmd10 = 1, dir10 = 0, ckp10 = 0, dap10 = 0) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb10. sck10 sotb10 sio10 csot10 csiif10 so10 si10 (receive aah) read/write trigger intcsi10
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 267 figure 13-4. timing in 3-wire serial i/o mode (2/2) (2) transmission/reception timing (type 2; trmd10 = 1, dir10 = 0, ckp10 = 0, dap10 = 1) abh 56h adh 5ah b5h 6ah d5h sck10 sotb10 sio10 csot10 csiif10 so10 si10 (receives aah) aah 55h (communication data) 55h is written to sotb10. read/write trigger intcsi10
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 268 figure 13-5. timing of clock/data phase (a) type 1; ckp10 = 0, dap10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (b) type 2; ckp10 = 0, dap10 = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (c) type 3; ckp10 = 1, dap10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (d) type 4; ckp10 = 1, dap10 = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 269 (4) timing of output to so10 pin (first bit) when communication is started, the value of transmit buffer register 10 (sotb10) is output from the so10 pin. the output operation of the first bit at this time is described below. figure 13-6. output operation of first bit (1) when ckp10 = 0, dap10 = 0 (or ckp10 = 1, dap10 = 0) sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 first bit 2nd bit output latch the first bit is directly latched by the sotb10 register to the output latch at the falling (or rising) edge of the sck10, and output from the so10 pin via an output selector. then, the value of the sotb10 register is transferred to the sio10 register at the next rising (or falling) edge of sck10, and shifted one bit. at the same time, the first bit of the receive data is stored in the sio10 register via the si10 pin. the second and subsequent bits are latched by the sio10 register to the output latch at the next falling (or rising) edge of sck10, and the data is output from the so10 pin. (2) when ckp10 = 0, dap10 = 1 (or ckp10 = 1, dap10 = 1) sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 first bit 2nd bit 3rd bit output latch the first bit is directly latched by the sotb10 register at the falling edge of the write signal of the sotb10 register or the read signal of the sio10 register, and output from the so10 pin via an output selector. then, the value of the sotb10 register is transferred to the sio10 register at the next rising (or falling) edge of sck10, and shifted one bit. at the same time, the first bit of the receive data is stored in the sio10 register via the si10 pin. the second and subsequent bits are latched by the sio10 register to the output latch at the next falling (or rising) edge of sck10, and the data is output from the so10 pin.
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 270 (5) output value of so10 pin (last bit) after communication has been completed, the so10 pin holds the output value of the last bit. figure 13-7. output value of so10 pin (last bit) (1) type 1; when ckp10 = 0 and dap10 = 0 (or ckp10 = 1, dap10 = 0) sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 ( next request is issued.) last bit output latch (2) type 2; when ckp10 = 0 and dap10 = 1 (or ckp10 = 1, dap10 = 1) sck10 sotb10 sio10 so10 last bit writing to sotb10 or reading from sio10 ( next request is issued.) output latch
chapter 13 serial interface csi10 preliminary user ? s manual u15836ej2v1ud 271 (6) so10 pin the status of the so10 pin is as follows if bit 7 (csie10) of serial operation mode register 10 (csim10) is cleared to 0. table 13-2. so10 pin status trmd10 dap10 dir10 so10 pin trmd10 = 0 note ?? outputs low level note . dap10 = 0 ? value of so10 latch (low-level output) dir10 = 0 value of bit 7 of sotb10 trmd10 = 1 dap10 = 1 dir10 = 1 value of bit 0 of sotb10 note status after reset caution if a value is written to trmd10, dap10, and dir10, the output value of the so10 pin changes.
preliminary user?s manual u15836ej2v1ud 272 chapter 14 interrupt functions 14.1 interrupt function types the following two types of interrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). multiple interrupt servicing of high-priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupt is serviced according to its predetermined priority (see table 14-1 ). a standby release signal is generated. six external interrupt requests and 12 internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 14.2 interrupt sources and configuration a total of 19 interrupt sources exist for maskable and software interrupts. in addition, maximum total of 5 reset sources are also provided (see table 14-1 ).
chapter 14 interrupt functions preliminary user?s manual u15836ej2v1ud 273 table 14-1. interrupt source list interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 note 4 end of csi10 transfer/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and crh1 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and crh0 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified) 0022h 16 intad end of a/d conversion 0024h maskable 17 intsr0 note 4 end of uart0 reception internal 0026h (a) software ? brk brk instruction execution ? 003eh (c) reset reset input poc power-on-clear note 5 lvi low-voltage detection note 6 clock monitor x1 input clock stop detection reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority is the priority applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 17 is the lowest. 2. basic configuration types (a) to (c) correspond to (a) to (c) in figure 14-1. 3. when bit 1 (lvimd) = 0 is selected for the low-voltage detection register (lvim). 4. the interrupt sources intst0 and intsr0 are available only in the pd780102, 780103, and 78f0103. 5. when ?poc used? is selected by mask option. 6. when lvimd = 1 is selected.
chapter 14 interrupt functions preliminary user?s manual u15836ej2v1ud 274 figure 14-1. basic configuration of interrupt function (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable interrupt (intp0 to intp5) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector (c) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 275 14.3 registers controlling interrupt function the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specification flag register (pr0l, pr0h, pr1l) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 14-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 14-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt request register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 dualif0 note 2 dualmk0 note 2 dualpr0 note 2 intst0 note 1 csiif10 note 3 csimk10 note 3 csipr10 note 3 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 intad adif 1f1l admk mk1l adpr pr1l intsr0 note 1 srif0 note 1 srmk0 note 1 srpr0 note 1 notes 1. pd780102, 780103, and 78f0103 only. 2. flag name in the pd780102, 780103, and 78f0103. if either of the two types of interrupt sources is generated, these flags are set (1). 3. flag name in the pd780101
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 276 (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are read with a 16-bit memory manipulation instruction. reset input sets these registers to 00h. figure 14-2. format of interrupt request flag register (if0l, if0h, if1l) address: ffe0h after reset: 00h r/w symbol76543210 if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol76543210 if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 note 1 stif6 srif6 address: ffe2h after reset: 00h r/w symbol76543210 if1l 0 0 0 0 0 0 srif0 note 2 adif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. this is csiif10 in the pd780101. 2. incorporated only in the pd780102, 780103, and 78f0103. cautions 1. be sure to set bits 2 to 7 of if1l to 0. 2. when operating a timer, serial interface, or a/d converter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 3. when an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 277 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form a 16-bit register mk0, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 14-3. format of interrupt mask flag register (mk0l, mk0h, mk1l) address: ffe4h after reset: ffh r/w symbol76543210 mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol76543210 mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 note 1 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol76543210 mk1l 1 1 1 1 1 1 srmk0 note 2 admk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. this is csimk10 in the pd780101. 2. incorporated only in the pd780102, 780103, and 78f0103. cautions 1. because ports 3 and 12 have an alternate function as external interrupt request inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 2. be sure to set bits 2 to 7 of mk1l to 1.
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 278 (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flag registers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 14-4. format of priority specification flag register (pr0l, pr0h, pr1l) address: ffe8h after reset: ffh r/w symbol76543210 pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol76543210 pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpro note 1 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol76543210 pr1l 1 1 1 1 1 1 srpr0 note 2 adpr xxprx priority level selection 0 high priority level 1 low priority level notes 1. this is csipri0 in the pd780101. 2. incorporated only in the pd780102, 780103, and 78f0103. caution be sure to set bits 2 to 7 of pr1l to 1.
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 279 (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp5. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 14-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol76543210 egp 0 0 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol76543210 egn 0 0 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 5) 0 0 interrupt disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 280 (5) program status word (psw) the program status word is a register used to hold the instruction execution result and the current status for an interrupt request. the ie flag that sets maskable interrupt enable/disable and the isp flag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 14-6. format of program status word 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disable priority of interrupt currently being serviced interrupt request acknowledgement enable/disable used when normal instruction is executed enable interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 281 14.4 interrupt servicing operations 14.4.1 maskable interrupt acknowledgement a maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 14-3 below. for the interrupt request acknowledgement timing, see figures 14-8 and 14-9 . table 14-3. time from generation of maskable interrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 14-7 shows the interrupt request acknowledgement algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data determined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction.
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 282 figure 14-7. interrupt request acknowledgement processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgement of maskable interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing)
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 283 figure 14-8. interrupt request acknowledgement timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 14-9. interrupt request acknowledgement timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 14.4.2 software interrupt request acknowledgement a software interrupt acknowledge is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possible by using the retb instruction. caution do not use the reti instruction for restoring from the software interrupt.
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 284 14.4.3 multiple interrupt servicing multiple interrupt occurs when another interrupt request is acknowledged during execution of an interrupt. multiple interrupt does not occur unless the interrupt request acknowledgement enabled state is selected (ie = 1). also, when an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgement. moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt. interrupt requests that are not enabled because interrupts are in the interrupt disabled state or they have a lower priority are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of one main processing instruction execution. table 14-4 shows interrupt requests enabled for multiple interrupt and figure 14-10 shows multiple interrupt examples. table 14-4. interrupt request enabled for multiple interrupt during interrupt servicing multiple interrupt request maskable interrupt request pr = 0 pr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 isp = 0 maskable interrupt isp = 1 software interrupt remarks 1. : multiple interrupt enabled 2. : multiple interrupt disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgement is disabled. ie = 1: interrupt request acknowledgement is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0: higher priority level pr = 1: lower priority level
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 285 figure 14-10. examples of multiple interrupt servicing (1/2) example 1. multiple interrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgement. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgement disabled
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 286 figure 14-10. examples of multiple interrupt servicing (2/2) example 3. multiple interrupt servicing does not occur because interrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 interrupts are not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgement disabled
chapter 14 interrupt functions preliminary user ? s manual u15836ej2v1ud 287 14.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, and pr1l registers. caution the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. figure 14-11 shows the timing at which interrupt requests are held pending. figure 14-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (instruction request).
preliminary user?s manual u15836ej2v1ud 288 chapter 15 standby function 15.1 standby function and configuration 15.1.1 standby function table 15-1. relationship between halt and stop modes and clock x1 input clock ring-osc clock cpu clock halt mode oscillation continues oscillation continues operation stopped stop mode oscillation stopped oscillation continues operation stopped the standby function is designed to reduce the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. the x1 input clock and ring-osc clock oscillators continue oscillating. in this mode, current consumption is not decreased as much as in the stop mode. however, the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the x1 input clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu power consumption. because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to secure the oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. when shifting to the stop mode, be sure to stop the peripheral hardware operation before executing stop instruction. 2. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. 3. ring-osc clock oscillation cannot be stopped in the stop mode. however, when the ring- osc clock is used as the cpu clock, operation is stopped for 17/f r (s) after stop mode is released.
chapter 15 standby function preliminary user?s manual u15836ej2v1ud 289 figure 15-1. operation timing when stop mode is released ring-osc clock is used as cpu clock when stop instruction is executed ring-osc clock x1 input clock x1 input clock is used as cpu clock when stop instruction is executed stop mode release stop mode operation stopped (17/f r ) clock switched by software ring-osc clock x1 input clock halt status (oscillation stabilization time set by osts) x1 input clock
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 290 15.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time counter status register (ostc) ? oscillation stabilization time select register (osts) (1) oscillation stabilization time counter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. reset input, stop instruction, and mstop =1 clear ostc to 00h. figure 15-2. format of oscillation stabilization time counter status register (ostc) address: ffa3h after reset: 00h r symbol76543210 ostc 0 0 0 most11 most13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 100002 11 /f xp min. (204.8 s min.) 110002 13 /f xp min. (819.2 s min.) 111002 14 /f xp min. (1.64 ms min.) 111102 15 /f xp min. (3.27 ms min.) 111112 16 /f xp min. (6.55 ms min.) caution after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. remarks 1. values in parentheses are for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 291 (2) oscillation stabilization time select register (osts) this register is used to select the oscillation stabilization time of the x1 input clock when stop mode is released. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 15-3. format of oscillation stabilization time select register (osts) address: ffa4h after reset: 05h r/w symbol76543210 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 0012 11 /f xp (204.8 s) 0102 13 /f xp (819.2 s) 0112 14 /f xp (1.64 ms) 1002 15 /f xp (3.27 ms) 1012 16 /f xp (6.55 ms) other setting prohibited cautions 1. if the stop mode is entered and then released while the ring-osc is being used as the cpu clock, set the oscillation stabilization time as follows. ? ? ? ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the setting value of osts can be initialized (to 05h) only by a reset. therefore, note that the x1 oscillation stabilization time counter counts up to the set value of osts after stop mode is released when the ring-osc is used as the cpu clock. 2. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. stop mode release x1 pin voltage waveform v ss a remarks 1. values in parentheses are for operation with f xp = 10 mhz. 2. f xp : x1 input clock oscillation frequency
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 292 15.2 standby function operation 15.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. halt mode can be set regardless of whether cpu clock before the setting was the x1 input clock or ring-osc clock. the operating statuses in the halt mode are shown below. table 15-2. operating statuses in halt mode when halt instruction is executed while cpu is operating using x1 input clock when halt instruction is executed while cpu is operating using ring-osc clock halt mode setting item ring-osc oscillation continues ring-osc oscillation stopped note 1 x1 input clock oscillation continues x1 input clock oscillation stopped system clock both x1 input clock and ring-osc clock can be oscillated. clock supply to cpu stops cpu operation stopped port (output latch) holds the status before halt mode is set 16-bit timer/event counter 00 operable operation stopped 8-bit timer/event counter 50 operable operable only when ti50 is selected as count clock h0 operable operable only when to50 is selected as count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operable only when f r /2 7 is selected as count clock watchdog timer operable operable only when x1 input clock is selected as operation clock operable operable only when ring-osc clock input is selected as operation clock a/d converter operable operation disabled uart0 note 2 operable uart6 operable operable only when to50 is selected as serial clock during 8-bit timer/event counter 50 operation serial interface csi10 operable operable only when external sck10 is selected as serial clock clock monitor operable operation stopped operable operation stopped power-on-clear function note 3 operable low-voltage detection function operable external interrupt operable notes 1. when ? stopped by software ? is selected for ring-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 20 mask options ). 2. pd780102, 780103, and 78f0103 only. 3. when ? poc used ? is selected by mask option (for mask options, see chapter 20 mask options ).
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 293 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 15-4. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation x1 input clock or ring-osc clock cpu clock standby release signal interrupt request remarks 1. the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 294 (b) release by reset input when the reset signal is input, halt mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. figure 15-5. halt mode release by reset input (1) when x1 input clock is used as cpu clock halt instruction reset signal x1 input clock operating mode halt mode reset period oscillation stopped operating mode oscillates oscillation stopped oscillates cpu clock (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/ f r ) (2) when ring-osc clock is used as cpu clock halt instruction reset signal ring-osc clock operating mode halt mode reset period oscillation stopped operating mode oscillates oscillation stopped oscillates cpu clock (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency table 15-3. operation after halt mode release release source mk pr ie isp operation 000 next address instruction execution 001 interrupt servicing execution 0101 01 0 next address instruction execution 0111interrupt servicing execution maskable interrupt request 1 halt mode held reset input ?? reset processing : don't care
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 295 15.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing the stop instruction. it can be set regardless of whether the cpu clock before the setting was the x1 input clock or ring-osc clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (osts) has elapsed. the operating statuses in the stop mode are shown below. table 15-4. operating statuses in stop mode when stop instruction is executed while cpu is operating using x1 input clock halt mode setting item ring-osc oscillation continues ring-osc oscillation stopped note 1 when stop instruction is executed while cpu is operating using ring-osc clock system clock only x1 input clock oscillation stops. clock supply to cpu stops cpu operation stopped port (output latch) holds the status before stop mode is set 16-bit timer/event counter 00 operation stopped 8-bit timer/event counter 50 operable only when ti50 is selected as count clock h0 operable when to50 is selected as count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable note 2 operation stopped operable note 2 watchdog timer operable only when ring-osc clock input is selected as operation clock operation stopped operable only when ring-osc clock input is selected as operation clock a/d converter operation stopped uart0 note 3 uart6 operable only when to50 is selected as count clock during 8-bit timer/event counter 50 operation serial interface csi10 operable only when external sck10 is selected as serial clock clock monitor operation stopped power-on-clear function note 4 operable low-voltage detection function operable external interrupt operable notes 1. when ? stopped by software ? is selected for ring-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 20 mask options ). 2. operable only when f r /2 7 is selected as count clock. 3. pd780102, 780103, and 78f0103 only. 4. when ? poc used ? is selected by a mask option (for mask options, see chapter 20 mask options ).
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 296 (2) stop mode release the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 15-6. stop mode release by interrupt request generation (1) when x1 input clock is used as cpu clock operating mode operating mode oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait status oscillation stopped x1 input clock cpu clock oscillation stabilization time (set by osts) (x1 input clock) (x1 input clock) (2) when ring-osc clock is used as cpu clock operating mode operating mode oscillates stop instruction stop mode standby release signal ring-osc clock cpu clock (ring-osc clock) oscillation stopped (17/ f r ) (ring-osc clock) remark the broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
chapter 15 standby function preliminary user ? s manual u15836ej2v1ud 297 (b) release by reset input when the reset signal is input, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 15-7. stop mode release by reset input (1) when x1 input clock is used as cpu clock stop instruction reset signal x1 input clock operating mode stop mode reset period oscillation stopped operating mode oscillates oscillation stopped oscillates cpu clock (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) oscillation stopped (2) when ring-osc clock is used as cpu clock stop instruction reset signal ring-osc clock operating mode stop mode reset period oscillation stopped operating mode oscillates oscillation stopped oscillates cpu clock (ring-osc clock) (17/f r ) (ring-osc clock) table 15-5. operation after stop mode release release source mk pr ie isp operation 000 next address instruction execution 001 interrupt servicing execution 0101 01 0 next address instruction execution 0111interrupt servicing execution maskable interrupt request 1 stop mode held reset input ?? reset processing : don't care
preliminary user?s manual u15836ej2v1ud 298 chapter 16 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by clock monitor x1 clock oscillation stop detection (4) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (5) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h when the reset signal is input. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, x1 clock oscillation stop is detected by the clock monitor, or by poc and lvi circuit voltage detection, and each hardware is set to the status shown in table 16-1. each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for p130, which is low-level output. when a high level is input to the reset pin, the reset is released and program execution starts using the ring- osc clock after the cpu clock operation has stopped for 17/f r (s). reset by the watchdog timer or clock timer source is automatically released and program execution starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see figures 16-2 to 16-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after reset, and program execution starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see chapter 18 power-on-clear circuit and chapter 19 low-voltage detector ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 input clock and ring-osc clock stop oscillating. 3. when the stop mode is released by a reset, the stop mode contents are held during reset input. however, the port pins become high-impedance, except for p130, which is set to low- level output.
chapter 16 reset function preliminary user?s manual u15836ej2v1ud 299 figure 16-1. block diagram of reset function clmrf lvirf wdtrf reset control flag register (resf) internal bus wdtres (watchdog timer reset signal) clmresb (clock monitor reset signal) reset pocresb (power-on-clear circuit reset signal) lviresb (low-voltage detector reset signal) reset signal reset signal reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal reset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register
chapter 16 reset function preliminary user ? s manual u15836ej2v1ud 300 figure 16-2. timing of reset by reset input delay delay hi-z note normal operation reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 reset internal reset signal port pin cpu clock figure 16-3. timing of reset due to watchdog timer overflow hi-z note normal operation reset period (oscillation stop) x1 watchdog timer overflow internal reset signal port pin operation stop (17/f r ) normal operation (reset processing, ring-osc clock) cpu clock caution a watchdog timer internal reset resets the watchdog timer. figure 16-4. timing of reset in stop mode by reset input delay delay hi-z note normal operation x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) cpu clock note port pins become high-impedance, except for p130, which is set to low-level output. remark for the reset timing of the power-on-clear circuit and low-voltage detector, see chapter 18 power- on-clear circuit and chapter 19 low-voltage detector .
chapter 16 reset function preliminary user ? s manual u15836ej2v1ud 301 table 16-1. hardware statuses after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p3, p12, p13) (output latches) 00h port mode registers (pm0, pm1, pm3, pm12) ffh pull-up resistor option registers (pu0, pu1, pu3, pu12) 00h input switch control register (isc) 00h internal memory size switching register (ims) cfh internal expansion ram size switching register (ixs) 0ch processor clock control register (pcc) 00h ring-osc mode register (rcm) 00h main clock mode register (mcm) 00h main osc control register (moc) 00h oscillation stabilization time select register (osts) 05h oscillation stabilization time counter status register (ostc) 00h timer counter 00 (tm00) 0000h capture/compare registers 000, 010 (cr000, cr010) 0000h mode control register 00 (tmc00) 00h prescaler mode register 00 (prm00) 00h capture/compare control register 00 (crc00) 00h 16-bit timer/event counter 00 timer output control register 00 (toc00) 00h timer counter 50 (tm50) 00h compare register 50 (cr50) 00h timer clock selection register 50 (tcl50) 00h 8-bit timer/event counter 50 mode control register 50 (tmc50) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h 8-bit timer/event counters h0, h1 mode registers (tmhmd0, tmhmd1) 00h mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result register (adcr) 0000h mode register (adm) 00h analog input channel specification register (ads) 00h power-fail comparison mode register (pfm) 00h a/d converter power-fail comparison threshold register (pft) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset.
chapter 16 reset function preliminary user ? s manual u15836ej2v1ud 302 table 16-1. hardware statuses after reset (2/2) hardware status after reset receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface operation mode register 0 (asim0) 01h serial interface uart0 note 1 baud rate generator control register 0 (brgc0) 1fh receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface operation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmission error status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh serial interface uart6 asynchronous serial interface control register 6 (asicl6) 16h transmit buffer register 10 (sotb10) undefined serial i/o shift register 10 (sio10) 00h serial operation mode register 10 (csim10) 00h serial interface csi10 serial clock selection register 10 (csic10) 00h clock monitor mode register (clm) 00h reset function reset control flag register (resf) 00h note 2 low-voltage detection register (lvim) 00h note 2 low-voltage detector low-voltage detection level selection register (lvis) 00h note 2 request flag registers 0l, 0h, 1l (if0l, if0h, if1l) 00h mask flag registers 0l, 0h, 1l (mk0l, mk0h, mk1l) ffh priority specification flag registers 0l, 0h, 1l (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h notes 1. pd780102, 780103, and 78f0103 only. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by clm reset by lvi resf see table 16-2 . lvim lvis cleared (00h) cleared (00h) cleared (00h) cleared (00h) held
chapter 16 reset function preliminary user ? s manual u15836ej2v1ud 303 16.1 register for confirming reset source many internal reset generation sources exist in the 78k0/kb1 series. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc) circuit, and reading resf clear resf to 00h. figure 16-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol76543210 resf 0 0 0 wdtrf 0 0 clmrf lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. clmrf internal reset request by clock monitor (clm) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bit memory manipulation instruction. the status of resf when a reset request is generated is shown in table 16-2. table 16-2. resf status when reset request is generated reset source register reset input reset by poc reset by wdt reset by clm reset by lvi wdtrf set (1) held held clmrf held set (1) held lvirf cleared (0) cleared (0) held held set (1)
preliminary user?s manual u15836ej2v1ud 304 chapter 17 clock monitor 17.1 functions of clock monitor the clock monitor samples the x1 input clock using the on-chip ring-osc, and generates an internal reset signal when the x1 input clock is stopped. when a reset signal is generated by the clock monitor, bit 1 (clmrf) of the reset control flag register (resf) is set to 1. for details of resf, refer to chapter 16 reset function . the clock monitor automatically stops under the following conditions. ? in stop mode and during the oscillation stabilization time ? when the x1 input clock is stopped (mstop = 1, when cpu operates on the ring-osc clock) ? oscillation stabilization time after reset is released ? when the ring-osc clock is stopped remark mstop: bit 7 of the main osc control register (moc) 17.2 configuration of clock monitor clock monitor consists of the following hardware. table 17-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 17-1. block diagram of clock monitor x1 input clock ring-osc clock internal reset signal enable/disable clme clock monitor mode register (clm)
chapter 17 clock monitor preliminary user ? s manual u15836ej2v1ud 305 17.3 registers controlling clock monitor clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) this register sets the operation mode of the clock monitor. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 17-2. format of clock monitor mode register (clm) 7 0 clme 0 1 symbol clm address: ffa9h after reset: 00h r/w 6 0 disables clock monitor operation enables clock monitor operation 5 0 4 0 3 0 enables/disables clock monitor operation 2 0 1 0 0 clme cautions 1. once bit 0 (clme) is set to 1, it cannot be cleared to 0 except by reset input and the internal reset signal. 2. if the reset signal is generated by the clock monitor, clme is cleared to 0 and bit 1 (clmrf) of the reset control flag register (resf) is set to 1. clmrf is read by software and then automatically cleared to 0. clmrf is cleared under the following conditions. ? ? ? ? reset input ? ? ? ? internal reset signal generation by poc ? ? ? ? after read by software
chapter 17 clock monitor preliminary user ? s manual u15836ej2v1ud 306 17.4 operation of clock monitor this section explains the functions of the clock monitor. the start and stop conditions are as follows. set bit 0 (clme) of the clock monitor mode register (clm) to operation enabled (1). ? in stop mode and during the oscillation stabilization time ? when the x1 input clock is stopped (mstop = 1, when the cpu operates on the ring-osc clock) ? oscillation stabilization time after reset is released ? when the ring-osc clock is stopped remark mstop: bit 7 of the main osc control register (moc) table 17-2. operation status of clock monitor (when clme =1) cpu operation clock operation mode x1 input clock status ring-osc clock status clock monitor status oscillating stop mode stopped stopped note oscillating reset input stopped note stopped oscillating operating x1 input clock halt mode oscillating stopped note stopped stop mode reset input stopped oscillating stopped oscillating operating ring-osc clock halt mode stopped stopped note the ring-osc clock is stopped only when the "ring-osc can be stopped by software" is selected by a mask option. if "ring-osc cannot be stopped" is selected, the ring-osc clock cannot be stopped. the clock monitor timing is as shown in figure 17-3.
chapter 17 clock monitor preliminary user ? s manual u15836ej2v1ud 307 figure 17-3. timing of clock monitor (1/3) (1) when internal reset is executed by oscillation stop of x1 input clock 4 clocks of ring-osc clock x1 input clock ring-osc clock internal reset signal clme clmrf note note clmrf is read by software and then automatically cleared to 0. clmrf is cleared under the following conditions. ? reset input ? internal reset signal generation by poc ? after read by software (2) clock monitor status after stop mode is released (clme = 1 is set when cpu clock operates on x1 input clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring clme ring-osc clock x1 input clock cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time.
chapter 17 clock monitor preliminary user ? s manual u15836ej2v1ud 308 figure 17-3. timing of clock monitor (2/3) (3) clock monitor status after stop mode is released (clme = 1 is set when cpu clock operates on ring-osc clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring stopped monitoring clme ring-osc clock x1 input clock cpu operation normal operation 17 clocks clock supply stopped normal operation (ring-osc clock) oscillation stopped oscillation stabilization time (set by osts register) stop when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. (4) clock monitor status after reset input (clme = 1 is set after reset input and during x1 input clock oscillation stabilization time) cpu operation clock monitor status clme ring-osc clock x1 input clock reset oscillation stopped oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring waiting for end of oscillation stabilization time oscillation stopped 17 clocks set to 1 by software reset reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. even if clme is set to 1 by software during the oscillation stabilization time of the x1 input clock, monitoring is not performed until the oscillation stabilization time of the x1 input clock ends. monitoring is automatically started at the end of the oscillation stabilization time.
chapter 17 clock monitor preliminary user ? s manual u15836ej2v1ud 309 figure 17-3. timing of clock monitor (3/3) (5) clock monitor status after reset input (clme = 1 is set after reset input and at the end of x1 input clock oscillation stabilization time) cpu operation clock monitor status clme reset ring-osc clock x1 input clock reset oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring 17 clocks set to 1 by software reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. when clme is set to 1 by software at the end of the oscillation stabilization time of the x1 input clock, monitoring is started.
preliminary user?s manual u15836ej2v1ud 310 chapter 18 power-on-clear circuit 18.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. ? compares supply voltage (v dd ) and detection voltage (v poc ), and generates internal reset signal when v dd < v poc . ? the following can be selected by a mask option. ? poc disabled ? poc used (detection voltage: v poc = 2.85 v 0.15 v) ? poc used (detection voltage: v poc = 3.5 v 0.2 v) caution if an internal reset signal is generated in the poc circuit, the reset control flag register (resf) is cleared to 00h. remark this product incorporates multiple hardware functions that generate an internal reset signal. a flag that indicates the reset cause is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt), low-voltage-detection (lvi) circuit, or clock monitor. resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt, lvi, or the clock monitor. for details of the resf, refer to chapter 16 reset function .
chapter 18 power-on-clear circuit preliminary user?s manual u15836ej2v1ud 311 18.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 18-1. figure 18-1. block diagram of power-on-clear circuit ? + detection voltage source (v poc ) internal reset signal v dd v dd 18.3 operation of power-on-clear circuit in the power-on-clear circuit, the supply voltage (v dd ) and detection voltage (v poc ) are compared, and when v dd < v poc , an internal reset signal is generated. figure 18-2. timing of internal reset signal generation in power-on-clear circuit time supply voltage (v dd ) poc detection voltage (v poc ) 2.7 v internal reset signal
chapter 18 power-on-clear circuit preliminary user?s manual u15836ej2v1ud 312 18.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. figure 18-3. example of software processing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of poc detection voltage yes power-on-clear ; the ring-osc clock is set as the cpu clock when the reset signal is generated ; the cause of reset (power-on-clear, wdt, lvi, or clock monitor) can be identified by the resf register. ; change the cpu clock from the ring-osc clock to the x1 input clock. ; check the stabilization of oscillation of the x1 input clock by using the ostc register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports ; 8-bit timer h1 can operate with the ring-osc clock. source: f r (240 khz)/2 7 compare 100 = 53 ms (f r : ring-osc clock oscillation frequency) no note 1 reset checking cause of reset note 2 check stabilization of oscillation change cpu clock 50 ms has passed? (tmifh1 = 1?) initialization processing start timer (set to 50 ms) notes 1. if reset is generated again during this period, initialization processing is not started. 2. a flowchart is shown on the next page.
chapter 18 power-on-clear circuit preliminary user?s manual u15836ej2v1ud 313 figure 18-3. example of software processing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by clock monitor reset processing by low-voltage detector no no wdtrf of resf register = 1? clmrf of resf register = 1? lvirf of resf register = 1? yes yes
preliminary user?s manual u15836ej2v1ud 314 chapter 19 low-voltage detector 19.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? compares supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . ? detection levels (five levels) of supply voltage can be changed by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for details of resf, refer to chapter 16 reset function . 19.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown below. figure 19-1. block diagram of low-voltage detector lvis1 lvis0 lvion lvie ? + detection voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvimd lvif internal reset signal 3 low-voltage detection level selector selector
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 315 19.3 registers controlling low-voltage detector the low-voltage detector is controlled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) (1) low-voltage detection register (lvim) this register sets low-voltage detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction.
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 316 figure 19-2. format of low-voltage detection register (lvim) 0 lvif 1 lvimd 2 0 3 0 4 lvie 5 0 6 0 7 lvion symbol lvim address: ffbeh after reset: 00h r/w lvion notes 1, 2 enables low-voltage detection operation 0 disables operation 1 operation starts lvie notes 1, 3, 4 specifies reference voltage generator 0 disables operation 1 enables operation lvimd note 1 low-voltage detection operation mode selection 0 generates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 5 low-voltage detection flag 0 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. lvion, lvie, and lvimd are cleared to 0 at a reset other than an lvi reset. these are not cleared to 0 at an lvi reset. 2. when lvion is set to 1, operation of the comparator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 3. when lvie is set to 1, a reference voltage generator operation in the lvi circuit is started. use software to instigate a wait of at least 2 ms from when lvie is set to 1 until lvion is set to 1. 4. if ? use poc ? is selected by a mask option, leave lvie as 0. a wait time (2 ms) until lvion is set to 1 is not necessary. 5. the value of lvif is output as the interrupt request signal intlvi when lvion = 1 and lvimd = 0. caution to stop lvi, follow either of the procedures below. ? ? ? ? when using 8-bit manipulation instruction: write 00h to lvim. ? ? ? ? when using 1-bit memory manipulation instruction: clear lvion to 0 first and then clear lvie to 0.
chapter 19 low-voltage detector preliminary user?s manual u15836ej2v1ud 317 (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. figure 19-3. format of low-voltage detection level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 0 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis2 lvis1 lvis0 detection level 000v lvi0 (4.3 v 0.2 v) 001v lvi1 (4.1 v 0.2 v) 010v lvi2 (3.9 v 0.2 v) 011v lvi3 (3.7 v 0.2 v) 100v lvi4 (3.5 v 0.2 v) note 101v lvi5 (3.3 v 0.15 v) note 110v lvi6 (3.1 v 0.15 v) note 1 1 1 setting prohibited note when the detection voltage of the poc circuit is specified as v poc = 3.5 v 0.2 v by a mask option, do not select v lvi4 to v lvi6 as the lvi detection voltage. even if v lvi4 to v lvi6 are selected, poc circuit has priority.
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 318 19.4 operation of low-voltage detector the low-voltage detector can be used in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection register (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> confirm that ? supply voltage (v dd ) > detection voltage (v lvi ) ? at bit 0 (lvif) of lvim. <8> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <5>. 2. if "use poc" is selected by a mask option, procedures <3> and <4> are not required. 3. if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following procedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0, lvion to 0, and lvie to 0 in that order.
chapter 19 low-voltage detector preliminary user?s manual u15836ej2v1ud 319 figure 19-4. timing of low-voltage detector internal reset signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v lvif flag lvirf flag note lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared not cleared not cleared cleared by software <2> <1> <5> <7> <8> time clear clear clear clear <3> <4> 2 ms or longer <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) lvimd flag (set by software) note lvirf is bit 0 of the reset control flag register (resf). for details of resf, refer to chapter 16 reset function . remark <1> to <8> in figure 19-4 above correspond to <1> to <8> in the description of ? when starting operation ? in 19.4 (1) when used as reset .
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 320 (2) when used as interrupt ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection register (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> confirm that ? supply voltage (v dd ) > detection voltage (v lvi ) ? at bit 0 (lvif) of lvim. <8> clear the interrupt request flag of lvi (lviif) to 0. <9> release the interrupt mask flag of lvi (lvimk). <10> execute the ei instruction (when vector interrupts are used). caution if ?use poc? is selected by a mask option, procedures <3> and <4> are not required. ? when stopping operation either of the following procedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0 first, and then clear lvie to 0.
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 321 figure 19-5. timing of low-voltage detector interrupt signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v time lvif flag intlvi lviif flag internal reset signal <2> <1> <5> <7> <8> cleared by software <3> <4> 2 ms or longer <9> cleared by software <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) remark <1> to <9> in figure 19-5 above correspond to <1> to <9> in the description of ? when starting operation ? in 19.4 (2) when used as interrupt .
chapter 19 low-voltage detector preliminary user?s manual u15836ej2v1ud 322 19.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take action (2) below. in this system, take the following actions. (1) when used as reset after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports.
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 323 figure 19-6. example of software processing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage yes lvi ; the ring-osc clock is set as the cpu clock when the reset signal is generated ; the cause of reset (power-on-clear, wdt, lvi, or clock monitor) can be identified by the resf register. ; change the cpu clock from the ring-osc clock to the x1 input clock. ; check the stabilization of oscillation of the x1 input clock by using the ostc register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports ; 8-bit timer h1 can operate with the ring-osc clock. source: f r (240 khz)/2 7 compare 100 = 53 ms (f r : ring-osc clock oscillation frequency) no note 1 reset checking cause of reset note 2 check stabilization of oscillation change cpu clock 50 ms has passed? (tmifh1 = 1?) initialization processing start timer (set to 50 ms) notes 1. if reset is generated again during this period, initialization processing is not started. 2. a flowchart is shown on the next page.
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 324 figure 19-6. example of software processing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by clock monitor reset processing by low-voltage detector no yes wdtrf of resf register = 1? clmrf of resf register = 1? lvirf of resf register = 1? yes no
chapter 19 low-voltage detector preliminary user ? s manual u15836ej2v1ud 325 (2) when used as interrupt disable interrupts (di) in the servicing routine of the lvi interrupt, and check to see if ? supply voltage (v dd ) > detection voltage (v lvi ) ? , by using bit 0 (lvif) of the low-voltage detection register (lvim). then enable interrupts (ei). in a system where the supply voltage fluctuation period is long in the vicinity of the lvi detection voltage, disable interrupts (di), wait for the supply voltage fluctuation period, check that ? supply voltage (v dd ) > detection voltage (v lvi ) ? with the lvif flag, and then enable interrupts (ei). figure 19-7. example of software processing of lvi interrupt ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check that supply voltage (v dd ) > detection voltage (v lvi ). ; tmifh1 = 1: interrupt request is generated ; enable interrupts. ; disable interrupts. yes no lvif1 of lvim register = 0? yes no 50 ms has passed? (tmifh1 = 1?) lvi lvi interrupt start timer (set to 50 ms) ei di lvi interrupt servicing
preliminary user?s manual u15836ej2v1ud 326 chapter 20 mask options mask rom versions are provided with the following mask options. 1. power-on-clear (poc) circuit ? poc cannot be used ? poc used (detection voltage: v poc = 2.85 v 0.15 v) ? poc used (detection voltage: v poc = 3.5 v 0.2 v) 2. ring-osc ? cannot be stopped ? can be stopped by software flash memory versions that support the mask options of the mask rom versions are as follows. table 20-1. flash memory versions supporting mask options of mask rom versions mask option poc circuit ring-osc flash memory version cannot be stopped pd78f0103m1 poc cannot be used can be stopped by software pd78f0103m2 cannot be stopped pd78f0103m3 poc used (v poc = 2.85 v 0.15 v) can be stopped by software pd78f0103m4 cannot be stopped pd78f0103m5 poc used (v poc = 3.5 v 0.2 v) can be stopped by software pd78f0103m6
preliminary user?s manual u15836ej2v1ud 327 chapter 21 pd78f0103 the pd78f0103 is provided as the flash memory version of the 78k0/kb1 series. the pd78f0103 replaces the internal mask rom of the pd780103 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. table 21-1 lists the differences between the pd78f0103 and the mask rom versions. table 21-1. differences between pd78f0103 and mask rom versions item pd78f0103 mask rom versions internal rom configuration flash memory mask rom internal rom capacity 24 kb note pd780101: 8 kb pd780102: 16 kb pd780103: 24 kb internal high-speed ram capacity 768 bytes note pd780101: 512 bytes pd780102: 768 bytes pd780103: 768 bytes ic pin none available v pp pin available none electrical specifications refer to chapter 23 electrical specifications (target values) . note the same capacity as the mask rom versions can be specified by means of the internal memory size switching register (ims). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions.
chapter 21 pd78f0103 preliminary user?s manual u15836ej2v1ud 328 21.1 internal memory size switching register the pd78f0103 allows users to select the internal memory capacity using the internal memory size switching register (ims) so that the same memory map as that of the mask rom versions with a different internal memory capacity can be achieved. ims is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. caution the initial value of ims is ?setting prohibited (cfh)?. be sure to set the value of the relevant mask rom version at initialization. figure 21-1. format of internal memory size switching register (ims) address: fff0h after reset: cfh r/w symbol76543210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 0 0 0 768 bytes 0 1 0 512 bytes other setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 00108 kb 010016 kb 011024 kb other setting prohibited the ims settings required to obtain the same memory map as mask rom versions are shown in table 21-2. table 21-2. internal memory size switching register settings target mask rom versions ims setting pd780101 42h pd780102 04h pd780103 06h caution when using a mask rom version, be sure to set the value indicated in table 21-2 to ims.
chapter 21 pd78f0103 preliminary user?s manual u15836ej2v1ud 329 21.2 flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is performed after connecting a dedicated flash programmer (flashpro iii (fl-pr3, pg-fp3)) to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro iii. remark fl-pr3 is a product of naito densei machida mfg. co., ltd. 21.2.1 selection of communication mode writing to flash memory is performed using flashpro iii and serial communication. select the communication mode for writing from table 21-3. for the selection of the communication mode, a format like the one shown in figure 21-2 is used. the communication mode is selected according to the number of v pp pulses shown in table 21-3. table 21-3. communication mode list communication mode number of channels pin used note 1 number of v pp pulses sck10/txd0/p10 si10/rxd0/p11 so10/p12 0 3-wire serial i/o 1 sck10/txd0/p10 si10/rxd0/p11 so10/p12 hs/p15/toh0 3 txd0/sck10/p10 rxd0/si10/p11 8 uart (uart0) note 2 1 txd0/sck10/p10 rxd0/si10/p11 hs/p15/toh0 11 uart (uart6) 1 txd6/p13 rxd6/p14 9 notes 1. after shifting to flash memory programming mode, all pins not used for flash memory programming are set to the same state as after reset. therefore, since all ports become output high-impedance, pin processing, such as connecting to v dd or v ss via a resistor is required if the output high-impedance state is not acknowledged by external devices. 2. pd780102, 780103, and 78f0103 only. caution be sure to select the number of v pp pulses shown in table 21-3 for the communication mode.
chapter 21 pd78f0103 preliminary user?s manual u15836ej2v1ud 330 figure 21-2. communication mode selection format 10 v v pp reset v dd v ss v dd v ss v pp pulses flash memory write mode 21.2.2 flash memory programming function flash memory writing is performed via command and data transmit/receive operations using the selected communication mode. the main functions are listed in table 21-4. table 21-4. main functions of flash memory programming function description reset used to detect write stop and transmission synchronization. batch verify compares entire memory contents and input data. batch erase erases the entire memory contents. batch blank check checks the erase status of the entire memory. high-speed write performs writing to flash memory according to write start address and number of write data (bytes). continuous write performs successive write operations using the data input with high-speed write operation. status checks the current operation mode and operation end. oscillation frequency setting inputs the resonator oscillation frequency information. delete time setting inputs the memory delete time. baud rate setting sets the communication rate when the uart method is used. silicon signature read outputs the device name, memory capacity, and device block information.
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 331 21.2.3 connecting flashpro iii the connection between flashpro iii and the pd78f0103 differs depending on the communication mode (3-wire serial i/o or uart). figures 21-3 to 21-7 show the connection diagrams of each case. figure 21-3. connection of flashpro iii in 3-wire serial i/o mode vpp vdd reset sck so si gnd v pp v dd / av ref reset sck10 si10 so10 v ss / av ss flashpro iii pd78f0103 figure 21-4. connection of flashpro iii in 3-wire serial i/o mode (using handshake) vpp vdd reset sck so si gnd v pp v dd / av ref reset sck10 si10 so10 hs hs (p15) v ss / av ss flashpro iii pd78f0103
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 332 figure 21-5. connection of flashpro iii in uart (uart0) mode vpp vdd reset so si gnd v pp v dd / av ref reset rxd0 txd0 v ss / av ss flashpro iii pd78f0103 figure 21-6. connection of flashpro iii in uart (uart0) mode (using handshake) vpp vdd reset so si gnd v pp v dd / av ref reset rxd0 txd0 hs hs (p15) v ss / av ss flashpro iii pd78f0103 figure 21-7. connection of flashpro iii in uart (uart6) mode vpp vdd reset so si gnd v pp v dd / av ref reset rxd6 txd6 v ss / av ss flashpro iii pd78f0103
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 333 21.2.4 connection on adapter for flash memory writing examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 21-8. example of wiring adapter for flash memory writing in 3-wire serial i/o mode 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f0103 lvdd vdd gnd si so sck clkout reset vpp writer interface reserve/hs flash vdd (2.7 to 5.5v) gnd
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 334 figure 21-9. example of wiring adapter for flash memory writing in 3-wire serial i/o mode (using handshake) 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f0103 lvdd vdd gnd si so sck clkout reset vpp writer interface reserve/hs flash vdd (2.7 to 5.5v) gnd
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 335 figure 21-10. example of wiring adapter for flash memory writing in uart mode (uart0) 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f0103 lvdd vdd gnd si so sck clkout reset vpp writer interface reserve/hs flash vdd (2.7 to 5.5v) gnd
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 336 figure 21-11. example of wiring adapter for flash memory writing in uart mode (uart0) (using handshake) 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f0103 lvdd vdd gnd si so sck clkout reset vpp writer interface reserve/hs flash vdd (2.7 to 5.5v) gnd
chapter 21 pd78f0103 preliminary user ? s manual u15836ej2v1ud 337 figure 21-12. example of wiring adapter for flash memory writing in uart mode (uart6) 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f0103 lvdd vdd gnd si so sck clkout reset vpp writer interface reserve/hs flash vdd (2.7 to 5.5v) gnd
preliminary user?s manual u15836ej2v1ud 338 chapter 22 instruction set this chapter lists each instruction set of the 78k0/kb1 series in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instruction user?s manual (u12326e) . 22.1 conventions used in operation list 22.1.1 operand identifiers and specification methods operands are written in the ?operand? column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more methods, select one of them. upper case letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 22-1. operand identifiers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special function register symbols, refer to table 3-5 special function register list .
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 339 22.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 22.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 340 22.2 operation list clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7sfr byte a, r note 3 12 ? a r r, a note 3 12 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5a sfr sfr, a 2 ? 5sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) mov [hl + c], a 1 6 7 + m (hl + c) a a, r note 3 12 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 341 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8ax sfrp sfrp, ax 2 ? 8sfrp ax ax, rp note 3 14 ? ax rp rp, ax note 3 14 ? rp ax ax, !addr16 3 10 12 + 2n ax (addr16) movw !addr16, ax 3 10 12 + 2m (addr16) ax 16-bit data transfer xchw ax, rp note 3 14 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 24 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) add a, [hl + c] 2 8 9 + n a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 24 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + c a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 342 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 24 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 + n a, cy a ? (addr16) a, [hl] 1 4 5 + n a, cy a ? (hl) a, [hl + byte] 2 8 9 + n a, cy a ? (hl + byte) a, [hl + b] 2 8 9 + n a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 + n a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 24 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 + n a, cy a ? (addr16) ? cy a, [hl] 1 4 5 + n a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 + n a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 + n a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 + n a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a [hl] a, [hl + byte] 2 8 9 + n a a [hl + byte] a, [hl + b] 2 8 9 + n a a [hl + b] 8-bit operation and a, [hl + c] 2 8 9 + n a a [hl + c] notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 343 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) or a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) xor a, [hl + c] 2 8 9 + n a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 24 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 + n a ? (addr16) a, [hl] 1 4 5 + n a ? (hl) a, [hl + byte] 2 8 9 + n a ? (hl + byte) a, [hl + b] 2 8 9 + n a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 + n a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 344 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x216 ? ax a x multiply/ divide divuw c225 ? ax (quotient), c (remainder) ax c r12 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r12 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 + n + m a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 24 ? decimal adjust accumulator after addition bcd adjustment adjbs 24 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 345 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy saddr.bit) cy, sfr.bit 3 ? 7cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7cy cy psw.bit and1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7cy cy psw.bit or1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7cy cy psw.bit xor1 cy, [hl].bit 2 6 7 + n cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 + n + m (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 ? cy 11 clr1 cy 1 2 ? cy 00 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 346 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 brk 16 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 16 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr call/return retb 16 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8sp ax stack manipulate movw ax, sp 2 ? 8ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 347 clock flag instruction group mnemonic operands byte note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr. $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 12 ? no operation ei 2 ? 6ie 1(enable interrupt) di 2 ? 6ie 0(disable interrupt) halt 26 ? set halt mode cpu control stop 26 ? set stop mode notes 1. when the internal high-speed ram area is accessed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 348 22.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmovmov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except r = a
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 349 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1
chapter 22 instruction set preliminary user?s manual u15836ej2v1ud 350 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
preliminary user?s manual u15836ej2v1ud 351 chapter 23 electrical specifications (target values) these specifications are only target values, and may not be satisfied by mass-produced products. the electrical specifications (target values) of (a1) products are under evaluation. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0103 only note 2 ? 0.3 to +10.5 v i vdd total value of operating current and high- level output current ? 60 ma supply current i vss total value of operating current and low- level output current 70 ma v i1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, p130, x1, x2, reset ? 0.3 to v dd + 0.3 note 1 v input voltage v i2 v pp in flash programming mode ( pd78f0103 only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 10 ma p30 to p33, p120 ? 30 ma output current, high i oh total of all pins ? 60 ma p00 to p03, p10 to p17, p130 ? 30 ma per pin 20 ma p30 to p33, p120 35 ma output current, low i ol total of all pins 70 ma p00 to p03, p10 to p17, p130 35 ma operating ambient temperature t a in normal operation mode ? 40 to +85 c pd780101, 780102, 780103 ? 65 to +150 storage temperature t stg pd78f0103 ? 40 to +125 c note 1. must be 6.5 v or lower. (refer to note 2 on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 23 electrical specifications (target values) preliminary user?s manual u15836ej2v1ud 352 note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? ? ? ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). ? ? ? ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). 2.7 v v dd 0 v 0 v v pp 2.7 v a b
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 353 x1 oscillator characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 ceramic resonator c1 x2 x1 ic (v pp ) c2 oscillation frequency (f xp ) note 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 crystal resonator c1 x2 x1 ic (v pp ) c2 oscillation frequency (f xp ) note 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 x1 input frequency (f xp ) note 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 46 500 3.3 v v dd < 4.0 v 56 500 external clock x2 x1 x1 input high-/low- level width (t xh , t xl ) 2.7 v v dd < 3.3 v 96 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. ring-osc oscillator characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 480 khz
chapter 23 electrical specifications (target values) preliminary user?s manual u15836ej2v1ud 354 dc characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit per pin 4.0 v v dd 5.5 v ? 5ma total of p30 to p33, p120 4.0 v v dd 5.5 v ? 25 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v ? 25 ma output current, high i oh total of all pins 2.7 v v dd < 4.0 v ? 10 ma per pin for p00 to p03, p10 to p17, p30 to p33, p120, p130 4.0 v v dd 5.5 v 10 ma total of p30 to p33, p120 4.0 v v dd 5.5 v 30 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v 30 ma output current, low i ol total of all pins 2.7 v v dd < 4.0 v 10 ma v ih1 p12, p13, p15 0.7v dd v dd v v ih2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0.8v dd v dd v v ih3 p20 to p23 note 0.7av ref av ref v input voltage, high v ih4 x1, x2 v dd ? 0.5 v dd v v il1 p12, p13, p15 0 0.3v dd v v il2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 00.2v dd v v il3 p20 to p23 note 00.3av ref v input voltage, low v il4 x1, x2 0 0.4 v total of p30 to p33, p120 pins i oh = ? 25 ma 4.0 v v dd 5.5 v, i oh = ? 5 ma v dd ? 1.0 v total of p00 to p03, p10 to p17, p130 pins i oh = ? 25 ma 4.0 v v dd 5.5 v, i oh = ? 5 ma v dd ? 1.0 v output voltage, high v oh i oh = ? 100 a 2.7 v v dd < 4.0 v v dd ? 0.5 v total of p30 to p33, p120 pins i ol = 30 ma 4.0 v v dd 5.5 v, i ol = 10 ma 1.3 v total of p00 to p03, p10 to p17, p130 pins i ol = 30 ma 4.0 v v dd 5.5 v, i ol = 10 ma 1.3 v output voltage, low v ol i ol = 400 a 2.7 v v dd < 4.0 v 0.4 v v i = v dd p00 to p03, p10 to p17, p30 to p33, p120, p130, reset 3 a i lih1 v i = av ref p20 to p23 3 a input leakage current, high i lih2 v i = v dd x1, x2 20 a i lil1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, p130, reset ? 3 a input leakage current, low i lil2 v i = 0 v x1, x2 ? 20 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ? 3 a pull-up resistance value r v i = 0 v 10 30 100 k ? v pp supply voltage ( pd78f0103 only) v pp1 in normal operation mode 0 0.2v dd v note when used as a/d converter analog input pins, set av ref = v dd . remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 23 electrical specifications (target values) preliminary user?s manual u15836ej2v1ud 355 dc characteristics (2/3): pd78f0103 (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 12 22 ma f xp = 10 mhz, v dd = 5.0 v 10% note 3 when a/d converter is operating note 4 13 24 ma when a/d converter is stopped 4 7.3 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 5 mhz, v dd = 3.0 v 10% note 3 when a/d converter is operating note 4 4.6 8.5 ma when peripheral functions are stopped 1.7 3.4 ma f xp = 10 mhz, v dd = 5.0 v 10% note 3 when peripheral functions are operating 5.2 ma when peripheral functions are stopped 0.4 0.8 ma i dd2 x1 crystal oscillation halt mode f xp = 5 mhz, v dd = 3.0 v 10% note 3 when peripheral functions are operating 1.7 ma v dd = 5.0 v 10% 0.4 1.6 ma i dd3 ring-osc operating mode note 5 v dd = 3.0 v 10% 0.3 1.2 ma poc: off, ring: off 0.1 30 a poc: off, ring: on 14 58 a poc: on note 6 , ring: off 3.5 35.5 a v dd = 5.0 v 10% poc: on note 6 , ring: on 17.5 63.5 a poc: off, ring: off 0.05 10 a poc: off, ring: on 7.5 25 a poc: on note 6 , ring: off 3.5 15.5 a supply current note 1 i dd4 stop mode v dd = 3.0 v 10% poc: on note 6 , ring: on 11 30.5 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. including the current that flows through the av ref pin. 5. when main system clock is stopped. 6. including when lvie (bit 4 of lvim) = 1 with poc-off selected by a mask option.
chapter 23 electrical specifications (target values) preliminary user?s manual u15836ej2v1ud 356 dc characteristics (3/3): pd780101, 780102, and 780103 (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 5.5 11 ma f xp = 10 mhz, v dd = 5.0 v 10% note 3 when a/d converter is operating note 4 6.5 13 ma when a/d converter is stopped 1.5 3 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 5 mhz, v dd = 3.0 v 10% note 3 when a/d converter is operating note 4 2.5 5 ma when peripheral functions are stopped 1.1 2.2 ma f xp = 10 mhz, v dd = 5.0 v 10% note 3 when peripheral functions are operating 4.4 ma when peripheral functions are stopped 0.6 1.2 ma i dd2 x1 crystal oscillation halt mode f xp = 5 mhz, v dd = 3.0 v 10% note 3 when peripheral functions are operating 2.4 ma v dd = 5.0 v 10% 0.3 0.9 ma i dd3 ring-osc operating mode note 5 v dd = 3.0 v 10% 0.19 0.57 ma poc: off, ring: off 0.1 30 a poc: off, ring: on 14 58 a poc: on note 6 , ring: off 3.5 35.5 a v dd = 5.0 v 10% poc: on note 6 , ring: on 17.5 63.5 a poc: off, ring: off 0.05 10 a poc: off, ring: on 7.5 25 a poc: on note 6 , ring: off 3.5 15.5 a supply current note 1 i dd4 stop mode v dd = 3.0 v 10% poc: on note 6 , ring: on 11 30.5 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. including the current that flows through the av ref pin. 5. when main system clock is stopped. 6. including when lvie (bit 4 of lvim) = 1 with poc-off selected by a mask option.
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 357 ac characteristics (1) basic operation (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.2 32 s 3.3 v v dd < 4.0 v 0.24 32 s x1 input clock 2.7 v v dd < 3.3 v 0.4 32 s instruction cycle (minimum instruction execution time) t cy ring-osc clock 4.17 8.33 16.67 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note s ti00 input high-level width, low- level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note s 4.0 v v dd 5.5 v 10 ti50 input frequency f ti5 2.7 v v dd < 4.0 v 5 mhz 4.0 v v dd 5.5 v 50 ns ti50 input high-level width, low- level width t tih5 , t til5 2.7 v v dd < 4.0 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s reset low-level width t rst 10 s note selection of f sam = f xp , f xp /4, f xp /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). note that when selecting the ti000 or ti010 valid edge as the count clock, f sam = f xp.
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 358 t cy vs. v dd (x1 input clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 3.3 guaranteed operation range 20.0 32.0 0.24
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 359 (2) serial interface (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) (a) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbs (b) uart mode (uart0, dedicated baud rate generator output): pd780102, 780103, and 78f0103 only parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbs (c) 3-wire serial i/o mode (master mode, sck10... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 3.3 v v dd < 4.0 v 240 ns sck10 cycle time t kcy1 2.7 v v dd < 3.3 v 400 ns sck10 high-/low-level width t kh1 , t kl1 t kcy1 /2 ? 10 ns si10 setup time (to sck10 )t sik1 30 ns si10 hold time (from sck10 )t ksi1 30 ns delay time from sck10 to so10 output t kso1 c = 100 pf note 30 ns note c is the load capacitance of the sck10 and so10 output lines. (d) 3-wire serial i/o mode (master mode, sck10... external clock input) parameter symbol conditions min. typ. max. unit sck10 cycle time t kcy2 200 ns sck10 high-/low-level width t kh2 , t kl2 t kcy2 /2 ? 10 ns si10 setup time (to sck10 )t sik2 30 ns si10 hold time (from sck10 )t ksi2 30 ns delay time from sck10 to so10 output t kso2 c = 100 pf note 30 ns note c is the load capacitance of the so10 output line.
chapter 23 electrical specifications (target values) preliminary user?s manual u15836ej2v1ud 360 (e) 3-wire serial i/o mode (slave mode, sck10... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 3.3 v v dd < 4.0 v 240 ns sck10 cycle time t kcy3 2.7 v v dd < 3.3 v 400 ns sck10 high-/low-level width t kh3 , t kl3 t kcy3 /2 ? 10 ns si10 setup time (to sck10 )t sik3 50 ns si10 hold time (from sck10 )t ksi3 50 ns delay time from sck10 to so10 output t kso3 c = 100 pf note 50 ns note c is the load capacitance of the sck10 and so10 output lines. (f) 3-wire serial i/o mode (slave mode, sck10... external clock input) parameter symbol conditions min. typ. max. unit sck10 cycle time t kcy4 200 ns sck10 high-/low-level width t kh4 , t kl4 t kcy4 /2 ? 10 ns si10 setup time (to sck10 )t sik4 50 ns si10 hold time (from sck10 )t ksi4 50 ns delay time from sck10 to so10 output t kso4 c = 100 pf note 50 ns note c is the load capacitance of the so10 output line. ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih4 (min.) v il4 (max.) 1/f xp t xl t xh
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 361 ti timing ti00 t til0 t tih0 ti50 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth reset input timing reset t rsl
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 362 serial transfer timing 3-wire serial i/o mode: si10 so10 t kcym t klm t khm t sikm t ksim input data t ksom output data sck10 remark m = 1 to 4
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 363 a/d converter characteristics (t a = ? ? ? ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.4 %fsr overall error notes 1, 2 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 4.0 v av ref 5.5 v 14 100 s conversion time t conv 2.7 v av ref < 4.0 v 17 100 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. poc circuit characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v poc0 mask option = 3.5 v 3.3 3.5 3.7 v detection voltage v poc1 mask option = 2.85 v 2.7 2.85 3.0 v v dd : 0 v 2.7 v 0.0015 1500 ms power supply rise time t pth v dd : 0 v 3.3 v 0.002 1800 ms response delay time 1 note t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note t pd when power supply falls, v dd = 1.7 v 1.0 ms minimum pulse width t pw 0.2 ms note time required from voltage detection to reset release. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd
chapter 23 electrical specifications (target values) preliminary user?s manual u15836ej2v1ud 364 lvi circuit characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.5 v v lvi1 3.9 4.1 4.3 v v lvi2 3.7 3.9 4.1 v v lvi3 3.5 3.7 3.9 v v lvi4 3.3 3.5 3.7 v v lvi5 3.15 3.3 3.45 v detection voltage v lvi6 2.95 3.1 3.25 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time note 2 t lwait0 0.5 2.0 ms operation stabilization wait time note 3 t lwait1 0.1 0.2 ms notes 1. time required from voltage detection to interrupt output or reset output. 2. time required from setting lvie to 1 to reference voltage stabilization when poc = off is selected by the poc mask option. 3. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 > v lvi5 > v lvi6 2. v pocn < v lvim (n = 0 and 1, m = 0 to 6) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t wait0 t lw t ld t wait1 lvie 1 lvion 1 data memory stop mode low supply voltage data retention characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.6 5.5 v release signal set time t srel 0 s
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 365 flash memory programming characteristics: pd78f0103 (t a = +10 to +60 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xp = 10 mhz, v dd = 5.5 v 37 ma v pp supply current i pp v pp = v pp2 100 ma step erase time note 1 t er 0.199 0.2 0.201 s overall erase time note 2 t era when step erase time = 0.2 s 20 s/chip writeback time note 3 t wb 49.4 50 50.6 ms number of writebacks per 1 writeback command note 4 c wb when writeback time = 50 ms 60 times number of erases/writebacks c erwb 16 times step write time note 5 t wr 48 50 52 s overall write time per word note 6 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 7 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the issuance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ? erase write ? and ? write only ? are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remark the range of the operating clock during flash memory programming is the same as the range during normal operation.
chapter 23 electrical specifications (target values) preliminary user ? s manual u15836ej2v1ud 366 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 10 s v pp pulse input start time from reset t rp 2ms v pp pulse high-/low-level width t pw 8 s v pp pulse input end time from reset t rpe 20 ms v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe
preliminary user?s manual u15836ej2v1ud 367 chapter 24 package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
preliminary user?s manual u15836ej2v1ud 368 chapter 25 cautions for wait 25.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflicts with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to table 25-1 ). this must be noted when real-time processing is performed.
chapter 25 cautions for wait preliminary user?s manual u15836ej2v1ud 369 25.2 peripheral hardware that generates wait table 25-1 lists the registers that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 25-1. registers that generate wait and number of cpu wait clocks peripheral hardware register access number of wait clocks watchdog timer wdtm write 3 clocks (fixed) serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) adm write ads write pfm write pft write 2 to 5 clocks note (when adm.5 flag = ?1?) 2 to 9 clocks note (when adm.5 flag = ?0?) adcr read 1 to 5 clocks (when adm.5 flag = ?1?) 1 to 9 clocks (when adm.5 flag = ?0?) a/d converter {(1/f macro ) 2/(1/f cpu )} + 1 *the result after the decimal point is truncated if it is less than t cpul after it has been multiplied by (1/f cpu ), and is rounded up if it exceeds t cpul . f macro : macro operating frequency (when bit 5 (fr2) of adm = ?1?: f x /2, when bit 5 (fr2) of adm = ?0?: f x /2 2 ) f cpu : cpu clock frequency t cpul : low-level width of cpu clock note no wait cycle is generated for the cpu if the number of wait clocks calculated by the above expression is 1. remark the clock is the cpu clock (f cpu ).
chapter 25 cautions for wait preliminary user?s manual u15836ej2v1ud 370 25.3 example of wait occurrence <1> watchdog timer number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (mov sfr, a).) number of execution clocks: 10 (7 clocks when data is written to a register that does not issue a wait (mov sfr, #byte).) <2> serial interface uart6 number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (mov a, sfr).) <3> a/d converter table 25-2. number of wait clocks and number of execution clocks on occurrence of wait (a/d converter) ? when f x = 10 mhz, t cpul = 50 ns value of bit 5 (fr2) of adm register f cpu number of wait clocks number of execution clocks f x 9 clocks 14 clocks f x /2 5 clocks 10 clocks f x /2 2 3 clocks 8 clocks f x /2 3 2 clocks 7 clocks 0 f x /2 4 0 clocks (1 clock note ) 5 clocks (6 clocks note ) f x 5 clocks 10 clocks f x /2 3 clocks 8 clocks f x /2 2 2 clocks 7 clocks f x /2 3 0 clocks (1 clock note ) 5 clocks (6 clocks note ) 1 f x /2 4 0 clocks (1 clock note ) 5 clocks (6 clocks note ) note on execution of mov a, adcr remark the clock is the cpu clock (f cpu ). f x : x1 input clock frequency t cpul : low-level width of cpu clock
preliminary user?s manual u15836ej2v1ud 371 appendix a development tools the following development tools are available for the development of systems that employ the 78k0/kb1 series. figure a-1 shows the development tool configuration. ? ? ? ? support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at compatibles. ? ? ? ? windows unless otherwise specified, ?windows? means the following oss. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver 4.0
appendix a development tools preliminary user?s manual u15836ej2v1ud 372 figure a-1. development tool configuration system simulator integrated debugger device file embedded software real-time os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer performance board remark the item in the broken-line box differs according to the development environment. see a.4.1 hardware .
appendix a development tools preliminary user ? s manual u15836ej2v1ud 373 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
appendix a development tools preliminary user ? s manual u15836ej2v1ud 374 a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df780103) (sold separately). this assembler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. ra78k0 assembler package part number: s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an assembler package and device file (both sold separately). this c compiler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. cc78k0 c compiler package part number: s cc78k0 this file contains information peculiar to the device. this device file should be used in combination with a tool (ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0) (all sold separately). the corresponding os and host machine differ depending on the tool to be used (all sold separately). df780103 notes 1, 2 device file part number: s df780103 this is a source file of the functions that configure the object library included in the c compiler package (cc78k0). this file is required to match the object library included in the c compiler package to the user ? s specifications. cc78k0-l note 3 c library source file part number: s cc78k0-l notes 1. the df780103 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0. 2. under development 3. the cc78k0-l is not included in the software package (sp78k0).
appendix a development tools preliminary user ? s manual u15836ej2v1ud 375 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 windows (japanese version) bb13 windows (english version) 3.5-inch 2hd fd ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4) solaris tm (rel. 2.5.1) cd-rom s df780103 s cc78k0-l host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4) solaris (rel. 2.5.1) 1/4-inch cgmt a.3 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flash programmer flash programmer dedicated to microcontrollers with on-chip flash memory. fa-30mc flash memory writing adapter flash memory writing adapter used connected to the flashpro iii. 30-pin plastic ssop (mc-5a4 type) flashpro iii controller program to control flashpro iii from a pc. provided with flashpro iii. remark fl-pr3 and fa-30mc are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd.
appendix a development tools preliminary user ? s manual u15836ej2v1ud 376 a.4 debugging tools a.4.1 hardware ie-78k0-ns in-circuit emulator the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-78k0-ns-pa performance board this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. ie-78k0-ns-a in-circuit emulator product that combines the ie-78k0-ns and ie-78k0-ns-pa ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a 100 v to 240 v ac outlet. ie-70000-98-if-c interface adapter this adapter is required when using a pc-9800 series computer (except notebook type) as the ie-78k0-ns(-a) host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable required when using a notebook-type computer as the ie-78k0-ns(-a) host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc compatible computer as the ie-78k0- ns(-a) host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the ie-78k0-ns(-a) host machine. ie-780148-ns-em1 note emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. np-36gs emulation probe this probe is used to connect the in-circuit emulator to a target system and is designed for use with 30-pin plastic ssop (mc-5a4 type). ngs-30 conversion socket this conversion socket connects the np-36gs to a target system board designed for a 30-pin plastic ssop (mc-5a4 type). np-30mc emulation probe this probe is used to connect the in-circuit emulator to the target system and is designed for use with a 30-pin plastic ssop (mc-5a4 type). nspack30bk yspack30bk hspack30bk yqguide conversion socket this conversion socket connects the np-30mc to a target system board designed to mount a 30-pin plastic ssop (mc-5a4 type). note under development remarks 1. np-36gs, np-30mc, and ngs-30 are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. nspack30bk, yspack30bk, hspack30bk, and yqguide are products of tokyo eletech corporation. for further information, contact daimaru kogyo co., ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672)
appendix a development tools preliminary user ? s manual u15836ej2v1ud 377 a.4.2 software this system simulator is used to perform debugging at c source level or assembler level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in- circuit emulator, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with a device file (df780103) (sold separately). sm78k0 system simulator part number: s sm78k0 this debugger is a control program used to debug 78k/0 series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif tm . it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen at c-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function modules such as a task debugger and system performance analyzer, the efficiency of debugging programs that run on real-time oss can be improved. it should be used in combination with a device file (sold separately). id78k0-ns integrated debugger (supporting in-circuit emulator ie-78k0-ns(-a)) part number: s id78k0-ns remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns host machine os supply medium ab13 windows (japanese version) bb13 windows (english version) 3.5-inch 2hd fd ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
preliminary user?s manual u15836ej2v1ud 378 appendix b embedded software the following embedded products are available for efficient development and maintenance of the 78k0/kb1 series. real-time os the rx78k/0 is a real-time os conforming to the itron specifications. a tool (configurator) for generating the nucleus of the rx78k/0 and multiple information tables is supplied. used in combination with an assembler package (ra78k/0) and device file (df780103) (both sold separately). the real-time os is a dos-based application. it should be used in the dos prompt when using it in windows. rx78k/0 real-time os part number: s rx78013- ???? caution to purchase the rx78k/0, first fill in the purchase application form and sign the user agreement. remark and ???? in the part number differ depending on the host machine and os used. s rx78013- ???? ???? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production ???? host machine os supply medium aa13 pc-9800 series windows (japanese version) note 3.5-inch 2hd fd ab13 windows (japanese version) note bb13 ibm pc/at compatibles windows (english version) note 3.5-inch 2hd fd 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4), solaris (rel. 2.5.1) 1/4-inch cgmt note can also be operated in dos environment.
preliminary user?s manual u15836ej2v1ud 379 appendix c register index c.1 register index (in alphabetical order with respect to register names) [a] a/d conversion result register (adcr) ? 174 a/d converter mode register (adm) ? 176 analog input channel specification register (ads) ? 178 asynchronous serial interface control register 6 (asicl6) ? 228 asynchronous serial interface operation mode register 0 (asim0) ? 196 asynchronous serial interface operation mode register 6 (asim6) ? 222 asynchronous serial interface reception error status register 0 (asis0) ? 198 asynchronous serial interface reception error status register 6 (asis6) ? 224 asynchronous serial interface transmission status register 6 (asif6) ? 225 [b] baud rate generator control register 0 (brgc0) ? 199 baud rate generator control register 6 (brgc6) ? 227 [c] capture/compare control register 00 (crc00) ? 117 clock monitor mode register (clm) ? 305 clock selection register 6 (cksr6) ? 226 [e] 8-bit timer compare register 50 (cr50) ? 138 8-bit timer counter 50 (tm50) ? 138 8-bit timer h compare register 00 (cmp00) ? 150 8-bit timer h compare register 01 (cmp01) ? 150 8-bit timer h compare register 10 (cmp10) ? 150 8-bit timer h compare register 11 (cmp11) ? 150 8-bit timer h mode register 0 (tmhmd0) ? 151 8-bit timer h mode register 1 (tmhmd1) ? 151 8-bit timer mode control register 50 (tmc50) ? 140 external interrupt falling edge enable register (egn) ? 279 external interrupt rising edge enable register (egp) ? 279 [i] input switch control register (isc) ? 91 internal memory size switching register (ims) ? 328 interrupt mask flag register 0h (mk0h) ? 277 interrupt mask flag register 0l (mk0l) ? 277 interrupt mask flag register 1l (mk1l) ? 277 interrupt request flag register 0h (if0h) ? 276 interrupt request flag register 0l (if0l) ? 276 interrupt request flag register 1l (if1l) ? 276
appendix c register index preliminary user?s manual u15836ej2v1ud 380 [l] low-voltage detection level selection register (lvis) ? 317 low-voltage detection register (lvim) ? 315 [m] main clock mode register (mcm) ? 97 main osc control register (moc) ? 98 [o] oscillation stabilization time counter status register (ostc) ? 98, 290 oscillation stabilization time select register (osts) ? 99, 291 [p] port 0 (p0) ? 75 port 1 (p1) ? 78 port 12 (p12) ? 86 port 13 (p13) ? 87 port 2 (p2) ? 84 port 3 (p3) ? 85 port mode register 0 (pm0) ? 87, 120 port mode register 1 (pm1) ? 87, 141 port mode register 12 (pm12) ? 87 port mode register 3 (pm3) ? 87 power-fail comparison mode register (pfm) ? 178 power-fail comparison threshold register (pft) ? 179 prescaler mode register 00 (prm00) ? 119 priority specification flag register 0h (pr0h) ? 278 priority specification flag register 0l (pr0l) ? 278 priority specification flag register 1l (pr1l) ? 278 processor clock control register (pcc) ? 95 pull-up resistor option register 0 (pu0) ? 90 pull-up resistor option register 1 (pu1) ? 90 pull-up resistor option register 12 (pu12) ? 90 pull-up resistor option register 3 (pu3) ? 90 [r] receive buffer register 0 (rxb0) ? 195 receive buffer register 6 (rxb6) ? 221 reset control flag register (resf) ? 303 ring-osc mode register (rcm) ? 96 [s] serial clock selection register 10 (csic10) ? 261 serial operation mode register 10 (csim10) ? 260 serial i/o shift register 10 (sio10) ? 259 16-bit timer capture/compare register 000 (cr000) ? 113 16-bit timer capture/compare register 010 (cr010) ? 114 16-bit timer counter 00 (tm00) ? 113
appendix c register index preliminary user?s manual u15836ej2v1ud 381 16-bit timer mode control register 00 (tmc00) ? 115 16-bit timer output control register 00 (toc00) ? 118 [t] timer clock selection register 50 (tcl50) ? 139 transmit buffer register 10 (sotb10) ? 259 transmit buffer register 6 (txb6) ? 221 transmit shift register 0 (txs0) ? 195 [w] watchdog timer enable register (wdte) ? 167 watchdog timer mode register (wdtm) ? 165
appendix c register index preliminary user?s manual u15836ej2v1ud 382 c.2 register index (in alphabetical order with respect to register symbol) [a] adcr: a/d conversion result register ? 174 adm: a/d converter mode register ? 176 ads: analog input channel specification register ? 178 asicl6: asynchronous serial interface control register 6 ? 228 asif6: asynchronous serial interface transmission status register 6 ? 225 asim0: asynchronous serial interface operation mode register 0 ? 196 asim6: asynchronous serial interface operation mode register 6 ? 222 asis0: asynchronous serial interface reception error status register 0 ? 198 asis6: asynchronous serial interface reception error status register 6 ? 224 [b] brgc0: baud rate generator control register 0 ? 199 brgc6: baud rate generator control register 6 ? 227 [c] cksr6: clock selection register 6 ? 226 clm: clock monitor mode register ? 305 cmp00: 8-bit timer h compare register 00 ? 150 cmp01: 8-bit timer h compare register 01 ? 150 cmp10: 8-bit timer h compare register 10 ? 150 cmp11: 8-bit timer h compare register 11 ? 150 cr000: 16-bit timer capture/compare register 000 ? 113 cr010: 16-bit timer capture/compare register 010 ? 114 cr50: 8-bit timer compare register 50 ? 138 crc00: capture/compare control register 00 ? 117 csic10: serial clock selection register 10 ? 261 csim10: serial operation mode register 10 ? 260 [e] egn: external interrupt falling edge enable register ? 279 egp: external interrupt rising edge enable register ? 279 [i] if0h: interrupt request flag register 0h ? 276 if0l: interrupt request flag register 0l ? 276 if1l: interrupt request flag register 1l ? 276 ims: internal memory size switching register ? 328 isc: input switch control register ? 91 [l] lvim: low-voltage detection register ? 315 lvis: low-voltage detection level selection register ? 317 [m] mcm: main clock mode register ? 97
appendix c register index preliminary user?s manual u15836ej2v1ud 383 mk0h: interrupt mask flag register 0h ? 277 mk0l: interrupt mask flag register 0l ? 277 mk1l: interrupt mask flag register 1l ? 277 moc: main osc control register ? 98 [o] ostc: oscillation stabilization time counter status register ? 98, 290 osts: oscillation stabilization time select register ? 99, 291 [p] p0: port 0 ? 75 p1: port 1 ? 78 p12: port 12 ? 86 p13: port 13 ? 87 p2: port 2 ? 84 p3: port 3 ? 85 pcc: processor clock control register ? 95 pfm: power-fail comparison mode register ? 178 pft: power-fail comparison threshold register ? 179 pm0: port mode register 0 ? 87, 120 pm1: port mode register 1 ? 87, 141 pm12: port mode register 12 ? 87 pm3: port mode register 3 ? 87 pr0h: priority specification flag register 0h ? 278 pr0l: priority specification flag register 0l ? 278 pr1l: priority specification flag register 1l ? 278 prm00: prescaler mode register 00 ? 119 pu0: pull-up resistor option register 0 ? 90 pu1: pull-up resistor option register 1 ? 90 pu12: pull-up resistor option register 12 ? 90 pu3: pull-up resistor option register 3 ? 90 [r] rcm: ring-osc mode register ? 96 resf: reset control flag register ? 303 rxb0: receive buffer register 0 ? 195 rxb6: receive buffer register 6 ? 221 [s] sio10: serial i/o shift register 10 ? 259 sotb10: transmit buffer register 10 ? 259 [t] tcl50: timer clock selection register 50 ? 139 tm00: 16-bit timer counter 00 ? 113 tm50: 8-bit timer counter 50 ? 138 tmc00: 16-bit timer mode control register 00 ? 115 tmc50: 8-bit timer mode control register 50 ? 140
appendix c register index preliminary user?s manual u15836ej2v1ud 384 tmhmd0: 8-bit timer h mode register 0 ? 151 tmhmd1: 8-bit timer h mode register 1 ? 151 toc00: 16-bit timer output control register 00 ? 118 txb6: transmit buffer register 6 ? 221 txs0: transmit shift register 0 ? 195 [w] wdte: watchdog timer enable register ? 167 wdtm: watchdog timer mode register ? 165
preliminary user?s manual u15836ej2v1ud 385 appendix d revision history a history of the revisions up to this edition is shown below. ?applied to:? indicates the chapters to which the revision was applied. (1/2) edition description applied to: x1 input clock oscillation stabilization time 2 12 /f x , 2 14 /f x , 2 15 /f x , 2 16 /f x , 2 17 /f x 2 11 /f x , 2 13 /f x , 2 14 /f x , 2 15 /f x , 2 16 /f x throughout modification of figure 4-5 block diagram of p10 modification of table 4-3 settings of port mode register and output latch when alternate-function is used chapter 4 port functions modification of figure 5-6 format of oscillation stabilization time counter status register (ostc) modification of figure 5-7 format of oscillation stabilization time select register (osts) addition of 5.7 clock selection flowchart and register settings chapter 5 clock generator addition of remark to 12.1 functions of serial interface uart6 chapter 12 serial interface uart6 addition of reset to table 14-1 interrupt source list chapter 14 interrupt functions modification of figure 15-2 format of oscillation stabilization time counter status register (ostc) modification of figure 15-3 format of oscillation stabilization time select register (osts) chapter 15 standby function 2nd addition of chapter 25 retry chapter 25 retry modification of reset value of the following register in table 3-5 special function register list ? serial i/o shift register 10 (sio10) modification of manipulatable bit unit of the following registers in table 3-5 special function register list ? oscillation stabilization time counter status register (ostc) ? interrupt request flag register 1l (if1l) ? interrupt mask flag register 1l (mk1l) ? priority specification flag register 1l (pr1l) chapter 3 cpu architecture modification of manipulatable bit unit in 5.3 (5) oscillation stabilization time counter status register (ostc) modification of figure 5-11 status transition diagram modification of table 5-3 relationship between operation clocks in each operation status modification of table 5-4 oscillation control flags and clock oscillation status modification of table 5-6 clock and register settings chapter 5 clock generator modification of reset value in 6.2 (2) 16-bit timer capture/compare register 000 (cr000) and (3) 16-bit timer capture/compare register 010 (cr010) 2nd (corrected edition) modification of manipulatable bit unit in 6.3 (4) prescaler mode register 00 (prm00) chapter 6 16-bit timer/event counter 00
appendix d revision history preliminary user?s manual u15836ej2v1ud 386 (2/2) edition description applied to: modification of caution in 9.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option modification of 9.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) addition of 9.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask option) chapter 9 watchdog timer addition of (11) a/d converter sampling time and a/d conversion start delay time in 10.6 cautions for a/d converter chapter 10 a/d converter modification of reset value in 13.2 (2) serial i/o shift register 10 (sio10) chapter 13 serial interface csi10 modification of manipulatable bit unit in 15.1.2 (1) oscillation stabilization time counter status register (ostc) modification of a/d converter item in table 15-2 operating statuses in halt mode chapter 15 standby function addition of 18.4 cautions for power-on-clear circuit chapter 18 power-on- clear circuit modification of figure 19-3 format of low-voltage detection level selection register (lvis) addition of 19.5 cautions for low-voltage detector chapter 19 low-voltage detector modification of the following contents in chapter 23 electrical specifications (target values) ? absolute maximum ratings ? x1 oscillator characteristics ? dc characteristics ? a/d converter characteristics ? poc circuit characteristics ? lvi circuit characteristics ? data memory stop mode low supply voltage data retention characteristics (deletion of data retention supply current) ? deletion of ring-osc characteristics ? flash memory programming characteristics chapter 23 electrical specifications (target values) 2nd (corrected edition) modification from chapter 25 retry to chapter 25 cautions for wait chapter 25 cautions for wait
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