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data sheet 1 stp2003qfp pcio pci i/o controller d escription the pcio chip is a high integration, high performance single chip io subsystem connected to the pci local bus. using a single pci bus load it integrates high speed ethernet and ebus2. ebus2 is a generic slave dma bus (pseudo-isa bus) to which off-the-shelf peripherals are connected to implement the rest of the sun core io system. pcio is built around an internal bus (the channel engine interface). this structure is the key to the pcios modularity. above the channel engine interface, the bus adapter connects to the pci bus. the two identical ports on the channel engine interface are used for each of pcio? functional units: ethernet and ebus2. each of these has its own set of control and status registers, data buffers and the core logic function . features pci local bus master/slave interface, compliant with pci local bus speci?ation, revision 2.1 [1] . 10baset (802.3) and 100baset (802.30) ethernet, using a derivative of media access control (mac), with fully buffered transmit and receive channels; media-independent interface (mii). expansion bus interface (ebus2), supporting eight external devices and four buffered slave dma channels. oscillator for 40 mhz scsi clock, and free running 10 mhz real-time clock. ieee 1149.1 jtag compliant test architecture. the following functions are implemented with off-the-shelf devices, connecting directly to the ebus2: pc87303 super io, integrating 82077-compatible ?ppy controller with dma, parallel port, p1284-compliant, with ecp and epp with dma and two 16c550 serial controllers with 16-byte fifos for keyboard and mouse. two high performance sync/async serial ports, using siemens sab82532, 460.8 kbaud async, 384 kbaud sync. sun compatible nvram, mk48t59, with alarm clock interrupt for power management. eprom of ?sh eprom, 8-bit wide, up to 16 mbyte, for obp and post code. cs4231 audio codec. access to usc and dsc control port. auxiliary io ports, for power supply control, temperature sensor, frequency calibration and other miscellaneous functions. product summary the pcio uses symbios?vs 500, cmos 3-layer metal technology. it has 0.75 micron drawn, 0.5 micron effec- tive gate length, and operates at 5 volts. the device is packaged in a 208 pin pqfp. it has 157 signals and 51 vss/vdd pads. the pcio cell has 88k gates and 39k bits of ram. the operating frequency for the pci bus, ebus2 channel engine and the dma engine of the ethernet channel is 33.3 mhz. the core, media access control (mac), operates at 25 mhz. maximum power consumption of the pcio is 2 watts. 1. although designed to the pci 2.0 specification, the pcio controller is compatible with the 2.1 specification as well. however, certain 2.1 recommended features, such as pseudo-split reads and a tighter interpretation of the initial latency rule are not implemented. august 2001
2 stp2003qfp pci i/o controller pcio august 2001 b lock d iagram figure 1. pcio block diagram ebus2 channel engine ethernet channel engine mii ebus2 pci configuration space (multi-function) bus adapter pci bus v2.1 compliant, 33 mhz double 64-byte write buffers 100+ mbytes/sec peak transfer rate jtag pci local bus scan control ethernet dma ?2 dma channels ?2048 byte fifo per channel media access control ?tp 10/100 mhz ?mii ebus2 dma ?4 dma channels ?128 byte fifo p/channel ebus2 interface ?prog. timing ?prog. priority
3 pci i/o controller pcio stp2003qfp august 2001 bus adapter the bus adapter provides a bus-independent layer between the channel engines and the pci bus. the pci bus interface is 32-bit and 33 mhz, fully compliant with the pci local bus speci?ation, revision 2.0 . as a mas- ter, it is capable of 64-byte (8 word) bursts. dma writes are buffered in the bus adapter to support back to back transactions. the bus adapter also contains the pci bus con?uration space. pcio presents itself to pci as a multi-func- tion device: ebus2 (a bridge) and ethernet. each function has its own area in the con?uration space. channel engine interface the bus adapter contains two identical channel engine interface ports, one for each channel engine. the channel engine interface is a bus independent interface, resulting in a high level of modularity at the design and test level. ebus2 channel engine the ebus2 channel engine interfaces standard off-the-shelf devices to pcio. up to eight single or multi-func- tion intel-style 8-bit devices can be accommodated with a minimum of glue logic. four internal dma engines can be attached to any of these devices, buffering data streams in 128-byte fifos for each channel. the standard set of io devices is: pc87303 or superio (integrates 82077 ?ppy controller, dual 16c550 serial controllers for keyboard and mouse and ecp/epp p1284 parallel port), sab82532 serial communications controller, cs4231 audio codec, mk48t59 nvram with alarm clock, boot prom and usc/dsc control port. the ebus2 channel engine provides access to several general purpose io lines ( a.k.a. auxio), used to control miscellaneous system functions. ethernet channel engine the ethernet channel engine provides a buffered full duplex dma engine and a media access control func- tion based on mac. the descriptor-based dma engine contains independent transmit and receive channels, each with 2048 bytes of on-chip buffering. the mac provides a 10 or 100 mbps csma/cd protocol based network interface conforming to ieee 802.3, proposed ieee 802.30 and ethernet speci?ations. scan control block the scan control contains a tap controller. t ypical s ystem a pplication the following diagram shows one possible con?uration of u2p and pcio in a pci based ultra sparc sys- tem. u2p connects to the system controller chip and other upa ports via a upa address, control and data buses. the system has both pci and epci slots, as well as an on board pci device (pcio). interrupt informa- tion is provided by the ric chip, and a jtag port is provided for board testing as well as in-circuit testing and debugging of u2p.
4 stp2003qfp pci i/o controller pcio august 2001 figure 2. typical system application p inout d escription pin naming conventions all pin names are in lower case, except power (vdd) and ground (vss). active low signals are denoted by an underscore and a letter ??_l following the name. direction is input (i), output (o), tri-state output (t), bidirectional (b), and open drain (d). table 1: describes the pre?es used to name signals. ultra sdb tag 512kb e$ clk ta (15:0) td (24+3+p) da(18+16be) d (128+16p) sf3 graphics system memory simms memory address memory control memory data (256+32ecc) xb1 upa_a0(35:0) upa_a1(35:0) upa_d0(127:0+ecc) upa_a1(63:0+ecc) upa_ctrl upa interface pci interface a pci interface b pci bus ric controller sparc-1 sf3a pci bus bus adaptor u2p ethernet ebus2 pcio upa/s 64b
5 pci i/o controller pcio stp2003qfp august 2001 pin summary table 1: signal name pre?es functional block pre? pci bus pci_ ethernet enet_ ebus2 eb_ jtag port jtag_ table 2: pin count summary section pins what it includes pci interface 53 full pci bus v2.0; 1br/bg lines; 4 interrupt lines clock oscillator 7 scsi clock oscillator ethernet interface 20 mii interface, including transceiver management and serial/nibble selection ebus2 interface 41 8 address lines, 8 chip selects miscellaneous 25 mode pin, more interrupts, auxio test 11 jtag port and diagnostics signal total 157 power/ground 51 includes analog power for oscillator total 208
6 stp2003qfp pci i/o controller pcio august 2001 pinout by function table 3: pinout by function name pin dir type description pci interface: 53 pins pci_ad[0] 160 bidir pcib pci address/data bus (lsb) pci_ad[1] 158 bidir pcib pci address/data bus pci_ad[2] 157 bidir pcib pci address/data bus pci_ad[3] 156 bidir pcib pci address/data bus pci_ad[4] 155 bidir pcib pci address/data bus pci_ad[5] 154 bidir pcib pci address/data bus pci_ad[6] 153 bidir pcib pci address/data bus pci_ad[7] 152 bidir pcib pci address/data bus pci_ad[8] 149 bidir pcib pci address/data bus pci_ad[9] 148 bidir pcib pci address/data bus pci_ad[10] 147 bidir pcib pci address/data bus pci_ad[11] 146 bidir pcib pci address/data bus pci_ad[12] 144 bidir pcib pci address/data bus pci_ad[13] 142 bidir pcib pci address/data bus pci_ad[14] 140 bidir pcib pci address/data bus pci_ad[15] 139 bidir pcib pci address/data bus pci_ad[16] 125 bidir pcib pci address/data bus pci_ad[17] 123 bidir pcib pci address/data bus pci_ad[18] 122 bidir pcib pci address/data bus pci_ad[19] 121 bidir pcib pci address/data bus pci_ad[20] 120 bidir pcib pci address/data bus pci_ad[21] 118 bidir pcib pci address/data bus pci_ad[22] 115 bidir pcib pci address/data bus pci_ad[23] 114 bidir pcib pci address/data bus pci_ad[24] 111 bidir pcib pci address/data bus pci_ad[25] 110 bidir pcib pci address/data bus pci_ad[26] 108 bidir pcib pci address/data bus pci_ad[27] 107 bidir pcib pci address/data bus pci_ad[28] 106 bidir pcib pci address/data bus pci_ad[29] 105 bidir pcib pci address/data bus pci_ad[30] 104 bidir pcib pci address/data bus pci_ad[31] 103 bidir pcib pci address/data bus (msb) pci_c_be_l[0] 150 bidir pcib pci command/byte enable pci_c_be_l[1] 138 bidir pcib pci command/byte enable
7 pci i/o controller pcio stp2003qfp august 2001 pci_c_be_l[2] 126 bidir pcib pci command/byte enable pci_c_be_l[3] 112 bidir pcib pci command/byte enable pci_clk 99 in i pci clock (33.3 mhz) pci_frame_l 127 bidir pcib pci frame pci_devsel_l 132 bidir pcib pci device select pci_idsel 113 bidir pcib pci device select - con?uration cycle pci_irdy_l 130 bidir pcib pci initiator ready pci_trdy_l 128 bidir pcib pci target ready pci_stop_l 133 bidir pcib pci transaction terminator pci_par 136 bidir pcib pci data parity pci_perr_l 134 bidir pcib pci parity error pci_serr_l 135 bidir pcib pci system error pci_gnt_l 101 bidir pcib pci bus grant pci_req_l 102 bidir pcib pci bus request pci_rst_l 97 bidir pcib pci reset pci_inta_l 95 bidir pcib pci interrupt request a pci_intb_l 94 bidir pcib pci interrupt request b pci_intc_l 93 bidir pcib pci interrupt request c pci_intd_l 92 bidir pcib pci interrupt request d ebus2 interface: 41 pins eb_a[0] 203 out o4s ebus2 address bus (lsb) eb_a[1] 202 out o4s ebus2 address bus eb_a[2] 201 out o4s ebus2 address bus eb_a[3] 200 out o4s ebus2 address bus eb_a[4] 198 out o4s ebus2 address bus eb_a[5] 197 out o4s ebus2 address bus eb_a[6] 196 out o4s ebus2 address bus eb_a[7] 194 out o4s ebus2 address bus (msb) eb_clken 162 out o4s ebus2 address latch enable (bits 23:8) eb_cs_l[0] 181 tri t4s eprom chip select eb_cs_l[1] 180 tri t4s tod chip select eb_cs_l[2] 179 tri t4s general purpose chip select 0 eb_cs_l[3] 177 tri t4s audio codec chip select eb_cs_l[4] 176 tri t4s superio chip select eb_cs_l[5] 175 tri t4s 85c30 scc chip select eb_cs_l[6] 174 tri t4s ultrasparc system controller chip select table 3: pinout by function (continued) name pin dir type description
8 stp2003qfp pci i/o controller pcio august 2001 eb_cs_l[7] 172 tri t4s general purpose chip select 1 eb_d[0] 193 bidir b8s ebus2 data bus (lsb) eb_d[1] 192 bidir b8s ebus2 data bus eb_d[2] 190 bidir b8s ebus2 data bus eb_d[3] 188 bidir b8s ebus2 data bus eb_d[4] 187 bidir b8s ebus2 data bus eb_d[5] 186 bidir b8s ebus2 data bus eb_d[6] 185 bidir b8s ebus2 data bus eb_d[7] 184 bidir b8s ebus2 data bus (msb) eb_dack_l[0] 170 tri t4s ebus2 dma acknowledge 0 (parallel port) eb_dack_l[1] 168 tri t4s ebus2 dma acknowledge 1 (floppy) eb_dack_l[2] 167 tri t4s ebus2 dma acknowledge 2 (audioin) eb_dack_l[3] 166 tri t4s ebus2 dma acknowledge 3 (audioout) eb_dreq[0] 207 in i ebus2 dma request 0 (parallel port) eb_dreq[1] 206 in i ebus2 dma request 1 (floppy) eb_dreq[2] 205 in i ebus2 dma request 2 (audio in) eb_dreq[3] 204 in i ebus2 dma request 3 (audio out) eb_irq1 76 in i ebus2 interrupt 0 (parallel port) eb_irq2 75 in i ebus2 interrupt 1 (floppy) eb_irq3 74 in i ebus2 interrupt 2 (audio playback) eb_irq4 73 in i ebus2 interrupt 3 (audio capture) eb_rd_l 163 tri t8s ebus2 read eb_wr_l 164 tri t8s ebus2 write eb_rdy 77 in i ebus2 ready input (25 ma pull-up) eb_tcs 165 tri t4s ebus2 dma terminal count ethernet interface: 20 pins enet_exvr_en 31 tri t4s external transceiver enable enet_mgt_clk 32 tri t16 transceiver management clock enet_mgt_d0 34 bidir b4s transceiver management data enet_mgt_d1 33 bidir b4s transceiver management data enet_rx_clk 21 in i 100baset receive clock enet_rx_dv 22 in i 100baset receive frame delimit enet_rx_er 23 in i 100baset receive error enet_rxd[0] 19 in i 100baset receive data enet_rxd[1] 18 in i 100baset receive data enet_rxd[2] 17 in i 100baset receive data table 3: pinout by function (continued) name pin dir type description
9 pci i/o controller pcio stp2003qfp august 2001 enet_rxd[3] 16 in i 100baset receive data enet_tx_clki 10 in i 10baset transmit clock in enet_tx_clko 8 tri t16 100baset transmit clock out enet_tx_col 14 in i 100baset colision detect enet_tx_crs 11 in i 100baset carrier sense enet_tx_en 9 tri t16 100baset transmit enable enet_txd[0] 30 tri t16 100baset transmit data enet_txd[1] 28 tri t16 100baset transmit data enet_txd[2] 26 tri t16 100baset transmit data enet_txd[3] 24 tri t16 100baset transmit data miscellaneous & auxio: 25 pins au_cap_irq_l 72 out o4s audio capture int (motherboard mode) au_pb_irq_l 71 out o4s audio playback int (motherboard mode) aux_ps_off 52 out o4s power off output to courtesy outlet boot[0] 90 in i boot prom reset address boot[1] 89 in i boot prom reset address cod_pdwn_l 45 out o4s audio codec powerdown output fpy_dsel 53 out o4s floppy density select output fpy_dsens 54 in i floppy density sense input freq0 70 in i frequency margining 0 freq1 69 in i frequency margining 1 freq2 67 in i frequency margining 2 mode 35 in i pcio mode = 1 for add-in pcio mode = 0 for motherboard pci_s0_prsnt1 65 in i pci slot 0 preset - bit 1 pci_s0_prsnt2 63 in i pci slot 0 preset - bit 2 pci_s1_prsnt1 62 in i pci slot 1 preset - bit 1 pci_s1_prsnt2 61 in i pci slot 1 preset - bit 2 pci_s2_prsnt1 60 in i pci slot 2 preset - bit 1 pci_s2_prsnt2 59 in i pci slot 2 preset - bit 2 pci_s3_prsnt1 58 in i pci slot 3 preset - bit 1 pci_s3_prsnt2 57 in i pci slot 3 preset - bit 2 sys_ps_off 51 out o4s power off output to power supply system_led 55 out o4s system led output tsens_clk 49 out o4s temp sensor clock tsens_cs_l 47 out o4s temp sensor chip select tsens_d 48 bidir b4s temp sensor data table 3: pinout by function (continued) name pin dir type description
10 stp2003qfp pci i/o controller pcio august 2001 scsi clock oscillator: 7 pins osc_rst_l 1 in i oscillator reset scsi_clk 83 out o4s 40/80 mhz scsi clock output scsi_oscen 82 in i scsi oscillator enable scsi_x1 85 in c 40/80 mhz scsi crystal - x1 scsi_x2 86 out n 40/80 mhz scsi crystal - x2 clk_10m 81 out o4s real time clock time base - 10 mhz clk_5m 79 out o4s real time clock time base - 5 mhz jtag port & diagnostics: 11 pins clock_stop 44 in i stop clock input diag[0] 7 out o4s no function diag[1] 5 out o4s no function diag[2] 4 out o4s no function diag[3] 3 out o4s no function diag[4] 2 out o4s no function jtag_clk 40 in i jtag clock jtag_tdi 38 in i jtag test data input(100ma pull-up) jtag_tdo 36 out o4s jtag test data output jtag_tms 42 in i jtag test mode select (100 ma pull-up) jtag_trst_l 43 in i jtag reset (100 ma pull-up) power and ground: 51 pins bsinvssio bsvssio 37 96 131 183 vss - pad ring bsvssio_1 6 12 20 27 46 50 56 66 78 84 98 100 109 vss - pad ring table 3: pinout by function (continued) name pin dir type description
11 pci i/o controller pcio stp2003qfp august 2001 bsvssio_1 116 124 137 145 151 161 171 178 189 199 208 vss - pad ring pcivddio 91 119 143 159 vdd - pci pad ring - socket compliant vddio 15 29 41 68 87 173 191 vdd - pad ring vsscore 13 39 80 117 141 182 vss - logic core vddcore 25 64 88 129 169 195 vdd - logic core table 3: pinout by function (continued) name pin dir type description
12 stp2003qfp pci i/o controller pcio august 2001 pinout by pin number table 4: pinout by pin number name pin dir type description osc_rst_l 1 in i oscillator reset diag[4] 2 out o4s no function diag[3] 3 out o4s no function diag[2] 4 out o4s no function diag[1] 5 out o4s no function bsvssio_1 6 diag[0] 7 out o4s no function enet_tx_clko 8 tri t16 100baset transmit clock out enet_tx_en 9 tri t16 100baset transmit enable enet_tx_clki 10 in i 10baset transmit clock in enet_tx_crs 11 in i 100baset carrier sense bsvssio_1 12 vsscore 13 enet_tx_col 14 in i 100baset colision detect vddio 15 enet_rxd[3] 16 in i 100baset receive data enet_rxd[2] 17 in i 100baset receive data enet_rxd[1] 18 in i 100baset receive data enet_rxd[0] 19 in i 100baset receive data bsvssio_1 20 enet_rx_clk 21 in i 100baset receive clock enet_rx_dv 22 in i 100baset receive frame delimit enet_rx_er 23 in i 100baset receive error enet_txd[3] 24 tri t16 100baset transmit data vddcore 25 enet_txd[2] 26 tri t16 100baset transmit data bsvssio_1 27 enet_txd[1] 28 tri t16 100baset transmit data vddio 29 enet_txd[0] 30 tri t16 100baset transmit data enet_exvr_en 31 tri t4s external transceiver enable enet_mgt_clk 32 tri t16 transceiver management clock enet_mgt_d1 33 bidir b4s transceiver management data enet_mgt_d0 34 bidir b4s transceiver management data mode 35 in i pcio mode: add-in/motherboard
13 pci i/o controller pcio stp2003qfp august 2001 jtag_tdo 36 out o4s jtag test data output bsinvssio 37 jtag_tdi 38 in i jtag test data input(100ma pull-up) vsscore 39 jtag_clk 40 in i jtag clock vddio 41 jtag_tms 42 in i jtag test mode select (100 ma pull-up) jtag_trst_l 43 in i jtag reset (100 ma pull-up) clock_stop 44 in i stop clock input cod_pdwn_l 45 out o4s audio codec powerdown output bsvssio_1 46 tsens_cs_l 47 out o4s temp sensor chip select tsens_d 48 bidir b4s temp sensor data tsens_clk 49 out o4s temp sensor clock bsvssio_1 50 sys_ps_off 51 out o4s power off output to power supply aux_ps_off 52 out o4s power off output to courtesy outlet fpy_dsel 53 out o4s floppy density select output fpy_dsens 54 in i floppy density sense input system_led 55 out o4s system led output bsvssio_1 56 pci_s3_prsnt2 57 in i pci slot 3 preset - bit 2 pci_s3_prsnt1 58 in i pci slot 3 preset - bit 1 pci_s2_prsnt2 59 in i pci slot 2 preset - bit 2 pci_s2_prsnt1 60 in i pci slot 2 preset - bit 1 pci_s1_prsnt2 61 in i pci slot 1 preset - bit 2 pci_s1_prsnt1 62 in i pci slot 1 preset - bit 1 pci_s0_prsnt2 63 in i pci slot 0 preset - bit 2 vddcore 64 pci_s0_prsnt1 65 in i pci slot 0 preset - bit 1 bsvssio_1 66 freq2 67 in i frequency margining 2 vddio 68 freq1 69 in i frequency margining 1 freq0 70 in i frequency margining 0 au_pb_irq_l 71 out o4s audio playback int (motherboard mode) table 4: pinout by pin number (continued) name pin dir type description
14 stp2003qfp pci i/o controller pcio august 2001 au_cap_irq_l 72 out o4s audio capture int (motherboard mode) eb_irq4 73 in i ebus2 interrupt 3 (audio capture) eb_irq3 74 in i ebus2 interrupt 2 (audio playback) eb_irq2 75 in i ebus2 interrupt 1 (floppy) eb_irq1 76 in i ebus2 interrupt 0 (parallel port) eb_rdy 77 in i ebus2 ready input (25 ma pull-up) bsvssio 78 clk_5m 79 out o4s real time clock time base - 5 mhz vsscore 80 clk_10m 81 out o4s real time clock time base - 10 mhz scsi_oscen 82 in i scsi oscillator enable scsi_clk 83 out o4s 40/80 mhz scsi clock output bsvssio_1 84 scsi_x1 85 in 40/80 mhz scsi crystal - x1 scsi_x2 86 out 40/80 mhz scsi crystal - x2 vddio 87 vddcore 88 boot[1] 89 in i boot prom reset address boot[0] 90 in i boot prom reset address pcivddio 91 pci_intd_l 92 bidir pcib pci interrupt request d pci_intc_l 93 bidir pcib pci interrupt request c pci_intb_l 94 bidir pcib pci interrupt request b pci_inta_l 95 bidir pcib pci interrupt request a bsvssio 96 pci_rst_l 97 bidir pcib pci reset bsvssio_1 98 pci_clk 99 in i pci clock (33 mhz) bsvssio_1 100 pci_gnt_l 101 bidir pcib pci bus grant pci_req_l 102 bidir pcib pci bus request pci_ad[31] 103 bidir pcib pci address/data bus (msb) pci_ad[30] 104 bidir pcib pci address/data bus pci_ad[29] 105 bidir pcib pci address/data bus pci_ad[28] 106 bidir pcib pci address/data bus pci_ad[27] 107 bidir pcib pci address/data bus table 4: pinout by pin number (continued) name pin dir type description
15 pci i/o controller pcio stp2003qfp august 2001 pci_ad[26] 108 bidir pcib pci address/data bus bsvssio_1 109 pci_ad[25] 110 bidir pcib pci address/data bus pci_ad[24] 111 bidir pcib pci address/data bus pci_c_be_l[3] 112 bidir pcib pci command/byte enable pci_idsel 113 bidir pcib pci device select - con?uration cycle pci_ad[23] 114 bidir pcib pci address/data bus pci_ad[22] 115 bidir pcib pci address/data bus bsvssio_1 116 vsscore 117 pci_ad[21] 118 bidir pcib pci address/data bus pcivddio 119 pci_ad[20] 120 bidir pcib pci address/data bus pci_ad[19] 121 bidir pcib pci address/data bus pci_ad[18] 122 bidir pcib pci address/data bus pci_ad[17] 123 bidir pcib pci address/data bus bsvssio_1 124 pci_ad[16] 125 bidir pcib pci address/data bus pci_c_be_l[2] 126 bidir pcib pci command/byte enable pci_frame_l 127 bidir pcib pci frame pci_trdy_l 128 bidir pcib pci target ready vddcore 129 pci_irdy_l 130 bidir pcib pci initiator ready bsvssio 131 pci_devsel_l 132 bidir pcib pci device select pci_stop_l 133 bidir pcib pci transaction terminator pci_perr_l 134 bidir pcib pci parity error pci_serr_l 135 bidir pcib pci system error pci_par 136 bidir pcib pci data parity bsvssio_1 137 pci_c_be_l[1] 138 bidir pcib pci command/byte enable pci_ad[15] 139 bidir pcib pci address/data bus pci_ad[14] 140 bidir pcib pci address/data bus vsscore 141 pci_ad[13] 142 bidir pcib pci address/data bus pcivddio 143 table 4: pinout by pin number (continued) name pin dir type description
16 stp2003qfp pci i/o controller pcio august 2001 pci_ad[12] 144 bidir pcib pci address/data bus bsvssio_1 145 pci_ad[11] 146 bidir pcib pci address/data bus pci_ad[10] 147 bidir pcib pci address/data bus pci_ad[9] 148 bidir pcib pci address/data bus pci_ad[8] 149 bidir pcib pci address/data bus pci_c_be_l[0] 150 bidir pcib pci command/byte enable bsvssio_1 151 pci_ad[7] 152 bidir pcib pci address/data bus pci_ad[6] 153 bidir pcib pci address/data bus pci_ad[5] 154 bidir pcib pci address/data bus pci_ad[4] 155 bidir pcib pci address/data bus pci_ad[3] 156 bidir pcib pci address/data bus pci_ad[2] 157 bidir pcib pci address/data bus pci_ad[1] 158 bidir pcib pci address/data bus pcivddio 159 pci_ad[0] 160 bidir pcib pci address/data bus (lsb) bsvssio_1 161 eb_clken 162 out o4s ebus2 address latch enable (bits 23:12) eb_rd_l 163 tri t8s ebus2 read eb_wr_l 164 tri t8s ebus2 write eb_tcs 165 tri t4s ebus2 dma terminal count eb_dack_l[3] 166 tri t4s ebus2 dma acknowledge 3 (audioout) eb_dack_l[2] 167 tri t4s ebus2 dma acknowledge 2 (audio in) eb_dack_l[1] 168 tri t4s ebus2 dma acknowledge 1 (floppy) vddcore 169 eb_dack_l[0] 170 tri t4s ebus2 dma acknowledge 0 (parallel port) bsvssio_1 171 eb_cs_l[7] 172 tri t4s general purpose chip select 1 vddio 173 eb_cs_l[6] 174 tri t4s ultrasparc system controller chip select eb_cs_l[5] 175 tri t4s 85c30 scc chip select eb_cs_l[4] 176 tri t4s superio chip select eb_cs_l[3] 177 tri t4s audio codec chip select bsvssio_1 178 eb_cs_l[2] 179 tri t4s general purpose chip select 0 table 4: pinout by pin number (continued) name pin dir type description
17 pci i/o controller pcio stp2003qfp august 2001 eb_cs_l[1] 180 tri t4s tod chip select eb_cs_l[0] 181 tri t4s eprom chip select vsscore 182 bsvssio 183 eb_d[7] 184 bidir b8s ebus2 data bus (msb) eb_d[6] 185 bidir b8s ebus2 data bus eb_d[5] 186 bidir b8s ebus2 data bus eb_d[4] 187 bidir b8s ebus2 data bus eb_d[3] 188 bidir b8s ebus2 data bus bsvssio_1 189 eb_d[2] 190 bidir b8s ebus2 data bus vddio 191 eb_d[1] 192 bidir b8s ebus2 data bus eb_d[0] 193 bidir b8s ebus2 data bus (lsb) eb_a[7] 194 out o4s ebus2 address bus (msb) vddcore 195 eb_a[6] 196 out o4s ebus2 address bus eb_a[5] 197 out o4s ebus2 address bus eb_a[4] 198 out o4s ebus2 address bus bsvssio_1 199 eb_a[3] 200 out o4s ebus2 address bus eb_a[2] 201 out o4s ebus2 address bus eb_a[1] 202 out o4s ebus2 address bus eb_a[0] 203 out o4s ebus2 address bus (lsb) eb_dreq[3] 204 in i ebus2 dma request 3 (audio out) eb_dreq[2] 205 in i ebus2 dma request 2 (audio in) eb_dreq[1] 206 in i ebus2 dma request 1 (floppy) eb_dreq[0] 207 in i ebus2 dma request 0 (parallel port) bsvssio_1 208 table 4: pinout by pin number (continued) name pin dir type description
18 stp2003qfp pci i/o controller pcio august 2001 pinout by pin name table 5: pinout by pin name name pin dir type description bsinvssio 37 vss - pad ring bsvssio 131 183 78 96 vss - pad ring bsvssio_1 100 109 116 12 124 137 145 151 161 171 178 189 199 20 208 27 46 50 56 6 66 84 98 vss - pad ring pcivddio 119 143 159 91 vdd - pci pad ring vddcore 129 169 195 25 64 88 vdd - logic core
19 pci i/o controller pcio stp2003qfp august 2001 vddio 15 173 191 29 41 68 87 vdd - pad ring vsscore 117 13 141 182 39 80 vss - logic core au_cap_irq_l 72 out o4s audio capture int (motherboard mode) au_pb_irq_l 71 out o4s audio playback int (motherboard mode) aux_ps_off 52 out o4s power off output to courtesy outlet boot[0] 90 in i boot prom reset address boot[1] 89 in i boot prom reset address clk_10m 81 out o4s real time clock time base - 10 mhz clk_5m 79 out o4s real time clock time base - 5 mhz clock_stop 44 in i stop clock input cod_pdwn_l 45 out o4s audio codec powerdown output diag[0] 7 out o4s no function diag[1] 5 out o4s no function diag[2] 4 out o4s no function diag[3] 3 out o4s no function diag[4] 2 out o4s no function eb_a[0] 203 out o4s ebus2 address bus (lsb) eb_a[1] 202 out o4s ebus2 address bus eb_a[2] 201 out o4s ebus2 address bus eb_a[3] 200 out o4s ebus2 address bus eb_a[4] 198 out o4s ebus2 address bus eb_a[5] 197 out o4s ebus2 address bus eb_a[6] 196 out o4s ebus2 address bus eb_a[7] 194 out o4s ebus2 address bus (msb) eb_clken 162 out o4s ebus2 address latch enable (bits 23:12) eb_cs_l[0] 181 tri t4s eprom chip select eb_cs_l[1] 180 tri t4s tod chip select table 5: pinout by pin name (continued) name pin dir type description
20 stp2003qfp pci i/o controller pcio august 2001 eb_cs_l[2] 179 tri t4s general purpose chip select 0 eb_cs_l[3] 177 tri t4s audio codec chip select eb_cs_l[4] 176 tri t4s superio chip select eb_cs_l[5] 175 tri t4s 85c30 scc chip select eb_cs_l[6] 174 tri t4s ultrasparc system controller chip select eb_cs_l[7] 172 tri t4s general purpose chip select 1 eb_d[0] 193 bidir b8s ebus2 data bus (lsb) eb_d[1] 192 bidir b8s ebus2 data bus eb_d[2] 190 bidir b8s ebus2 data bus eb_d[3] 188 bidir b8s ebus2 data bus eb_d[4] 187 bidir b8s ebus2 data bus eb_d[5] 186 bidir b8s ebus2 data bus eb_d[6] 185 bidir b8s ebus2 data bus eb_d[7] 184 bidir b8s ebus2 data bus (msb) eb_dack_l[0] 170 tri t4s ebus2 dma acknowledge 0 (parallel port) eb_dack_l[1] 168 tri t4s ebus2 dma acknowledge 1 (floppy) eb_dack_l[2] 167 tri t4s ebus2 dma acknowledge 2 (audio in) eb_dack_l[3] 166 tri t4s ebus2 dma acknowledge 3 (audioout) eb_dreq[0] 207 in i ebus2 dma request 0 (parallel port) eb_dreq[1] 206 in i ebus2 dma request 1 (floppy) eb_dreq[2] 205 in i ebus2 dma request 2 (audio in) eb_dreq[3] 204 in i ebus2 dma request 3 (audio out) eb_irq1 76 in i ebus2 interrupt 0 (parallel port) eb_irq2 75 in i ebus2 interrupt 1 (floppy) eb_irq3 74 in i ebus2 interrupt 2 (audio playback) eb_irq4 73 in i ebus2 interrupt 3 (audio capture) eb_rd_l 163 tri t8s ebus2 read eb_rdy 77 in i ebus2 ready input (25 ma pull-up) eb_tcs 165 tri t4s ebus2 dma terminal count eb_wr_l 164 tri t8s ebus2 write enet_exvr_en 31 tri t4s external transceiver enable enet_mgt_clk 32 tri t16 transceiver management clock enet_mgt_d0 34 bidir b4s transceiver management data enet_mgt_d1 33 bidir b4s transceiver management data enet_rx_clk 21 in i 100baset receive clock enet_rx_dv 22 in i 100baset receive frame delimit table 5: pinout by pin name (continued) name pin dir type description
21 pci i/o controller pcio stp2003qfp august 2001 enet_rx_er 23 in i 100baset receive error enet_rxd[0] 19 in i 100baset receive data enet_rxd[1] 18 in i 100baset receive data enet_rxd[2] 17 in i 100baset receive data enet_rxd[3] 16 in i 100baset receive data enet_tx_clki 10 in i 10baset transmit clock in enet_tx_clko 8 tri t16 100baset transmit clock out enet_tx_col 14 in i 100baset colision detect enet_tx_crs 11 in i 100baset carrier sense enet_tx_en 9 tri t16 100baset transmit enable enet_txd[0] 30 tri t16 100baset transmit data enet_txd[1] 28 tri t16 100baset transmit data enet_txd[2] 26 tri t16 100baset transmit data enet_txd[3] 24 tri t16 100baset transmit data fpy_dsel 53 out o4s floppy density select output fpy_dsens 54 in i floppy density sense input freq0 70 in i frequency margining 0 freq1 69 in i frequency margining 1 freq2 67 in i frequency margining 2 jtag_clk 40 in i jtag clock jtag_tdi 38 in i jtag test data input(100ma pull-up) jtag_tdo 36 out o4s jtag test data output jtag_tms 42 in i jtag test mode select (100 ma pull-up) jtag_trst_l 43 in i jtag reset (100 ma pull-up) mode 35 in i pcio mode: add-in/motherboard osc_rst_l 1 in i oscillator reset pci_ad[0] 160 bidir pcib pci address/data bus (lsb) pci_ad[1] 158 bidir pcib pci address/data bus pci_ad[2] 157 bidir pcib pci address/data bus pci_ad[3] 156 bidir pcib pci address/data bus pci_ad[4] 155 bidir pcib pci address/data bus pci_ad[5] 154 bidir pcib pci address/data bus pci_ad[6] 153 bidir pcib pci address/data bus pci_ad[7] 152 bidir pcib pci address/data bus pci_ad[8] 149 bidir pcib pci address/data bus pci_ad[9] 148 bidir pcib pci address/data bus table 5: pinout by pin name (continued) name pin dir type description
22 stp2003qfp pci i/o controller pcio august 2001 pci_ad[10] 147 bidir pcib pci address/data bus pci_ad[11] 146 bidir pcib pci address/data bus pci_ad[12] 144 bidir pcib pci address/data bus pci_ad[13] 142 bidir pcib pci address/data bus pci_ad[14] 140 bidir pcib pci address/data bus pci_ad[15] 139 bidir pcib pci address/data bus pci_ad[16] 125 bidir pcib pci address/data bus pci_ad[17] 123 bidir pcib pci address/data bus pci_ad[18] 122 bidir pcib pci address/data bus pci_ad[19] 121 bidir pcib pci address/data bus pci_ad[20] 120 bidir pcib pci address/data bus pci_ad[21] 118 bidir pcib pci address/data bus pci_ad[22] 115 bidir pcib pci address/data bus pci_ad[23] 114 bidir pcib pci address/data bus pci_ad[24] 111 bidir pcib pci address/data bus pci_ad[25] 110 bidir pcib pci address/data bus pci_ad[26] 108 bidir pcib pci address/data bus pci_ad[27] 107 bidir pcib pci address/data bus pci_ad[28] 106 bidir pcib pci address/data bus pci_ad[29] 105 bidir pcib pci address/data bus pci_ad[30] 104 bidir pcib pci address/data bus pci_ad[31] 103 bidir pcib pci address/data bus (msb) pci_c_be_l[0] 150 bidir pcib pci command/byte enable pci_c_be_l[1] 138 bidir pcib pci command/byte enable pci_c_be_l[2] 126 bidir pcib pci command/byte enable pci_c_be_l[3] 112 bidir pcib pci command/byte enable pci_clk 99 in i pci clock (33 mhz) pci_devsel_l 132 bidir pcib pci device select pci_frame_l 127 bidir pcib pci frame pci_gnt_l 101 bidir pcib pci bus grant pci_idsel 113 bidir pcib pci device select - con?uration cycle pci_inta_l 95 bidir pcib pci interrupt request a pci_intb_l 94 bidir pcib pci interrupt request b pci_intc_l 93 bidir pcib pci interrupt request c pci_intd_l 92 bidir pcib pci interrupt request d pci_irdy_l 130 bidir pcib pci initiator ready table 5: pinout by pin name (continued) name pin dir type description
23 pci i/o controller pcio stp2003qfp august 2001 pci_par 136 bidir pcib pci data parity pci_perr_l 134 bidir pcib pci parity error pci_req_l 102 bidir pcib pci bus request pci_rst_l 97 bidir pcib pci reset pci_s0_prsnt1 65 in i pci slot 0 preset - bit 1 pci_s0_prsnt2 63 in i pci slot 0 preset - bit 2 pci_s1_prsnt1 62 in i pci slot 1 preset - bit 1 pci_s1_prsnt2 61 in i pci slot 1 preset - bit 2 pci_s2_prsnt1 60 in i pci slot 2 preset - bit 1 pci_s2_prsnt2 59 in i pci slot 2 preset - bit 2 pci_s3_prsnt1 58 in i pci slot 3 preset - bit 1 pci_s3_prsnt2 57 in i pci slot 3 preset - bit 2 pci_serr_l 135 bidir pcib pci system error pci_stop_l 133 bidir pcib pci transaction terminator pci_trdy_l 128 bidir pcib pci target ready scsi_clk 83 out o4s 40/80 mhz scsi clock output scsi_oscen 82 in i scsi oscillator enable scsi_x1 85 in c 40/80 mhz scsi crystal - x1 scsi_x2 86 out n 40/80 mhz scsi crystal - x2 sys_ps_off 51 out o4s power off output to power supply system_led 55 out o4s system led output tsens_clk 49 out o4s temp sensor clock tsens_cs_l 47 out o4s temp sensor chip select tsens_d 48 bidir b4s temp sensor data table 5: pinout by pin name (continued) name pin dir type description
24 stp2003qfp pci i/o controller pcio august 2001 e lectrical s pecifications note: stresses beyond those listed in the above table may cause physical damage to the device and should be avoided. table 6: absolute maximum ratings symbol parameter limit unit vdd dc power supply voltage -0.5 to 7.0 v vin, vout dc input, output voltage -0.5 to vdd + 0.5 v i dc current drain per vdd and vss pair 100 ma tstg storage temperature -55 to 150 c tcm maximum case temperature 85 c pd power dissipation 2.0 watts table 7: recommended operating conditions symbol parameter limit unit vdd dc power supply voltage 4.75 to 5.25 v vin, vout dc input, output voltage 0 to vdd v tco operating case temperature 0 to 70 c
25 pci i/o controller pcio stp2003qfp august 2001 table 8: dc characteristics [1] 1. jtag are ttl input levels symbol parameter conditions min max unit vil input low voltage ttl 0.8 v cmos vdd*0.3 v vih input high voltage ttl 2.0 v cmos vdd*0.7 v voh output high voltage ttl ioh = -4,-8,-16 ma 2.4 v cmos ioh = -4,-8,-16 ma vdd -0.8 v pci (dc) ioh = -2 ma 2.4 v vol output low voltage ttl iol = -4, -8, -16 ma 0.4 v cmos iol = -4, -8, -16 ma 0.5 v pci (dc) iol = -3, -6 ma [2] 2. signals without pullup must have 3 ma iol . signals requiring pullup must have 6 ma iol . 0.5 v ii input leakage (non pci pins) vin=vdd or gnd +/- 10 a iih input high leakage (pci pins) vin=2.7v 70 a iil inputlow leakage (pci pins) vin=0.5v - 70 a cin input pin capacitance (pci) 10 pf cclk clk pin capacitance (pci) 12 pf cidsel idsel pin capacitance (pci) 8pf table 9: environmental electrical protection esd latch up minimum minimum 2kv 150 ma
26 stp2003qfp pci i/o controller pcio august 2001 ac c haracteristics ac timing characteristics have been obtained with operating conditions exceeding the recommended limits. a 10% voltage variation, 4.5v to 5.5v, is factored into the vendors bccom and wccom timing libraries and is speci?d in table 10 through table 13. figure 3. general timing waveforms 1. static timing analysis indicates 350ps t_su requirement. test vector extraction software required 1ns granularity. pci t_su s peci?ation currently being tested to 7.5 ns value. 2. static timing analysis shows 250ps t_hold requirement. test vector extraction software required 1ns granularity. pci t_hold s peci?ation currently being tested to 0.5 ns value table 10: pci ac timing characteristics symbol parameter conditions min max unit t_cyc pci_clk cycle time 30 dc ns t_high pci_clk high time 11 ns t_low pci_clk low time 11 ns pci inputs t_su input setup time to pci_clk - bused see note 1 7.5 ns t_su(ptp) input setup time to pci_clk - pci_gnt_l 10 ns t_hold input hold time from pci_clk see note 2 0.5 ns pci outputs t_val pci_clk to signal valid delay - bused 50pf load 2 11 ns t_val(ptp) pci_clk to signal valid delay - pci_req_l 50pf load 2 12 ns t_on float to active delay 2 ns t_off active to float delay 28 ns t_su t_hold t_low t_high t_cyc t_val t_on t_off clock input output tri_output
27 pci i/o controller pcio stp2003qfp august 2001 table 11: ethernet timing characteristics symbol parameter conditions min max unit rx and tx clocks t_cyc rx/tx clk cycle time 40 ns duty cycle 35 65 % mii interface t_su(rx) mii rx inputs setup time to rx_clk 8.0 ns t_hld(rx) mii rx inputs hold time to rx_clk 8.0 ns t_su(tx) mii tx inputs setup time to tx_clk 8.0 ns t_hld(tx) mii tx inputs hold time to tx_clk 8.0 t_val mii tx output valid time from tx_clk 30pf load 15 ns table 12: jtag timing characteristics symbol parameter conditions min max unit jtag clock t_cyc jtag clk cycle time 100 ns jtag inputs t_su(rx) jtag inputs setup time to jtag_clk 0 ns t_hld(rx) jtag inputs hold time to jtag_clk 44 ns t_val jtag output valid time from jtag_clk negative edge 30pf load 20 ns
28 stp2003qfp pci i/o controller pcio august 2001 ebus2 timing the ebus2 is an asynchronous bus. its timing is self regulated handshaking, having no ?ed relationship to the pcio clock. the ebus2 timing is programmable via three timing control registers in the ebus2 channel engine. the timing control registers programming is detailed in the pcio user? manual: see chapter 7 ?bus2 channel engine,?section 7.5.2, section 7.6 and section 7.7. the three timing control registers enable the following functions: ? etup t ime (tsu) and h old t ime (thld) of eb_csx_ or dackx_ with respect to the eb_rd_ or eb_wr_ strobes. minimum deassertion time or r ecovery t ime (thld) between consecutive eb_rd_ or eb_wr_ strobes. ? idth (tstrb) of eb_rd_ or eb_wr_ strobes. selection of dma priority algorithm figure 4 illustrates the timing parameters which can be controlled through timing control registers. timing control registers are programmable at boot time. do not alter them after boot time. the timing given in the timing control register tables is in terms of the number of ebus2 clocks. note that the ebus2 clock is the same as the pci clock which has a duration of 30ns. figure 4. programmable timing paramaters trec tstrb tsu eb_csx_/dackx_ eb_rd_/eb_wr_ thld
29 pci i/o controller pcio stp2003qfp august 2001 ebus2 output and input signals: ac timing characteristics table 13 speci?s the ac tming characteristics required on the ebus2 input and output signals. table 13: ebus2 timing characteristics symbol parameter condition minimum maximum units tcyc ebus2 clock cycle time [1] 1. the ebus2 clock is an ebus2 channel engine internal clock used in pcio chips. ebus 2 is the same as the pci clock which has a duration of 30ns. 30 ns t_high ebus2 clock high time [1] 11 ns t_low ebus2 clock low time [1] 11 ns ebus2 inputs tsu input setup time to the eb_clk 8 ns th input hold time from the eb_clk 8 ns ebus2 outputs tdo eb_clk to output valid delay 50 pf load 13 ns
30 stp2003qfp pci i/o controller pcio august 2001 m echanical i nformation package information and drawings pcio is packaged in a 208-pin, molded pqfp with copper fused lead frame and heat spreader for enhanced thermal dissipation. the die attach pad is 512 x 512 mil. package drawings and mechanical data are shown below. package marking (production version) dtxxxxx: lot trace number (e.g. dt06551) yyyy: assembly date code (for example: 9542; and only for dates 96xx and later) table 14: thermal characteristics (extrapolated - no air ?w) package type theta_ja theta_jc unit fused lead frame + heat spreader 20.0 5.0 c/w sun part number 100-4183-05 dtxxxxx yyyy (sun logo) stp2003qfp 609-0392059 korea (sun copy rights)
31 pci i/o controller pcio stp2003qfp august 2001 208-pin pqfp package dimensions pin 1 index 30.6 0.2 sq. 28.0 0.2 sq. 25.35 ref. 0.22 0.05 0.50 nom. 3.4 0.2 4.1 max. 0.25 / 0.40 seating plane 0.50 / 0.75 0.10 max 0~7 157 208 104 53 52 1 dimensions in millimeters.
32 stp2003qfp pci i/o controller pcio august 2001 o rdering i nformation document part number: 802-7836-02 part number description STP2003PQFP pcio controller, 208-pin plastic quad flat pack (pqfp)

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