d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct280 9-bit odd/even parity generator/checker for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation 9-bit odd/even parity generator/checker 74hc/hct280 features word-length easily expanded by cascading similar pin configuration to the 180 for easy system up-grading generates either odd or even parity for nine data bits output capability: standard i cc category: msi general description the 74hc/hct280 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct280 are 9-bit parity generators or checkers commonly used to detect errors in high-speed data transmission or data retrieval systems. both even and odd parity outputs are available for generating or checking even or odd parity up to 9 bits. the even parity output ( ? e ) is high when an even number of data inputs (i 0 to i 8 ) are high. the odd parity output ( ? 0 ) is high when an odd number of data inputs are high. expansion to larger word sizes is accomplished by tying the even outputs ( ? e ) of up to nine parallel devices to the data inputs of the final stage. for a single-chip 16-bit even/odd parity generator/checker, see pc74hc/hct7080. applications 25-line parity generator/checker 81-line parity generator/checker quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay c l = 15 pf; v cc =5 v i n to ? e 17 18 ns i n to ? o 20 22 ns c i input capacitance 3.5 3.5 pf c pd power dissipationcapacitance per package notes 1 and 2 65 65 pf
december 1990 3 philips semiconductors product speci?cation 9-bit odd/even parity generator/checker 74hc/hct280 pin description pin no. symbol name and function 8, 9, 10, 11, 12, 13, 1, 2, 4 i 0 to i 8 data inputs 5, 6 ? e , ? o parity outputs 7 gnd ground (0 v) 14 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation 9-bit odd/even parity generator/checker 74hc/hct280 fig.4 functional diagram. function table note 1. h = high voltage level l = low voltage level inputs outputs number of high data inputs (i 0 to i 8 ) ? e ? o even odd h l l h fig.5 logic diagram.
december 1990 5 philips semiconductors product speci?cation 9-bit odd/even parity generator/checker 74hc/hct280 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . out put capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay i n to ? e 55 20 16 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.6 t phl / t plh propagation delay i n to ? o 63 23 18 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.6 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.6
december 1990 6 philips semiconductors product speci?cation 9-bit odd/even parity generator/checker 74hc/hct280 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf input unit load coefficient i n 1.0 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay i n to ? e 21 42 53 63 ns 4.5 fig.6 t phl / t plh propagation delay i n to ? o 26 45 56 68 ns 4.5 fig.6 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.6
december 1990 7 philips semiconductors product speci?cation 9-bit odd/even parity generator/checker 74hc/hct280 ac waveforms application information package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.6 waveforms showing the data input (i n ) to parity outputs ( ? e , ? o ) propagation delays and the output transition time. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.7 cascaded 17-bit odd/even parity generator/checker. for a single-chip 16-bit even/odd parity generator/checker, see pc74hc/hct7080.
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