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cortina systems ? lxt972a single-port 10/100 mbps phy transceiver datasheet the cortina systems ? lxt972a single-port 10/100 mbps phy transceiver (lxt972a phy) directly supports both 100base-tx and 10base-t applications. the lx t972a phy is ieee compliant and provides a media independent inte rface (mii) for easy attachment to 10/100 media access controllers (macs). the lxt972a phy supports full-duplex operation at 10 mbps and 100 mbps. operating conditions for the lxt972a phy can be set using auto- negotiation, parallel detection, or manual control. the lxt972a phy is fabricated with an advanced cmos process and re quires only a single 2.5/3.3 v power supply with 2.5 v mii interface support. applications product features ? combination 10base-t/ 100base-tx network interface cards (nics) ? network printers ? 10/100 mbps pcmcia cards ? cable modems and set-top boxes ? 3.3 v operation ? low power consumption (300 mw typical) ? 10base-t and 100base-tx using a single rj- 45 connection ? ieee 802.3-compliant 10base-t or 100base- tx ports with integrated filters ? auto-negotiation an d parallel detection ? mii interface wit h extended regist er capability ? robust baseline wander correction ? carrier sense multiple access / collision detection (csma/cd) or full-duplex operation ? jtag boundary scan ? mdio serial port or hardware pin configurable ? integrated, programmable led drivers ? 64-pin low-profile quad flat package (lqfp) lxt972alc - commercial (0 to 70 c amb.)
lxt972a phy datasheet 249186, revision 5.2 13 september 2007 legal disclaimers informa t ion in this document is prov ided in connection with cortina systems ? products. no license, express or implied, by estoppel or ot herwise, to any intellectual property rights is granted by this document. except as provided in cortina?s terms and conditions of sale of such products, cortina assumes no liability whatsoever, and cortina disclaims any express or implied warranty relating to the sale and/or use of cortina products, including li ability or warranties relating to fitness for a particular purpose, merchantability or infringement of any patent, copyright or other intellectual property right. cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. cortina systems ? and the cortina systems logo are the trademarks or registered trademarks of cortina systems, inc. and its subsidiaries in the u.s. and other countries. other names and brands may be claimed as the property of others. copyright ? 2001 ? page 2 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver
page 3 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 contents contents 1.0 introduction to this document .............. ................ ................. ................................................ ... 10 1.1 document overview ........................................................................................................... 10 1.2 related documents ........................................................................................................... .10 2.0 block diagram ............................................................................................................... .............. 11 3.0 ball and pin assignments .................................................................................................... ...... 12 4.0 signal descriptions ......................................................................................................... ............ 15 5.0 functional description...................................................................................................... .......... 21 5.1 device overview ............................................................................................................. .... 21 5.1.1 comprehensive functiona lity ................................................................................ 21 5.1.2 optimal signal processing architecture .................................................................21 5.2 network media / protocol support ...................................................................................... 22 5.2.1 10/100 network interface....................................................................................... 22 5.2.2 mii data interface .................................................................................................. 23 5.2.3 configuration management interface .................................................................... 23 5.3 operating requirements........ ............................................................................................. 2 5 5.3.1 power requirements ............................................................................................. 25 5.3.2 clock requirements ....... .......................................................................................26 5.4 initialization .............................................................................................................. ........... 26 5.4.1 mdio control mode and hardware cont rol mode................................................. 26 5.4.2 reduced-power modes ......................................................................................... 27 5.4.3 reset ..................................................................................................................... 27 5.4.4 hardware configuration settings ........................................................................... 28 5.5 establishing link ........................................................................................................... ...... 28 5.5.1 auto-negotiation .................................................................................................... 29 5.5.2 parallel detection................................................................................................... 30 5.6 mii operation ............................................................................................................... ....... 30 5.6.1 mii clocks .............................................................................................................. 31 5.6.2 transmit enable..................................................................................................... 32 5.6.3 receive data valid ................................................................................................ 32 5.6.4 carrier sense......................................................................................................... 33 5.6.5 error signals .......................................................................................................... 33 5.6.6 collision ................................................................................................................. 33 5.6.7 loopback ............................................................................................................... 33 5.7 100 mbps operation ........................................................................................................... 35 5.7.1 100base-x network operations .............. ................................................ ............. 35 5.7.2 collision indication ................................................................................................. 37 5.7.3 100base-x protocol sublay er operations..... ................ ................. ............ .......... 38 5.8 10 mbps operation ............................................................................................................ .42 5.8.1 10base-t preamble hand ling .............. ................ .......................... ............ .......... 42 5.8.2 10base-t carrier sense ................................................ ................. ............ .......... 42 5.8.3 10base-t dribble bits ... ................................................ ................. ............ .......... 42 5.8.4 10base-t link in tegrity test ...... ................................................................ .......... 42 5.8.5 link failure ............................................................................................................ 43 5.8.6 10base-t sqe (heartbeat ) .................. ................ .......................... ............ .......... 43 5.8.7 10base-t jabber . ................ ................. ................ .......................... ............ .......... 43
page 4 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 contents 5.8.8 10base-t polarity correction ..... ................................................................ .......... 43 5.9 monitoring operations ....................................................................................................... .43 5.9.1 monitoring auto-negotiation .................................................................................. 43 5.9.2 monitoring next page exchange ........................................................................... 44 5.9.3 led functions ....................................................................................................... 44 5.9.4 led pulse stretching............................................................................................. 44 5.10 boundary scan (jtag 1149 .1) functions .......................................................................... 45 5.10.1 boundary scan interface ....................................................................................... 45 5.10.2 state machine ........................................................................................................ 45 5.10.3 instruction register ............................ .................................................................... 45 5.10.4 boundary scan register .................... .................................................................... 46 5.10.5 device id register ................................................................................................. 46 6.0 application information ..................................................................................................... ......... 47 6.1 magnetics information ....................................................................................................... .47 6.2 typical twisted-pair interface ............................................................................................ 47 7.0 electrical specifications ... ................................................................................................ .......... 51 7.1 dc electrical parameters ................................................................................................... 5 1 7.2 ac timing diagrams and para meters ................................................................................ 54 8.0 register definitions - ieee ba se registers ....... ................................ ................. ............ .......... 63 9.0 register definiti ons - product-specific regi sters ............ ................ ................. ............ .......... 71 10.0 package specifications..................................................................................................... .......... 79
page 5 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 figures figures 1 block diagram ................................................................................................................. .............. 11 2 64-pin lqfp package: pin assignments ...................................................................................... 12 3 management interface read frame structure ............................................................................. 24 4 management interface write frame structure ............................................................................. 24 5 mii interrupt logic .......................................................................................................... ............... 25 6 link establishment overview .................................................................................................. ..... 29 7 clocking for 10base-t ... ................. ................................................ .......................... .......... ......... 31 8 clocking for 100base-x ....................................................................................................... ....... 32 9 clocking for link down clock transition ...................................................................................... 32 10 loopback paths .............................................................................................................. .............. 34 11 100base-x frame format .............. ................................................................ ............. ........... .....35 12 100base-tx data path .............. ................ ................. ................................ ............. ............ ....... 36 13 100base-tx reception with no er rors ................ ................................ ................. ............ .......... 36 14 100base-tx reception with invalid symbol ........ ................................ ................. ............ .......... 37 15 100base-tx transmission with no errors ........ ................................................................ .......... 37 16 100base-tx transmission with collision .......... ................................................................ .......... 37 17 protocol sublayers .......................................................................................................... ............. 38 18 led pulse stretching ........................................................................................................ ........... 45 19 typical twisted-pair interface - switch ...................................................................................... ... 48 20 typical twisted-pair interface - nic ......................................................................................... .....49 21 typical media independent interface .......................................................................................... .. 50 22 100base-tx receive timing ...... ................ ................. ................................................ ............. ... 55 23 100base-tx transmit timing .. ................................ ................. ................................................ ... 56 24 10base-t transmit timing ...... ................................ ................. ................................ ............. ...... 57 25 10base-t jabber and unjabber ti ming ............ ................................................................ .......... 58 26 10base-t sqe (heartbeat) timi ng ................ ................................................................ ............. 58 27 auto-negotiation and fast link pulse timing ............................................................................... 59 28 fast link pulse timing ....................................................................................................... ........... 59 29 mdio input timing ............................................................................................................ ............ 60 30 mdio output timing........................................................................................................... ........... 60 31 power-up timing .............................................................................................................. ............. 61 32 reset_l pulse width and recovery timing ........ ................................ ................. ............ .......... 61 33 phy identifier bit mapping . ................................................................................................. .........66 34 lqfp package specifications .................................................................................................. ..... 79
page 6 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 tables tables 1 related documents ............................................................................................................. .......... 10 2 phy signal types .............................................................................................................. ........... 12 3 lqfp numeric pin list ......................................................................................................... ......... 13 4 phy signal types .............................................................................................................. ........... 15 5 mii data interface signal descriptions ........................................................................................ .. 16 6 mii controller interface signal descriptions .................................................................................. 17 7 lxt972a: network interface sig nal descriptions.......................................................................... 17 8 lxt972a: standard bus and interface signal descriptions .......................................................... 17 9 lxt972a: configuration and led driver signal descriptions ....................................................... 18 10 lxt972a: power, ground, no-c onnect signal descriptions ........................................................ 19 11 lxt972a: jtag test signal descriptions..................................................................................... 19 12 lxt972a: pin types and modes................................................................................................. .. 20 13 hardware configuration settings .............................................................................................. ..... 28 14 carrier sense, loopback, and collision conditions ...... ................................................................ 33 15 4b/5b coding ................................................................................................................. ............... 39 16 bsr mode of operation ........................................................................................................ ........ 46 17 device id register........................................................................................................... .............. 46 18 magnetics requirements....................................................................................................... ........ 47 19 i/o pin comparison of nic and switch rj-45 setups................................................................... 47 20 absolute maximum ratings .............................. ....................................................................... ......51 21 recommended operating conditions .................... ....................................................................... 51 22 digital i/o characteristics (except for mii, xi/xo, and led/cfg pins) ........................................ 52 23 digital i/o characteristics 1 - mii pins ............................................................................................ 52 24 i/o characteristics - refclk/xi and xo pins .............................................................................. 53 25 i/o characteristics - led/cfg pins ........................................................................................... ...53 26 100base-tx phy characteristics ............... ................. ................................................ ............... .53 27 10base-t phy characteristics ................................ ................. ................................................ ... 54 28 10base-t link integrity timing characteristics.. ................................................................ .......... 54 29 thermal characteristics...................................................................................................... ........... 54 30 100base-tx receive timing parame ters - 4b mode ..... ................................................ ............. 56 31 10base-t receive timing parame ters ................. ................................ ................. ............ .......... 57 32 10base-t jabber and unjabber ti ming ............. ................................................................ .......... 58 33 phy 10base-t sqe (heartbeat) ti ming.................. ................. ................ ............. ............ .......... 58 34 auto-negotiation a nd fast link pulse timing parameters ............................................................ 59 35 mdio timing .................................................................................................................. ............... 60 36 power-up timing .............................................................................................................. ............. 61 37 reset_l pulse width and recovery timing ........ ................................ ................. ............ .......... 62 38 register set for ieee base re gisters .............................................................................. ........... .. 63 39 control register - address 0, hex 0 ............. ............................................................................. ....64 40 mii status register #1 - address 1, hex 1 .................................................................................... 65 41 phy identification register 1 - address 2, hex 2 .......................................................................... 66 42 phy identification register 2 - address 3, hex 3 .......................................................................... 66 43 auto-negotiation advertisement re gister - address 4, hex 4....................................................... 67 44 auto-negotiation link pa rtner base page ability register - a ddress 5, hex 5 ............................. 68 45 auto-negotiation expansion - address 6, hex 6 ........................................................................... 69 46 auto-negotiation next pa ge transmit register - address 7, hex 7 .............................................. 69 47 auto-negotiation link pa rtner next page receive register - address 8, hex 8 .......................... 70 48 register set for product-specif ic registers .................................................................................. 71
page 7 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 tables 49 configuration register - address 16, hex 10 ...... .......................................................................... 71 50 status register #2 - address 17, hex 11 ...................................................................................... 72 51 interrupt enable register - address 18, hex 12 ............................................................................ 74 52 status change register - address 19, hex 13.............................................................................. 74 53 led configuration register - address 20, hex 14 ........................................................................ 76 54 digital configuration register - address 26, he x 1a..................................................................... 77 55 transmit control register - address 30, hex 1e .......................................................................... 78
page 8 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 revision history revision history revision 5.2 revision date: 13 september 2007 ? removed outdated figure 3: 64-pin pb-free lqfp package: pins assignments ? removed the ordering information. this informati on is now available from www.cortina-systems.com. revision 5.1 revision date: 23 july 2007 added section 10.0, package specifications back into datasheet. revision 5.0 revision date: 2 july 2007 first release of this document from cortina systems, inc. revision 004 revision date: 25 october 2005 front page text changed. added ta b l e 1 , related documents added section 11.1, top label markings . modified table 141, product ordering information and figure 124, order matrix for cortina systems? lxt972a transceiver (b3498) under section 14.0, product ordering information . revision 003 revision date: 06 august 2002 added ?jtag boundary scan? to product features on front page. modified figure 1 ?lxt972a 64-pin lqfp assignm ents? (replaced test1 and test0 with gnd). modified table 1 ?lqfp numeric pin list? (replaced test1 and test0 with gnd). added note under section 2.0, ?signal descriptions? : ?intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused.? modified table 4 ?lxt972a miscellaneous signal descriptions? . modified table 5 ?lxt972a power supply signal descriptions? . added table 8 ?lxt972a pin types and modes? . added section 3.2.2.1, ?increased mii drive strength? . modified figure 7 ?hardware configuration settings? . modified table 13 ?supported jtag instructions? . modified table 14 ?device id register? . modified table 17 ?absolute maximum ratings? . modified table 18 ?operating conditions? : added typ values to vcc current. modified table 20 ?digital i/o characteristics - mii pins? . modified table 22 ?i/o characteri stics - led/cfg pins? . added table 26 ?lxt972a thermal characteristics? . modified table 29 ?10base-t receive timing parameters? . modified table 38 ?register bit map? (added address 26 information).
page 9 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 revision history added table 53 ?digital config register (address 26)? . modified table 54 ?transmit control register #2 (address 30)? . added section 8.0, ?product ordering information? . revision 002 revision date: 15 january 2001 clock requirements: modified language under clock requirements heading. i/o characteristics refclk (table): changed values for input clock duty cycle under min from 40 to 35 and under max from 60 to 65. revision 001 revision date: 01 january 2001 initial release. revision 003 revision date: 06 august 2002
page 10 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 1.0 introduction to this document 1.0 introduction to this document this document includes inform ation on the cortina systems ? lxt972a single-port 10/ 100 mbps phy transcei ver (lxt972a phy). 1.1 document overview this document includes the following subjects: 2.0, block diagram, on page 11 3.0, ball and pin assignments , on page 12 4.0, signal descriptions , on page 15 5.0, functional description , on page 21 6.0, application information , on page 47 7.0, electrical specifications , on page 51 8.0, register definitions - ieee base registers , on page 63 9.0, register definitions - product-specific registers , on page 71 1.2 related documents table 1 related documents document title document number cortina systems ? lxt971a, lxt972a, lxt972m single-port 10/ 100 mbps phy specification update 249354 cortina systems ? lxt971a, lxt972a, and lxt972m 3.3 v phy design and layout guide - application note 249016 magnetic manufacturers for netw orking product applications - application note 248991
page 11 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 2.0 block diagram 2.0 block diagram figure 1 block diagram tx_en rx_er crs power supply management / mode select logic addr[4:0] mdio mdc tx_er rxdv tpon tpop tpin tpip refclk vcc gnd col rx_clk tx_clk txd[3:0] decoder & descrambler + - + - serial-to- parallel converter scrambler & encoder parallel/serial converter carrier sense data valid error detect auto negotiation manchester decoder manchester encoder 10 100 10 100 media select tp driver tp out ecl driver register set register set clock generator + - 10bt collision detect clock generator tx pcs osp ? adaptive eq with baseline wander cancellation osp ? slicer osp ? pulse shaper rxd[3:0] + - 100tx tp in mddis txslew[1:0] rx pcs pwrdwn jtag 5 tdio tms tck trst_l reset_l mdint_l b3493-02 led1/cfg1 led3/cfg3 led2/cfg2
page 12 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 3.0 ball and pin assignments 3.0 ball and pin assignments see the following diagrams for signal placement: ? figure 2, 64-pin lqfp package: pin assignments , on page 12 see the following tables for signal lists: ? ta b l e 3 , lqfp numeric pin list , on page 13 note: ta b l e 2 list the signal type abbreviations used in the signal tables. table 2 phy signal types abbreviation definition ai analog input ao analog output i input i/o input/output o output od open drain figure 2 64-pin lqfp package: pin assignments b3388-03 rbias 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 refclk/xi xo mddis reset_l txslew0 txslew1 gnd vccio nc nc gnd addr0 addr1 addr2 addr3 addr4 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 tpfop tpfon vcca vcca tpfip tpfin sd/tp_l sleep mdint_l crs col txd3 txd2 txd1 txd0 tx_en tx_c lk tx_er rx_er rx_clk vccd rx_dv 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 rxd0 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rxd1 rxd2 rxd3 nc mdc mdio gnd vccio pwrdwn led1/cfg1 led2/cfg2 led3/cfg3 gnd gnd pause 48 trst_l tck tms tdo tdi gnd gnd gnd gnd
page 13 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 3.0 ball and pin assignments table 3 lqfp numeric pin list (sheet 1 of 2) pin symbol type 1 refclk/xi i 2x o o 3m d d i s i 4 reset_l i 5t x s l e w 0 i 6t x s l e w 1 i 7g n d ? 8 vccio ? 9n c ? 10 nc ? 11 gnd ? 12 addr0 i 13 gnd ? 14 gnd ? 15 gnd ? 16 gnd ? 17 rbias ai 18 gnd ? 19 tpop o 20 tpon o 21 vcca ? 22 vcca ? 23 tpip i 24 tpin i 25 gnd ? 26 gnd ? 27 tdi i 28 tdo output 29 tms i 30 tck i 31 trst_l i 32 gnd ? 33 pause i 34 gnd ? 35 gnd ? 36 led/cfg3 i/o 37 led/cfg2 i/o
page 14 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 3.0 ball and pin assignments 38 led/cfg1 i/o 39 pwrdwn i 40 vccio ? 41 gnd ? 42 mdio i/o 43 mdc i 44 nc ? 45 rxd3 o 46 rxd2 o 47 rxd1 o 48 rxd0 o 49 rx_dv o 50 gnd ? 51 vccd ? 52 rx_clk o 53 rx_er o 54 tx_er i 55 tx_clk o 56 tx_en i 57 txd0 i 58 txd1 i 59 txd2 i 60 txd3 i 61 gnd ? 62 col o 63 crs o 64 mdint_l od table 3 lqfp numeric pin list (sheet 2 of 2) pin symbol type
page 15 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 4.0 signal descriptions 4.0 signal descriptions cortina recommends the following configurations for unused pins: ? unused inputs. configure all unused inputs and unused multi-function pins for inactive states. ? unused outputs. leave all unused outputs floating. ? no connects. do not use pins designated as nc (no connect), and do not terminate them. note: ta b l e 4 list the signal type abbreviations used in the signal tables. tables in this sectio n include the following: ? ta b l e 5 , mii data interface signal descriptions , on page 16 ? ta b l e 6 , mii controller interfac e signal descriptions , on page 17 ? ta b l e 7 , lxt972a: network interface signal descriptions , on page 17 ? ta b l e 8 , lxt972a: standard bus and interface signal descriptions , on page 17 ? ta b l e 9 , lxt972a: configuration and led driver signal descriptions , on page 18 ? ta b l e 1 0 , lxt972a: power, ground, no-connect signal descriptions , on page 19 ? table 11, lxt972a: jtag test signal descriptions , on page 19 ? ta b l e 1 2 , lxt972a: pin types and modes , on page 20 table 4 phy signal types abbreviation definition ai analog input ao analog output i input i/o input/output o output od open drain
page 16 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 4.0 signal descriptions table 5 mii data interface signal descriptions lqfp pin# symbol type signal description 60 59 58 57 txd3 txd2 txd1 txd0 i transmit data. txd is a group of parallel data signals that are driven by the mac. txd[3:0] transition synchronously with respect to tx_clk. txd[0] is the least-significant bit. 56 tx_en i transmit enable. the mac asserts this signal when it drives valid data on txd. this signal must be synchronized to tx_clk. 55 tx_clk o transmit clock. tx_clk is sourced by the phy in both 10 and 100 mbps operations. 2.5 mhz for 10 mbps operation 25 mhz for 100 mbps operation. 45 46 47 48 rxd3 rxd2 rxd1 rxd0 o receive data. rxd is a group of parallel signals that tr ansition synchronously with respect to rx_clk. rxd[0] is the least-significant bit. 49 rx_dv o receive data valid. the phy asserts this signal when it drives valid data on rxd. this output is synchronous to rx_clk. 53 rx_er o receive error. signals a receive error condition has occurred. this output is synchronous to rx_clk. 54 tx_er i transmit error. signals a transmit error condition. this signal must be synchronized to tx_clk. 52 rx_clk o receive clock. 25 mhz for 100 mbps operation. 2.5 mhz for 10 mbps operation. for details, see section 5.3.2, clock requirements , on page 26 in the functional description section. 62 col o collision detected . the phy asserts this output when a collision is detected. this output remains high for the duration of the collision. this signal is asynchronous and is inactive during full- duplex operation. 63 crs o carrier sense . during half-duplex operation (register bit 0.8 = 0), the phy asserts this output when either transmitting or receiving data packets. during full-duplex operation (register bit 0.8 = 1), crs is asserted only during receive. crs assertion is asynchronous with respect to rx_clk. crs is de- asserted on loss of carrier, synchronous to rx_clk.
page 17 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 4.0 signal descriptions . table 6 mii controller interface signal descriptions lqfp pin# symbol type signal description5 3 mddis i management data disable . when mddis is high, the mdio is disabled from read and write operations. when mddis is low at power-up or reset, the hardware control interface pins control only the initial or ?default? values of their respective register bits. after the power-up/reset cycle is complete, bit control reverts to the mdio serial channel. 43 mdc i management data clock . clock for the mdio serial data channel. maximum frequency is 8 mhz. 42 mdio i/o management data input/output . bidirectional serial data channel for phy/sta communication. 64 mdint_l od management data interrupt . when register bit 18.1 = 1, a low output on this active-low pin indicates a status change. interrupt is cleared by reading register 19. table 7 lxt972a: network in terface signal descriptions lqfp pin# symbol type signal description 19 20 tpop tpon o twisted-pair outputs, positive and negative. during 100base-tx or 10base-t oper ation, tpop/n pins drive ieee 802.3 compliant pulses onto the line. 23 24 tpip tpin i twisted-pair inputs, positive and negative. during 100base-tx or 10base-t operation, tpip/n pins receive differential 100base-tx or 10base-t signals from the line. table 8 lxt972a: standard bus an d interface signal descriptions lqfp pin# symbol type signal description 12 addr0 i address 0 . sets device address.
page 18 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 4.0 signal descriptions table 9 lxt972a: configuration and led driver signal descriptions lqfp pin# symbol type signal description note: implement 10 k pull-up/pull-down resistors if leds are not used in the design. 5 6 txslew0 txslew1 i tx output slew controls 0 and 1 . these pins select the tx output slew rate (rise and fall time) as follows: txslew1 txslew0 slew rate (rise and fall time) 0 0 3.0 ns 0 1 3.4 ns 1 0 3.9 ns 1 1 4.4 ns 4 reset_l i reset . this active low input is ored with the control register reset bit (register bit 0.15). the phy reset cycle is extended to 258 s (nominal) after reset is de-asserted. 17 rbias ai reference current bias . this pin provides bias current for the internal circuitry. must be tied to ground through a 22.1 k , 1% resistor. 33 pause i pause . when set high, the phy advertises pause capabilities during auto- negotiation. 39 pwrdwn i power down . when set high, this pin puts the phy in a power-down mode. 1 2 refclk/xi xo i and o reference clock input / crystal input and crystal output . a 25 mhz crystal oscillator circuit can be connected across xi and xo. a clock can also be used at xi. refer to section 5.3.2, clock requirements , on page 26 in the functional description section. 38 37 36 led/cfg1 led/cfg2 led/cfg3 i/o led drivers 1-3. these pins drive led indicators. each led can display one of several available status conditions as se lected by the led configuration register. (for details, see table 53, led configuration register - address 20, hex 14 , on page 76 .) configuration inputs 1-3. these pins also provide initial conf iguration settings. (for details, see table 13, hardware configuration settings , on page 28 .)
page 19 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 4.0 signal descriptions table 10 lxt972a: power, ground, no-connect signal descriptions lqfp pin# symbol type signal description 51 vccd ? digital power. requires a 3.3 v power supply. 7, 11, 13, 14, 15, 16, 18, 25, 26, 32, 34, 35, 41, 50, 61 gnd ? ground. 8, 40 vccio ? mii power. requires either a 3.3 v or a 2.5 v supply. must be supplied from the same source used to power the mac on the other side of the mii. vccio is 3.3 v. 21, 22 vcca ? analog power. requires a 3.3 v power supply. 9, 10, 44 nc - no connection . these pins are not used and should not be terminated. table 11 lxt972a: jtag test signal descriptions lqfp pin# symbol type signal description note: these pins do not need to be terminated if a jtag port is not used. 27 tdi i test data input . test data sampled with respect to the rising edge of tck. 28 tdo o test data output . test data driven with respect to the falling edge of tck. 29 tms i test mode select . 30 tck i test clock . clock input for boundary scan. 31 trst_l i test reset . this active-low test reset input is sourced by ate.
page 20 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 4.0 signal descriptions table 12 lxt972a: pin types and modes modes rxd3:0 rx_dv tx/rx clks output rx_er output col output crs output txd3:0 input tx_en input tx_er input hwreset dldldhdldldl id id id sftpwrdn dl dl active dl dl dl id id id hwpwrdnhzhzhzhzhzhzhzhzhz isolate hz with id hz with id hz with id hz with id hz with id hz with id id id id ? dh = driven high (logic 1) ? dl = driven low (logic 0) ? hz = high impedance ? id = internal pull-down (weak)
page 21 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.0 functional description 5.0 functional description this chapter has the following sections: ? section 5.1, device overview , on page 21 ? section 5.2, network media / protocol support , on page 22 ? section 5.3, operating requirements , on page 25 ? section 5.4, initialization , on page 26 ? section 5.5, establishing link , on page 28 ? section 5.6, mii operation , on page 30 ? section 5.7, 100 mbps operation , on page 35 ? section 5.8, 10 mbps operation , on page 42 ? section 5.9, monitoring operations , on page 43 ? section 5.10, boundary scan (jtag 1149.1) functions , on page 45 5.1 device overview the lxt972a phy is a single-port fast ethe rnet 10/100 phy that supports 10 mbps and 100 mbps networks. it complies with applicable requirement s of ieee 802.3. it directly drives either a 100base- tx line or a 10base-t line. 5.1.1 comprehensive functionality the lxt972a phy provides a standard media independent interface (mii) for 10/100 macs. the lxt972a phy performs all function s of the physical coding sublayer (pcs) and physical media attachment (pma) sublay er as defined in the ieee 802.3 100base-x standard. it also performs all functions of the physical media dependent (pmd) sublayer for 100base-tx connections. the lxt972a phy reads its configuration pins on power-up to check for forced operation settings. if the lxt972a phy is not set for forced oper ation, it uses auto-negotiation/parallel detection to automatically determine line oper ating conditions. if the phy device on the other side of the link supports auto-negotiation, the lxt972a phy auto-negotiates with it using fast link pulse (flp) bursts. if the ph y partner does not support auto-negotiation, the lxt972a phy automatically detects the presence of either link pulses (10 mbps phy) or idle symbols (100 mbps phy) and sets its operating conditions accordingly. the lxt972a phy provides half-duplex and full-duplex operation at 100 mbps and 10 mbps. 5.1.2 optimal signal pr ocessing architecture the lxt972a phy incorporates high-efficie ncy optimal signal processing (osp) design techniques, which combine optimal properties of digital and analog signal processing. the receiver utilizes decision feedback equa lization to increase noise and cross-talk immunity by as much as 3 db over an ideal all-analog equalizer. using osp mixed-signal processing techniques in the receive equa lizer avoids the quantization noise and
page 22 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.2 network media / protocol support calculation truncation errors found in tradit ional dsp-based receivers (typically complex dsp engines with a/d converters). this result s in improved receiver noise and cross-talk performance. the osp signal processing scheme also requ ires substantially less computational logic than traditional dsp-based designs. this lowers power consumption and also reduces the logic switching noise generated by dsp engi nes. this logic switching noise can be a considerable source of emi generated on the device?s power supplies. the osp-based lxt972a phy provides improved data recovery, emi performance, and low power consumption. 5.2 network media / protocol support this section includes the following: ? section 5.2.1, 10/100 network interface ? section 5.2.2, mii data interface ? section 5.2.3, configuration management interface the lxt972a phy supports both 10base-t and 100base-tx ethernet over twisted-pair 5.2.1 10/100 network interface the network interface port consists of two differential signal pairs. for specific pin assignments, see section 4.0, signal descriptions , on page 15 . the lxt972a phy output drivers can generate one of the following outputs: ? 100base-tx ? 10base-t when not transmitting data, the lxt972a phy generates ieee 802.3-compliant link pulses or idle code. depending on the mode selected, input signals are decoded as one of the following: ? 100base-tx ? 10base-t auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. 5.2.1.1 twisted-pair interface the lxt972a phy supports either 100base-tx or 10base- t connections over 100 , category 5 , unshielded twisted pair (utp) cable. when operating at 100 mbps, the lxt972a phy continuously transmits and rece ives mlt3 symbols. when not transmitting data, the lxt972a phy generates ?idle? symbols. during 10 mbps operation, xilin k* manchester-encoded data is exchanged. when no data is being exchanged, the line is left in an idle state. link pulses are transmitted periodically to keep the link up. only a transformer, rj-45 connector, load resistor and bypass capacitors are required to complete this interface. on the transmit side, the lxt972a phy has an active internal termination and does not require external te rmination resistors. cortina?s waveshaping technology shapes the outgoing signal to help reduce the need for external emi filters. four slew rate settings allow the designer to match the output waveform to the magnetic
page 23 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.2 network media / protocol support characteristics. on the receive side, the inte rnal impedance is high enough that it has no practical effect on the external termination circuit. (for the slew rate settings, see ta b l e 5 5 , transmit control register - address 30, hex 1e , on page 78 .) 5.2.1.2 remote fault detection and reporting the lxt972a phy supports the remote faul t detection and reporting mechanisms. ?remote fault? refers to a mac-to-mac communi cation function that is transparent to phy layer devices. it is used only during au to-negotiation, and is applicable only to twisted-pair links. remote fault detection. register bit 4.13 in the auto-n egotiation advertisement register is reserved for remote fault indications. it is typically used when re-starting the auto- negotiation sequence to indica te to the link partner that the link is down because the advertising device detected a local fault. when the lxt972a phy receives a remote fault indication from its partner during auto- negotiation, the following occurs: ? register bit 5.13 in the link partne r base page ability register is set. ? remote fault register bit 1.4 in the mii stat us register is set to pass this information to the local controller. 5.2.2 mii data interface the lxt972a phy supports a standard media independent interface (mii). the mii consists of a data interface and a management interface. the mii data interface passes data between the lxt972a phy and a media access controller (mac). separate parallel buses are provided for transmit and receive. th is interface operates at either 10 mbps or 100 mbps. the speed is set automatically, on ce the operating conditions of the network link have been determined. for details, see section 5.6, mii operation , on page 30 . increased mii drive strength. a higher media independent interface (mii) drive strength may be desired in some designs to drive signals over longer pcb trace lengths, or over high-capacitive loads, through multiple vi as, or through a connector. the mii drive strength in the lxt972a phy can be increased by setting register bit 26.11 through software control. setting register bit 26.11 = 1 through the mdc/mdio interface sets the mii pins (rxd[3:0], rx_dv, rx_clk, rx_er, col, crs, and tx_clk) to a higher drive strength. 5.2.3 configuration ma nagement interface the lxt972a phy provides both an mdio interface and a reduced hardware control interface for device configuration and management. 5.2.3.1 mdio management interface mdio management interface topics include the following: ? section 5.2.3.1.1, mdio addressing ? section 5.2.3.1.2, mdio frame structure the lxt972a phy supports th e ieee 802.3 mii management in terface also known as the management data input/output (mdio) interface. this in terface allows upper-layer devices to monitor and control the state of the lxt972a phy. the mdio interface consists of a physical connecti on, a specific protocol that ru ns across the connection, and an internal set of addressable registers.
page 24 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.2 network media / protocol support some registers ar e required and their functions are defined by the i eee 802.3 standard. the lxt972a phy also supports additional registers for expanded functionality. the lxt972a phy supports multiple in ternal registers, each of which is 16 bits wide. specific register bits are referenced using an ?x.y? nota tion, where x is the register number (0-31) and y is the bit number (0-15). the physical interface consists of a data line (mdio) and clock line (mdc). operation of this interface is controlled by the mddis input pin. when mddis is high, the mdio read and write operations are disabled and the hardware control interface provides primary configuration control. when mddis is low, the mdio port is enabled for both read and write operations and the hardware control interface is not used. 5.2.3.1.1 mdio addressing the mdio addressing protocol allows a cont roller to communicate with multiple phys. pin addr0 determines the phy device address that is selected as follows. ? connect pin addr0 low to get phy address 0. ? connect pin addr0 high to get phy address 1. 5.2.3.1.2 mdio frame structure the physical interface consists of a data line (mdio) and clock line (mdc). the frame structure is shown in figure 3 and figure 4 (read and write). mdio interface timing is given in section 7.0, electrical specifications . 5.2.3.1.3 mii interrupts figure 5 shows the mii interrupt logic. the lxt972a phy provides a hardware interrupt pin (mdint_l) and two dedicated interrupt registers, register 18 and register 19. ? register 18 provides interrupt enable and mask functions. setting register bit 18.1 = 1 enables the device to request interrupt via the mdint_l pin. an active low on this pin figure 3 management interface read frame structure figure 4 management interface write frame structure mdc mdio (read) 32 "1"s 0110 preamble st op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data write read d15 d14 d1 d0 idle high z b3489-01 mdc mdio (write) 32 "1"s 0101 preamble st op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 d0 data idle idle write b3490-01
page 25 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.3 operating requirements indicates a status change on the lxt972a phy. interrupts may be caused by any of the following four conditions: ? auto-negotiation complete ? speed status change ? duplex status change ? link status change ? register 19 provides the interrupt status. 5.2.3.1.4 mii status change register mii status change is indicated in register 19 by any of the following four conditions: ? auto-negotiation complete ? speed status change ? duplex status change ? link status change 5.2.3.2 hardware control interface the lxt972a phy provides a hardware control interface for applications where the mdio is not desired. the hardware control interface uses the hardware configuration pins to set device configuration. for details, see section 5.4.4, hardware configuration settings , on page 28. 5.3 operating requirements 5.3.1 power requirements the lxt972a phy requires three power supply inputs: ? vcca ? vccd ? vccio figure 5 mii interrupt logic nand even x mask reg even x status reg force interrupt interrupt enable and interrupt pin mdint_l b3474-01 or
page 26 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.4 initialization the digital and analog circuits require 3.3 v supplies (vcca and vccd). these inputs may be supplied from a single source. each s upply input must be de-coupled to ground. an additional supply may be used for the mii (v ccio). the supply may be either 2.5 v or 3.3 v. also, the inputs on the mii interface are tolerant to 5 v signals from the controller on the other side of the mii interface. for mii i/o char acteristics, see table 23, digital i/o characteristics 1 - mii pins , on page 52 . notes: 1. bring up power supplies as clos e to the same time as possible. 2. as a matter of good practice, keep power supplies as clean as possible. 5.3.2 clock requirements 5.3.2.1 external crystal/oscillator the lxt972a phy requires a reference clock input that is used to generate transmit signals and recover receive signals. it may be provided by either of two methods: by connecting a crystal across the oscillator pins (xi and xo) with load capacitors, or by connecting an external clock source to pin xi. the connection of a clock source to the xi pin requires the xo pin to be left open. to minimize transmit jitter, co rtina recommends a crystal-based clock instead of a derived clock (that is, a pll-based clock). a crystal is typically used in nic applicatio ns. an external 25 mhz clock source, rather than a crystal, is frequently used in switch app lications. for clock timing requirements, see ta b l e 2 4 , i/o characteristics - refclk/xi and xo pins , on page 53 . 5.3.2.2 mdio clock the mii management channel (mdio) also requires an external clock. the managed data clock (mdc) speed is a maximum of 8 mhz. 5.4 initialization this section includes the following topics: ? section 5.4.1, mdio control mode and hardware control mode ? section 5.4.2, reduced-power modes ? section 5.4.3, reset ? section 5.4.4, hardware configuration settings when the lxt972a phy is first powered on, reset, or encounters a link failure state, it checks the mdio register configuration bits to determine the line speed and operating conditions to use for the network link. ta b l e 1 3 shows the lxt972a phy initialization seque nce. the configuration bits may be set by the hardware cont rol or mdio interface. 5.4.1 mdio control mode and hardware control mode in the mdio control mode, the lxt972a phy reads the hardware control interface pins to set the initial (default) values of the mdio registers. once the initial values are set, bit control reverts to the mdio interface. the following modes are available using ei ther hardware control or mdio control:
page 27 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.4 initialization ? force network link operation to: ? 100base-tx, full-duplex ? 100base-tx, half-duplex ? 10base-t, full-duplex ? 10base-t, half-duplex ? allow auto-negotiation /parallel-detection on power-up or hardware reset, the lxt972a phy reads the hardware control interface pins and sets the mdio registers accordingly. when the network link is forced to a specific configuration, the lxt972a phy immediately begins operating the network interface as commanded. when auto-negotiation is enabled, the lxt972a phy begins the auto-negotiation/parallel-detection operation. 5.4.2 reduced-power modes this section discusses the lxt972a phy reduced-power modes. 5.4.2.1 hardware power down the hardware power-down mode is controll ed by the pwrdwn pi n. when pwrdwn is high, the following co nditions are true: ? the lxt972a phy network port and clock are shut down. ? all outputs are tristated. ? all weak pad pull-up and pull-down resistors are disabled. ? the mdio registers are not accessible. 5.4.2.2 software power down software power-down control is provided by register bit 0.11 in the control register. during soft power-down, the following conditions are true: ? the network port is shut down. ? the mdio registers remain accessible. 5.4.3 reset the lxt972a phy provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. for a software reset, register bit 0.15 = 1. for register bit definitions used for software reset, see table 39, control register - address 0, hex 0 , on page 64 . ? during a software reset, bit settings in table 43, auto-negotiation advertisement register - address 4, hex 4 , on page 67 are not re-read from the lxt972a phy configuration pins. instead, the bit settings revert to the values that were read in during the last hardware reset. therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. ? during a software reset, registers are available for reading. to see when the lxt972a phy has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0).
page 28 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.5 establishing link for pin settings used during a hardware reset, see section 5.4.4, hardware configuration settings . during a hardware reset, configuration settings for auto-negotiation and speed are read in from pins, and register information is unavailable for 1 ms after de-assertion of the reset. 5.4.4 hardware configuration settings the lxt972a phy provides a hardware option to set the initial device configuration. as listed in ta b l e 1 3 , the hardware option uses the hardwar e configuration pins, the settings for which provide control bits. 5.5 establishing link figure 6 shows an overview of link es tablishment for the lxt972a phy. note: when a link is established by using parallel detection, the lxt972a phy sets the duplex mode to half-duplex, as defin ed by the ieee 802.3 standard. table 13 hardware configuration settings desired mode led/cfg pin settings 1 resulting register bit values control register auto-negotiation advertisement register auto-neg. speed (mbps) duplex 123 auto- neg. 0.12 speed 0.13 full- duplex 0.8 100 base-tx full- duplex 4.8 100 base- tx 4.7 10 base-t full- duplex 4.6 10 base-t 4.5 disabled 10 half lll 0 00 n/a auto-negotiation advertisement full l l h 0 1 100 half l h l 1 0 full l h h 1 1 enabled 100 only half h l l 1 10 0 1 0 0 full/half h l h 1 1 1 1 0 0 10/100 half only h h l 1 0 0 1 0 1 full or half h h h 1 1 1 1 1 1 1. l = low, and h = high. for le d/cfg pin assi gnments, see section 3.0, ball and pin assignments
page 29 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.5 establishing link 5.5.1 auto-negotiation if not configured for forced operation, the lxt972a phy attempts to auto-negotiate with its link partner by sending fast link pulse (flp ) bursts. each burst consists of up to 33 link pulses spaced 62.5 s apart. odd link pulses (clock pulses) are always present. even link pulses (data pulses) may be absent or present to indicate a ?0? or a ?1?. each flp burst exchanges 16 bits of data, which are referred to as a ?link code word?. all devices that support auto-negotiation must implement t he ?base page? defined by the ieee 802.3 standard (registers 4 and 5). the lxt972a phy also supports the optional ?next page? function as listed in ta b l e 4 6 , auto-negotiation next page transm it register - address 7, hex 7 , on page 69 and ta b l e 4 7 , auto-negotiation link partner next page receive register - address 8, hex 8 , on page 70. 5.5.1.1 base page exchange by exchanging base pages, the lxt972a phy and its link partner communicate their capabilities to each other. both sides must receive at least three consecutive identical base pages for negotiation to continue. each side identifies the highest common capabilities that both sides support, and each side conf igures itself accordingly. 5.5.1.2 manual next page exchange ?next page exchange? information is additiona l information that exceeds the information required by base page exchange and that is sent by ?next pages?. the lxt972a phy fully supports the ieee 802.3 standard method of negotiation throug h the next page exchange. figure 6 link establishment overview check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link up? no yes power-up, reset, or link failure disable auto-negotiation 0.12 = 0 0.12 = 1 b3496-01
page 30 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.6 mii operation the next page exchange uses register 7 to se nd information and register 8 to receive it. next page exchange occurs only if both ends of the link pa rtners advertise their ability to exchange next pages. register bit 6.1 is used to make manual next page exchange easier for software. this register bit is cleared w hen a new negotiation occurs, preventing the user from reading an old value in register 6 and assuming there is valid information in registers 5 and 8. 5.5.1.3 controlling auto-negotiation when auto-negotiation is controlled by softwa re, cortina recommends the following steps: 1. after power-up, power-down, or reset, the power-down recovery time (specified in ta b l e 3 7 , reset_l pulse width and recovery timing , on page 62 ) must be exhausted before proceeding. 2. set the auto-negotiation advertisement register bits. 3. enable auto-negotiation. (set mdio register bit 0.12 = 1.) 4. to ensure proper operation, enable or rest art auto-negotiation as soon as possible after writing to register 4. 5.5.2 parallel detection in parallel with auto-negotiation, the lxt972a phy also monitors for 10 mbps normal link pulses (nlp) or 100 mbps idle symbols. if either symbol is detected, the device automatically reverts to the corresponding speed in half-duplex mode. parallel detection allows the lxt972a phy to communicate with devices that do not support auto- negotiation. when parallel detection resolves a link, the link must be established in half-duplex mode. according to ieee standards, the forced link pa rtner cannot be configur ed to full-duplex. if the auto-negotiat ion link partner does not advertise ha lf-duplex capability at the speed of the forced link partner, link is not established. the ieee st andard prevents full-duplex-to- half-duplex link connections. 5.6 mii operation this section includes the following topics: ? section 5.6.1, mii clocks ? section 5.6.2, transmit enable ? section 5.6.3, receive data valid ? section 5.6.4, carrier sense ? section 5.6.5, error signals ? section 5.6.6, collision ? section 5.6.7, loopback the lxt972a phy implements the media indepe ndent interface (mii) as defined by the ieee 802.3 standa rd. separate channels ar e provided for transmitti ng data from the mac to the lxt972a phy (txd), and for passing da ta received from th e line (rxd) to the mac. each channel has its own clock, data bus, and control signals. the following signals are used to pass received data to the mac: ?col
page 31 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.6 mii operation ? crs ?rx_clk ?rx_dv ? rx_er ? rxd[3:0] the following signals are used to transmit data from the mac: ?tx_clk ? tx_en ? tx_er ? txd[3:0] the lxt972a phy supplies both clock signals as well as separate outputs for carrier sense and collision. data tran smission across the mii is normally implemented in 4-bit- wide nibbles. 5.6.1 mii clocks the lxt972a phy is the master clock source for data transmission, and it supplies both mii clocks (rx_clk and tx_clk). it automatically sets the clock speeds to match link conditions. ? when the link is operating at 100 mbp s, the clocks are set to 25 mhz. ? when the link is operating at 10 mbps, the clocks are set to 2.5 mhz. figure 7 through figure 9 show the clock cycles for each mode. note: the transmit data and control signals must always be synchronized to tx_clk by the mac. the lxt972a phy samples these signals on the rising edge of tx_clk. figure 7 clocking for 10base-t rx_clk 2.5 mhz during auto-negotiation and 10base-t data & idle tx_clk 2.5 mhz during auto-negotiation and 10base-t data & idle constant 25 mhz xi b3390-01
page 32 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.6 mii operation 5.6.2 transmit enable the mac must assert tx_en the same time as the first nibble of preamble and de-assert tx_en after the last nibble of the packet. 5.6.3 receive data valid the lxt972a phy asserts rx_dv when it receives a valid packet. timing changes depend on line operating speed: ? for 100base-tx links, rx_dv is asserted from the first nibble of preamble to the last nibble of the data packet. ? for 10base-t links, the entire pr eamble is truncated. rx_dv is asserted with the first nibble of the start of frame delimiter (sfd) ?5d? and remains asserted until the end of the packet. figure 8 clocking for 100base-x figure 9 clocking for link down clock transition rx_clk 2.5 mhz during auto-negotiation tx_clk constant 25 mhz xi 25 mhz once 100base-x link established 2.5 mhz during auto-negotiation 25 mhz once 100base-x link established b3391-01 any clock 2.5 mhz clock clock transition time does not exceed 2x the nominal clock period: 10 mbps = 2.5 mhz 100 mbps = 25 mhz link-down condition/auto-negotiate enabled rx_clk tx_clk b3503-01
page 33 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.6 mii operation 5.6.4 carrier sense carrier sense (crs) is an asynchronous output. ? crs is always generated when the lxt972a phy receives a packet from the line. ? crs is also generated when the lxt972a phy is in half-duplex mode when a packet is transmitted. ta b l e 1 4 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. carrier sense is not generat ed when a packet is transmitted and in full- duplex mode. . 5.6.5 error signals when the lxt972a phy is in 100 mbps mode and receives an invalid symbol from the network, it asserts rx_er and drives ?0101? on the rxd pins. when the mac asserts tx_er, the lxt972a phy drives ?h? symbols out on the tpfop/ n pins. 5.6.6 collision the lxt972a phy asserts its collision signal asynchronously to an y clock whenever the line state is half-duplex and the transmitter and receiver are active at the same time. ta b l e 1 4 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. 5.6.7 loopback the lxt972a phy provides the following loopback functions: ? section 5.6.7.1, operational loopback ? section 5.6.7.2, internal digital loopback (test loopback) figure 10 shows lxt972a phy operational and test loopback paths. (an internal digital loopback path is not shown.) for more information on loopback functions, see table 14, carrier sense, loopback , and collision conditions , on page 33 .) table 14 carrier sense, loopba ck, and collision conditions speed duplex condition carrier sense test loop- back 1, 2 operational loop- back 1, 2 collision 100 mbps full-duplex receive only yes no none half-duplex transmit or receive no no transmit and receive 10 mbps full-duplex receive only yes no none half-duplex, register bit 16.8 = 0 transmit or receive yes yes transmit and receive half-duplex, register bit 16.8 = 1 transmit or receive no no transmit and receive 1. test loopback is enabled when register bit 0.14 = 1. 2. for descriptions of test loopbac k and operational loopback, see section 5.6.7, loopback , on page 33 .
page 34 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.6 mii operation 5.6.7.1 operational loopback ? operational loopback is provided for 10 mbps half-duplex links when register bit 16.8 = 0. data that the mac (txdata) transmits loops back on the receive side of the mii (rxdata). ? operational loopback is not provided for 100 mbps links, full-duplex links, or when register 16.8 = 1. 5.6.7.2 internal digital lo opback (test loopback) a test loopback function is pr ovided for diagnostic testing of the lxt972a phy. during test loopback, twisted-pair interfaces are disabled. data transmitted by the mac is internally looped back by the lxt972a phy and returned to the mac. test loopback is available fo r both 100base-tx and 10base-t operation, and is enabled by setting the following register bits: ? register bit 0.14 = 1 (setting to enable loopback mode) ? register bit 0.8 = 1 (setting for full-duplex mode) ? register bit 0.12 = 0 (disable auto-negotiation) note: parallel detection can reso lve the phy configuration. figure 10 loopback paths b3393-02 10t loopback digital block mii 100 x loopback analog block lxt97x phy operational loopback test loopback tx driver
page 35 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation 5.7 100 mbps operation 5.7.1 100base-x network operations during 100base-x operation, the lxt972a ph y transmits and receives 5-bit symbols across the network link. figure 11 shows the structure of a standard frame pack et in 100base-x mode. when the mac is not actively transmitting data, the lxt972a phy sends out idle symbols on the line. as figure 11 shows, the mac starts each transmission with a preamble pattern. as soon as the lxt972a phy detects the start of preamble, it transmits a start-of-stream delimiter (ssd, symbols j and k) to the network. it th en encodes and transmits the rest of the packet, including the balance of the preamble, the sfd, packet data, and crc. once the packet ends, the lxt972a phy transmits the end-of-stream delimiter (esd, symbols t and r) and then returns to transmitting idle symbols. for details on the symbols used, see 4b/5b coding listed in ta b l e 1 5 , 4b/5b coding , on page 39 . as shown in figure 12, in 100base-tx mode, the lx t972a phy scrambles and transmits the data to the network using mlt-3 line code. mlt-3 signals received from the network are de-scrambled, decoded, and sent across the mii to the mac. figure 11 100base-x frame format p0 p1 p6 sfd 64-bit preamble (8 octets) start-of-frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet length (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code-groups end-of-stream delimiter (esd) ifg replaced by /j/k/ code-groups start-of-stream delimiter (ssd) b3466-01
page 36 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation figure 13 shows normal reception with no errors. as shown in figure 14 , when the lxt972a phy receives invalid symbols from the line, it asserts rx_er. figure 12 100base-tx data path s0 s1 s2 s3 s4 parallel to serial serial to parallel mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scrambler bypass data flow s0 s1 s2 s3 s4 standard data flow d0 d1 d2 d3 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble b3467-01 figure 13 100base-tx reception with no errors rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da da da crc crc crc crc b3468-01
page 37 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation 5.7.2 collision indication figure 15 shows normal transmission. upon detection of a collis ion, the col output is asserted and remains asserted for the duration of the co llision as shown in figure 16 . figure 14 100base-tx recept ion with invalid symbol rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da xx xx xx xx xx xx xx xx xx xx b3469-01 figure 15 100base-tx transmission with no errors da da da da da dada da da tx_clk tx_en txd<3:0> crs col pr ea mb le b3470-01 figure 16 100base-tx tran smission with collision jam tx_clk tx_en txd<3:0> crs col pr ea mb le jam jam jam b3471-01
page 38 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation 5.7.3 100base-x protocol sublayer operations with respect to the 7-layer communications model, the lxt972a phy is a physical layer 1 (phy) device. the lxt972a phy implements the following subl ayers of the reference model defined by the ieee 802.3 standard, a nd discussed from the refere nce model point of view: ? section 5.7.3.1, physical coding sublayer ? section 5.7.3.2, physical medium attachment sublayer ? section 5.7.3.3, twisted-pair physical medium dependent sublayer figure 17 shows the lxt972a phy protocol sublayers. 5.7.3.1 physical coding sublayer the physical coding sublayer (pcs) provides the mii interface, as well as the 4b/5b encoding/decoding function. for 100base-tx operation, the pcs layer provides idle sy mbols to the pmd-layer line driver as long as tx_en is de-asserted. 5.7.3.1.1 preamble handling when the mac asserts tx_en, the pcs substitutes a /j/k symbol pair, also known as the start-of-stream delimiter (ssd), for the first two nibbles received across the mii. the pcs layer continues to encode the remaining mii data, following the 4b/5b coding in ta b l e 1 5 , until tx_en is de-asserted. it then returns to supplying idle symbols to the line driver. figure 17 protocol sublayers encoder/decoder serializer /de-serializer link/carrier detect pcs sublayer pma sublayer mii interface lxt97x phy 100base-tx scrambler/ de-scrambler pmd sublayer b3395 -03
page 39 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation in the receive direction, the pcs layer perf orms the opposite functi on, substituting two preamble nibbles for the ssd. in 100 mbps operation, preamble is always passed through the pcs layer to the mii interface. table 15 4b/5b coding (sheet 1 of 2) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation data 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 used as inter-stream fill code control 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs, and /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs, and /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
page 40 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation 5.7.3.2 physical medium attachment sublayer 5.7.3.2.1 link in 100 mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. this operation filters out small noise hits that may disrupt the link. for short periods, mlt-3 idle waveforms meet all criteria for 10base-t start delimiters. a working 10base-t receive may te mporarily indicate link to 100base-tx waveforms. however, the phy does not bring up a permanent 10 mbps link. the lxt972a phy reports link failure through the mii status bits (register bits 1.2 and 17.10) and interrupt functions. link failure causes the lxt972a phy to re-negotiate if auto-negotiation is enabled. 5.7.3.2.2 link failure override the lxt972a phy normally transmits data packets only if it detects the link is up. setting register bit 16.14 = 1 overrides this function, allowing the lxt972a phy to transmit data packets even when the link is down. this featur e is provided as a transmit diagnostic tool. note: auto-negotiation must be disabled to transmit data packets in the absence of link. if auto- negotiation is enabled, the lxt972a phy automatically transmits flp bursts if the link is down. caution: during normal operation, cortina does not recommend setting register bit 16.14 for 100 mbps receive functions because receive errors may be generated. invalid undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid table 15 4b/5b coding (sheet 2 of 2) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs, and /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs, and /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
page 41 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.7 100 mbps operation 5.7.3.2.3 carrier sense for 100base-tx links, a start-of -stream delimiter (ssd) or /j/k symbol pair causes assertion of carrier sense (crs). an end-of-s tream delimiter (esd) or /t/r symbol pair causes de-assertion of crs. the pma layer al so de-asserts crs if idle symbols are received without /t/r. however, in this case rx_er is asserted for one clock cycle when crs is de-asserted. cortina does not recommend using crs for interframe gap (ifg) timing for the following reasons: ? crs de-assertion time is slig htly longer than crs assertion time. as a result, an ifg interval appears somewhat shorter to the mac than it actually is on the wire. ? crs de-assertion is not aligned with tx_en de-assertion on transmit loopbacks in half-duplex mode. 5.7.3.2.4 receive data valid the lxt972a phy asserts rx_dv to indicate that the received data maps to valid symbols. in 100 mbps operation, rx_dv is ac tive with the first nibble of preamble. 5.7.3.3 twisted-pair physical medium dependent sublayer the twisted-pair physical medium dependent (pmd) layer provides signal scrambling and de-scrambling functions, line coding and decoding functions (mlt-3 for 100base-tx, manchester for 10base-t) , as well as receiving, polarity correction, and baseline wander correction functions. 5.7.3.3.1 scrambler/descrambler the purpose of the scrambler/descrambler is to spread the signal power spectrum and further reduce emi using an 11-bit, data -independent polynomial. the receiver automatically decodes the polynomial whenever idle symbols are received. scrambler seeding. once the transmit data (or idle symbols) are properly encoded, they are scrambled to further reduce emi and to spread the power spectrum using an 11-bit scrambler seed. five seed bits are determi ned by the phy address, and the remaining bits are hard coded in the design. scrambler bypass. the scrambler/de-scrambler can be bypassed by setting register bit 16.12 = 1. scrambler bypass is provided for diagnostic and test support. 5.7.3.3.2 polarity correction the 100 mbps twisted pair signaling is not pola rity sensitive. as a result, the polarity status is not a valid status indicator. 5.7.3.3.3 baseline wander correction the lxt972a phy provides a baseline wander correction function for when the lxt972a phy is under network operating conditions. the mlt3 coding sche me used in 100base- tx is by definition ?unbalanced?. as a result , the average value of the signal voltage can ?wander? significantly over short time interv als (tenths of seconds). this wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. exact characteristics of the wander are completely data dependent. the lxt972a phy baseline wander correction characteristics allow the device to recover error-free data while rece iving worst-case packets over all cable lengths.
page 42 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.8 10 mbps operation 5.7.3.3.4 programmable slew rate control the lxt972a phy device supports a progra mmable slew-rate mechanism whereby one of four pre-selected slew rates can be used. (for details, see table 55, transmit control register - address 30, hex 1e , on page 78 .) the slew-rate mechanism allows the designer to optimize the output waveform to match the characteristics of the magnetics. note: for hardware control of the slew rate, use the txslew pins. 5.8 10 mbps operation the lxt972a phy opera tes as a standard 10 base-t phy and lxt972a phy supports standard 10 mbps functions. during 10base-t operation, the lxt972a phy transmits and receives xilinks* manche ster-encoded data across th e network link. when the mac is not actively transmitting data, the lxt9 72a phy drives link pulses onto the line. in 10base-t mode, the polynomial scrambler /de-scrambler is inactive. manchester- encoded signals received from the network are decoded by the lxt972a phy and sent across the mii to the mac. 5.8.1 10base-t preamble handling the lxt972a phy offers two options for preamble handling, selected by register bit 16.5. ? in 10base-t mode when register bit 16.5 = 0, the lxt972a phy strips the entire preamble off of received pa ckets. crs is asserted coinci dent with the start of the preamble. rx_dv is held low for the duration of the preamble. when rx_dv is asserted, the very first two nibbles driven by the lxt972a phy are the sfd ?5d? hex followed by the body of the packet. ? in 10base-t mode when register bit 16. 5 = 1, the lxt972 a phy passes the preamble through the mii and asserts rx_dv and crs simultaneously. (in 10base-t loopback, the lxt972a phy loops back whatev er the mac transmits to it, including the preamble.) 5.8.2 10base-t carrier sense for 10base-t links, cr s assertion is based on reception of valid preamble, and crs de- assertion is based on reception of an end-of-f rame (eof) marker. register bit 16.7 allows crs de-assertion to be synchronized with rx_dv de-assertion. for details, see ta b l e 4 9 , configuration register - address 16, hex 10 , on page 71 . 5.8.3 10base-t dribble bits the lxt972a phy handles dribble bits in all modes. if one to four dribble bits are received, the nibble is passed across the mii, padded with ones if necessary. if five to seven dribble bits are received, the seco nd nibble is not sent to the mii bus. 5.8.4 10base-t link integrity test in 10base-t mode, the lx t972a phy always tr ansmits link pulses. ? if the link integrity test function is en abled (the normal configuration), the lxt972a phy monitors the connection for link puls es. once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. if the link pulses st op, the data transmission is disabled.
page 43 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.9 monitoring operations ? if the link integrity test function is disabled (which can be done by setting configuration register bit 16.14 to ?1?), the lxt972a phy transmits to the connection regardless of dete cted link pulses. 5.8.5 link failure link failure occurs if the link integrity test is enabled and link pulses or packets stop being received. if this condition occurs, the lxt972a phy returns to the auto-negotiation phase if auto-negotiation is enabled. if the link integrity test function is disabled by setting configuration register bit 16.14 to ?1?, the lxt972a phy transmits packets, regardless of link status. 5.8.6 10base-t sqe (heartbeat) by default, the signal quality error (sqe) or heartbeat function is disabled on the lxt972a phy. to enable this function, set re gister bit 16.9 = 1. when this function is enabled, the lxt972a phy asserts its col output for 5 to 15 bit times (bt) after each packet. for sqe timing parameters, see figure 26, 10base-t sqe (heartbeat) timing , on page 58 . 5.8.7 10base-t jabber if a transmission exceeds the jabber timer, the lxt972a phy disables the transmit and loopback functions. for jabber timing parameters, see figure 25, 10base-t jabber and unjabber timing , on page 58 . the lxt972a phy automatically exits jabber mode after the unjabber time has expired. this function can be disabled by setting register bit 16.10 = 1. 5.8.8 10base-t polarity correction the lxt972a phy automatically detects and corrects for the condition in which the receive signal (tpip/n) is inverted. reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame (eof) markers, are received consecutively. if link pulses or data are not received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a non-inverted state. when polarity reversal is detected in 10base-t operation, r egister 17.5 is set to 1. (for details, see bit 17.5 in table 50, status register #2 - address 17, hex 11 , on page 72 .) 5.9 monitoring operations 5.9.1 monitoring auto-negotiation auto-negotiation can be monitored as follows: ? register bit 17.7 is set to ?1? once th e auto-negotiation process is completed. ? register bits 1.2 and 17.10 are set to ?1? once the link is established. ? register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). note: when the lxt972a phy detects incorrect polar ity for a 10base-t operation, register bit 17.5 is set to ?1?.
page 44 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.9 monitoring operations 5.9.2 monitoring next page exchange the lxt972a phy offers an alternate next page mode to simplify the next page exchange process. normally, register bit 6.1 (page received) remains set until read. when alternate next page mode is enabled, r egister bit 6.1 is automatically cleared whenever a new negotiation process takes plac e. this action prevents the user from reading an old value in bit 6.1 and assuming that registers 5 and 8 (partner ability) contain valid information. additionally, the lx t972a phy uses register bit 6.5 to indicate when the current received page is the base page. this informat ion is useful for recognizing when next pages must be resent due to a new negotiation process starting. register bits 6.1 and 6.5 are cleared when read. 5.9.3 led functions the lxt972a phy has these direct led dr iver pins: led1/cfg1, led2/cfg2, and led3/cfg3. on power-up, all the drivers are asserted for approximately 1 second after reset de- asserts. each led driver can be programm ed using the led configuration register ( table 53, led configuration register - address 20, hex 14 , on page 76 ) to indicate one of the following conditions: ? collision condition ? duplex mode ? link status ? operating speed ? receive activity ? transmit activity the led drivers can also be programmed to display various combined status conditions. for example, setting register bits 20.15:12 to ?1101? produces the following combination of link and activity indications: ? if link is down, led is off. if activity is detected from the mac, the led still blinks even if the link is down. ? if link is up, led is on. ? if link is up and activity is detected, the led blinks at the stretch interval selected by register bits 20.3:2 and continues to b link as long as activity is present. the lxt972a phy led driver pins also prov ide initial configuration settings. the led pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits (10 ma max current rating) as required by the hardware configuration. for details, see the discussion of section 5.4.4, hardware configuration settings , on page 28 . 5.9.4 led pulse stretching the led configuration register also provides optional led pulse stretching to 30, 60, or 100 ms. the pulse stretch time is extended further if the event occurs again during this pulse stretch period.
page 45 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.10 boundary scan (jtag 1149.1) functions when an event such as receiving a packet occurs, the event is edge detected and it starts the stretch timer. the led driver remains a sserted until the stretch timer expires. if another event occurs before the stretch timer expires, then the stretch timer is reset and the stretch time is extended. when a long event (such as duplex status) occu rs, the event is edge detected and it starts the stretch timer. when the stretch timer expires, the edge detector is reset so that a long event causes another pulse to be generated from the edge detector, which resets the stretch timer and causes the led driver to remain asserted. figure 18 shows how the stretch operation functions. 5.10 boundary scan (j tag 1149.1) functions the lxt972a phy includes a ieee 1149.1 bo undary scan test port for board level testing. all digital input, output, and input/output pins are accessible. note: for the related bsdl file, contact your local sales office or access the cortina website (www.cortina-systems.com) . 5.10.1 boundary scan interface the boundary scan interface consists of five pins (tms, tdi, tdo, trst_l, and tck). it includes a state machine, data register array, and instruction register. the tms and tdi pins are pulled up internally. tck is pulled down internally. tdo does not have an internal pull-up or pull-down. 5.10.2 state machine the tap controller is a state machine, with 16 states driven by the tck and tms pins. upon reset, the test_logic_reset state is entered. the state machine is also reset when tms and tdi are high for five tck periods. 5.10.3 instruction register after the state machine resets, the idcode instruction is always invoked. the decode logic ensures the correct data flow to the data registers according to the current instruction. ta b l e 1 6 lists valid lxt972a phy jtag instructions. figure 18 led pulse stretching event led note: the direct drive led outputs in this diagram are shown as active low. stretch stretch stretch b3475-01
page 46 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 5.10 boundary scan (jtag 1149.1) functions 5.10.4 boundary scan register each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage. ta b l e 1 6 lists the four bsr modes of operation. 5.10.5 device id register ta b l e 1 7 lists the bits for the device id regist er. for the current version of the jedec continuation characters, see the specif ication update for the lxt972a phy. table 16 bsr mode of operation mode description 1c a p t u r e 2s h i f t 3 update 4 system function table 17 device id register bits 31:28 bits 27:12 bits 11:8 bits 7:1 bit 0 version part id (hex) jedec continuation characters jedec id 1 reserved xxxx 03cb 0000 111 1110 1 1. the jedec id is an 8-bit identifier. the msb is for parity and is ignored. the jedec id is fe (1111 1110), which bec omes 111 1110.
page 47 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 6.0 application information 6.0 application information 6.1 magnetics information the lxt972a phy requires a 1:1 ratio for both the receive and transmit transformers. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. for transformer/magnetics requirements, see ta b l e 1 8 . note: before committing to a specific component, contact the manufacturer for current product specifications and validate the magne tics for the specific application. 6.2 typical twisted-pair interface ta b l e 1 9 provides a comparison of the rj-45 connections for nic and switch applications in a typical twisted-pa ir interface setting. figure 19 shows the lxt972a phy in a typical t wisted-pair interfac e, with the rj-45 connections crossed over for a switch configuration. table 18 magnetics requirements parameter min nom max units test condition rx turns ratio ? 1 : 1 ? ? ? tx turns ratio ? 1 : 1 ? ? ? insertion loss 0.0 0.6 1.1 db ? primary inductance 350 ? ? h? transformer isolation ? 1.5 ? kv ? differential to common mode rejection 40 ? ? db 0.1 to 60 mhz 35 ? ? db 60 to 100 mhz return loss -16 ? ? db 30 mhz -10 ? ? db 80 mhz table 19 i/o pin comparison of nic and switch rj-45 setups symbol rj-45 switch nic tpip 1 3 tpin 2 6 tpop 3 1 tpon 6 2
page 48 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 6 . 2 ty pi cal twis te d-pai r interface figure 20 shows the lxt972a phy in a typical t wisted-pair interfac e, with the rj-45 connections configured for a nic application. figure 19 typical twisted-pair interface - switch tpip tpin rj-45 * = 0.001 f / 2.0 kv to t wisted-pair netw ork 3 6 1 2 1:1 lxt 97x phy 50 50 50 50 50 50 4 5 8 7 1:1 1 tpop tpon vcca gnd 0.1 f .01 f 2 270 pf 5% 270 pf 5% 0.01 f 50 1% 50 1% ** 3 4 0.1 f 1. center tap current may be supplied from 3.3 v v cca as shown. additional power savings may be realized by supplying the center ta p from a 2.5 v current source. a separate ferrite bead (rated at 50 ma) should be used to supply center tap current. 2. the 100 transmit load termination resistor typi cally required is integrated in the phy. 3. magnetics without a receive pair center -tap do not require a 2 kv termination. 4. rj-45 connections shown are fo r a standard switch application.
page 49 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 6 . 2 ty pi cal twis te d-pai r interface figure 20 typical twisted-pair interface - nic tpip tpin * = 0.001 f / 2.0 kv to twisted-pair network 1:1 lxt 97x phy 1:1 1 tpop tpon vcca gnd 0.1 f .01 f 2 270 pf 5% 270 pf 5% 0.01 f 50 1% 50 1% ** 3 sd/tp_l 6 3 8 7 5 4 1 2 50 50 50 rj-45 50 50 50 4 0.1 f b3399-03 1. center tap current may be supplied from 3.3 v v cca as shown. additional power savings may be realized by supplying the center tap from a 2.5 v curr ent source. a separate ferrite bead (rated at 50 ma) should be used to supply center-tap current. 2. the 100 transmit load termination re sistor typically required is integrated in the phy. 3. magnetics without a receive pair center tap do not require a 2 kv termination. 4. rj-45 connections shown for standard nic. tx/rx cr ossover may be required for repeater and switch applications.
page 50 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 6 . 2 ty pi cal twis te d-pai r interface figure 21 show a typical media independent interface (mii) for the lxt972a phy. figure 21 typical media independent interface mac tx_en tx_er txd[3:0] tx_clk rx_dv rx_er rxd[3:0] crs col rx_clk lxt 97x phy trans - former rj-45 b3400-03
page 51 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.0 electrical specifications 7.0 electrical specifications this chapter includes test specifications fo r the lxt972a phy. these specifications are guaranteed by test except where noted ?by design?. 7.1 dc electric al parameters see the following dc specifications: ?table20, absolute maximum ratings , on page 51 ?table21, recommended operating conditions , on page 51 ?table22, digital i/o characteristics (except for mii, xi/xo, and led/cfg pins) , on page 52 ?table23, digital i/o characteristics 1 - mii pins , on page 52 ?table24, i/o characteristics - refclk/xi and xo pins , on page 53 ?table25, i/o characteristics - led/cfg pins , on page 53 ?table26, 100base-tx phy characteristics , on page 53 ?table27, 10base-t phy ch aracteristics , on page 54 ?table28, 10base-t link integrity timing characteristics , on page 54 ?table29, thermal characteristics , on page 54 caution: exceeding the absolute maximum rating values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for ex tended periods may affect device reliability. table 20 absolute maximum ratings parameter sym min max units supply voltage v cc -0.3 4.0 v storage temperature t st -65 +150 oc table 21 recommended operatin g conditions (sheet 1 of 2) parameter sym min typ 1 max units recommended operating temperature t op a 0?70oc recommended supply voltage 2 - analog and digital vcca, vccd 3.14 3.3 3.45 v recommended supply voltage 2 - i/o vccio 2.35 ? 3.45 v vcc current - 100 base-tx i cc ? 92 110 ma vcc current - 10 base-t i cc ?6682ma 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. voltages are with respect to ground unless otherwise specified.
page 52 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.1 dc electrical parameters hard power down i cc ?? 1ma soft power down icc ? 51 ? ma auto-negotiation i cc ? 90 110 ma table 22 digital i/o characteristics (exc ept for mii, xi/xo, and led/cfg pins) parameter sym min typ 1 max units test conditions input low voltage v il ??0 . 8v? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a 0.0 < v i < v cc output low voltage v ol ??0 . 4vi ol = 4 ma output high voltage v oh 2.4 ? ? v i oh = -4 ma 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. table 23 digital i/o characteristics 1 - mii pins parameter sym min typ 2 max units test conditions input low voltage v il ??0.8v? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a 0.0 < v i < vccio output low voltage v ol ??0.4vi ol = 4 ma output high voltage v oh 2.2 ? ? v i oh = -4 ma, vccio = 3.3 v v oh 2.0 ? ? v i oh = -4 ma, vccio = 2.5 v driver output resistance (line driver output enabled) r o 3 ? 100 ? vccio = 2.5 v r o 3 ? 100 ? vccio = 3.3 v 1. mii digital i/o pins are tolerant to 5 v inputs. 2. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 3. parameter is guaranteed by design and not subject to production testing. table 21 recommended operatin g conditions (sheet 2 of 2) parameter sym min typ 1 max units 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. voltages are with respect to ground unless otherwise specified.
page 53 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.1 dc electrical parameters table 24 i/o characteristics - refclk/xi and xo pins parameter symbol min typ 1 max units test conditions input low voltage v il ??0.8v ? input high voltage v ih 2.0 ? ? v ? input clock frequency tolerance 2 f?? 100 ppm ? input clock duty cycle 2 tdc 35 ? 65 % ? input capacitance c in ?3.0 ?pf ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. parameter is guaranteed by design and not subject to production testing. table 25 i/o characteristics - led/cfg pins parameter symbol min typ max units test conditions input low voltage v il ??0.8 v ? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a0 < v i < vccio output low voltage v ol ??0.4 vi ol = 10 ma output high voltage v oh 2.0 ? ? v i oh = -10 ma table 26 100base-tx phy characteristics parameter symbol min typ 1 max units test conditions peak differential output voltage v p 0.95 ? 1.05 v note 2 signal amplitude symmetry vss 98 ? 102 % note 2 signal rise/fall time t rf 3.0 ? 5.0 ns note 2 rise/fall time symmetry t rfs ? ? 0.5 ns note 2 duty cycle distortion d cd 35 50 65 % offset from 16 ns pulse width at 50% of pulse peak overshoot/undershoot v os ?? 5 % ? jitter (measured differentially) ? ? ? 1.4 ns ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. measured at the line side of th e transformer, line replaced by 100 (+/-1%) resistor.
page 54 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters 7.2 ac timing diagra ms and parameters see the following timing diagrams and ac parameters: ? figure 22, 100base-tx receive timing , on page 55 ? figure 23, 100base-tx transmit timing , on page 56 ? figure 24, 10base-t transmit timing , on page 57 table 27 10base-t phy characteristics parameter symbol min typ max units test conditions transmitter peak differential output voltage v op 2.2 2.5 2.8 v with transformer, line replaced by 100 resistor transition timing jitter added by the mau and pls sections ?0211ns after line model specified by ieee 802.3 for 10base-t mau receiver receive input impedance z in ??22k ? differential squelch threshold v ds 300 420 585 mv ? table 28 10base-t link integr ity timing characteristics parameter symbol min typ max units test conditions time link loss receive t ll 50 ? 150 ms ? link pulse t lp 2?7link pulses ? link min receive timer t lr m in 2?7 ms ? link max receive timer t lr m ax 50 ? 150 ms ? link transmit period tlt 8 ? 24 ms ? link pulse width tlpw 60 ? 150 ns ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. table 29 thermal characteristics parameter value package 1 0x 10 x1.4 64 ld lqfp theta-ja 58 c/w theta-jc 27 c/w psi - jt 3.4 c/w
page 55 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters ? figure 25, 10base-t jabber and unjabber timing , on page 58 ? figure 26, 10base-t sqe (heartbeat) timing , on page 58 ? figure 27, auto-negotiation and fast link pulse timing , on page 59 ? figure 28, fast link pulse timing , on page 59 ? figure 29, mdio input timing , on page 60 ? figure 30, mdio output timing , on page 60 ? figure 31, power-up timing , on page 61 ? figure 32, reset_l pulse width and recovery timing , on page 61 figure 22 100base-tx receive timing t4 t5 t3 t6 t7 0 ns 250 ns crs rx_dv rxd[3:0] rx_clk col t1 t2 tpi b3492-03 note: timing diagram depicts 4b mode.
page 56 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters table 30 100base-tx receive timing parameters - 4b mode parameter sym min typ 1 max units 2 test conditions rxd[3:0], rx_dv, rx_er 3 setup to rx_clk high t1 10 ? ? ns ? rxd[3:0], rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? crs asserted to rxd[3:0], rx_dv t3 3 ? 5 bt ? receive start of ?j? to crs asserted t4 12 ? 16 bt ? receive start of ?t? to crs de-asserted t5 10 ? 17 bt ? receive start of ?j? to col asserted t6 16 ? 22 bt ? receive start of ?t? to col de-asserted t7 17 ? 20 bt ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. bt (bit time) is the duration of one bit as transferr ed to and from the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. 3. rx_er is not shown in the figure. figure 23 100base-tx transmit timing t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd[3:0] tpo crs b3454-03 note: timing diagram depicts 4b mode.
page 57 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters table 31 10base-t receive timing parameters parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t1 10 ? ? ns ? rxd, rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? tpip/n in to rxd out (rx latency) t3 4.2 ? 6.6 bt ? crs asserted to rxd, rx_dv, rx_er asserted t4 5 ? 32 bt ? rxd, rx_dv, rx_er de-asserted to crs de-asserted t5 0.3 ? 0.5 bt ? tpi in to crs asserted t6 2 ? 28 bt ? tpi quiet to crs de-asserted t7 6 ? 10 bt ? tpi in to col asserted t8 1 ? 31 bt ? tpi quiet to col de-asserted t9 5 ? 10 bt ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. bt (bit time) is the duration of one bit as transferr ed to and from the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. figure 24 10base-t transmit timing tx_clk txd, tx_en, tx_er crs tpo t 1 t 3 t 4 t 5 t 2 b3460-01
page 58 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters figure 25 10base-t jabber and unjabber timing table 32 10base-t jabber and unjabber timing parameter symbol min typ 1 max units test conditions maximum transmit time t1 20 ? 150 ms ? unjabber time t2 250 ? 750 ms ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. figure 26 10base-t sqe (heartbeat) timing table 33 phy 10base-t sqe (heartbeat) timing parameter symbol min typ 1 max units test conditions col (sqe) delay after tx_en off t1 0.65 ? 1.6 us ? col (sqe) pulse duration t2 0.5 ? 1.5 us ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. txd col t 1 t 2 tx_en b3455-01 tx_clk tx_en t 1 t 2 col b3458-01
page 59 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters figure 27 auto-negotiation and fast link pulse timing figure 28 fast link pulse timing table 34 auto-negotiation and fast link pulse timing parameters parameter symbol min typ 1 max units test conditions clock/data pulse width t1 ? 100 ? ns ? clock pulse to data pulse t2 55.5 ? 63.8 s? clock pulse to cl ock pulse t3 123 ? 127 s? flp burst width t4 ? 2 ? ms ? flp burst to flp burst t5 8 12 24 ms ? clock/data pulses per burst ? 17 ? 33 each clock pulse or data pulse ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. tpop t1 t1 t2 t3 clock pulse data pulse clock pulse b3464-01 t4 t5 flp burst flp burst tpop b3465-01
page 60 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters figure 29 mdio input timing figure 30 mdio output timing table 35 mdio timing parameter symbol min typ 1 max units test conditions mdio setup before mdc, sourced by sta t1 10 ? ? ns ? mdio hold after mdc, sourced by sta t2 5 ? ? ns ? mdc to mdio output delay, sourced by phy t3 ? ? 150 ns ? mdc period t4 125 ? ? ns mdc = 8 mhz 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. t1 mdc mdio t2 t3 mdc mdio t4
page 61 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters figure 31 power-up timing table 36 power-up timing parameter symbol min typ 1 max units test conditions voltage threshold v1 ? 2.9 ? v ? power up delay 2 t1 ? ? 300 s? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. power-up delay is specified as a maximum value be cause it refers to the phy guaranteed performance. the phy comes out of reset after a delay of no more than 300 s. system designers s hould consider this value as a minimum value. after threshold v1 is reached, the mac should delay no less than 300 s before accessing the mdio port. figure 32 reset_l pulse width and recovery timing t1 vcc mdio, and so on v1 b3494-01 t2 reset_l mdio, and so on t1 b3495-01
page 62 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 7.2 ac timing diagrams and parameters table 37 reset_l pulse width and recovery timing parameter symbol min typ 1 max units test conditions reset_l pulse width t1 10 ? ? ns ? reset_l recovery delay 2 t2 ? 300 s? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. reset recovery delay is specified as a maxim um value because it refers to the phy guaranteed performance. the phy comes out of reset after a delay of no more than 300 s. system designers should consider this value as a minimum value. after de-asserting reset _l, the mac should delay no less than 300 s before accessing the mdio port.
page 63 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers 8.0 register definitions - ieee base registers this chapter includes definitions for the i eee base registers used by the lxt972a phy. section 9.0, register definitions - product-specific registers includes definitions of additional product-specific lxt972a phy regist ers, which are defined in accordance with the ieee 802.3 standa rd for adding unique device functions. the lxt972a phy register set has multiple 16-bit registers. ? ta b l e 3 8 is a register set listing of the ieee base registers. ? ta b l e 3 9 through ta b l e 4 7 provide bit descriptions of the base registers (address 0 through 8), which are define d in accordance with the ?reconciliation sublayer and media independent interface? and ?physical layer link signaling for 10/100 mbps auto-negotiation? se ctions of the i eee 802.3 standard. table 38 register set for ieee base registers address register name bit assignments 0 control register see table 39 on page 64 1 status register #1 see table 40 on page 65 2 phy identification register 1 see table 41 on page 66 3 phy identification register 2 see table 42 on page 66 4 auto-negotiation advertisement register see table 43 on page 67 5 auto-negotiation link partner base page ability register see table 44 on page 68 6 auto-negotiation expansion register see table 45 on page 69 7 auto-negotiation next page transmit register see table 46 on page 69 8 auto-negotiation link partner next page receive register see table 47 on page 70 9 1000base-t/100base-t2 control register not implemented 10 1000base-t/100base-t2 status register not implemented 11 to 14 reserved not implemented 15 extended status register not implemented
page 64 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 39 control register - address 0, hex 0 bit name description type 1 default 0.15 reset 0 = normal operation 1 = phy reset r/w sc 0 0.14 loopback 0 = disable loopback mode 1 = enable loopback mode r/w 0 0.13 speed selection 0.6 0.13 speed selected r/w note 2 0 0 1 1 0 1 0 1 10 mbps 100 mbps 1000 mbps (not supported) reserved 0.12 auto-negotiation enable 0 = disable auto-negotiation process 1 = enable auto-negotiation process r/w note 2 0.11 power-down 0 = normal operation 1 = power-down r/w 0 0.10 isolate 0 = normal operation 1 = electrically isolate phy from mii r/w 0 0.9 restart auto- negotiation 0 = normal operation 1 = restart auto-negotiation process r/w sc 0 0.8 duplex mode 0 = half-duplex 1 = full-duplex r/w note 2 0.7 collision test 0 = disable col signal test 1 = enable col signal test r/w 0 0.6 speed selection 0.6 0.13 speed selected r/w 0 0 0 1 1 0 1 0 1 10 mbps 100 mbps 1000 mbps (not supported) reserved 0.5:0 reserved write as ?0?. ignore on read. r/w 00000 1. r/w = read/write sc = self clearing 2. some bits have their defaul t values determined at reset by hardware configuration pins. for default details for these bits, see section 5.4.4, hardware configuration settings .
page 65 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 40 mii status register #1 - address 1, hex 1 bit name description type 1 default 1.15 100base-t4 not supported 0 = phy not able to perform 100base-t4 1 = phy able to perform 100base-t4 ro 0 1.14 100base-x full- duplex 0 = phy not able to perform full-duplex 100base- x 1 = phy able to perform full-duplex 100base-x ro 1 1.13 100base-x half- duplex 0 = phy not able to perform half-duplex 100base-x 1 = phy able to perform half-duplex 100base-x ro 1 1.12 10 mbps full-duplex 0 = phy not able to operate at 10 mbps full-duplex mode 1 = phy able to operate at 10 mbps in full-duplex mode ro 1 1.11 10 mbps half-duplex 0 = phy not able to operate at 10 mbps in half- duplex 1 = phy able to operate at 10 mbps in half-duplex mode ro 1 1.10 100base-t2 full- duplex not supported 0 = phy not able to perform full-duplex 100base-t2 1 = phy able to perform full-duplex 100base-t2 ro 0 1.9 100base-t2 half- duplex not supported 0 = phy not able to perform half-duplex 100base-t2 1 = phy able to perform half-duplex 100base-t2 ro 0 1.8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 0 1.7 reserved ignore when read. ro 0 1.6 mf preamble suppression 0 = phy cannot accept management frames with preamble suppressed 1 = phy accepts management frames with preamble suppressed ro 0 1.5 auto-negotiation complete 0 = auto-negotiation not complete 1 = auto-negotiation complete ro 0 1.4 remote fault 0 = no remote fault condition detected 1 = remote fault condition detected ro/lh 0 1.3 auto-negotiation ability 0 = phy is not able to perform auto-negotiation 1 = phy is able to perform auto-negotiation ro 1 1.2 link status 0 = link is down 1 = link is up ro/ll 0 1.1 jabber detect 0 = jabber condition not detected 1 = jabber condition detected ro/lh 0 1.0 extended capability 0 = basic register capabilities 1 = extended register capabilities ro 1 1. ro = read only ll = latching low lh = latching high
page 66 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 41 phy identification regi ster 1 - address 2, hex 2 bit name description type 1 default note: see figure 33 for identifier bit mapping. 2.15:0 phy id number the phy identifier is composed of bits 3 through 18 of the organizationally unique identifier (oui). ro 0013 hex 1. ro = read only table 42 phy identification regi ster 2 - address 3, hex 3 bit name description type 1 default note: see figure 33 for identifier bit mapping. 3.15:1 0 phy id number the phy identifier is composed of bits 19 through 24 of the oui. ro 011110 3.9:4 manufacturer?s model number 6 bits containing manufacturer?s part number. ro 001110 3.3:0 manufacturer?s revision number 4 bits containing manufacturer?s revision number. ro for current revision id information, see the specificatio n update. 1. ro = read only figure 33 phy identifier bit mapping b3504-01 note: the intel oui is 00207b hex 7b phy id register #1 (address 2) = 0013 organizationally unique identifier (qui) phy id register #2 (address 3) manufacturer's model number revision number 50 910 15 15 43 0 0 11 01 11 1 000011 1 00000 1000000000000 a b c r s x 00 0 3 20 00 note : the cortina oui is 00207b hex
page 67 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 43 auto-negotiation advertisem ent register - address 4, hex 4 bit name description type 1 default 4.15 next page 0 = port has no ability to send multiple pages. 1 = port has ability to send multiple pages. r/w 0 4.14 reserved ignore when read. ro 0 4.13 remote fault 0 = no remote fault. 1 = remote fault. r/w 0 4.12 reserved write as ?0?. ignore on read. r/w 0 4.11 asymmetric pause pause operation defined in ieee 802.3 standard, clause 40 and 27 r/w 0 4.10 pause 0 = pause operation disabled. 1 = pause operation enabled for full-duplex link. r/w note 2 4.9 100base-t4 0 = 100base-t4 capability is not available. 1 = 100base-t4 capability is available. note: the lxt972a phy does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 phy can be switched in if this capability is desired. r/w 0 4.8 100base-tx full-duplex (for lxt972a phy) 0 = port is not 100base-tx full-duplex capable. 1 = port is 100base-tx full-duplex capable. r/w note 3 4.7 100base-tx (for lxt972a phy) 0 = port is not 100base-tx capable. 1 = port is 100base-tx capable. r/w note 3 4.6 10base-t full-duplex (forlxt972a phy) 0 = port is not 10base-t full-duplex capable. 1 = port is 10base-t full-duplex capable. r/w note 3 4.5 10base-t 0 = port is not 10base-t capable. 1 = port is 10base-t capable. r/w note 3 4.4:0 selector field, s<4:0> 00001 =ieee 802.3. 00010 =ieee 802.9 islan-16t. 00000 =reserved for future auto-negotiation development. 11111 = reserved for future auto-negotiation development. note: unspecified or re served combinations must not be transmitted. r/w 00001 1. r/w = read/write ro = read only 2. default setting is determined by pin 33 at reset. 3. some bits have their default values determined at reset by hardware conf iguration pins. for default details for these bits, see section 5.4.4, hardware configuration settings .
page 68 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 44 auto-negotiation link partner base page ability register - address 5, hex 5 bit name description type 1 default 5.15 next page 0 = link partner has no ability to send multiple pages. 1 = link partner has ability to send multiple pages. ro 0 5.14 acknowledge 0 = link partner has not received link code word from the lxt972a phy. 1 = link partner has received link code word from the lxt972a phy. ro 0 5.13 remote fault 0 = no remote fault. 1 = remote fault. ro 0 5.12 reserved ignore when read. ro 0 5.11 asymmetric pause pause operation defined in ieee 802.3 standard, clause 40 and 27. 0 = link partner is not pause capable. 1 = link partner is pause capable. ro 0 5.10 pause 0 = link partner is not pause capable. 1 = link partner is pause capable. ro 0 5.9 100base-t4 0 = link partner is not 100base-t4 capable. 1 = link partner is 100base-t4 capable. ro 0 5.8 100base-tx full-duplex 0 = link partner is not 100base-tx full-duplex capable. 1 = link partner is 100base-tx full-duplex capable. ro 0 5.7 100base-tx 0 = link partner is not 100base-tx capable. 1 = link partner is 100base-tx capable. ro 0 5.6 10base-t full-duplex 0 = link partner is not 10base-t full-duplex capable. 1 = link partner is 10base-t full-duplex capable. ro 0 5.5 10base-t 0 = link partner is not 10base-t capable. 1 = link partner is 10base-t capable. ro 0 5.4:0 selector field s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto- negotiation development. unspecified or reserved combinations must not be transmitted. ro 0 1. ro = read only
page 69 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 45 auto-negotiation expansion - address 6, hex 6 bit name description type 1 default 6.15:6 reserved ignore when read. ro 0 6.5 base page this bit indicates the status of the auto-negotiation variable base page. it flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links. this bit is used only if register bit 16.1 (that is , alternate np feature) is set. 0 = base page = false (base page not received) 1 = base page = true (base page received) ro/lh 0 6.4 parallel detection fault 0 = parallel detection f ault has not occurred. 1 = parallel detection fault has occurred. ro/lh 0 6.3 link partner next page able 0 = link partner is not next page able. 1 = link partner is next page able. ro 0 6.2 next page able 0 = local device is not next page able. 1 = local device is next page able. ro 1 6.1 page received this bit is cleared on read. if register bit 16.1 is set, the page received bit is also cleared when either mr_page_rx = false or transmit_disable = true. 1 = indicates a new page is received and the received code word is loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of ieee 802.3. ro/lh 0 6.0 link partner a/n able 0 = link partner is not auto-negotiation able. 1 = link partner is auto-negotiation able. ro 0 1. ro = read only lh = latching high table 46 auto-negotiation next page tr ansmit register - address 7, hex 7 bit name description type 1 default 7.15 next page (np) 0 = last page 1 = additional next pages follow r/w 0 7.14 reserved ignore when read. ro 0 7.13 message page (mp) 0 = register bits 7.10:0 are user defined. 1 = register bits 7.10.0 follow ieee message page format. r/w 1 7.12 acknowledge 2 (ack2) 0 = cannot comply with message 1 = complies with message r/w 0 7.11 toggle (t) 0 = previous value of the transmitted link code word equalled logic one 1 = previous value of the transmitted link code word equalled logic zero r/w 0 7.10:0 message/ unformatted code field if register bits 7.13 = 0, register bits 7.10:0 are user-defined. if register bits 7.13 = 1, register bits 7.10:0 follow ieee message page format. r/w 0000 0000 001 1. ro = read only. r/w = read/write
page 70 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 8.0 register definitions - ieee base registers table 47 auto-negotiation link partner next page receive register - address 8, hex 8 bit name description type 1 default 8.15 next page (np) 0 = link partner has no additional next pages to send 1 = link partner has additional next pages to send ro 0 8.14 acknowledge (ack) 0 = link partner has not received link code word from lxt972a phy. 1 = link partner has received link code word from lxt972a phy. ro 0 8.13 message page (mp) 0 = register bits 8.10:0 are user defined. 1 = register bits 8.10:0 follow ieee message page format. ro 0 8.12 acknowledge 2 (ack2) 0 = link partner cannot comply with the message 1 = link partner complies with the message ro 0 8.11 toggle (t) 0 = previous value of transmitted link code word equal to logic one 1 = previous value of transmitted link code word equal to logic zero ro 0 8.10:0 message/ unformatted code field if register bit 8.13 = 0, register bits 18.10:0 are user defined. if register bit 8.13 = 1, register bits 18.10:0 follow ieee message page format. ro 0000 0000 00 1. ro = read only.
page 71 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers 9.0 register definitions - product-specific registers this chapter includes definitions of produ ct-specific lxt972a phy registers that are defined in accordance with the ieee 802.3 standar d for adding unique device functions. (for definitions of the ieee base regi sters used by the lxt972a phy, see section 8.0, register definitions - ieee base registers .) ? ta b l e 4 8 lists the register set of the product-specific registers. ? ta b l e 4 9 through ta b l e 5 5 provide bit descriptions of the product-specific registers (address 17 through 30). table 48 register set for product-specific registers address register name bit assignments 16 port configuration register see ta b l e 4 9 17 status register #2 see ta b l e 5 0 18 interrupt enable register see ta b l e 5 1 19 status change register see ta b l e 5 2 20 led configuration register see ta b l e 5 3 21 reserved ? 22-25 reserved ? 26 digital configuration register see ta b l e 5 4 27 reserved ? 28 reserved ? 29 reserved ? 30 transmit control register see ta b l e 5 5 31 reserved ? table 49 configuration register - address 16, hex 10 (sheet 1 of 2) bit name description type 1 default 16.15 reserved write as ?0?. ignore on read. r/w 0 16.14 force link pass 0 = normal operation 1 = force link pass r/w 0 16.13 transmit disable 0 = normal operation 1 = disable twisted pair transmitter r/w 0 16.12 bypass scrambler (100base-tx) 0 = normal operation 1 = bypass scrambler and descrambler r/w 0 16.11 reserved write as ?0?. ignore on read. r/w 0 16.10 jabber (10base-t) 0 = normal operation 1 = disable jabber correction r/w 0 16.9 sqe (10base-t) 0 = disable heart beat 1 = enable heart beat r/w 0 1. r/w = read /write
page 72 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers 16.8 tp loopback (10base-t) 0 = normal operation 1 = disable tp loopback during half-duplex operation r/w 0 16.7 crs select (10base-t) 0 = normal operation 1 = crs deassert extends to rx_dv deassert r/w 1 16.6 reserved write as ?0?. ignore on read. r/w 0 16.5 pre_en preamble enable. 0 = set rx_dv high coincident with sfd. 1 = set rx_dv high and rxd = preamble when crs is asserted. note: preamble is always enabled in 100 mbps operation. r/w 0 16.4:3 reserved write as ?0?. ignore on read. r/w 00 16.2 reserved write as ?0?. ignore on read. r/w 0 16.1 alternate np feature 0 = disable alternate auto negotiate next page feature. 1 = enable alternate auto negotiate next page feature. note: this bit enables or disables the register bit 6.5 capability. r/w 0 16.0 reserved write as ?0?. ignore on read. r/w 0 table 50 status register #2 - address 17, hex 11 (sheet 1 of 2) bit name description type 1 default 17.15 reserved always 0. ro 0 17.14 10/100 mode 0 = lxt972a phy is not operating 100base-tx mode. 1 = lxt972a phy is operating in 100base-tx mode. ro 0 17.13 transmit status 0 = lxt972a phy is not transmitting a packet. 1 = lxt972a phy is transmitting a packet. ro 0 17.12 receive status 0 = lxt972a phy is not receiving a packet. 1 = lxt972a phy is receiving a packet. ro 0 17.11 collision status 0 = no collision. 1 = collision is occurring. ro 0 17.10 link 0 = link is down. 1 = link is up. ro 0 17.9 duplex mode 0 = half-duplex. 1 = full-duplex. ro 0 17.8 auto-negotiation 0 = lxt972a phy is in manual mode. 1 = lxt972a phy is in auto-negotiation mode. ro 0 1. ro = read only. r/w = read/write table 49 configuration register - address 16, hex 10 (sheet 2 of 2) bit name description type 1 default 1. r/w = read /write
page 73 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers 17.7 auto-negotiation complete 0 = auto-negotiation process not completed. 1 = auto-negotiation process completed. this bit is valid only when auto negotiate is enabled. the value is equiva lent to the value of register bit 1.5. ro 0 17.6 reserved always 0. ro 0 17.5 polarity 0 = polarity is not reversed. 1 = polarity is reversed. note: polarity is not a valid status in 100 mbps mode. ro 0 17.4 pause 0 = the lxt972a phy is not pause capable. 1 = the lxt972a phy is pause capable. r0 17:3 error 0 = no error occurred 1 = error occurred (remote fault, jabber, parallel detect fault) note: the register bit is cleared when the registers that generate the error condition are read. ro 0 17:2 reserved always 0. ro 0 17:1 reserved always 0. ro 0 17.0 reserved always 0. ro 0 table 50 status register #2 - address 17, hex 11 (sheet 2 of 2) bit name description type 1 default 1. ro = read only. r/w = read/write
page 74 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers table 51 interrupt enable register - address 18, hex 12 bit name description type 1 default 18. 15:9 reserved write as ?0?. ignore on read. r/w n/a 18.8 reserved write as ?0?. ignore on read. r/w 0 18.7 anmsk mask for auto negotiate complete 0 = do not allow event to cause interrupt. 1 = enable event to cause interrupt. r/w 0 18.6 speedmsk mask for speed interrupt 0 = do not allow event to cause interrupt. 1 = enable event to cause interrupt. r/w 0 18.5 duplexmsk mask for duplex interrupt 0 = do not allow event to cause interrupt. 1 = enable event to cause interrupt. r/w 0 18.4 linkmsk mask for link status interrupt 0 = do not allow event to cause interrupt. 1 = enable event to cause interrupt. r/w 0 18.3 reserved write as ?0?. ignore on read. r/w 0 18.2 reserved write as ?0?. ignore on read. r/w 0 18.1 inten interrupt enable. 0 = disable interrupts. 1 = enable interrupts. r/w 0 18.0 tint test force interrupt 0 = normal operation. 1 = force interrupt on mdint_l r/w 0 1. r/w = read /write table 52 status change register - address 19, hex 13 (sheet 1 of 2) bit name description type 1 default 19.15:9 reserved ignore on read. ro n/a 19.8 reserved ignore on read. ro 0 19.7 andone auto-negotiation status 0 = auto-negotiation has not completed. 1 = auto-negotiation has completed. ro/ sc n/a 19.6 speedchg speed change status 0 = a speed change has not occurred since last reading this register. 1 = a speed change has occurred since last reading this register. ro/ sc 0 19.5 duplexchg duplex change status 0 = a duplex change has not occurred since last reading this register. 1 = a duplex change has occurred since last reading this register. ro/ sc 0 1. r/w = read/write, ro = read only, sc = self clearing.
page 75 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers 19.4 linkchg link status change status 0 = a link change has not occurred since last reading this register. 1 = a link change has occurred since last reading this register. ro/ sc 0 19.3 reserved ignore on read. ro 0 19.2 mdint_l 0 = management data interrupt (mii interrupt) status.no mii interrupt pending. 1 = mii interrupt pending. ro 0 19.1 reserved ignore on read. ro 0 19.0 reserved ignore on read. ro 0 table 52 status change register - address 19, hex 13 (sheet 2 of 2) bit name description type 1 default 1. r/w = read/write, ro = read only, sc = self clearing.
page 76 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers table 53 led configuratio n register - address 20, hex 14 (sheet 1 of 2) bit name description type 1 default 20.15:12 led1 programming bits 0000 =display speed status (continuous, default) 0001 =display transmit status (stretched) 0010 =display receive status (stretched) 0011 = display collisi on status (stretched) 0100 =display link status (continuous) 0101 =display duplex status (continuous) 0110 = unused 0111 = display receive or transmit activity (stretched) 1000 =test mode - turn led on (continuous) 1001 =test mode - turn led off (continuous) 1010 =1010 = test mode - blink led fast (continuous) 1011 = test mode - blink led slow (continuous) 1100 = display link and re ceive status combined 2 (stretched) 3 1101 = display link and ac tivity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0000 20.11:8 led2 programming bits 0000 =0000 = display speed status 0001 =display transmit status 0010 =display receive status 0011 = display collision status 0100 =display link status (default) 0101 =display duplex status 0110 = unused 0111 = display receiv e or transmit activity 1000 =test mode - turn led on 1001 =test mode - turn led off 1010 =test mode - blink led fast 1011 = test mode - blink led slow 1100 = display link and re ceive status combined 2 (stretched) 3 1101 = display link and ac tivity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0100 1. r/w = read /write. ro = read only. lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activi ty) causes the led to change state (blink). activity causes the le d to blink, regardless of the link status. 3. combined event led settings are not affected by puls e stretch register bit 20. 1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are approximations. no t guaranteed or production tested.
page 77 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers 20.7:4 led3 programming bits 0000 =display speed status 0001 =display transmit status 0010 =display receive status (default) 0011 = display collision status 0100 =display link status 0101 =display duplex status 0110 = unused 0111 = display receiv e or transmit activity 1000 =test mode- turn led on 1001 =test mode- turn led off 1010 =test mode- blink led fast 1011 = test mode- blink led slow 1100 = display link and re ceive status combined 2 (stretched) 3 1101 = display link and ac tivity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0010 20.3:2 ledfreq 5 00 = stretch led events to 30 ms. 01 = stretch led events to 60 ms. 10 = stretch led events to 100 ms. 11 = reserved. r/w 00 20.1 pulse- stretch 0 = disable pulse stretching of all leds. 1 = enable pulse stretching of all leds. r/w 1 20.0 reserved write as ?0?. ignore on read. r/w 0 table 54 digital configuration register - address 26, hex 1a (sheet 1 of 2) bit name description type 1 default 26.15:12 reserved write as ?0?. ignore on read. r/w 0000 26.11 mii drive strength mii drive strength 0 = normal mii drive strength 1 = increase mii drive strength r/w 0 26.10 reserved write as ?0?. ignore on read. r/w 0 26.9 show symbol error show symbol error 0 = normal mii_rxer 1 = 100base-x error signal to mii_rxer r/w 0 26.8:6 reserved write as ?0?. ignore on read. ro 0 1. r/w = read /write, ro = read only table 53 led configuratio n register - address 20, hex 14 (sheet 2 of 2) bit name description type 1 default 1. r/w = read /write. ro = read only. lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activi ty) causes the led to change state (blink). activity causes the le d to blink, regardless of the link status. 3. combined event led settings are not affected by puls e stretch register bit 20. 1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are approximations. no t guaranteed or production tested.
page 78 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 9.0 register definitions - product-specific registers 26.5:4 reserved write as ?0?. ignore on read. r/w 00 26.3 reserved write as ?0?. ignore on read. ro 0 26.2:0 reserved write as ?0?. ignore on read. r/w 0 table 55 transmit control register - address 30, hex 1e bit name description type 2 default 30.15:13 reserved write as ?0?. ignore on read. r/w 000 30.12 transmit low power transmit low power 0 = normal transmission. 1 = forces the transmitter into low power mode. also forces a zero-d ifferential transmission. r/w 0 30.11:10 port rise time control 1 port rise time control 00 = 3.0 ns (default = setting on txslew[1:0] pins) 01 = 3.4 ns 10 = 3.9 ns 11 = 4.4 ns r/w note 3 30.4:0 reserved ignore on read. r/w 0 1. values are approximations and ma y vary outside indicated values based upon implementation loading conditions. 2. r/w = read/write 3. latch state during reset is based on the stat e of hardware configurat ion pins at reset_l. table 54 digital configuration register - address 26, hex 1a (sheet 2 of 2) bit name description type 1 default 1. r/w = read /write, ro = read only
page 79 cortina systems ? lxt972a single-port 10/100 mbps phy transceiver lxt972a phy datasheet 249186, revision 5.2 13 september 2007 10.0 package specifications 10.0 package specifications figure 34 lqfp package specifications 64-pin low-profile quad flat pack note: the package figure is generic and d d 1 a 1 a 2 l a b l 1 3 3 e e 1 e / 2 e dim millimeters min max a ? 1.60 a 1 0.05 0.15 a 2 1.35 1.45 b 0.17 0.27 d 11.85 12.15 d 1 9.9 10.1 e 11.85 12.15 e 1 9.9 10.1 e 0.50 bsc 1 l 0.45 0.75 l 1 1.00 ref
~ end of document ~ for additional product an d ordering information: www.cortina-systems.com tm

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