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intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process and intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology 1 datasheet 2 ghz ? 3.40 ghz frequencies supporting hyper-threading technology 1 at 3.06 ghz with 533 mhz system bus and all frequencies with 800 mhz system bus the intel ? pentium ? 4 processor family supporting hyper-threading technology 1 (ht technology) delivers intel's most advanced, most powerful processors for desktop pcs and entry-level workstations, which are based on the intel netburst ? microarchitecture. the pentium 4 processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. these applications include internet audio and streaming video, image processing, video content creation, speech, 3d, cad, games, multimedia, and multitasking user environments. the intel ? pentium ? 4 processor extreme edition supporting ht technology features 2 mb of l3 cache and offers high levels of performance targeted specifically for high-end gamers and computing power users. available at 2 ghz, 2.20 ghz, 2.26 ghz, 2.40 ghz, 2.50 ghz, 2.53 ghz, 2.60 ghz, 2.66 ghz, 2.80 ghz, 3 ghz, 3.06 ghz, 3.20 ghz, and 3.40 ghz supports hyper-threading technology (ht technology) at 3.06 ghz with 533 mhz system bus and all frequencies with 800 mhz system bus binary compatible with applications running on previous members of the intel microprocessor line intel netburst ? microarchitecture system bus frequency at 400 mhz, 533 mhz, and 800 mhz rapid execution engine: arithmetic logic units (alus) run at twice the processor core frequency hyper-pipelined technology ? advance dynamic execution ? very deep out-of-order execution enhanced branch prediction optimized for 32-bit applications running on advanced 32-bit operating systems 8-kb level 1 data cache level 1 execution trace cache stores 12-k micro-ops and removes decoder latency from main execution loops 512-kb advanced transfer cache (on-die, full-speed level 2 (l2) cache) with 8-way associativity and error correcting code (ecc) 2-mb integrated level 3 (l3) cache with 8-way associativity that is supported by intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology 144 streaming simd extensions 2 (sse2) instructions enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3d performance power management capabilities ? system management mode ? multiple low-power states 8-way cache associativity provides improved cache hit rate on load/store operations 478-pin package february 2004 document number: 298643-012
2 intel ? pentium ? 4 processor on 0.13 micron process datasheet information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? pentium ? 4 processor on 0.13 micron process may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. 1 hyper-threading technology requires a computer system with an intel ? pentium ? 4 processor supporting ht technology and a hyper-threading technology enabled chipset, bios and operating system. performance will vary depending on the specific hardware and software yo u use. see <> for more information including details on which processors support ht technology. intel, pentium, intel netburst, and the intel logo are trademarks or registered trademarks of intel corporation or its subsidia ries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2001?2004, intel corporation
intel ? pentium ? 4 processor on 0.13 micron process datasheet 3 contents 1 introduction .................................................................................................................. 9 1.1 terminology.........................................................................................................11 1.1.1 processor packaging terminology.........................................................11 1.2 references ..........................................................................................................12 2 electrical specifications ........................................................................................15 2.1 system bus and gtlref ...................................................................................15 2.2 power and ground pins ......................................................................................15 2.3 decoupling guidelines ........................................................................................16 2.3.1 vcc decoupling .....................................................................................16 2.3.2 system bus agtl+ decoupling.............................................................16 2.4 voltage identification ...........................................................................................16 2.4.1 phase lock loop (pll) power and filter...............................................18 2.5 reserved, unused pins, and testhi[12:0]........................................................20 2.6 system bus signal groups .................................................................................21 2.7 asynchronous gtl+ signals...............................................................................22 2.8 test access port (tap) connection....................................................................22 2.9 system bus frequency select signals (bsel[1:0])............................................22 2.10 maximum ratings................................................................................................23 2.11 processor dc specifications...............................................................................23 2.12 agtl+ system bus specifications .....................................................................35 3 package mechanical specifications .................................................................37 3.1 package load specifications ..............................................................................40 3.2 processor insertion specifications ......................................................................41 3.3 processor mass specifications ...........................................................................41 3.4 processor materials.............................................................................................41 3.5 processor markings.............................................................................................42 4 pin lists and signal descriptions .....................................................................45 4.1 processor pin assignments ................................................................................45 4.2 signal descriptions..............................................................................................58 5 thermal specifications and design considerations .................................67 5.1 processor thermal specifications.......................................................................68 5.1.1 thermal specifications ...........................................................................68 5.1.2 thermal metrology .................................................................................70 5.1.2.1 processor case temperature measurement ............................70 6features .......................................................................................................................71 6.1 power-on configuration options ........................................................................71 6.2 clock control and low power states..................................................................71 6.2.1 normal state?state 1 ...........................................................................71 6.2.2 autohalt powerdown state?state 2...................................................72 6.2.3 stop-grant state?state 3 .....................................................................73 6.2.4 halt/grant snoop state?state 4 ........................................................73 6.2.5 sleep state?state 5..............................................................................74
4 intel ? pentium ? 4 processor on 0.13 micron process datasheet 6.3 thermal monitor .................................................................................................. 74 6.3.1 thermal diode........................................................................................ 76 7 boxed processor specifications ....................................................................... 77 7.1 introduction ......................................................................................................... 77 7.2 mechanical specifications................................................................................... 78 7.2.1 boxed processor cooling solution dimensions ..................................... 78 7.2.2 boxed processor fan heatsink weight.................................................. 79 7.2.3 boxed processor retention mechanism and heatsink assembly.......... 79 7.3 electrical requirements ...................................................................................... 80 7.3.1 fan heatsink power supply ................................................................... 80 7.4 thermal specifications........................................................................................ 82 7.4.1 boxed processor cooling requirements ............................................... 82 7.4.2 variable speed fan ............................................................................... 83 8 debug tools specifications ................................................................................. 85 8.1 logic analyzer interface (lai)............................................................................. 85 8.1.1 mechanical considerations .................................................................... 85 8.1.2 electrical considerations........................................................................ 85
intel ? pentium ? 4 processor on 0.13 micron process datasheet 5 figures 2-1 v cc vid pin voltage and current requirements .................................................17 2-2 typical vcciopll, vcca and vssa power distribution ..................................19 2-3 phase lock loop (pll) filter requirements ......................................................19 2-4 v cc static and transient tolerance (for intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process)...............................29 2-5 v cc static and transient tolerance (for intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology)...............31 2-6 itpclkout[1:0] output buffer diagram ............................................................34 2-7 test circuit ..........................................................................................................35 3-1 exploded view of processor components on a system board ..........................37 3-2 processor package .............................................................................................38 3-3 processor cross-section and keep-in ................................................................39 3-4 processor pin detail............................................................................................39 3-5 ihs flatness specification ..................................................................................40 3-6 processor markings (processors with fixed vid) ...............................................42 3-7 processor markings (processors with multiple vid) ...........................................42 3-8 the coordinates of the processor pins as viewed from the top of the package ....................................................................................................43 5-1 example thermal solution (not to scale) ...........................................................67 5-2 guideline locations for case temperature (tc) thermocouple placement ......70 6-1 stop clock state machine ...................................................................................72 7-1 mechanical representation of the boxed processor ..........................................77 7-2 side view space requirements for the boxed processor ..................................78 7-3 top view space requirements for the boxed processor ...................................79 7-4 boxed processor fan heatsink power cable connector description.................80 7-5 motherboard power header placement relative to processor socket ..............81 7-6 boxed processor fan heatsink airspace keep-out requirements (side 1 view) .......................................................................................................82 7-7 boxed processor fan heatsink airspace keep-out requirements (side 2 view) .......................................................................................................83 7-8 boxed processor fan heatsink set points .........................................................83
6 intel ? pentium ? 4 processor on 0.13 micron process datasheet tables 1-1 references.......................................................................................................... 12 2-1 v cc vid pin voltage requirements ..................................................................... 17 2-2 voltage identification definition........................................................................... 18 2-3 system bus pin groups ...................................................................................... 21 2-4 bsel[1:0] frequency table for bclk[1:0] ......................................................... 22 2-5 processor dc absolute maximum ratings ......................................................... 23 2-6 voltage and current specifications..................................................................... 24 2-7 v cc static and transient tolerance (for intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process) .............................. 28 2-8 vcc static and transient tolerance (for intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology) .............. 30 2-9 agtl+ signal group dc specifications ............................................................. 32 2-10 asynchronous gtl+ signal group dc specifications ........................................ 32 2-11 pwrgood and tap signal group dc specifications ...................................... 33 2-12 itpclkout[1:0] dc specifications.................................................................... 33 2-13 bsel [1:0] and vid[4:0] dc specifications......................................................... 34 2-14 agtl+ bus voltage definitions........................................................................... 35 3-1 description table for processor dimensions ...................................................... 38 3-2 package dynamic and static load specifications .............................................. 40 3-3 processor mass .................................................................................................. 41 3-4 processor material properties............................................................................. 41 4-1 pin listing by pin name ...................................................................................... 46 4-2 pin listing by pin number................................................................................... 52 4-3 signal descriptions ............................................................................................. 58 5-1 processor thermal design power ...................................................................... 69 6-1 power-on configuration option pins .................................................................. 71 6-2 thermal diode parameters ................................................................................. 76 6-3 thermal diode interface...................................................................................... 76 7-1 fan heatsink power and signal specifications................................................... 81 7-2 boxed processor fan heatsink set points ......................................................... 84
intel ? pentium ? 4 processor on 0.13 micron process datasheet 7 revision history revision description date -005 added thermal and electrical specifications for frequencies through 3.06 ghz and included multiple vid specifications. updated the thermtrip# and dbi# signal descriptions. removed deep sleep state section. updated boxed processor fan heatsink set points table and figure. update power- on configuration option pins table. november 2002 -006 minor update to dc specifications december 2002 -007 corrected table 4-3, signal description. item trst#, last sentence. measurement changed from 680 w pull-down resistor to 680 ? pull-down resistor. january 2003 -008 added 800 mhz system bus specifications. added impsel definition. updated stop-grant, halt, and autohalt states april 2003 -009 added thermal and electrical specifications for 2.40c ghz, 2.60c ghz, and 2.80c ghz with 800 mhz system bus. updated thermal specifications and thermal monitor chapter. updated prochot# pin definition. may 2003 -010 added thermal and electrical specifications for 3.20c ghz. updated processor markings. june 2003 -011 added intel ? pentium ? 4 processor extreme edition supporting hyper- threading technology november 2003 -012 added 3.40 ghz thermal and electrical specifications for the intel pentium 4 processor extreme edition and intel pentium 4 processor with 512-kb l2 cache on 0.13 micron process february 2004
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intel ? pentium ? 4 processor on 0.13 micron process datasheet 9 introduction introduction 1 the intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process and the intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology are follow-on processors to the intel ? pentium ? 4 processor in the 478-pin package with intel netburst ? microarchitecture. these processors use flip-chip pin grid array (fc-pga2) package technology, and plug into a 478-pin surface mount, zero insertion force (zif) socket, referred to as the mpga478b socket. the pentium 4 processor with 512-kb l2 cache on 0.13 micron process and the pentium 4 processor extreme edition supporting hyper-threading technology, like the pentium 4 processor in the 478-pin package, are based on the same intel 32-bit microarchitecture and maintain the tradition of compatibility with ia-32 software. the pentium 4 processor with 512-kb l2 cache on 0.13 micron process contains an on-die 512-kb advanced transfer l2 cache. the pentium 4 processor extreme edition supporting hyper-threading technology contains an on-die 512-kb level 2 (l2) advanced transfer cache and an on-die 2-mb integrated level 3 (l3) cache. both processors are on a 0.13 micron process. this document covers the pentium 4 processors with 512-kb l2 cache on 0.13 micron process and the pentium 4 processor extreme edition supporting hyper-threading technology. note: unless otherwise specified in this document, the term ?pentium 4 processor on 0.13 micron process? (or simply processor) refers to both the pentium 4 processor with 512-kb l2 cache on 0.13 micron process and the pentium 4 processor extreme edition supporting hyper-threading technology. hyper-threading technology 1 is a new feature in the pentium 4 processor on 0.13 micron process at 800 mhz system bus. it is also on the pentium 4 processor with 512-kb l2 cache on 0.13 micron process at 3.06 ghz/533 mhz system bus. ht technology allows a single, physical pentium 4 processor on 0.13 micron process to function as two logical processors. while some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architecture state with its own set of general-purpose registers, control registers to provide increased system responsiveness in multitasking environments, and headroom for next generation multi-threaded applications. intel recommends enabling ht technology with microsoft windows* xp professional or windows* xp home, and disabling ht technology via the bios for all previous versions of windows operating systems. for more information on hyper- threading technology, see www.intel.com/info/hyperthreading. refer to section 6.1 for ht technology configuration details. the intel netburst microarchitecture features include hyper-pipelined technology, a rapid execution engine, a 400 mhz, 533 mhz, or 800 mhz system bus, and an execution trace cache. the hyper-pipelined technology doubles the pipeline depth in the pentium 4 processor on 0.13 micron process, allowing the processor to reach much higher core frequencies. the rapid execution engine allows the two integer alus in the processor to run at twice the core frequency; this allows many integer instructions to execute in 1/2 clock cycle. the 400 mhz, 533 mhz, or 800 mhz system bus is a quad-pumped bus running off a 100 mhz or a 133 mhz system clock, making 3.2 gbytes/sec, 4.3 gbytes/sec, or 6.4 gbytes/sec data transfer rates possible. the execution trace cache is a first-level cache that stores approximately 12-k decoded micro- operations that removes the instruction decoding logic from the main execution path, thereby increasing performance.
10 intel ? pentium ? 4 processor on 0.13 micron process datasheet introduction additional features within the intel netburst microarchitecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and streaming simd extensions 2 (sse2). the advanced dynamic execution improves speculative execution and branch prediction internal to the processor. the advanced transfer cache is a 512-kb, on-die level 2 (l2) cache. a new floating point and multi-media unit has been implemented that provides superior performance for multi-media and mathematically intensive applications. finally, sse2 adds 144 new instructions for double-precision floating point, simd integer, and memory management. power management capabilities (such as autohalt, stop-grant, and sleep) have been retained. the streaming simd extensions 2 (sse2) enable break-through levels of performance in multi- media applications including 3-d graphics, video decoding/encoding, and speech recognition. the new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-d geometry techniques (such as ray tracing). the 2-mb l3 cache is available with only the pentium 4 processor extreme edition. the additional third level of cache is located on the processor die and is designed specifically to meet the compute needs of high-end gamers and other power users. the integrated level 3 cache is available in 2-mb and is coupled with the 800 mhz system bus to provide a high bandwidth path to memory. the efficient design of the integrated level 3 cache provides a faster path to large data sets stored in cache on the processor. this results in reduced average memory latency and increased throughput for larger workloads. the intel netburst microarchitecture system bus on the pentium 4 processor on 0.13 micron process uses a split-transaction, deferred reply protocol like the pentium 4 processor in the 478-pin package. this system bus is not compatible with the p6 processor family bus. the intel netburst microarchitecture system bus uses source-synchronous transfer (sst) of address and data to improve performance by transferring data four times per bus clock (4x data transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or 2x address bus. working together, the 4x data bus and 2x address bus provide a data bus bandwidth of up to 6.4 gbytes/second. intel will enable support components for the pentium 4 processor on 0.13 micron process including heatsinks, heatsink retention mechanisms, and sockets. manufacturability is a high priority; hence, mechanical assembly can be completed from the top of the motherboard, and should not require any special tooling. the processor system bus uses a variant of gtl+ signalling technology called assisted gunning transceiver logic (agtl+) signal technology.
intel ? pentium ? 4 processor on 0.13 micron process datasheet 11 introduction 1.1 terminology a ?#? symbol after a signal name refers to an active low signal, indicating that the signal is in the active state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the ?#? symbol indicates that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). the term ?system bus? refers to the interface between the processor and system core logic (also known as the chipset components). the system bus is a multiprocessing interface to processors, memory, and i/o. 1.1.1 processor packaging terminology commonly used terms are explained here for clarification: ? intel pentium 4 processor in the 478-pin package ? 0.18-micron pentium 4 processor core in the fc-pga2 package. ? intel pentium 4 processor in the 423-pin package ? 0.18-micron pentium 4 processor core in the pga package. ? intel pentium 4 processor with 512-kb l2 cache on 0.13 micron process ? 0.13 micron version of pentium 4 processor in the 478-pin package core in the fc-pga2 package with a 512-kb l2 cache. ? intel pentium 4 processor extreme edition supporting hyper-threading technology ? 0.13 micron version of pentium 4 processor in the 478-pin package core in the fc-pga2 package with a 512-kb l2 cache and a 2-mb l3 cache. ? processor ? for this document, the term processor shall mean pentium 4 processor with 512-kb l2 cache on 0.13 micron process and the pentium 4 processor extreme edition supporting hyper-threading technology. ? keep-out zone ? the area on or near the processor that system design can not utilize. this area must be kept free of all components to make room for the processor package, retention mechanism, heatsink, and heatsink clips. ? hyper-threading technology ? hyper-threading technology allows a single, physical pentium 4 processor to function as two logical processors when the necessary system ingredients are present. for more information, see: www.intel.com/info/hyperthreading. ? intel ? 875p chipset ? chipset that supports ddr memory technology for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process. this chipset also supports the pentium 4 processor extreme edition supporting hyper-threading technology in platforms that meet the thermal design guidelines for this processor. ? intel ? 865g/865gv/865pe chipset ? chipset that supports ddr memory technology for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process. ? intel ? 865p chipset ? chipset that supports ddr memory technology for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process. ? intel ? 850 chipset ? chipset that supports rambus rdram* memory technology for pentium 4 processor with 512-kb l2 cache on 0.13 micron process and pentium 4 processor in the 478-pin package. ? intel ? 845 chipset ? chipset that supports pc133 and ddr memory technologies for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process and pentium 4 processor in the 478-pin package.
12 intel ? pentium ? 4 processor on 0.13 micron process datasheet introduction ? processor core ? pentium 4 processor with 512-kb l2 cache on 0.13 micron process core die with integrated l2 cache and the pentium 4 processor extreme edition supporting hyper- threading technology core die with integrated l2 and l3 caches. ? fc-pga2 package ? flip-chip pin grid array package with 50-mil pin pitch and integrated heat spreader. ? mpga478b socket ? surface mount, 478 pin, zero insertion force (zif) socket with 50-mil pin pitch. the socket mates the processor to the system board. ? integrated heat spreader ? the surface used to make contact between a heatsink or other thermal solution and the processor. integrated heat spreader is abbreviated ihs. ? retention mechanism ? the structure mounted on the system board that provides support and retention of the processor heatsink. 1.2 references material and concepts available in the following documents may be beneficial when reading this document. table 1-1. references (sheet 1 of 2) document location intel ? 875p chipset platform design guide http://developer.intel.com/design/ chipsets/designex/252527.htm intel ? 865g/865pe/865p chipset platform design guide http://developer.intel.com/design/ chipsets/designex/252518.htm intel ? pentium ? 4 processor in the 478-pin package / intel ? 850 chipset platform family design guide http://developer.intel.com/design/ pentium4/guides/249888.htm intel ? pentium ? 4 processor in the 478-pin package and intel ? 845 chipset platform for ddr platform design guide http://developer.intel.com/design/ chipsets/designex/298605.htm intel ? pentium ? 4 processor in the 478-pin package and intel ? 845e chipset platform for ddr platform design guide http://developer.intel.com/design/ chipsets/designex/298652.htm intel ? pentium ? 4 processor in the 478-pin package and intel ? 845 chipset platform for sdr platform design guide http://developer.intel.com/design/ chipsets/designex/298354.htm intel ? pentium ? 4 processor in the 478-pin package and intel ? 845ge/845pe chipset platform design guide http://developer.intel.com/design/ chipsets/designex/251925.htm intel ? pentium ? 4 processor in 478-pin package and intel ? 845g/845gl/845gv chipset platform design guide http://developer.intel.com/design/ chipsets/designex/298654.htm intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines http://developer.intel.com/design/ pentium4/guides/252161.htm mechanical enabling for the intel ? pentium ? 4 processor in the 478-pin package http://developer.intel.com/design/ pentium4/guides/290728.htm assembling intel reference components for the intel ? pentium ? 4 processor in the 478-pin package http://developer.intel.com/design/ pentium4/guides/298590.htm voltage regulator-down (vrd) 10.0: for desktop socket 478 design guide http://developer.intel.com/design/ pentium4/guides/252885.htm voltage regulator module (vrm) 9.0 dc-dc converter design guidelines http://developer.intel.com/design/ pentium4/guides/249205.htm intel ? pentium ? 4 processor vr-down design guidelines http://developer.intel.com/design/ pentium4/guides/249891.htm ck00 clock synthesizer/driver design guidelines http://developer.intel.com/design/ pentium4/guides/249206.htm intel ? pentium ? 4 processor 478-pin socket (mpga478b) socket design guidelines http://developer.intel.com/design/ pentium4/guides/249890.htm
intel ? pentium ? 4 processor on 0.13 micron process datasheet 13 introduction ia-32 intel ? architecture software developer?s manual volume 1: basic architecture http://developer.intel.com/design/ pentium4/manuals/245470.htm ia-32 intel ? architecture software developer?s manual, volume 2: instruction set reference http://developer.intel.com/design/ pentium4/manuals/245471.htm ia-32 intel ? architecture software developer?s manual, volume 3: system programming guide http://developer.intel.com/design/ pentium4/manuals/245472.htm ap-485 intel ? processor identification and the cpuid instruction http://developer.intel.com/design/ xeon/applnots/241618.htm itp700 debug port design guide http://developer.intel.com/design/ xeon/guides/249679.htm table 1-1. references (sheet 2 of 2) document location
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intel ? pentium ? 4 processor on 0.13 micron process datasheet 15 electrical specifications electrical specifications 2 2.1 system bus and gtlref most pentium 4 processor on 0.13 micron process system bus signals use assisted gunning transceiver logic (agtl+) signalling technology. as with the p6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. like the pentium 4 processor in the 478-pin package, the termination voltage level for the pentium 4 processor on 0.13 micron process agtl+ signals is v cc , which is the operating voltage of the processor core. the use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for the pentium 4 processor on 0.13 micron process. because of the speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. design guidelines for the pentium 4 processor on 0.13 micron process system bus are detailed in the appropriate platform design guide (refer to table 1-1 ). the agtl+ inputs require a reference voltage (gtlref) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. gtlref must be generated on the system board. termination resistors are provided on the processor silicon and are terminated to its core voltage (v cc ). the intel ? 875p chipset, intel ? 865g/865gv/865pe/865p chipsets, intel ? 850 chipset, and the intel ? 845 chipset also provide on-die termination. this eliminates the need to terminate the bus on the system board for most agtl+ signals. however, some agtl+ signals do not include on-die termination and must be terminated on the system board. for more information, refer to the appropriate platform design guide. the agtl+ bus depends on incident wave switching. therefore, timing calculations for agtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. for more information, refer to the appropriate platform design guide. 2.2 power and ground pins for clean on-chip power distribution, the pentium 4 processor on 0.13 micron process has 85 vcc (power) and 180 vss (ground) inputs. all power pins must be connected to v cc , while all v ss pins must be connected to a system ground plane.the processor vcc pins must be supplied with the voltage defined by the vid (voltage id) pins and the loadline specifications (see figure 2-4 ).
16 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications 2.3 decoupling guidelines because of the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. this may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in table 2-6 . failure to do so can result in timing violations and/or affect the long term reliability of the processor. for further information and design guidelines, refer to the appropriate platform design guide and the intel ? pentium ? 4 processor vr-down design guidelines. 2.3.1 v cc decoupling vcc regulator solutions need to provide sufficient decoupling capacitance to satisfy processor voltage specifications. this includes bulk capacitance with low effective series resistance (esr) to keep the voltage rail within specifications during large swings in load current. in addition, ceramic decoupling capacitors are required to filter high frequency content generated by bus and processor activity. consult the voltage regulator down design guide and appropriate platform design guide for further information. 2.3.2 system bus agtl+ decoupling pentium 4 processors on 0.13 micron process integrate signal termination on the die and incorporate high frequency decoupling capacitance on the processor package. decoupling must also be provided by the system motherboard for proper agtl+ bus operation. for more information, refer to the appropriate platform design guide. 2.4 voltage identification the vid specification for pentium 4 processors on 0.13 micron process is supported by the intel ? pentium ? 4 processor vr-down design guidelines, voltage regulator-down (vrd) 10.0 design guide , and voltage regulator-down (vrd) 10.0 design guide addendum . the voltage set by the vid pins is the maximum voltage allowed by the processor. a minimum voltage is provided in table 2-6 and changes with frequency. this allows processors running at a higher frequency to have a relaxed minimum voltage specification. the specifications have been set such that one voltage regulator can work with all supported frequencies. pentium 4 processors on 0.13 micron process use five voltage identification pins, vid[4:0], to support automatic selection of power supply voltages. the vid pins for the pentium 4 processor on 0.13 micron process are open drain outputs driven by the processor vid circuitry. the vid signals rely on pull-up resistors tied to a 3.3 v (maximum) supply to set the signal to a logic high level. these pull-up resistors may be either external logic on the motherboard, or internal to the voltage regulator. table 2-2 specifies the voltage level corresponding to the state of vid[4:0]. a ?1? in this table refers to a high voltage level, and a ?0? refers to low voltage level. the definition provided in table 2-2 is not related in any way to previous p6 processors or vrs, but is compatible with the pentium 4 processor in the 478-pin package. if the processor socket is empty (vid[4:0] = 11111) or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. see the intel ? pentium ? 4 processor vr-down design guidelines, voltage regulator-down (vrd) 10.0 design guide , or voltage regulator-down (vrd) 10.0 design guide addendum for more details .
intel ? pentium ? 4 processor on 0.13 micron process datasheet 17 electrical specifications power source characteristics must be stable when the supply to the voltage regulator is stable. refer to the appropriate platform design guide for timing details of the power up sequence. refer to the appropriate platform design guide for implementation details. the voltage identification circuit requires an independent 1.2 v supply. this voltage must be routed to the processor v cc vid pin. figure 2-1 and table 2-1 show the voltage and current requirements of the v cc vid pin. note: 1. this specification applies to both static and transient components. the rising edge of v cc vid must be monotonic from 0 to 1.1 v. see figure 2-1 for current requirements. in this case, monotonic is defined as continuously increasing with less than 50 mv of peak to peak noise for any width greater than 2 ns superimposed on the rising edge. table 2-1. v cc vid pin voltage requirements symbol parameter min typ max unit notes v cc vid v cc for voltage identification circuit ?5% 1.2 +10% v 1 figure 2-1. v cc vid pin voltage and current requirements v cc vid 1.2 v + 10% 1.2 v - 5% 4 ns vids latched 30 ma 1.0 v 1 ma
18 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications 2.4.1 phase lock loop (pll) power and filter v cca and v cciopll are power sources required by the pll clock generators on the pentium 4 processor on 0.13 micron process. since these plls are analog, they require quiet power supplies for minimum jitter. jitter is detrimental to the system; it degrades external i/o timings as well as internal core timings (i.e., maximum frequency). to prevent this degradation, these supplies must be low pass filtered from v cc . a typical filter topology is shown in figure 2-2 . the ac low-pass requirements, with input at v cc and output measured across the capacitor (c a or c io in figure 2-2 ), is as follows: ? < 0.2 db gain in pass band ? < 0.5 db attenuation in pass band < 1 hz ? > 34 db attenuation from 1 mhz to 66 mhz ? > 28 db attenuation from 66 mhz to core frequency refer to the appropriate platform design guide for recommendations on implementing the filter. table 2-2. voltage identification definition processor pins v cc_max vid4 vid3 vid2 vid1 vid0 11111vrm output off 111101.100 111011.125 111001.150 110111.175 110101.200 110011.225 110001.250 101111.275 101101.300 101011.325 101001.350 100111.375 100101.400 100011.425 100001.450 011111.475 011101.500 011011.525 011001.550 010111.575 010101.600
intel ? pentium ? 4 processor on 0.13 micron process datasheet 19 electrical specifications . notes: 1. diagram not to scale. 2. no specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 mhz. figure 2-2. typical v cciopll , v cca and v ssa power distribution figure 2-3. phase lock loop (pll) filter requirements vcc vcca vssa vcciopll l l processor core pll c a c io 0 db ?28 db ?34 db 0.2 db ?0.5 db 1 mhz 66 mhz fcore fpeak 1 hz dc passband high frequency band forbidden zone forbidden zone
20 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications 2.5 reserved, unused pins, and testhi[12:0] all reserved pins must remain unconnected. connection of these pins to v cc , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future pentium 4 processors on 0.13 micron process. see chapter 4 for a pin listing of the processor and the location of all reserved pins. for reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. note that on-die termination has been included on the pentium 4 processor on 0.13 micron process to allow signals to be terminated within the processor silicon. unused active low agtl+ inputs may be left as no connects if agtl+ termination is provided on the processor silicon. table 2-3 lists details on agtl+ signals that do not include on- die termination. unused active high inputs should be connected through a resistor to ground (v ss ). refer to the appropriate platform design guide for the appropriate resistor values. unused outputs can be left unconnected. however, this may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. for unused agtl+ input or i/o signals that don?t have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors (rtt). see table 2-14 . the tap, asynchronous gtl+ inputs, and asynchronous gtl+ outputs do not include on-die termination. inputs and used outputs must be terminated on the system board. unused outputs may be terminated on the system board or left unconnected. note that leaving unused output unterminated may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. signal termination for these signal types is discussed in the appropriate platform design guide listed in table 1-1 . the testhi pins should be tied to the processor v cc using a matched resistor, where a matched resistor has a resistance value within 20% of the impedance of the board transmission line traces. for example, if the trace impedance is 50 ?, then a value between 40 ? and 60 ? is required. the testhi pins may use individual pull-up resistors or may be grouped together as follows: 1. testhi[1:0] 2. testhi[5:2] 3. testhi[10:8] 4. testhi[12:11] a matched resistor should be used for each group. additionally, if the itpclkout[1:0] pins are not used, they may be connected individually to v cc using matched resistors or may be grouped with testhi[5:2] with a single matched resistor. if they are being used, individual termination with 1 k ? resistors is required. tying itpclkout[1:0] directly to v cc or sharing a pull-up resistor to v cc will prevent use of debug interposers. this implementation is strongly discouraged for system boards that do not implement an inboard debug port. as an alternative, group2 (testhi[5:2]) and the itpclkout[1:0] pins may be tied directly to the processor v cc . this has no impact on system functionality. testhi0 and testhi12 may also be tied directly to the processor v cc if resistor termination is a problem, but matched resistor termination is recommended. in the case of the itpclkout[1:0] pins, direct tie to v cc is strongly discouraged for system boards that do not implement an inboard debug port. tying any of the testhi pins together will prevent the ability to perform boundary scan testing.
intel ? pentium ? 4 processor on 0.13 micron process datasheet 21 electrical specifications 2.6 system bus signal groups to simplify the following discussion, the system bus signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers that use gtlref as a reference level. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output? refers to the agtl+ output group as well as the agtl+ i/o group when driving. with the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals that are dependent on the rising edge of bclk0 (ads#, hit#, hitm#, etc.), and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address), as well as the rising edge of bclk0. asychronous signals are still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. table 2-3 identifies which signals are common clock, source synchronous, and asynchronous signals. notes: 1. refer to section 5.2 for signal descriptions. 2. these agtl+ signals do not have on-die termination. refer to section 2.5 and the itp700 debug port design guide for termination requirements. 3. in processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. 4. these signal groups are not terminated by the processor. refer to section 2.5 , the itp700 debug port design guide, and the appropriate platform design guide for termination requirements and further details. 5. the value of these pins during the active-to-inactive edge of reset# defines the processor configuration options. see section 6.1 for details. table 2-3. system bus pin groups signal group type signals 1 agtl+ common clock input common clock bpri#, defer#, reset# 2 , rs[2:0]#, rsp#, trdy# agtl+ common clock i/o synchronous ap[1:0]#, ads#, binit#, bnr#, bpm[5:0]# 2 , br0# 2 , dbsy#, dp[3:0]#, drdy#, hit#, hitm#, lock#, mcerr# agtl+ source synchronous i/o source synchronous agtl+ strobes common clock adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# asynchronous gtl+ input 4,5 asynchronous a20m#, ignne#, init#, lint0/intr, lint1/nmi, smi#, slp#, stpclk# asynchronous gtl+ output 4 asynchronous ferr#, ierr# 2 , thermtrip# asynchronous gtl+ input/ output 4 asynchronous prochot# tap input 4 synchronous to tck tck, tdi, tms, trst# tap output 4 synchronous to tck tdo system bus clock n/a bclk[1:0], itp_clk[1:0] 3 power/other n/a v cc , v cca , v cciopll , v cc vid, vid[4:0], v ss , v ssa , gtlref[3:0], comp[1:0], reserved, testhi[5:0, 12:8], itpclkout[1:0], thermda, thermdc, impsel, dbr# 3 , pwrgood, sktocc#, v cc_sense , v ss_sense, bsel[1:0], signals associated strobe req[4:0]#, a[16:3]# 5 adstb0# a[35:17]# 5 adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
22 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications 2.7 asynchronous gtl+ signals the pentium 4 processor on 0.13 micron process does not use cmos voltage levels on any signals that connect to the processor. as a result, legacy input signals (such as a20m#, ignne#, init#, lint0/intr, lint1/nmi, pwrgood, smi#, slp#, and stpclk#) use gtl+ input buffers. legacy output ferr# and other non-agtl+ signals (thermtrip#) use gtl+ output buffers. prochot# uses gtl+ input/output buffer. all of these signals follow the same dc requirements as agtl+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between gtl+ and agtl+). these signals do not have setup or hold time specifications in relation to bclk[1:0]. however, all of the asynchronous gtl+ signals are required to be asserted for at least two bclks for the processor to recognize them. see section 2.11 for the dc specifications for the asynchronous gtl+ signal groups. see section 6.2 for additional timing requirements for entering and leaving the low power states. 2.8 test access port (tap) connection because of the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the pentium 4 processor on 0.13 micron process be first in the tap chain and followed by any other components within the system. a translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. similar considerations must be made for tck, tms, and trst#. two copies of each signal may be required, with each driving a different voltage level. 2.9 system bus frequency select signals (bsel[1:0]) the bsel[1:0] are output signals used to select the frequency of the processor input clock (bclk[1:0]). table 2-4 defines the possible combinations of the signals, and the frequency associated with each combination. the required frequency is determined by the processor, chipset, and clock synthesizer. all agents must operate at the same frequency. the pentium 4 processor with 512-kb l2 cache on 0.13 micron process currently operates at a 400 mhz, 533 mhz, or 800 mhz system bus frequency. the pentium 4 processor extreme edition supporting hyper-threading technology currently operates at 800 mhz system bus frequency. individual processors will operate only at their specified system bus frequency. for more information about these pins, refer to section 4.2 and the appropriate platform design guidelines. table 2-4. bsel[1:0] frequency table for bclk[1:0] bsel1 bsel0 function l l 100 mhz l h 133 mhz h l 200 mhz h h reserved
intel ? pentium ? 4 processor on 0.13 micron process datasheet 23 electrical specifications 2.10 maximum ratings table 2-5 lists the processor?s maximum environmental stress ratings. the processor should not receive a clock while subjected to these conditions. functional operating parameters are listed in the dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from electro static discharge (esd), one should always take precautions to avoid high static voltages or electric fields. notes: 1. this rating applies to any processor pin. 2. contact intel for storage requirements in excess of one year. 2.11 processor dc specifications the processor dc specifications in this section are defined at the processor core silicon unless noted otherwise. see chapter 4 for the pin signal definitions and signal pin assignments. most of the signals on the processor system bus are in the agtl+ signal group. the dc specifications for these signals are listed in table 2-9 . previously, legacy signals and test access port (tap) signals to the processor used low-voltage cmos buffer types. however, these interfaces now follow dc specifications similar to gtl+. the dc specifications for these signal groups are listed in table 2-10 . table 2-6 through table 2-10 list the dc specifications for the pentium 4 processor on 0.13 micron process, and are valid only while meeting specifications for case temperature, clock frequency, and input voltages. care should be taken to read all notes associated with each parameter. processors with multiple vid have i cc _ max of the highest vid for the specified frequency. for example, for processors through 2.80 ghz, the i cc _ max would be the one at vid=1.525 v. table 2-5. processor dc absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature ?40 85 c 2 v cc any processor supply voltage with respect to v ss ?0.3 1.75 v 1 v inagtl+ agtl+ buffer dc input voltage with respect to v ss ?0.1 1.75 v v inasynch_gtl+ asynch gtl+ buffer dc input voltage with respect to v ss ?0.1 1.75 v i vid max vid pin current 5 ma
24 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications table 2-6. voltage and current specifications (sheet 1 of 4) symbol parameter min typ max unit notes 10 v cc (400 mhz fsb) v cc for processor at vid=1.475 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 1.315 1.310 1.300 1.300 1.295 refer to table 2-7 and figure 2-4 1.390 1.385 1.380 1.375 1.375 v 1, 2, 3, 4 v cc for processor at vid=1.500 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 1.340 1.335 1.330 1.325 1.320 1.415 1.410 1.405 1.400 1.400 v cc for processor at vid=1.525 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 1.365 1.360 1.350 1.350 1.345 1.440 1.435 1.430 1.430 1.425 v cc (533 mhz fsb) v cc for processor at vid=1.475 v 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 3.06 ghz 1.305 1.300 1.295 1.295 1.290 1.265 refer to table 2-7 and figure 2-4 1.380 1.380 1.375 1.370 1.370 1.345 v 1, 2, 3, 4 v cc for processor at vid=1.500 v 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 3.06 ghz 1.330 1.330 1.325 1.320 1.315 1.290 1.405 1.405 1.400 1.395 1.395 1.370 v cc for processor at vid=1.525 v 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 3.06 ghz 1.355 1.350 1.345 1.345 1.340 1.315 1.435 1.430 1.430 1.420 1.420 1.395 v cc for processor at vid=1.550 v 3.06 ghz 1.340 1.425
intel ? pentium ? 4 processor on 0.13 micron process datasheet 25 electrical specifications v cc (800 mhz fsb with 512-kb l2 cache only) v cc for processor at vid=1.475 v 2.40c ghz 2.60c ghz 2.80c ghz 3ghz 3.20c ghz 3.40 ghz 1.295 1.290 1.288 1.265 1.260 1.280 refer to table 2-7 , figure 2-4 . and table 2-8 , figure 2-5 1.375 1.370 1.369 1.350 1.345 1.350 v 1, 2, 3, 4,13 v cc for processor at vid=1.500 v 2.40c ghz 2.60c ghz 2.80c ghz 3ghz 3.20c ghz 3.40 ghz 1.320 1.315 1.313 1.290 1.285 1.305 1.400 1.395 1.394 1.375 1.370 1.375 v cc for process or at vid=1.525 v 2.40c ghz 2.60c ghz 2.80c ghz 3ghz 3.20c ghz 3.40 ghz 1.345 1.340 1.338 1.315 1.310 1.330 1.425 1.420 1.419 1.400 1.395 1.400 v cc for processor at vid=1.550 v 3ghz 3.20c ghz 3.40 ghz 1.340 1.335 1.355 1.425 1.420 1.425 v cc (800 mhz fsb with 2 mb l3 cache) vcc for processor at vid=1.475 v: 3.20 ghz 1.285 refer to table 2-8 and figure 2-5 1.340 v 1,2,4,13 vcc for processor at vid=1.500 v: 3.20 ghz 1.310 1.365 vcc for processor at vid=1.525 v 3.20 ghz 3.40 ghz 1.335 1.325 1.390 1.380 vcc for processor at vid=1.550 v 3.20 ghz 3.40 ghz 1.360 1.350 1.415 1.405 vcc for processor at vid=1.575 v 3.40 ghz 1.375 1.430 vcc for processor at vid=1.600 v 3.40 ghz 1.400 1.455 v cc vid v cc for voltage identification circuit ?5% 1.2 +10% v 9 table 2-6. voltage and current specifications (sheet 2 of 4) symbol parameter min typ max unit notes 10
26 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications i cc (400 mhz fsb) i cc for processor at vid=1.500 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 44.3 47.1 49.8 51.3 a 3,4,6,10 i cc for processor at vid=1.525 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 45.1 47.9 50.7 52.0 53.5 i cc for processor with multiple vids 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 45.1 47.9 50.7 52.0 53.5 i cc (533 mhz fsb) i cc for processor at vid=1.500 v 2.26 ghz 2.40b ghz 2.53 ghz 48 49.8 51.5 a 3,4,6,10 i cc for processor at vid=1.525 v 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 48.6 50.7 52.5 53.9 55.9 i cc for processor with multiple vids 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 3.06 ghz 48.6 50.7 52.5 53.9 55.9 65.4 i cc (800 mhz fsb with 512-kb l2 cache only) i cc for processor with multiple vids 2.40c ghz 2.60c ghz 2.80c ghz 3ghz 3.20c ghz 3.40 ghz 52.4 55.0 55.9 64.8 67.4 71.6 a 3,4,6,10 i cc (800 mhz fsb with 2-mb l3 cache) i cc for processor with multiple vids: 3.20 ghz 3.40 ghz 71.5 77.7 a 4,6,10,13 table 2-6. voltage and current specifications (sheet 3 of 4) symbol parameter min typ max unit notes 10
intel ? pentium ? 4 processor on 0.13 micron process datasheet 27 electrical specifications notes: 1. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. see table 2-2 for more information. the vid bits will set the maximum v cc with the minimum being defined according to current consumption at that voltage. 2. the voltage specification requirements are measured across v cc_sense and v ss_sense pins at the socket with a 100 mhz bandwidth oscilloscope, 1.5 pf maximum probe capacitance, and 1 m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 3. refer to table 2-7 and figure 2-4 for the minimum, typical, and maximum v cc allowed for a given current. the processor should not be subjected to any v cc and i cc combination wherein v cc exceeds v cc_max for a given current. failure to adhere to this specification can affect the long term reliability of the processor. 4. v cc_min is defined at i cc_max . 5. the current specified is also for autohalt state. 6. the maximum instantaneous current that the processor will draw while the thermal control circuit is active as indicated by the assertion of prochot# is the same as the maximum i cc for the processor. 7. i cc stop-grant and i cc sleep are specified at v cc_max . 8. these specifications apply to the processor with maximum vid setting of 1.525 v for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process. 9. this specification applies to both static and transient components. the rising edge of v cc vid must be monotonic from 0 to 1.1 v. see figure 2-1 for current requirements. in this case monotonic is defined as continuously increasing with less than 50 mv of peak to peak noise for any width greater than 2 ns superimposed on the rising edge. 10.i cc_max is specified for highest vid only. the processor will be shipped under multiple vids listed for each frequency; however, the i cc_max specifications will be the same as highest vid specified in table. 11.these specifications apply to the processor with maximum vid setting of 1.550 v for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process. 12.this specification applies to processors with maximum vid setting of 1.550 v for the pentium 4 processor extreme edition supporting hyper-threading technology. 13.refer to table 2-8 and figure 2-5 for the minimum, typical, and maximum v cc allowed for a given current. the processor should not be subjected to any v cc and i cc combination wherein v cc exceeds v cc_max for a given current. failure to adhere to this specification can affect the long term reliability of the processor. 14.these specifications apply to processors with maximum vid setting of 1.600 v for the pentium 4 processor extreme edition supporting hyper-threading technology. i sgnt islp i cc stop-grant 23 a 5,7,8 27 5,7,11 32 5,7,12 35 5,7,14 i tcc i cc tcc active i cc a6 i cc pll i cc for pll pins 60 ma table 2-6. voltage and current specifications (sheet 4 of 4) symbol parameter min typ max unit notes 10
28 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications notes: 1. the loadline specifications include both static and transient limits. 2. this table is intended to aid in reading discrete points on the following loadline figure. 3. the loadlines specify voltage limits at the die measured at v cc_sense and v ss_sense pins. voltage regulation feedback for voltage regulator circuits must be taken from processor v cc and v ss pins. refer to the intel ? pentium ? 4 processor vr-down design guidelines for v cc and v ss socket loadline specifications and vr implementation details. 4. adherence to this loadline specification for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process is required to ensure reliable processor operation. table 2-7. v cc static and transient tolerance (for intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process at frequencies up to and including 3.2 ghz) icc (a) voltage deviation from vid setting (v) 1,2,3 maximum typical minimum 0 0.000 ?0.025 ?0.050 5 ?0.010 ?0.036 ?0.062 10 ?0.019 ?0.047 ?0.075 15 ?0.029 ?0.058 ?0.087 20 ?0.038 ?0.069 ?0.099 25 ?0.048 ?0.079 ?0.111 30 ?0.057 ?0.090 ?0.124 35 ?0.067 ?0.101 ?0.136 40 ?0.076 ?0.112 ?0.148 45 ?0.085 ?0.123 ?0.160 50 ?0.095 ?0.134 ?0.173 55 ?0.105 ?0.145 ?0.185 60 ?0.114 ?0.156 ?0.197 65 ?0.124 ?0.166 ?0.209 70 ?0.133 ?0.177 ?0.222
intel ? pentium ? 4 processor on 0.13 micron process datasheet 29 electrical specifications notes: 1. the loadline specification includes both static and transient limits. 2. refer to table 2-7 for specific offsets from vid voltage which apply to all vid settings. 3. the loadlines specify voltage limits at the die measured at v cc_sense and v ss_sense pins. voltage regulation feedback for voltage regulator circuits must be taken from processor v cc and v ss pins. refer to the intel ? pentium ? 4 processor vr-down design guidelines v cc and v ss socket loadline specifications and vr implementation details. 4. adherence to this loadline specification for the pentium 4 processor with 512-kb l2 cache on 0.13 micron process is required to ensure reliable processor operation. figure 2-4. v cc static and transient tolerance (for intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process at frequencies up to and including 3.2 ghz) 70 60 50 40 i cc (a) 30 20 10 0 vid -250 mv vid -200 mv vid -150 mv vid -50 mv vid -100 mv vid vid +50 mv v cc (v) v cc maximum v cc typical v cc minimum
30 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications notes: 1. the loadline specifications include both static and transient limits. 2. this table is intended to aid in reading discrete points on the following loadline figure. 3. the loadlines specify voltage limits at the die measured at v cc_sense and v ss_sense pins. voltage regulation feedback for voltage regulator circuits must be taken from processor v cc and v ss pins. refer to the voltage regulator-down (vrd) 10.0 design guide addendum for v cc and v ss socket loadline specifications and vr implementation details. 4. adherence to this loadline specification for the processor is required to ensure reliable processor operation. table 2-8. vcc static and transient tolerance (for intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology, and intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process at 3.4 ghz) icc (a) voltage deviation from vid setting (v) 1,2,3 maximum typical minimum 0 0 -0.019 -0.038 5 -0.009 -0.029 -0.049 10 -0.019 -0.039 -0.059 15 -0.028 -0.049 -0.070 20 -0.037 -0.059 -0.080 25 -0.046 -0.068 -0.091 30 -0.056 -0.078 -0.101 35 -0.065 -0.088 -0.112 40 -0.074 -0.098 -0.122 45 -0.083 -0.108 -0.133 50 -0.093 -0.118 -0.143 55 -0.102 -0.128 -0.154 60 -0.111 -0.138 -0.164 65 -0.120 -0.147 -0.175 70 -0.130 -0.157 -0.185 75 -0.139 -0.167 -0.196 80 -0.148 -0.177 -0.206 85 -0.157 -0.187 -0.217 90 -0.167 -0.197 -0.227
intel ? pentium ? 4 processor on 0.13 micron process datasheet 31 electrical specifications notes: 1. the loadline specification includes both static and transient limits. 2. refer to table 2-8 for specific offsets from vid voltage which apply to all vid settings. 3. the loadlines specify voltage limits at the die measured at v cc_sense and v ss_sense pins. voltage regulation feedback for voltage regulator circuits must be taken from processor v cc and v ss pins. refer to the voltage regulator-down (vrd) 10.0 design guide addendum v cc and v ss socket loadline specifications and vr implementation details. 4. adherence to this loadline specification for the processor is required to ensure reliable processor operation. figure 2-5. v cc static and transient tolerance (for intel ? pentium ? 4 processor extreme edition supporting hyper-threading technology, and intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process at 3.4 ghz) i cc (amperes) 0306090 vid-250 mv vid+25 mv vid vid-225 mv vid-200 mv vid-175 mv vid-150 mv vid-125 mv vid-100 mv vid-75 mv vid-50 mv vid-25 mv v cc (volts) 10 40 70 20 50 v cc maximum v cc typical v cc minimum 80
32 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. v ih is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. refer to processor i/o buffer models for i/v characteristics. 5. the v cc referred to in these specifications is the instantaneous v cc . 6. vol max of 0.450 v is guaranteed when driving into a test load of 50 ? as indicated in figure 2-7 . 7. leakage to v ss with pin held at v cc . 8. leakage to v cc with pin held at 300 mv. 9. r on value is defined for a platform that is forward compatible with future processors. 10.gtlref value is defined for a platform that is forward compatible with future processors. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open-drain. 3. the v cc referred to in these specifications refers to instantaneous v cc . 4. this specification applies to the asynchronous gtl+ signal group. 5. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in figure 2-7 . 6. refer to the processor i/o buffer models for i/v characteristics. 7. vol max of 0.270 volts is guaranteed when driving into a test load of 50 ? as indicated in figure 2-7 for the asynchronous gtl+ signals. 8. leakage to v ss with pin held at v cc . 9. leakage to v cc with pin held at 300 mv. 10.r on value is defined for a platform that is forward compatible with future processors. table 2-9. agtl+ signal group dc specifications symbol parameter min max unit notes 1 gtlref reference voltage 2/3 v cc ? 2% 2/3 v cc + 2% v gtlref compatible reference voltage 0.63 v cc ? 2% 0.63 v cc +2% v 10 v ih input high voltage 1.10*gtlref v cc v2,5 v il input low voltage 0.0 0.9*gtlref v 3,5 v oh output high voltage n/a v cc v6 i ol output low current n/a 50 ma 5 i hi pin leakage high n/a 100 a 7 i lo pin leakage low n/a 500 a 8 r on buffer on resistance 7 11 ? 4 r on compatible buffer on resistance 8.4 13.2 ? 4, 9 table 2-10. asynchronous gtl+ signal group dc specifications symbol parameter min max unit notes 1 v ih input high voltage asynch gtl+ 1.10*gtlref v cc v3, 4 v il input low voltage asynch gtl+ 0 0.9*gtlref v 4 v oh output high voltage v cc v2, 3 i ol output low current 50 ma 5, 7 i hi pin leakage high n/a 100 a 8 i lo pin leakage low n/a 500 a 9 r on buffer on resistance asynch gtl+ 7 11 ? 4,6 r on compatible buffer on resistance asynch gtl+ 8.4 13.2 ? 4,6,10
intel ? pentium ? 4 processor on 0.13 micron process datasheet 33 electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open-drain. 3. refer to i/o buffer models for i/v characteristics. 4. the v cc referred to in these specifications refers to instantaneous v cc . 5. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in figure 2-7 . 6. vol max of 0.320 v is guaranteed when driving into a test load of 50 ? as indicated in figure 2-7 for the tap signals. 7. v hys represents the amount of hysteresis, nominally centered about 1/2 v cc for all tap inputs. 8. leakage to v ss with pin held at v cc . 9. leakage to v cc with pin held at 300 mv. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are not tested and are based on design simulations. 3. see figure 2-6 for itpclkout[1:0] output buffer diagram. table 2-11. pwrgood and tap signal group dc specifications symbol parameter min max unit notes 1 v hys input hysteresis 200 300 mv 6 v t+ input low to high threshold voltage 1/2*(v cc +v hys_min )1/2*(v cc +v hys_max )v4 v t- input high to low threshold voltage 1/2*(v cc ?v hys_max )1/2*(v cc ?v hys_min )v5 v oh output high voltage n/a v cc v2,3,4 i ol output low current n/a 40 ma 5,6 i hi pin leakage high n/a 100 a 8 i lo pin leakage low n/a 500 a 9 r on buffer on resistance 8.75 13.75 ? 3 table 2-12. itpclkout[1:0] dc specifications symbol parameter min max unit notes 1 ron buffer on resistance 27 46 ? 2,3
34 intel ? pentium ? 4 processor on 0.13 micron process datasheet electrical specifications notes: 1. see table 2-12 for range of ron. 2. the v cc referred to in this figure is the instantaneous vcc. 3. refer to the itp 700 debug port design guide and the appropriate platform design guidelines for the value of rext. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are not tested and are based on design simulations. 3. leakage to vss with pin held at 2.50 v. figure 2-6. itpclkout[1:0] output buffer diagram rext ron processor package to debug port v cc table 2-13. bsel [1:0] and vid[4:0] dc specifications symbol parameter min max unit notes 1 ron (bsel) buffer on resistance 9.2 14.3 ? 2 ron (vid) buffer on resistance 7.8 12.8 ? 2 i hi pin leakage high n/a 100 a 3
intel ? pentium ? 4 processor on 0.13 micron process datasheet 35 electrical specifications 2.12 agtl+ system bus specifications routing topology recommendations may be found in the appropriate platform design guide listed in table 1-1 . termination resistors are not required for most agtl+ signals because they are integrated into the processor silicon. valid high and low levels are determined by the input buffers which compare a signal?s voltage with a reference voltage called gtlref (known as v ref in previous documentation). table 2-14 lists the gtlref specifications. the agtl+ reference voltage (gtlref) should be generated on the system board using high precision voltage divider circuits. it is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the agtl+ signal group traces is known and is well-controlled. for more details on platform design, see the appropriate platform design guide . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. the tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of v cc . 3. gtlref should be generated from v cc by a voltage divider of 1% tolerance resistors or 1% tolerance, matched resistors. refer to the appropriate platform design guide for implementation details. 4. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. refer to processor i/o buffer models for i/v characteristics. 5. comp resistance must be provided on the system board with 1% tolerance resistors. see the appropriate platform design guide for implementation details. 6. the v cc referred to in these specifications is the instantaneous v cc . 7. the specifications are for a platform to be forward compatible with future processors. a compatible platform is one that is designed for some level of compatibility with future processors. table 2-14. agtl+ bus voltage definitions symbol parameter min typ max units notes 1 gtlref bus reference voltage 2/3 v cc ?2% 2/3 v cc 2/3 v cc +2% v 2, 3, 6 gtlref compatible bus reference voltage 0.63 v cc ?2% 0.63 v cc 0.63 v cc +2% v 2, 3, 6, 7 r tt termination resistance 45 50 55 ? 4 r tt compatible termination resistance 54 60 66 ? 4, 7 comp[1:0] comp resistance 50.49 51 51.51 ? 5 comp[1:0] compatible comp resistance 61.3 61.9 62.5 ? 5, 7 figure 2-7. test circuit 2.4 nh 1.2 pf rload = 50 ? v cc v cc 420 mils, 50 ? , 169 ps/in
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intel ? pentium ? 4 processor on 0.13 micron process datasheet 37 package mechanical specifications package mechanical specifications 3 the pentium 4 processor on 0.13 micron process is packaged in a flip-chip pin grid array (fc-pga2) package. components of the package include an integrated heat spreader (ihs), processor die, and the substrate which is the pin carrier. mechanical specifications for the processor are given in this section. see section 1.1 . for a terminology listing. the processor socket that accepts the pentium 4 processor on 0.13 micron process is referred to as a 478-pin micro pga (mpga478b) socket. see the intel ? pentium ? 4 processor 478-pin socket (mpga478b) socket design guidelines for complete details on the mpga478b socket. note: for figure 3-1 through figure 3-8 , the following notes apply: 1. unless otherwise specified, the following drawings are dimensioned in millimeters. 2. figures and drawings labelled as ?reference dimensions? are provided for informational purposes only. reference dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. reference dimensions are not checked as part of the processor manufacturing process. unless noted as such, dimensions in parentheses without tolerances are reference dimensions. 3. drawings are not to scale. note: figure 3-1 is not to scale and is for reference only. the socket and system board are supplied as a reference only. figure 3-1. exploded view of processor components on a system board s y stem board mpga478b 31 mm heat spreader substrate 35mm square 3.5mm 2.0mm 478 pins socket
38 intel ? pentium ? 4 processor on 0.13 micron process datasheet package mechanical specifications figure 3-2. processor package table 3-1. description table for processor dimensions code letter dimension (mm) notes min nominal max a1 2.266 2.378 2.490 original package (6 layer) a2 0.980 1.080 1.180 original package (6 layer) a1 2.42 2.55 2.67 alternate equivalent package (8 layer) a2 1.13 1.20 1.27 alternate equivalent package (8 layer) b1 30.800 31.000 31.200 b2 30.800 31.000 31.200 c1 33.000 includes placement tolerance c2 33.000 includes placement tolerance d 34.900 35.000 35.100 d1 31.500 31.750 32.000 g1 13.970 keep-in zone dimension g2 13.970 keep-in zone dimension g3 1.250 keep-in zone dimension h 1.270 l 1.950 2.030 2.110 p 0.280 0.305 0.330 pin tp 0.254 diametric true position (pin-to-pin) ihs flatness 0.05
intel ? pentium ? 4 processor on 0.13 micron process datasheet 39 package mechanical specifications figure 3-3 details the keep-in specification for pin-side components. the pentium 4 processor on 0.13 micron process may contain pin-side capacitors mounted to the processor package. figure 3-5 details the flatness and tilt specifications for the ihs. tilt is measured with the reference datum set to the bottom of the processor susbstrate. notes: 1. pin plating consists of 0.2 micrometers au over 2.0 micrometer ni. 2. 0.254 mm diametric true position, pin-to-pin. figure 3-3. processor cross-section and keep-in figure 3-4. processor pin detail 13.97mm 1.25mm ihs fcpga component keepin socket must allow clearance for pin shoulders and mate flush with this surface substrate 13.97mm 1.25mm ihs fcpga component keepin socket must allow clearance for pin shoulders and mate flush with this surface substrate 2 pinhead diameter ? 0.65 max keep out zone ? 1.032 max 2.030.08 solder fillet height 0.3 max all dimensions are in milimeters ? 0.3050.025
40 intel ? pentium ? 4 processor on 0.13 micron process datasheet package mechanical specifications notes: 1. flatness is specific as overall, not per unit of length. 2. all dimensions are in millimeters. 3.1 package load specifications table 3-2 provides dynamic and static load specifications for the processor ihs. these mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions. the heatsink attach solutions must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heatsink-to-processor thermal interface contact. it is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions. notes: 1. this specification applies to a uniform compressive load. 2. this is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 3. dynamic loading specifications are defined assuming a maximum duration of 11 ms and 200 lbf is achieved by superimposing a 100 lbf dynamic load (1 lbm at 50 g) on the static compressive load. figure 3-5. ihs flatness specification substrate ihs substrate ihs ihs table 3-2. package dynamic and static load specifications parameter max unit notes static 100 lbf 1, 2 dynamic 200 lbf 1, 3
intel ? pentium ? 4 processor on 0.13 micron process datasheet 41 package mechanical specifications 3.2 processor insertion specifications the pentium 4 processor on 0.13 micron process can be inserted and removed 15 times from a mpga478b socket meeting the intel ? pentium ? 4 processor 478-pin socket (mpga478b) socket design guidelines document. 3.3 processor mass specifications table 3-3 specifies the processor?s mass. this includes all components which make up the entire processor product. 3.4 processor materials the pentium 4 processor on 0.13 micron process is assembled from several components. the basic material properties are described in table 3-4 . table 3-3. processor mass processor mass (grams) intel ? pentium ? 4 processor on 0.13 micron process 19 table 3-4. processor material properties component material integrated heat spreader nickel over copper substrate fiber-reinforced resin substrate pins gold over nickel
42 intel ? pentium ? 4 processor on 0.13 micron process datasheet package mechanical specifications 3.5 processor markings figure 3-6 and figure 3-7 detail the processor top-side markings and is provided to aid in the identification of the pentium 4 processors on 0.13 micron process. note: intel will continue to ship old and new marked parts until old mark inventory has been depleted. figure 3-6. processor markings (processors with fixed vid) figure 3-7. processor markings (processors with multiple vid) 2-d matrix mark 2.40 ghz/512/800/1.50v syyyy xxxxxx ffffffff?nnnn m c `01 pentium ? 4 intel frequency/cache/bus/voltage s-spec/country of assy fpo ? serial # 2-d matrix mark 2.40 ghz/512/800 syyyy xxxxxx ffffffff?nnnn m c `01 pentium ? 4 intel frequency/cache/bus s-spec/country of assy fpo ? serial # 2-d matrix mark 2.40 ghz/512/800 syyyy xxxxxx ffffffff pentium ? 4 intel frequency/cache/bus s-spec/country of assy fpo aaaaaaaa nnnn unique unit identifier atpo serial # mc `03
intel ? pentium ? 4 processor on 0.13 micron process datasheet 43 package mechanical specifications figure 3-8. the coordinates of the processor pins as viewed from the top of the package
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intel ? pentium ? 4 processor on 0.13 micron process datasheet 45 pin lists and signal descriptions pin lists and signal descriptions 4 4.1 processor pin assignments this section contains pin lists for the pentium 4 processor on 0.13 micron process. table 4-1 is ordered alphabetically by pin name; table 4-2 is ordered alphabetically by pin number.
pin lists and signal descriptions 46 intel ? pentium ? 4 processor on 0.13 micron process datasheet table 4-1. pin listing by pin name pin name pin number signal buffer type direction a3# k2 source synch input/output a4# k4 source synch input/output a5# l6 source synch input/output a6# k1 source synch input/output a7# l3 source synch input/output a8# m6 source synch input/output a9# l2 source synch input/output a10# m3 source synch input/output a11# m4 source synch input/output a12# n1 source synch input/output a13# m1 source synch input/output a14# n2 source synch input/output a15# n4 source synch input/output a16# n5 source synch input/output a17# t1 source synch input/output a18# r2 source synch input/output a19# p3 source synch input/output a20# p4 source synch input/output a21# r3 source synch input/output a22# t2 source synch input/output a23# u1 source synch input/output a24# p6 source synch input/output a25# u3 source synch input/output a26# t4 source synch input/output a27# v2 source synch input/output a28# r6 source synch input/output a29# w1 source synch input/output a30# t5 source synch input/output a31# u4 source synch input/output a32# v3 source synch input/output a33# w2 source synch input/output a34# y1 source synch input/output a35# ab1 source synch input/output a20m# c6 asynch gtl+ input ads# g1 common clock input/output adstb0# l5 source synch input/output adstb1# r5 source synch input/output ap0# ac1 common clock input/output ap1# v5 common clock input/output bclk0 af22 bus clock input bclk1 af23 bus clock input binit# aa3 common clock input/output bnr# g2 common clock input/output bpm0# ac6 common clock input/output bpm1# ab5 common clock input/output bpm2# ac4 common clock input/output bpm3# y6 common clock input/output bpm4# aa5 common clock input/output bpm5# ab4 common clock input/output bpri# d2 common clock input br0# h6 common clock input/output bsel0 ad6 power/other output bsel1 ad5 power/other output comp0 l24 power/other input/output comp1 p1 power/other input/output d0# b21 source synch input/output d1# b22 source synch input/output d2# a23 source synch input/output d3# a25 source synch input/output d4# c21 source synch input/output d5# d22 source synch input/output d6# b24 source synch input/output d7# c23 source synch input/output d8# c24 source synch input/output d9# b25 source synch input/output d10# g22 source synch input/output d11# h21 source synch input/output d12# c26 source synch input/output d13# d23 source synch input/output d14# j21 source synch input/output d15# d25 source synch input/output d16# h22 source synch input/output d17# e24 source synch input/output d18# g23 source synch input/output d19# f23 source synch input/output d20# f24 source synch input/output d21# e25 source synch input/output d22# f26 source synch input/output d23# d26 source synch input/output d24# l21 source synch input/output d25# g26 source synch input/output d26# h24 source synch input/output d27# m21 source synch input/output d28# l22 source synch input/output d29# j24 source synch input/output d30# k23 source synch input/output d31# h25 source synch input/output d32# m23 source synch input/output table 4-1. pin listing by pin name pin name pin number signal buffer type direction
pin lists and signal descriptions intel ? pentium ? 4 processor on 0.13 micron process datasheet 47 d33# n22 source synch input/output d34# p21 source synch input/output d35# m24 source synch input/output d36# n23 source synch input/output d37# m26 source synch input/output d38# n26 source synch input/output d39# n25 source synch input/output d40# r21 source synch input/output d41# p24 source synch input/output d42# r25 source synch input/output d43# r24 source synch input/output d44# t26 source synch input/output d45# t25 source synch input/output d46# t22 source synch input/output d47# t23 source synch input/output d48# u26 source synch input/output d49# u24 source synch input/output d50# u23 source synch input/output d51# v25 source synch input/output d52# u21 source synch input/output d53# v22 source synch input/output d54# v24 source synch input/output d55# w26 source synch input/output d56# y26 source synch input/output d57# w25 source synch input/output d58# y23 source synch input/output d59# y24 source synch input/output d60# y21 source synch input/output d61# aa25 source synch input/output d62# aa22 source synch input/output d63# aa24 source synch input/output dbi0# e21 source synch input/output dbi1# g25 source synch input/output dbi2# p26 source synch input/output dbi3# v21 source synch input/output dbr# ae25 power/other output dbsy# h5 common clock input/output defer# e2 common clock input dp0# j26 common clock input/output dp1# k25 common clock input/output dp2# k26 common clock input/output dp3# l25 common clock input/output drdy# h2 common clock input/output dstbn0# e22 source synch input/output table 4-1. pin listing by pin name pin name pin number signal buffer type direction dstbn1# k22 source synch input/output dstbn2# r22 source synch input/output dstbn3# w22 source synch input/output dstbp0# f21 source synch input/output dstbp1# j23 source synch input/output dstbp2# p23 source synch input/output dstbp3# w23 source synch input/output ferr# b6 asynch agl+ output gtlref aa21 power/other input gtlref aa6 power/other input gtlref f20 power/other input gtlref f6 power/other input hit# f3 common clock input/output hitm# e3 common clock input/output ierr# ac3 common clock output ignne# b2 asynch gtl+ input impsel ae26 power/other input init# w5 asynch gtl+ input itpclkout0 aa20 power/other output itpclkout1 ab22 power/other output itp_clk0 ac26 tap input itp_clk1 ad26 tap input lint0 d1 asynch gtl+ input lint1 e5 asynch gtl+ input lock# g4 common clock input/output mcerr# v6 common clock input/output prochot# c3 asynch gtl+ input/output pwrgood ab23 power/other input req0# j1 source synch input/output req1# k5 source synch input/output req2# j4 source synch input/output req3# j3 source synch input/output req4# h3 source synch input/output reserved a22 reserved a7 reserved ad2 reserved ad3 reserved ae21 reserved af3 reserved af24 reserved af25 reset# ab25 common clock input rs0# f1 common clock input rs1# g5 common clock input table 4-1. pin listing by pin name pin name pin number signal buffer type direction
pin lists and signal descriptions 48 intel ? pentium ? 4 processor on 0.13 micron process datasheet rs2# f4 common clock input rsp# ab2 common clock input sktocc# af26 power/other output slp# ab26 asynch gtl+ input smi# b5 asynch gtl+ input stpclk# y4 asynch gtl+ input tck d4 tap input tdi c1 tap input tdo d5 tap output testhi0 ad24 power/other input testhi1 aa2 power/other input testhi2 ac21 power/other input testhi3 ac20 power/other input testhi4 ac24 power/other input testhi5 ac23 power/other input testhi8 u6 power/other input testhi9 w4 power/other input testhi10 y3 power/other input testhi11 a6 power/other input testhi12 ad25 power/other input thermda b3 power/other thermdc c4 power/other thermtrip# a2 asynch gtl+ output tms f7 tap input trdy# j6 common clock input trst# e6 tap input vcc a10 power/other vcc a12 power/other vcc a14 power/other vcc a16 power/other vcc a18 power/other vcc a20 power/other vcc a8 power/other vcc aa10 power/other vcc aa12 power/other vcc aa14 power/other vcc aa16 power/other vcc aa18 power/other vcc aa8 power/other vcc ab11 power/other vcc ab13 power/other vcc ab15 power/other vcc ab17 power/other vcc ab19 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction vcc ab7 power/other vcc ab9 power/other vcc ac10 power/other vcc ac12 power/other vcc ac14 power/other vcc ac16 power/other vcc ac18 power/other vcc ac8 power/other vcc ad11 power/other vcc ad13 power/other vcc ad15 power/other vcc ad17 power/other vcc ad19 power/other vcc ad7 power/other vcc ad9 power/other vcc ae10 power/other vcc ae12 power/other vcc ae14 power/other vcc ae16 power/other vcc ae18 power/other vcc ae20 power/other vcc ae6 power/other vcc ae8 power/other vcc af11 power/other vcc af13 power/other vcc af15 power/other vcc af17 power/other vcc af19 power/other vcc af2 power/other vcc af21 power/other vcc af5 power/other vcc af7 power/other vcc af9 power/other vcc b11 power/other vcc b13 power/other vcc b15 power/other vcc b17 power/other vcc b19 power/other vcc b7 power/other vcc b9 power/other vcc c10 power/other vcc c12 power/other vcc c14 power/other vcc c16 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction
pin lists and signal descriptions intel ? pentium ? 4 processor on 0.13 micron process datasheet 49 vcc c18 power/other vcc c20 power/other vcc c8 power/other vcc d11 power/other vcc d13 power/other vcc d15 power/other vcc d17 power/other vcc d19 power/other vcc d7 power/other vcc d9 power/other vcc e10 power/other vcc e12 power/other vcc e14 power/other vcc e16 power/other vcc e18 power/other vcc e20 power/other vcc e8 power/other vcc f11 power/other vcc f13 power/other vcc f15 power/other vcc f17 power/other vcc f19 power/other vcc f9 power/other vcca ad20 power/other vcciopll ae23 power/other vcc_sense a5 power/other output vccvid af4 power/other input vid0 ae5 power/other output vid1 ae4 power/other output vid2 ae3 power/other output vid3 ae2 power/other output vid4 ae1 power/other output vss d10 power/other vss a11 power/other vss a13 power/other vss a15 power/other vss a17 power/other vss a19 power/other vss a21 power/other vss a24 power/other vss a26 power/other vss a3 power/other vss a9 power/other vss aa1 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction vss aa11 power/other vss aa13 power/other vss aa15 power/other vss aa17 power/other vss aa19 power/other vss aa23 power/other vss aa26 power/other vss aa4 power/other vss aa7 power/other vss aa9 power/other vss ab10 power/other vss ab12 power/other vss ab14 power/other vss ab16 power/other vss ab18 power/other vss ab20 power/other vss ab21 power/other vss ab24 power/other vss ab3 power/other vss ab6 power/other vss ab8 power/other vss ac11 power/other vss ac13 power/other vss ac15 power/other vss ac17 power/other vss ac19 power/other vss ac2 power/other vss ac22 power/other vss ac25 power/other vss ac5 power/other vss ac7 power/other vss ac9 power/other vss ad1 power/other vss ad10 power/other vss ad12 power/other vss ad14 power/other vss ad16 power/other vss ad18 power/other vss ad21 power/other vss ad23 power/other vss ad4 power/other vss ad8 power/other vss ae11 power/other vss ae13 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction
pin lists and signal descriptions 50 intel ? pentium ? 4 processor on 0.13 micron process datasheet vss ae15 power/other vss ae17 power/other vss ae19 power/other vss ae22 power/other vss ae24 power/other vss ae7 power/other vss ae9 power/other vss af1 power/other vss af10 power/other vss af12 power/other vss af14 power/other vss af16 power/other vss af18 power/other vss af20 power/other vss af6 power/other vss af8 power/other vss b10 power/other vss b12 power/other vss b14 power/other vss b16 power/other vss b18 power/other vss b20 power/other vss b23 power/other vss b26 power/other vss b4 power/other vss b8 power/other vss c11 power/other vss c13 power/other vss c15 power/other vss c17 power/other vss c19 power/other vss c2 power/other vss c22 power/other vss c25 power/other vss c5 power/other vss c7 power/other vss c9 power/other vss d12 power/other vss d14 power/other vss d16 power/other vss d18 power/other vss d20 power/other vss d21 power/other vss d24 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction vss d3 power/other vss d6 power/other vss d8 power/other vss e1 power/other vss e11 power/other vss e13 power/other vss e15 power/other vss e17 power/other vss e19 power/other vss e23 power/other vss e26 power/other vss e4 power/other vss e7 power/other vss e9 power/other vss f10 power/other vss f12 power/other vss f14 power/other vss f16 power/other vss f18 power/other vss f2 power/other vss f22 power/other vss f25 power/other vss f5 power/other vss f8 power/other vss g21 power/other vss g24 power/other vss g3 power/other vss g6 power/other vss h1 power/other vss h23 power/other vss h26 power/other vss h4 power/other vss j2 power/other vss j22 power/other vss j25 power/other vss j5 power/other vss k21 power/other vss k24 power/other vss k3 power/other vss k6 power/other vss l1 power/other vss l23 power/other vss l26 power/other vss l4 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction
pin lists and signal descriptions intel ? pentium ? 4 processor on 0.13 micron process datasheet 51 vss m2 power/other vss m22 power/other vss m25 power/other vss m5 power/other vss n21 power/other vss n24 power/other vss n3 power/other vss n6 power/other vss p2 power/other vss p22 power/other vss p25 power/other vss p5 power/other vss r1 power/other vss r23 power/other vss r26 power/other vss r4 power/other vss t21 power/other vss t24 power/other vss t3 power/other table 4-1. pin listing by pin name pin name pin number signal buffer type direction vss t6 power/other vss u2 power/other vss u22 power/other vss u25 power/other vss u5 power/other vss v1 power/other vss v23 power/other vss v26 power/other vss v4 power/other vss w21 power/other vss w24 power/other vss w3 power/other vss w6 power/other vss y2 power/other vss y22 power/other vss y25 power/other vss y5 power/other vssa ad22 power/other vss_sense a4 power/other output table 4-1. pin listing by pin name pin name pin number signal buffer type direction
pin lists and signal descriptions 52 intel ? pentium ? 4 processor on 0.13 micron process datasheet table 4-2. pin listing by pin number pin number pin name signal buffer type direction a2 thermtrip# asynch gtl+ output a3 vss power/other a4 vss_sense power/other output a5 vcc_sense power/other output a6 testhi11 power/other input a7 reserved a8 vcc power/other a9 vss power/other a10 vcc power/other a11 vss power/other a12 vcc power/other a13 vss power/other a14 vcc power/other a15 vss power/other a16 vcc power/other a17 vss power/other a18 vcc power/other a19 vss power/other a20 vcc power/other a21 vss power/other a22 reserved a23 d2# source synch input/output a24 vss power/other a25 d3# source synch input/output a26 vss power/other aa1 vss power/other aa2 testhi1 power/other input aa3 binit# common clock input/output aa4 vss power/other aa5 bpm4# common clock input/output aa6 gtlref power/other input aa7 vss power/other aa8 vcc power/other aa9 vss power/other aa10 vcc power/other aa11 vss power/other aa12 vcc power/other aa13 vss power/other aa14 vcc power/other aa15 vss power/other aa16 vcc power/other aa17 vss power/other aa18 vcc power/other aa19 vss power/other aa20 itpclk[0] power/other output aa21 gtlref power/other input aa22 d62# source synch input/output aa23 vss power/other aa24 d63# source synch input/output aa25 d61# source synch input/output aa26 vss power/other ab1 a35# source synch input/output ab2 rsp# common clock input ab3 vss power/other ab4 bpm5# common clock input/output ab5 bpm1# common clock input/output ab6 vss power/other ab7 vcc power/other ab8 vss power/other ab9 vcc power/other ab10 vss power/other ab11 vcc power/other ab12 vss power/other ab13 vcc power/other ab14 vss power/other ab15 vcc power/other ab16 vss power/other ab17 vcc power/other ab18 vss power/other ab19 vcc power/other ab20 vss power/other ab21 vss power/other ab22 itpclk[1] power/other output ab23 pwrgood power/other input ab24 vss power/other ab25 reset# common clock input ab26 slp# asynch gtl+ input ac1 ap#[0] common clock input/output ac2 vss power/other ac3 ierr# common clock output ac4 bpm2# common clock input/output ac5 vss power/other ac6 bpm0# common clock input/output ac7 vss power/other ac8 vcc power/other ac9 vss power/other ac10 vcc power/other ac11 vss power/other table 4-2. pin listing by pin number pin number pin name signal buffer type direction
pin lists and signal descriptions intel ? pentium ? 4 processor on 0.13 micron process datasheet 53 ac12 vcc power/other ac13 vss power/other ac14 vcc power/other ac15 vss power/other ac16 vcc power/other ac17 vss power/other ac18 vcc power/other ac19 vss power/other ac20 testhi3 power/other input ac21 testhi2 power/other input ac22 vss power/other ac23 testhi5 power/other input ac24 testhi4 power/other input ac25 vss power/other ac26 itp_clk0 tap input ad1 vss power/other ad2 reserved ad3 reserved ad4 vss power/other ad5 bsel1 power/other output ad6 bsel0 power/other output ad7 vcc power/other ad8 vss power/other ad9 vcc power/other ad10 vss power/other ad11 vcc power/other ad12 vss power/other ad13 vcc power/other ad14 vss power/other ad15 vcc power/other ad16 vss power/other ad17 vcc power/other ad18 vss power/other ad19 vcc power/other ad20 vcca power/other ad21 vss power/other ad22 vssa power/other ad23 vss power/other ad24 testhi0 power/other input ad25 testhi12 power/other input ad26 itp_clk1 tap input ae1 vid4 power/other output ae2 vid3 power/other output ae3 vid2 power/other output table 4-2. pin listing by pin number pin number pin name signal buffer type direction ae4 vid1 power/other output ae5 vid0 power/other output ae6 vcc power/other ae7 vss power/other ae8 vcc power/other ae9 vss power/other ae10 vcc power/other ae11 vss power/other ae12 vcc power/other ae13 vss power/other ae14 vcc power/other ae15 vss power/other ae16 vcc power/other ae17 vss power/other ae18 vcc power/other ae19 vss power/other ae20 vcc power/other ae21 reserved ae22 vss power/other ae23 vcciopll power/other ae24 vss power/other ae25 dbr# asynch gtl+ output ae26 impsel power/other input af1 vss power/other af2 vcc power/other af3 reserved af4 vccvid power/other input af5 vcc power/other af6 vss power/other af7 vcc power/other af8 vss power/other af9 vcc power/other af10 vss power/other af11 vcc power/other af12 vss power/other af13 vcc power/other af14 vss power/other af15 vcc power/other af16 vss power/other af17 vcc power/other af18 vss power/other af19 vcc power/other af20 vss power/other af21 vcc power/other table 4-2. pin listing by pin number pin number pin name signal buffer type direction
pin lists and signal descriptions 54 intel ? pentium ? 4 processor on 0.13 micron process datasheet af22 bclk[0] bus clock input af23 bclk[1] bus clock input af24 reserved af25 reserved af26 sktocc# power/other output b2 ignne# asynch gtl+ input b3 thermda power/other b4 vss power/other b5 smi# asynch gtl+ input b6 ferr# asynch agl+ output b7 vcc power/other b8 vss power/other b9 vcc power/other b10 vss power/other b11 vcc power/other b12 vss power/other b13 vcc power/other b14 vss power/other b15 vcc power/other b16 vss power/other b17 vcc power/other b18 vss power/other b19 vcc power/other b20 vss power/other b21 d0# source synch input/output b22 d01# source synch input/output b23 vss power/other b24 d6# source synch input/output b25 d9# source synch input/output b26 vss power/other c1 tdi tap input c2 vss power/other c3 prochot# asynch gtl+ input/output c4 thermdc power/other c5 vss power/other c6 a20m# asynch gtl+ input c7 vss power/other c8 vcc power/other c9 vss power/other c10 vcc power/other c11 vss power/other c12 vcc power/other c13 vss power/other c14 vcc power/other table 4-2. pin listing by pin number pin number pin name signal buffer type direction c15 vss power/other c16 vcc power/other c17 vss power/other c18 vcc power/other c19 vss power/other c20 vcc power/other c21 d4# source synch input/output c22 vss power/other c23 d7# source synch input/output c24 d8# source synch input/output c25 vss power/other c26 d12# source synch input/output d1 lint0 asynch gtl+ input d2 bpri# common clock input d3 vss power/other d4 tck tap input d5 tdo tap output d6 vss power/other d7 vcc power/other d8 vss power/other d9 vcc power/other d10 vss power/other d11 vcc power/other d12 vss power/other d13 vcc power/other d14 vss power/other d15 vcc power/other d16 vss power/other d17 vcc power/other d18 vss power/other d19 vcc power/other d20 vss power/other d21 vss power/other d22 d5# source synch input/output d23 d13# source synch input/output d24 vss power/other d25 d15# source synch input/output d26 d23# source synch input/output e1 vss power/other e2 defer# common clock input e3 hitm# common clock input/output e4 vss power/other e5 lint1 asynch gtl+ input e6 trst# tap input table 4-2. pin listing by pin number pin number pin name signal buffer type direction
pin lists and signal descriptions intel ? pentium ? 4 processor on 0.13 micron process datasheet 55 e7 vss power/other e8 vcc power/other e9 vss power/other e10 vcc power/other e11 vss power/other e12 vcc power/other e13 vss power/other e14 vcc power/other e15 vss power/other e16 vcc power/other e17 vss power/other e18 vcc power/other e19 vss power/other e20 vcc power/other e21 dbi0# source synch input/output e22 dstbn0# source synch input/output e23 vss power/other e24 d17# source synch input/output e25 d21# source synch input/output e26 vss power/other f1 rs0# common clock input f2 vss power/other f3 hit# common clock input/output f4 rs2# common clock input f5 vss power/other f6 gtlref power/other input f7 tms tap input f8 vss power/other f9 vcc power/other f10 vss power/other f11 vcc power/other f12 vss power/other f13 vcc power/other f14 vss power/other f15 vcc power/other f16 vss power/other f17 vcc power/other f18 vss power/other f19 vcc power/other f20 gtlref power/other input f21 dstbp0# source synch input/output f22 vss power/other f23 d19# source synch input/output f24 d20# source synch input/output table 4-2. pin listing by pin number pin number pin name signal buffer type direction f25 vss power/other f26 d22# source synch input/output g1 ads# common clock input/output g2 bnr# common clock input/output g3 vss power/other g4 lock# common clock input/output g5 rs1# common clock input g6 vss power/other g21 vss power/other g22 d10# source synch input/output g23 d18# source synch input/output g24 vss power/other g25 dbi1# source synch input/output g26 d25# source synch input/output h1 vss power/other h2 drdy# common clock input/output h3 req4# source synch input/output h4 vss power/other h5 dbsy# common clock input/output h6 br0# common clock input/output h21 d11# source synch input/output h22 d16# source synch input/output h23 vss power/other h24 d26# source synch input/output h25 d31# source synch input/output h26 vss power/other j1 req0# source synch input/output j2 vss power/other j3 req3# source synch input/output j4 req2# source synch input/output j5 vss power/other j6 trdy# common clock input j21 d14# source synch input/output j22 vss power/other j23 dstbp1# source synch input/output j24 d29# source synch input/output j25 vss power/other j26 dp0# common clock input/output k1 a6# source synch input/output k2 a3# source synch input/output k3 vss power/other k4 a4# source synch input/output k5 req1# source synch input/output k6 vss power/other table 4-2. pin listing by pin number pin number pin name signal buffer type direction
pin lists and signal descriptions 56 intel ? pentium ? 4 processor on 0.13 micron process datasheet k21 vss power/other k22 dstbn1# source synch input/output k23 d30# source synch input/output k24 vss power/other k25 dp1# common clock input/output k26 dp2# common clock input/output l1 vss power/other l2 a9# source synch input/output l3 a7# source synch input/output l4 vss power/other l5 adstb0# source synch input/output l6 a5# source synch input/output l21 d24# source synch input/output l22 d28# source synch input/output l23 vss power/other l24 comp0 power/other input/output l25 dp3# common clock input/output l26 vss power/other m1 a13# source synch input/output m2 vss power/other m3 a10# source synch input/output m4 a11# source synch input/output m5 vss power/other m6 a8# source synch input/output m21 d27# source synch input/output m22 vss power/other m23 d32# source synch input/output m24 d35# source synch input/output m25 vss power/other m26 d37# source synch input/output n1 a12# source synch input/output n2 a14# source synch input/output n3 vss power/other n4 a15# source synch input/output n5 a16# source synch input/output n6 vss power/other n21 vss power/other n22 d33# source synch input/output n23 d36# source synch input/output n24 vss power/other n25 d39# source synch input/output n26 d38# source synch input/output p1 comp1 power/other input/output p2 vss power/other table 4-2. pin listing by pin number pin number pin name signal buffer type direction p3 a19# source synch input/output p4 a20# source synch input/output p5 vss power/other p6 a24# source synch input/output p21 d34# source synch input/output p22 vss power/other p23 dstbp2# source synch input/output p24 d41# source synch input/output p25 vss power/other p26 dbi2# source synch input/output r1 vss power/other r2 a18# source synch input/output r3 a21# source synch input/output r4 vss power/other r5 adstb1# source synch input/output r6 a28# source synch input/output r21 d40# source synch input/output r22 dstbn2# source synch input/output r23 vss power/other r24 d43# source synch input/output r25 d42# source synch input/output r26 vss power/other t1 a17# source synch input/output t2 a22# source synch input/output t3 vss power/other t4 a26# source synch input/output t5 a30# source synch input/output t6 vss power/other t21 vss power/other t22 d46# source synch input/output t23 d47# source synch input/output t24 vss power/other t25 d45# source synch input/output t26 d44# source synch input/output u1 a23# source synch input/output u2 vss power/other u3 a25# source synch input/output u4 a31# source synch input/output u5 vss power/other u6 testhi8 power/other input u21 d52# source synch input/output u22 vss power/other u23 d50# source synch input/output u24 d49# source synch input/output table 4-2. pin listing by pin number pin number pin name signal buffer type direction
pin lists and signal descriptions intel ? pentium ? 4 processor on 0.13 micron process datasheet 57 u25 vss power/other u26 d48# source synch input/output v1 vss power/other v2 a27# source synch input/output v3 a32# source synch input/output v4 vss power/other v5 ap1# common clock input/output v6 mcerr# common clock input/output v21 dbi3# source synch input/output v22 d53# source synch input/output v23 vss power/other v24 d54# source synch input/output v25 d51# source synch input/output v26 vss power/other w1 a29# source synch input/output w2 a33# source synch input/output w3 vss power/other w4 testhi9 power/other input w5 init# asynch gtl+ input table 4-2. pin listing by pin number pin number pin name signal buffer type direction w6 vss power/other w21 vss power/other w22 dstbn3# source synch input/output w23 dstbp3# source synch input/output w24 vss power/other w25 d57# source synch input/output w26 d55# source synch input/output y1 a34# source synch input/output y2 vss power/other y3 testhi10 power/other input y4 stpclk# asynch gtl+ input y5 vss power/other y6 bpm3# common clock input/output y21 d60# source synch input/output y22 vss power/other y23 d58# source synch input/output y24 d59# source synch input/output y25 vss power/other y26 d56# source synch input/output table 4-2. pin listing by pin number pin number pin name signal buffer type direction
58 intel ? pentium ? 4 processor on 0.13 micron process datasheet pin lists and signal descriptions 4.2 signal descriptions table 4-3. signal descriptions (sheet 1 of 8) name type description a[35:3]# input/ output a[35:3]# (address) define a 2 36 -byte physical memory address space. in sub-phase 1 of the address phase, these pins transmit the address of a transaction. in sub-phase 2, these pins transmit transaction type information. these signals must connect the appropriate pins of all agents on the intel ? pentium ? 4 processor on 0.13 micron process system bus. a[35:3]# are protected by parity signals ap[1:0]#. a[35:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processor samples a subset of the a[35:3]# pins to determine power-on configuration. see section 6.1 for more details. a20m# input if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[35:3]# and req[4:0]# on their rising and falling edges. strobes are associated with signals as shown below. ap[1:0]# input/ output ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[35:3]#, and the transaction type on the req[4:0]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate pins of all pentium 4 processors on 0.13 micron process system bus agents. the following table defines the coverage model of these signals. bclk[1:0] input the differential pair bclk (bus clock) determines the system bus frequency. all processor system bus agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of bclk0 crossing v cross . signals associated strobe req[4:0]#, a[16:3]# adstb0# a[35:17]# adstb1# request signals subphase 1 subphase 2 a[35:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0#
intel ? pentium ? 4 processor on 0.13 micron process datasheet 59 pin lists and signal descriptions binit# input/ output binit# (bus initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. if the binit# driver is enabled during power-on configuration, binit# is asserted to signal any bus condition that prevents reliable future operation. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, symmetric agents reset their bus lock# activity and bus request arbitration state machines. the bus agents do not reset their ioq and transaction tracking state machines upon observation of binit# activation. once the binit# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and ioq entries. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. bnr# input/ output bnr# (block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. bpm[5:0]# input/ output bpm[5:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[5:0]# should connect the appropriate pins of all pentium 4 processors on 0.13 micron process system bus agents. bpm4# provides prdy# (probe ready) functionality for the tap port. prdy# is a processor output used by debug tools to determine processor debug readiness. bpm5# provides preq# (probe request) functionality for the tap port. preq# is used by debug tools to request debug operation of the processor. refer to the appropriate platform design guide for more detailed information. these signals do not have on-die termination and must be terminated on the system board. bpri# input bpri# (bus priority request) is used to arbitrate for ownership of the processor system bus. it must connect the appropriate pins of all processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. br0# input/ output br0# drives the breq0# signal in the system and is used by the processor to request the bus. during power-on configuration this pin is sampled to determine the agent id = 0. this signal does not have on-die termination and must be terminated. bsel[1:0] input/ output bsel[1:0] (bus select) are used to select the processor input clock frequency. table 2-4 defines the possible combinations of the signals and the frequency associated with each combination. the required frequency is determined by the processor, chipset and clock synthesizer. all agents must operate at the same frequency. for more information about these pins, including termination recommendations refer to section 2.9 and the appropriate platform design guidelines. comp[1:0] analog comp[1:0] must be terminated on the system board using precision resistors. refer to the appropriate platform design guide for details on implementation. table 4-3. signal descriptions (sheet 2 of 8) name type description
60 intel ? pentium ? 4 processor on 0.13 micron process datasheet pin lists and signal descriptions d[63:0]# input/ output d[63:0]# (data) are the data signals. these signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dbi#. furthermore, the dbi# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is active, the corresponding data group is inverted and therefore sampled active high. dbi[3:0]# input/ output dbi[3:0]# (data bus inversion) are source synchronous and indicate the polarity of the d[63:0]# signals. the dbi[3:0]# signals are activated when the data on the data bus is inverted. if more than half the data bits within a 16-bit group would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. dbr# output dbr# (data bus reset) is used only in processor systems where no debug port is implemented on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemented in the system, dbr# is a no connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor system bus agents. defer# input defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins of all processor system bus agents. dp[3:0]# input/ output dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all pentium 4 processor on 0.13 micron process system bus agents. table 4-3. signal descriptions (sheet 3 of 8) name type description quad-pumped signal groups data group dstbn#/ dstbp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0]# assignment to data bus bus signal data bus signals dbi3# d[63:48]# dbi2# d[47:32]# dbi1# d[31:16]# dbi0# d[15:0]#
intel ? pentium ? 4 processor on 0.13 micron process datasheet 61 pin lists and signal descriptions drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all processor system bus agents. dstbn[3:0]# input/ output data strobe used to latch in d[63:0]#: dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#: ferr#/pbe# output ferr#/pbe# (floating point error/pending break event) is a multiplexed signal which is qualified by stpclk#. when stpclk# is not asserted, ferr# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. when stpclk# is not asserted, ferr#/pbe# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using microsoft ms-dos*-type floating-point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. when ferr#/pbe# is asserted, indicating a break event, it will remain asserted until stpclk# is deasserted. for addition information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to the ia-32 intel ? architecture software developer?s manual (vol. 1 - vol. 3) and the intel ? processor identification and the cpuid instruction application note. gtlref input gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v cc . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical 1. refer to the appropriate platform design guide for more information. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. any system bus agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the processor system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#. this signal does not have on-die termination and must be terminated on the system board. table 4-3. signal descriptions (sheet 4 of 8) name type description signals associated strobe d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobe d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
62 intel ? pentium ? 4 processor on 0.13 micron process datasheet pin lists and signal descriptions ignne# input ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. impsel input impsel input will determine whether the processor uses a 50 ? or 60 ? buffer. this pin must be tied to gnd on 50 ? platforms and left as nc on 60 ? platforms. init# input init# (initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itpclkout[1:0] output itpclkout[1:0] is an uncompensated differential clock output that is a delayed copy of bclk[1:0], which is an input to the processor. this clock output can be used as the differential clock into the itp port that is designed onto the motherboard. if itpclkout[1:0] outputs are not used, they must be terminated properly. refer to section 2.5 for additional details and termination requirements. refer to the itp 700 debug port design guide for details on implementing a debug port. itp_clk[1:0] input itp_clk[1:0] are copies of bclk that are used only in processor systems where no debug port is implemented on the system board. itp_clk[1:0] are used as bclk[1:0] references for a debug port implemented on an interposer. if a debug port is implemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. lint[1:0] input lint[1:0] (local apic interrupt) must connect the appropriate pins of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. table 4-3. signal descriptions (sheet 5 of 8) name type description
intel ? pentium ? 4 processor on 0.13 micron process datasheet 63 pin lists and signal descriptions mcerr# input/ output mcerr# (machine check error) is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor system bus agents. mcerr# assertion conditions are configurable at a system level. assertion options are defined by the following options: ? enabled or disabled. ? asserted, if configured, for internal errors along with ierr#. ? asserted, if configured, by the request initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, refer to the ia-32 intel ? software developer?s manual, volume 3: system programming guide . prochot# input/ output as an output, prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit has been activated, if enabled. as an input, assertion of prochot# by the system will activate the tcc, if enabled. the tcc will remain active until the system deasserts prochot#. see section 6.3 for more details. note: the prochot# signal functionality has changed from output to input/output on cpuid 0xf27 and beyond. pwrgood input pwrgood (power good) is a processor input. the processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must connect the appropriate pins of all processor system bus agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb0#. refer to the ap[1:0]# signal description for details on parity checking of these signals. reset# input asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least one millisecond after v cc and bclk have reached their proper specifications. on observing active reset#, all system bus agents will deassert their outputs within two clocks. reset# must not be kept asserted for more than 10 ms while pwrgood is asserted. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the section 6.1 . this signal does not have on-die termination and must be terminated on the system board. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. table 4-3. signal descriptions (sheet 6 of 8) name type description
64 intel ? pentium ? 4 processor on 0.13 micron process datasheet pin lists and signal descriptions rsp# input rsp# (response parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect to the appropriate pins of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. sktocc# output sktocc# (socket occupied) will be pulled to ground by the processor. system board designers may use this pin to determine if the processor is present. slp# input slp# (sleep), when asserted in stop-grant state, causes the processor to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will only recognize the assertion of the reset# signal, deassertion of slp#, and removal of the bclk input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. smi# input smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enters system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during the deassertion of reset# the processor will tristate its outputs. stpclk# input assertion of stpclk# (stop clock) causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck input tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi[12:8] testhi[5:0] input testhi[12:8] and testhi[5:0] must be connected to a v cc power source through a resistor for proper processor operation. see section 2.5 for more details. thermda other thermal diode anode. see section 6.3.1 . thermdc other thermal diode cathode. see section 6.3.1 . table 4-3. signal descriptions (sheet 7 of 8) name type description
intel ? pentium ? 4 processor on 0.13 micron process datasheet 65 pin lists and signal descriptions thermtrip# output assertion of thermtrip# (thermal trip) indicates the processor junction temperature has reached a level where permanent silicon damage may occur. measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135 c. upon assertion of thermtrip#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. to protect the processor, its core voltage (v cc ) must be removed within 0.5 seconds of the assertion of thermtrip#. for processors with cpuid of 0xf24: ? once activated, thermtrip# remains latched until reset# is asserted. while the assertion of the reset# signal will de-assert thermtrip#, if the processor?s junction temperature remains at or above the trip level, thermtrip# will again be asserted. for processors with cpuid of 0xf27 and beyond: ? driving of the thermtrip# signal is enabled within 10 s of the assertion of pwrgood and is disabled on de-assertion of pwrgood. once activated, thermtrip# remains latched until pwrgood is de-asserted. while the de-assertion of the pwrgood signal will de-assert thermtrip#, if the processor?s junction temperature remains at or above the trip level, thermtrip# will again be asserted within 10 s of the assertion of pwrgood. tms input tms (test mode select) is a jtag specification support signal used by debug tools. trdy# input trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all system bus agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. this can be done with a 680 ? pull-down resistor. v cca input v cca provides isolated power for the internal processor core plls. refer to the appropriate platform design guide for complete implementation details. v cciopll input v cciopll provides isolated power for internal processor system bus plls. follow the guidelines for v cca , and refer to the appropriate platform design guide for complete implementation details. v cc_sense output v cc_sense is an isolated low impedance connection to processor core power (v cc ). it can be used to sense or measure power near the silicon with little noise. v cc vid input independent 1.2 v supply must be routed to v cc vid pin for the pentium 4 processor on 0.13 micron process?s voltage identification circuit. vid[4:0] output vid[4:0] (voltage id) pins are used to support automatic selection of power supply voltages (v cc ). unlike previous generations of processors, these are open drain signals that are driven by the pentium 4 processor on 0.13 micron process and must be pulled up to 3.3 v (max.) with 1 k ? resistors. the voltage supply for these pins must be valid before the vr can supply v cc to the processor. conversely, the vr output must be disabled until the voltage supply for the vid pins becomes valid. the vid pins are needed to support the processor voltage specification variations. see table 2-2 for definitions of these pins. the vr must supply the voltage that is requested by the pins, or disable itself. v ssa input v ssa is the isolated ground for internal plls. v ss_sense output v ss_sense is an isolated low impedance connection to processor core v ss . it can be used to sense or measure ground near the silicon with little noise table 4-3. signal descriptions (sheet 8 of 8) name type description
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intel ? pentium ? 4 processor on 0.13 micron process datasheet 67 thermal specifications and design considerations thermal specifications and design considerations 5 the pentium 4 processor on 0.13 micron process uses an integrated heat spreader (ihs) for heatsink attachment that is intended to provide for multiple types of thermal solutions. this chapter provides data necessary for development of a thermal solution. see figure 5-1 for an enlarged view of an example of the pentium 4 processor on 0.13 micron process thermal solution. this is for illustration purposes only. for further thermal solution design details, refer to the. intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines . note: the processor is shipped either by itself or with a heatsink for boxed processors. see chapter 7 for details on boxed processors. figure 5-1. example thermal solution (not to scale) clip assembly fan/shroud heatsink retention mechanism processor mpga478b 478-pin socket
68 intel ? pentium ? 4 processor on 0.13 micron process datasheet thermal specifications and design considerations 5.1 processor thermal specifications the pentium 4 processor on 0.13 micron process requires a thermal solution to maintain temperatures within the operating limits as set forth in section 5.1.1 . any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. as processor technology changes, thermal management becomes increasingly crucial when building computer systems. maintaining the proper thermal environment is key to reliable, long-term system operation. a complete thermal solution includes both component and system level thermal management features. component-level thermal solutions can include active or passive heatsinks attached to the processor ihs. typical system level thermal solutions may consist of system fans combined with ducting and venting. for more information on designing a component level thermal solution, refer to intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines . 5.1.1 thermal specifications to allow for the optimal operation and long-term reliability of intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (t c ) specifications when operating at or below the thermal design power (tdp) value listed per frequency in table 5-1 . thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. for more details on thermal solution design, refer to the appropriate processor thermal design guidelines. the case temperature is defined at the geometric top center of the processor ihs. analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. intel recommends that complete thermal solution designs target the thermal design power (tdp) indicated in table 5-1 instead of the maximum processor power consumption. the thermal monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the tdp recommendation for a sustained period of time. for more details on the usage of this feature, refer to section 6.3 . to ensure maximum flexibility for future requirements, systems should be designed to the flexible motherboard (fmb) guidelines, even if a processor with a lower thermal dissipation is currently planned. in all cases, the thermal monitor feature must be enabled for the processor to remain within specification .
intel ? pentium ? 4 processor on 0.13 micron process datasheet 69 thermal specifications and design considerations table 5-1. processor thermal design power front side bus frequency processor and core frequency thermal design power 1,2 (w) minimum t c (c) maximum t c (c) notes 3 400 mhz processors with vid=1.500 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 52.4 55.1 57.8 59.3 5 5 5 5 68 69 70 71 processors with vid=1.525 v 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 54.3 57.1 59.8 61.0 62.6 5 5 5 5 5 69 70 71 72 72 processors with multiple vids 2a ghz 2.20 ghz 2.40 ghz 2.50 ghz 2.60 ghz 54.3 57.1 59.8 61.0 62.6 5 5 5 5 5 69 70 71 72 72 533 mhz processors with vid=1.500 v 2.26 ghz 2.40b ghz 2.53 ghz 56.0 57.8 59.3 5 5 5 70 70 71 processors with vid=1.525 v 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 58.0 59.8 61.5 66.1 68.4 5 5 5 5 5 70 71 72 74 75 processors with multiple vids 2.26 ghz 2.40b ghz 2.53 ghz 2.66 ghz 2.80 ghz 3.06 ghz 58.0 59.8 61.5 66.1 68.4 81.8 5 5 5 5 5 5 70 71 72 74 75 69 800 mhz fsb with 512-kb l2 cache only processors with multiple vids 2.40c ghz 2.60c ghz 2.80c ghz 3 ghz 3.20c ghz 3.40 ghz 66.2 69.0 69.7 81.9 82.0 89.0 5 5 5 5 5 5 74 75 75 70 70 68 800 mhz fsb with 2-mb l3 cache processors with multiple vids 3.20 ghz 3.40 ghz 92.1 102.9 5 5 64 67
70 intel ? pentium ? 4 processor on 0.13 micron process datasheet thermal specifications and design considerations notes: 1. these values are specified at v cc_max for the processor. systems must be designed to ensure that the processor is not subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified i cc . refer to loadline specifications in chapter 2 . 2. the numbers in this column reflect intel?s recommended design point and are not indicative of the maximum power the processor can dissipate under worst case conditions. for more details, refer to the intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines . 3. tdp and t c are specified for highest vid only. processors will be shipped under multiple vids for each frequency; however, the tdp and t c specifications will be the same as highest vid specified in the table. 5.1.2 thermal metrology 5.1.2.1 processor case temperature measurement the maximum and minimum case temperature (t c ) for the pentium 4 processor on 0.13 micron process is specified in table 5-1 . this temperature specification is meant to help ensure proper operation of the processor. figure 5-2 illustrates where intel recommends t c thermal measurements should be made. for detailed guidelines on temperature measurement methodology, refer to the intel ? pentium ? processor 4 with 512-kb l2 cache on 0.13 micron process thermal design guidelines . figure 5-2. guideline locations for case temperature (t c ) thermocouple placement measure tcase at this point thermal interface material should cover the entire surface of the inte g rated heat s p reade r 0.689? 17.5 mm 0.689? 17.5 mm 35 mm package
intel ? pentium ? 4 processor on 0.13 micron process datasheet 71 features features 6 6.1 power-on configuration options several configuration options can be configured by hardware. the pentium 4 processor on 0.13 micron process samples hardware configuration at reset, on the active-to-inactive transition of reset#. for specifications on these options, refer to table 6-1 . the sampled information configures the processor for subsequent operation. these configuration options cannot be changed except by another reset. all resets reconfigure the processor; for reset purposes, the processor does not distinguish between a ?warm? reset and a ?power-on? reset. note: 1. asserting this signal during reset# will select the corresponding option. 6.2 clock control and low power states the use of autohalt, stop-grant, and sleep states is allowed in pentium 4 processor on 0.13 micron process-based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 6-1 for a visual representation of the processor low power states. 6.2.1 normal state?state 1 this is the normal operating state for the processor. table 6-1. power-on configuration option pins configuration option pin 1 output tristate smi# execute bist init# in order queue pipelining (set ioq depth to 1) a7# disable mcerr# observation a9# disable binit# observation a10# apic cluster id (0-3) a[12:11]# disable bus parking a15# disable hyper-threading technology a31# symmetric agent arbitration id br0#
72 intel ? pentium ? 4 processor on 0.13 micron process datasheet features 6.2.2 autohalt powerdown state?state 2 autohalt is a low power state entered when the processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#, binit#, init#, or lint[1:0] (nmi, intr). reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the autohalt power down state. see the intel ? architecture software developer's manual, volume iii: system programmer's guide for more information. the system can generate a stpclk# while the processor is in the autohalt power down state. when the system deasserts the stpclk# interrupt, the processor will return execution to the halt state. while in autohalt power down state, the processor will process bus snoops and interrupts. figure 6-1. stop clock state machine 2. auto halt power down state bclk running. snoops and interrupts allowed. 4. halt/grant snoop state bclk running. service snoops to caches. snoop event occurs snoop event serviced halt instruction and halt bus cycle generated init#, binit#, intr, nmi, smi#, reset# snoop event occurs snoop event serviced 1. normal state normal execution. 3. stop grant state bclk running. snoops and interrupts allowed. stpclk# asserted stpclk# de-asserted 5. sleep state bclk running. no snoops and interrupts allowed. slp# asserted slp# de-asserted stpclk# asserted stpclk# de-asserted
intel ? pentium ? 4 processor on 0.13 micron process datasheet 73 features 6.2.3 stop-grant state?state 3 when the stpclk# pin is asserted, the stop-grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued stop-grant acknowledge special bus cycle. since the agtl+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to v cc ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the system bus should be driven to the inactive state. binit# will not be serviced while the processor is in stop-grant state. the event will be latched and can be serviced by software upon exit from the stop-grant state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the de-assertion of the stpclk# signal. when re-entering the stop-grant state from the sleep state, stpclk# should only be de-asserted one or more bus clocks after the de-assertion of slp#. a transition to the halt/grant snoop state will occur when the processor detects a snoop on the system bus (see section 6.2.4 ). a transition to the sleep state (see section 6.2.5 ) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init#, binit# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. while in stop-grant state, the processor will process snoops on the system bus and it will latch interrupts delivered on the system bus. the pbe# signal can be driven when the processor is in stop-grant state. pbe# will be asserted if there is any pending interrupt latched within the processor. pending interrupts that are blocked by the eflags.if bit being clear will still cause assertion of pbe#. assertion of pbe# indicates to system logic that it should return the processor to the normal state. 6.2.4 halt/grant snoop state?state 4 the processor will respond to snoop or interrupt transactions on the system bus while in stop-grant state or in autohalt power down state. during a snoop or interrupt transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or other agent on the system bus) or the interrupt has been latched. after the snoop is serviced or the interrupt is latched, the processor will return to the stop-grant state or autohalt power down state, as appropriate.
74 intel ? pentium ? 4 processor on 0.13 micron process datasheet features 6.2.5 sleep state?state 5 the sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sleep state can be entered only from stop-grant state. once in the stop-grant state, the processor will enter the sleep state upon the assertion of the slp# signal. the slp# pin should be asserted only when the processor is in the stop-grant state. slp# assertions while the processor is not in the stop-grant state is out of specification, and may result in unapproved operation. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp# or reset#) are allowed on the system bus while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state and is held active as specified in the reset# pin specification, the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure that the processor correctly executes the reset sequence. once in the sleep state, the slp# pin must be de-asserted if another asynchronous system bus event needs to occur. the slp# pin has a minimum assertion of one bclk period. when the processor is in sleep state, it will not respond to interrupts or snoop transactions. 6.3 thermal monitor the thermal monitor feature helps control the processor temperature by activating the thermal control circuit (tcc) when the processor silicon reaches its maximum operating temperature. the tcc reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. the thermal monitor feature must be enabled for the processor to be operating within specifications. the temperature at which thermal monitor activates the thermal control circuit is not user configurable and is not software visible. bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. when the thermal monitor feature is enabled, and a high temperature situation exists (i.e., tcc is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30?50%). clocks often will not be off for more than 3.0 s when the tcc is active. cycle times are processor speed dependent and will decrease as processor core frequencies increase. a small amount of hysteresis has been included to prevent rapid active/ inactive transitions of the tcc when the processor temperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the tcc goes inactive and clock modulation ceases. with a properly designed and characterized thermal solution, it is anticipated that the tcc would only be activated for very short periods of time when running the most power intensive applications. the processor performance impact due to these brief periods of tcc activation is expected to be so minor that it would be immeasurable. an under-designed thermal solution that is not able to prevent excessive activation of the tcc in the anticipated ambient environment may
intel ? pentium ? 4 processor on 0.13 micron process datasheet 75 features cause a noticeable performance loss, and in some cases may result in a t c that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. in addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the tcc is active continuously. refer to the intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines for information on designing a thermal solution. the duty cycle for the tcc, when activated by the thermal monitor, is factory configured and cannot be modified. the thermal monitor does not require any additional hardware, software drivers, or interrupt handling routines. the tcc may also be activated via on-demand mode. if bit 4 of the acpi thermal monitor control register is written to a 1, the tcc will be activated immediately independent of the processor temperature. when using on-demand mode to activate the tcc, the duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi thermal monitor control register. in automatic mode, the duty cycle is fixed. however, in on-demand mode, the duty cycle can be programmed from 12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used at the same time automatic mode is enabled. however, if the system tries to enable the tcc via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, the duty cycle of the automatic mode will override the duty cycle selected by the on-demand mode. an external signal, prochot# (processor hot), is asserted when the processor detects that its temperature is at the thermal trip point. bus snooping and interrupt latching are also active while the tcc is active. the temperature at which the thermal control circuit activates is not user configurable and is not software visible. besides the thermal sensor and tcc, the thermal monitor feature also includes one acpi register, performance monitoring logic, bits in three model specific registers (msr), and one i/o pin (prochot#). all are available to monitor and control the state of the thermal monitor feature. thermal monitor can be configured to generate an interrupt upon the assertion or de-assertion of prochot#. if automatic mode is disabled, the processor will be operating out of specification. regardless of enabling of the automatic or on-demand modes, in the event of a catastrophic cooling failure the processor automatically shuts down when the silicon has reached a temperature of approximately 135 c. at this point the system bus signal thermtrip# goes active and stays active until reset# has been initiated. thermtrip# activation is independent of processor activity and does not generate any bus cycles. if thermtrip# is asserted, processor core voltage (v cc ) must be removed within 0.5 seconds.
76 intel ? pentium ? 4 processor on 0.13 micron process datasheet features 6.3.1 thermal diode the pentium 4 processor on 0.13 micron process incorporates an on-die thermal diode. a thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. table 6-2 and table 6-3 provide the diode parameter and interface specifications. this thermal diode is separate from the thermal monitor?s thermal sensor and cannot be used to predict the behavior of the thermal monitor. notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. characterized at 75 c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: i fw =i s *(e (qv d /nkt) -1) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). 5. the series resistance, r t , is provided to allow for a more accurate measurement of the diode junction temperature. r t as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. r t can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: t error = [r t *(n-1)*i fwmin ]/[(nk/q)*ln n] where t error = sensor temperature error, n = sensor current ration, k = boltzmann constant, q = electronic charge. table 6-2. thermal diode parameters symbol parameter min typ max unit notes 1 i fw forward bias current 5 300 a1 n diode ideality factor 1.0011 1.0021 1.0030 2,3,4 r t series resistance 3.64 ? 2,3,4,5 table 6-3. thermal diode interface pin name pin number pin description thermda b3 diode anode thermdc c4 diode cathode
intel ? pentium ? 4 processor on 0.13 micron process datasheet 77 boxed processor specifications boxed processor specifications 7 7.1 introduction the pentium 4 processor on 0.13 micron process will also be offered as an intel boxed processor. intel boxed processors are intended for system integrators who build systems from motherboards and standard components. the boxed pentium 4 processor on 0.13 micron process will be supplied with a cooling solution. this chapter documents motherboard and system requirements for the cooling solution that will be supplied with the boxed pentium 4 processor on 0.13 micron process this chapter is particularly important for oems that manufacture motherboards for system integrators. unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. figure 7-1 shows a mechanical representation of a boxed pentium 4 processor on 0.13 micron process. note: drawings in this section reflect only the specifications on the intel boxed processor product. these dimensions should not be used as a generic keep-out zone for all cooling solutions. it is the system designer's responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platform and chassis. refer to the intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines for further guidance. note: the airflow is into the center and out of the sides of the fan heatsink. figure 7-1. mechanical representation of the boxed processor
78 intel ? pentium ? 4 processor on 0.13 micron process datasheet boxed processor specifications 7.2 mechanical specifications 7.2.1 boxed processor cooling solution dimensions this section describes the mechanical specifications of the boxed pentium 4 processor on 0.13 micron process. the boxed processor will be shipped with an unattached fan heatsink. figure 7-1 shows a mechanical representation of the boxed pentium 4 processor on 0.13 micron process. clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. the physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in figure 7-2 (side views), and figure 7-3 (top view). the airspace requirements for the boxed processor fan heatsink must also be incorporated into new motherboard and system designs. airspace requirements are shown in figure 7-6 and figure 7-7 . note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning. figure 7-2. side view space requirements for the boxed processor
intel ? pentium ? 4 processor on 0.13 micron process datasheet 79 boxed processor specifications 7.2.2 boxed processor fan heatsink weight the boxed processor fan heatsink will not weigh more than 450 grams. see chapter 5 and the intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines for details on the processor weight and heatsink requirements. 7.2.3 boxed processor retention mechanism and heatsink assembly the boxed processor thermal solution requires a processor retention mechanism and a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket. the boxed processor will not ship with retention mechanisms but will ship with the heatsink attach clip assembly. motherboards designed for use by system integrators should include the retention mechanism that supports the boxed pentium 4 processor on 0.13 micron process. motherboard documentation should include appropriate retention mechanism installation instructions. note: the processor retention mechanism based on the intel reference design should be used to ensure compatibility with the heatsink attach clip assembly and the boxed processor thermal solution. the heatsink attach clip assembly is latched to the retention tab features at each corner of the retention mechanism. figure 7-3. top view space requirements for the boxed processor
80 intel ? pentium ? 4 processor on 0.13 micron process datasheet boxed processor specifications the target load applied by the clips to the processor heat spreader for intel?s reference design is 75 15 lbf (maximum load is constrained by the package load capability). it is normal to observe a bow or bend in the board due to this compressive load on the processor package and the socket. the level of bow or bend depends on the motherboard material properties and component layout. any additional board stiffening devices such as plates are not necessary and should not be used along with the reference mechanical components and boxed processor. using such devices increase the compressive load on the processor package and socket, likely beyond the maximum load that is specified for those components. refer to the intel ? pentium ? 4 processor with 512-kb l2 cache on 0.13 micron process thermal design guidelines for details on the intel reference design. 7.3 electrical requirements 7.3.1 fan heatsink power supply the boxed processor's fan heatsink requires a +12 v power supply. a fan power cable will be shipped with the boxed processor to draw power from a power header on the motherboard. the power cable connector and pinout are shown in figure 7-4 . motherboards must provide a matched power header to support the boxed processor. table 7-1 contains specifications for the input and output signals at the fan heatsink connector. the fan heatsink outputs a sense signal, which is an open-collector output that pulses at a rate of two pulses per fan revolution. a motherboard pull-up resistor provides v oh to match the system board-mounted fan speed monitor requirements, if applicable. use of the sense signal is optional. if the sense signal is not used, pin 3 of the connector should be tied to gnd. note: the motherboard must supply a constant +12 v to the processor?s power header to ensure proper operation of the variable speed fan for the boxed processor. the power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. the power header identification and location should be documented in the platform documentation, or on the system board itself. figure 7-5 shows the location of the fan power connector relative to the processor socket. the motherboard power header should be positioned within 4.33 inches from the center of the processor socket. figure 7-4. boxed processor fan heatsink power cable connector description pin signal straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. waldom*/molex* p/n 22-01-3037 or equivalent. match with straight pin, friction lock header on motherboard waldom/molex p/n 22-23-2031, amp* p/n 640456-3, or equivalent. 1 2 3 gnd +12v sense 123
intel ? pentium ? 4 processor on 0.13 micron process datasheet 81 boxed processor specifications note: 1. motherboard should pull this pin up to v cc with a resistor. table 7-1. fan heatsink power and signal specifications description min typ max unit notes +12 v: 12 volt fan power supply 10.2 12 13.8 v ic: fan current draw 740 ma sense: sense frequency 2 pulses per fan revolution 1 figure 7-5. motherboard power header placement relative to processor socket
82 intel ? pentium ? 4 processor on 0.13 micron process datasheet boxed processor specifications 7.4 thermal specifications this section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.4.1 boxed processor cooling requirements the boxed processor may be directly cooled with a fan heatsink. however, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and is ultimately the responsibility of the system integrator. the processor temperature specification is found in chapter 5 . the boxed processor fan heatsink is able to keep the processor temperature within the specifications (see table 5-1 ) in chassis that provide good thermal management. for the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink be unimpeded. airflow is into the center and out of the sides of the fan heatsink. airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. figure 7-6 and figure 7-7 illustrate an acceptable airspace clearance for the fan heatsink. the air temperature entering the fan should be kept below 40 c. again, meeting the processor's temperature specification is the responsibility of the system integrator. figure 7-6. boxed processor fan heatsink airspace keep-out requirements (side 1 view)
intel ? pentium ? 4 processor on 0.13 micron process datasheet 83 boxed processor specifications 7.4.2 variable speed fan the boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. this allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. if internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. at that point, the fan speed is at its maximum. as fan speed increases, so does fan noise levels. systems should be designed to provide adequate air around the boxed processor fan heatsink that remains below the lower set point. these set points, represented in figure 7-8 and table 7-2 , can vary by a few degrees from fan heatsink to fan heatsink. the internal chassis temperature should be kept below 38 oc. meeting the processor?s temperature specification (see chapter 5 ) is the responsibility of the system integrator. figure 7-7. boxed processor fan heatsink airspace keep-out requirements (side 2 view) figure 7-8. boxed processor fan heatsink set points lower set point lowest noise level internal chassis temperature (degrees c) x yz increasing fan speed & noise higher set point highest noise level
84 intel ? pentium ? 4 processor on 0.13 micron process datasheet boxed processor specifications note: 1. set point variance is approximately 1 c from fan heatsink to fan heatsink. table 7-2. boxed processor fan heatsink set points boxed processor fan heatsink set point (oc) boxed processor fan speed notes boxed intel ? pentium ? 4 processors 2.80 ghz (and below) x 33 when the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. recommended maximum internal chassis temperature for nominal operating environment. 1 y = 40 when the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. recommended maximum internal chassis temperature for worst-case operating environment. z 43 when the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. 1 boxed intel ? pentium ? 4 processors 3 ghz (and above) x 32 when the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. recommended maximum internal chassis temperature for nominal operating environment. 1 y = 38 when the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. recommended maximum internal chassis temperature for worst-case operating environment. z 40 when the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. 1
intel ? pentium ? 4 processor on 0.13 micron process datasheet 85 debug tools specifications debug tools specifications 8 refer to the itp 700 debug port design guide and the appropriate platform design guidelines for more detailed information regarding debug tools specifications (such as integration details). 8.1 logic analyzer interface (lai) intel is working with two logic analyzer vendors to provide logic analyzer interfaces (lais) for use in debugging pentium 4 processors on 0.13 micron process systems. tektronix and agilent should be contacted to get specific information about their logic analyzer interfaces. the following information is general in nature. specific information must be obtained from the logic analyzer vendor. due to the complexity of the pentium 4 processor on 0.13 micron process systems, the lai is critical in providing the ability to probe and capture system bus signals. there are two sets of considerations to keep in mind when designing a pentium 4 processor on 0.13 micron process system that can make use of an lai: mechanical and electrical. 8.1.1 mechanical considerations the lai is installed between the processor socket and the processor. the lai pins plug into the socket, while the processor pins plug into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the processor and a logic analyzer. the maximum volume occupied by the lai, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstructed inside the system. note that it is possible that the keepout volume reserved for the lai may differ from the space normally occupied by the pentium 4 processor on 0.13 micron process heatsink. if this is the case, the logic analyzer vendor will provide a cooling solution as part of the lai. 8.1.2 electrical considerations the lai will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system. contact the logic analyzer vendor for electrical specifications and load models for the lai solution they provide.
intel(r) pentium(r) 4 processors - product order codes us home | intel worldwide where to buy | training & events | contact us | about intel site identifier search support navigation header pentium? 4 processors home software & drivers technical specs troubleshooting warranty information email support navigation header intel? processor frequency id utility product overview datasheets manuals performance indicators specification update processors intel? pentium? 4 processors product order codes pentium? 4 processors in the 478-pin package speed/features front side bus speed boxed processor oem/tray processor process 3.20 ghz 800 mhz bx80532pg3200d rk80532pg088512 0.13 micron 3.06 ghz 533 mhz bx80532pe3066d rk80532pe083512 0.13 micron 3 ghz 800 mhz bx80532pg3000d rk8032pg080512 0.13 micron 2.80c ghz 800 mhz bx80532pg2800d rk80532pg072512 0.13 micron 2.80 ghz 533 mhz bx80532pe2800d rk80532pe072512 0.13 micron 2.66 ghz 533 mhz bx80532pe2667d rk80532pe067512 0.13 micron 2.60c ghz 800 mhz bx80532pg2600d rk80532pg064512 0.13 micron 2.60 ghz 400 mhz bx80532pc2600d rk80532pc064512 0.13 micron 2.53 ghz 533 mhz bx80532pe2533d rk80532pe061512 0.13 micron 2.50 ghz 400 mhz bx80532pc2500d rk80532pc060512 0.13 micron 2.40c ghz 800 mhz bx80532pg2400d rk80532pg056512 0.13 micron 2.40b ghz 533 mhz bx80532pe2400d rk80532pe056512 0.13 micron 2.40 ghz 400 mhz bx80532pc2400d rk80532pc056512 0.13 micron 2.26 ghz 533 mhz bx80532pe2266d rk80532pe051512 0.13 micron 2.20 ghz 400 mhz bx80532pc2200d rk80532pc049512 0.13 micron 2a ghz 400 mhz bx80532pc2000d rk80532pc041512 0.13 micron 2 ghz 400 mhz bx80531nk200g RK80531PC041G0K 0.18 micron 1.90 ghz 400 mhz bx80531nk190g rk80531pc037g0k 0.18 micron 1.80a ghz 400 mhz bx80532pc1800d rk80532pc033512 0.13 micron file://///bnsndv31/data/prod/prod-image/vip_pro...%20processors%20-%20product%20order%20codes.htm (1 of 3) [2/22/2005 1:47:32 pm]
intel(r) pentium(r) 4 processors - product order codes 1.80 ghz 400 mhz bx80531nk180g rk80531pc033g0k 0.18 micron 1.70 ghz 400 mhz bx80531nk170g rk80531pc029g0k 0.18 micron 1.60a ghz 400 mhz bx80532pc1600d rk80532pc025512 0.13 micron 1.60 ghz 400 mhz bx80531nk160g rk80531pc025g0k 0.18 micron 1.50 ghz 400 mhz bx80531nk150g rk80531pc021g0k 0.18 micron on july 20, 2001, intel announced that it discontinued the bundling of rdram memory in boxed pentium? 4 processors (see the product change notice). memory included product code two 64-mb pc800 rdram* memory modules for a total of 128-mb of system memory ends in r ex. bx80528jk170gr *two 128-mb pc800 rdram* memory modules for a total of 256-mb of system memory ends in r2 ex. bx80528jk170gr2 **no memory modules included. processor only. ends in g ex. bx80528jk170g * only available for boxed pentium 4 processors 1.4, 1.5, and 1.7 ghz. ** only available for boxed pentium 4 processors 1.4 ghz and above. pentium 4 processors in the 423-pin package speed/features single pack bulk pack 2 ghz (includes 0mb rdram) bx80528jk200g n/a 1.90 ghz (includes 0mb rdram) bx80528jk190g n/a 1.80 ghz (includes 0mb rdram) bx80528jk180g n/a 1.70 ghz (includes 256mb rdram) bx80528jk170gr2 bk80528jk170gr2 1.70 ghz (includes 128mb rdram) bx80528jk170gr bk80528jk170gr 1.70 ghz (includes 0mb rdram) bx80528jk170g n/a 1.60 ghz (includes 0mb rdram) bx80528jk160g n/a 1.50 ghz (includes 256mb rdram) bx80528jk150gr2 bk80528jk150gr2 1.50 ghz (includes 128mb rdram) bx80528jk150gr bk80528jk150gr 1.40 ghz (includes 128mb rdram) bx80528jk140gr bk80528jk140gr 1.30 ghz (includes 128mb rdram) bx80528jk130gr bk80528jk130gr file://///bnsndv31/data/prod/prod-image/vip_pro...%20processors%20-%20product%20order%20codes.htm (2 of 3) [2/22/2005 1:47:32 pm]
intel(r) pentium(r) 4 processors - product order codes this applies to: intel? pentium? 4 processors pentium? 4 processor extreme edition solution id: cs-007993 date created: 10-jul-2003 last modified: 23-dec-2003 back to top file://///bnsndv31/data/prod/prod-image/vip_pro...%20processors%20-%20product%20order%20codes.htm (3 of 3) [2/22/2005 1:47:32 pm]

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