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toshiba plc2 (TC35821F) specification ( 2 ) 1998 toshiba corp. the information contained herein is presented only as a guide for the product operation, its functions, and applications. we request that the operation of any application system incorporating this product is fully tested by system bender. precaution during usage these toshiba products are intended for usage in general commercial application (office equipment, communication equipment, measuring equipment, domestic appliances, etc.). please make sure that you consult with us before you use these toshiba products in equipment which requires extraordinarily high quality and/or reliability, and in equipment which may involve life threatening or critical applications, including but not limited to such uses as atomic energy controls, airplane or spaceship instrumentation, traffic signals, medical instrumentation, combustion control, all types of safety devices, etc. toshiba cannot accept and hereby disclaim liability for any damage which may occur in case the toshiba products are used in such equipment or applications without prior consultation with toshiba. technical data contained herein are proprietary information of toshiba corporation which shall be treated confidentially, and shall not be furnished to third parties or made public without prior written permission by toshiba corporation. these technical data are subject to export control law of japan/cocom regulations, and diversion contrary thereto is prohibited. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others.
toshiba plc2 (TC35821F) specification ( 3 ) primary features of plc2 1) sonet:sts-3c, sts-1, sts-1/2, sdh:stm-1 2) 155mhz pecl serial line interface with on-chip clock recovery and on-chip clock synthesis 3) cell interface operates in following mode: utopia level-2 single-phy(compatible with utopia level-1) with 8 bit data bus. utopia level-2 multi-phy with 8 bit data bus. utopia level-2 multi-phy with 16 bit data bus. 4) programmable soh/poh handling 5) 19.44mhz/6.48mhz/3.24mhz internal operation 6) maximum 40mhz cell interface operation 7) 0.6 m m cmos technology 8) 5.0v single power supply 9) 144pin thin plastic qfp functional summary of plc2 receive functions 1) clock recovery from 156/52/26mbps nrz signal 2) byte alignment and frame synchronization 3) frame descrambling 4) frame overhead analysis 5) atm cell synchronization 6) atm cell header error correction 7) atm cell payload descramble transmit functions 1) atm cell payload scramble 2) atm hec generation 3) frame overhead generation 4) frame assembly 5) frame scrambling
toshiba plc2 (TC35821F) specification ( 4 ) table of contents 1 general 1.1 frame format 1.2 frame overhead 1.3 error status 1.4 alarm signaling 1.5 performance monit oring 2 interface 2.1 block diagram 2.2 pin description 2.3 line interface 2.4 cell interface 2.5 cpu interface 3 registers 4 receive functions 4.1 receive clock 4.2 frame synchronization 4.3 frame descrambling 4.4 bip/febe count 4.5 pointer operation 4.6 detection of irregular state 4.7 detection of alarm signals 4.8 cell processing 5 transmit functions 5.1 transmit clock generation 5.2 frame scrambling 5.3 bip calculation 5.4 soh bytes insertion 5.5 poh bytes insertion 5.6 alarm signal insertion 5.7 transmit cell processing 6 operation and test 6.1 startup procedure
toshiba plc2 (TC35821F) specification ( 5 ) 6.2 loop back 6.3 diagnostic test 7 absolute maximum ratings 8 dc characteristics 9 timing characteristics 9.1 line interface 9.2 cell interface 9.3 cpu i nterface appendix a.1 plc2 internal operation a.2 plc2 clocking details a.3 plc2 application guidance
toshiba plc2 (TC35821F) specification 1- 1 1. general the plc2 supports sonet sts-3c(sdh stm-1), sts-1 and sts-1/2. the following sections 1.1-1.5 review the frame format, frame overhead, error status, alarm signaling and performance monitoring. 1.1 frame format (1) sts-3c (stm-1) the sts-3c (stm-1) has a frame of 270 columns ( in bytes) and 9 rows, with 9 columns of overhead and 261 columns of payload as shown in figure 1.1.1. the virtual container vc4 is mapped into the payload area of sts-3c(stm-1). vc4 has a column of overhead called poh (path overhead) and 260 columns of payload. the atm cells are mapped into the payload area of vc4. 270 9 261 atm cell 9 261 9 soh au-4 soh poh 260 1 figure 1.1.1 sts-3c (stm-1) frame format sts-3c (stm-1) frame vc-4 vc-4
toshiba plc2 (TC35821F) specification 1- 2 (2) sts-1, sts-1/2 the sts-1 has a frame of 90 columns (in bytes) and 9 rows, with 3 columns of overhead called soh and 87 columns of payload as shown in figure 1.1.2. the sts-1 spe(=synchronous payload envelope), which is mapped into the payload area, has a column of overhead called poh(=path overhead) and 87 columns of payload. the atm cells are mapped into the payload area of sts-1 spe except for the 30th and 59th columns which are designated stuff columns. sts-1/2 has the same frame format with sts-1. 90 soh 9 sts-1 spe sts-1 payload capacity sts-1 spe poh 1 30 59 87 figure 1.1.2 sts-1 (sts-1/2) frame format sts-1 (sts-1/2) frame
toshiba plc2 (TC35821F) specification 1- 3 1.2 frame overhead the overhead bytes are assigned into soh and poh as shown in figure 1.2.1 for sts- 3c(stm-1) and figure 1.2.2 for sts-1 and sts-1/2. soh poh a1 a1 a1 a2 a2 a2 c1 c1 c1 j1 b1 ** ** e1 ** ** f1 ** ** b3 d1 ** ** d2 ** ** d3 ** ** c2 h1 h1 h1 h2 h2 h2 h3 h3 h3 g1 b2 b2 b2 k1 ** ** k2 ** ** f2 d4 ** ** d5 ** ** d6 ** ** h4 d7 ** ** d8 ** ** d9 ** ** z3 d10 ** ** d11 ** ** d12 ** ** z4 z1 z1 z1 z2 z2 z2 e2 ** ** z5 ( ** : not defined) figure 1.2.1 sts-3c(stm-1) overhead byte assignment soh poh a1 a2 c1 j1 b1 e1 f1 b3 d1 d2 d3 c2 h1 h2 h3 g1 b2 k1 k2 f2 d4 d5 d6 h4 d7 d8 d9 z3 d10 d11 d12 z4 z1 z2 e2 z5 figure 1.2.2 sts-1(sts-1/2) overhead byte assignment the usage of these bytes are almost common for sts-3c(stm-1) , sts-1 and sts1/2. table 1.2.1 and table 1.2.2 summarize the usage of the overhead bytes in soh and poh, respectively.
toshiba plc2 (TC35821F) specification 1- 4 name function a1, a2 frame synchronization. c1 identify sts1's in sts-n frame(sonet) / stm-1's in stm-n frame(sdh). b1 section bip-8 error. e1 not used in uni. f1 not used in uni. d1-d3 not used in uni. h1, h2 au pointer and path-ais. h3 stuff operation. b2 line bip-24 for sts-3c and line bip-8 for sts-1. k1 not used in uni. k2 line ais and line rdi. d4-d12 not used in uni. z1 not used in uni. z2 line febe. table 1.2.1 o verhead byte functions in soh. name function j1 check path connection. b3 monitor path bip-8 error. c2 indicate the payload type. for atm cell, the value should be 13h. g1 path rdi and path febe. f2 not used in uni. h4 indicate the location of the first atm cell following h4. z3 not used in uni. z4 not used in uni. z5 not used in uni. table 1.2.2 overhead byte functions in poh.
toshiba plc2 (TC35821F) specification 1- 5 1.3 error status plc2 detects following five error status. los : loss of signal condition/action detection no signal condition continues for t1 m sec ( 2.3 t 1 100). release two consecutive valid frame alignment patterns ( a1's and a2's) have been detected without no los between the two valid frame alignment patterns. action once los is detected, the equipment shall send line ais, line rdi, path ais or path rdi. oof : out of frame condition/action detection four consecutive invalid framing patterns have been received. release two consecutive valid frame alignment patterns have been detected. action the equipment should monitor the duration of oof. lof : loss of frame condition/action detection oof has continued for 3 msec. release in frame condition has continued for 3 msec. action once lof is detected, the equipment shall send line ais, line rdi, path ais or path rdi. lop : loss of pointer condition/action detection a valid pointer is not found in n consecutive frames or n consecutive ndf's are detected, where 8 n 10. release a valid pointer with normal ndf, or a concatenation indicator, is detected in three consecutive frames. when an all 1's pointer(ais) is detected in three consecutive frames, the equipment should exit from the lop state and enter the path ais state. action once lop is detected, the equipment shall send path ais or path rdi. loc : loss of cell delineation condition/action detection 7 consecutive hec errors have been detected. release 7 consecutive normal hec's have been detected. action when loc is detected, the equipment shall send path ais or path rdi.
toshiba plc2 (TC35821F) specification 1- 6 1.4 alarm signaling plc2 supports following 4 alarm signals. line ais definition condition of generation state of los or lof. generation k2(b6-8) = 111 and all-ones in the payload of sts-3c/sts-1 frame. condition of removal exit from los and lof. removal k2(b6-8) 1 111. detection of generation k2(b6-8) = 111 in five consecutive frames(sonet) / in at least three consecutive frames(sdh). detection of removal k2(b6-8) 1 111 in five consecutive frames(sonet) / in at least three consecutive frames(sdh). line rdi definition condition of generation detection of los, lof or line ais generation k2(b6-8) = 110. condition of removal exit from los, lof and line ais. removal k2(b6-8) 1 110. detection of generation k2(b6-8) = 110 in five consecutive frames(sonet) / in at least three consecutive frames(sdh). detection of removal k2(b6-8) 1 110 in five consecutive frames(sonet) / in at least three consecutive frames(sdh). path ais definition condition of generation detection of los, lof, lop, loc or line ais. generation all-ones in the h1/h2/h3 bytes and the entire payload. condition of removal exit from los, lof, lop, loc and line ais. removal a correct sts pointer with ndf set to '1001' followed by normal pointer operations and normal data in the payload. detection of generation all-ones in the h1/h2 bytes for three consecutive frames (for sonet and sdh as well). detection of removal a valid sts pointer with ndf set to '1001', or a valid sts pointer with normal ndf in three consecutive frames (for sonet and sdh as well) or lop is detected (in sdh mode only).
toshiba plc2 (TC35821F) specification 1- 7 path rdi definition condition of generation detection of los, lof, lop, loc, line ais or path ais. generation g1(b5) = 1. condition of removal exit from los, lof, lop, loc, line ais and path ais. removal g1(b5) = 0. detection of generation g1(b5) = 1 in ten consecutive frames(sonet) / in at least three consecutive frames(sdh). detection of removal g1(b5) =0 in ten consecutive frames(sonet) / in at least three consecutive frames(sdh). 1.5 performance monitoring plc2 supports following two performance monitors. line febe line bip-24 is calculated over the entire area of each frame after descrambling except for the first to third rows of soh based on 24 bits interleaved parity calculation using even parity. the calculated bip-24 code is compared with the triple b2 bytes of the following frame. differences indicates the line level bit errors. the bit errors are counted and inserted to the third z2 byte of transmit soh as shown in figure 1.5.1. z2 z2 z2 00h 00h 0 l-febe[6:0] figure 1.5.1 l-febe insertion to z2 byte. path febe path bip-8 is calculated over the entire area of each vc4 (or spe for sts-1) after descrambling based on 8bits interleaved parity calculation using even parity. the calculated bip-8 code is compared with the b3 byte of the following frame. differences indicates the path level bit errors. the bit errors are counted and inserted to the higher 4 bits of g1 byte of transmit soh as shown in figure 1.5.2. g1 p-febe[3:0] 000 - p-rdi figure 1.5.2 p-febe insertion to g1 byte.
2. interface 2.1 block diagram plc2 block diagram is shown below.
toshiba plc2 (TC35821F) specification 2- 2 2.2 pin description line i/f (20 pin) pin name pin no. i/o type description rxcip rxcim 134, 135 i p-ecl receive clock differential p-ecl input. when rcksel is tied low, rxdip/m is sampled on this clock. they should be terminated to 3.0v via 50 ohm. these pins should be tied to ground when they are not used. rxdip rxdim 128, 129 i p-ecl receive date differential p-ecl input. they should be terminated to 3.0v via 50 ohm. txcop txcom 118, 119 o p-ecl transmit clock differential p-ecl output. they should be terminated to 3.0v via 50 ohm. txcip txcim 125, 126 i p-ecl transmit reference clock differential p-ecl input. when tcksel is tied low, txdop/m is updated on this clock. they should be terminated to 3.0v via 50 ohm. these pins should be tied to ground when they are not used. txdop txdom 122, 123 o p-ecl transmit data differential p-ecl output. they should be terminated to 3.0v via 50 ohm. loocp loocm 131, 132 i p-ecl loocp/m should be connected with signal detect output sd-/+ of optical module. when looc is tied high, rxdi input is fixed to zero inside plc2 and receive pll switches to the reference clock refck to keep the oscillation. loocp/m should be terminated to 3.0v via 50 ohm. these pins should be tied to ground when they are not used. biasp biasm 114, 115 i p-ecl this input generates p-ecl voltage level. they should be connected to 3.0v via 50 ohm. rxcko 139 o cmos receive serial clock (recovered from receive data or rxcip/m depending on rcksel) is divided by eight and output from rxcko when clksel of tsmod2 register is set to 0. transmit serial clock is divided by eight and output from rxcko when clksel is set to 1. rxfilt 106 ao analog rxfilt should be connected to avssr via lpf for receive pll. rxres 107 ao analog rxres should be connected to avssr via resistor for reference current of receive pll. txfilt 111 ao analog txfilt should be connected with avsst via lpf for transmit pll. txres 110 ao analog txres should be connected to avsst via resistor for reference current of transmit pll. refck 143 i cmos reference clock of 19.44mhz should be input regardless of transmission rate (sts-3, sts-1, sts-1/2).
toshiba plc2 (TC35821F) specification 2- 3 cell i/f (53 pin) pin name pin no. i/o type description txdac[15: 0] 43, 45-53, 56-61 ti ttl the transmit cell data bus from atm layer. txsoc 63 ti ttl the transmit start of cell indication is asserted when txdac contains the first byte of cell data. -txenb 41 i ttl the active low cell transfer enable signal is activated when txdac contains valid cell data. txcav 42 to ttl the transmit cell available is asserted high when plc2 can receive a complete cell data from atm layer. txclkc 40 i ttl the operation clock for the transmit cell interface. txpty 62 i ttl the parity bit for txdac. both odd parity and even parity are selectable. txadd[4:0] 65-69 i ttl tx phy port address rxdac[15: 0] 6, 7, 9-11, 14-17, 20-23, 25-27 to ttl the receive cell data bus to atm layer. rxsoc 30 to ttl the receive start of cell indication is asserted high when rxdac contains the first byte of cell data. -rxenb 3 i ttl the receive cell transfer enable signal is asserted low when atm layer device will sample cell data in the next cycle. rxcav 5 to ttl the receive cell available is asserted high when plc2 is ready to transfer a complete cell data to atm layer. rxclkc 2 i ttl the operation clock for the receive cell interface. rxpty 29 to ttl the parity bit for rxdac. both odd parity and even parity are selectable. rxadd[4:0] 32-34, 38, 39 i ttl rx phy port address trien 31 i cmos tri - state enable. when it is tied high, type to signals of cell interface operate as tri-state output. when it is tied low, they are always in drive mode.
toshiba plc2 (TC35821F) specification 2- 4 cpu i/f (23 pin) pin name pin no. i/o type description a[6:0] 87-89, 91-94 i ttl address bus d[7:0] 76-79, 82-85 bidirect ttl data bus ale 95 i ttl address latch enable. address a[6:0] is latched at falling edge of ale. when ale is high, the internal address latches are transparent. -ce 96 i ttl active low chip enable -rd 97 i ttl active low read command -wr 98 i ttl active low write command -ready 99 to ttl active low ready signal -reset 75 i ttl active low hardware reset signal -int 101 o ttl active low interrupt signal clk 74 i ttl cpu i/f clock signal. recommended to be 19.44mhz. monitor output (1 pin) pin name pin no. i/o type description rxref 70 o ttl when monsel bit in tsmod2 register is set high, 8khz frame clock is output. it goes high for one byte clock period at one frame interval (sts-3/stm-1, sts-1) or two frame interval (sts-1/2). when monsel bit in tsmod2 register is set low, internal signal "refsyn" is output. mode select (6 pin) pin name pin no. i/o type description rcksel 137 i cmos receive clock select. when it is tied high, internally recovered clock is used to sample rxdip/m. when it is tied low, external clock rscip/m is used to sample rxdip/m. tcksel 138 i cmos transmit clock select. when it is tied high, txpll generates clock used to serialize transmit data. when tied low, txcip/m is used to serialize transmit data. in loop-timing mode, the receive clock is used as transmit clock and tcksel has no effect. refsel 141 i cmos when tied high, rxpll generates x8 clock from refck. when tied low, rxpll recovers clock from receive data as long as receive data is normal. tsdsel 142 i cmos transmit data select. when it is tied low, normal transmit data is output from txdop/m. when it is tied high, rxdip/m is directly output from txdop/m. hizen 103 i cmos this input selects following mode 1: all the terminal are set to hi-z 0: normal operation dlysel 102 i cmos this input selects following mode 0: rxdip/m is sampled on the rising edge of receive serial clock 1: rxdip/m is sampled on the falling edge of receive serial clock
toshiba plc2 (TC35821F) specification 2- 5 vdd/gnd (41 pin) pin name pin no. description dvdd(15) 1,12,18,24, 36,37,54,72, 81,90,117,121, 127,133,144 vdd for digital block and p-ecl buffer dvss(20) 4,8, 13,19, 28,35, 44,55, 64,71, 73,80, 86,100,116,120, 124,130,136,140 vss for digital block and p-ecl buffer avddr 105 vdd dedicated for receive pll. it should be coupled with dvdd via filter or ferrite beads. avssr 108 vss dedicated for receive pll. it should be coupled with dvss via filter or ferrite beads. avddt 112 vdd dedicated for transmit pll. it should be coupled with dvdd via filter or ferrite beads. avsst 109 vss dedicated for transmit pll. it should be coupled with dvss via filter or ferrite beads. tvss(2) 104, 113 vss dedicated for guard pwell. they should be separated with dvss via filter or ferrite beads. '-' indicates active low signal
toshiba plc2 (TC35821F) specification 2- 6 plc2 pin layout pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 dvdd 37 dvdd 73 dvss 109 avsst 2 rxclkc 38 rxadd3 74 clk 110 txres 3 -rxenb 39 rxadd4 75 -reset 111 txfilt 4 dvss 40 txclkc 76 d0 112 avddt 5 rxcav 41 -txenb 77 d1 113 tvss 6 rxdac0 42 txc av 78 d2 114 biasp 7 rxdac1 43 txdac0 79 d3 115 biasm 8 dvss 44 dvss 80 dvss 116 dvss 9 rxdac2 45 txdac1 81 dvdd 117 dvdd 10 rxdac3 46 txdac2 82 d4 118 txcop 11 rxdac4 47 txdac3 83 d5 119 txcom 12 dvdd 48 txdac4 84 d6 120 dvss 13 dvss 49 txdac5 85 d7 121 dvdd 14 rxdac5 50 txdac6 86 dvss 122 txdop 15 rxdac6 51 t xdac7 87 a0 123 txdom 16 rxdac7 52 txdac8 88 a1 124 dvss 17 rxdac8 53 txdac9 89 a2 125 txcip 18 dvdd 54 dvdd 90 dvdd 126 txcim 19 dvss 55 dvss 91 a3 127 dvdd 20 rxdac9 56 txdac10 92 a4 128 rxdip 21 rxdac10 57 txdac11 93 a5 129 rxdim 22 rxdac11 58 txdac12 94 a6 130 dvss 23 rxdac12 59 txdac13 95 ale 131 loocp 24 dvdd 60 txdac14 96 -ce 132 loocm 25 rxdac13 61 txdac15 97 -rd 133 dvdd 26 rxdac14 62 txpty 98 -wr 134 rxcip 27 rxdac15 63 txsoc 99 -ready 135 rxcim 28 dvss 64 dvss 100 dvss 136 dvss 29 rxpty 65 txadd0 101 -int 137 rcksel 30 rxsoc 66 txadd1 102 dlysel 138 tcksel 31 trien 67 txadd2 103 hizen 139 rxcko 32 rxadd0 68 txadd3 104 tvss 140 dvss 33 rxadd1 69 txadd4 105 avddr 141 refsel 34 rxadd2 70 -rxref 106 rxfilt 142 tsdsel 35 dvss 71 dvss 107 rxres 143 refck 36 dvdd 72 dvdd 108 avssr 144 dvdd
toshiba plc2 (TC35821F) specification 2- 7 1 36 37 72 73 108 109 144 dvdd rxclkc -rxenb rxcav rxdac0 rxdac1 rxdac2 dvss rxdac3 rxdac4 rxdac5 dvdd dvss rxdac6 rxdac7 rxdac8 rxdac9 dvdd rxdac10 rxdac11 rxdac12 rxdac13 dvss rxdac14 rxdac15 rxpty rxsoc rxadd0 rxadd1 rxadd2 rxadd3 rxadd4 dvss dvdd dvss dvdd dvdd trien txclkc -txenb txcav txdac0 dvss txdac1 txdac2 txdac3 txdac4 txdac5 txdac6 txdac7 txdac8 dvss dvdd txdac9 txdac10 txdac11 txdac12 txdac13 txdac14 txdac15 txpty txsoc dvss txadd0 txadd1 txadd2 txadd3 txadd4 dvss dvdd dvss clk -reset d0 d1 d2 d3 dvss hizen tvss0 avddr rxfilt rxres avssr avsst txfilt txres avddt tvss1 biasp biasm dvss dvdd txcop txcom dvss dvdd txdop txdom dvss txcip txcim dvdd rxdip rxdim dvss loocp loocm dvdd rxcip rxcim dvss rcksel tcksel rxcko dvss refsel tsdsel refck dvdd plc2 dvss d4 d5 d6 d7 a0 a1 a2 a3 dvdd a4 a5 a6 ale -ce -rd -wr -ready -int dvss dvss dlysel rxref dvdd plc2 pin assignment
toshiba plc2 (TC35821F) specification 2- 8 2.3 line interface (1) receive line interface rxcip/m the bit serial receive clock input is used when the on-chip clock recovery is disabled. the frequency should be 155.52mhz for sts-3, 51.84mhz for sts-1 and 25.92mhz for sts-1/2. when the on-chip clock recovery is enabled, rxcip/m is not used. rxdip/m the receive differential serial data input rxdip/m is sampled on the rising edge of receive serial clock, which is rxcip/m or internally recovered clock depending on rcksel. optionally rxdip/m can be sampled on the falling edge of receive serial clock by tying dlysel pin to high. (2) transmit line interface txcip/m the differential transmit clock input is used when the bit serial interface is selected and the on-chip transmit clock synthesis is disabled. the frequency should be 155.52mhz for sts-3, 51.84mhz for sts-1 and 25.92mhz for sts-1/2. when the on-chip transmit clock synthesis is enabled or loop timing mode is selected, txcip/m is not used. txdop/m the transmit differential serial data output is updated on the falling edge of txcip/m. rxdip/m rxcip/m ts_rxdi th_rxdi figure 2.3.1 rx line interface timing txdip/m txcip/m td_txdo figure 2.3.2 tx line interface timing
toshiba plc2 (TC35821F) specification 2- 9 2.4 cell interface (1) transmit cell interface in single-phy mode the transmit cell interface operates basically in cell mode instead of byte mode, that is, the plc2 asserts txcav when it has capacity for a complete cell. but it can receive the byte mode cell transfer. txclkc transmit cell interface clock provided by the atm layer. txcav active high, cell available signal asserted by the plc2 to indicate it can receive a complete cell. if the plc2 has no more capacity for a cell, it deasserts txcav when the 44th payload of a cell is output on txdac[7:0]. txenb* active low enable signal asserted by the atm layer when txdac[7:0] contains a valid data. txsoc active high, start of cell signal asserted by the atm layer. txadd[4:0] polling address input is ignored in single-phy mode. txdac[7:0] transmit cell data bus driven by the atm layer device. txpty the parity bit for txdac[7:0]. both odd parity and even parity are selectable. when a parity error is detected in a cell received by the plc2, it is just reported to the host cpu and the cell is not discarded.
toshiba plc2 (TC35821F) specification 2- 10 figure 2.4.1 shows the consecutive transmit cell transfer without any obstacles. when plc2 finds the transmit fifo has a room for a complete cell, it asserts txcav at the rising edge of txclkc. the atm layer recognizes this indication and asserts txenb* and puts valid cell data on txdac[7:0]. txsoc coincides with the first byte of a cell. figure 2.4.2 shows the case where the atm layer stops the data transfer for one cycle. the atm layer deasserts txenb* to indicate that the data on txdac[7:0] is invalid. txclkc txsoc txcav txenb* txdac p48 p47 p46 p44 p43 p45 h1 h2 h1 h2 h3 h4 x figure 2.4.1 transmit cell transfer (1) txclkc txsoc txcav txenb* txdac p48 p47 p46 p44 p43 p45 h1 h2 h1 h2 x h3 x figure 2.4.2 transmit cell transfer (2)
toshiba plc2 (TC35821F) specification 2- 11 figure 2.4.3 shows the case of a single cell data transfer. the plc2 deasserts txcav when the 44th payload byte is on txdac, to indicate it cannot accept another cell. the atm layer stops the cell transfer and deasserts txenb* after the last byte of the cell has been transferred. figure 2.4.4 shows the case where the plc2 stops the next cell transfer. the plc2 finds, when receiving a cell data, no room for another cell and deasserts txcav when it is receiving the 44th payload byte. the atm layer continues the cell transfer and stops it and deasserts txenb* in the next cycle of the last byte of the cell. at the same instance, the plc2 finds the transmit fifo has now a room for a cell and asserts txcav. watching this, the atm layer resumes the transfer of cell. txclkc txsoc txcav txenb* txdac p48 p47 p46 p44 p43 p45 h1 h2 x x figure 2.4.3 transmit cell transfer (3) txclkc txsoc txcav txenb* txdac p48 p47 p46 p44 p43 p45 h1 h2 h1 h2 x h3 x figure 2.4.4 transmit cell transfer (4)
toshiba plc2 (TC35821F) specification 2- 12 (2) receive cell interface in single-phy mode the receive cell interface operates basically in cell mode instead of byte mode, that is, the plc2 starts cell transfer when is has a complete cell in the receive cell fifo. but the plc2 can stop the cell transfer when it is so requested by the atm layer. rxclkc receive cell interface operation clock. rxcav active high, cell available signal asserted by the plc2 to indicate it has a complete cell available for transfer to the atm layer. rxenb* active low, enable signal asserted by the atm layer to indicate that rxdac and rxsoc will be sampled at the next cycle. rxsoc active high, start of cell signal asserted by the plc2 when the first byte of the cell appears on rxdac. rxadd[4:0] polling address input is ignored in single-phy mode. rxdac[7:0] receive cell data bus driven by the plc. rxdac[7:0] is tri-state type. when trien is set low, rxdac is always driven by the plc2. when trien is set high, rxdac[7:0] is driven by the plc2 only in cycles following those with rxenb* asserted. rxpty the parity bit for rxdac[7:0]. both odd parity and even parity are selectable. when trien is set low, rxpty is always driven by the plc2. when trien is set high, rxpty is driven by the plc2 only in cycles following those with rxenb* asserted. fig 2.4.5 shows the consecutive receive cell transfer without any obstacles. when the plc2 has a complete cell to transfer, it activates rxcav at the rising edge of rxclkc. rxclkc rxsoc rxcav rxenb* rxdac p48 p47 p46 p45 h1 h2 h3 h4 h1 h2 x h3 figure 2.4.5 receive cell transfer (1)
toshiba plc2 (TC35821F) specification 2- 13 the atm layer then activates rxenb* indicating that it will sample the data on rxdac from the next cycle. the plc2 begin the transfer of the cell data on rxdac. figure 2.4.6 shows the case where the atm layer stops the cell transfer. the plc2 recognizes rxenb* deactivated and outputs the 47th payload byte again. figure 2.4.7 shows the case where the plc2 deasserts rxcav for a cycle after a cell transfer has been completed. in the cycles denoted by x on rxdac, the atm layer waits for another cell transfer with keeping rxenb* low. rxclkc rxsoc rxcav rxenb* rxdac h1 h2 x h3 p48 p47 p46 p45 h1 h2 h3 figure 2.4.6 receive cell transfer (2) rxclkc rxsoc rxcav rxenb* rxdac p48 p47 p46 p45 h1 h2 h3 h1 h2 x h3 x figure 2.4.7 receive cell transfer (3)
toshiba plc2 (TC35821F) specification 2- 14 (3) transmit cell interface in multi-phy mode the transmit cell interface operates basically in cell mode instead of byte mode, that is, the plc2 asserts txcav when it is polled and it can receive a complete cell into the transmit cell fifo. but the atm layer can halt ongoing cell transmission anytime by deasserting -txenb. txclkc transmit cell interface clock provided by the atm layer. txcav active high, cell available signal asserted by the plc2 to indicate it can receive a complete cell. when plc2 is polled, plc2 drives txcav high or low in the following cycle, depending on the condition of the transmit cell fifo of the port. when the fifo can receive a cell, txcav is driven high, otherwise txcav is driven low. txcav is always driven by plc2 when trien is tied low. txenb* -txenb indicates that txdac[15:0] contains valid data when asserted low. it is also used to select a port to send cell data. for port selection, -txenb is kept high and at the same time, txadd[4:0] indicates which port should be selected. in the following cycle, -txenb is asserted and txdac[15:0] outputs valid cell data. txsoc active high, start of cell indication asserted by the atm layer. txadd[4:0] transmit polling address driven by the atm layer. txdac[15:0] transmit cell data bus driven by the atm layer. txpty the parity bit for txdac[15:0]. both odd parity and even parity are selectable. when a parity error is detected in a cell received by the plc2, it is reported to the host cpu and the cell is not discarded. fig. 2.4.8 shows polling at transmit interface. the polling takes two steps. for instance, at clock edge #2, atm layer indicates that port "n" is to be polled. then at clock edge #3, atm layer does not change the level of -txenb and plc2 drives or not drive txcav depending on the condition in plc2. the plc2 drives txcav high if port "n" exists in plc2 and the port is ready to receive a cell from atm layer. it drives txcav low if port "n" exists in plc2 and the port is not ready to receive a cell from atm layer. it does not drive txcav at clock edge #3 if port address "n" does not match the port address in plc2. the port address is stored in ciadr register. atm layer should not change the level of - txenb from high to low during polling phase because such a move is considered by plc2 as "selection" and plc2 starts to receive cell. care should be taken that when atm
toshiba plc2 (TC35821F) specification 2- 15 layer transmits cell to port n, it should not poll the port n. such polling behavior is not assumed. figure 2.4.9 shows selection at transmit interface. at clock edge #4 atm layer indicates the port address to be selected on txadd[4:0] and at clock edge #5 asserts -txenb to indicate that selection is being done. at clock edge #5, atm layer starts cell transmission. this figure shows a case of the minimum interval between adjacent cell transmission. txclkc txadd[4:0] 1 2 3 4 5 6 txcav 7 -txenb n n+1 n+2 1f 1f 1f 1f n n+1 n+2 figure 2.4.8 polling at transfer interface 1 2 3 4 5 6 7 txclkc txadd[4:0] txcav 1f 1f 1f 1f -txenb txsoc txdac[15:0] & txpty p48 p47 h1 h2 n n+1 n+2 n n+1 n+2 phy n-1 phy n+1 cell trans- mission to: p46 p45 p44 p43 h3 h4 h5 udf figure 2.4.9 selection at transmit interface
toshiba plc2 (TC35821F) specification 2- 16 figure 2.4.10 shows a case where polling is done before restart of cell transmission. during polling, atm layer leaves txsoc, txpty and txadd[15:0] in hi-z state. figure 2.4.11 shows a case where cell transmission is paused halfway. to restart the cell transmission atm layer selects port m explicitly at clock edge #7. txclkc txadd[4:0] txcav 1f 1f 1f 1f 1 2 3 4 5 6 -txenb txsoc txdac[15:0] & txpty n n+1 n+1 n+2 1f 7 8 9 n n+1 n+1 n+2 phy n-1 phy n+1 cell trans- mission to: p44 p43 p46 p45 p48 p47 h1 h2 h3 h4 h5 udf figure 2.4.10 end and restart of cell transmission at transmit interface txclkc txadd[4:0] txcav 1f 1f 1f 1f 1 2 3 4 5 6 -txenb txsoc txdac[15:0] & txpty p12 p11 p10 p13 p14 p15 n n+1 m n+2 1f 7 8 9 n n+1 m n+2 phy m phy m cell trans- mission to: p16 p17 p18 p19 p20 p21 figure 2.4.11 cell transmission to phy paused for three cycles
toshiba plc2 (TC35821F) specification 2- 17 (4) receive cell interface in multi-phy mode the receive cell interface operates basically in cell mode instead of byte mode, that is, the plc2 starts cell transmission when it has a complete cell in the receive cell fifo. but the atm layer can halt the cell transmission by deasserting -rxenb. rxclkc receive cell interface operation clock. rxcav active high, cell available signal asserted by the plc2 to indicate it can transmit a complete cell. when plc2 is polled, plc2 drives rxcav high or low in the following cycle, depending on the condition of the receive cell fifo of the port. when the fifo contains a complete cell to transmission, rxcav is driven high, otherwise rxcav is driven low. rxcav is always driven by plc2 when trien is tied low. -rxenb -rxenb indicates that rxdac[15:0] contain valid data in the following cycle when asserted low. it is also used to select a port to transmission cell data. for port selection, - rxenb is deasserted and at the same time, rxadd[4:0] indicates which port is selected. in the following cycle, -rxenb is asserted and rxdac[15:0] is sampled from the following cycle. rxsoc active high, start of cell signal asserted by the plc2 when the first byte of the cell appears on rxdac[15:0]. rxadd[4:0] receive polling address driven by the atm layer. rxdac[15:0] receive cell data bus driven by the plc. rxdac[15:0] is tri-state type. when trien is set low, rxdac is always driven by the plc2. when trien is set high, rxdac[15:0] is driven by the plc2 only in cycles following those with -rxenb asserted. rxpty the parity bit for rxdac[7:0]. both odd parity and even parity are selectable. when trien is set low, rxpty is always driven by the plc2. when trien is set high, rxpty is driven by the plc2 only in cycles following those with -rxenb asserted.
toshiba plc2 (TC35821F) specification 2- 18 fig. 2.4.12 shows polling at receive interface. the polling takes two steps. for instance, at clock edge #2, atm layer indicates that port "n" is to be polled. then at clock edge #3, atm layer does not change the level of -rxenb and plc2 drives or not drive rxcav depending on the condition in plc2. the plc2 drives rxcav high if port "n" exists in plc2 and it is ready to transmit a cell to atm layer. it drives rxcav low if port "n" exists in plc2 and the port is not ready to transmit a cell to atm layer. it does not drive rxcav at clock edge #3 if port address "n" does not match the port address in plc2. the port address is stored in ciadr register. atm layer should not change the level of -rxenb from high to low during polling phase because such a move is considered by plc2 as "selection" and plc2 starts to transmit cell. care should be taken that when atm layer receives a cell from port n, it should not poll the port n. such polling behavior is not assumed. figure 2.4.13 shows selection at receive interface. at clock edge #3 atm layer indicates the port address to be selected on txadd[4:0] and at clock edge #4 asserts - rxenb to indicate that selection is being done. at clock edge #5, plc2 starts cell transmission to atm layer. this figure shows a case of the minimum interval between adjacent cell transmission of different port. rxclkc rxadd[4:0] rxcav 1 2 3 4 5 6 7 -rxenb 1f 1f 1f 1f n n+1 n+2 n n+1 n+2 figure 2.4.12 polling at receive interface
toshiba plc2 (TC35821F) specification 2- 19 figure 2.4.14 shows a case where polling is done before restart of cell transmission. at clock edge #4, atm layer finds no port other than port n-1is ready to transmit a cell to atm layer and let -rxenb asserted to see if port n-1 is ready to transmit a cell. at clock edge #5, atm layer finds that port n-1 has no more cell because plc2 leaves rxsoc low. then atm layer deasserts -rxenb to indicate that cell transmission is over. during the cycle of clock edge #5, plc2 continues driving rxsoc, rxpty and rxdac[15:0] because -rxenb was asserted during the cycle of clock edge #4. polling continues during such transaction. at clock edge #8, atm layer find that port n+2 is ready to transmit a cell. then port n+2 is selected at clock edge #9. port n+2 starts cell transmission at clock edge #10. 1 2 3 4 5 6 7 rxclkc rxadd[4:0] rxcav 1f 1f 1f -rxenb rxsoc rxdac[15:0] & rxpty n n+1 n+2 n n+1 n+2 phy n-1 phy n+1 cell trans- mission from: n+3 p44 p43 p46 p45 p48 p47 h1 h2 h3 h4 h5 udf figure 2.4.13 selection at receive interface rxclkc rxadd[4:0] rxcav 1f 1f 1f 1f 1 2 3 4 5 6 -rxenb rxsoc rxdac[15:0] & rxpty n n+1 n+2 n+2 1f 7 8 9 n n+1 n+2 n+2 phy n-1 phy n+1 cell trans- mission from: xx n+3 1f 10 11 n+3 p44 p43 p46 p45 p48 p47 h1 h2 h3 h4 figure 2.4.14 end and restart of rell transmission at receive interface
toshiba plc2 (TC35821F) specification 2- 20 figure 2.4.15 shows a case of back to back cell transmission. at clock edge #5, atm layer leaves -rxenb asserted because no other port than phy n is ready to transmit a cell. at clock edge #6, port n finds that it is invited to transmit one more cell and the port happens to have a cell to transmit, then it starts to transmit a cell. figure 2.4.16 shows atm layer stops cell transmission halfway by deasserting -rxenb for three cycles. atm layer should select the port ( in this case port "m") again before restarting cell transmission. atm layer can continue polling when it suspends cell transmission. rxclkc rxadd[4:0] rxcav 1f 1f 1f 1f 1 2 3 4 5 6 -rxenb rxsoc rxdac[15:0] & rxpty n+2 n+3 n+4 n+5 1f 7 8 9 n+2 n+3 n+4 n+5 phy n phy n cell trans- mission from: n+6 1f 10 11 n+6 p48 p47 p46 p45 p44 p43 p41 p42 p39 p40 h1 h2 h3 h4 h5 udf p1 p2 p3 p4 p5 p6 figure 2.4.15 two consecutive cells from same phy txclkc rxadd[4:0] rxcav 1f 1f 1f 1f 1 2 3 4 5 6 -rxenb rxsoc rxdac[15:0] & rxpty n n+1 m n+2 7 8 9 n n+1 m n+2 phy m phy m cell trans- mission from: n+3 p12 p11 p10 p13 p14 p15 p16 p17 p18 p19 p20 p21 figure 2.4.16 cell transmission from phy paused for three cycles
toshiba plc2 (TC35821F) specification 2- 21 2.5 cpu interface the host cpu can read/write registers and memories in plc2 following the procedures described below. the registers can be accessed directly while the internal memories should be accessed indirectly via memal/h and memd registers. (1) read access [with active ale] the cpu puts the read address on address bus a[6:0] and asserts ale. the valid address on a[6:0] must have setup time ( ts_a) and hold time ( th_a) to the falling edge of ale. the data bus d[7:0] is driven by plc2 when (-ce + -rd) is low. the valid data access time from (-ce + -rd) is defined as td_d. -ready turns valid td_ready after (-ce + - rd) goes low. then -ready immediately goes low when read access is made to invalid address. otherwise -ready goes low when the valid data appears on d[7:0]. -ce + -rd valid address a[6:0] ale ts_a th_a tw_ale ts_ale tw_rrecov th_ale d[7:0] -ready valid data tz_rd td_ready tdn_ready td_rd figure 2.5.1 host cpu read access timing with active ale
toshiba plc2 (TC35821F) specification 2- 22 [with ale fixed to high] the cpu puts the read address on address bus a[6:0]. the valid address on a[6:0] must have setup time ( ts_a) to the falling edge of (-ce + -rd) and hold time ( th_a) to the rising edge of (-ce + -rd). the data bus d[7:0] is driven by plc2 when (-ce + -rd) is low. the valid data access time from (-ce + -rd) is defined as td_d. -ready turns valid within td_ready after (-ce + -rd) goes low. then -ready immediately goes low when read access is made to invalid address. otherwise -ready goes low when the valid data appears on d[7:0]. -ce + -rd valid address a[6:0] ale ts_a th_a tw_rrecov d[7:0] -ready valid data tz_rd td_ready tdn_ready td_rd figure 2.5.2 host cpu read access timing with fixed ale
toshiba plc2 (TC35821F) specification 2- 23 (2) write access [with active ale] the cpu puts the write address on address bus a[6:0] and deasserts ale. the valid address on a[6:0] must have setup time ( ts_a) and hold time ( th_a) to the falling edge of ale. the valid write data must have setup time ts_d to the falling edge of (-ce + -wr) and hold time th_d from the rising edge of (-ce + -wr). -ready turns valid within td_ready after (-ce + -wr) goes low. then -ready immediately goes low when write access is made to invalid address. otherwise -ready goes low when the write access is finished in plc2. the (-ce + -wr) low pulse must have minimum width tw_cewr to ensure successful write access. valid address a[6:0] ale d[7:0] -ready ts_a th_a tw_ale ts_ale tw_cewr ts_wd valid data th_wd td_ready tdn_ready -ce + -wr figure 2.5.3 host cpu write access timing with active ale tw_wrecov
toshiba plc2 (TC35821F) specification 2- 24 [with ale fixed to high] the cpu puts the write address on address bus a[6:0]. the valid address on a[6:0] must have setup time ( ts_a) to falling edge of (-ce + -wr) and hold time ( th_a) to the rising edge of (-ce + -wr). the valid write data must have setup time ts_d to the falling edge of (-ce + -wr) and hold time th_d to the rising edge of (-ce + -wr). -ready turns valid within td_ready after (-ce + -wr) goes low. then -ready immediately goes low when write access is made to invalid address. otherwise -ready goes low when the write access is finished in plc2. the (-ce + -wr) low pulse must have minimum width tw_cewr to ensure successful write access. valid address a[6:0] ale d[7:0] -ready ts_a th_a tw_cewr ts_wd valid data th_wd td_ready tdn_ready -ce + -wr figure 2.5.4 host cpu write access timing with fixed ale tw_wrecov
toshiba plc2 (TC35821F) specification 3- 1 3 registers 3.1 register map following registers can be accessed from the host cpu. configuration registers address name type function 00h cont r/w reset/stop of plc2 01h frms r/w frame management register 02h cms1 r/w cell management register 1 03h cms2 r/w cell management register 2 04h loop r/w loop mode select 05h fsync r/w frame synchronization mode 06h csync r/w cell synchronization mode 07h losct r/w los control register 08h reserved 09h j1posh r/w position of j1 byte in tx frame (horizontal) 0ah j1posv r/w position of j1 byte in tx frame (vertical) 0bh ciadr r/w port address in utopia level 2 mode 0ch txalm1 r/w alarm signal control 1 0dh txalm2 r/w alarm signal control 2 0eh reserved 0fh cms3 r/w cell management register 3 status registers address name type function 10h intsel1 r/w interrupt control register 1 11h intsel2 r/w interrupt control register 2 12h intsel3 r/w interrupt control register 3 13h reserved 14h reserved 15h intind1 r/w interrupt status register 1 16h intind2 r/w interrupt status register 2 17h intind3 r/w interrupt status register 3 18h reserved 19h reserved 1ah status1 r status register 1 1bh status2 r status register 2 1ch status3 r status register 3 1dh reserved 1eh reserved 1fh rgfc r receive gfc status
toshiba plc2 (TC35821F) specification 3- 2 error counters address name type function 20h b1errl r b1-sbip8 error counter [7:0] 21h b1errh r b1-sbip8 error counter [15:8] 22h b2errl r b2-lbip24 error counter [7:0] 23h b2errm r b2-lbip24 error counter [15:8] 24h b2errh r b2-lbip24 error counter [19:16] 25h b3errl r b3-pbip8 error counter [7:0] 26h b3errh r b3-pbip8 error counter [15:8] 27h lfebel r r-lfebe counter [7:0] 28h lfebem r r-lfebe counter [15:8] 29h lfebeh r r-lfebe counter [19:16] 2ah pfebel r r-pfebe counter[7:0] 2bh pfebeh r r-pfebe counter [15:8] 2fh fcupd r/w error counter update flag cell counters address name type function 30h coher r corrected cell header error counter 31h ucher r uncollected cell header error counter 32h rxccl r receive valid cell counter [7:0] 33h rxccm r receive valid cell counter [15:8] 34h rxcch r receive valid cell counter [19:16] 35h txccl r transmit valid cell counter [7:0] 36h txccm r transmit valid cell counter [15:8] 37h txcch r transmit valid cell counter [19:16] 3fh ccupd r/w cell counter update flag memory access registers address name type function 40h memal r/w address register [7:0] 41h memah r/w address register [12:8] 42h memd r/w data register test registers address name type function 50h tsmod1 r/w plc2 test mode register 1 51h tsmod2 r/w plc2 test mode register 2 52h tsgen r/w plc2 test mode register 3 53h lfebei r/w plc2 test mode register 4 54h pfebei r/w plc2 test mode register 5
toshiba plc2 (TC35821F) specification 3- 3 hereafter, each register is described in detail. a register field table shows: bit number field name default value on reset in register table, "rsvd" means reserved bit.
toshiba plc2 (TC35821F) specification 3- 4 address : 00h name : cont type : r/w function : reset/stop of plc 7 6 5 4 3 2 1 0 autocse loocde pllini oolde txfres rxfres stop reset 0 0 0 0 0 0 1 1 reset software reset bit. when this bit is set to one , all the registers and counters are initialized. a hardware reset clears the reset bit. the reset bit should be set for at least 10 cycles of the slowest cl ock provided to plc2. 0: plc2 is not held in reset. 1: plc2 is held in reset. stop software stop bit. when this bit is set to one , plc2 stops operation, but does not change the state in plc2. the host cpu can set value to registers and counters for dia gnostic or initialize purpose. the default value of the stop bit on a hardware reset is 1. 0: plc2 is not held in stop mode. 1: plc2 is held in stop mode. rxfres the rxfres bit controls the state of the receive fifo. setting this bit does not corrupt o ngoing receive cell transfer. that is, after the last byte of cell has been transferred, the receive fifo stops operation. the rxfres bit should be asserted at least 2.7 m s for single-phy mode and 10.8 m s for multi-phy mode. 0: the receive fifo operates normally. 1: all cells in the receive fifo is discarded. the receive fifo stops operation. txfres the txfres bit controls the state of the transmit fifo. setting this bit affects ongoing transmit cell transfer. that is, after the last byte of the cel l has been transferred, the cell is discarded. the txfres bit should be asserted at least 2.7 m s for single-phy mode and 10.8 m s for multi-phy mode. 0: the transmit fifo operates normally. 1: all cells in the transmit fifo is discarded. the transmit fifo st ops operation. oolde the oolde bit controls the out of lock detector. 0: the out of lock detector is disabled. 1: the out of lock detector is enabled. pllini the pllini bit controls the receive pll. 0: the receive pll operates normally. 1: the receive pll locks to reference clock refck regardless of other conditions. loocde the loocde bit controls the internal loss of optical carrier detector. 0: the loss of optical carrier detector is disabled. 1: the loss of optical carrier detector is enabled.
toshiba plc2 (TC35821F) specification 3- 5 autocse the autocse controls receive pll. 0: receive pll recovers clock from receive data or generates x8 clock from refck depending on the state of refsel. 1: receive pll usually recovers clock from receive data. when looc input is tied high or no signal transition is detected for 80 bit period or recovered clock deviates more than 244 ppm from reference clock, the receive pll automatically switches reference source from receive data to reference clock, as far as refsel is tied low. the receive pll loc ks to refck when refsel is tied high regardless of autocse bit.
toshiba plc2 (TC35821F) specification 3- 6 address : 01h type : r/w name : frms function : frame management 7 6 5 4 3 2 1 0 rsvd sdh j1 nodsbf noscbf nostf tc1 tc0 - 0 0 0 0 0 0 0 tc1, tc0 the tc1 and tc0 define the transmiss ion frame. tc1 tc0 frame 0 don't care sts-3c/stm-1 1 0 sts-1 1 1 sts-1/2 nostf the nostf bit selects stuff byte mode in sts-1 operation. 0: columns 30 and 59 are treated as fixed bytes in sts-1 operation. 1: columns 30 and 59 are treated as data bytes in sts-1 operation. noscbf the noscbf bit controls the scramble of transmit frame. 0: enable the scramble of transmit frame. 1: disable the scramble of transmit frame. nodsbf the nodsbf bit controls the descramble of receive frame. 0: enable the des cramble. 1: disable the descramble. j1 the j1 bit controls the j1 byte insertion of transmit frame. 0: the j1 byte of transmit frame is fixed to 00h. 1: 64 bytes character code stored in the transmit overhead memory is inserted to j1 bytes cyclically. sdh the sdh bit controls plc2 operation in terms of the difference between sonet and sdh. 0: plc2 operates in sonet mode. 1: plc2 operates in sdh mode. the difference of operation by plc2 between sonet/sdh is summarized below. sonet mode sdh mode c1 bytes in transmit frame 01h/02h/03h 01h/aah/aah ss bits of h1 byte in transmit frame ? 00 ? ? 10 ? l-rdi detection 5 consecutive frames 3 consecutive frames l-ais detection 5 consecutive frames 3 consecutive frames p-rdi detection 10 consecutive frames 3 consecutive frames (notice: p-ais detection criteria is 3 consecutive frames both for sonet and sdh.)
toshiba plc2 (TC35821F) specification 3- 7 address : 02h type : r/w name : cms1 function : cell management register 1 7 6 5 4 3 2 1 0 uac txf2 txf1 udf parity direct width utopia 0 0 0 0 0 0 0 0 utopia the utopia bit selects utopia mode. 0: single-phy 1: multi-phy width the width bit selects utopia i/f data bus width. 0: 8 bit data bus (for single-phy or multi-phy mode) 1: 16 bit data bus (for multi-phy mode only) direct the direct bit en ables direct status mode in multi-phy mode. 0: normal mode 1: direct status mode parity the parity bit selects parity mode. 0: odd parity 1: even parity udf the udf bit controls hec insertion in 16 bit cell format. 0: udf1 for hec 1: udf2 for hec txf2/txf1 the txf2/txf1 bits control the transmit fifo depth. txf2 txf1 fifo depth 0 0 4 cell deep 0 1 1 cell deep 1 0 2 cell deep 1 1 3 cell deep uac the uac bit controls idle/unassigned cell insertion. 0: when there is no cell in transmit fifo, idle cells are inserted into transmit frame. 1: when there is no cell in transmit fifo, unassigned cells with gfc field set to ? 0001 ? are inserted into transmit frame.
toshiba plc2 (TC35821F) specification 3- 8 address : 03h type : r/w name : cms2 function : cell management register 2 7 6 5 4 3 2 1 0 gfcen notc noscbc nohec norc nodsbc pass drop 0 0 0 0 0 0 0 0 drop the drop bit controls the cell delineation. 0: normal cell delineation as specified in itu-t i.432. 1: all received cells with header error are discarded. pass the pass bit controls the cell delineation. 0: normal cell delineation as specified in itu-t i.432. 1: all cells are passed, regardless of header error, toward atm layer. the cell delineation state transition is treated as specified in itu-t i.432. nodsbc the nodsb c bit controls descramble of received cell. 0: enable the payload descramble of received cell. 1: disable the payload descramble of received cell. norc the norc bit controls hec calculation option of received cell. 0: the coset polynomial, x 6 +x 4 +x 2 +1, is added(modulo 2) in hec calculation of received cell. 1: no polynomial is added nohec the nohec bit controls hec calculation of transmit cell. 0: enable calculation and insertion of hec of transmit cell and. 1: disable calculation and insertion of hec o f transmit cell. the hec field of transmit cell is as received from atm layer. noscbc the noscbc bit controls payload scramble of transmit cell. 0: enable the payload scramble of transmit cell. 1: disable the payload scramble of transmit cell. notc t he notc bit controls hec calculation option of transmit cell. 0: the coset polynomial, x 6 +x 4 +x 2 +1( ? 55h ? ), is added(modulo 2) in hec calculation of transmit cell. 1: no polynomial is added gfcen the gfcen bit controls limited gfc function. when gfc field of received cell indicates ? halt ? ( ? 1xxx ? ), plc2 can withhold the transmission of valid cells. when valid cells are withheld, idle cells are transmitted instead. 0: disable gfc control 1: enable gfc control
toshiba plc2 (TC35821F) specification 3- 9 address : 04h type : r/w name : loop function : loop mode select 7 6 5 4 3 2 1 0 rsvd rsvd loop2en loopl loopt loopu loop2 loop1 - - 0 0 0 0 0 0 loop1 the loop1 bit controls diagnostic loop back mode in lsi side. when this bit is set to one, txdop/m is connected to rxdip/m internally so that the transmit serial data is just returned as the receive serial data. 0: disable diagnostic loop back. 1: enable diagnostic loop back. loop2 the loop2 bit controls deep line loop back mode. when this bit is set to one, receive data input to rxd ip/m is put through rx serial to parallel converter and then to tx parallel to serial converter and output on txdop/m. 0: disable deep line loop back. 1: enable deep line loop back. loopu the loopu bit controls utopia loop back mode. when this bit is se t to one, transmit parallel data is looped back to the receive parallel input. 0 disable utopia loop back mode. 1: enable utopia loop back mode. loopt when the loopt bit is set to one, transmit clock of plc2 is synchronized with a clock extracted from received data. (loop timing mode) 0 disable loop timing mode. the transmit clock is synchronized with the reference clock, refck. 1: enable loop timing mode loopl the loopl bit controls the shallow line loop back mode. when this bit is set to on e, rxdip/m input is directly looped back to txdop/m. 0: disable shallow line loop back. 1: enable shallow line loop back. loop2en the loop2en bit determines whether the internal receive processor can set loop2 bit. 0: the internal receive proc essor cannot set or reset loop2 bit of loop register. 1: the internal receive processor can set and reset loop2 bit of loop register.
toshiba plc2 (TC35821F) specification 3- 10 address : 05h type : r/w name : fsync function : frame synchronization control 7 6 5 4 3 2 1 0 rsvd frwdf[2:0] rsvd bkwdf[2:0] - 1 0 0 - 0 1 0 frwdf[2:0] the frwd [2:0] field is set to the number ? n ? of forward protection of frame synchronization. when plc2 loses ? n ? times of frame synchronization in ? sync ? mode, plc2 moves to ? hunt ? mode. bkwdf[2:0] the bkwd [2:0] field is set to the number ? m ? of backward protection of frame synchronization. when plc2 catches ? m ? times of frame synchronization in ? hunt ? mode, plc2 moves to ? sync ? mode.
toshiba plc2 (TC35821F) specification 3- 11 address : 06h type : r/w name : csync function : cell synchronization mode 7 6 5 4 3 2 1 0 rsvd frwdc[2:0] rsvd bkwdc[2:0] - 1 1 1 - 1 1 1 frwdc[2:0] this field are set to the number ? n ? of forward protection of cell synchronization. when plc2 loses ? n ? times of cell synchronization in ? sync ? mode, plc2 moves to ? hunt ? mode. bkwdc[2:0] this field are set to the number ? m ? of backward protection of cell synchronization. when plc2 catches ? m ? times of cell synchronization in ? hunt ? mode, plc2 moves to ? sync ? mode.
toshiba plc2 (TC35821F) specification 3- 12 address : 07h type : r/w name : losct function : los control register 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rsvd rsvd rsvd extlos - - - - - - - 0 extlos the extlos bit controls whether loocp/m input affects los status. 0: when loocp/m input is high, rxdip/m input is fixed to low. 1: loocp/m input has no effect on plc2 los detection.
toshiba plc2 (TC35821F) specification 3- 13 address : 09h type : r/w name : j1posh function : horizontal position of j1 byte in transmit frame 7 6 5 4 3 2 1 0 rsvd j1h[6:0] - 0 0 0 0 0 1 1 address : 0ah type : r/w name : j1posv function : v ertical position of j1 byte of transmit frame 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd j1v[3:0] - - - - 0 0 1 1 j1h[6:0] this register is used only for diagnostic purpose. j1v[3:0] this register is used only for diagnostic purpose. note: the defa ult values of j1h and j1v correspond to pointer 0 on h1 and h2 bytes.
toshiba plc2 (TC35821F) specification 3- 14 address : 0bh type : r/w name : ciadr function : port address in multi-phy mode 7 6 5 4 3 2 1 0 rsvd rsvd rsvd addr[4:0] - - - 1 1 1 1 1 addr[4:0] when plc2 operates in multi-phy mode, addr [4:0] is used as physical port address of this device.
toshiba plc2 (TC35821F) specification 3- 15 address : 0ch type : r/w name : txalm1 function : alarm signal control 1 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd pais prdi lais lrdi - - - - 0 1 0 1 plc2 can send following alarm status automatically by setting this field. lrdi the lrdi bit controls automatic transmission of line rdi. 0: disable the automatic transmission 1: enable automatic transmission, when plc2 detects los, lof or lais. lais the lais bit controls automatic trans mission of line ais. 0: disable the automatic transmission 1: enable automatic transmission, when plc2 detects los or lof. prdi the prdi bit controls automatic transmission of path rdi. 0: disable the automatic transmission 1: enable automatic transmiss ion, when plc2 detects los, lof, lop, loc, lais or pais. pais the pais bit controls automatic transmission of path ais. 0: disable the automatic transmission 1: enable automatic transmission, when plc2 detects los, lof, lop, loc or lais. note: when aut omatic alarm transmission is used by setting this register, corresponding bit of txalm2 register must be set to zero.
toshiba plc2 (TC35821F) specification 3- 16 address : 0dh type : r/w name : txalm2 function : alarm signal control 2 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd pais prdi lais lrdi - - - - 0 0 0 0 plc2 can be forced to send following alarm signals by using this field. while each bit is set to one, plc2 continues to send corresponding alarm signal. lrdi the lrdi bit controls forced transmission of line rdi. 0: stop sending l-rdi 1: start sending l-rdi lais the lais bit controls forced transmission of line ais. 0: stop sending l-ais 1: start sending l-ais prdi the prdi bit controls forced transmission of path rdi. 0: stop sending p-rdi 1: start sending p-rdi pais the pais b it controls forced transmission of path ais. 0: stop sending p-ais 1: start sending p-ais note: when the forced alarm transmission is used by setting this register, corresponding bit of txalm1 register must be set to zero.
toshiba plc2 (TC35821F) specification 3- 17 address : 0fh type : r/w name : cms3 function : cell management register 3 7 6 5 4 3 2 1 0 tgfc[3:0] opt rsvd rsvd tgfcen 0 0 0 0 0 - - 0 tgfcen the tgfcen controls whether to insert tgfc[3:0] to gfc field of every assigned cell to transmit. 0: gfc field of assigned cell to transmit is not changed. 1: tgfc [3:0] is inserted to gfc field of every assigned cell to transmit. opt the opt bit controls gfc field of unassigned cell generated in plc2. 0: pattern ? 0001 ? is inserted to gfc field of unassigned cell generated in plc2 . 1: tgfc [3:0] is inserted to gfc field of unassigned cell generated in plc2. tgfc [3:0] when tgfcen is set, tgfc [3:0] is inserted to gfc field of every assigned cell to transmit.
toshiba plc2 (TC35821F) specification 3- 18 address : 10h type : r/w name : intsel1 function : interrupt control r egister of status1 7 6 5 4 3 2 1 0 b3 b2 b1 loc lop lof oof los 0 0 0 0 0 0 0 0 each bit of intsel1 register controls interrupt generation of corresponding bit of status1 register. los the los bit controls los interrupt. 0: disable an interrupt gene ration 1: enable an interrupt generation, when loss of signal status change is detected oof the oof bit controls oof interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when out of frame status change is detected lof the lo f bit controls lof interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when loss of frame status change is detected lop the lop bit controls lop interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when loss of pointer status change is detected loc the loc bit controls loc interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when loss of cell delineation status change is detected b1 the b1 bit controls b1 interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when b1-sbip8 error is detected b2 the b2 bit controls b2 interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when b2-lbip24 error is detected b3 the b3 b it controls b3 interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when b3-pbip8 error is detected
toshiba plc2 (TC35821F) specification 3- 19 address : 11h type : r/w name : intsel2 function : interrupt control register 2 7 6 5 4 3 2 1 0 c2 pfebe lfebe rsvd pais prdi lais lrdi 0 0 0 - 0 0 0 0 each bit of intsel2 register controls interrupt generation of corresponding bit of status2 register. lrdi the lrdi bit controls lrdi interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when lin e-rdi status changes lais the lais bit controls lais interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when line-ais status changes prdi the prdi bit controls prdi interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when path-rdi status changes pais the pais bit controls path ais interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when path-ais status changes lfebe the lfebe bit controls line febe interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when line-febe is detected pfebe the pfebe bit controls path febe interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when path-febe is detected c2 the c2 bit controls c2 interrupt. 0: disable an interrupt generation 1: enable an interrupt generation, when c2 error is detected
toshiba plc2 (TC35821F) specification 3- 20 address : 12h type : r/w name : intsel3 function : interrupt control register 3 7 6 5 4 3 2 1 0 looc gfc txool rxool uch coh pty rfov 0 0 0 0 0 0 0 0 each bit of intsel3 register controls interrupt generation of corresponding bit of status3 register. rfov 0: disable an interrupt generation. 1: enable an interrupt generation, when receive fifo overflow is detected. pty 0: disable an interrupt generation. 1: enable an interrupt generation, when parity error is detected. coh 0: disable an interrupt generation. 1: enable an interrupt generation, when plc2 corrected a single bit header error. uch 0: disable an interrupt ge neration. 1: enable an interrupt generation, when plc2 detects uncorrectable header error. rxool 0: disable an interrupt generation. 1: enable an interrupt generation, when the receive pll gets out of lock. txool 0: disable an interrupt generation. 1: enable an interrupt generation, when the transmit pll gets out of lock. gfc 0: disable an interrupt generation. 1: enable an interrupt generation, when plc2 detects a command in gfc field of received cell. looc 0: disable an interrupt generation. 1: e nable an interrupt generation, when plc2 detects logical high level at loocp/m input.
toshiba plc2 (TC35821F) specification 3- 21 address : 15h type : r/w name : intind1 function : interrupt status register 1 7 6 5 4 3 2 1 0 b3 b2 b1 loc lop lof oof los 0 0 0 0 0 0 0 0 intind1 register indicates interrupt status, when plc2 generates an interrupt. each bit of this register is one, when corresponding status of status1 register has any transition or transition to 1. the host cpu can find interrupt cause by reading this register, when interrupt is occurred. each bit is cleared when 0 is written by the host cpu. los 0: indicates no transition in los status. 1: indicates transition in los status. oof 0: indicates no transition in oof status. 1: indicates transition in oof status. lof 0: indicates no transition in lof status. 1: indicates transition in lof status. lop 0: indicates no transition in lop status. 1: indicates transition in lop status. loc 0: indicates no transition in loc status. 1: indicates transition in loc status. b1 0: indicate s no transition to 1 in b1 status. 1: indicates transition to 1 in b1 status. b2 0: indicates no transition to 1 in b2 status. 1: indicates transition to 1 in b2 status. b3 0: indicates no transition to 1 in b3 status. 1: indicates transition to 1 in b3 status.
toshiba plc2 (TC35821F) specification 3- 22 address : 16h type : r/w name : intind2 function : interrupt status register 2 7 6 5 4 3 2 1 0 c2 pfebe lfebe rsvd pais prdi lais lrdi 0 0 0 - 0 0 0 0 intind2 register indicates interrupt status, when plc2 generates an interrupt. each bit of this register is one, when corresponding status of status2 register has any transition or transition to 1. the host cpu can find interrupt cause by reading this register, when interrupt is occurred. each bit is cleared when 0 is written by the host cpu. lrdi 0: indicates no transition in lrdi status. 1: indicates transition in lrdi status. lais 0: indicates no transition in lais status. 1: indicates transition in lais status. prdi 0: indicates no transition in prdi status. 1: indicates transition in prdi status. pais 0: indicates no transition in pais status. 1: indicates transition in pais status. lfebe 0: indicates no transition to 1 in lfebe status. 1: indicates transition to 1 in lfebe status. pfebe 0: indicates no transition to 1 in pfebe stat us. 1: indicates transition to 1 in pfebe status. c2 0: indicates no transition to 1 in c2 status. 1: indicates transition to 1 in c2 status.
toshiba plc2 (TC35821F) specification 3- 23 address : 17h type : r/w name : intind3 function : interrupt status register 3 7 6 5 4 3 2 1 0 looc gfc txool rxool uch coh pty rfov 0 0 0 0 0 0 0 0 intind3 register indicates interrupt status, when plc2 generates an interrupt. each bit of this register is one, when corresponding status of status3 register has any transition or transition to 1. the host cpu can find interrupt cause by reading this register, when interrupt is occurred. each bit is cleared when 0 is written by the host cpu. rfov 0: indicates no transition to 1 in rfov status. 1: indicates transition to 1 in rfov status. coh 0: indicates no tra nsition to 1 in coh status. 1: indicates transition to 1 in coh status. uch 0: indicates no transition to 1 in uch status. 1: indicates transition to 1 in uch status. rxool 0: indicates no transition in rxool status. 1: indicates transition in rxool stat us. txool 0: indicates no transition in txool status. 1: indicates transition in txool status. gfc 0: indicates no transition to 1 in gfc status. 1: indicates transition to 1 in gfc status. looc 0: indicates no transition to 1 in looc status. 1: indicat es transition to 1 in looc status.
toshiba plc2 (TC35821F) specification 3- 24 address : 1ah type : r name : status1 function : receive status register 7 6 5 4 3 2 1 0 b3 b2 b1 loc lop lof oof los 0 0 0 0 0 0 0 0 los this bit indicates status of loss of signal. when los is detected, plc2 set s this field to one. when los condition disappears, this bit is cleared. oof this bit indicates status of out of frame. when oof is detected, plc2 sets this bit to one. when oof condition disappears, this bit is cleared. lof this bit indicates statu s of loss of frame. when lof is detected, plc2 sets this bit to one. when lof condition disappears, this bit is cleared. lop this bit indicates status of loss of pointer. when lop is detected, plc2 sets this bit to one. when lop condition disappears, this bit is cleared. loc this bit indicates status of loss of cell delineation. when loc is detected, plc2 sets this bit to one. when loc condition disappears, this bit is cleared. b1 this bit indicates b1-sbip8 error of receiving frame. when b1-sbip8 error is detected, plc2 sets this bit to one. when b1-sbip8 error is not detected in next frame, this bit is cleared. b2 this bit indicates b2-lbip24 error of receiving frame. when b2-lbip24 error is detected, plc2 sets this bit to one. when b2-lbip2 4 error is not detected in next frame, this bit is cleared. b3 this bit indicates b3-pbip8 error of receiving frame. when b3-pbip8 error is detected, plc2 sets this bit to one. when b3-pbip8 error is not detected in next frame, this bit is cleared. note: this register indicates current status. it is not cleared when accessed by host cpu.
toshiba plc2 (TC35821F) specification 3- 25 address : 1bh type : r name : status2 function : alarm status register 7 6 5 4 3 2 1 0 c2 pfebe lfebe rsvd pais prdi lais lrdi 0 0 0 - 0 0 0 0 lrdi this bit ind icates l-rdi state of receiving frame. when l-rdi is judged to be set, plc2 sets this bit to one. when l-rdi is judged to be reset, this bit is cleared. lais this bit indicates l-ais state of receiving frame. when l-ais is judged to be set , plc2 sets this bit to one. when l-ais is judged to be reset, this bit is cleared. prdi this bit indicates p-rdi state of receiving frame. when p-rdi is judged to be set, plc2 sets this bit to one. when p-rdi is judged to be reset, this bit is cleared. pais t his bit indicates p-ais state of receiving frame. when p-ais is judged to be set, plc2 sets this bit to one. when p-ais is judged to be reset, this bit is cleared. lfebe this bit indicates l-febe state of receiving frame. when received l-febe is non-ze ro, plc2 sets this bit to one. when received l-febe is zero, this bit is cleared. pfebe this bit indicates p-febe state of receiving frame. when received p-febe is non-zero, plc2 sets this bit to one. when received p-febe is zero, this bit is cleared. c2 this bit indicates c2 error of receiving frame. when c2 error is detected, plc2 sets this bit to one. when c2 error is not detected in next frame or later, this bit is cleared. note: this register indicates current status. it is not cleared when a ccessed by host cpu.
toshiba plc2 (TC35821F) specification 3- 26 address : 1ch type : r name : status3 function : plc2 internal status 7 6 5 4 3 2 1 0 looc gfc txool rxool uch coh pty rfov 0 0 0 0 0 0 0 0 rfov when the receive fifo overflow is detected, plc2 sets this bit to one. when the re ceive fifo overflow is cleared, plc2 sets this bit to zero. pty when plc2 detects parity error in received cell at transmit side cell interface, this bit is set to one. when plc2 detects normal parity, this bit is cleared. coh when plc2 corrected a single bit header error in a receiving cell, this bit is set to one. when the following cell has normal header or uncorrectable header, this bit is set to zero. uch when plc2 detects uncorrectable header error in receiving cell, this bit is set to one . when the allowing cell has normal header or correctable single bit error, this bit is set to zero. rxool when the receive pll is out of lock, this bit is set to one. when the receive pll is in lock, this bit is set to zero. txool when the transmi t pll is out of lock, this bit is set to one. when the transmit pll is in lock, this bit is set to zero. gfc when plc2 detects gfc commands (1xxx, x1xx or xx1x) in gfc field of received cell, plc2 sets this bit to one. when plc2 detects "000x" in gfc field of received cell, plc2 sets this bit to zero. looc when plc2 detects logical high level at loocp/m input, plc2 sets this bit to one. when plc2 detects logical low level at loocp/m input, plc2 sets this bit to zero. note: this register indicate s current status. it is not cleared when accessed by host cpu.
toshiba plc2 (TC35821F) specification 3- 27 address : 1fh type : r name : rgfc function : receive gfc status 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rgfc[3:0] - - - - 0 0 0 0 rgfc[3:0] rgfc[3:0] indicates gfc field of received cell. it is updated when gfc field of the current cell is different from the preceding one.
toshiba plc2 (TC35821F) specification 3- 28 address : 20h type : r name : b1errl function : b1-sbip8 error counter [7:0] 7 6 5 4 3 2 1 0 b1err[7:0] 0 0 0 0 0 0 0 0 address : 21h type : r name : b1errh function : b1-sbip8 error counter [15:8] 7 6 5 4 3 2 1 0 b1err[15:8] 0 0 0 0 0 0 0 0 this register indicates b1-sbip8 error count. when b1 bit of fcupd register is set to one, this counter is updated within 150 m s and b1 bit is automatically cleared. the value of this counter is kept until next update request. the b1-sbip8 count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 29 address : 22h type : r name : b2errl function : b2-lbip24 error counter[7:0] 7 6 5 4 3 2 1 0 b2err[7:0] 0 0 0 0 0 0 0 0 address : 23h type : r name : b2errm function : b2-lbip24 error counter[15:8] 7 6 5 4 3 2 1 0 b2err[15:8] 0 0 0 0 0 0 0 0 address : 24h type : r name : b2errh function : b2-lbip24 error counter[19:16] 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd b2err[19:16] - - - - 0 0 0 0 this register indicates b2-lbip24 error count. when b2 bit of fcupd register is set to one, this counter is updated within 150 m s and b2 bit is automatically cleared. the value of this counter is kept until next update request. the b2-lbip24 count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 30 address : 25h type : r name : b3errl function : b3-pbip8 error counter[7:0] 7 6 5 4 3 2 1 0 b3err[7:0] 0 0 0 0 0 0 0 0 address : 26h type : r name : b3errh function : b3-pbip8 error counter[15:8] 7 6 5 4 3 2 1 0 b3err[15:8] 0 0 0 0 0 0 0 0 this register indicates b3-pbip8 error count. when b3 bit of fcupd register is set to one, this counter is updated within 150 m s and b3 bit is automatically cleared. the value of this counter is kept until next update request. the b3-pbip8 count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 31 address : 27h type : r name : lfebel function : receive lfebe counter[7:0] 7 6 5 4 3 2 1 0 lfebe[7:0] 0 0 0 0 0 0 0 0 address : 28h type : r name : lfebem function : receive lfebe counter[15 :8] 7 6 5 4 3 2 1 0 lfebe[15:8] 0 0 0 0 0 0 0 0 address : 29h type : r name : lfebeh function : receive lfebe counter[19:16] 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd lfebe[19:16] - - - - 0 0 0 0 this register indicates receive l-febe count. when lfebe bit of fcupd register is set to one, this counter is updated within 150 m s and lfebe bit is automatically cleared. the value of this counter is kept until next update request. the l-febe count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 32 address : 2ah type : r name : pfebel function : receive pfebe counter[7:0] 7 6 5 4 3 2 1 0 pfebe[7:0] 0 0 0 0 0 0 0 0 address : 2bh type : r name : pfebeh function : receive pfebe counter[15:8] 7 6 5 4 3 2 1 0 pfebe[15:8] 0 0 0 0 0 0 0 0 this register indicates received p-febe count. when pfebe bit of fcupd register is set to one, this counter is updated within 150 m s and pfebe bit is automatically cleared. the value of this counter is kept until next update request. the p-febe count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 33 address : 2fh type : r/w name : fcupd function : error counter update flag 7 6 5 4 3 2 1 0 rsvd rsvd rsvd pfebe lfebe b3 b2 b1 - - - 0 0 0 0 0 b1 update control of b1errl/h registers 0: no operation 1: internal b1-sbip8 error count is loaded into b1errl/h registers within 150 m s and b1 bit is cleared automatically. b2 update control of b2errl/m/h registers 0: no operation 1: internal b2-lbip24 error count is loaded into b2errl/m/h registers within 150 m s and b2 bit is cleared automatically. b3 update control of b3errl/h registers 0: no operation 1: internal b3-pbip8 error count is loaded into b3errl/h registers within 150 m s and b3 bit is cleared automatically. lfebe update control of lfebel/m/h registers 0: no operation 1: internal lfebe count is loaded into lfebel/m/h registers within 150 m s and lfebe bit is cleared automatically. pfebe update control of pfebel/h registers. 0: no operation 1: internal pfebe count is loaded into pfebel/h registers within 150 m s and pfebe bit is cleared automatically.
toshiba plc2 (TC35821F) specification 3- 34 address : 30h type : r name : coher function : corrected cell header error counter 7 6 5 4 3 2 1 0 coher[7:0] 0 0 0 0 0 0 0 0 the coher register indicates count of corrected header error. this register is cleared automatically on read. the error count stops when the count reach 255 (10) . when header error correction is disabled, coher register has no meaning.
toshiba plc2 (TC35821F) specification 3- 35 address : 31h type : r name : ucher function : uncorrected cell header error counter 7 6 5 4 3 2 1 0 ucher[7:0] 0 0 0 0 0 0 0 0 the ucher register indicates count of uncorrected header error. this register is cleared automatically on read. the error count stops when the count reach 255 (10) .
toshiba plc2 (TC35821F) specification 3- 36 address : 32h type : r name : rxccl function : receive valid cell counter[7:0] 7 6 5 4 3 2 1 0 rxcc[7:0] 0 0 0 0 0 0 0 0 address : 33h type : r name : rxccm function : receive valid cell counter[15:8] 7 6 5 4 3 2 1 0 rxcc[15:8] 0 0 0 0 0 0 0 0 address : 34h type : r name : rxcch function : receive valid cell counter[19:16 ] 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rxcc[19:16] - - - - 0 0 0 0 this register indicates received valid cell count. when rxcc bit of ccupd register is set to one, this counter is updated within 1 m s. the value of this counter is kept until next update. the receive valid cell count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 37 address : 35h type : r name : txccl function : transmit valid cell counter[7:0] 7 6 5 4 3 2 1 0 txcc[7:0] 0 0 0 0 0 0 0 0 address : 36h type : r name : txccm function : transmit va lid cell counter[15:8] 7 6 5 4 3 2 1 0 txcc[15:8] 0 0 0 0 0 0 0 0 address : 37h type : r name : txcch function : transmit valid cell counter[19:16] 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd txcc[19:16] - - - - 0 0 0 0 this register indicates transmit valid cell count. when txcc bit of ccupd register is set to one, this counter is updated within 1 m s. the value of this register is kept until next update request by setting txcc bit to one. the transmit valid cell count stops when 4 msb bits reach '1111'.
toshiba plc2 (TC35821F) specification 3- 38 address : 3fh type : r/w name : ccupd function : cell counter update flag 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rsvd rsvd txcc rxcc - - - - - - 0 0 rxcc update control of rxccl/m/h registers 0: no operation 1: internal received valid cell count is loaded into rxccl/m/h registers within 1 m s and rxcc bit is cleared automatically. txcc update control of txccl/m/h registers 0: no operation 1: internal transmit valid cell count is loaded into txccl/m/h registers within 1 m s and txcc bit is clear ed automatically.
toshiba plc2 (TC35821F) specification 3- 39 address : 40h type : r/w name : memal function : memory a ddress r egister [7:0] 7 6 5 4 3 2 1 0 memal[7:0] 0 0 0 0 0 0 0 0 address : 41h type : r/w name : memah function : memory a ddress r egister [3:0] 7 6 5 4 3 2 1 0 memwr rsvd rsvd memah[4:0] 0 - - 0 0 0 0 0 address : 42h type : r/w name : memd function : data c ontrol r egister 7 6 5 4 3 2 1 0 memd[7:0] 0 0 0 0 0 0 0 0 these registers is used to access the plc2 internal memory. for access, follow the steps below. read operation (1) set address to memah register. (2) set address to memal register. (3) wait for tbd nsec. (4) read memd register. for read access to consecutive addresses, follow steps (2) to (4). write operation (1) set address to memah register with memwr set high. (2) set address to memal. (3) write the value to memd register. for write access to consecutive addresses, follow steps (2) to (3).
toshiba plc2 (TC35821F) specification 3- 40 address mapping is as follows. 0x0000-0x07ff rx firmware 0x0800-0x0bff tx firmware 0x0c00-0x0cff rx ov erhead memory 0x0d00-0x0dff tx overhead memory 0x0e00-0x0eff rx cell fifo 0x0f00-0x0fff tx cell fifo 0x1000-0x10ff rx internal registers 0x1100-0x11ff tx internal registers field assignment in rx/tx overhead memory is shown below. address is increased from upper left corner to rightward and then downward. for instance, the address of g1 byte in rx overhead memory is 0x0c39. the soh/poh bytes are extracted from received data and stored in rx overhead memory every frame. other area in rx overhead memory is used as working storage by internal processor. in tx overhead memory, a1, a2, b1, b3, c1, h1, h2, h3, b2, k2, h4, z2, j1, b3, c2, g1 and h4 bytes are automatically updated by internal processor while other bytes are filled with zero automatically . a1 a1 a1 a2 a2 a2 c1 c1 c1 j1 b1 - - e1 - - f1 - - b3 d1 - - d2 - - d3 - - c2 h1 h1 h1 h2 h2 h2 h3 h3 h3 g1 b2 b2 b2 k1 - - k2 - - f2 d4 - - d5 - - d6 - - h4 d7 - - d8 - - d9 - - z3 d10 - - d11 - - d12 - - z4 z1 z1 z1 z2 z2 z2 e2 - - z5 field assignment of rx/tx overhead memory
toshiba plc2 (TC35821F) specification 3- 41 address : 50h type : r/w name : tsmod1 function : test m ode r egister 1 7 6 5 4 3 2 1 0 rfhlt date clke looce txcoe notp norp reg 0 0 0 0 0 0 0 0 this register is used for diagnostic or lsi internal testing purpose. usually this register should be set to zero. reg register operation mode 0: write to read only register is not allowed. 1: write to read only registers is allowed. norp receive processor operation mode 0: normal operation 1: stop receive processor notp transmit processor operation mode 0: normal operation 1: stop transmit pr ocessor txcoe the txcoe bit controls pecl buffer of txcop/m. 0: enables pecl output buffer of txcop/m 1: disables pecl output buffer of txcop/m looce the looce bit controls pecl buffer of loocp/m. 0: enables pecl input buffer of loocp/m 1: disables pec l input buffer of loocp/m clke the clke bit controls pecl buffer of rxcip/m and txcip/m. 0: enables pecl input buffer of rxcip/m and txcip/m 1: disables pecl input buffer of rxcip/m and txcip/m date the date bit controls pecl buffer of rxdip/m and txdo p/m. 0: enables pecl input buffer of rxdip/m and txdop/m. 1: disables pecl input buffer of rxdip/m and txdop/m. rfhlt the rfhlt controls receive cell fifo. this bit is used for evaluation only. 0: receive cell fifo is in normal operation. 1: when rfhlt b it is set high, receive cell fifo stops immediately.
toshiba plc2 (TC35821F) specification 3- 42 address : 51h type : r/w name : tsmod2 function : test m ode r egister 2 7 6 5 4 3 2 1 0 rct dwld vc rsvd ooltst tstck clksel monsel 0 0 0 - 0 0 0 0 this register is used for diagnostic or lsi internal testing purpose. usually this register should be set to zero. monsel monsel is used for production test only. clksel the clksel determines the output on rxck pin.. 0: the receive parallel clock is output from rxck pin. 1: the transmit parallel c lock is output from rxck pin. tstck the tstck bit is used for evaluation only. 0: refck is divided and distributed to plc2 digital part when loopu bit is set high. 1: refck is always directly distributed to plc2 digital part when loopu bit is set high. ooltst the ooltst bit is used for evaluation only. 0: the out of lock detector is enabled only when rcksel is tied high. 1: the out of lock detector is enabled regardless of rcksel. vc c the vc bit controls frame format. this bit can be ignored in norm al operation. 0: vc4 is assumed in sts-3c/stm-1 frame. 1: vc3 is assumed in sts-3c/stm-1 frame. dwld the dwld bit is used for evaluation only. 0: normal operation 1: the download mode is activated. rct the rct bit is used for evaluation only. 0: the ce ll delineation is enabled when oof is cleared. 1: the cell delineation is always enabled.
toshiba plc2 (TC35821F) specification 3- 43 address : 52h type : r/w name : tsgen function : test m ode r egister 3 7 6 5 4 3 2 1 0 rsvd rsvd heci loci bipi lopi oofi losi - - 0 0 0 0 0 0 this register is used for diagnostic or lsi internal testing purpose. usually this register should be set to zero. losi transmit frame option 1 0: normal operation 1: transmit all ? 00h ? data oofi transmit frame option 2 0: normal operation 1: a1/a2 bytes of transmit fr ame are set to ? 00h ? lopi transmit frame option 3 0: normal operation 1: h1/h2 pointer of transmit data is set to invalid value bipi transmit frame option 4 0: normal operation 1: b1/b2/b3 bytes of transmit frame are bit-reversed. loci transmit frame option 5 0: normal operation 1: hec byte of transmit cells are bit-reversed. heci transmit frame option 6 0: normal operation 1: the lsb of hec byte of transmit cells are bit-reversed.
toshiba plc2 (TC35821F) specification 3- 44 address : 53h type : r/w name : lfebei function : test m ode r egister 4 7 6 5 4 3 2 1 0 rsvd rsvd lfebee lfebei[4:0] - - 0 0 0 0 0 0 this register is used for diagnostic or lsi internal testing purpose. usually this register should be set to zero. lfebei[4:0] set this field with the value to send as lfebe lfebee transmit frame option 7 0: normal operation 1: transmit the value of lfebei[4:0] instead of calculated lfebe
toshiba plc2 (TC35821F) specification 3- 45 address : 54h type : r/w name : pfebei function : test m ode r egister 5 7 6 5 4 3 2 1 0 rsvd rsvd rsvd pfebee pfebei[3:0] - - - 0 0 0 0 0 this register is used for diagnostic or lsi internal testing purpose. usually this register should be set to zero. pfebei[3:0] set this field with the value to send as pfebe pfebee transmit frame option 8 0: normal operation 1: transmit the value of pfeb ei[3:0] instead of calculated pfebe
toshiba plc2 (TC35821F) specification 4- 1 4. receive functions 4.1 receive clock 4.1.1 external clock mode when rcksel pin is tied low, externally provided clock, rxcip/m is and the clock recovery pll is deactivated. usually rxdip/m is sampled at the rising edge of rxcip/m. optionally rxdip/m can be sampled at the falling edge of rxcip/m by tying dlysel pin to high. 4.1.2 on-chip clock recovery mode when rcksel pin is tied high, the receive side of plc2 operates on internally recovered clock. the recovered clock is divided by 8 and compared with the reference clock refck. when the recovered clock frequency is out of 244ppm range of refck, the clock recovery pll is judged to be out of lock and rxool bit of status1 register is set. the clock recovery pll automatically switches to refck for reference source to keep oscillation in the vicinity of 155.52mhz (for sts-3 /stm- 1 ) , 51.84mhz (for sts-1) or 25.92mhz (for sts-1/2) when the recovered clock is out of 244ppm range of refck or 80 bits period of no transition in receive data is detected or loocp/m input is tied high and autocse bit in cont register is set high. during the period when the clock recovery pll locks to refck, the data transition detector keeps sampling the receive data. when the data transition detector detects at least one data transition in 80 bits period and loocp/m input is tied low and the clock recovery pll generates clock at frequency in 244ppm range of refck , the clock recovery pll switches back to receive data for reference. above is typical case. there are many options available. (1) 80bit transition detector can be masked by setting zero to loocde bit of cont register (address: 00 h). (2) external loocp/m input can be masked by setting one to looce bit of tsmod 1 register (address: 50 h). (3) automatic switching between clock recovery mode in which rx pll locks to receive data and reference mode in which rx pll locks to refck can be cancelled by setting zero to autocse bit of cont register (address:00h). (4) 244 ppm detector can be masked by setting zero to oolde bit of cont register (address: 00 h). (5) when autocse bit is zero, rx pll operation mode can be controlled by external pin refsel and pllini bit of cont register. the operation is as follows. refsel=1 or pllini=1 : rx pll locks to refck. otherwise: rx pll locks to receive data. (6) even when autocse is set to one, rx pll can be forced into reference mode by making refsel=1 or pllini=1. (notice: stop bit in pcont register must be cleared to let autocse effective.)
toshiba plc2 (TC35821F) specification 4- 2 4.2 frame synchronization (1) sts-3c(stm-1) hunt the framing patt ern of 3 consecutive a1's followed by 3 consecutive a2's is searched. when the framing pattern is found, framing operation enters presync mode. presync when one more expected framing pattern is with 2430 byte interval, the framing operation enters sync mode. sync the framing pattern is checked every frame. if invalid framing patterns are found in 4 consecutive frames, oof is set in status1 register and the framing operation enters hunt mode. (2)sts-1, sts-1/2 hunt the framing pattern of one a1 fol lowed by one a2 is searched. when the framing pattern is found, framing operation enters presync mode. presync when one more framing pattern is found with 810 byte interval, the framing operation enters sync mode. sync the framing pattern is checked every frame. if invalid framing patterns are found in 4 consecutive frames, oof is set in status1 register and the framing operation enters hunt mode. 4.3 frame descrambling the received frame data is descrambled by quasi random pattern generated by the polynomial 1+ x 6 +x 7 . the first line of soh ( i.e. a1, a2, c1 bytes) is excluded from the descramble operation. the descramble operation starts from the byte following the last c1 byte with initial data for the generating polynomial '1111111.' the descramble operation can optionally be disabled by setting 1 to nodsbf bit in frmsel register. 4.4 bip/febe count
toshiba plc2 (TC35821F) specification 4- 3 (1) section bip-8 section bip-8 is calculated over the entire area of each received frame before descrambling based on 8 bits interleaved parity calculation using even parity. the calculated bip-8 code is compared with the b1 byte of the following frame bit by bit. the differences indicates the section level bit errors. the bit errors are counted and accumulated in a internal counter frame by frame. this counter value can be accessed via b1errl/h register. the host cpu is required to read them every one second for performance monitoring. before reading them, host cpu should set 1 to b1 bit in fcupd register. in about one frame time , b1errl/h are updated and b1 bit in fcupd register is automatically cleared. section bip-8 counter stops counting when 4 msb bits become ? 1111 ? . (2) line bip-24 line bip-24 is calculated over the entire area of each frame after descrambling except for the first to third rows of soh based on 24 bits interleaved parity calculation using even parity. the calculated bip-24 code is compared with the three b2 bytes of the following frame bit by bit. the differences indicates the line level bit errors. the bit errors are counted and the count is inserted to the z2 byte of the transmit soh as line febe, as well as accumulated in a internal counter frame by frame. this counter value can be accessed via b2errl/m/h register. the host cpu is required to read them every one second for performance monitoring. before reading them, host cpu should set 1 to b2 bit in fcupd register. in about one frame time , b2errl/m/h are updated and b2 bit in fcupd register is automatically cleared. line bip-24 counter stops counting when 4 msb bits become ? 1111 ? . (3) path bip-8 path bip-8 is calculated over the entire area of each vc4 (or spe for sts-1) after descrambling based on 8 bits interleaved parity calculation using even parity. the calculated bip-8 code is compared with the b3 byte of the following frame bit by bit. the differences indicates the path level bit errors. the bit errors are counted and inserted to the g1 byte of the transmit poh as path febe, as well as accumulated in a internal counter frame by frame. this counter value can be accessed via b3errl/h register. the host cpu is required to read them every one second for performance monitoring. before reading them, host cpu should set 1 to b3 bit in fcupd register. in about one frame time , b3errl/h are updated and b3 bit in fcupd register is automatically cleared. path bip-8 counter stops counting when 4 msb bits become ? 1111 ? . (4) line febe line febe value of every received frame is accumulated in line febe counter. this counter value can be accessed via lfebel/m/h registers. the host cpu is required to read them every one second for performance monitoring. before reading them, host cpu should set 1 to lfebe bit in fcupd register. in about one frame time , lfebel/m/h are updated and febe bit in fcupd register is automatically cleared. line febe counter stops counting when 4 msb bits become ? 1111 ? .
toshiba plc2 (TC35821F) specification 4- 4 (5) path febe path febe value of every received frame is accumulated in path febe counter. this counter value can be accessed via pfebel/h registers. the host cpu is required to read them every one second for performance monitoring. before reading them, host cpu should set 1 to pfebe bit in fcupd register. in about one frame time , pfebel/h are updated and febe bit in fcupd register is automatically cleared. path febe counter stops counting when 4 msb bits become ? 1111 ? . 4.5 pointer operation the first h1 and the first h2 in soh are used to locate j1 byte of vc4 ( or spe for sts-1). the second and third h1 bytes have fixed value of 93h. the second and third h2 bytes have fixed value of ffh. the second and third h1/h2 bytes are not used for pointer operation. figure 4.1 shows the field assignment of the first h1/h2 bytes. h1 h2 ndf fixed pointer n n n n s s i d i d i d i d i d figure 4.1 field assignment of h1/h2 bytes. ndf has two values; nnnn=0110 indicates no change in the pointer value while nnnn=1001 indicates change in pointer value. fixed field is usually ignored. the normal value depends on whether the receive data is sonet type or sdh type. when the receive data is sonet type, ss=00. when the receive data is sdh type, ss=10. when h1 and h2 bytes should carry pais, ss=11. pointer usually locates j1 byte. the pointer value is a binary number with a range from 0 to 782, which indicates the offset between the third h3 and the j1 byte of vc4. soh bytes are not counted in the offset. for example, a pointer value of 0 indicates the j1 byte immediately follows the third h3 byte, whereas an offset of 522 indicates that the j1 byte immediately follows the third c1 byte. pointer field is also used to indicate stuff operation. if the pointer value of the current frame equals the pointer value of the previous frame with 3 or more i bits inverted, it is the positive stuff indication. if the pointer value of the current frame equals the pointer value of the previous frame with 3 or more d bits inverted, it is the negative stuff indication. there are 6 cases for the pointer operation. (1) new data flag active normally ndf has value of 0110. if ndf=1001 or 0001 or 1101 or 1011 or 1000, new data flag indication is considered active. the coincident pointer value replaces the previous pointer value as far as the pointer value is normal, that is in the range from 0 to 782. the updated pointer value takes effect from the first j1 byte
toshiba plc2 (TC35821F) specification 4- 5 following h1, h2. when new data flag is considered active, the positive stuff indication and the negative stuff indication are ignored. (2) positive stuff operation when following conditions are met, positive stuff operation is executed. 1) three or more i bits are inverted. 2) 2 or less d bits, if at all, are inverted. 3) new data flag indication is not active. 4) the pointer is not updated in preceding three frames. in positive stuff operation, three bytes ( one byte in sts-1) following the third h3 byte is ignored as payload only in the current frame . the pointer value is incremented by one. (3) negative stuff operation when following conditions are met, negative stuff operation is executed. 1) three or more d bits are inverted. 2) 2 or less i bits, if at all, are inverted. 3) new data flag indication is not active. 4) the pointer is not updated in preceding three frames. in negative stuff operation, three h3 bytes ( one h3 byte for sts-1) are included as part of vc4 ( or spe in sts-1 ) only in the current frame. the pointer value is reduced by one. (4) 3 consecutive, consistent new value when consistent, normal ( in the range of 0 to 782 ) new pointer value is received for three consecutive frames, the pointer value replaces the previous value. (5) detection of path ais if all ones pattern is detected in h1 and h2 for three consecutive frames, pais bit is set in status1 register. pais bit is reset when valid pointers are detected for three consecutive frames . in sdh mode, pais is also reset when lop is detected. (6) lop detection the lop bit in status1 register is set when a valid pointer is not found for 8 consecutive frames or when 8 consecutive ndf with the value of 1001 are detected. the lop bit is reset when a valid pointer with normal ndf is detected for three consecutive frames or all ones pattern (that is pais) is detected in h1 and h2 for three consecutive frames. 4.6 detection of irregular state (1) los : loss of signal the receive data is sampled by refck clock and compared with the data sample d one cycle before. the los is declared and los bit in status1 register is set when one of following two conditions is met for 20 m sec :
toshiba plc2 (TC35821F) specification 4- 6 1. no data transition is observed at rxdip/m input. 2. extlos bit in losct register is set high and loocp/m input is logical high. los bit is cleared when two consecutive valid frame alignment patterns (a1, a2) have been received without no los set condition (20 m sec of no data transition or loocp/m input high) in between. (2) oof : out of frame framing operation se t oof bit in status1 register when four consecutive invalid frame alignment patterns (a1, a2) have been received and reset oof bit when two consecutive valid frame alignment pattern have been detected. (3) lof : loss of frame the receive processor checks oof status every frame. when oof is set for 24 consecutive frames ( i.e. for 3 msec), lof bit in status1 register is set. if oof is found reset for 24 consecutive frames, the lof bit is cleared. (4) lop : loss of pointer the lop bit in status1 register is set when a valid pointer is not found for 8 consecutive frames or when 8 consecutive ndf with the value of 1001 are detected. the lop bit is reset when a valid pointer with normal ndf is detected for three consecutive frames or all ones pattern (that is pais) is detected in h1 and h2 for three consecutive frames. (5) loc : loss of cell delineation the loc bit in status1 register is set when the cell delineation is in hunt state. the loc bit is reset when the cell delineation enters sync state. for the cell delineation, refer to section 4.8. 4.7 detection of alarm signals the receive processor checks the k2 and g1 bytes to detect line ais, line rdi, path rdi along with h1/h2 bytes to detect path ais. when one of these alarms are detected, a corresponding bit in status2 register is set. the alarm detection criteria is different for sonet and sdh. for sdh mode operation, sdh bit of frms register (address:0 1 h) should be set to one. (1) lais : line alarm indication signal when a 111 binary pattern is detected in bits 6,7,8 of k2 byte for five consecutive frames (sonet mode) or three consecutive frames (sdh mode), lais is declared and lais bit of status2 register is set high. lais is removed when any pattern other than 111 is detected in bits 6,7,8 of k2 bytes for five consecutive frames (sonet mode) or three consecutive frames (sdh mode).
toshiba plc2 (TC35821F) specification 4- 7 (2) lrdi : line remote defect indication when a 110 binary pattern is detected in bits 6,7,8 of k2 byte for five consecutive frames (sonet mode) or three consecutive frames (sdh mode), lrdi is declared and lrdi bit of status2 register is set high. lrdi is removed when any pattern other than 110 is detected in bits 6,7,8 of k2 bytes for five consecutive frames (sonet mode) or three consecutive frames (sdh mode). (3) pais : path alarm indication signal when all 1 binary pattern is detected in h1/h2 bytes for three consecutive frames, pais is declared and pais bit of status2 register is set high. pais is removed when a valid pointer with ndf set to '1001' is detected or when the same valid pointer with normal ndf is detected in three consecutive frames. in sdh mode, pais is also removed when lop is detected. (4) prdi : path remote defect indication when bit 5 of g1 byte is detected to be 1 for ten consecutive frames (sonet mode) or three consecutive frames (sdh mode), prdi is declared and prdi bit of status2 register is set high. prdi is removed when bit 5 of g1 byte is detected to be 0 for ten consecutive frames (sonet mode) or three consecutive frames (sdh mode). 4.8 cell processing the payload is extracted from sts-3c(stm-1)/sts-1 frame in framing operation and provided to the cell delineation operation. (1) cell delineation hunt the cell delineation operation searches the cell header with correct hec. when a correct hec is found, the cell delineation operation enters presync state. presync with 53 byte interval, the cell header is checked for hec. if correct hec's are found for 6 cells, the cell delineation enters sync state. if an incorrect hec is found before that, the cell delineation operation returns to hunt state. sync the hec pattern is check cell by cell. if 7 consecutive incorrect hec's are found, the cell delineation returns to hunt state. the sync state has two mode; correction mode and detection mode. the cell delineation enters correction mode from presync state at first. when one bit hec error is found in correction mode, it is corrected and the cell delineation enters detection mode. if multiple bit hec error is found in correction mode, the cell is dropped and the operation enters detection mode. when a correct hec is found in
toshiba plc2 (TC35821F) specification 4- 8 detection mode, the operation returns to correction mode. (2) cell payload descramble the 48 byte cell payload is descrambled by the sequence generated by the polynomial ' x 43 +1.' the descramble operation can optionally be disabled by setting 1 to nodsbc in cms2 register. (3) fifo control receive cell data is stored in the 4 cell deep receive fifo. the receive fifo is controlled on cell basis. when the fifo is full of cell and there is more cells to be stored, these additional cells are discarded and rfov bit in status2 register is set high. the receive fifo can be reset independently by setting rxfres bit of pcont register. in reset state, the receive fifo discards cells stored in it and ignores writes. the rxfres bit should be set for at least 10.8 m s. (4) receive cell interface receive cell interface operates according to utopia level-2 defined in atm forum. the single-phy mode defined in utopia level-2 is compatible with utopia level-1. in single phy operation, data bus width is 8 bit. the maximum operation frequency is 33 mhz. in multi phy operation, data bus width can be 8 bit or 16 bit. optional direct status indication is also supported. the maximum operation frequency is 40 mhz. for parity bit, odd parity and even parity are selectable. when 16 bit data bus operation is selected and hec field is calculated in atm layer, hec can be inserted in udf1 or udf2. the parity selection and hec selection are set in cms1 register. details of the receive cell interface operation is described in section 2.4. (5) performance monitoring the number of cells which have been passed with hec error corrected are counted in 8 bit coher counter while the number of cells which have been dropped due to hec error are counted in 8 bit ucher counter. coher counter and u c her counter stop counting when the count value reaches ffh. the number of normal or corrected cells which have been stored into receive cell fifo is counted in 20 bit internal counter. the count value can be read via rxccl/m/h register. the rxccl/m/h are updated by setting 1 to rxcc bit in ccupd register. the receive cell counter stops counting when 4 msb bits reach ? 1111 ? . (6) optional mode when drop bit in cms2 re gister is set high, every cell with at least one hec error is dropped in sync mode. no hec correction is made. when pass bit in cms2 register is set high, every cell is passed to the receive cell fifo regardless of hec error in sync mode. when norc bit in cms2 register is set high, the coset polynomial x 6 +x 4 +x 2 +1, is not added(modulo 2) in hec calculation of received cell in these optional mode, cell delineation state transition is made as normal mode.
toshiba plc2 (TC35821F) specification 4- 9 (7) gfc handling gfc field is checked every cell. when plc2 finds any command (1xxx, x1xx or xx1x) in gfc field of received cell, it sets gfc bit of status2 register. when the command is halt(1xxx) and gfc en bit is set in cms2 register, transmit of cells is stopped. gfc field of received cell is stored in rgfc register.
toshiba plc2 (TC35821F) specification 5- 1 5. transmit functions 5.1 transmit clock generation (1) loop timing mode plc2 transmit side operates in loop timing mode when loopt bit of loop register is set high. in the loop timing mode, transmit clock is the same as the receive side clock. even when the clock recovery pll fails to lock with the receive data, the transmit clock frequency is kept because in such situation, the clock recovery pll switches the reference source to externally provided refck when autocse bit in cont register is set high . (2) internal clock generation mode plc2 generates transmit serial clock (155.52mhz/51.84mhz /25.92mhz ) from refck when loopt bit of loop register is set low and tcksel pin is tied high. (3) external clock mode plc2 transmit part operates on externally provided serial clock, txcip/m when loopt bit of loop register is set low and tcksel pin is tied low. 5.2 frame scrambling the transmit data is scrambled by quasi random pattern generated by polynomial 1+x 6 +x 7 . the first line of soh ( a1, a2, c1 ) is excluded from the scramble operation. the scramble operation start from the byte data following c1 with initial data for the polynomial '1111111.' this scramble operation can optionally be disabled by setting 1 to nodsbf bit in frms register. 5.3 bip calculation (1) section bip-8 the section bip-8 is calculated over the entire area of each frame after scramble based on 8 bits interleaved parity calculation using even parity. the calculated bip-8 code is inserted to b1 byte in the following frame before scrambling. (2) line bip-24 the line bip-24 is calculated over the entire area of each frame before scrambling except for the first to third rows of soh based on 24 bits interleaved parity calculation using even parity. the calculated bip-24 code is inserted into b2 bytes in the following frame before scrambling. (3) path bip-8 the path bip-8 is calculated over the entire area of each vc4 (or spe for sts-1 )
toshiba plc2 (TC35821F) specification 5- 2 before scrambling based on 8 bits interleaved parity calculation using even parity. the calculated bip-8 code is inserted into b3 byte in the following frame before scrambling. 5 .4 soh bytes insertion (1) a1, a2 the value should be f6h for a1 ? s and 28h for a2 ? s. these values are automatically inserted to transmit soh in plc2. (2) c1 the value should be 01h/02h/03h for sonet and 01h/aah/aah for sdh. these values are automatically inserted to transmit soh in plc2. (3) b1 the section bip-8 is calculated automatically and inserted to the b1 byte in the transmit soh. (4) h1, h2 the h1 and h2 bytes are automatically set to value shown in fig. 5.1 by internal processor. the pointer value is 0. the value of ss is 00 for sonet and 10 for sdh. for sdh mode operation, sdh bit of frms register (address:0 1 h) should be set to 1. for diagnostic purpose, h1 and h2 bytes in transmit frame can be written from outside. in this case internal transmit processor should be stopped by setting 1 in notp bit of t s mod 1 register. the pointer value in h1 and h2 bytes must be consistent with the value set to the j1posh/j1posv registers. table 5.1 shows some examples. pointer j1v j1h 0 86 521 522 782 3 3 8 0 2 3 89 89 3 89 table 5.1 correspondence between pointer and j1v/j1h h1 h1 h1 h2 h2 h2 0110 ss 93h 93h pointer[7:0] ffh ffh - pointer[9:8] pointer[9:0]=0h by default. ss=00 for sonet and 10 for sdh. figure 5.1 values for three h1's and three h2's in transmit soh.
toshiba plc2 (TC35821F) specification 5- 3 (5) h3 the h3 bytes are set automatically in transmit soh. the value is usually 00h and, when plc2 generates pais, ffh. (6) b2 the line bip-24 is calculated automatically and inserted to the b2 bytes of transmit soh. (7) k2 the line ais and line rdi are set into the k2 byte automatically in plc2 according to the condition tabulated in section 1.4. (8) z2 the line febe is calculated auto matically and inserted to the z2 byte. (9) others the other soh bytes are automatically filled with zero . 5.5 poh bytes insertion (1) b3 the path bip-8 is calculated automatically and inserted into the b3 byte. (2) c2 the value should be 13h because payload type is always atm for plc2. this value is automatically inserted to transmit poh in plc2. (3) g1 the path rdi are inserted automatically to the g1 byte according to the condition tabulated in section 1.4. the path febe is calculated and inserted to the g1 byte, too. (4) h4 the cell offset is counted automatically and set into the h4 byte. (5) others the other poh bytes are automatically filled with zero . 5.6 alarm signal insertion (1) lais: line alarm indication signal when los or lof is detected in the receive side, line ais is automatically inserted by transmitting the code 111 in bit 6, 7, 8 of the k2 byte of transmitting frame
toshiba plc2 (TC35821F) specification 5- 4 if lais bit is set in txalm1 register. lais is inserted without any condition when lais bit is set high in txalm2 register. (2) lrdi: line remote defect indication when los or lof is detected or lais is declared in the receive side, line rdi is automatically inserted by transmitting the code 110 in bit 6, 7, 8 of the k2 byte of transmitting frame if lrdi bit is set in txalm1 register. lrdi is inserted without condition when lrdi bit is set high in txalm2 register. (3) pais: path alarm indication signal when los, lof, lop, loc is detected or lais is declared in the receive side, path ais is automatically inserted by setting all-ones in h1/h2/h3 bytes and the entire payload field if pais bit is set in txalm1 register. pais is also inserted without condition when pais bit is set high in txalm2 register. (4) prdi: path remote defect indication when los, lof, lop, loc is detected or lais or pais is declared in the receive side, path rdi is automatically inserted by setting 1 in bit 5 of the g1 byte of transmitting frame if prdi bit is set in txalm1 register. prdi is inserted without condition when prdi bit is set high in txalm2 register. 5.7 transmit cell processing (1) transmit cell interface transmit cell interface operates according to utopia level-2 defined in atm forum. the single-phy mode defined in utopia level-2 is compatible with utopia level-1. in single phy operation, data bus width is 8 bit. the maximum operation frequency is 33 mhz. in multi phy operation, data bus width can be 8 bit or 16 bit. optional direct status indication is also supported. the maximum operation frequency is 40 mhz. for p arity bit, odd parity and even parity are selectable. when 16 bit data bus operation is selected, hec can be inserted in udf1 or udf2. the parity selection and hec selection are set in cms1 register. details of the transmit cell interface operation is described in section 2.4. (2) fifo control transmit cell data received from atm layer is stored in the transmit fifo. the transmit fifo is controlled in cell level. the fifo is programmable to be 1, 2, 3 or 4 cell deep. when the fifo is full of cell data, plc2 rejects receiving more cells from atm layer by deasserting txcav when it is polled. the transmit fifo can be reset independently by setting txfres bit of cont register. in reset state, the transmit fifo discards cells stored in it and ignores writes. the txfres bit should be set for at least 10.8 m sec.
toshiba plc2 (TC35821F) specification 5- 5 (3) cell header calculation a crc-8 calculation is performed over the first four header bytes. a parallel implementation of the polynomial, x 8 +x 2 +x+1 is used. the coset polynomial, x 6 +x 4 +x 2 +1 is added by modulo 2 to the residue. the result is inserted to the fifth byte of the atm cell. the coset polynomial addition can optionally be disabled by setting 1 to notc in cms2 register. the cell header calculation can optionally disabled by setting 1 to nohec bit in cms2 register. in this case, the 5th byte of the cell data goes through unchanged. (4) cell payload scrambling the 48 bytes of cell payload is scrambled with the sequence generated by the polynomial ' x 43 +1.' the scramble operation can optionally be disabled by setting high to noscbc in cms2 register. (5) performance monitoring the number of assigned or unassigned cells which have been read from transmit cell fifo and inserted in the transmit frames are counted in internal 20 bit counter. the count value can be read via txccl/m/h register. the txccl/m/h are updated by setting 1 to txcc bit in ccupd register. the transmit cell counter stops counting when 4 msb bits become ? 1111 ? . (6) gfc handling transmit of cells is stopped when gfchlt bit is set in gfc register and halt bits are set in gfc field of received cells. when tgfcen bit is set in cms3 register, tgfc[3:0] in cms3 register is inserted in the gfc field of assigned/unassigned cells transmitted from atm layer. additionally, when opt bit in gfc register is set high, tgfc[3:0] in cms3 register is also inserted in unassigned cells generated in plc2. (7) idle/unassigned cell insertion when there is no cell in the transmit fifo, plc2 inserts idle/unassigned cell to transmit frame dependent on register control. if uac bit is set high in cms1 register, plc2 inserts unassigned cells with gfc field set to ? 0001 ? or tgfc[3:0] depending on opt bit in cms3 register. if uac bit is set low, plc2 inserts idle cells.
toshiba plc2 (TC35821F) specification 6- 1 6. operation and test 6.1 startup procedure for startup, follow the procedure below. step 1: hardware reset -reset pin should be tied low for 10 cycles of clk to reset the configuration registers. these configuration registers have default values after reset. step 2: software reset set reset bits of cont registers to high for at least 20 cycles of refck to reset internal registers and then clear these reset bits. step 3: operation mode set set configuration registers according to the usage. if default values are sufficient, skip this step. step 4: clear stop clear stop bit of cont register of each port to start normal operation. setting stop bit high during normal operation is not recommended because it results in loss of frames and cells. 6.2 loop back loop back mode is controlled by loop register and tsdsel pin. (1) serial line loop back setting one to loopl bit of loop register or tying tsdsel pin to high forces plc2 into serial line loop back mode. in this mode, receive serial data rxdip/m is directly output from transmit serial port txdop/m and at the same time fed to receive part . (2) parallel line loop back setting one to loop2 bit of loop register forces plc2 into parallel line loop back mode. in this mode, receive serial data rxdip/m is serial/parallel converted and fed to receive parallel part and at the same time parallel/serial converted in transmit section and output from transmit serial port txdop/m. (3) serial utopia loop back setting one to loop1 bit of loop register forces plc2 into serial utopia loop back mode. in this mode, transmit serial data is looped back to receive serial input internally and at the same time output from transmit serial port txdop/m .
toshiba plc2 (TC35821F) specification 6- 2 (4) parallel utopia loop back setting one to loopu bit of loop register forces plc2 into parallel utopia loop back mode. in this mode, transmit parallel data is looped back to receive parallel part and at the same time parallel/serial converted and output from transmit serial port txdop/m. rx s/p tx p/s pecl /cmos cmos /pecl rx digital part tx digital part 16 bit 16 bit 8 bit 8 bit 1 bit 1 bit 1 bit 1 bit rxdip/m t xdop/m rxdac[15:0] t xdac[15:0] parallel utopia loop back rx s/p tx p/s pecl /cmos cmos /pecl rx digital part tx digital part 16 bit 16 bit 8 bit 8 bit 1 bit 1 bit 1 bit 1 bit rxdip/m t xdop/m rxdac[15:0] t xdac[15:0] serial utopia loop back serial line loop back rx s/p tx p/s pecl /cmos cmos /pecl rx digital part tx digital part 16 bit 16 bit 8 bit 8 bit 1 bit 1 bit 1 bit 1 bit rxdip/m t xdop/m rxdac[15:0] t xdac[15:0] rx s/p tx p/s pecl /cmos cmos /pecl rx digital part tx digital part 16 bit 16 bit 8 bit 8 bit 1 bit 1 bit 1 bit 1 bit rxdip/m t xdop/m rxdac[15:0] t xdac[15:0] parallel line loop back
toshiba plc2 (TC35821F) specification 6- 3 6.3 diagnostic test receive state detection capability can be tested in loop back mode using tsgen register. los, oof, lop, bip error, loc detection test can be made setting corresponding bit in tsgen register.
toshiba plc2 (TC35821F) specification 7- 1 7 . absolute maximum ratings parameter ratings ambient temperature under bias 0 c to 70 c storage temperature -65 c to 150 c supply voltage -0.5 v to 7.0 v input voltage applied -0.5 v to vdd + 0.5 v soldering temperature (10 sec) 240 c
toshiba plc2 (TC35821F) specification 8- 1 8. dc characteristics (ta = 0 c ~ 70 c , vdd = 5 v +/- 5 %) ttl level input and output symbol parameter min max units conditions volt u ttl utopia i/f output low voltage 0.4 volts iol = +8 ma voht u ttl utopia i/f output high voltage 2.4 volts ioh = -8 ma volt ttl output low voltage 0.4 volts iol = +4 ma voht ttl output high voltage 2.4 volts ioh = -4 ma vilt ttl input low voltage 0.8 volts viht ttl input high voltage 2.0 volts iilt ttl input low current -10 m a vil = vss iiht ttl input high current +10 m a vih = vdd cmos level input symbol parameter min max units conditions vilc cmos input low voltage 2.0 volts vihc cmos input high voltage 3.0 volts iilc cmos input low current -10 m a vil = vss iihc cmos input high current +10 m a vih = vdd pecl input and output symbol parameter min max units conditions volp pecl output low voltage vdd -1.9 vdd -1.5 volts note 1 vohp pecl output high voltage vdd -1.15 vdd -0.75 volts note 1 vilp pecl input low voltage vdd -1.9 vdd -1.5 volts note 1 vihp pecl input high voltage vdd -1.15 vdd -0.75 volts note 1 iilp pecl input low current -10 m a vil = vss iihp pecl input high current +10 m a vih = vdd note 1: ta = 25 c , vdd = 5 v, terminated to 3.0 v via 50 w symbol parameter min max units conditions iddd operating current 220 ma note 2 cin input capacitance 6 pf cout output capacitance 6 pf cio bi-directional capacitance 6 pf note2: vdd = 5.25 v, outputs loaded with 50 pf, txdop/m and rxdip/m operating at 155.52 mbit/s
toshiba plc2 (TC35821F) specification 9- 1 9. timing characteristics 9.1 line interface rx line interface symbol description min max units rxcip/m duty cycle 45 55 ns rxcip/m frequency tolerance -20 +20 ppm ts_rxdi rxdip/m setup time to rxcip/m high 2 ns th_rxdi rxdip/m hold time to rxcip/m high 2 ns tx line interface symbol description min max units txcip/m duty cycle 45 55 ns txcip/m frequency tolerance -20 +20 ppm ts_txdop txdop/m delay from txcip/m low -2 2 ns txdip/m txcip/m td_txdo figure 9.1.2 tx line interface timing rxdip/m rxcip/m ts_rxdi th_rxdi figure 9.1.1 rx line interface timing
toshiba plc2 (TC35821F) specification 9- 2 9.2 cell interface tx cell interface fig. 9.2.1 tx cell interface timing txclkc txenb ts_txenb th_txenb txcav txsoc txdac[15:0] txpty td_txcav ts_txsoc th_txsoc ts_txdac th_txdac ts_txpty th_txpty txadd[4:0] ts_txenb th_txenb
toshiba plc2 (TC35821F) specification 9- 3 transmit utopia level-2 single-phy or multi-phy with 8 bits data bus symbol description min max units txclkc frequency 33 mhz txclkc duty cycle 40 60 % ts_txenb txenb setup time to txclkc high 8 ns th_txenb txenb hold time to txclkc high 1 ns ts_txadd txadd[4:0] setup time to txclkc high 8 ns th_txadd txadd[4:0] hold time to txclkc high 1 ns td_txcav txcav delay from txclkc high 1 22 ns ts_txsoc txsoc setup time to txclkc high 8 ns th_txsoc txsoc hold time to txclkc high 1 ns ts_txdac txdac[7:0] setup time to txclkc high 8 ns th_txdac txdac[7:0] hold time to txclkc high 1 ns ts_txpty txpty setup time to txclkc high 8 ns th_txpty txpty hold time to txclkc high 1 ns transmit utopia level-2 multi-phy with 16 bits data bus symbol description min max units txclkc frequency 40 mhz txclkc duty cycle 40 60 % ts_txenb txenb setup time to txclkc high 6 ns th_txenb txenb hold time to txclkc high 1 ns ts_txadd txadd[4:0] setup time to txclkc high 6 ns th_txadd txadd[4:0] hold time to txclkc high 1 ns td_txcav txcav delay from txclkc high 1 1 9 ns ts_txsoc txsoc setup time to txclkc high 4 ns th_txsoc txsoc hold time to txclkc high 1 ns ts_txdac txdac [15:0] setup time to txclkc high 4 ns th_txdac txdac [15:0] hold time to txclkc high 1 ns ts_txpty txpty setup time to txclkc high 4 ns th_txpty txpty hold time to txclkc high 1 ns
toshiba plc2 (TC35821F) specification 9- 4 rx cell interface fig. 9.2.2 rx cell interface timing rxclkc rxenb ts_rxenb th_rxenb rxcav rxsoc rxdac[15:0] rxpty td_rxcav td_rxsoc td_rxdac td_rxpty rxadd[4:0] ts_rxadd th_rxadd
toshiba plc2 (TC35821F) specification 9- 5 receive utopia level-2 single-phy or multi-phy with 8 bits data bus symbol description min max units rxclkc frequency 33 mhz rxclkc duty cycle 40 60 % ts_rxenb rxenb setup time to rxclkc high 8 ns th_rxenb rxenb hold time to rxclkc high 1 ns ts_rxadd rxadd[4:0] setup time to rxclkc high 8 ns th_rxadd rxadd[4:0] hold time to rxclkc high 1 ns td_rxcav rxcav delay from rxclkc high 1 22 ns td_rxsoc rxsoc delay from rxclkc high 1 22 ns td_rxdac rxdac[7:0] delay from rxclkc high 1 22 ns td_rxpty rxpty delay from rxclkc high 1 22 ns receive utopia level-2 multi-phy with 16 bits data bus symbol description min max units rxclkc frequency 4 0 mhz rxclkc duty cycle 40 60 % ts_rxenb rxenb setup time to rxclkc high 6 ns th_rxenb rxenb hold time to rxclkc high 1 ns ts_rxadd rxadd[4:0] setup time to rxclkc high 6 ns th_rxadd rxadd[4:0] hold time to rxclkc high 1 ns td_rxcav rxcav delay from rxclkc high 1 1 9 ns td_rxsoc rxsoc delay from rxclkc high 1 1 9 ns td_rxdac rxdac[15:0] delay from rxclkc high 1 1 9 ns td_rxpty rxpty delay from rxclkc high 1 1 9 ns
toshiba plc2 (TC35821F) specification 9- 6 9.3 cpu interface cpu interface read timing [with active ale] figure 9.3.1 cpu interface read access with active ale read access starts when (-rd + -ce) goes down and ends when (-rd + -ce) goes up. symbol description min max units ts_a valid address setup time to ale 25 ns th_a valid address hold time from ale 5 ns tw_ale ale high pulse width 20 ns ts_ale ale low setup time to read start 0 ns th_ale ale low hold time to read end (1) ns td_rd valid data delay from read start (2) ns tz_rd data output hi-z from read end 1 20 ns td_ready ready valid delay from read start tbd tbd ns tdn_ready ready low delay from read start (3) ns tw_rrecov read recovery time (4) ns table. 9.3.1 cpu interface re ad timing with active ale valid address a[6:0] ale ts_a th_a tw_ale ts_ale tw_rrecov th_ale d[7:0] -ready valid data tz_rd td_ready tdn_ready td_rd
toshiba plc2 (TC35821F) specification 9- 7 [with ale fixed to high] figure 9.3.2 cpu interface read access with fixed ale read access starts when (-rd + -ce) goes down and ends when (-rd + -ce) goes up. symbol description min max units ts_a valid address setup time to (-ce + -rd) low 25 ns th_a valid address hold time from (-ce + -rd) high 5 ns td_rd valid data delay from read start (2) ns tz_rd data output hi-z from read end 1 20 ns td_ready ready valid delay from read start tbd tbd ns tdn_ready ready low delay from read start (3) ns tw_rrecov read recovery time (4) ns table. 9.3.2 cpu interface read timing with ale fixed to high -ce + -rd valid address a[6:0] ale ts_a th_a tw_rrecov d[7:0] -ready valid data tz_rd td_ready tdn_ready td_rd
toshiba plc2 (TC35821F) specification 9- 8 in the formula below, fmin is lower frequency of byte clock and clk (host interface clock). byte clock is 19.44mhz for sts-3 (stm-1), 6.38mhz for sts-1 and 3.24mhz for sts-1/2. clk is 19.44mhz. (1) th_ale(min) = (1 / fmin ) * 2 [ ns] (2) for internal registers and internal memories except for tx/rx overhead memories: td_rd (max) = (1 / fmin ) * 3 + 50 [ ns] for tx/rx overhead memories: td_rd (max) = (1 / fmin ) * 3 + 50 [ ns] when stop bit in pcont register is set. td_rd (max) = (1 / fmin ) * 100 [ ns] when stop bit in pcont register is not set. (3) for internal registers and internal memories except for tx/rx overhead memories: td_ready (max) = (1 / fmin ) * 3 + 50 [ ns] for tx/rx overhead memories: td_ready (max) = (1 / fmin ) * 3 + 50 [ ns] when stop bit in pcont register is set. td_ready (max) = (1 / fmin ) * 100 [ ns] when stop bit in pcont register is not set. in the formula above, fmin is lower frequency of byte clock and clk (host interface clock). byte clock is 19.44mhz for sts-3 (stm-1), 6.38mhz for sts-1 and 3.24mhz for sts-1/2. clk is 19.44mhz. (4) tw_recov(min) = (1 / fmin ) * 3 [ ns]
toshiba plc2 (TC35821F) specification 9- 9 cpu interface write timing [with active ale] write access starts when (-wr + -ce) goes down and ends when (-wr + -ce) goes up. symbol description min max units ts_a valid address setup time to ale 25 * ns th_a valid address hold time to ale 5 * ns tw_ale ale high pulse width 20 * ns ts_ale ale low setup time to write start 0 * ns th_ale ale low hold time to write end (1) * ns tw_cewr write pulse width (2) * ns ts_wd write data setup time to write start 0 * ns th_wd write data hold time to write end 0 * ns td_ready ready valid delay from write start tbd tbd ns tdn_ready ready low delay from write start * (3) ns tw_wrecov write recovery time * (4) ns table 9.3.3 cpu interface write timing with ac tive ale valid address a[6:0] ale d[7:0] -ready ts_a th_a tw_ale ts_ale tw_cewr ts_wd valid data th_wd td_ready tdn_ready -ce + -wr figure 9.3.3 cpu interface write access with active ale tw_wrecov
toshiba plc2 (TC35821F) specification 9- 10 [with ale fixed to high] write access starts when (-wr + -ce) goes down and ends when (-wr + -ce) goes up. symbol description min max units ts_a valid address setup time to (-ce + -wr) low 25 * ns th_a valid address hold time from (-ce + -wr) high 5 * ns tw_cewr write pulse width (2) * ns ts_wd write data setup time to write start 0 * ns th_wd write data hold time to write end 0 * ns td_ready ready valid delay from write start tbd tbd ns tdn_ready ready low delay from write start * (3) ns tw_wrecov write recovery time * (4) ns table 9.3.4 cpu interface write timing with ale fixed to high valid address a[6:0] ale d[7:0] -ready ts_a th_a tw_cewr ts_wd valid data th_wd td_ready tdn_ready -ce + -wr figure 9.3.4 cpu interface write access with fixed ale tw_wrecov
toshiba plc2 (TC35821F) specification 9- 11 in the formula below, fmin is lower frequency of byte clock and clk (host interface clock). byte clock is 19.44mhz for sts-3 (stm-1), 6.38mhz for sts-1 and 3.24mhz for sts-1/2. clk is 19.44mhz. (1) th_ale(min) = (1 / fmin ) * 2 [ ns] (2) for internal registers and internal memories except for tx/rx overhead memories: tw_cewr (max) = (1 / fmin ) * 4 [ ns] for tx/rx overhead memories: tw_cewr (max) = (1 / fmin ) * 4 [ ns] when stop bit in pcont register is set. tw_cewr (max) = (1 / fmin ) * 100 [ ns] when stop bit in pcont register is not set. (3) for internal registers and internal memories except for tx/rx overhead memories: td_ready (max) = (1 / fmin ) * 3 + 50 [ ns] for tx/rx overhead memories: td_ready (max) = (1 / fmin ) * 3 + 50 [ ns] when stop bit in pcont register is set. td_ready (max) = (1 / fmin ) * 100 [ ns] when stop bit in pcont register is not set. (4) tw_recov(min) = (1 / fmin ) * 3 [ ns]
toshiba plc2 (TC35821F) specification a- 1 a.1 plc2 internal operation rx clock recovery block recovers clock from nrz signal of 155.52mbps or 51.84mbps. the clock recovery pll switches to the reference clock refck when at least one of three conditions below are satisfied: (1) looc is asserted (2) 80 bit period of no signal transition is detected (3) pll frequency deviated more than 244ppm from the reference clock the clock recovery pll switches to the incoming data again when three conditions below are all satisfied: (1) looc is not asserted. (2) signal transition is detected in 80 bit period (3) pll frequency is within 244 ppm range of the reference clock rx serial to parallel converter received signal data is converted to 8 bits parallel form in this block. the operation clock can be selectable between internally recovered clock or externally provided clock. receive frame handler (1) the frame structure is recognized and synchronization is done. when the frame synch r onization is in hunt mode, oof is declared. when oof continues more than 3msec, lof is declared. (2) the point tracking is done in this block. when the pointer value in h1/h2 bytes are invalid, lop (loss of pointer) is declared. (3) the entire soh/poh area of each incoming frame is stored in the receive overhead memory. the payload area is transferred to the receive cell handler. (4) section bip-8, line bip-24 and path bip-8 are calculated for each incoming frame. receive overhead memory the 256 bytes receive overhead memory stores soh/poh of each incoming frame for processing by the receive processor. it is used as working area for the receive processor. receive processor the receive processor accesses the receive overhead memory for soh/poh handling. for each frame, the receive processor: (1) checks the k2 byte to declare line ais and line rdi. (2) checks the h1/h2 byte to declare path ais. (3) checks the g1 byte to declare path rdi. (4) checks the b1 byte to count section bip-8 errors and accumulates the error count. (5) checks the b2 byte to count line bip-24 errors and accumulates the error count. (6) checks the b3 byte to count path bip-8 errors and accumulates the error count.
toshiba plc2 (TC35821F) specification a- 2 (7) checks the z2 byte to accumulate line febe count. (8) checks the g1 byte to accumulate path febe count. receive program memory the receive program memory stores up to 1024 steps of instruction codes for the receive processor. receive cell handler the receive cell handler makes cell delineation. it checks the header of incoming cells. when a cell with 1bit header error is found while in sync correction mode, the receive cell handler corrects the error and send it to the receive cell fifo. when a cell with 1 bit error is found in sync detection mode or when a cell with multiple bit error is found while in sync correction mode, the receive cell handler discards the cell. cells with corrected header, cells which are discarded and cells which are normal or corrected and stored in the receive cell fifo are counted respectively. in the hunt mode, the receive cell handler declares loc (loss of cell delineation). receive cell fifo the receive cell fifo can store up to 4 cells. the fifo depth is fixed to be 4 cell deep. when an entire cell is stored, the full flag is set and the receive cell interface begins to read the cell data and send it to atm layer. the write port of the fifo operates on the receive network clock while the read port operates on the cell interface clock provided from the atm layer. receive cell interface the receive cell interface reads cell data from the receive cell fifo and send it to the atm layer. the cell transfer begins when the entire cell data has been stored in the receive cell fifo. utopia level1 and level2 are both supported. the data bus width is selectable between 8 bits and 16 bits. transmit clock synthesis the transmit clock synthesis pll generates 155.52mhz/51.84mhz from reference clock of 19.44mhz/6.48mhz. if it fails to get within 244ppm range of the reference clock, txool is declared. tx parallel to serial converter the tx parallel to serial converter converts the transmit parallel data to serial one. the operation clock can be selectable between internally generated clock and ex t ernally provided clock. transmit frame handler (1) b1, b2 and b3 value for the tra n smit frame are calculated. (2) the transmit frame is assembled with soh/poh read from the transmit overhead memory and payload received from the transmit cell handler.
toshiba plc2 (TC35821F) specification a- 3 transmit overhead memory the 256 byte transmit overhead memory stores soh/poh to transmit. it is used as working area for the transmit processor. transmit processor for each transmit frame, the transmit processor: (1) checks status1, status2 and if conditions are satisfied, inserts line ais, line rdi, path ais, path rdi to soh/poh in the transmit overhead memory. (2) copies b1, b2 and b3 value from the corresponding registers of the transmit frame handler to b1, b2 and b3 bytes of soh/poh in the transmit overhead memory. (3) copies line febe and path febe value from the corresponding registers of the transmit frame handler to z2 and g1 bytes of soh/poh in the transmit overhead memory. transmit program memory the transmit program memory stores up to 512 steps of instruction codes for the transmit processor. transmit cell handler the transmit cell handler read cell data from the transmit cell fifo and calculates and inserts hec field and send the cell data to the transmit frame handler. transmit of cell can be stopped by register control when halt bit is set in the gfc field of received cells. transmit cell fifo the transmit cell fifo can store up to 4 cells. the fifo depth can be programmed to be 1, 2, 3 and 4. when an entire cell is stored, the full flag is set and the transmit cell handler begins to read the cell data. the write port of the fifo operates on the cell interface clock provided from the atm layer while the read port operates on the network clock. transmit cell interface the transmit cell interface receives transmit cells from atm layer and stores them into the receive cell fifo. the cell transfer begins when the cell fifo has space for an entire cell. utopia level1 and level2 are both supported. the data bus width is selectable between 8 bits and 16 bits. host interface plc2 registers and internal memories can be accessed via the host interface. ale (address latch enable) signal and the address latch is included so as to allow address/data multiplexed bus. the registers are accessed directly while internal memories are accessed via memah/l and memd port.
toshiba plc2 (TC35821F) specification a- 4 a.2 plc2 clocking details 1) rx serial clock rx serial clock is used for the rx serial to parallel converter. the rx serial clock is divided by eight and usually delivered to the main part of rx block. the internally recovered clock or externally provided clock can be selected as the rx serial clock. the selection is made by rcksel pin. < internal clock recovery mode> the rx pll recovers the serial clock from the serial data input rxdp/m. the recovered clock is divided by 8 and compared with reference clock refck in rxool detector. initially rx pll locks to the reference clock. when the frequency of the rx pll enters within 244ppm of the reference clock, rx pll tries to lock to the serial data input rxdp/m. once data lock is succe s sfu l , rx pll reverts to the reference clock if the frequency of the recovered clock is not within 244ppm of the reference clock or loocp is high and loocm is low or no signal transition is detected for 80 bits period. when rcksel input is set high, the internally recovered clock is selected as rx serial clock. < external serial clock mode> when rcksel input is set low, the external serial clock is selected as rx serial clock. the external serial clock is input to pecl input pins rxcip/m. (2) rx main clock (rxclkn) rx main clock is used in the rx main part of plc2 where the soh/poh processing, cell delineation and write of retrieved cell data to receive cell fifo are executed. basically rx main clock is divide by 8 of rx serial clock. rx serial clock is internally recovered clock or externally provided clock. when rcksel pin is set high, the internally recovered clock is selected. when rcksel is set low, the externally provided clock is selected. the selected clock is divided by 8 and is input to the rxool detector. when the divided by 8 clock is out of 244ppm of the reference clock, rxool is set high and the reference clock, refck is selected as rx main clock. refck is also selected when the diagnostic loop back mode is enabled. (3) rx cell interface clock (rxclkc) rx cell interface clock, rxclkc is input from atm layer. it is used to read cells from the receive cell fifo and transfer them to atm layer. the rxclkc frequency is required to be from 20mhz to 33mhz for utopia level-1 operation and up to 40mhz for utopia level-2 operation. (4) tx serial clock < loop timing mode> plc2 enters loop timing mode when loopt bit is set high in loop register. in loop timing mode, rx serial clock is used as tx serial clock. rx serial clock can be internally recovered clock or externally provided serial clock rxcip/m dependent on
toshiba plc2 (TC35821F) specification a- 5 rcksel input. when the internally recovered clock is selected as rx serial clock and it can not lock to serial data input, rx pll locks to refck and continues to provide serial clock to tx line i/f block. < external transmit clock mode> when loopt bit is set low in loop register and tcksel is set low, external serial clock , txcip/m is selected as tx serial clock. < internal tx serial clock synthesis mode> when loopt bit in loop register is set low and tcksel input is set high, tx pll output is selected as tx serial clock. tx pll generates 8 times frequency of the reference clock, refck. when refck is 19.44mhz, tx pll generates 155.52mhz. when refck is 6.48mhz, tx pll generates 51.84mhz. tx pll output is divided by eight and compared with refck. when the divided clock is not within 244ppm of refck, txool is set high. < line loop b ack mode> plc2 enters line loop back mode when loop2 bit is set high in loop register. in loop timing mode, rx serial clock is used as tx serial clock. rx serial clock can be internally recovered clock or externally provided serial clock rxcip/m dependent on rcksel input. when the internally recovered clock is selected as rx serial clock and it can not lock to serial data input, rx pll locks to refck and continues to provide serial clock to tx line i/f block. (5) tx main clock tx main clock is used in tx main part where transmit data is processed in 8 bit parallel. < loop timing mode> when loopt bit in loop register is set high, divided by eight of rx serial clock is selected as tx main clock. when rx serial clock is rx pll output and rx pll can not lock to the receive data, tx main clock is automatically changed to the reference clock, refck. < external transmit clock mode> when loopt bit in loop register is set low and tcksel is set low, divided by eight of external serial clock input txcip/m is selected as tx main clock. < internal tx serial clock synthesis mode> when loopt bit in loop register is set low and tcksel is set high, refck is selected as tx main clock. < line loop b ack mode> when loop2 bit in loop register is set high, plc2 enters line loopback mode and the divided by eight of rx serial clock is selected as tx main clock. when rx serial clock is rx pll output and rx pll can not lock to the receive data, tx main clock is
toshiba plc2 (TC35821F) specification a- 6 automatically changed to the reference clock, refck. (6) tx cell interface clock (txclkc) tx cell interface clock, txclkc is delivered from atm layer. it is used to receive cells from atm layer and write them to the transmit fifo. the txclkc frequency is required to be within 20mhz to 33mhz for utopia level-1 operation and up to 40mhz for utopia level-2 operation. (7) host interface clock (clk) host interface clock, clk is used to the host register read/write operation. it is recommended to be around 20mhz. for instance, clk input can be the same as refck input, i.e. 19.44mhz/6.48mhz.
toshiba plc2 (TC35821F) specification a- 7 a.3 plc2 application guidance -connection between plc2 and an optical transceiver -plc2 analog components connection -supplemental information about plc 2 application board design
toshiba plc2 (TC35821F) specification a- 8 rxdip rxdim 82? 130? dvdd dvss 82? 130? dvdd dvss loocp loocm 82? 130? dvdd dvss 82? 130? dvdd dvss optical transceiver plc2 txdop txdom 82? 130? dvdd dvss 82? 130? dvdd dvss txd+ txd- rxd+ rxd- sd- sd+ connection between plc2 and an optical transceiver txcip dvss txcim dvss rxcip dvss rxcim dvss it is assumed that sd is asserted high when certain level of optical signal is detected. if sd output of the optical transceiver has single ended, meaning that only sd+ is output, then loocp input should be tied to 3.7v. it is realized, for instance, by tying loocp to dvdd via1.3k? and to dvss via 3.7k?. biasp biasm 82? 130? dvdd dvss 82? 130? dvdd dvss
toshiba plc2 (TC35821F) specification a- 9 plc2 analog components connection plc2 dvdd dvss r2 c1 rxfilt r1 rxres rxpll avssr avddr r4 c2 txfilt r3 txres txpll avsst avddt tvss0 tvss1 c3 c4 c5 c6 l1 l2 l3 l4 l5 l6 r1: tbd. r2: tbd. r3: tbd. r4: tbd. c1: tbd. c2: tbd. c3: 0.1f & 1.0f c4: 0.1f & 1.0f c5: 0.1f & 1.0f c6: 0.1f & 1.0f l1~l6: ferrite bead
toshiba plc2 (TC35821F) specification a- 10 avsst txfilt txres avddt avssr rxfilt rxres avddr transmit analog island receive analog island plc2 1. resistors and capacitors connected to rxres or rxfilt should be included in receive analog island. 2. resistors and capacitors connected to txres or txfilt should be included in transmit analog island. 3. these analog island should be as small as possible to reduce coupling with surrounding digital area. 3. digital signal lines should not run over analog islands. 4. ideally every power pins should have 0.1f and 4,7 f decoupling chip capacitors. 5. ideally every pecl terminators should have 0.1 f decoupling chip capacitors. supplemental information about plc2 application board design

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