5 5 4 4 3 3 2 2 1 1 d d c c b b a a IT8711F application circuit v0.2 page4 : vid,ir,cir,fdc & smart card reader connecto r preliminary for reference onl y revision his tory revi sion pc b revi sion modification ite ms drawing and modification descriti on date it-8711-cg-s01 ver 0.1 ** subject to ch ange without notice schematic page1 : revision history page3 : serial & parallel ports n/a page5 : la yout & routing guideline april 17,2001 for intel ch ipset first d raft it-8711-cg-s01 ver 0.2 n/a 2. adding vid circuit june 21,200 1 page2 : it 8711f 4. modify r33 & rn8 from 1k ohm to 150 ohm 5. add jp8 for keyboard/mouse power supplied by vcc/v cch 3. modify r11 & r12 from 22 ohm to 4.7k ohm 6. add layout/routing guidelines for 3vsb circuit 1. modify u1 pin27 connect to 3vsb 7. swap it8711 pin67 and pin68 off-page connector label it-8711-cg-s01 v0.2 0.2 IT8711F revision history ite, inc. 1 5 monday, january 07, 2002 title size document number rev date: sheet of
5 5 4 4 3 3 2 2 1 1 d d c c b b a a ** subject to ch ange without notice preliminary for reference onl y power on strapping 2-3 : disab le kbc jp4 : 1-2 : base address = 2eh/2fh note : vref pull-up to +5v for game port reference jp3 : 2-3 : base address = 4eh/4fh low pin count (lpc) interface signals jp2 : power control signals. please reference power con trol suggestion applications circuitr y of page 5. jp1 : this power-on straping pin is re served for ite test. note : only one function ( keyboard lock or (spare for battery installation glitch) tantalum cap. pc board layout checklist .recommended net "vbat" minimum trace width 12mils .place c3 close t o IT8711F .isolated the vbat pin2 9 and chipset pin ga20 & kbrst# connect to south brid ge 2-3 for c irtx 1-2 for key board cirtx ) could be select a t the same time keyboard lock jumper during lreset#, a pill-up on t his pin is needed. 1-2 : enabl e kbc .recommended net "3vsb" minimum trace width 12mils pc board layout checklist .place bc3 close to IT8711F it-8711-cg-s01 v0.2 0.2 it871 1f ite, inc. 2 5 monday, january 07, 2002 title size document number rev date: sheet of pciclk densel# lframe# midi_in scpsnt# dsr1# drva# kblk#/cirtx pd2 lad3 clkin rts1#/jp2 kdat pwbou t# irtx jab1 wga te# pd6 midi_out index # dir# irrx scpwr dtr1#/jp1 pd4 rdata# afd# scio pd3 sout 2 slct pwrctl# gnd vcc5 pd7 scclk rts2 # mt ra# gnd sin2 pme# lrese t# ldrq# slin# jbcx pe pd5 jbb1 gnd pd0 kblk#/cirtx lad2 busy dcd2# scrst jacy hdsel# kclk vcc5 ri2# jbb2 dcd1# jab2 ri1# dsr2# dskchg# lad0 wpt# sl psx# sout1/jp3 serirq pd1 cts2 # cirtx vref ste p# err# st b# jbcy init# sin1 cirrx cts1 # gnd jacx ack# wdata # mclk dtr2# lad1 trk0# 3vsb ldrq# pme# gnd vb at md at pwbtin# kbrst # ga20 vcc3 vcc3 kblk# vid0 vid1 vid2 vid3 vid4 ldrq# lframe# rts2# 3 irrx 4 drva# 4 pd4 3 scrst 4 kdat 4 dsr2# 3 pd3 3 densel# 4 lad0 txd2 3 dcd2# 3 ri1# 3 pm e# cts2# 3 md at 4 dtr2# 3 rxd2 3 jbcy 4 pd5 3 scio 4 pd0 3 pd6 3 jacx 4 scclk 4 pciclk scpwr 4 mclk 4 pwbout # serirq midi_out 4 lad1 ri2# 3 lad2 dtr1# 3 irtx 4 lreset # stb# 3 pd7 3 midi_in 4 jab2 4 pwrctl# lad3 pd2 3 init# 3 rdata# 4 sl psx# slin# 3 mt ra# 4 jbcx 4 wdat a# 4 afd# 3 err# 3 pd1 3 rts1 # 3 jbb1 4 jab1 4 kclk 4 jacy 4 cirtx 4 jbb2 4 txd 1 3 cirrx 4 scpsnt# 4 ga20 kbrst # rxd1 3 dsr1# 3 dcd1# 3 cts1 # 3 dir# 4 st ep# 4 wg ate# 4 hdsel# 4 trk0 # 4 dskchg# 4 wpt# 4 index # 4 slct 3 pe 3 vid0 4 vid1 4 vid2 4 vid3 4 vid4 4 busy 3 ack# 3 vcc3 vcc5 vcch vcc3 3vs b vcc3 vcc3 3vsb jp6 1 2 3 d1 1n4148 jp4 1 2 3 r1 1k r2 1k bc2 0.1uf r3 1k r8 4.7k u1 IT8711F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 59 56 57 58 60 62 63 64 61 66 65 68 67 69 70 71 72 73 74 75 76 77 78 79 80 81 82 85 84 83 86 87 90 89 88 91 92 93 94 95 96 97 98 99 100 dcd2#/gp62 sin2/gp63 gnd ri2#/gp10 cts2#/gp11 dtr2#/gp12 rts2#/gp13 dsr2#/gp14 sout2/gp15 ga20/gp16 krst#/gp17 kclk/gp20 kdat/gp21 mclk/gp22 mdat/gp23 pwbtin#/gp24 pwbtout#/gp25 slpsx#/gp26 pwrctl#gp27 vid0/gp30 vid1/gp31 vid2/gp32 vid3/gp33 vid4/gp34 gp35 gp36 vcch gnd vbat kblk#/cirtx/gp40 cirrx/gp41 irtx/gp42 irrx/gp43 pme# scpsnt#/gp44 scrst/gp45 scpwr/gp46 scclk/gp47 scio/gp60 ldrq# lframe# lreset# serirq lad0 lad1 lad2 lad3 pciclk densel# mtra# drva# cklin gnd vcc wdata# dir# step# hdsel# wgate# rdata# trk0# index# wpt# dskchg# slct pe busy ack# slin# init# err# afd# stb# pd0 pd1 pd2 pd3 gnd pd4 pd5 pd6 pd7 dcd1# ri1# cts1# dtri1#/jp1 rts1#/jp2 dsr1# sout1/jp3 sin1 vcc jbb2/gp57 jbb1/gp56 jab2/gp55 jab1/gp54 jbcy/gp53 jbcx/gp52 jacy/gp51 jacx/gp50 jvr/gp61 r9 33 c3 0.1uf sw1 u2 24mhz\o sc 1 7 14 8 nc gnd vcc out jp2 1 2 3 jp3 1 2 3 r5 1k r10 22 r7 4.7k + bat1 li-bat 2 1 r6 4.7k c5 4.7uf/10v jp5 bc3 0.1uf r4 10k c4 1uf jp1 1 2 3 r11 4.7k bc1 0.1uf r12 4.7k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a preliminary for referenc e only ** subject to change wi thout notice op tional serial ports op tional to chipset parallel p ort it-8711-cg-s01 v0. 2 0.2 serial & parallel ports ite, inc. 3 5 monday, january 07, 2002 title siz e document number rev date: sh eet of dsr2# nri2# dcd2# nt xd2 ri2# ndcd2# ndcd2# rxd1 txd1 nt xd1 nr ts1# nct s2# dtr 2# rts2# cts2# ndtr 2# ndcd1# nt xd2 nr ts2# rxd2 nri1# nr ts1# nt xd1 ndtr 1# ndtr2 # ri1# ndsr1# nri2# nc ts1# cts1# nc ts2# ndcd1# dsr1# rts1# ndsr2# nrxd1 ndsr2# vcc5 txd2 dcd1# ndsr1# nc ts1# nri1# ndtr 1# nrxd2 nr ts2# nrxd2 nrxd1 dtr 1# nri1# nri2# vcc5 +12 v pd5 st b# pd4 pd6 err# ack # pe bus y pd7 pd2 slin# vcc5 pd3 afd# init# slct pd1 pd0 -1 2v dcd2# 2 cts1# 2 rxd1 2 dsr2# 2 dtr 2# 2 rxd2 2 ri1# 2 rts2# 2 txd2 2 dcd1# 2 ri2# 2 dtr 1# 2 dsr1# 2 txd1 2 cts2# 2 rts1# 2 ring# pd5 2 slin# 2 pd6 2 st b# 2 ack # 2 pd3 2 bus y 2 afd# 2 pd2 2 init# 2 slct 2 pd7 2 pe 2 pd1 2 err# 2 pd4 2 pd0 2 vcc5 vcc5 vcc5 vcch +1 2v -12v c9 100 pf r1 8 2.2 k c6 100 pf c23 180 pf c13 100 pf c33 180 pf c10 100 pf rn4 8p4r-2 .2k 1 2 3 4 6 7 8 5 c1 2 100 pf c26 180 pf c19 100 pf lp t1 print-fem 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 d4 1n4 148 r15 10k r1 4 10 k c16 100 pf c2 7 180p f r13 4.7k c21 100 pf rn6 8p4r -22 1 2 3 4 6 7 8 5 c18 100 pf c28 180 pf c2 0 100 pf c2 2 180p f rn3 8p4r-2 .2k 1 2 3 4 6 7 8 5 c14 100 pf c25 180 pf c1 5 100 pf c29 180 pf c17 100 pf q2 2n7 002 q1 2n7 002 c3 2 180p f u4 gd 75232 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 +12v vcc ra0 ry0 ra1 ry1 ra2 ry2 dy0 da0 dy1 da1 ra3 ry3 dy2 da2 ra4 ry4 -12v gnd d2 1n4 001 rn1 8p4r-2 .2k 1 2 3 4 6 7 8 5 com 2 head 10 1 2 3 4 5 6 7 9 8 10 c31 180 pf d6 1n 4148 com 1 db9 5 9 4 8 3 7 2 6 1 c34 180 pf c24 180 pf c3 7 180p f rn2 8p4r-2 .2k 1 2 3 4 6 7 8 5 rn7 8p4r -22 1 2 3 4 6 7 8 5 d5 1n4 148 r17 10k rn5 8p4r -22 1 2 3 4 6 7 8 5 r1 6 10 k u3 gd 75232 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 +12v vcc ra0 ry0 ra1 ry1 ra2 ry2 dy0 da0 dy1 da1 ra3 ry3 dy2 da2 ra4 ry4 -12v gnd c35 180 pf c11 100 pf c30 180 pf d3 1n4 001 c8 100 pf c38 180 pf c7 100 pf c36 180 pf
5 5 4 4 3 3 2 2 1 1 d d c c b b a a preliminary for referenc e only ** subject to change wit hout notice ir & c ir connector fdc connec tor smart card read er connector game & midi port ps/2 mouse por t from cp u to pwm dc-d c conve rter vid con trol at keyboard keyboa rd port ps/2 mouse it-8711-cg-s01 v0. 2 0.2 flash rom ite, inc. 4 5 monday, january 07, 2002 title siz e document number rev date: sh eet of irtx cirrx irrx cirtx index # wg ate# trk0 # wpt # st ep# wdat a# drva # dskchg # rd ata# dens el# mt ra# hdse l# dir# vcc5 jbcy jacy jb b2 vcc5 ja b1 jb b1 ja b2 jbcx jacx midi_out midi_in vid2 vid3 vid4 vid0 vid1 kcl k gnd gnd mclk gnd pvcc pvcc gnd gnd gnd kdat md at gnd cirrx 2 cirtx 2 irtx 2 irrx 2 hdse l# 2 mt ra# 2 index # 2 dir# 2 rd ata# 2 dskchg # 2 wpt # 2 drva # 2 st ep# 2 trk0 # 2 dens el# 2 wdat a# 2 wg ate# 2 scr st 2 scpw r 2 sccl k 2 scp snt# 2 scio 2 jacx 2 jbb 2 2 jab 2 2 jacy 2 jbcy 2 jbcx 2 jab 1 2 jbb 1 2 midi_out 2 midi_in 2 vid4 2 vid2 2 vid0 2 vid1 2 vid3 2 md at 2 kcl k 2 mclk 2 kdat 2 vcc5 vcc5 vcch vcc5 vcc5 vcch vcc5 vcc3 vcc5 vcch rn8 8p4 r-150 1 2 3 4 6 7 8 5 cn4 ps2-m s 3 5 1 2 6 4 7 8 9 c41 0.01uf r31 2.2k 1 2 r22 4.7k r32 2.2k 1 2 c49 220 pf 1 2 c50 220 pf 1 2 c42 0. 01uf r24 4.7k r45 820 c4 0 0.01uf r43 47k c46 0.001uf r23 4.7k jp8 1 2 3 r26 2.2k r4 4 47 k r2 7 470 r28 2.2k r3 3 15 0 r3 0 470 c39 0. 01uf cn2 1 2 3 4 5 c47 0. 001uf r46 820 r47 820 jp7 1 2 3 cn1 1 2 3 4 5 r48 820 r4 9 82 0 cn7 smcardcn 1 2 3 4 5 6 7 14 13 12 11 10 9 8 vcc nc scrfet# scrclk rfu gnd nc nc scrpres# scrio rfu scrrest nc led cn3 db 15 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 r25 2.2k r36 4.7k r19 4.7k r20 4.7k r41 47k r40 47k c4 5 0.001uf l4 fb l5 fb l6 fb c43 0. 001uf cn5 at-k b 1 4 2 5 3 7 6 r34 2.2k 1 2 r35 2.2k 1 2 c53 .1uf 1 2 cn6 fdc_co n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 gnd densel# gnd nc gnd nc gnd index# gnd mtra# gnd nc gnd drva# gnd nc gnd dir# gnd step# gnd wdata# gnd wgate# gnd trk0# gnd wpt# nc rdata# gnd hdsel# nc dskchg# c48 0. 001uf c51 220 pf 1 2 c52 220 pf 1 2 l2 fb l3 fb c44 0. 001uf r42 47k l1 fb r2 1 4.7 k r29 2.2k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a 1.for clock lines : 2)vb at should be routed with a minimum trace width of 12 mils. 1)if possible, please avoid using any through-hole. 3)the spacing to th e closest neighbor should be wide enough. 2.for the vbat circuits : layout/routing guideli nes 2)please make the trace length short, and the trace width wide enough. 4)the discrete damping resistors an d capacitors are recommended. 1)place the 1uf capacit or of vbat pin close to ite i/o chip. 3)isolate the vbat pin of ite i/o chip from the pin g1/vccrtc of intel's ich with diode. 4)the 4.7uf/10v tantalum capacitor connected to the diode of b attery is spare for battery installation glitches. ** subject to change without no tice preliminary for reference only 5)please do n't share the i/o clock, 24/48mhz, with other device. 5.please don't change the resistors and capacitors values in the game and midi circuits. 4.please don't remove the pull-up resistor of ldrq#. 7.IT8711F power cont rol suggestion applications circuitry. 6. the physical pin layout of smart card reader connector must match with the pin ar rangement of the 2x7 connector in ite schematics. 2)3v sb should be routed with a minimum trace width of 12 mils. 3.for the 3vsb circuits : 1)place the 0.1uf cap acitor of pin27 close to ite i/o chip. atx power supply slpsx# slp_s5# south bridge (pin 17) pwrctl# (pin 16) (pin 18) IT8711F sio_wakeup pwbtout# pwbtin# pson# (pin 19) system on/off button (or slp_s3#) it-8711-cg-s01 v0.2 0.2 layout & routing guideline ite, inc. 5 5 mo nday, january 07, 2002 title size document number rev date: sheet of vcch 3vsb vcch 3vsb 8.2k 20k 8.2k
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