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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with nec electronics sales representative for availability and additional information. mos integrated circuit pd44321181, 44321321, 44321361 32m-bit zerosb tm sram flow through operation document no. m15958ej1v0ds00 (1st edition) date published december 2002 ns cp(k) printed in japan preliminary data sheet 2002 the mark shows major revised points. description the pd44321181 is a 2,097,152-word by 18-bit, the pd44321321 is a 1,048,576-word by 32-bit and the pd44321361 is a 1,048,576-word by 36-bit zerosb static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. the pd44321181, pd44321321 and pd44321361 are optimized to eliminate dead cycles for read to write, or write to read transitions. these zerosb static rams integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as sram core. all input registers are controlled by a positive edge of the single clock input (clk). the pd44321181, pd44321321 and pd44321361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. zz has to be set low at the normal operation. when zz is set high, the sram enters power down state (?sleep?). in the ?sleep? state, the sram internal state is preserved. when zz is set low again, the sram resumes normal operation. the pd44321181, pd44321321 and pd44321361 are packaged in 100-pin plastic lqfp with a 1.4 mm package thickness or 165-pin plastic fbga for high density and low capacitive loading. features ? low voltage core supply: v dd = 3.3 0.165v (-a65, -a75, -a85, -a65y, -a75y, -a85y) v dd = 2.5 0.125v (-c75, -c85, -c75y, -c85y) ? synchronous operation ? operating temperature : t a = 0 to 70 c (-a65, -a75, -a85, -c75, -c85) t a = ?40 to +85 c (-a65y, -a75y, -a85y, -c75y, -c85y) ? 100 percent bus utilization ? internally self-timed write control ? burst read / write : interleaved burst and linear burst sequence ? fully registered inputs and outputs for flow through operation ? all registers triggered off positive clock edge ? 3.3v or 2.5v lvttl compatible : all inputs and outputs ? fast clock access time : 6.5 ns (133 mhz), 7.5 ns (117 mhz), 8.5 ns (100 mhz) ? asynchronous output enable : /g ? burst sequence selectable : mode ? sleep mode : zz (zz = open or low : normal operation) ? separate byte write enable : /bw1 to /bw4 ( pd44321321 and pd44321361) /bw1 and /bw2 ( pd44321181) ? three chip enables for easy depth expansion ? common i/o using three state outputs
2 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 ordering information (1/2) part number access time ns clock frequency mhz core supply voltage v i/o interface operating temperature c package pd44321181gf-a65 6.5 133 3.3 0.165 3.3 v or 0 to 70 100-pin plastic lqfp pd44321181gf-a75 7.5 117 2.5 v lvttl (14 x 20) pd44321181gf-a85 8.5 100 pd44321321gf-a65 6.5 133 pd44321321gf-a75 7.5 117 pd44321321gf-a85 8.5 100 pd44321361gf-a65 6.5 133 pd44321361gf-a75 7.5 117 pd44321361gf-a85 8.5 100 pd44321181gf-c75 7.5 117 2.5 0.125 2.5 v lvttl pd44321181gf-c85 8.5 100 pd44321321gf-c75 7.5 117 pd44321321gf-c85 8.5 100 pd44321361gf-c75 7.5 117 pd44321361gf-c85 8.5 100 pd44321181f1-a65-fq2 note 6.5 133 3.3 0.165 3.3 v or 165-pin plastic fbga pd44321181f1-a75-fq2 note 7.5 117 2.5 v lvttl (15 x 17) pd44321181f1-a85-fq2 note 8.5 100 pd44321321f1-a65-fq2 note 6.5 133 pd44321321f1-a75-fq2 note 7.5 117 pd44321321f1-a85-fq2 note 8.5 100 pd44321361f1-a65-fq2 note 6.5 133 pd44321361f1-a75-fq2 note 7.5 117 pd44321361f1-a85-fq2 note 8.5 100 pd44321181f1-c75-fq2 note 7.5 117 2.5 0.125 2.5 v lvttl pd44321181f1-c85-fq2 note 8.5 100 pd44321321f1-c75-fq2 note 7.5 117 pd44321321f1-c85-fq2 note 8.5 100 pd44321361f1-c75-fq2 note 7.5 117 pd44321361f1-c85-fq2 note 8.5 100 note under development
3 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 (2/2) part number access time ns clock frequency mhz core supply voltage v i/o interface operating temperature c package pd44321181gf-a65y 6.5 133 3.3 0.165 3.3 v or ?40 to +85 100-pin plastic lqfp pd44321181gf-a75y 7.5 117 2.5 v lvttl (14 x 20) pd44321181gf-a85y 8.5 100 pd44321321gf-a65y 6.5 133 pd44321321gf-a75y 7.5 117 pd44321321gf-a85y 8.5 100 pd44321361gf-a65y 6.5 133 pd44321361gf-a75y 7.5 117 pd44321361gf-a85y 8.5 100 pd44321181gf-c75y 7.5 117 2.5 0.125 2.5 v lvttl pd44321181gf-c85y 8.5 100 pd44321321gf-c75y 7.5 117 pd44321321gf-c85y 8.5 100 pd44321361gf-c75y 7.5 117 pd44321361gf-c85y 8.5 100 pd44321181f1-a65y-fq2 note 6.5 133 3.3 0.165 3.3 v or 165-pin plastic fbga pd44321181f1-a75y-fq2 note 7.5 117 2.5 v lvttl (15 x 17) pd44321181f1-a85y-fq2 note 8.5 100 pd44321321f1-a65y-fq2 note 6.5 133 pd44321321f1-a75y-fq2 note 7.5 117 pd44321321f1-a85y-fq2 note 8.5 100 pd44321361f1-a65y-fq2 note 6.5 133 pd44321361f1-a75y-fq2 note 7.5 117 pd44321361f1-a85y-fq2 note 8.5 100 pd44321181f1-c75y-fq2 note 7.5 117 2.5 0.125 2.5 v lvttl pd44321181f1-c85y-fq2 note 8.5 100 pd44321321f1-c75y-fq2 note 7.5 117 pd44321321f1-c85y-fq2 note 8.5 100 pd44321361f1-c75y-fq2 note 7.5 117 pd44321361f1-c85y-fq2 note 8.5 100 note under development
4 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 pin configurations / indicates active low signal. 100-pin plastic lqfp (14 20) [ pd44321181gf] marking side nc nc nc v dd q v ss q nc nc i/o9 i/o10 v ss q v dd q i/o11 i/o12 v ss v dd v dd v ss i/o13 i/o14 v dd q v ss q i/o15 i/o16 i/op2 nc v ss q v dd q nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a20 nc nc v dd q v ss q nc i/op1 i/o8 i/o7 v ss q v dd q i/o6 i/o5 v ss v ss v dd zz i/o4 i/o3 v dd q v ss q i/o2 i/o1 nc nc v ss q v dd q nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 nc nc /bw2 /bw1 /ce2 v dd v ss clk /we /cke /g adv a18 a17 a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a19 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawing for the 1-pin index mark.
5 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 pin identifications [ pd44321181gf] symbol pin no. description a0 to a20 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, synchronous address input 44, 45, 46, 47, 48, 49, 50, 83, 84, 43, 80 i/o1 to i/o16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, synchronous data in, 18, 19, 22, 23 synchronous / asynchronous data out i/op1 74 synchronous data in (parity), i/op2 24 synchronous / asynchronous data out (parity) adv 85 synchronous address load / advance input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /we 88 synchronous write enable input /bw1, /bw2 93, 94 synchronous byte write enable input /g 86 asynchronous output enable input clk 89 clock input /cke 87 synchronous clock enable input mode 31 asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 15, 16, 41, 65, 91 power supply v ss 14, 17, 40, 66, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, no connection 51, 52, 53, 56, 57, 75, 78, 79, 95, 96
6 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 100-pin plastic lqfp (14 20) [ pd44321321gf, pd44321361gf] marking side i/op3, nc i/o17 i/o18 v dd q v ss q i/o19 i/o20 i/o21 i/o22 v ss q v dd q i/o23 i/o24 v ss v dd v dd v ss i/o25 i/o26 v dd q v ss q i/o27 i/o28 i/o29 i/o30 v ss q v dd q i/o31 i/o32 i/op4, nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/op2, nc i/o16 i/o15 v dd q v ss q i/o14 i/o13 i/o12 i/o11 v ss q v dd q i/o10 i/o9 v ss v ss v dd zz i/o8 i/o7 v dd q v ss q i/o6 i/o5 i/o4 i/o3 v ss q v dd q i/o2 i/o1 i/op1, nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /we /cke /g adv a18 a17 a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a19 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawing for the 1-pin index mark.
7 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 [ pd44321321gf, pd44321361gf] symbol pin no. description a0 to a19 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, synchronous address input 45, 46, 47, 48, 49, 50, 83, 84, 43 i/o1 to i/o32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, synchronous data in, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, synchronous / asynchronous data out 18, 19, 22, 23, 24, 25, 28, 29 i/op1, nc note 51 synchronous data in (parity), i/op2, nc note 80 synchronous / asynchronous data out (parity) i/op3, nc note 1 i/op4, nc note 30 adv 85 synchronous address load / advance input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /we 88 synchronous write enable input /bw1 to /bw4 93, 94, 95, 96 synchronous byte write enable input /g 86 asynchronous output enable input clk 89 clock input /cke 87 synchronous clock enable input mode 31 asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 15, 16, 41, 65, 91 power supply v ss 14, 17, 40, 66, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 38, 39, 42 no connection note nc (no connection) is used in the pd44321321gf. i/op1 to i/op4 are used in the pd44321361gf.
8 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 165-pin plastic fbga (15 x 17) [ pd44321181f1] top view 1 234567891011 a nc a7 /ce /bw2 nc /ce2 /cke adv a17 a9 a20 b nc a6 ce2 nc /bw1 clk /we /g a18 a8 nc cnc ncv dd qv ss v ss v ss v ss v ss v dd qnc i/op1 dnc i/o9v dd qv dd v ss v ss v ss v dd v dd qnc i/o8 e nc i/o10 v dd qv dd v ss v ss v ss v dd v dd qnc i/o7 f nc i/o11 v dd qv dd v ss v ss v ss v dd v dd qnc i/o6 g nc i/o12 v dd qv dd v ss v ss v ss v dd v dd qnc i/o5 hnc v dd nc v dd v ss v ss v ss v dd nc nc zz j i/o13 nc v dd qv dd v ss v ss v ss v dd v dd qi/o4 nc k i/o14 nc v dd qv dd v ss v ss v ss v dd v dd qi/o3 nc l i/o15 nc v dd qv dd v ss v ss v ss v dd v dd qi/o2 nc m i/o16 nc v dd qv dd v ss v ss v ss v dd v dd qi/o1 nc n i/op2 nc v dd qv ss nc nc nc v ss v dd qnc nc p nc nc a4 a12 tdi a1 tdo a19 a13 a14 nc r mode a5 a3 a2 tms a0 tck a10 a11 a15 a16 remark refer to package drawings for the index mark.
9 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 [ pd44321181f1] symbol pin no. description a0 to a20 6r, 6p, 4r, 3r, 3p, 2r, 2b, 2a, 10b, 10a, 8r, 9r, synchronous address input 4p, 9p, 10p, 10r, 11r, 9a, 9b, 8p, 11a i/o1 to i/o16 10m, 10l, 10k, 10j, 11g, 11f, 11e, 11d, 2d, 2e, synchronous data in, 2f, 2g, 1j, 1k, 1l, 1m synchronous / asynchronous data out i/op1 11c synchronous data in (parity), i/op2 1n synchronous / asynchronous data out (parity) adv 8a synchronous address load / advance input /ce, ce2, /ce2 3a, 3b, 6a synchronous chip enable input /we 7b synchronous write enable input /bw1, /bw2 5b, 4a synchronous byte write enable input /g 8b asynchronous output enable input clk 6b clock input /cke 7a synchronous clock enable input mode 1r asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 11h asynchronous power down state input v dd 2h, 4d, 4e, 4f, 4g, 4h, 4j, 4k, 4l, 4m, 8d, 8e, power supply 8f, 8g, 8h, 8j, 8k, 8l, 8m v ss 4c, 4n, 5c, 5d, 5e, 5f, 5g, 5h, 5j, 5k, 5l, 5m, ground 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6k, 6l, 6m, 7c, 7d, 7e, 7f, 7g, 7h, 7j, 7k, 7l, 7m, 8c, 8n v dd q 3c, 3d, 3e, 3f, 3g, 3j, 3k, 3l, 3m, 3n, 9c, 9d, output buffer power supply 9e, 9f, 9g, 9j, 9k, 9l, 9m, 9n nc 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1p, 2c, 2j, 2k, no connection 2l, 2m, 2n, 2p, 3h, 4b, 5a, 5n, 6n, 7n, 9h, 10c, 10d, 10e, 10f, 10g, 10h, 10n, 11b, 11j, 11k, 11l, 11m, 11n, 11p tms 5r test mode select (jtag) tdi 5p test data input (jtag) tck 7r test clock input (jtag) tdo 7p test data output (jtag)
10 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 165-pin plastic fbga (15 x 17) [ pd44321321f1, pd44321361f1] top view 1 234567891011 a nc a7 /ce /bw3 /bw2 /ce2 /cke adv a17 a9 nc b nc a6 ce2 /bw4 /bw1 clk /we /g a18 a8 nc c i/op3,nc nc v dd qv ss v ss v ss v ss v ss v dd qnci/op2,nc d i/o17 i/o21 v dd qv dd v ss v ss v ss v dd v dd q i/o16 i/o12 e i/o18 i/o22 v dd qv dd v ss v ss v ss v dd v dd q i/o15 i/o11 f i/o19 i/o23 v dd qv dd v ss v ss v ss v dd v dd q i/o14 i/o10 g i/o20 i/o24 v dd qv dd v ss v ss v ss v dd v dd qi/o13 i/o9 hnc v dd nc v dd v ss v ss v ss v dd nc nc zz j i/o25 i/o29 v dd qv dd v ss v ss v ss v dd v dd qi/o8 i/o4 k i/o26 i/o30 v dd qv dd v ss v ss v ss v dd v dd qi/o7 i/o3 l i/o27 i/o31 v dd qv dd v ss v ss v ss v dd v dd qi/o6 i/o2 m i/o28 i/o32 v dd qv dd v ss v ss v ss v dd v dd qi/o5 i/o1 n i/op4,nc nc v dd qv ss nc nc nc v ss v dd qnci/op1,nc p nc nc a4 a12 tdi a1 tdo a19 a13 a14 nc r mode a5 a3 a2 tms a0 tck a10 a11 a15 a16 remark refer to package drawings for the index mark.
11 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 [ pd44321321gf, pd44321361gf] symbol pin no. description a0 to a19 6r, 6p, 4r, 3r, 3p, 2r, 2b, 2a, 10b, 10a, 8r, 9r, synchronous address input 4p, 9p, 10p, 10r, 11r, 9a, 9b, 8p i/o1 to i/o32 11m, 11l, 11k, 11j, 10m, 10l, 10k, 10j, 11g, 11f, synchronous data in, 11e, 11d, 10g, 10f, 10e, 10d, 1d, 1e, 1f, 1g, 2d, synchronous / asynchronous data out 2e, 2f, 2g,1j, 1k, 1l, 1m, 2j, 2k, 2l, 2m i/op1, nc note 11n synchronous data in (parity), i/op2, nc note 11c synchronous / asynchronous data out (parity) i/op3, nc note 1c i/op4, nc note 1n adv 8a synchronous address load / advance input /ce, ce2, /ce2 3a, 3b, 6a synchronous chip enable input /we 7b synchronous write enable input /bw1 to /bw4 5b, 5a, 4a, 4b synchronous byte write enable input /g 8b asynchronous output enable input clk 6b clock input /cke 7a synchronous clock enable input mode 1r asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 11h asynchronous power down state input v dd 2h, 4d, 4e, 4f, 4g, 4h, 4j, 4k, 4l, 4m, 8d, 8e, 8f, power supply 8g, 8h, 8j, 8k, 8l, 8m v ss 4c, 4n, 5c, 5d, 5e, 5f, 5g, 5h, 5j, 5k, 5l, 5m, ground 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6k, 6l, 6m, 7c, 7d, 7e, 7f, 7g, 7h, 7j, 7k, 7l, 7m, 8c, 8n v dd q 3c, 3d, 3e, 3f, 3g, 3j, 3k, 3l, 3m, 3n, 9c, 9d, 9e, output buffer power supply 9f, 9g, 9j, 9k, 9l, 9m, 9n nc 1a, 1b, 1h, 1p, 2c, 2n, 2p, 3h, 5n, 6n, 7n, 9h, no connection 10c, 10h, 10n, 11a, 11b, 11p tms 5r test mode select (jtag) tdi 5p test data input (jtag) tck 7r test clock input (jtag) tdo 7p test data output (jtag) note nc (no connection) is used in the pd44321321gf. i/op1 to i/op4 are used in the pd44321361gf.
12 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 block diagrams [ pd44321181] a0 to a20 mode clk /cke adv /bw1 /bw2 /we /g /ce ce2 /ce2 address register 0 burst logic write address register write registry and data coherency control logic write drivers data steering adv k memory cell array 2,048 x 18 columns (37,748,736 bits) a1 a0 a1? a0? sense amplifiers read logic input register e output buffers e i/o1 to i/o16 i/op1, i/op2 21 19 21 21 21 18 18 18 18 zz power down control k 1,024 rows burst sequence [ pd44321181] interleaved burst sequence table (mode = v dd ) external address a20 to a2, a1, a0 1st burst address a20 to a2, a1, /a0 2nd burst address a20 to a2, /a1, a0 3rd burst address a20 to a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a20 to a2, 0, 0 a20 to a2, 0, 1 a20 to a2, 1, 0 a20 to a2, 1, 1 1st burst address a20 to a2, 0, 1 a20 to a2, 1, 0 a20 to a2, 1, 1 a20 to a2, 0, 0 2nd burst address a20 to a2, 1, 0 a20 to a2, 1, 1 a20 to a2, 0, 0 a20 to a2, 0, 1 3rd burst address a20 to a2, 1, 1 a20 to a2, 0, 0 a20 to a2, 0, 1 a20 to a2, 1, 0
13 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 [ pd44321321, pd44321361] a0 to a19 mode clk /cke adv /bw1 /bw2 /we /g /ce ce2 /ce2 address register 0 burst logic write address register write registry and data coherency control logic write drivers data steering adv k a1 a0 a1 ? a0 ? sense amplifiers read logic input register e output buffers e i/o1 to i/o32 i/op1 to i/op4 20 18 20 20 20 32/36 32/36 32/36 32/36 /bw3 /bw4 zz power down control k memory cell array 1,024 x 32 columns (33,554,432 bits) 1,024 x 36 columns (37,748,736 bits) 1,024 rows [ pd44321321, pd44321361] interleaved burst sequence table (mode = v dd ) external address a19 to a2, a1, a0 1st burst address a19 to a2, a1, /a0 2nd burst address a19 to a2, /a1, a0 3rd burst address a19 to a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a19 to a2, 0, 0 a19 to a2, 0, 1 a19 to a2, 1, 0 a19 to a2, 1, 1 1st burst address a19 to a2, 0, 1 a19 to a2, 1, 0 a19 to a2, 1, 1 a19 to a2, 0, 0 2nd burst address a19 to a2, 1, 0 a19 to a2, 1, 1 a19 to a2, 0, 0 a19 to a2, 0, 1 3rd burst address a19 to a2, 1, 1 a19 to a2, 0, 0 a19 to a2, 0, 1 a19 to a2, 1, 0
14 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 state diagram deselect begin read burst read begin write burst write write read read ds ds write read burst burst write read write read burst write burst ds burst ds ds command operation ds deselect read new read write new write burst burst read, burst write or continue deselect remarks 1. states change on the rising edge of the clock. 2. a stall or ignore clock edge cycle is not shown in the above diagram. this is because /cke high only blocks the clock (clk) input and does not change the state of the device.
15 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 asynchronous truth table operation /g i/o read cycle l data-out read cycle h high-z write cycle high-z, data-in deselected high-z remark : don?t care synchronous truth table operation /ce ce2 /ce2 adv /we /bws /cke clk i/o address note deselected h l ll h high-z none 1 deselected l l ll h high-z none 1 deselected hl ll h high-z none 1 continue deselected h ll h high-z none 1 read cycle / begin burst l h l l h ll h data-out external read cycle / continue burst h ll h data-out next write cycle / begin burst lhllllll h data-in external write cycle / continue burst h lll h data-in next write cycle / write abort l h l l l h l l h high-z external write cycle / write abort h hll h high-z next stall / ignore clock edge hl h ? current 2 notes 1. deselect status is held until new ?begin burst? entry. 2. if an ignore clock edge command occurs during a read operation, the i/o bus will remain active (low impedance). if it occurs during a write cycle, the bus will remain high impedance. no write operation will be performed during the ignore clock edge cycle. remarks 1. : don?t care 2. /bws = l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) are low. /bws = h means all byte write enables (/bw1, /bw2, /bw3 or /bw4) are high.
16 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 partial truth table for write enables [ pd44321181] operation /we /bw1 /bw2 read cycle h write cycle / byte 1 (i/o [1:8], i/op1) l l h write cycle / byte 2 (i/o [9:16], i/op2) l h l write cycle / all bytes l l l write abort / nop l h h remark : don?t care [ pd44321321, pd44321361] operation /we /bw1 /bw2 /bw3 /bw4 read cycle h write cycle / byte 1 (i/o [1:8], i/op1) l l h h h write cycle / byte 2 (i/o [9:16], i/op2) l h l h h write cycle / byte 3 (i/o [17:24], i/op3) l h h l h write cycle / byte 4 (i/o [25:32], i/op4) l h h h l write cycle / all bytes lllll write abort / nop l h h h h remark : don?t care zz (sleep) truth table zz chip status 0.2 v active open active v dd ? 0.2 v sleep
17 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit supply voltage v dd -a65, -a75, -a85 ?0.5 +4.0 v -a65y, -a75y, -a85y -c75, -c85 ?0.5 +3.0 -c75y, -c85y output supply voltage v dd q ?0.5 v dd v input voltage v in ?0.5 note v dd + 0.5 v input / output voltage v i/o ?0.5 note v dd q + 0.5 v operating ambient t a -a65, -a75, -a85, -c75, -c85 0 70 c temperature -a65y, -a75y, -a85y, -c75y, -c85y ?40 +85 storage temperature t stg ?55 +125 c note ?2.0 v (min.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (1/2) parameter symbol conditions -a65, -a75, -a85 unit -a65y, -a75y, -a85y min. typ. max. supply voltage v dd 3.135 3.3 3.465 v 2.5 v lvttl interface output supply voltage v dd q 2.375 2.5 2.9 v high level input voltage v ih 1.7 v dd q + 0.3 v low level input voltage v il ?0.3 note +0.7 v 3.3 v lvttl interface output supply voltage v dd q 3.135 3.3 3.465 v high level input voltage v ih 2.0 v dd q + v low level input voltage v il ?0.3 note +0.8 v note ?0.8 v (min.) (pulse width : 2 ns) recommended dc operating conditions (2/2) parameter symbol conditions -c75, -c85 unit -c75y, -c85y min. typ. max. supply voltage v dd 2.375 2.5 2.625 v output supply voltage v dd q 2.375 2.5 2.625 v high level input voltage v ih 1.7 v dd q + 0.3 v low level input voltage v il ?0.3 note +0.7 v note ?0.8 v (min.) (pulse width : 2 ns)
18 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 dc characteristics (v dd = 3.3 0.165 v or 2.5 0.125 v) parameter symbol test condition min. typ. max. unit input leakage current i li v in (except zz, mode) = 0 v to v dd ?2 +2 a i/o leakage current i lo v i/o = 0 v to v dd q, outputs are disabled. ?2 +2 a operating supply current i dd device selected, -a65 310 ma cycle = max. -a65y v in v il or v in v ih , -a75, -c75 290 i i/o = 0 ma -a75y, -c75y -a85, -c85 270 -a85y, -c85y standby supply current i sb device deselected, cycle = 0 mhz, 70 ma v in v il or v in v ih , all inputs are static. i sb1 device deselected, cycle = 0 mhz, 60 v in 0.2 v or v in v dd ? 0.2 v, v i/o 0.2 v, all inputs are static. i sb2 device deselected, cycle = max. 110 v in v il or v in v ih power down supply current i sbzz zz v dd ? 0.2 v, v i/o v dd q + 0.2 v 60 ma 2.5 v lvttl interface high level output voltage v oh i oh = ?2.0 ma 1.7 v i oh = ?1.0 ma 2.1 low level output voltage v ol i ol = +2.0 ma 0.7 v i ol = +1.0 ma 0.4 3.3 v lvttl interface high level output voltage v oh i oh = ?4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v capacitance (t a = 25 c, f = 1mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 6.0 pf input / output capacitance c i/o v i/o = 0 v 8.0 pf clock input capacitance c clk v clk = 0 v 6.0 pf remark these parameters are periodically sampled and not 100 % tested.
19 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 ac characteristics (v dd = 3.3 0.165 v or 2.5 0.125 v) ac test conditions 2.5 v lvttl interface input waveform (rise / fall time 2.4 ns) test points v ss 2.4 v 1.2 v 1.2 v output waveform test points 1.2 v 1.2 v 3.3 v lvttl interface input waveform (rise / fall time 3.0 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load condition c l : 30 pf 5 pf (tkhqx1, tkhqx2, tglqx, tghqz, tkhqz) figure external load at test v t = +1.2 v / +1.5 v i/o (output) 50 ? z o = 50 ? c l remark c l includes capacitances of the probe and jig, and stray capacitances.
20 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 read and write cycle parameter symbol -a65 -a75, -c75 -a85, -c85 unit notes -a65y -a75y, -c75y -a85y, -c85y (133 mhz) (117 mhz) (100 mhz) standard alias min. max. min. max. min. max. cycle time tkhkh tcyc 7.5 ? 8.6 ? 10 ? ns clock access time tkhqv tcd ?6.5?7.5?8.5 ns output enable access time tglqv toe ?3.5?3.5?3.5 ns clock high to output active tkhqx1 tdc1 2.5?2.5?2.5? ns 1, 2 clock high to output change tkhqx2 tdc2 2.5?2.5?2.5? ns output enable to output active tglqx tolz 0?0?0? ns 1 output disable to output high-z tghqz tohz 03.503.503.5 ns 1 clock high to output high-z tkhqz tcz 2.552.552.55 ns 1, 2 clock high pulse width tkhkl tch 2.5?2.5?2.5? ns clock low pulse width tklkh tcl 2.5?2.5?2.5? ns setup times address tavkh tas 1.5 ? 1.5 ? 2 ? ns address advance tadvvkh tadvs clock enable tevkh tces chip enable tcvkh tcss data in tdvkh tds write enable twvkh tws hold times address tkhax tah 0.5?0.5?0.5? ns address advance tkhadvx tadvh clock enable tkhex tceh chip enable tkhcx tcsh data in tkhdx tdh write enable tkhwx twh power down entry time tzze tzze ?7.5?8.6? 10 ns power down recovery time tzzr tzzr ?7.5?8.6? 10 ns notes 1. transition is measured 200 mv from steady state. 2. to avoid bus contention, the output buffers are designed such that tkhqz (device turn-off) is faster than tkhqx1 (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because tkhqx1 is a min. parameter that is worse case at totally different conditions (t a min., v dd max.) than tkhqz, which is a max. parameter (worse case at t a max., v dd min.).
21 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 read / write cycle write d (a1) clk /cke /ces adv /we data in data out /g /bws address command 12345678910 d (a1) d (a2) d (a2+1) d (a5) q (a3) q (a4) q (a4+1) q (a6) q (a7) write d (a2) burst write d (a2+1) read q (a3) read q (a4) burst read q (a4+1) write d (a5) read q (a6) write q (a7) deselect tkhkh tevkh tkhex tcvkh tkhcx tklkh tdvkh tkhdx tkhqx1 tkhqv tkhqx2 tghqz tglqx tkhqx2 tglqv tkhqz tkhkl tadvvkh tkhadvx twvkh tkhwx twvkh tkhwx note 1 note 2 a2 a7 tavkh tkhax a1 a3 a4 a5 a6 high-z high-z high-z high-z high-z notes 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. 2. /bws refers to /bw1, /bw2, /bw3 and /bw4. when /bws is low, any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) are low.
22 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 nop, stall and deselect cycle 12345678910 write d (a1) clk /cke /ces adv /we data in data out /bws address command d (a1) d (a4) q (a2) q (a3) q (a5) read q (a2) stall read q (a3) write d (a4) stall nop read q (a5) deselect continue deselect tkhqx2 tkhqz a2 a1 a3 a4 a5 high-z high-z high-z high-z high-z high-z
23 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 power down (zz) cycle 12345678910 clk /cke adv /we /g data out /bws address q (a1) a1 11 12 q1 (a2) q2 (a2) zz tkhkh tkhkl tklkh tzze tzzr power down (i sbzz ) state a2 /ces note note high-z high-z note /we or /ces must be held high at clk rising edge (clock edge no.3 in this figure) prior to power down state entry.
24 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 jtag specifications only the 165-pin plastic fbga package of pd44321181, pd44321321 and pd44321361 support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name description tck test clock input. all input are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select. this is the command input for the tap controller state machine. tdi test data input. this is the input side of the serial registers placed between tdi and tdo.the register placed between tdi and tdo is deter-mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. remark the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the tap controller state is also reset on the sram power-up. jtag dc characteristics (v dd = 3.3 0.165 v) (1/2) parameter symbol conditions min. typ. max. unit note jtag input leakage current i li 0 v v in v dd ?5.0 ? +5.0 a jtag i/o leakage current i lo 0 v v in v dd q , ?5.0 ? +5.0 a outputs disabled jtag input high voltage v ih 2.0 ? v dd +0.3 v jtag input low voltage v il ?0.3 ? +0.5 v jtag output high voltage v oh i oh = ?4 ma 2.4 ? ? v jtag output low voltage v ol i ol = 8 ma ? ? 0.4 v jtag dc characteristics (v dd = 2.5 0.125 v) (2/2) parameter symbol conditions min. typ. max. unit note jtag input leakage current i li 0 v v in v dd ?5.0 ? +5.0 a jtag i/o leakage current i lo 0 v v in v dd q , ?5.0 ? +5.0 a outputs disabled jtag input high voltage v ih 1.7 ? v dd +0.3 v jtag input low voltage v il ?0.3 ? +0.5 v jtag output high voltage v oh i oh = ?2.0 ma 1.7 v i oh = ?1.0 ma 2.1 jtag output low voltage v ol i ol = +2.0 ma 0.7 v i ol = +1.0 ma 0.4
25 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 jtag ac test conditions [-a65, -a75, -a85, -a65y, -a75y, -a85y] input waveform (rise / fall time 1 ns ) output waveform [-c75, -c85, -c75y, -c85y] input waveform (rise / fall time 1 ns ) output waveform output load tdo z o = 50 ? 20 pf 50 ? v tt = 1.2 v / 1.5 v test points 1.5 v 1.5 v test points 1.2 v 1.2 v test points 1.2 v 1.2 v 0 v 2.4 v
26 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 jtag ac characteristics parameter symbol conditions min. typ. max. unit note clock cycle time (tck) t thth 100 ? ns clock phase time (tck) t thtl / t tlth 40 ? ns setup time (tms / tdi) t mvth / t dvth 10 ? ns hold time (tms / tdi) t thmx / t thdx 10 ? ns tck low to tdo valid (tdo) t tlqv ?20ns jtag timing diagram
27 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 scan register definition (1) register name description instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run-test/idle or the various data register state. the register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe which device bump connects to each boundary register location. the first column defines the bit?s position in the boundary register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. scan register definition (2) register name bit size unit instruction register 3 bit bypass register 1 bit id register 32 bit boundary register 77 bit id register definition part number organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit pd44321181 2m x 18 xxxx 0000 0000 0010 1000 00000010000 1 pd44321321 1m x 32 xxxx 0000 0000 0010 1001 00000010000 1 pd44321361 1m x 36 xxxx 0000 0000 0010 1010 00000010000 1
28 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 scan exit order [ pd44321321 (1m words by 32 bits) ] [ pd44321181 (2m words by 18 bits) ] [ pd44321361 (1m words by 36 bits) ] bit no. signal name bump id bit no. signal name bump id bit no. signal name bump id bit no. signal name bump id 1 nc 6n 40 /ce2 6a 1 nc 6n 40 /ce2 6a 2 a19 8p 41 /bw1 5b 2 a19 8p 41 /bw1 5b 3 a10 8r 42 nc 5a 3 a10 8r 42 /bw2 5a 4 a11 9r 43 /bw2 4a 4 a11 9r 43 /bw3 4a 5 a13 9p 44 nc 4b 5 a13 9p 44 /bw4 4b 6 a14 10p 45 ce2 3b 6 a14 10p 45 ce2 3b 7 a15 10r 46 /ce 3a 7 a15 10r 46 /ce1 3a 8 a16 11r 47 a7 2a 8 a16 11r 47 a7 2a 9 nc 11p 48 a6 2b 9 nc 11p 48 a6 2b 10 zz 11h 49 nc 1b 10 zz 11h 49 nc 1b 11 nc 11n 50 nc 1a 11 i/op1, nc 11n 50 nc 1a 12 nc 11m 51 nc 1c 12 i/o1 11m 51 i/op3, nc 1c 13 nc 11l 52 nc 1d 13 i/o2 11l 52 i/o17 1d 14 nc 11k 53 nc 1e 14 i/o3 11k 53 i/o18 1e 15 nc 11j 54 nc 1f 15 i/o4 11j 54 i/o19 1f 16 i/o1 10m 55 nc 1g 16 i/o5 10m 55 i/o20 1g 17 i/o2 10l 56 i/o9 2d 17 i/o6 10l 56 i/o21 2d 18 i/o3 10k 57 i/o10 2e 18 i/o7 10k 57 i/o22 2e 19 i/o4 10j 58 i/o11 2f 19 i/o8 10j 58 i/o23 2f 20 i/o5 11g 59 i/o12 2g 20 i/o9 11g 59 i/o24 2g 21 i/o6 11f 60 i/o13 1j 21 i/o10 11f 60 i/o25 1j 22 i/o7 11e 61 i/o14 1k 22 i/o11 11e 61 i/o26 1k 23 i/o8 11d 62 i/o15 1l 23 i/o12 11d 62 i/o27 1l 24 i/op1 11c 63 i/o16 1m 24 i/o13 10g 63 i/o28 1m 25 nc 10f 64 i/op2 1n 25 i/o14 10f 64 i/o29 2j 26 nc 10e 65 nc 2k 26 i/o15 10e 65 i/o30 2k 27 nc 10d 66 nc 2l 27 i/o16 10d 66 i/o31 2l 28 nc 10g 67 nc 2m 28 i/op2, nc 11c 67 i/o32 2m 29 a20 11a 68 nc 2j 29 nc 11a 68 i/op4, nc 1n 30 nc 11b 69 a5 2r 30 nc 11b 69 a5 2r 31 a9 10a 70 mode 1r 31 a9 10a 70 mode 1r 32 a8 10b 71 a4 3p 32 a8 10b 71 a4 3p 33 a17 9a 72 a3 3r 33 a17 9a 72 a3 3r 34 a18 9b 73 a2 4r 34 a18 9b 73 a2 4r 35 adv 8a 74 a12 4p 35 adv 8a 74 a12 4p 36 /g 8b 75 a1 6p 36 /g 8b 75 a1 6p 37 /cke 7a 76 a0 6r 37 /cke 7a 76 a0 6r 38 /we 7b 38 /we 7b 39 clk 6b 39 clk 6b
29 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 jtag instructions instructions description extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore this device is not 1149.1 compliant. nevertheless, this rams tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instruction register the ram responds just as it does in response to the sample instruction, except the ram output are forced to high impedance any time the instruction is loaded. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample sample is a standard 1149.1 mandatory public instruction. when the sample instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. this functionality is not standard 1149.1 compliant. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high impedance) and the boundary register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag instruction cording ir2 ir1 ir0 instruction note 000 extest 1 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note 1. tristate all data drivers and capture the pad values into a serial scan latch.
30 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 tap controller state diagram disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1 k ? resistor. tdo should be left unconnected.
31 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 test logic operation (instruction scan) tck contoroller state tdi tms tdo test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle idcode instruction register state new instruction output inactive
32 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 test logic (data scan) controller state tdi tms tdo run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr shift-dr exit1-dr update-dr test-logic-reset instruction instructin register state idcode run-test/idle select-dr-scan select-ir-scan output inactive tck
33 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 package drawings 100-pin plastic lqfp (14x20) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 22.0 0.2 20.0 0.2 0.65 (t.p.) 0.575 j 16.0 0.2 k c 14.0 0.2 i 0.13 1.0 0.2 l 0.5 0.2 f 0.825 n p q 0.10 1.4 0.125 0.075 s100gf-65-8et-1 s 1.7 max. h 0.32 + 0.08 ? 0.07 m 0.17 + 0.06 ? 0.05 r3 + 7 ? 3 m 80 81 51 50 30 31 100 1 s s n j detail of lead end c d a b r k m l p i s q g f h
34 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 y1 s s y s a b s a b x m b e a1 h a2 a index mark d zd ze rpnmlkjhgfedcba 11 10 9 8 7 6 5 4 3 2 1 a s w b s e w item millimeters d e zd ze e h a a1 a2 b y x w y1 15.00 17.00 2.50 1.50 1.00 0.60 1.40 0.40 1.00 0.45 0.08 0.08 0.15 0.20 this package drawing is a preliminary version. it may be changed in the future. 165-pin plastic fbga (15x17)
35 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 recommended soldering condition please consult with our sales offices for soldering conditions of the pd44321181, pd44321321 and pd44321361. types of surface mount devices pd44321181gf : 100-pin plastic lqfp (14 x 20) pd44321321gf : 100-pin plastic lqfp (14 x 20) pd44321361gf : 100-pin plastic lqfp (14 x 20) pd44321181f1-fq2 : 165-pin plastic fbga (15 x 17) pd44321321f1-fq2 : 165-pin plastic fbga (15 x 17) pd44321361f1-fq2 : 165-pin plastic fbga (15 x 17)
36 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 1st edition/ throughout throughout modification ? preliminary product information dec. 2002 preliminary data sheet deletion ? pd44321161 addition ? extended operating temperature products (t a = ? 40 to +85 c) pp.2, 3 pp.2, 3 addition ordering information under development (165-pin plastic fbga (15 x 17)) p.27 p.27 addition id register definition addition of id [27:12] part no.
37 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 [memo]
38 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 [memo]
39 preliminary data sheet m15958ej1v0ds pd44321181, 44321321, 44321361 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd44321181, 44321321, 44321361 zerosb is a trademark of nec electronics corporation. the information in this document is current as of december, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec e lectronics endeavors to enhance the quality, reliability and safety of nec e lectronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec e lectronics product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec e lectronics" as used in this statement means nec electronics c orporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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