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power management 1 www.semtech.com sc1211 high speed, combi-sense tm synchronous mosfet driver features applications october 12, 2003 the sc1211 is a high speed, combi-sense tm , dual out- put driver designed to drive high-side and low-side mosfets in a synchronous buck converter. these drivers combined with combi-sense pwm controllers, such as semtech sc2643vx or sc2643, provide a cost effective multi-phase voltage regulator for advanced microprocessors. the combi-sense tm is a technique to sense the inductor current for peak current mode control of voltage regula- tor without using sensing resistor. it provides the follow- ing advantages: - no costly precision sensing resistor - lossless current sensing - high level noise free signal - fast response - suitable for wide range of duty cycle - only two small signal components (third optional) the detailed explanation of the technique can be found in the applications information section. a 30ns max propagation delay from input transition to the gate of the power fet?s guarantees operation at high switching frequencies. internal overlap protection circuit prevents shoot-through from vin to pgnd in the main and synchronous mosfets. the adaptive overlap pro- tection circuit ensures the bottom fet does not turn on until the top fet source has reached 1v, to prevent cross- conduction. 8.5v gate drive provides optimum enhancement of mosfets at minimum driver and mosfet switching loss. high current drive capability allows fast switching, thus reducing switching losses at high (up to 1.5mhz) frequen- cies without causing thermal stress on the driver. under-voltage-lockout and over-temperature shutdown features are included for proper and safe operation. timed latches and improved robustness are built into the housekeeping functions such as the under voltage lockout and adaptive shoot-through protection circuitry to prevent false triggering and to assure safe operation. the sc1211 is offered in a power soic-8l package. high efficiency +12v supply voltage with internal ldo for optimum gate drive high peak drive current adaptive non-overlapping gate drives provide shoot-through protection support combi-sense tm and vid-on-fly operations fast rise and fall times (15ns typical with 3000pf load) ultra-low (<30ns) propagation delay (bg going low) floating top gate drive crowbar function for over voltage protection high frequency (to 1.5 mhz) operation allows use of small inductors and low cost ceramic capacitors under-voltage-lockout low quiescent current intel pentium ? processor power supplies amd athlon tm and amd-k8 tm processor power supplies high current low voltage dc-dc converter s description
2 ? 2003 semtech corp. www.semtech.com power management sc1211 typical application circuit vid4 r3 1r0 + c18 1800uf/6.3v c39 1nf vin c8 2.2nf r16 100k vcore r27 100 c30 1uf c3 4.7uf vpn3 c38 1nf r2 1r0 r5 22.1k r22 1r0 + c5 1800uf/6.3v c6 0.1uf r18 250k l2 900nh 1 2 p4gnd r26 100 u4 sc1211 1 2 3 4 6 7 8 9 5 drn tg bst co vin vreg bg pgnd vpn r25 optional c12 4.7nf +12v r24 0r0 q1 vcore r9 33.2k c17 4.7uf r7 931 u3 sc1211 1 2 3 4 6 7 8 9 5 drn tg bst co vin vreg bg pgnd vpn vid0 + c27 1800uf/6.3v c37 1nf c26 4.7uf d3 d1n4148 q2 c11 4.7uf r19 1r0 vpn1 c23 0.1uf + c29 1800uf/6.3v c31 4.7uf c36 0.1uf c21 470pf vpn1 vin c13 4.7nf r8 301 r11 33.2k c22 1uf c25 2.2nf u1 sc1211 1 2 3 4 6 7 8 9 5 drn tg bst co vin vreg bg pgnd vpn c34 2.2nf c20 1uf + c19 1800uf/6.3v q3 + c32 1800uf/6.3v vpn2 d2 d1n4148 r23 1r0 c2 1uf + c9 1800uf/6.3v d1 d1n4148 + c14 1800uf/6.3v l1 640nh 1 2 r21 3.7k + c33 1800uf/6.3v vid3 vid1 c16 1uf vid5 r17 10k r1 2r2 vpn3 vpn1 vpn3 c35 4.7uf l3 900nh 1 2 vpn2 vid_pwrgd vin r6 22.1k r12 500 + c24 1800uf/6.3v c4 4.7uf + c28 1500uf + c1 1500uf u2 sc2643vx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 os3 os2 os1 bgout errout gndsen fb dacstep vcc vid4 vid3 vid2 vid1 vid0 vid5 pgood oscref agnd out1 out2 out3 out4 outsen os4 vpn2 p4gnd r4 22.1k c10 4.7nf vid2 vcore + c15 1500uf q6 r20 optional q5 r13 21.5k pgood c7 3.3nf r14 10 r10 33.2k r15 1r0 l4 900nh 1 2 r28 100 vcc q4
3 ? 2003 semtech corp. www.semtech.com power management sc1211 electrical characteristics absolute maximum ratings unless specified: t a = 25c; v in = 12v; v reg = 8.5v r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u y l p p u s r e w o p e g a t l o v y l p p u sv n i 92 15 1v g n i t a r e p o , t n e r r u c t n e c s e i u qp o _ q i0 . 3a m t u o k c o l e g a t l o v r e d n u f o d l o h s e r h t t r a t sv g e r e g a t l o vv t r a t s _ g e r 43 . 4v s i s e r e t s y hs y h v o l v u 0 6 1v m o d l l a n r e t n i t u p t u o o d lv g e r v n i v 5 1 o t v 9 =5 . 8v e g a t l o v t u o p o r dv p o r d v n i v 8 . 8 o t v 5 =3 . 0v exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. r e t e m a r a pl o b m y ss n o i t i d n o cm u m i x a ms t i n u v n i e g a t l o v y l p p u sv n i 6 1v n r d o t t s bv n r d - t s b 1 1v n r d o t g tv n r d - g t 1 1 o t 3 . 0 -v e s l u p n r d o t g tv e s l u p - n r d - g t v k a e p t , e s l u p s n 0 2 < ) 2 ( 2 -v d n g p o t t s bv d n g p - t s b 0 4v e s l u p d n g p o t t s bv e s l u p - d n g - t s b t e s l u p s n 0 0 1 <5 4v d n g p o t n r dv d n g p - n r d 0 3 o t 2 -v e s l u p d n g p o t n r dv e s l u p - d n g p - n r d v k a e p t , e s l u p s n 0 0 2 < ) 2 ( 5 3 o t 5 -v v k a e p t , e s l u p s n 0 2 < ) 2 ( v - g e r 5 3 o tv d n g p o t g bv d n g p - g b 1 1 o t 3 . 0 -v e s l u p d n g p o t g bv e s l u p - d n g p - g b v k a e p t , e s l u p s n 0 2 < ) 2 ( 5 . 3 -v d n g p o t g e r vv d n g p - g e r 1 1v d n g p o t n p vv n p 6 1v e s l u p d n g p o t n p vv e s l u p - n p t e s l u p s n 0 0 1 <0 2v t u p n i m w po c5 . 8 o t 3 . 0 -v n o i t a p i s s i d r e w o p s u o u n i t n o cp d t a t , c 5 2 = j c 5 2 1 =6 5 . 2w e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h t c j 8w / c e g n a r e r u t a r e p m e t n o i t c n u jt j 0 5 1 + o t 0c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3c note: (1). this device is esd sensitive. use of standard esd handling precautions is required. (2). pulse width measured from 50% to 50% of peak voltage v peak .
4 ? 2003 semtech corp. www.semtech.com power management sc1211 r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u o c e g a t l o v t u p n i h g i h c i g o lv h _ o c 0 . 2v e g a t l o v t u p n i w o l c i g o lv l _ o c 8 . 0v n w o d t u h s l a m r e h t t n i o p p i r t e r u t a r e p m e t r e v ot p t o 5 5 1c s i s e r e t s y ht t s y h 0 1c ) g t ( r e v i r d e d i s h g i h e c n a d e p m i t u p t u o r g t _ c r s v t s b v - n r d v 5 . 8 = 5 . 10 . 3 ? r g t _ k n i s 0 . 10 . 2 e m i t e s i rt g t _ r v , f n 3 . 3 = l c t s b v - n r d v 5 . 8 =5 1s n e m i t l l a ft g t _ f v , f n 3 . 3 = l c t s b v - n r d v 5 . 8 =0 1s n h g i h g n i o g g t , y a l e d n o i t a g a p o r pt g t _ h d p v t s b v - n r d v 5 . 8 =7 3s n w o l g n i o g g t , y a l e d n o i t a g a p o r pt g t _ l d p v t s b v - n r d v 5 . 8 =0 3s n ) g b ( r e v i r d e d i s - w o l e c n a d e p m i t u p t u o r g b _ c r s v g e r v 5 . 8 = 5 . 10 . 3 ? r g b _ k n i s 5 . 10 . 3 e m i t e s i rt g b _ r v , f n 3 . 3 = l c g e r v 5 . 8 =0 1s n e m i t l l a ft g b _ f v , f n 3 . 3 = l c g e r v 5 . 8 =0 1s n h g i h g n i o g g b , y a l e d n o i t a g a p o r pt g b _ h d p v g e r v 5 . 8 =0 2s n w o l g n i o g g b , y a l e d n o i t a g a p o r pt g b _ l d p v g e r v 5 . 8 =7 2s n e m i t - f f o m u m i n i m g b ) 1 ( t g b _ f f o 5 7s n y a l e d e m i t t u o k c o l - e g a t l o v - r e d n u v g e r p u g n i p m a rt o l v u _ h d p 2s v g e r n w o d g n i p m a rt o l v u _ l d p 2s electrical characteristics (cont.) unless specified: t a = 25c; v in = 12v; v reg = 8.5v note: (1) guaranteed by design.
5 ? 2003 semtech corp. www.semtech.com power management sc1211 timing diagrams co t pdl_bg t f_bg t pdh_tg t r_tg bg tg t pdl_tg t f_tg t pdh_bg t r_bg ris in g ed ge tr ans it ion falling edge transition dr n 1.4v 1.0v
6 ? 2003 semtech corp. www.semtech.com power management sc1211 pin configuration ordering information note: (1) only available in tape and reel packaging. a reel con- tains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. e c i v e d ) 1 ( e g a k c a pt ( e g n a r p m e t j ) r t s 1 1 2 1 c s8 - o s p d ec 5 2 1 o t 0 t r t s 1 1 2 1 c s ) 2 ( 8 - o s p d ec 5 2 1 o t 0 pin descriptions # n i pe m a n n i pn o i t c n u f n i p 1n r d e b n a c n i p s i h t . r e t r e v n o c k c u b s u o n o r h c n y s e h t f o ) e d o n g n i h c t i w s r o ( e d o n e s a h p r e w o p e h t v - o t p u e k i p s e v i t a g e n a o t d e t c e j b u s g e r . n o i t a r e p o g n i t c e f f a t u o h t i w d n g p o t e v i t a l e r 2g t. t e f s o m ) p o t ( g n i h c t i w s e h t r o f e v i r d e t a g t u p t u o 3t s b g n i t a o l f e h t p o l e v e d o t s n i p n r d d n a t s b n e e w t e b d e t c e n n o c s i r o t i c a p a c a . n i p p a r t s t o o b . ) c i m a r e c ( f 1 y l l a c i p y t s i e u l a v r o t i c a p a c e h t . t e f s o m e d i s - h g i h e h t r o f e g a t l o v p a r t s t o o b 4o c m h o k 0 5 l a n r e t n i n a . r e l l o r t n o c l a n r e t x e y b d e i l p p u s 1 1 2 1 c s e h t o t l a n g i s t u p n i m w p l e v e l c i g o l . d n g p o t n i p s i h t m o r f d e t c e n n o c s i r o t s i s e r 5n p v e l b a n e o t t n i o p e s n e s t u p t u o e h t d n a n i p s i h t n e e w t e b c r n a t c e n n o c . e d o n e s a h p l a u t r i v e s n e s - i b m o c m t . t i u c r i c n o i t a c i l p p a l a c i p y t e h t e e s . n o i t a r e p o 6n i v l a n r e t n i e h t d n a o d l r o f r e w o p y l p p u se s n e s - i b m o c m t e h t f o l i a r r e w o p t u p n i o t t c e n n o c . y r t i u c r i c . r e t r e v n o c 7g e r v . ) m m 5 ( " 2 . 0 n a h t e r o m o n h t g n e l d a e l h t i w ) c i m a r e c ( f 7 . 4 o t f 1 h t i w e l p u o c e d . t u p t u o o d l 8g b. t e f s o m ) m o t t o b ( s u o n o r h c n y s e h t r o f e v i r d e t a g t u p t u o d a pd n g p . e c r u o s s t e f s o m s u o n o r h c n y s e h t o t e s o l c n i p s i h t p e e k . d n u o r g top view (power soic-8) tg vin bst 5 6 7 8 vreg vpn drn co bg 1 2 3 4 pgnd exposed pad must be soldered to power ground plane
7 ? 2003 semtech corp. www.semtech.com power management sc1211 block diagram pgnd vreg vpn tg ldo bst bg dr n co cont rol & ov erlap prot ection circ uit uv lo vin logic
8 ? 2003 semtech corp. www.semtech.com power management sc1211 applications information theor theor theor theor theor y of opera y of opera y of opera y of opera y of opera tion tion tion tion tion the sc1211 is a high speed, combi-sense tm , dual out- put driver designed to drive top and bottom mosfets in a synchronous buck converter. it features adaptive de- lay for shoot-through protection and vid-on-fly opera- tion; internal ldo for optimum gate drive voltage; and virtual phase node for combi-sense tm solution. these drivers combined with pwm controller sc2643vx form a multi-phase voltage regulator for advanced micropro- cessors. a three-phase voltage regulator with 12v input 60a output is shown in the typical application circuit sec- tion. startup and uvlo startup and uvlo startup and uvlo startup and uvlo startup and uvlo to startup the driver, a supply voltage is applied to vin pin of the sc1211. the top and bottom gates are held low until vin exceeds uvlo threshold of the driver, typi- cally 4.0v. then the top gate remains low and the bot- tom gate is pulled high to turn on the bottom fet. once vin exceeds uvlo threshold of the pwm controller, typi- cally 7.5v, the soft-start begins and the pwm signal takes fully control of the gate transitions. gat gat gat gat gat e t e t e t e t e t ransition and shoo ransition and shoo ransition and shoo ransition and shoo ransition and shoo t thr t thr t thr t thr t thr ough pr ough pr ough pr ough pr ough pr o o o o o t t t t t ection ection ection ection ection refer to the timing diagrams section, the rising edge of the pwm input initiates the bottom fet turn-off and the top fet turn-on. after a short propagation delay (t pdl_bg ), the bottom gate begins to fall (t f_bg ). an adaptive circuit in the sc1211 monitors the bottom gate voltage to drop below 1.4v. then after a preset delay time (t pdh_tg ) is expired, the top gate turns on. the delay time is set to be 20ns typically. this prevents the top fet from turning on until the bottom fet is off. during the transition, the inductor current is freewheeling through the body diode of either bottom fet or top fet, upon the direction of the inductor current. the phase node could be low (ground) or high (vin). the falling edge of the pwm input controls the top fet turn-off and the bottom fet turn-on. after a short propa- gation delay (t pdl_tg ), the top gate begins to fall (t f_tg ). as the inductor current is commutated from the top fet to the body diode of the bottom fet, the phase node begins to fall. the adaptive circuit in the sc1211 de- tects the phase node voltage. it holds the bottom fet off until the phase node voltage has dropped below 1.0v. this prevents the top and bottom fets from conducting simultaneously or shoot-through. minimum off-time for bottom gate minimum off-time for bottom gate minimum off-time for bottom gate minimum off-time for bottom gate minimum off-time for bottom gate during a load transient of the voltage regulator, the pwm controller could generate a very narrow pulse for the driver sc1211. the pulse is so narrow that it reaches the rising edge threshold of the sc1211 at one point then immediately falls below the falling edge threshold. to response such a pwm input, the bottom gate of the sc1211 has to pull down and pull up almost simulta- neously, resulting in a voltage spike at the bg pin. the spike could exceed the gate voltage rating and damage the gate. to prevent such fast gate transition, a mini- mum off-time (typically 75ns) for the bottom gate is de- signed in the sc1211. when the pwm input reaches the rising edge threshold of the sc1211, the bottom gate pulls low and will stay low for the minimum off-time no matter what the pwm input at the co pin is. vid-on-fly operation vid-on-fly operation vid-on-fly operation vid-on-fly operation vid-on-fly operation certain new processors have required to changing the vid dynamically during the operation, or refered as vid- on-fly operation. a vid-on-fly can occur under light load or heavy load conditions. at light load, it could force the converter to sink current. upon turn-off of the top fet, the reversed inductor current has to be freewheeling through the body diode of the top fet instead of the bottom fet. as a result, the phase node voltage remains high. the sc1211 incorporates the ability by pulling the bottom gate to high internally, which over rides the adap- tive circuit and turns the bottom fet on. the delay time from the pwm falling egde to the bottom gate turn-on is set at 200ns typically. virtual phase node for virtual phase node for virtual phase node for virtual phase node for virtual phase node for combi-sense combi-sense combi-sense combi-sense combi-sense tm tm tm tm tm peak-current-mode control is widely employed in multi- phase voltage regulators. it features phase current bal- ance, fast transient response, and over current protec- tion, etc. these are essential to low-voltage high-cur- rent regulators designed for advanced microprocessors. usually, a costly current sensing resistor is required to obtain the output inductor current information for the peak current control. the combi-sense tm technique fea- tured by the sc1211 is an approach to sense inductor current without using sensing resistor.
9 ? 2003 semtech corp. www.semtech.com power management sc1211 ind uctor c urr ent si g nal vout qcst vin rcs c sc1211 pgnd vin vpn lo q2 qcsb drn q1 + co ccs the above circuit shows the concept of combi-sense tm technique. an internal totem pole (qcst, qcsb) generates a vpn (virtual phase node) signal. this vpn follows the drn (or the power phase node) with the same timing. a rc network (rcs and ccs) is connected between vpn and vout. during q1 turn-on, qcst turns on as well. the voltage drop across q1 and lo charges ccs. during q2 turn-on, qcsb turns on as well. the voltage drop across q2 and lo discharges ccs. both voltage drops are pro- portional to the inductor current and a resistance equal to fet?s rdson plus esr of the inductor. if the time con- stant rcs x ccs is close to the lo/ro of the inductor, where ro is given by ) 1 ( * * _ _ d r d r r ro ls dson hs dson inductor the signal developed across ccs will be proportional to the inductor current, where ro is the equivalent current sensing resistance. in the above equation, rinductor is esr of the inductor, rdson_hs and rdson_ls are the top and bottom fet?s rdson, and d is the duty cycle of the converter. since a perfect timing match down to the nanosecond is impossible, the vpn totem pole is held in tri-state during the communtations of drn in the sc1211. this avoids errors and offset on the current detection which can be significant since the timing mismatch is multiplied by the input voltage. an optional capacitor between vpn and drn allows these two nodes to be ac coupled during the tri-state window, hence yields a perfect timing match. applications information (cont.) refer to semtech sc2643vx combi-sense tm current mode controller about the details of the combi-sense technique. optimized gat optimized gat optimized gat optimized gat optimized gat e driv e driv e driv e driv e driv e v e v e v e v e v oltage oltage oltage oltage oltage with the supply voltage in between 9v to 16v, an inter- nal ldo is designed with the sc1211 to bring the volt- age to a lower level for gate drive. an external ceramic capacitor(1uf to 4.7uf) connected in between vreg to ground is needed to support the ldo. the ldo output is connected to low gate drive internally, and has to be connected to high gate drive through an external boot- strap circuit. the ldo output voltage is set at 8.5v. the manufacture data and bench tested results show that, for low r dson fets run at applied load current, the opti- mum gate drive voltage is around 8.5v, where the total power losses of power fets, including conduction loss and switching loss, are minimized. thermal shut down thermal shut down thermal shut down thermal shut down thermal shut down the sc1211 will shut down by pulling both driver out- puts low if its junction temperature, t j , exceeds 155c. component selection component selection component selection component selection component selection switching f switching f switching f switching f switching f req req req req req uency uency uency uency uency , induct , induct , induct , induct , induct or and mosfet or and mosfet or and mosfet or and mosfet or and mosfet s s s s s the sc1211 is capable of providing up to 3.5a peak drive current, and operating up to 1.5mhz pwm frequency without causing thermal stress on the driver. the selec- tion of switching frequency, together with inductor and fets is a trade-off between the cost, size, and thermal management of a multi-phase voltage regulator. in mod- ern microprocessor applications, these parameters could be in the range of: switching frequency 100khz to 500khz per phase inductor value 0.2uh to 2uh fets 4m-ohm to 20m-ohm r dson 20nc to 100nc total gate charge bootstrap circuit bootstrap circuit bootstrap circuit bootstrap circuit bootstrap circuit the sc1211 uses an external bootstrap circuit to pro- vide a voltage for the top fet drive. this voltage, refer- ring to the phase node, is held up by a bootstrap capaci-
10 ? 2003 semtech corp. www.semtech.com power management sc1211 applications information (cont.) tor. the capacitor value can be calculated based on the total gate charge of the top fet, q top , and an allowed voltage ripple on the capacitor, ? v bst , in one pwm cycle: c bst > q top / ? v bst typically, it is recommended to use a 1uf ceramic ca- pacitor with 25v rating and a commonly available diode in4148 for the bootstrap circuit. in addition, a small re- sistor (one ohm) has to be added in between drn of the sc1211 and the phase node. the resistor is used to allievate the stress of the sc1211 from exposing to the negative spike at the phase node. a negative spike could occur at the phase node during the top fet turn-off due to parasitic inductance in the switching loop. the spike could be minimized with a careful pcb layout. in those applications with to-220 package fets, it is recom- mended to use a clamping diode on the drn pin to miti- gate the impact of the excessive phase node negative spike. filters for supply power filters for supply power filters for supply power filters for supply power filters for supply power for vreg pin of the sc1211, it is recommended to use a 1uf to 4.7uf, 25v rating ceramic capacitor for decoupling. la la la la la y y y y y out guidelines out guidelines out guidelines out guidelines out guidelines the switching regulator is a high di/dt power circuit. its printed circuit board (pcb) layout is critical. a good lay- out can achieve an optimum circuit performance while minimized the component stress, resulting in better sys- tem reliability. for a multi-phase voltage regulator, the sc1211 driver, fets, inductor, and supply decoupling capacitors in each phase have to be considered as a whole during pcb layout. refer to semtech sc2643vx/ sc1211 evb layout guideline. for the sc1211 driver, the following guidelines are typi- cally recommended during pcb layout: 1. place the sc1211 close to the fets for shortest gate drive traces and ground return paths. 2. connect bypass capacitors as close as possible to decoupling pins (vreg and vin) and pgnd. the trace length of the decoupling capacitor on vreg pin should be no more than 0.2? (5mm). 3. locate the components of the bootstrap circuit close to the sc1211. soldering considera soldering considera soldering considera soldering considera soldering considera tion tion tion tion tion the exposed die pad of the sc1211 is used for ground solder pad solder mask vias copper return and thermal release of the driver. the pad must be soldered to the ground plane that is further connected to the system ground in the inner layer through multiple vias. for better electrical and thermal performance, it is recommended to use all copper available under the driver as the ground plane, and place the vias as close as pos- sible to the solder pad. meanwhile, the vias have to be masked out to prevent solder leakage during reflow. the layout arrangement is detailed in the above figure, which also can be found in the ?land pattern ? power soic-8? section.
11 ? 2003 semtech corp. www.semtech.com power management sc1211 outline drawing - power soic-8 land pattern - power soic-8 outline drawing - power soic-8l h c n a r b n a w i a t 0 8 3 3 - 8 4 7 2 - 2 - 6 8 8 : l e t fx a0 9 3 3 - 8 4 7 2 - 2 - 6 8 8 : h b m g d n a l r e z t i w s h c e t m e s h c n a r b n a p a j 0 5 9 0 - 8 0 4 6 - 3 - 1 8 : l e t 1 5 9 0 - 8 0 4 6 - 3 - 1 8 : x a f h c n a r b a e r o k tl e7 7 3 4 - 7 2 5 - 2 - 2 8 : f6 7 3 4 - 7 2 5 - 2 - 2 8 : x a ) . k . u ( d e t i m i l h c e t m e s 0 0 6 - 7 2 5 - 4 9 7 1 - 4 4 : l e t 1 0 6 - 7 2 5 - 4 9 7 1 - 4 4 : x a f e c i f f o i a h g n a h s t0 3 8 0 - 1 9 3 6 - 1 2 - 6 8 : l e 1 3 8 0 - 1 9 3 6 - 1 2 - 6 8 : x a f l r a s e c n a r f h c e t m e s 0 0 - 2 2 - 8 2 - 9 6 1 ) 0 ( - 3 3 : l e t 8 9 - 2 1 - 8 2 - 9 6 1 ) 0 ( - 3 3 : x a f f o y r a i d i s b u s d e n w o - y l l o h w a s i g a l a n o i t a n r e t n i h c e t m e s . a . s . u e h t n i s r e t r a u q d a e h s t i s a h h c i h w , n o i t a r o p r o c h c e t m e s h b m g y n a m r e g h c e t m e s 3 2 1 - 0 4 1 - 1 6 1 8 ) 0 ( - 9 4 : l e t 4 2 1 - 0 4 1 - 1 6 1 8 ) 0 ( - 9 4 : x a f contact information for semtech international ag

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