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rev.1.0, sep.19.2003, page 1 of 45 M65582AMF-XXXFP ntsc tv signal processor with mcu rej03f0093-0100z rev.1.0 sep.19.2003 features ? 1package solution with tv baseband signals (video and chroma) processor, deflection and 8bit mcu ? high quality picture by 2 dimension adaptive y/c separation of 3 line type ? built-in vm (velocity modulation) circuit emphasizing the picture outline by the changing of the scanning speed ? built-in the correction circuits of the picture distortion which is east-west function etc. for flat tv ? available to use the software for best saled mcu m37272 ? available to input external video signal, s video signal and component video signal ? high performance osd function with ccd and half tone display ? analog video switch with 5 video inputs composite video : 3ch, s video : 1ch, component video : 1ch ? built-in a high performance blackstrech ? built-in ynr ? built-in 8bit mcu core m37272 rom : 60kbyte, ram : 2048byte applications ntsc color television receivers
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 2 of 45 pin configuration p44 p23/tim3 p22/sin/ad7 p21/sout/ad6 p20/sclk/ad5 p16 p15 p07/int1 p06/int2/ad4 p05/ad3 p04/pwm4/ad2 p45 p03/pwm3/ad1 p26/xcin p25/int3 p24/tim2 p27/xcout cvbs(x2) out dct filter vdd(digital) vss(digital) reset cvin vhold hlf filt vdd(mcu) vss(mcu) xout xin tv1 in vdd(input) y(y/c) in c(y/c) in vss(input) tv2 in vrt tv3 in vrb cnvss apc filter vz out vm vdd(output) r out vss(output) g out vdd(vcxo) b out vss(def) xtal(ntsc) n.c. test y(yuv) in u(yuv) in v(yuv) in p02/pwm2 h out akb in acl in p14/sda2 p13/sda1 p12/scl2 p11/scl1 p40 p41 p42 p43 p10 p00/pwm0 fbp in h corre e-w hvco fb vramp(+) vramp(-) vramp c vdd(def) afc1 filter p01/pwm1 65 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 1 15 16 17 18 19 20 21 22 23 24 14 13 12 11 10 9 8 7 6 5 4 3 2 40 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 64 50 49 48 47 46 45 44 43 42 41 51 52 53 54 55 56 57 58 59 60 61 62 63 M65582AMF-XXXFP
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 3 of 45 block diagram (whole) 51 40 34 52 39 38 37 41 50 49 42 36 46 hvco f/b afc1 fil ter apc fil ter test n.c. xt al(ntsc) vss(def) vdd(def) fbp in h out vdd(vcxo) acl in akb in 48 12 13 32 44 45 43 47 31 33 35 28 30 vramp c e-w out vramp out vdd(digital) vss(digital) vdd(output) vss(output) vz out 29 r/g/b out vm out 24 18 23 21 25 26 27 22 15 14 17 20 16 19 vrb vr t tv1/2/3 in / yc in / yuv in y(y/c) in c(y/c) in y(yuv) in u(yuv) in v(yuv) in tv1 in tv2 in tv3 in vss(input) vdd(input) cvbs(x2) out dct filter 54 79 59 58 57 69 68 67 65 66 1 80 56 60 74 75 78 77 73 76 p24/tim2 p20/sclk/ad5 p21/sout/ad6 p22/sin/ad7 p16 p23/tim3 72 p15 61 p27/xcout p44 p45 p04/pwm4/ad2 p05/ad3 p10 p42 p43 p41 p40 p1 1/scl1 p13/sda1 p25/int3 p26/xcin p03/pwm3/ad1 63 62 55 53 64 8 10 9 7 5 6 vdd(mcu) vss(mcu) p02/pwm2 hlf vhold cvin fil t p00/pwm0 p01/pwm1 11 reset in h correction 3 4 xout xin cnvss 2 71 70 p06/int2/ad4 p07/int1 ccd i/o port mcu core m37273 signal processor reset intelligent monitor scl half tone sda fast blk rgb out (osd) osd clk hd pls vd pls b out r out g out p14/sda2 p12/scl2 eeprom vramp(+) vramp(-)
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 4 of 45 block diagram (asic) 30 ref. current * (drive, cutoff) 32 * (afc1 gain) vrt=1.7v vrb=0.5v to mcu for ccd cvbs or y vss(output) * (cvbs/yc/yuv sw) cvbs y-signal dct filter *(h-phase, h-stop) bgp pins connected to external connection to mcu block inside * iic bus cntl * (monitoring) to rgbmtx 4fsc (reference clk) vz out * (slice level) vcxo afc1 filter c or u-v signal from mcu *input selector v sync sep. v count down *(v-shift) h-afc2 h out pulse gen. 36 43 46 41 41 8bit-d/a 10bit-d/a 10bit-d/a 10bit-d/a drive cutoff drive cutoff drive cutoff 29 35 33 31 rgb processor (inc. mtx) 37 39 38 40 50 42 49 47 48 45 44 e-w gen. 16bit- d/a e-w gen. 16bit- d/a * (h-size, parabola, trapezium, upper corner, lower corner) * (v-size, v-position, linearity, s-correction, service sw) h-afc h vco h count down sync separator vcxo c.p. p. d . 1/4 burst gate y-processing c-processing sw 2dycs by 3lines 1h dl 1h dl 13 12 vssdigital) * (sharpness, y-delay, black stretch) * (color, tint, killer off) osd(rgb) in f.b. in h.t. in 8bit-a/d 8bit-a/d * (cvbs/yc/yuv sw) "off"@y/c&yuv input 15 x2 acc amp sw * * c or u+v 24 22 vdd(digital) =3.3v 17 20 vss(input) vdd(input) =3.3v 14 * (half tone, blue back, abcl, contrast, gamma, blue stretch) tv1-3 & y/c & yuv to cvbs or y/c or yuv sel clamp clamp clamp clamp clamp clamp clamp bias 16 21 23 18 19 25 26 27 tv1 in 1.23vp-p tv2 in 1.23vp-p tv3 in 1.23vp-p v in 0.7vp-p u in 0.7vp-p y in 1.0vp-p c in 0.7vp-p y in 1.0vp-p vdd(ivcxo) =3.3v 34 low-speed 10bit-a/d 51 52 acl in (0-3.3v) akb in (0-3.3v) * (akb/acl/ dct sw) * akb&abcl&dct dct iic receiver intelligent monitoring int. mon out (ana & dig) vdd(output) =3.3v vdd(def) =3.3v 8fsc out (for osd) hd out vd out r out (0-1vp-p) g out (0-1vp-p) b out (0-1vp-p) e-w out (0-2vp-p) v ramp(-) out (0-2vp-p) v ramp(+) out (0-2vp-p) h out (0-3.3v) fbp in (0-3.3v) h correction (0-3.3v) from mcu sda (5v i/f) scl (5v i/f) reset to m c u int. mon out (ana&dig) to mcu to mcu apc fil ter xt al vss(def) hvco f/b y-sw out (2vp-p) vm out (0-1vp-p) n.c. test
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 5 of 45 absolute maximum ratings parameter symbol ratings unit conditions supply voltage (mcu : 5v) vdd (mcu) ? 0.3 to 6.0 v supply voltage (asic : 3.3v) vdd (asic) ? 0.3 to 4.0 v input voltage (mcu) vi (mcu) ? 0.3 to vcc+0.3 v output voltage (mcu) vo (mcu) ? 0.3 to vcc+0.3 v circuit current (mcu) ioh (mcu) 0 to 1 (see note 1) ma all voltage are based on vss.output transistors are cut off. circuit current (p00-p07, p10, p15, p16, p20-p27, p40-p45) iol1 (mcu) 0 to 2 (see note 2) ma circuit current (p11-p14) iol2 (mcu) 0 to 6 (see note 2) ma circuit current (p24-p27) iol3 (mcu) 10 (see note 3) ma digital input voltage vid (asic) ? 0.3 to vcc+0.3 v analog output current iout (asic) ? 30 ma power dissipation pd 2000 mw thermal derating kt 20.0 mw/ c operating temperature topr ? 20 to 70 c storage temperature tstg ? 40 to 125 c recommended conditions (ta=25 to 70 c, unless otherwise noted) limits parameter symbol min. typ. max. unit supply voltage (mcu) (see note 4) vdd (mcu) 4.75 5.0 5.25 v supply voltage (digital) vdd (digital) 3.13 3.3 3.47 v supply voltage (input) vdd (input) 3.13 3.3 3.47 v supply voltage (output) vdd (output) 3.13 3.3 3.47 v supply voltage (vcxo) vdd (vcxo) 3.13 3.3 3.47 v supply voltage (def) vdd (def) 3.13 3.3 3.47 v supply voltage (mcu) vss (mcu) 0 0 0 v high iutput voltage p00-p07, p10-p16, p20- p27, p40-p45, reset, x in vih1 (mcu) 0.8 vdd vdd v high iutput voltage scl1, scl2, sda1, sda2 (when using i2c -bus) vih2 (mcu) 0.7 vdd vdd v high iutput voltage fbp in vih3 (asic) 0.8 vdd vdd v low iutput voltage p00-p07, p10-p16, p20-p27 p40-p45 vil1 (mcu) 0 0.4 vdd v low iutput voltage scl1, scl2, sda1, sda2 (when using i2c-bus) vil2 (mcu) 0 0.3 vdd v low iutput voltage (see note 6) resetb, x in, tim2, tim3, int1, int2, int3, s in, s clk vil3 (mcu) 0 0.2 vdd v low iutput voltage fbp in vil4 (asic) 0 0.2 vdd v high average output current (see note 1) p10-p16, p20-p27, p40-p45 ioh (mcu) 1 ma
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 6 of 45 limits parameter symbol min. typ. max. unit low average output current (see note 2) p00-p07, p10, p15, p16, p20-p27, p40-p45 iol1(mcu) 2 ma low average output current (see note 2) p11-p14 iol2(mcu) 6 ma low average output current (see note 3) p24-p27 iol3(mcu) 10 ma oscillation frequency (for cpu operation) x in (see note 5) f(xin) (mcu) 7.9 8.0 8.1 mhz oscillation frequency (for sub-clock operation) x cin f(xcin) (mcu) 29 32 35 khz input frequency tim2, tim3, int1, int2, int3 fhs1 (mcu) 100 khz input frequency s clk fhs2 (mcu) 1 mhz input frequency scl1, scl2 fhs3 (mcu) 400 khz input amplitude video signal cv in vi (mcu) 1.5 2.0 2.5 v note 1: the total current that flows out the mcu must be 20ma or less. 2: the total input current to mcu (iol1+iol2) must be 30ma or less. 3: the total average input current for ports p24-p27 to mcu must be 20ma or less. 4: connect 0.1 f or more capacitor externally between the power source pins vdd-vss so as to reduce power source noise. 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillator circuit. when using the data slicer, use 8mhz. 6: p06, p07, p23-p25 have the hysteresis when these pins are used as interrupt input pins or timer pins. p11-p14 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p20-p22 have the hysteresis when these pins are used as serial i/o pins. 7: pin name in each parameter is described pin names. (1) dedicated pins: dedicated pin name. (2) double-/triple-function ports. when the same limits: i/o port name. when the limits of function except ports are different from i/o port limits: function pin name.
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 7 of 45 thermal derating thermal derating (maximum rating) power dissipation pd (w) 2.0 1.5 1.0 0.5 0.0 01 5 0 75 125 100 50 25 ambient temperature ta (c) 1.1 70
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 8 of 45 i 2 c bus i 2 c bus table v stop power down h stop 00h input video sw saw filter line-delay number 08h pedestal clamp vrt voltage sharpness noise coring level aperture frequency sharpness max gain eht ynr coring level ynr sw y delay 08h 6fh 0fh 10h tint contrast color 40h 40h 40h osd level (r) half tone osd comp rgb mtx osd level (b) osd level (g) brightness 80h h afc2 phase afc free run h afc gain 20h rgb p-on mute y thr 2d g out mute y 2d fix r out mute y mute c bpf fix b out mute 02h manexp alfa 02h blue stretch gamma fsc org rgb on fsc sel 80h h out duty h free up 02h v size v linearity v blk stop 20h 20h cuttoff (r) l drive (r) cutoff (r) h 00h c0h cuttoff (g) l drive (g) cutoff (g) h 00h c0h cuttoff (b) l drive (b) cutoff (b) h 00h c0h analog monitoring point 00h digital monitoring point test i/o inv 14h clk 14h clk dly a/d clk dly ds clk dly inv ds clk 00h 03h vjp width vjp sw abl sel uv lpf on 04h f4h ds d/a clk ctl abl speed ds d/adither 04h abl spe abl aspe 92h abl gain abl time constant 05h abl aspe2 02h akb mode eht gain akb p 60h ycs hbpf back ycs hbpf front 03h sharpness overshoot gain sharpness preshoot gain 20h 20h thr nzv 1 black stretch sw 34h thr nzv 2 thr nzh 2 thr nzh 1 ffh ffh ffh killer level 01h amp ctl rray c0h amp1 off l 5ah amp1 on amp1 off h 04h h charge pump ramp slew rate auto slice down auto slice up 78h skew corrector vcxo ctrl skew co. ini. 14h bw sel bw det 01h swap free run bg start 90h killer threshold 01h free run offset yuv mpx sel yuv cxuv yuv uv inv. uv gain 00h amp3 acc v mask time amp tim b2 ave sel 00h force killer c delay ave sel clamp bitsel osd limit 42h 4fsc sw hd sw killer sw bgp pos 68h acc sw mv2 sw mv1 sw mv 30h 20h a0h 20h note: sub address 03h, 07h, 1eh-2fh, 31h, 3ch, 4ah and 5eh-64h are not operational. black stretch time 1 black stretch time 2 uv dither test enable uv dither on black stretch depth bs t2 if on 61h 00h afc2 gain 2ch 67h sync slice level (v) vcxo free run h vco free run sync slice level (h) ewv v reset ref charge pump afc1 pull-in ref vco i/m test v sag macro off v ramp filter off lpf sync sync sep mask 4fsc sel 2 8fsc sel b pll c.p. 29h v cd mode v-latch off vd delay bgp c v cd mode 2 h blk stop v free 54h 4fh 4eh 4dh 4ch 4bh 49h 48h 47h 46h 45h 44h 43h 42h 41h 40h 3fh 3eh 3dh 3bh 3ah 39h 38h 37h 36h 35h 34h 33h 32h 30h 1dh 1ch 1bh 1ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 06h 05h 04h 02h 01h 00h bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah slave address sub address d7 d0 d1 d2 d3 d4 d5 d6 standard data 53h 52h 51h 50h
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 9 of 45 v aperture coring level v aperture max gain v aperture gain 04h 84h 40h 00h 40h 00h rom hys ave sel av 00h amp ctrl en 0fh killer status h coin still det akb ng akb end k moni mv 180 detnz 00h 8fh e6h 00h s correction 20h 20h amp2 on 20h 20h b2 rom <7:0> 20h 0fh 20h 20h 20h 08h 81h 80h 02h 04h 1eh 00h c gain 04h 0ch 15h 02h 00h 06h 00h 00h y a/d <7:0> akb a/d (b) <7:0> 1eh 00h 2ah cah 00h c a/d <7:0> 88h 00h 40h 00h 00h 80h amp2 off h amp2 off l amp3 on amp3 off h amp3 off l spot killer test i/o control xtest rst lpf sync on mem test test sel vm coring level vm max gain vm gain vm width vm pol h size parabola trapezium upper corner lower corner lim v position afc bow afc angle afc2 ramp pos v free 2 afc2 sel angle off h blk f position h blk r position clock sel fbp blk v blk pos akb ref pls pos v blk half kill vm delay vref sel a/d read page dct vth dct gain akb lim 1 akb lim 2 akb lim 3 akb add 1 akb add 2 akb comp (r) l akb comp (g) l akb comp (b) l v en off akb enable akb comp (r) h akb comp (g) h akb comp (b) h a/d d/a test en axis hys b2 comp u in offset v in offset acl gain acl on v pls width b2 rom <8> s det akb a/d (b) <9:8> akb new (b) akb a/d (g) <7:0> akb a/d (g) <9:8> akb new (g) akb a/d (r) <7:0> akb a/d (r) <9:8> akb new (r) bbh bbh bbh bbh bbh bbh bbh bbh bbh 9ah 99h 98h 97h 96h 95h 94h 93h 92h 91h 90h bbh bbh 9bh bbh ds clk latch pol ds clk latch on v sync lpf 2 weak sig det vth weak sig video att weak sig chroma att sync slice level (v/w) black stretch start point y clamp on y clamp fix v sync lpf 1 akb speed akb sel clk sel sar a/d ds clk div sel vm gain 2 akb swerr akb errc akb swpon akb pwerrc 8ah 89h 88h 87h 86h 85h 84h 83h 82h 81h 80h 7fh 7eh 7dh 7ch 7bh 7ah 79h 78h 77h 76h 75h 74h 73h 72h 71h 70h 6dh 6ch 6bh 6ah 69h 68h 67h 66h 65h 5dh 5ch 5bh 5ah 59h 58h 57h 56h 55h bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah bah slave address sub address 6fh 6eh d7 d0 d1 d2 d3 d4 d5 d6 standard data 8eh 8dh 8ch 8bh 7ch 14h 1eh 02h v coin b/w out 01 0 0
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 10 of 45 i 2 c bus function v latch 1 h stop h pulse stop bit d0-d4 d0-d3 d0-d6 d7 d0-d7 d0-d6 d7 d0-d7 d0-d6 d7 d0-d7 d0-d5 d7 d0-d5 d1 d0 d7 d6 d4-d5 d2-d3 d0-d1 d2-d3 d0-d1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d0-d5 d0-d7 d6-d7 d0-d5 d6-d7 d0-d5 d6-d7 d0-d5 d0-d6 d0-d6 d0-d6 d5-d6 d4 d0-d3 d4-d7 d0-d3 d4-d5 d0-d3 d7 d3-d4 d3-d7 d2 d0 d3 d0 01h 02h 04h 05h 06h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 30h sub address data description function note d4 d2-d3 d0-d1 d5 00h d1-d2 2 power down power down control (0: normal, 1: pd0, 2: pd1, 3: pd2) 1 v stop v output stop 1 line-delay number y/c separation mode (0: 3-line mode, 1: 2-line mode) 1 saw filter chroma bpf to high 5 input video sw input video sw (01: tv1 in, 02: tv2 in, 04: tv3 in, 08: y/c in, 10: yuv in) 2 vrt voltage a/d reference (0: 1.1v, 1: 1.2v, 2: 1.3v, 3: 1.4v) 1 pedestal clamp input clamp select (0: pedestal clamp, 1: sync-tip clamp) 4 sharpness noise coring level sharpness coring level (0: minimum ?? f: maximum) 2 aperture frequency sharpness f 0 (0: 2-clk 3: 5-clk) 4 sharpness max gain sharpness limiter level (0: minimum ?? f: maximum) 4 eht eht gain control (0: minimum ?? f: maximum) 4 ynr coring level ynr limiter level (0: minimum ?? f: maximum) 1 ynr sw ynr enable 2 y delay y delay time (0: 0nsec ?? 3: 210nsec) 7 tint tint level control (00: -45 ? ?? 7f: +45?) 7 color color level control (00: 0% ?? 7f: 200%) 7 contrast contrast control (00: 0% ?? 7f: 200%) v latch v latch v latch v latch v latch v latch v latch v latch v latch 6 osd level (r) r osd level (00: 0% ?? 7f: maximum) 2 half tone half tone level control (picture/osd ratio 0: 50%/50% ?? 3: 12.5%/87.5%) v latch v latch 6 osd level (g) g osd level (00: 0% ?? 7f: maximum) 2 rgb mtx rgb matrix ratio (0: 12/8, 1: 13/8, 2: 14/8, 3: 14/8) v latch v latch 6 osd level (b) b osd level (00: 0% ?? 7f: maximum) 2 osd comp contrast clip level for osd (0: low ?? 3: high) v latch v latch v latch 8 brightness brightness control (00: -50% ?? 7f: +50%) 6 h afc2 phase h position (00: +2.6sec ?? 7f: -2.6sec) 1 h afc gain afc1 gain (0: low, 1: high) 1 afc free run afc1 force free-run 1 y mute y output mute 1 c bpf fix chroma signal generate from h/v bpf only 1 b out mute b output mute 1 g out mute g output mute 1 y 2d fix y signal generate from 2dycs 1 r out mute r output mute 1 y thr 2d y signal through 2d ycs 1 rgb p-on mute rgb output mute 2 alfa adaptive detection sensitivity (0: minimum ?? 3: maximum) 1 manexp y/c separation force select (0: adaptive, 2: v, 3: h/v) 2 gamma gamma control (0: none ?? 3: deep) 2 blue stretch blue stretch control (0: none ?? 3: deep) 2 fsc org chroma decoder phase select 1 fsc sel chroma decoder clock select 1 rgb on rgb output (0: rgb mute except osd, 1: rgb output) 1 h free up afc1 free-run frequency up (about 700hz) 1 h out duty h pulse width (0: 25sec, 1: 19sec) 6 v size v ramp amplitude (00: -20% ?? 3f: +20%) 1 v blk stop v blanking off 6 v linearity v linearity (00: -3% ?? 3f: +3%) 9 cutoff (r) r cutoff control (000: dark ?? 1ff: light) 7 drive (r) r drive control (00: -2.5db ?? 7f: +3.5db) 4 analog monitoring point intelligent monitoring output select (analog) 5 digital monitoring point intelligent monitoring output select (digital) 1 test i/o intelligent monitoring output enable (digital) 2 a/d clk dly a/d clock delay adjust (0: none ?? 3: delay) 2 ds clk dly ? d/a (for v-ramp and e-w) clock delay adjust (0: none ?? 3: delay) 1 inv ds clk ? d/a (for v-ramp and e-w) clock polarity (0: none ?? 1: invert) 9 cutoff (g) g cutoff control (000: dark ?? 1ff: light) 7 drive (g) g drive control (00: -2.5db ?? 7f: +3.5db) 9 cutoff (b) b cutoff control (000: dark ?? 1ff: light) 7 drive (b) b drive control (00: -2.5db ?? 7f: +3.5db) v latch v latch v latch v latch v latch v latch
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 11 of 45 v latch 1 uv lpf on uv lpf (digital) enable 1 abl sel abl function (0: enable, 1: disenable) 1 vjp sw jump sw enable 1 vjp width jump pulse width (0: normal, 1: wide +2-line) 4 black stretch time 2 black stretch recover time (0: slow ?? f: fast) 4 black stretch time 1 black stretch attack time (0: slow ?? f fast) 2 abl speed abl processing speed (0: x1, 1: x2, 2: x4, 3: x8) 1 ds d/a dither ? d/a (for v-ramp and e-w) dither enable 2 ds d/a clk ctl ? d/a (for v-ramp and e-w) clock select (0: 28m, 1: 24m, 2: 14m, 3: 16m) 4 abl aspe abl attack speed (0: slow ?? 7: fast) 4 abl spe abl recover speed (0: slow ?? 7: fast) 4 abl gain abl gain control (0: minimum ?? 7: maximum) 3 abl time constant abl time constant (0: slow ?? 7: fast) 2 abl aspe 2 abl attack speed 2 (0: slow ?? 7: fast) 1 uv dither on uv dither enable 3 uv dither test enable uv dither test select 6 akb p akb reference pulse height (00: minimum ?? 3f: maximum) v latch 1 eht gain eht gain up (0: normal, 1: high) 1 akb mode akb mode select (0: differential mode, 1: absolute mode) 1 ycs hbpf front y/c separation front bpf band width (0: wide, 1: narrow) 2 ycs hbpf back y/c separation rear bpf band width (0: none, 1: wide ?? 2 and 3: narrow) 6 sharpness overshoot gain sharpness overshoot gain (00: soft ?? 3f: sharp) 6 sharpness preshoot gain sharpness preshoot gain (00: soft ?? 3f: sharp) 1 black stretch sw black stretch sw (0: disenable, 1: enable) 3 black stretch depth black stretch depth (0: shallow ?? 7: deep) 10 thr nzv noise detection threshold level in field (000: minimum ?? 3ff: maximum) 1 bs t2 if on black stretch recover time constant (0: slow, 1: fast) 16 thr nzh noise detection threshold level in line (0000: minimum ?? ffff: maximum) 7 killer level color killer threshold level (00: deep ?? 7f: shallow) 6 rray r-y phase offset (00: 0 ? ?? 3f: 90?) 2 amp ctl analog acc amp maximum gain (0: 0db ?? 3: +30db) 9 amp1 off analog acc amp #1 on ? >off level (000: minimum ?? 1ff: maximum) 7 amp1 on analog acc amp #1 off ?>on level (00: minimum ?? 7f: maximum) 4 mv macro vision (burst) detect level 1 mv1 sw macro vision (burst) detect enable 1 mv2 sw macro vision (burst) detect position 1 acc sw acc enable 5 bgp pos bgp (for chroma decoder) position 1 killer sw killer detector mode select (0: synchronous detect, 1: amplitude detect) 1 hd sw hd out (for osd) select (0: fbp, 1: afc1 pulse) 1 4fsc sw a/d-logic clock swap 2 ave sel chroma decoder time constant (0: 32h, 1: 16h, 2: 8h, 3: 1h) 2 c delay chroma delay time (0: none ?? 3: delay) 1 osd limit osd limit select 1 clamp bitsel y digital clamp time constant (0: fast, 1: slow) 2 b2 ave sel accumulation time control of demodulation 1 yuv cxuv yc/yuv select 1 yuv mpx sel u/v multiplex select (0: 2fsc, 1: fsc) 2 killer threshold pll stop burst level 6 bg start bgp (for pll) timing control 2 amp tim analog acc hysteresis select 1 amp3 acc acc maximum gain 4 free run offset vcxo free-run frequency adjust 1 yuv uv inv. u/v invert d5-d6 30h d7 2 14h clk dly 4fsc clock delay adjust (0: none ?? 3: delay) 1 inv 14h clk 4fsc clock polarity (0: none, 1: invert) 1 force killer forced killer 3 v mask time v masking time for demodulation 1 uv gain u/v gain up 1 free run vcxo force free-run 1 swap burst pll polarity (0: reverse, 1: normal) 2 bw det pll killer threshold level bit d7 d6 d5 d4 d0-d3 d7 d4-d6 d2-d3 d0-d1 d7 d6 d4 d2-d3 d0-d1 d7 d6 d5 d0-d4 d6 d5 d4 d0-d3 d0-d6 d7 d0-d7 d6-d7 d0-d5 d0-d6 d0-d7 d0-d7 d0-d7 d4-d5 d6 d1-d3 d0 d0-d5 d0-d5 d1-d2 d0 d7 d6 d0-d5 d3-d5 d2 d0-d1 d4-d6 d0-d3 d4-d7 d0-d3 d5-d6 d4 d2-d3 d4-d7 d0-d3 d7 d6 d1 33h 34h 35h 36h 37h 38h 39h 3ah 3dh 3bh 3eh 44h 45h 46h 47h 48h 4bh 4ch 49h sub address data description function note d0-d5 d0-d1 32h d2 3fh 41h 40h 42h 43h d6 d7 d0-d1 4dh
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 12 of 45 6 parabola e-w output amplitude (00: 0.1v p-p ?? 3f: 0.7v p-p ) v latch 1 bw sel ? d/a clock invert 1 skew co ini. skew corrector reference phase 4 vcxo ctrl vcxo phase adjust 3 skew corrector skew corrector phase control 2 auto slice down auto slicer level down (0: up ?? 3: down) 1 auto slice up auto slicer level up 2 ramp slew rate afc2 ramp slew rate 3 h charge pump afc1 charge pump current (4: minimum ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3: maximum) 1 ref vco ref pll loop gain up 2 vcxo free run vcxo f 0 adjust 1 afc1 pull-in afc1 pull-in range wide 3 ref charge pump ref pll charge pump current (4: minimum ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3: maximum) 8 h vco free run h vco f 0 adjust (in case of data is xyh, x decrease the f 0 , and y increase the f 0 ) 1 sync sep mask sync separator masking control 1 v sag v sag prevent on 2 afc2 gain afc2 gain control (0: fast ?? 3: slow) v latch 1 macro off top vend (when macrovision) prevent off 1 v ramp filter off v ramp and e-w output filter off 1 lpf sync pre sync separation lpf f 0 becomes low 1 i/m test intelligent monitoring signal (digital) enable to output to pin 51 1 b pll c.p. chroma apc charge pump current up (0: normal, 1: x5) 1 8fsc sel h rate clock select (0: 12mhz, 1: 4fsc skew clock) 1 4fsc sel 2 4fsc skew force off (0: h rate clock, 1: burst rate clock) 2 sync slice level (h) sync slice level (h sync separation) 1 ewv v reset ? d/a v reset on 2 sync slice level (v) sync slice level (v sync separation) 1 v free force v free-run 1 bgp c bgp (for deflection block) width (0: normal, 1: don't use. useful only test mode) 1 v cd mode 2 v sub-counter enable 1 h blk stop h blanking off 1 v-latch off iic v latch off (for test) 7 amp ctrl en analog acc amp #1, #2 and #3 enable 7 amp3 on analog acc amp #3 off ?>on level (00: minimum ?? 7f: maximum) 9 amp2 off analog acc amp #2 on ? >off level (000: minimum ?? 1ff: maximum) 9 amp3 off analog acc amp #3 on ? >off level (000: minimum ?? 1ff: maximum) 3 weak sig det vth noise detect level of rf weak signal (0: minimum ?? 7: maximum) 1 spot killer force spot killer 3 weak sig video att video attenuation control of rf weak signal (0: no attenuation ?? 7: maximum) 3 weak sig chroma att chroma attenuation control of rf weak signal (0: no attenuation ?? 7: maximum) 8 test i/o control test mode i/o control (only factory use) 3 test sel test mode select (only factory use) 1 mem test memory test mode (only factory use) 1 lpf sync on pre sync separation lpf enable 1 vm pol vm polarity 4 vm max gain vm limit level (0: minimum ?? f: maximum) 4 vm gain vm gain (0: minimum ?? f: maximum) 4 vm delay vm output delay (0: forward ?? f: delay) 1 y clamp fix y digital clamp control 1 (0: y digital clamp enable, 1: y digital clamp disenable) 1 y clamp on y digital clamp control 2 (0: clamp level is held, 1: clamp level is refleshed at all time) 1 xtest rst test mode select (only factory use) 4 v aperture max gain v aperture limit level (0: minimum ?? f: maximum) 4 v aperture gain v aperture gain (0: minimum ?? f: maximum) 2 vm width vm width (0: minimum ?? 3: maximum) 2 sync slice level (v/w) sync slice level (v sync separation within narrow window) 4 v aperture coring level v aperture coring level (0: minimum ?? f: maximum) 4 vm coring level vm coring level (0: minimum ?? f: maximum) 1 2 v cd mode vd delay v detect window switch timing (0: 5h, 1: 3h, 2: 1h, 3: force 1 window) vd pulse delay 1 amp2 on analog acc amp #2 off ?>on level (00: minimum ?? 7f: maximum) v latch v latch v latch v latch v latch v latch v latch 2 black stretch start point black stretch start point (0: 25%, 1: 31%, 2: 38%, 3: 44%) 6 s correction v ramp s correction (00: 0% ?? 3f: +3%) 6 h size e-w output dc level (00: +250mv ?? 3f: -250mv) d0-d5 6ch bit d0-d3 d6 d4-d5 d0-d3 d4-d7 d0-d3 d0-d3 d7 d6 d4-d5 d3 d0-d2 d0-d7 d4-d6 d1-d3 d0 d1-d3 d0 d0-d7 d0 d0-d7 d0-d6 d7 d0-d6 d7 d6 d5 d4 d3 d2 d0-d1 d7 d5-d6 d3-d4 d2 d1 d0 d7 d6 d5 d4 d2-d3 d1 d0 d0-d7 d5-d7 d4 d1-d2 d0 d5-d7 d3-d4 d2 d0-d1 d5-d7 d1-d4 d0 4fh 50h 5dh 52h 51h 65h 53h 59h 54h 55h 56h 5ah 66h 68h 69h 67h sub address data description function note d5 d4 d0-d3 d4-d7 4dh d2 5ch 57h 58h 5bh 4eh d0-d5 d6-d7 6ah d0-d5 6bh
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 13 of 45 6 trapezium e-w trapezium (00: -50% ?? 3f: +50%) 6 upper corner e-w upper corner (00: -200% ?? 3f: +200%) 6 lower corner e-w lower corner (00: -200% ?? 3f: +200%) 4 lim chroma detect level for 2d ycs (0: minimum ?? f: no limit) 6 v position v ramp output dc level (00: -10% ?? 3f: +10%) 6 afc bow afc bow (00: +1.5sec ?? 3f: -1.5sec) 6 afc angle afc angle (00: +/-1.5sec ?? 3f: -/+1.5sec) 4 afc2 ramp pos afc2 ramp position (0: -5.2sec ?? f: +5.2sec) 1 angle off afc angle/bow disenable 1 afc2 sel afc angle/bow and h correction disenable 1 v free 2 adaptive vertical free-run mode (by h coincidence) 1 clock sel ? d/a clock select (0: enable to select "ds d/a clk ctl, 1: same clock as a/d) 6 h blk f position h bllanking (right side) timing (00: +2.6sec ?? 3f: -2.6sec) 6 h blk r position h bllanking (left side) timing (00: +2.6sec ?? 3f: -2.6sec) 1 v blk half kill v blanking half h killer enable 1 akb ref pls pos akb reference pulse position (0: normal, 1: 3h delay) 2 v blk pos v blanking width (0: normal ?? 3: 3h wider, avairable only when akb ref pls pos="h") 1 fbp blk h blk mode select (0: adjustable by h blk f/r position, 1: fbp) 2 a/d read page a/d read page select 2 v sync lpf 1 v sync separation pre-lpf (rise edge) control (0: no filter ?? 3: 2sec) 2 v sync lpf 2 v sync separation pre-lpf (fall edge) control (0: no filter ?? 3: 2sec) 2 vref sel a/d reference voltage source select (use vz) 7 dct vth dc transfer threshold level (0: low ?? 7f: high) 5 dct gain dc transfer ratio control (0: 100% ?? 1f: 80%) 8 akb lim 2 akb lim 2 8 akb lim 1 akb lim 1 8 akb add 1 akb add1 8 akb comp (r) l akb comp (r) lsb 8 akb comp (g) l akb comp (g) lsb 8 akb comp (b) l akb comp (b) lsb 2 akb comp (r) h akb comp (r) msb 2 akb comp (b) h akb comp (b) msb 1 akb enable akb enable (0: akb level is held, 1: akb level is refleshed at all time) 1 v en off disenable to reflesh acc by vertinal rate 6 axis hys axis hys 2 ave sel av ave sel av 7 b2 comp b2 comp 4 u in offset u input dc offset level (0: ?10mv ?? f: +10mv) 4 v in offset v input dc offset level (0: ?10mv ?? f: +10mv) 1 acl on acl enable 1 acl gain acl gain up 2 clk sel sar a/d sar a/d clock select (0: 2fsc, 1: 4fsc, 2: 12mhz, 3: 6mhz) 2 akb sel akb control (0: akb disenable and available cutoff data, 1: akb enable, 2: test mode) 8 akb errc akb error detect time 8 akb swpon akb power on threshold 8 akb pwerrc akb power on time 2 ds clk div sel ? d/a clock divider select (0: 1/4, 1: 1/2, 2: 1/1, 3: clock off) 1 ds clk latch pol ? d/a clock latched by 4fsc clock polarity 2 vm gain 2 vm gain2 8 akb swerr akb error detect threshold 2 akb speed akb speed 1 ds clk latch on ? d/a clock latched by 4fsc clock enable 1 v pls width v pulse width (0: standard, 1: wide) 8 8 akb lim 3 akb add 2 akb lim 3 akb add 2 2 akb comp (g) h akb comp (g) msb v latch v latch v latch v latch bit d0-d7 d0-d7 d0-d7 d6 d4-d5 d3 d2 d0-d1 d6-d7 d4-d5 d2-d3 d1 d0 d4-d7 d0-d3 d0-d6 d6-d7 d0-d5 d0-d5 d0-d5 d7 d6 d4-d5 d2-d3 d0-d1 d0-d7 d0-d7 d0-d7 d0-d7 d0-d7 d0-d7 d0-d7 d0-d7 d0-d4 d0-d6 d6-d7 d4-d5 d2-d3 d0-d1 d5 d3-d4 d2 d1 d2-d7 d2-d7 d0 d7 d6 d4 d0-d3 d0-d5 d0-d5 d0-d5 d0-d3 d0-d5 d0-d5 d0-d5 70h 74h 76h 75h 8eh 7eh 85h 7dh 8bh 88h 86h 8dh 8ch sub address data description function note d0-d7 89h 8ah 84h 87h 6dh 6fh 6eh 71h 73h 72h 79h 7ch 77h 7ah 7bh 78h 83h 7fh 82h 80h 81h 6 a/d d/a test en test mode select for a/d and d/a (only factory use) 6 rom hys rom hys
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 14 of 45 1 akb end akb end output 1 s det s (y/c) input detector output 1 h coin horizontal coincidence output 1 k moni c-pro killer detector output 1 mv 180 macrovision detector output 1 still det vcr still detector outut 1 b/w out burst pll killer detector output 1 v coin vertical coincidence output 1 killer status color / killer status output 9 b2 rom b2 rom data output 10 akb a/d (r) akb a/d (r) output 2 c gain analog acc amp status 1 akb new (r) akb new (r) output 10 akb a/d (g) akb a/d (g) output 1 akb new (g) akb new (g) output 10 akb a/d (b) akb a/d (b) output 1 akb new (b) akb new (b) output 8 y a/d y a/d output monitoring 8 c a/d c a/d output monitoring 4 0001 product identification d4 1 detnz noise detector output 1 akb ng akb ng output d2 90h bit d6-d7 d0-d7 d0-d7 d5 d6-d7 d0-d7 d5 d6-d7 d0-d7 d5 d3-d4 d6-d7 d0-d7 d0-d7 d7 d6 d5 d4 d3 d2 d0 d7 d5 95h 94h 9ah 97h sub address data description function note d6 91h 92h 9bh 96h 93h 98h 99h read read read read read read read read read read read read read read read read read read read read read read
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 15 of 45 electrical characteristics (asic part) 1. test circuit 15p 15p p3 p4 47 0.01 47 + 47 0.01 47 + + 1 p14 p15 p16 0.1 tv1 in 50 47 y(y/c) in 50 0.1 p18 0.01 50 c(y/c) in p19 tv2 in 50 0.1 0.1 p22 0.1 p24 0.1 50 tv3 in p23 1 2 3 6 5 4 10 9 8 7 20 19 18 17 16 15 14 13 12 11 24 23 22 21 25 36 35 34 33 32 31 30 29 28 27 26 40 39 38 37 64 63 62 59 60 61 55 56 57 58 45 46 47 48 49 50 51 52 53 54 41 42 43 44 80 69 70 71 72 73 74 75 76 77 78 79 65 66 67 68 M65582AMF-XXXFP 0.1 50 y(yuv) in p25 0.1 50 u(yuv) in p26 p31 0.1 50 v(yuv) in p27 0.1 p28 47 p29 p33 p35 47 0.01 47 + 0.01 47 + 22p p37 22 0.01 p40 1k + 0.22 0.033 p46 2k + 0.1 0.01 p45 p44 6.8k + 1 0.01 p41 + 47 0.01 p43 + 10 p47 p49 p50 p51 0.01 p52 0.01 3k 5.1k 1 2 8 7 6 5 4 3 m74ls221p 16 15 9 10 11 12 13 14 2200p vr 20k 4700p vr 20k 3k 620 + 47 0.01 47 vdd(5v) vdd(3.3v) p54 100 sda p56 100 scl p57 100 osd(b) p58 100 osd(g) p59 100 osd(r) p60 100 fast blk p65 10k p66 10k p67 10k p68 10k p69 10k p70 10k p71 10k p72 10k p73 10k p74 10k p75 10k p76 10k p77 10k p78 10k p79 10k p80 10k 10k p64 10k p63 10k p62 10k p55 10k p53 a 47 3.3k 220k 2.2k x1: murata csa8.00mtz (8.00mhz) x2: siward 1-781-377-21 (14.31818mhz) x1 x2 p48 0.01
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 16 of 45 2. input signal sg.a sg.b sg.c sg no. input signal (value at pin terminal is 50 ) ntsc system standard video signal. apl can be varied. vy=0.714v (apl 100%), unless otherwise noted. the vertical signal should be interlaced at 60hz. 0.286v vy 4.5 s8.8 s 4.7s the amplitude and frequency of lumi- nance signal can be varied by signal sg.a. the typical amplitude is 0.714v p-p . the frequency of luminance, (f) as stated in test. 0.286v 4.5 s8.8 s 4.7s 0.286v f 0.286v ntsc system mono-chroma video signal. the amplitude and frequency of burst part and chroma part can be varied. the vertical signal should be interlaced at 60hz. standard condition: v y =0.286v v eb =0.286v, v ec =0.572v f eb =f ec =3.576545mhz 0.714v 4.5 s8.8 s 4.7s v eb 0.286v v ec f ec f eb sg.d ntsc system 2-phase chroma video signal. the vertical signal should be interlaced at 60hz. standard condition: v y =0.286v v eb =0.286v, vec=0.572v p eb =-180 , p ec 1=0?, p ec 2=90
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 17 of 45 sg no. input signal (value at pin terminal is 50 ? ) 0.286v duty cycle 90%, frequency can be varied, amplitude can be varied (typ. 0.286v p-p ) sg.g sg.h 0.286v duty cycle can be varied (typ. 95%), frequency can be varied (typ. 0.286v p-p ). 3. setup instruction for evaluation pcb 3.1 horizontal blanking pulse adjustment the timing and pulse width of the horizontal blanking pulse should be as shown in the following figure by adjusting the variable resistor of the single shot multi vibrator. pin50 (h out) 12s 8s fbp the variable resistor at pin15 of ttl ic 'm74ls221p' is used to fix the timing at 8 s and that at pin7 is used to fix the pulse width at 12 s. 3.2. h vco adjustment before measurement of m65582mf, hvco must be adjusted by the following procedure. set the frequency at pin50 (h out) to about 15.734khz by adjusting i 2 c-bus data of h vco control (51h d0-d7).
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 18 of 45 4. electric characteristics (ta=25 c, vdd=5.0, 3.3v) input signal limits parameter symbol pins sg test points max. typ. min. unit remarks standard conditions dc pin48 = 1.65v 3.3v supply current icc33 ? ? a 140 180 220 ma supply of asic a/d reference voltage (top) vrt ? ? 22 1.6 1.7 1.8 v a/d reference voltage (bottom) vrb ? ? 24 0.4 0.5 0.6 v input signal limits parameter symbol pins sg test points max. typ. min. unit remarks standard conditions of video parameter y pin48 = 1.65v cvbs out output level 2ag 16,21, 23 sg.a 15 1.8 2.0 2.2 vpp luminance standard output level yout 16,21, 23 sg.a 31,33, 35 560 700 840 mvpp video frequency characteristics fy 16,21, 23 sg.b 31,33, 35 ? 5 ? 2 1 db f=5mhz vm output level vm 16 sg.b 24 520 650 780 mvpp f=3.58mhz input signal limits parameter symbol pins sg test points max. typ. min. unit remarks standard conditions of chroma parameter c pin48 = 1.65v acc characteristic 1 acc1 16 sg.c 31 ? 3 0 3 db veb, vec : +6db of typical input level acc characteristic 2 acc2 16 sg.c 31 ? 3 0 3 db veb, vec : -20db of typical input level apc pull-in range (upper) apcu 16 sg.c 31 ? 300 ? ? hz feb=fec : variable apc pull-in range (lower) apcl 16 sg.c 31 ? ? 300 hz feb=fec : variable demodulation phase angle demp 16 sg.d 31,35 85 90 95 deg
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 19 of 45 2ag yout fy vm 00 y 00h 01h 02h 04h 05h 06h 08h 09h 0ah 0bh 0ch 0dh 0eh 10h 12h 16h 17h 18h 19h 1ah 32h 3bh 65h 66h 67h 68h 69h 79h 7ah 00 08 6e 80 20a0204040406f0f10 02 80 00 8300202005 c0 00 c0 00c0 00 8f 06 00 05 1bh 3ah 83h 8 9h 2a 00 51h adj bus condition (input initial data, unless otherwise noted. refer to section 8.1 for the standard data.) symbol ff 00 00 00 acc1 acc2 apcu apcl 83 83 83 83 c 00h 01h 02h 03h 08h 09h 0ah 0bh 0ch 0dh 0eh 10h 16h 17h 18h 19h 1ah 1bh 32h 41h 45h 47h 49h 4ch 4dh 4eh 50h 51h 5dh 00 08 6e 00 028020 a0 204040 4008 c0 00 c0 91 004b0830 c0 0105 c0 00 04 14 71 80 adj 42h 46h 83h 8 9h 2a 00 48h 00 bus condition (input initial data, unless otherwise noted. refer to section 8.1 for the standard data.) symbol demp icc33 vrt vrb dc 00h 01h 02h 04h 05h 06h 08h 09h 0ah 0bh 0ch 0dh 0eh 10h 12h 16h 17h 18h 19h 1ah 32h 3bh 65h 66h 67h 68h 69h 79h 7ah 00 08 6e 80 20 a0 20404040 6f0f 10 02 80 00 8300202005 c0 00 c0 00c0 00 8f 06 00 05 1bh 3ah 83h 8 9h 2a 00 51h adj bus condition (input initial data, unless otherwise noted. refer to section 8.1 for the standard data.) symbol
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 20 of 45 input signal limits parameter symbol pins sg test points max. typ. min. unit remarks standard conditions of rgb parameter rgb pin48 = 1.65v ouput pedestal voltage vped 16 sg.a 31,33, 35 2.7 3.0 3.3 v vy = 0.0v output blanking voltage vblk 16 sg.a 31,33, 35 3.1 ? 3.3 v vy = 0.0v matrix ratio r/b mtxr 16 sg.e 31,35 0.8 1.0 1.2 ? matrix ratio g/b mtxb 16 sg.e 31,35 0.2 0.3 0.4 ? akb reference pulse output level akbp 16 sg.a 31,33, 35 200 300 400 mv vy = 0.0v osd output level osd 16,57, 58,59 sg.f 31,33, 35 480 600 720 mvpp input signal limits parameter symbol pins sg test points max. typ. min. unit remarks standard conditions of deflection parameter def pin48 = 1.65v horizontal free-running frequency fh ? ? 50 15.48 15.73 15.98 khz horizontal pull-in range (upper) fphu 16 sg.g 50 600 ? ? hz vary frequency of input signal horizontal pull-in range (lower) fphl 16 sg.g 50 ? ? ? 600 hz vary frequency of input signal horizontal pulse amplitude hout 16 sg.a 50 2.7 3.0 3.3 v horizontal pulse width hptw 16 sg.a 50 17 19 22 sec vertical free-running frequency fv ? ? 50 57 60 63 hz vertical pull-in range (upper) fpvu 16 sg.h 44,45 ? ? 64 hz vary frequency of input signal vertical pull-in range (lower) fpvl 51 sg.h 44,45 56 ? ? hz vary frequency of input signal vertical output level vout 16 sg.a 44,45 1.0 1.2 1.4 vpp vertical ramp output dc voltage vdc 16 sg.a 44,45 1.5 1.7 1.9 v e-w output level ewout 16 sg.a 47 0.3 0.4 0.5 vpp e-w output dc voltage ewdc 16 sg.a 47 0.95 1.15 1.35 v
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 21 of 45 vped vblk mtxr mtxb 00 bf 00 00 00 rgb 00h 01h 02h 04h 05h 08h 09h 0ah 0bh 0ch 0dh 0eh 10h 12h 16h 17h 18h 19h 1ah 1bh 38h 3bh 65h 66h 67h 68h 69h 79h 7ah 00 08 6e 02 8020 a0 204040400f10 80 00 c0 83002020 a0 05 c0 00 c0 00 00 8f 06 00 05 32h 3ah 83h 8 9h 2a 00 51h adj bus condition (input initial data, unless otherwise noted. refer to section 8.1 for the standard data.) symbol akbp osd 00 00 fh fphu fphl def 00h 01h 02h 05h 0fh 13h 14h 15h 32h 34h 38h 46h 4ch 4fh 50h 51h 52h 53h 54h 5dh 6bh 6dh 6fh 71h 72h 73h 74h 75h 76h 00 08 6e 91 08 a0 4505202002 20 0f 60 71 adj 20202020200080296600 20 20 88 80 80 6ah 6ch 77h 8 ah 00 44 6eh 20 bus condition (input initial data, unless otherwise noted. refer to section 8.1 for the standard data.) symbol hout hptw fv fpvu fpvl vout vdc ewout ewdc
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 22 of 45 5. electrical characteristics test method y block 2ag: cvbs out output level 1. input sg.a to pin 16. 2. measure the amplitude (peak to peak) at pin 15. note: use sub address 01h to select tv1 in, tv2 in, tv3 in, y(y/c) in, y(yuv) in. yout: video standard output level 1. input sg.a to pin 16. 2. measure the amplitude (pedestal to top part) at pins 31, 33 and 35. note: use sub address 01h to select tv1 in, tv2 in, tv3 in, y(y/c) in, y(yuv) in. m pedestal level blanking part output waveform fy: video frequency characteristic 1. input sg.b (f=5mhz, 0.714vp-p) to pin 16. 2. measure the amplitude (peak to peak) except blanking part at pins 31, 33 and 35. the amplitude are defined as yb. 3. fy is defined as follows: yb (v p-p ) fy = 20 log yout (v p-p ) m pedestal level blanking part output waveform vm: vm output level 1. input sg.b (f=3.58mhz, 0.714vp-p) to pin 16. 2. measure the amplitude (peak to peak) at pin 29. c block acc1: acc characteristic 1 1. input sg.c (fec=feb+50khz, veb, vec; standard level) to pin 16. 2. measure the amplitude at pin 31. the amplitude is defined as cnorr. 3. and then, input sg.c (fec=feb+50khz, veb, vec; +6db) to pin 16. 4. measure the amplitude at pin 31. 5. acc1 is defined as follows: measured value (v p-p ) a cc1 = 20 log cnorr (v p-p )
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 23 of 45 acc2: acc characteristic 2 1. input sg.c (fec=feb+50khz, veb, vec; standard level) to pin 16. 2. measure the amplitude at pin 31. the amplitude is defined as cnorr. 3. and then, input sg.c (fec=feb+50khz, veb, vec; -20db) to pin 16. 4. measure the amplitude at pin 31. 5. acc1 is defined as follows: measured value (v p-p ) a cc2 = 20 log cnorr (v p-p ) apcu: apc pull-in range (upper) apcl: apc pull-in range (lower) 1. input sg.c (fec=feb=3.579545mhz) to pin 16. 2. increase the frequency until the waveform at pin 37 and input signal are asynchronous. and then, decrease the frequency and note the point when the waveform at pin 37 and input signal are synchronous; fu. 3. decrease the frequency until the waveform at pin 37 and input signal are asynchronous. and then, increase the frequency and note the point when the waveform and input signal are synchronous; fl. 4. apcu and apcl are defined as follows: apcu = fu - 3579545 (hz) apcl = fl - 3579545 (hz) demp: demodulation phase angle 1. input sg.d to pin 16. 2. measure the amplitude at pin 31 (r-y) and pin 35 (b-y), and defined as vr-y and vb-y respectively. 3. demp is defined as follows: v r-y (mv p-p ) demp = 180 - cos -1 (deg) v b-y (mv p-p ) rgb block vped: output pedestal voltage 1. input sg.a (vy=0v) to pin 16. 2. measure the voltage of pedestal part at pins 31, 33 and 35. m blanking part output waveform gnd vblk: output blanking voltage 1. input sg.a (vy=0v) to pin 16. 2. measure the voltage of blanking part at pins 31, 33 and 35. m blanking part output waveform gnd
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 24 of 45 akbp: akb reference pulse output level 1. input sg.a (vy=0v) to pin 16. 2. measure the amplitude of akb reference pulse at pins 31, 33 and 35. m blanking part output waveform akb reference pulse pedestal part mtxrb: matrix ratio r/b mtxgb: matrix ratio g/b 1. input sg.e (rainbow color bar signal) to pin 16. 2. measure the amplitude vr, vg and vb at pins 31, 33 and 35, respectively. 3. mtxrb and mtxgb are defined as follows: v r (mv p-p ) mtxrb = v b (mv p-p ) v g (mv p-p ) mtxgb = v b (mv p-p ) m blanking part output waveform osd: osd output level 1. input sg.f to pins 16, 57, 58, 59 and 60. 2. measure the output amplitude at pins 31, 33 and 35 except that at blanking part. m pedestal level blanking part output waveform deflection block fh: horizontal free-running frequency 1. measure the output frequency at pin 50 when no signal is input. fhup: h-free-up frequency 1. measure the output frequency at pin 50 when i 2 c bus data of h-free up (sub 13h d0) is set '1'.no signal is input. 2. fhup is defined as follows: fhup = measured value(hz) ? fh (hz)
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 25 of 45 fphu: horizontal pull-in range (upper) fphl: horizontal pull-in range (lower) 1. input sg.g to pin 16. 2. change the frequency of sg.g, and measure the frequency when the output signal at pin 50 and the input signal are synchronous. the horizontal pull-in range is measured by comparing with the horizontal frequency of video signal. 3. fphu and fphl are defined as follows: fphu = measured value (hz) ? 15734 (hz) fphl = measured value (hz) ? 15734 (hz) hout: horizontal pulse amplitude 1. input sg.a to pin 16. 2. measure the amplitude at pin 50. m output waveform hptw: horizontal pulse width 1. input sg.a to pin 16. 2. measure the pulse width of output signal at pin 50. m output waveform fv: vertical free-running frequency 1. measure the output frequency at pins 44 and 45 when no signal is input. fpvu: vertical pull-in range (upper) fpvl: vertical pull-in range (lower) 1. input sg.h to pin 16. 2. change the vertical frequency of sg.h, and measure the frequency when the output signal at pins 44 and 45 and the input signal are synchronous.
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 26 of 45 vout: vertical ramp output level vdc: vertical ramp output dc voltage 1. input sg.a to pin 16. 2. measure the output amplitude at pin 45; vout. 3. measure the dc volatge at pin 45 when the timing is 8.33 sec from start point of vertical ramp; vdc. output waveform gnd 8.33sec vdc vout ewout: e-w output level 1. input sg.a to pin 16. 2. measure the output amplitude at pin 47; ewout. 3. measure the dc volatge at pin 47 when the timing is 8.33 sec from start point of e-w; ewdc. output waveform gnd 8.33sec ewdc ewout
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 27 of 45 6. example of the typical characteristics note: 1. these characteristics are for reference, and not guaranteed by shipment test. 2. bus condition is standard, unless otherwise noted (refer to page 8). sharpness g amma 8 6543 1 01 0 9 frequency (mhz) 10 -30 -20 -15 -10 0 output gain (db) -25 -5 5 7 2 80 60504030 10 01 0 0 90 input luminance level (ire) 800 0 200 300 400 600 output amplitude (mvp-p) 100 500 700 70 20 0c 0a 08 06 02 00 10 0e vm gain data (hex) 800 0 200 300 400 600 vm output amplitude (v) 100 500 700 04 0c 0a 08 06 02 00 10 0e v aparture gain data (hex) 4.0 0 1.0 1.5 2.0 3.0 v aparture gain (db) 0.5 2.5 3.5 04 vm v aparture 60 -60 -40 -20 0 20 40 60 50 40 30 20 10 08 0 70 tint data (hex) color phase (deg) tint control 300 0 50 100 150 200 250 60 50 40 30 20 10 08 0 70 color data (hex) color gain (%) color control input sg.a, vy=variable color=00h input sg.b, vy=0.357v, f=variable color=00h brightness=ffh input sg.b, vy=0.714v, f=3.58mhz input sg.a, vy=0.714v color=00h input sg.c, vy=0.286v, veb=vec=0.286v brightness=ffh input sg.d, signal is standard level gamma=00h gamma=03h sharpness=20h sharpness=00h sharpness=3fh
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 28 of 45 60 50 40 30 20 10 08 0 70 drive data (hex) 5 -5 -3 -2 0 2 3 output signal gain (db) -4 -1 1 4 3.3 2.7 2.8 2.5 2.6 2.9 3.0 3.1 3.2 180 140 100 c0 80 400 200 1c0 cutoff data (hex) output pedestal voltage (v) 1500 0 250 500 750 1000 1250 60 50 40 30 20 10 08 0 70 contrast data (hex) output v ideo amplitude (mvp-p) 3.2 1.6 2.0 2.2 2.4 2.6 2.8 c0 a0 80 60 40 200 100 e0 brightness data (hex) output pedestal voltage (v) 1.8 3.0 800 0 200 300 400 500 600 3.0 2.5 2.0 1.5 1.0 0.5 04 . 0 3.5 acl input voltage (v) v ideo output amplitude (mvp-p) 100 700 3.5 1.5 2.0 2.5 3.0 3.0 2.5 2.0 1.5 1.0 0.5 04.0 3.5 acl input voltage (v) v ideo output dc voltage (v) contrast control abl characteristic acl characteristic drive control cutoff control brightness control input sg.a, vy=variable color=00h acl: off, abl: off input sg.a, vy=variable color=00h acl: off, abl: off input sg.a, vy=0.0v color=00h acl: off, abl: off input sg.a, vy=0.714v color=00h acl: off, abl: off input sg.a, vy=0.714v color=00h brightness=40h analog acl: on input sg.a, vy=0.714v color=00h brightness=ffh digital abl: on vy=0.714v v y=0.357v analog acl gain=00h analog acl gain=01h digital abl gain=08h digital abl gain=00h digital abl gain=0fh vy=0.0v v y=0.714v
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 29 of 45 time (msec) angle 3 4 5 6 7 time (sec) output dc voltage (v) 3 4 5 6 7 time (msec) time (sec) 18 12 108642 01 6 14 18 1210 8642 01 6 14 bow angle=20h angle=3fh angle=00h dct gain=10h dct gain=1fh dct gain=00h 2 4 5 6 8 30 28 20 18 10 08 00 40 38 h-phase data (hex) time (sec) 3 7 eht h-phase 1.0 1.05 1.1 1.15 1.2 3.0 2.5 2.0 1.5 1.0 0.5 04 . 0 3.5 acl input voltage (v) vramp(?) output amplitude (v p-p ) input sg.a, vy=0.714v eht mode=00h v-position=20h v-size=20h v-linearity=20h s-correction=00h eht gain=08h eht gain=00h eht gain=0fh input sg.a, vy=0.714v pin 48=1.65v color=00h acl: off, abl: off input signal h out input sg.a, vy=0.714v pin 48=1.65v h-phase=20h bow=20h input signal h out bow=20h bow=3fh bow=00h input sg.a, vy=0.714v pin 48=1.65v h-phase=20h angle=20h input signal h out 2 4 5 6 8 3.0 2.5 2.0 1.5 1.0 0.5 0 4.0 3.5 h-correction input voltage (v) time (sec) 3 7 h-correction input sg.a, vy=0.714v h-phase=20h color=00h acl: off, abl: off input signal h out dct 80 60504030 10 0100 90 input luminance level (ire) 3.3 2.5 2.7 2.8 2.9 3.1 2.6 3.0 3.2 70 20 input sg.a, vy=variable color=00h, brightness=80h contrast=40h, dctv=1eh
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 30 of 45 v-size v-position s-correction vramp( ?) output voltage (v) 0.5 1.0 1.5 2.0 2.5 vramp( ?) output voltage (v) 0.5 1.0 1.5 2.0 2.5 vramp( ?) output voltage (v) 0.5 1.0 1.5 2.0 2.5 vramp( ?) output voltage (v) v-linearity input sg.a, vy=0.714v v-size=20h v-linearity=20h s-correction=00h input sg.a, vy=0.714v v-position=20h v-linearity=20h s-correction=00h input sg.a, vy=0.714v v-position=20h v-size=20h s-correction=00h input sg.a, vy=0.714v v-position=20h v-size=20h v-linearity=20h v-linearity=20h v-linearity=00h v -linearity=3fh v-positon=20h v-positon=00h v -positon=3fh s-correction=00h s-correction=3fh v-size=20h v-size=00h v -size=3fh h-size parabola 0.5 1.0 1.5 2.0 2.5 12 10 8642 01 6 1 8 14 12108642 01 6 1 8 14 time (msec) e-w output voltage (v) 0.5 1.0 1.5 2.0 2.5 12 10 8642 01 6 1 8 14 time (msec) 12108642 01 618 14 time (msec) 12108642 01 618 14 time (msec) 1210 8642 01 618 14 t ime (msec) 2.5 0.5 1.0 1.5 2.0 time (msec) e-w output voltage (v) input sg.a, vy=0.714v parabola=20h trapezium=20h upper-corner=20h lower-corner=20h parabora=20h parabora=00h parabora=3fh h-size=20h h-size=00h h-size=3fh input sg.a, vy=0.714v h-size=20h trapezium=20h upper-corner=20h lower-corner=20h
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 31 of 45 time (msec) trapezium upper-corner 0.5 1.0 1.5 2.0 2.5 e-w output voltage (v) 0.5 1.0 1.5 2.0 2.5 time (msec) e-w output voltage (v) 18 12 108642 01 6 14 18 1210 8642 01 6 14 18 12108642 01 6 14 time (msec) e-w output voltage (v) 2.5 0.5 1.0 1.5 2.0 lower-corner input sg.a, vy=0.714v h-size=20h parabola=20h trapezium=20h lower-corner=20h input sg.a, vy=0.714v h-size=20h parabola=20h trapezium=20h upper-corner=20h upper-corner=30h upper-corner=20h upper-corner=3fh upper-corner=10h upper-corner=00h lower-corner=30h lower-corner=20h lower-corner=3fh lower-corner=10h lower-corner=00h trapezium=20h trapezium=00h t rapezium=3fh input sg.a, vy=0.714v h-size=20h parabola=20h upper-corner=20h lower-corner=20h
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 32 of 45 electrical characteristics (mcu part) 1. electrical characteristics (vdd=55%, vss=0v, f(xin)=8mhz, ta=-20c to 70c, unless otherwise noted) limits parameter symbol min. typ. max. unit test conditions test circuit power source current system operation icc 15 30 ma vdd=5.25v, f(xin)-8mhz osd off data slicer off 1 30 45 osd on 60 200 a vdd=5.25v, f(xin)=0, f(xcin)=32khz, osd off, data slicer off, low-power dissipation mode set (cm5="0", cm6="1") wait mode 2 4 ma vdd=5.25v, f(xin)-8mhz 25 100 a vdd=5.25v, f(xin)=0, f(xcin)=32khz, osd off, data slicer off, low-power dissipation mode set (cm5="0", cm6="1") 1 10 vdd=5.25v, f(xin)=0, f(xcin)=0 high output voltage p10-p16, p20-p27, p40-p45 voh 2.4 v vdd=4.75v, ioh=-0.5ma 2 low output voltage p00-p07,p10, p15, p16, p20-p27, p40-p45 vol 0.4 v vdd=4.75v, ioh=0.5ma 0.4 vdd=4.75v iol=3ma low output voltage p11-p14, 0.6 iol=6ma hysteresis (see note 1) reset, int1, int2, int3, tim2, tim3, sin, sclk, scl1, scl2, sda1, sda2 vt+- vt- 1.3 v vdd=5.0v 3 high input leak current p00-p07, p10-p16, p20-p27, p40-p45, reset iizh 5 a vdd=5.25v, vi=5.25v 4 low input leak current p00-p07, p10-p16, p20-p27, p40-p45, reset iizl 5 a vdd=5.25v, vi=0v 4 i 2 c-bus bus switch connection resistor (between scl1 and scl2, sda1 and sda2) rbs 130 ? vdd=4.75v 5 notes : 1. p06, p07, p23-p25 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p11-p14 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p20-p22 have the hysteresis when these pins are used as serial i/o pins.
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 33 of 45 2. test circuit 1 pin vdd is made the operation state and is measured the circuit, with a ceramic resonator . 8.00mhz vss x out osd clock x in vdd a icc power source voltage 28.64mhz vss each output pin vdd 4.75v 2 v v oh or v ol i oh or i ol after setting each output pin to high level when measuring v oh and to low level when measuring v ol , each pin is measured vss each input pin vdd 5.0v 3 vss each input pin vdd 5.25v 4 a i izh or i izl 4.75v 5 a i bs vss scl1 or sda1 vdd scl2 or sda2 r bs r bs = v bs /i bs v bs after setting each output pin off state, each pin is measured. ( 4 , 5 )
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 34 of 45 application example note: if you will apply this application example to practice, please study it fully. 15p 15p 47 + 1 0.1 tv1 in 47 y(y/c) in 0.1 0.01 c(y/c) in 0.1 0.1 0.1 0.1 tv3 in 1 2 3 6 5 4 10 9 8 7 20 19 18 17 16 15 14 13 12 11 24 23 22 21 25 36 35 34 33 32 31 30 29 28 27 26 40 39 38 37 64 63 62 59 60 61 55 56 57 58 45 46 47 48 49 50 51 52 53 54 41 42 43 44 80 69 70 71 72 73 74 75 76 77 78 79 65 66 67 68 M65582AMF-XXXFP y(yuv) in u(yuv) in v(yuv) in 0.1 47 47 0.01 47 22p 22 0.01 1k + 0.22 0.033 2k + 0.1 0.01 6.8k + + + + + 1 0.01 0.01 1 0.01 + 47 0.01 + 10 22 vdd(5v) vdd(3.3v) 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 0.01 10k 10k 10k 10k 10k 10k 10k 560 1000p 0.1 1m 0.1 1k + 1 220p 47 + 0.0147 + 0.01 47 + 0.01 47 tv2 in + + 0.01 47 0.1 0.1 0.1 47 2.4k 1k 1k vm_out 100 fbp in h out + ? + ? v-ramp(+) v -ramp(?) + ? e-w + ? 1k 3.3k 3.3k 6.8k vdd(9v) + ? r_out 1k 3.3k 3.3k 6.8k + ? g_out 1k 3.3k 3.3k 6.8k + ? b_out 1k 3.3k 3.3k 1 6.8k 220k 2.2k 3.3k x2 x1 x1: murata csa8.00mtz (8.00mhz) x2: siward 1-781-377-21 (14.31818mhz) + reset ic 3.3v h correction + 3.3v abcl in 10k 470p akb in 3.3v 3.3v 0.01
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 35 of 45 description of pin vss (mcu) 5 y filt 7 vdd (mcu) 6 cn vss 2 x in 3 x out 4 2 4 3 pin no. peripheral circuit of pins name note power source for mcu. 0v power source for mcu. 5.0v 5% 7 0v
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 36 of 45 hlf 8 impedance=n.a. (additional filter on pcb board) cmos input impedance>100k ? 8 pin no. peripheral circuit of pins name note power source for digital blocks. 0v power source for digital blocks. 3.3v 5% 9 vhold 9 10 cvin 10 11 y reset 11 vss(digital) 12 vdd(digital) 13 v ol = 0v : reset state v oh = 5v : release from reset state
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 37 of 45 pin no. peripheral circuit of pins name note dct filter 14 14 impedance=n.a. cvbs out 15 15 impedance=150? dc : 0.55v (sync) ac : 1.75v p-p (typ.) 18 16 25 23 21 tv1 in y(y/c) in tv2 in tv3 in y(yuv) in 16 18 21 23 25 impedance=n.a. dc : 0.5v (sync) ac : 1.0v p-p (typ.) 19 c(y/c) in 19 impedance=5k ? dc : 1.0v ac : 0.286v p-p (burst) power source for a/d etc. 3.3v 5% vdd(input) 17
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 38 of 45 pin no. peripheral circuit of pins name note vrt vrb 22 24 22 impedance=50 ? dc : 1.7v (vrt) 0.5v (vrb) 26 27 u(yuv) in v(yuv) in 26 27 impedance=n.a. dc : 1.0v ac : 0.7v p-p (typ.) 31 vm r out g out b out 29 31 33 35 impedance=500 ? dc : 1.65v (vm) 3v (blanking) power source for a/d etc. 0v vss(input) 20 24 vz out 28 28 impedance=400? dc : 2.05v 29 35 33
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 39 of 45 pin no. peripheral circuit of pins name note 37 xtal (ntsc) 37 impedance 1k ? power source for d/a etc. 3.3v 5% 3.3v 5% vdd(output) 30 n.c. 38 test 39 not useful (connect 0.01 f or more capacitor externally) vss(output) 32 vdd(vcxo) 34 vss(def) 36 power source for d/a etc. 0v power source for vcxo etc. power source for deflection block. 0v 39 40 apc filter 40 impedance=n.a. (additional filter on pcb board)
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 40 of 45 pin no. peripheral circuit of pins name note 43 vramp c 43 impedance 12.5k? impedance=n.a. (additional filter on pcb board) dc : 1.65v afc1 filter 41 vramp(?) vramp(+) e-w 44 45 47 ac : 1.0vpp (typ.) vdd(def) 42 power source for deflection blocks. 3.3v 5% 45 41 44 47 impedance=n.a. (additional filter on pcb board) dc : 1.65v hvco fb 46 46 48 impedance>1m? input voltage range : 0 to 3.3v 0v : h out +2.2 sec 3.3v : h out ?2.2 sec h corre 48 impedance 20k?
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 41 of 45 pin no. peripheral circuit of pins name note 51 akb in acl in 51 52 h out 50 14 52 49 y fbp in 49 cmos input v il =0v : rgb output v ih =3.3v : blanlking impedance>100k? a c y 50 cmos in/out 1 impedance>100k? (input) impedance<100? (output) c a p1 4 /sda2 p1 3 /sda1 p1 2 /scl2 p1 1 /scl1 53 54 55 56 b 53 y 56 55 54 cmos in/out 1 impedance>100k? (input) impedance<100? (output) input voltage range : 0 to 3.3v
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 42 of 45 pin no. peripheral circuit of pins name note c a p4 0 p4 1 p4 2 p4 3 p1 0 p4 4 p4 5 57 58 59 60 61 65 67 57 y 60 59 58 cmos in/out 1 impedance>100k? (input) impedance<100? (output) 61 p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 7 /int1 62 63 64 71 62 y 64 63 cmos in/out impedance>100k? (input) impedance<100? (output) 67 65 p0 3 /pwm3/ad1 p0 4 /pwm4/ad2 p0 5 /ad3 p0 6 /int2/ad4 66 68 69 70 66 y 70 69 68 cmos in/out impedance>100k? (input) impedance<100? (output) c a p1 4 /sda2 p1 3 /sda1 p1 2 /scl2 p1 1 /scl1 53 54 55 56 b 53 y 56 55 54 cmos in/out 1 impedance>100k? (input) impedance<100? (output)
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 43 of 45 pin no. peripheral circuit of pins name note c a p2 0 /sclk/ad5 p2 1 /sout/ad6 p2 2 /sin/ad7 74 75 76 74 y 76 75 cmos in/out impedance>100k? (input) impedance<100? (output) 80 p2 6 /xcin p2 7 /xcout 80 1 1 c a p1 5 p1 6 p2 3 /tim3 p2 4 /tim2 p2 5 /int3 72 73 77 78 79 72 y 78 77 73 cmos in/out 1 impedance>100k? (input) impedance<100? (output) 79
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 44 of 45 memory map M65582AMF-XXXFP 0000 16 00bf 16 00c0 16 00ff 16 0100 16 sfr1 area 01ff 16 0200 16 sfr2 area 020f 16 not used 0300 16 0320 16 05bf 16 rom correction function vector 1: addresses 0300 16 vector 2: addresses 0320 16 not used 06ff 16 not used 0800 16 087f 16 not used 0900 16 0b3f 16 1000 16 interrupt vector area ff00 16 ffde 16 ffff 16 osd ram (128 bytes) ram (2048 bytes) rom (60k bytes) zero page special page not used 11400 16 13bff 16 osd rom (10k bytes) not used 10000 16 1ffff 16
M65582AMF-XXXFP rev.1.0, sep.19.2003, page 45 of 45 package dimensions lqfp80-p-1420-0.8 weight(g) ? jedec code eiaj package code lead material cu alloy 80p6u-a plastic 80pin 14 ? 20mm body lqfp ? ? ? 0.2 ? ? ? ? ? ? ? ? ? ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 ? ? i 2 ? ? m d 14.4 ? ? m e 20.4 0? 8? 0.1 1.0 0.5 0.8 16.2 15.8 14.1 13.9 22.2 21.8 14.0 20.1 19.9 20.0 16.0 22.0 0.175 0.125 0.125 0.105 0.47 0.37 0.32 0.05 1.4 1.6 e under planning lp 0.45 0.35 10 ? ? 0.6 0.25 ? 0.75 0.65 0.2 ? x a3 recommended mount pad detail f mmp m d l 2 b 2 m e e e h e 80 65 25 40 24 1 41 64 h d d a y b x m e f a 1 a 2 l 1 l lp a3 c
? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices

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