View AFS090-1FGG256I_6920829.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

actel fusion ? handbook

fusion handbook table of contents low-power flash device handbooks introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i section i ? actel fusion ? datasheet fusion device family overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 dc and power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 package pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 section ii ? user?s guide low-power flash technology fpga array architecture in low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1- 1 global resources and clock conditioning global resources in actel low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 clock conditioning circuits in low-po wer flash devices and mixed-signal fpgas . . . . . . . . . . . . . . .3-1 fusion clock resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 embedded memories fusion embedded flash memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 flashrom in actel?s low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 sram and fifo memories in actel's low- power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 analog system designing the fusion analog system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 fusion design solutions and methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 interfacing with the fusion analog syst em: processor/microcontroller interface . . . . . . . . . . . . . . .10-1 interfacing with the fusion analog system: ip interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 temperature, voltage, and current calibration in fusion fpgas . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 i/o descriptions and usage i/o software control in low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3-1 ddr for actel?s low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 design migration prototyping with afs600 for smaller devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
table of contents programming and security programming flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 security in low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 in-system programming (isp) of actel? s low-power flash devices using flashpro3 . . . . . . . . . . . . .18-1 microprocessor programming of actel?s low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 boundary scan and ujtag boundary scan in low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 ujtag applications in actel?s low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1 board-level requirements fusion board-level design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1 software design tutorials and examples fusion solutions, design examples, and reference designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1 fusion glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
v1.2 i low-power flash device handbooks introduction device handbooks contain all th e information available to help designers understand and use actel's devices. handbook chapters are groupe d into sections on th e website to simplify navigation. each chapter of the handbook can be viewed as an individual pdf file. at the top of the handbook web page, you will see a pdf file for each product family. this file contains the complete device handbook. please re gister for product updates to be notified when a section of the handbook changes. table 1 ? differences between former data sheets and device handbooks description of change comparison between handbook and datasheet the silicon datasheet in the handbook does not contain the same chapters as the previous versions of the datasheets. the former version of the silicon datasheet contained the following: ? general description ? device architecture ? dc and switching characteristics ? packaging the current datasheet now contains: ? product brief (same information as the general description) ? dc and switching characteristics ? packaging the information previously contai ned in the device architecture chapter has been separated into individual chapters and merged with relevant application note co ntent to provide one location for information on each architectural feature. the device architecture section st ill exists in the fusion handbook only . the general description section no longer exists in datasheets. the product brief and the general description consisted of basically the same information but with different titles. to eliminate the duplicated information, we change d the document name to product brief. change tables were carried forward through this process; they contain information from the old datasheets and the new datasheets. it is important that all earlier technical changes from the datasheets are listed so customers can determine if any of the changes affect their designs. ch anges are listed chronolo gically, wi th the most current at the top and the earl ier changes listed below them. version numbers were restarted. the version numbers were restarted wh en the handbooks were created. for example, a datasheet may have been v2.1 and is now v1.0. the category (i.e., advance or production) of the datasheet did not change. the only change occu rred to the actual numbering of the datasheet. all version numbers are located in the footer of the page. publication date the publication date indicates when the document was published and posted to the actel website. the former datasheets were two columns and the current datasheets and handbooks are formatted with one column. we changed the datasheet forma t to accommodate the large graphics and to improve readability.
low-power flash device handbooks introduction ii v1.2 each chapter within a handbook can have a different version number. each chapter in the handbook has its own version number. since the chapters are independent docu ments and can be updated at different times, the version numb ers for each chapte r increment only when a change is made to that chapter. for example, in the proasic3l handbook, the dc and switching section is advance v0.2, the packaging pin assignments se ction is v1.0, and the global resources section is v1.1. the dc and switching section is advance because the data has not been fully characterized. the packaging and global resources chapters are both production versions because the data is final. they have di fferent version numbers because they were updated at different times. chapters can be numbered differently in each of the handbooks, but the version number for a chapter should be consistent througho ut all handbooks. chapters are also pub lished individually without chapter numbers. chapters with shared content are re used across multiple handbooks. the number of chapters in each handbook varies depending on content, so the pin descriptions chapter could be chapter 7 in one handbook and chapter 9 in another. this is shown only in the combined handbook version of the document. the content within the chapters and version numbers is the same across each handbook for that chapter. if the chapter is up dated, it will be reposted for all associated handbooks. there are multiple versions of the i/o structures chapter. there are several major difference s between the families regarding i/o structures, so the informatio n has been grouped by similar families. as a result, we have multiple i/o st ructures chapters to describe the features for each group of families in detail. the part number of the datasheet has changed. part numbers are used internally to track documents. each document has its own unique part number. the number after the second dash indicates the revision of the do cument. for exampl e, in the part number 51700094-006-1, 51700094-006 is the part number and 1 is the revision of the do cument. we start with 0 for all new documents. there is a part number for the current version of the datasheet on the back page with the addresses. in addition, all chapters in the datasheet and handbooks have th eir own unique part numbers. when we implemented the curre nt handbook format, existing documents were assigned new part numbers. the information contained in the core architecture section of the silicon handbook includes information previously found in application notes. the chapters in the si licon handbook combine application notes that previously had very detailed in formation about an architectural feature and information from the former datasheets. in addition, because the information was very similar among several of actel's low-power flash devices, we comb ined the inform ation into one document. the supported families tables describe which devices are supported in the docu ment. the application notes that contained specific architecture information were combined into the handbook and many no longer exist as st andalone application notes. those that do exist in sta ndalone version have been assigned an ac number (top right of first page ) to help identify them. the ac number appears in the standalo ne version and in the handbook chapters where they occur. table 1 ? differences between former datasheets and device handbooks (continued) description of change comparison between handbook and datasheet
low-power flash device handbooks introduction v1.2 iii versions device handbook chapters may have different version numbers. actel?s goal is to provide customers with the latest information in a timely matter. as a result, the handbook chapters will be updated independently of the handbook. categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advance," "preliminary," and "production." the definiti ons of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advance or production) and contains general product information. this document give s an overview of specific device and family information. advance this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on si mulation and/or initia l characterization. the information is believed to be co rrect, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. the location of the followin g information has changed in the current handbook format: former datasheet location current handbook location ccc/pll specification table core architecture dc and switching section > clock conditioning circuits peak-to-peak jitter waveform core archit ecture dc and switching section > clock conditioning circuits table 1 ? differences between former datasheets and device handbooks (continued) description of change comparison between handbook and datasheet
low-power flash device handbooks introduction iv v1.2 part number and revision date part number 51700094-001-2 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.2) page v1.1 (november 2008) table 1 differences between former datasheets and device handbooks was revised to indicate th at only the fusion handbook retains a device architecture section. the information on the i/o structures chapters was revised, as an i/o structures chap ter has been added for nano devices. i v1.0 (january 2008) this document was rewritten to addr ess the differences between the former datasheets and new device handbooks. n/a
section i ? actel fusion ? datasheet

july 2009 i ? 2009 actel corporation actel fusion family of mixed-signal fpgas features and benefits high-performance reprogrammable flash technology ? advanced 130-nm, 7-layer metal, flash-based cmos process ? nonvolatile, retains program when powered off ? live at power-up (lapu) single-chip solution ? 350 mhz system performance embedded flash memory ? user flash memory ? 2 mbits to 8 mbits ? configurable 8-, 16-, or 32-bit datapath ? 10 ns access in read-ahead mode ? 1 kbit of additional flashrom integrated a/d converter (adc) and analog i/o ? up to 12-bit resolution and up to 600 ksps ? internal 2.56 v or external reference voltage ? adc: up to 30 scalable analog input channels ? high-voltage input tolerance: ?10.5 v to +12 v ? current monitor and temperature monitor blocks ? up to 10 mosfet gate driver outputs ? p- and n-channel power mosfet support ? programmable 1, 3, 10, 30 a, and 20 ma drive strengths ? adc accuracy is better than 1% on-chip clocking support ? internal 100 mhz rc oscillator (accurate to 1%) ? crystal oscillator support (32 khz to 20 mhz) ? programmable real-time counter (rtc) ? 6 clock conditioning circuits (cccs) with 1 or 2 integrated plls ? phase shift, multiply/divide, and delay capabilities ? frequency: input 1.5?350 mhz, output 0.75?350 mhz low power consumption ? single 3.3 v power supply with on-chip 1.5 v regulator ? sleep and standby low-power modes in-system programming (isp) and security ? secure isp with 128-bit aes via jtag ?flashlock ? to secure fpga contents advanced digital i/o ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages ? up to 5 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v /1.8 v / 1.5 v, 3.3 v pci / 3.3 v pci-x, and lvcmos 2.5 v / 5.0 v input ? differential i/o standards: lvpecl, lvds, b-lvds, m-lvds ? built-in i/o registers ? 700 mbps ddr operation ? hot-swappable i/os ? programmable output slew ra te, drive strength, and weak pull-up/down resistor ? pin-compatible packages across the fusion family srams and fifos ? variable-aspect-ratio 4,608-bit sram blocks (1, 2, 4, 9, and 18 organizations available) ? true dual-port sram (except 18) ? programmable embedded fifo control logic soft arm ? cortex?-m1 fusion devices (m1) ? arm cortex-m1?enabled (without debug) pigeon point atca ip support (p1) ? targeted to actel's pigeon point ? board management reference (bmr) starter kits ? in partnership with pigeon point systems ? arm cortex-m1 enabled microblade advanced mezzanine card support (u1) ? targeted to advanced mezzanine card (advancedmc designs) ? designed in partnership with microblade ? 8051-based module management controller (mmc) fusion family fusion devices afs090 afs250 afs600 afs1500 arm cortex-m1 * devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 p1afs1500 microblade devices u1afs600 general information system gates 90,000 250,000 600,000 1,500,000 tiles (d-flip-flops) 2,304 6,144 13,824 38,400 secure (aes) isp yes yes yes yes plls 1122 globals 18181818 memory flash memory blocks (2 mbits) 1 1 2 4 total flash memory bits 2m 2m 4m 8m flashrom bits 1,024 1,024 1,024 1,024 ram blocks (4,608 bits) 6 8 24 60 ram kbits 27 36 108 270 analog and i/os analog quads 5 6 10 10 analog input channels 15 18 30 30 gate driver outputs 5 6 10 10 i/o banks (+ jtag) 4455 maximum digital i/os 75 114 172 252 analog i/os 20 24 40 40 note: *refer to the cortex-m1 product brief for more information. v2.0 ?
actel fusion family of mixed-signal fpgas ii v2.0 fusion device architecture overview package i/os: single-/double-ended (analog) figure 1-1 ? fusion device architecture overview (afs600) fusion devices afs090 afs250 afs600 afs1500 arm cortex-m1 devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 2, 3 p1afs1500 2, 3 microblade devices u1afs600 2 qn108 37/9 (16) qn180 60/16 (20) 65/15 (24) pq208 1 93/26 (24) 95/46 (40) fg256 75/22 (20) 114/37 (24) 119/58 (40) 119/58 (40) fg484 172/86 (40) 223/109 (40) fg676 252/126 (40) notes: 1. fusion devices in the same package are pin compatible wi th the exception of the pq208 package (afs250 and afs600). 2. microblade devices are only offered in fg256. 3. pigeon point devices are only offered in fg484 and fg256. versatile ccc ccc i/os osc c cc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad
product ordering codes v2.0 iii product ordering codes notes: 1. for fusion devices, quad flat no lead packages are only of fered as rohs compliant, qng packages. 2. microblade and pigeon point devices only support fg packages. m1afs600 fg _ part number fusion devices speed grade 1 blank = standard 1 = 15% faster than standard 2 = 25% faster than standard package type qn = quad flat no lead (0.5 mm pitch) 256 i g package lead count application (junction temperature range) blank = commercial (0 to +85c) i = industrial (?40 to +100c) pp = pre-production es = engineering silicon (room temperature only) 90,000 system gates afs090 = 250,000 system gates afs250 = arm-enabled fusion devices 600,000 system gates afs600 = 1,500,000 system gates afs1500 = microblade devices 600,000 system gates u1afs600 = pigeon point devices 600,000 system gates p1afs600 = 1,500,000 system gates p1afs1500 = 250,000 system gates m1afs250 = 600,000 system gates m1afs600 = 1,500,000 system gates m1afs1500 = pq = plastic quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch) lead-free packaging options blank = standard packaging g = rohs-compliant (green) packaging 1 2
actel fusion family of mixed-signal fpgas iv v2.0 temperature grade offerings speed grade and temperature grade matrix contact your local actel representa tive for device availability ( http://www.actel.com/contact/offices/index.html ). cortex-m1, pigeon point, and microblade fusion device information this datasheet provides information for a ll fusion (afs), cortex-m1 (m1), pigeon point (p1), and microblade (u1) devices. the remainder of the document will on ly list the fusion (afs) devi ces. please apply relevant information to m1, p1, and u1 devices when appropriate. please note the following: ? cortex-m1 devices are offered in the same speed grades and packages as basic fusion devices. ? pigeon point devices are only offered in ?2 speed grade and fg484 and fg256 packages. ? microblade devices are only offered in standard speed grade and the fg256 package. fusion devices afs090 afs250 afs600 afs1500 arm cortex-m1 devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 3 p1afs1500 3 microblade devices u1afs600 4 qn108 c, i ? ? ? qn180 c, i c, i ? ? pq208 ? c, i c, i ? fg256 c, ic, ic, ic, i fg484 ? ? c, i c, i fg676 ? ? ? c, i notes: 1. c = commercial temperature range: 0c to 85c junction 2. i = industrial temperature ra nge: ?40c to 100c junction 3. pigeon point devices are only offered in fg484 and fg256. 4. microblade devices are only offered in fg256. std. 1 ?1 ?2 2 c 3 ??? i 4 ??? notes: 1. microblade devices are only offered in standard speed grade. 2. pigeon point devices are only offered in ?2 speed grade. 3. c = commercial temperature range: 0c to 85c junction 4. i = industrial temperature ra nge: ?40c to 100c junction
v2.0 1-1 1 ? fusion device family overview introduction the actel fusion ? mixed-signal fpga satisfies the demand from system architects for a device that simplifies design and unleashes their creativity. as the world?s first mi xed-signal programmable logic family, fusion integrates mi xed-signal analog , flash memory, and fpga fabric in a monolithic device. actel fusion devices enable designers to quickly move from conc ept to completed design and then deliver feature-rich systems to market . this new technology takes advantage of the unique properties of actel flash- based fpgas, including a high-isola tion, triple-well process and the ability to support high-voltage transistors to meet the demanding requirements of mixed-signal system design. actel fusion mixed-signal fpgas bring the benefits of programmable logic to many application areas, including power management, smart battery charging, clock generation and management, and motor control. until now, these applications have only been implem ented with costly and space-consuming discrete analog components or mi xed-signal asic solution s. actel fusion mixed- signal fpgas present new capabili ties for system development by a llowing designers to integrate a wide range of functionalit y into a single device, while at the same time offering the flexibility of upgrades late in the manufacturing process or after the device is in the fiel d. actel fusi on devices provide an excellent alternative to costly and time-consuming mixed-si gnal asic designs. in addition, when used in conjunction with the acte l cortex-m1, actel fusion technology represents the definitive mixed- signal fpga platform. flash-based fusion devices are li ve at power-up. as soon as sy stem power is applied and within normal operating specifications, fu sion devices are working. fusion devices have a 128-bit flash- based lock and industry-leading aes decryption, us ed to secure programmed intellectual property (ip) and configuration data. actel fusion devices are the most comprehensive single-chip analog and digital programmable logic solution available today. to support this new ground-breaking technology , actel has developed a series of major tool innovations to help maximize designer producti vity. implemented as exte nsions to the popular actel libero ? integrated design enviro nment (ide), these new tool s allow design ers to easily instantiate and configure peripherals within a de sign, establish links between peripherals, create or import building blocks or reference designs, and perform hardware verification. this tool suite will also add comprehensive hardwa re/software debug capability as well as a suite of utilities to simplify development of embedded soft-processor- based solutions. general description the actel fusion family, based on the highly successful proasic ? 3 and proasic3e flash fpga architecture, has been designed as a high-perfo rmance, programmable, mi xed-signal platform. by combining an advanc ed flash fpga core with flash memory blocks and analog peripherals, fusion devices dramatically simplify system design and, as a result, dramatically reduce overall system cost and board space. the state-of-the-art flash memory technology offe rs high-density integrated flash memory blocks, enabling savings in cost, power, and board area relati ve to external flash so lutions, while providing increased flexibility and performance. the flash me mory blocks and integrated analog peripherals enable true mixed-mode programmable logic designs. two examples are using an on-chip soft processor to implem ent a fully functional flash mcu and using high-speed fpga logic to offer system and power supervisory capabilities. live at power-up and capable of operating from a single 3.3 v supply, the fusion family is ideally suited for system management and control applications. the devices in the fusion fami ly are categorized by fpga core density. each family member contains many peripherals, incl uding flash memory blocks, an an alog-to-digital-converter (adc), high-drive outputs, both rc and crystal oscillators, and a real-time counter (rtc). this provides the
fusion device family overview 1-2 v2.0 user with a high level of flexibility and integr ation to support a wide variety of mixed-signal applications. the flash memory block capacity ranges from 2 mbits to 8 mbits. the integrated 12-bit adc supports up to 30 independently configurable input channels. the on-chip crystal and rc oscillators work in conjunction with the integrated phase-locked loops (plls) to provide clocking support to the fpga array and on-chip re sources. in addition to supporting typical rtc uses such as watchdog timer, the fusion rtc ca n control the on-chip volt age regulator to power down the device (fpga fabric, flash memory bloc k, and adc), enabling a low-power standby mode. the actel fusion family offers revolutionary features, never befo re available in an fpga. the nonvolatile flash technology gives the fusion soluti on the advantage of being a secure, low-power, single-chip solution that is live at power-up. fu sion is reprogrammable and offers time-to-market benefits at an asic-level unit cost. these features enable design ers to create high-density systems using existing asic or fp ga design flows and tools. flash advantages reduced cost of ownership advantages to the designer extend beyond low unit cost, high performance, and ease of use. flash- based fusion devices are live at power-up and do not need to be loaded from an external boot prom. on-board security mechan isms prevent access to the programming information and enable secure remote updates of the fpga logic. de signers can perform secure remote in-system reprogramming to support future design iterat ions and field upgrades, with confidence that valuable ip cannot be compromi sed or copied. secure isp can be performed using the industry- standard aes algorithm with mac data authentica tion on the device. the fusion family device architecture mitigates the need for asic migratio n at higher user volume s. this makes the fusion family a cost-effective asic repl acement solution for ap plications in the consumer, networking and communications, co mputing, and avionics markets. security as the nonvolatile, flash-based fusion family requires no boot prom, there is no vulnerable external bitstream. fusion device s incorporate flashlock, which pr ovides a unique combination of reprogrammability and design securi ty without external overhead, advantages that only an fpga with nonvolatile flash programming can offer. fusion devices utilize a 128-bit flash-based key lo ck and a separate aes key to secure programmed ip and configuration data. the flashrom data in fusion devices can also be encrypted prior to loading. additionally, the flash memory blocks can be programmed during runtime using the industry-leading aes-128 block ci pher encryption standard (fips publication 192). the aes standard was adopted by the national institute of standard s and technology (nist) in 2000 and replaces the des standard, which was adopted in 1977. fusion devices have a built-in aes decryption engine and a flash-based aes key that make fusion de vices the most comprehens ive programmable logic device security solution available today. fusion devices with aes-based security allow for secure remote field updates over public networks, such as the internet, and ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip th ieves. as an additional security measure, the fpga configuration data of a programmed fusion device cannot be read back, although secure design verifi cation is possible. during design , the user controls and defines both internal and external acce ss to the flash memory blocks. security, built into the fpga fabric , is an inherent component of th e fusion family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. fusion with flashlock and aes security is unique in being highly resistant to both invasive and noninvasive attacks. your valuable ip is protected, making secure remote isp possible. a fusion de vice provides the most im penetrable security for programmable logic designs. single chip flash-based fpgas store their configuration information in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga structure, and no external configuration data needs to be loaded at system power-up (u nlike sram-based fpgas). therefore, flash-based fusion fpgas do not require system conf iguration components such as eeproms or
general description v2.0 1-3 microcontrollers to load device configuration da ta. this reduces bill-of-materials costs and pcb area, and increases securi ty and system reliability. live at power-up flash-based fusion device s are level 0 live at power-up (lapu). lapu fusion device s greatly simplify total system design and reduce total system cost by eliminating the need for cplds. the fusion lapu clocking (plls) replaces off-chip clocking resources. the fusion mi x of lapu clocking and analog resources makes these devi ces an excellent choice for both system supervisor and system management functions. lapu from a single 3.3 v source enables fusi on devices to initiate, control, and monitor multiple voltage supplies while also providing system clocks. in addition, glitches and brownouts in system power will no t corrupt the fusion device fl ash configuration. unlike sram- based fpgas, the device will not have to be reload ed when system power is restored. this enables reduction or complete removal of expensive voltage monitor and brownout detection devices from the pcb design. flash-based fusion devices simplify total system design and reduce cost and design risk, while increasing system reliability. firm errors firm errors occur most commonly when high-energ y neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energy of the coll ision can change the state of the configuration cell and thus change the logic, routing, or i/o behavior in an unpredictable way. another source of radiation-indu ced firm errors is alpha particles. for an alpha to cause a soft or firm error, its source must be in very close proxim ity to the affected circuit. the alpha source must be in the package molding compound or in the die itself. while low-alpha molding compounds are being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors. firm errors are impossible to prevent in sram fp gas. the consequence of this type of error can be a complete system failure. firm errors do not occur in fusion flash-based fpgas. once it is programmed, the flash cell config uration element of fusion fpga s cannot be altered by high- energy neutrons and is therefor e immune to errors from them. recoverable (or soft) errors occur in the user da ta srams of all fpga devices. these can easily be mitigated by using error detectio n and correction (edac) circui try built into the fpga fabric. low power flash-based fusion devices exhibi t power characteristics similar to those of an asic, making them an ideal choice for power-sensitive applications. wi th fusion devices, there is no power-on current surge and no high current transition, both of which occur on many fpgas. fusion devices also have low dynamic power consumption and support both low power standby mode and very low powe r sleep mode, offering further power savings. advanced flash technology the fusion family offers many benefits, includ ing nonvolatility and re programmability through an advanced flash-based, 130-nm lvcm os process with seven layers of metal. standard cmos design techniques are used to implement logic and control functi ons. the combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows very high logic utilization (much higher than competing sram technologies ) without compro mising device routability or performance. logic functions within the device are interconnected through a four-level routing hierarchy. advanced architecture the proprietary fusion architecture provides granularity co mparable to standard-cell asics. the fusion device consists of several distinct and pr ogrammable architectural features, including the following ( figure 1-1 on page 1-5 ): ? embedded memories ? flash memory blocks ?flashrom
fusion device family overview 1-4 v2.0 ? sram and fifo ? clocking resources ? pll and ccc ? rc oscillator ? crystal oscillator ? no-glitch mux (ngmux) ? digital i/os with advanced i/o standards ? fpga versatiles ? analog components ? adc ? analog i/os supporting voltage, current, and temperature monitoring ? 1.5 v on-board voltage regulator ? real-time counter the fpga core consists of a sea of versatiles. ea ch versatile can be configured as a three-input logic lookup table (lut) equivalent or a d-fl ip-flop or latch (with or without enable) by programming the appropriate flash switch interconne ctions. this versatility allows efficient use of the fpga fabric. the versatile capability is uniq ue to the actel families of flash-based fpgas. versatiles and larger functions are connected with any of the four le vels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circ uitry allows for rapid (3.3 v) single-voltage programming of fusion devices via an ieee 1532 jtag interface. unprecedented integration integrated analog blocks and analog i/os fusion devices offer robust and flex ible analog mixed-signal capabi lity in addition to the high- performance flash fpga fabric and flash memory block. the many built-in analog peripherals include a configurable 32:1 input analog mux, up to 10 independent mosfet gate driver outputs, and a configurable adc. the adc supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per second (ksps), diff erential nonlinearity (dnl) < 1.0 lsb, and total unadjusted error (tue) of 0.72 lsb in 10-bit mode. the tue is used for characterization of the conversion error and includes errors from all sources, su ch as offset and linearity. internal bandgap circui try offers 1% voltage reference accuracy with the flexibility of utilizing an external reference vo ltage. the adc channel sampling sequence and sampling rate are programmable and implemented in the fpga logi c using designer and li bero ide software tool support. two channels of the 32-channel adcmux are dedica ted. channel 0 is conn ected internally to v cc and can be used to monitor core power supply. channel 31 is connec ted to an internal temperature diode which can be used to monitor device te mperature. the 30 rema ining channels can be connected to external an alog signals. the exact number of i/ os available for external connection signals is devi ce-dependent (refer to the "fusion family" table on page i for details). with fusion, actel also introduces the analog quad i/ o structure ( figure 1-1 on page 1-5 ). each quad consists of three analog inputs and one gate driver. each quad can be configured in various built-in circuit combinations, such as three presca ler circuits, three digital input circuits, a current monitor circuit, or a temperature monitor ci rcuit. each prescaler has multiple scaling factors programmed by fpga signals to su pport a large range of analog in puts with positive or negative polarity. when the curren t monitor circuit is selected, two ad jacent analog inputs measure the voltage drop across a small external sense resi stor. for more information , refer to the "analog system characteristics " section in the device architecture chapter of the datasheet for more information. built-in oper ational amplifiers amplify small vo ltage signals for accurate current measurement. one analog input in each quad can be connecte d to an external temperature
unprecedented integration v2.0 1-5 monitor diode. in addition to the external temperature monitor diode(s), a fusion device can monitor an internal temper ature diode using dedicated channel 31 of the adcmux. figure 1-1 on page 1-5 illustrates a typical use of the anal og quad i/o structure. the analog quad shown is configured to monitor and control an external power supply. the av pad measures the source of the power supply. the ac pad measures th e voltage drop across an external sense resistor to calculate current. the ag mosfet gate driver pad turns the external mo sfet on and off. the at pad measures the load -side voltage level. embedded memories flash memory blocks the flash memory available in each fusion device is composed of one to four flash blocks, each 2 mbits in density. each block operates independently with a dedicated flash controller and interface. fusion flash memory blocks combine fast access times (60 ns random access and 10 ns access in read-ahead mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high-speed flash operation without wait states. the memory block is organized in pages and sectors. each page has 128 bytes, with 33 pages comprising one sector and 64 sectors per bl ock. the flash block can support multiple partitions. the only constrai nt on size is that partition boundaries must coincide with page boundaries. the flexibility and granularity enable many use models and allow added granularity in programming updates. fusion devices support two methods of external access to the flash memory blocks. the first method is a serial interface that features a bu ilt-in jtag-compliant port, which allows in-system programmability during user or mo nitor/test modes. this serial interface supports programming of figure 1-1 ? analog quad analog quad av ac at voltage monitor block current monitor block ag power line side load side pre- scaler digital input power mosfet gate driver current monitor/instr amplifier temperature monitor digital input digital input pre- scaler pre- scaler pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip r pullup from fpga (gdonx)
fusion device family overview 1-6 v2.0 an aes-encrypted stream. secure da ta can be passed through the jtag interface, decrypted, and then programmed in the flas h block. the second method is a soft parallel interface. fpga logic or an on-chip soft microprocessor can access flash memory through the parallel interface. since the flash parallel interface is implemented in the fpga fabric, it can potentially be customized to meet special user requirem ents. for more information, refer to the corecfi handbook. the flash memory parallel in terface provides configurable byte-wide (8), word-wide (16), or dual-word-wide (32) data port options. through the programmable flash parallel interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations. the flash memory has built-in secu rity. the user can configure either the entire flash block or the small blocks to prevent unintentional or intr usive attempts to change or destroy the storage contents. each on-chip flash memory block ha s a dedicated controller, enabling each block to operate independently. the flash block logic consists of the following sub-blocks: ? flash block ? contains all stored data. the flash block contains 64 sectors and each sector contains 33 pages of data. ? page buffer ? contains the contents of the cu rrent page being modified. a page contains 8 blocks of data. ? block buffer ? contains the contents of th e last block accessed. a block contains 128 data bits. ? ecc logic ? the flash memory stores erro r correction information with each block to perform single-bit error correction and double-bit error detection on all data blocks. user nonvolatile flashrom in addition to the flash blocks, actel fusion devices have 1 kbit of user-accessible, nonvolatile flashrom on-chip. the flashrom is organized as 8128-bit pages. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business mode ls (for example, set-top boxes) ? secure key storage for secu re communicati ons algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard ie ee 1532 jtag programming interface. pages can be individually programmed (erased and written). on-chip aes decryption can be used selectively over public networks to securely load data such as security keys st ored in the flas hrom for a user design. the flashrom can be programmed (erased and wri tten) via the jtag programming interface, and its contents can be read back either through th e jtag programming interface or via direct fpga core addressing. the flashpoint tool in the actel fusion developm ent software solutions, libero ide and designer, has extensive support for flash me mory blocks and flashrom. one su ch feature is auto-generation of sequential programmin g files for applicat ions requiring a unique se rial number in each part. another feature allows the inclusion of static data for system version control. data for the flashrom can be generated quickly and easily using the actel libero ide and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. sram and fifo fusion devices have embedded sram blocks alon g the north and south sides of the device. each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. th e individual blocks have indepe ndent read and write ports that can be configured with different bit widths on each port. for example, data can be written
unprecedented integration v2.0 1-7 through a 4-bit port and read as a single bitstre am. the sram blocks can be initialized from the flash memory blocks or via the device jtag port (rom emulation mode), using the ujtag macro. in addition, every sram block has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fi fo without using additional core versatiles. the fifo width and depth are programmable. the fifo also features programmable almost empty (aempty) and almost full (afull) flags in addition to the normal empty and full flags. the embedded fifo control unit contains the counte rs necessary for the genera tion of the read and write address pointers. the sram/fifo blocks can be cascaded to create larger configurations. clock resources plls and clock conditi oning circuits (cccs) fusion devices provide designers with very flexible clock conditioning capa bilities. each member of the fusion family contains six cccs. in the two larger family members, two of these cccs also include a pll; the smaller devices support one pll. the inputs of the ccc blocks are accessible from the fpga core or from one of several inputs with dedicated ccc block connections. the ccc block has the following key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz to 350 mhz ? output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz ? clock phase adjustment via pr ogrammable and fixed delays from ?6.275 ns to +8.75 ns ? clock skew minimization (pll) ? clock frequency synthesis (pll) ? on-chip analog clocking resources usable as inputs: ? 100 mhz on-chip rc oscillator ? crystal oscillator additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270 ? output duty cycle = 50% 1.5% ? low output jitter. samples of peak-to-peak period jitter when a single global network is used: ? 70 ps at 350 mhz ? 90 ps at 100 mhz ? 180 ps at 24 mhz ? worst case < 2.5% clock period ? maximum acquisition time = 150 s ? low power consumption of 5 mw global clocking fusion devices have exte nsive support for multiple clocking domains. in addition to the ccc and pll support described above, there are on-chip oscillators as well as a comprehensive global clock distribution network. the integrated rc oscillator generates a 100 mhz cl ock. it is used internally to provide a known clock source to the flash memory re ad and write control. it can also be used as a source for the plls. the crystal oscillator supports the following operating modes: ? crystal (32.768 khz to 20 mhz) ? ceramic (500 khz to 8 mhz) ? rc (32.768 khz to 4 mhz) each versatile input and output port has access to nine versanets: six main and three quadrant global networks. the versanets can be driven by the ccc or directly acce ssed from the core via
fusion device family overview 1-8 v2.0 muxes. the versanets can be used to distribute lo w-skew clock signals or for rapid distribution of high-fanout nets. digital i/os with advanced i/o standards the fusion family of fpgas features a flexible digital i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). fusion fpgas supp ort many different digital i/o standards, both single-ended an d differential. the i/os are organized into banks, with four or five banks per device. the configuration of these banks determines the i/o standards supported. th e banks along the east and west sides of the device support the full range of i/o standards (single-ended and differ ential). the south bank supports the analog quads (analog i/o). in th e family's two smaller devices, the north bank supports multiple single-ended digital i/o standard s. in the family?s larger devices, the north bank is divided into two banks of digital pro i/os, supporting a wide variety of single-ended, differential, and voltage-referenced i/o standards. each i/o module contains several input, output , and enable registers. these registers allow the implementation of the following applications: ? single-data-rate (s dr) applications ? double-data-rate (ddr) applications?ddr lvds i/o for chip-to-chip communications ? fusion banks support lvpecl, lvds, blvds, and m-lvds with 20 multi-drop points. versatiles the fusion core consists of versatiles, which are also used in the successful actel proasic3 family. the fusion versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set and optional enable refer to figure 1-2 for the versatile configuration arrangement. figure 1-2 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ffe data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
related documents v2.0 1-9 related documents datasheet core8051 www.actel.com/ipdo cs/core8051_ds.pdf application notes fusion flashrom http://www.actel.com/documents/fusion_from_an.pdf fusion sram/fifo blocks http://www.actel.com/documen ts/fusion_ram_fifo_an.pdf using ddr in fusion devices http://www.actel.com/documents/fusion_ddr_an.pdf fusion security http://www.actel.com/documen ts/fusion_secu rity_an.pdf using fusion ram as multipliers http://www.actel.com/documents/fusion_multipliers_an.pdf handbook cortex-m1 handbook www.actel.com/documents/cortexm1_hb.pdf fusion handbook http://www.actel.com/documents/fusion_hb.pdf prototyping with afs600 for smaller devices http://www.actel.com/documen ts/fusion_prototyp_hbs.pdf ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf in-system programming (isp) of actel's low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf user?s guides designer user's guide http://www.actel.com/documents/designer_ug.pdf fusion, igloo/e and proasi c3/e macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf smartgen, flashrom, flash memo ry system builder, and analog system builder user's guide http://www.actel.com/documents/genguide_ug.pdf white papers fusion technology http://www.actel.com/documents/fusion_tech_wp.pdf
fusion device family overview 1-10 v2.0 part number and revision date part number 51700092-013-1 revised july 2009 list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v2.0) page preliminary v1.7 (october 2008) the microblade and fusion datasheets have been combin ed. pigeon point information is new. coremp7 support was removed sinc e it is no longer offered. ?f was removed from the datasheet since it is no longer offered. the operating temperature was changed from ambient to junction to better reflect actual condit ions of operations. commercial: 0c to 85c industrial: ?40c to 100c the version number category was changed from preliminary to production, which means the datasheet contai ns information based on final characterization. the version number ch anged from preliminary v1.7 to v2.0. n/a the "integrated analog blocks and analog i/os" section was updated to include a reference to the "a nalog system characteristics " section in the device architecture chapter of the datasheet, which includes table 2-46 ? analog channel specifications and specific voltage data. 1-4 advance v1.6 (august 2008) the version number category was change d from advance to preliminary, which means the datasheet contains informatio n based on simulation and/or initial characterization. the information is be lieved to be correct, but changes are possible. advance v1.4 (july 2008) the title of the datasheet changed fr om actel programmable system chips to actel fusion mixed- signal fpgas. in addition, all instances of programmable system chip were changed to mixed-signal fpga. n/a advance v0.9 (october 2007) the following bullet was updated from hi gh-voltage input tolerance: 12 v to high-voltage input tolerance: 10.5 v to 12 v. i the following bullet was updated from programmable 1, 3, 10, 30 a and 25 ma drive strengths to programmable 1, 3, 10, 30 a and 20 ma drive strengths. i this bullet was added to the "integrated a/d converter (adc) and analog i/o" section : adc accuracy is better than 1% i in the "integrated analog blocks and analog i/os" section , 4 lsb was changed to 0.72. the following sentence was deleted: the input range for voltage signals is from ?12 v to + 12 v with full-scale output values from 0.125 v to 16 v. in addition, 2c was changed to 3c: "one analog input in each quad can be connected to an external temperature monitor diode and achieves de tection accuracy of 3oc." the following sentence was deleted: the input range for voltage signals is from ?12 v to + 12 v with full-scale output values from 0.125 v to 16 v. 1-4
list of changes v2.0 1-11 advance v0.7 (january 2007) in the "package i/os: single-/double-ended (analog)" table , the afs1500/m7afs1500 i/o counts were updated for the following devices: fg484: 223/109 fg676: 252/126 ii advance v0.4 (april 2006) the afs1500 digital i/o count was updated in the "fusion family" table . i the afs1500 digital i/o co unt was updated in the "package i/os: single- /double-ended (analog)" table . ii advance v0.3 (april 2006) the g was moved in the "product ordering codes" section . iii advance v0.2 (april 2006) the "features and benefits" section was updated. i the "fusion family" table was updated. i the "package i/os: single-/double-ended (analog)" table was updated. ii advance v0.2 (continued) the "product ordering codes" table was updated. iii the "temperature grade offerings" table was updated. iv the "general description" section was updated to incl ude arm information. 1-1 previous version changes in current version (v2.0) page
fusion device family overview 1-12 v2.0 datasheet categories categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advance," "preliminary," and "production." the definiti ons of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advance or production) and contains general product information. this document give s an overview of specific device and family information. advance this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on si mulation and/or initia l characterization. the information is believed to be co rrect, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information.
v2.0 2-1 2 ? device architecture fusion stack architecture to manage the unprecedented level of integratio n in fusion devices, ac tel developed the fusion technology stack ( figure 2-1 ). this layered model offers a fl exible design environment, enabling design at very high and very low levels of abstra ction. fusion peripheral s include hard analog ip and hard and soft digital ip. perip herals communicate across the fpga fabric via a layer of soft gates?the fusion backbone. much more than a common bus interface, this fusion backbone integrates a micro-sequencer within the fpga fabric and configures the indi vidual peripherals and supports low-level processing of peripheral da ta. fusion applets are application building blocks that can control and respond to peripherals and other system si gnals. applets can be rapidly combined to create large applicatio ns. the technology is scalable across devices, families, design types, and user expertise, and supports a well -defined interface for external ip and tool integration. at the lowest level, level 0, ar e fusion peripherals. these are conf igurable functional blocks that can be hardwired structures such as a pll or anal og input channel, or soft (fpga gate) blocks such as a uart or two-wire serial interface. the fusi on peripherals are configurable and support a standard interface to facilitate communication and implementation. connecting and controlling access to the peripherals is the fusion backbone, level 1. the backbone is a soft-gate structure, scalable to any number of peripherals. the backbone is a bus and much more; it manages peripheral configuration to en sure proper operation. leveraging the common peripheral interface and a low-lev el state machine, the backbone efficiently offloads peripheral management from the system desi gn. the backbone can set and clear flags based upon peripheral behavior and can define performa nce criteria. the flexibility of the stack enables a designer to configure the silicon, directly bypassing the backbone if that level of control is desired. one step up from the backbone is the fusion applet, leve l 2. the applet is an application building block that implements a specific function in fpga gates. it can react to stimuli and board-level events coming through the backbone or from ot her sources, and respon ds to these stimuli by accessing and manipulating peripherals via the back bone or initiating some other action. an applet controls or responds to the peri pheral(s). applets can be easily imported or exported from the design environment. the applet structure is open and well-def ined, enabling users to import applets from actel, system developers, third parties, and user groups. note: levels 1, 2, and 3 are implemented in fpga logic gates. figure 2-1 ? fusion architecture stack flash memory analog smart peripheral 1 analog smart peripheral 2 analog smart peripheral n smart peripherals in fpga fabric (e.g., logic, pll, fifo) fusion smart backbone fusion applets user applications level 1 level 0 level 2 level 3 optional arm or 8051 processor
fusion family of mi xed-signal flash fpgas device architecture 2-2 v2.0 the system application, level 3, is the larger us er application that utili zes one or more applets. designing at the highest level of abstraction supp orted by the actel fusion technology stack, the application can be easily created in fpga gates by importing and configuring multiple applets. in fact, in some cases an entire fpga system design can be created without any hdl coding. an optional mcu enables a combination of softw are and hdl-based design methodologies. the mcu can be on-chip or off-chip as system requirem ents dictate. system porti oning is very flexible, allowing the mcu to reside abov e the applets or to absorb appl ets, or applets and backbone, if desired. the actel fusion technology stack enables a very flexible design environment. users can engage in design across a continuum of abstract ion from very low to very high. core architecture versatile based upon successful actel proasic3/e logic ar chitecture, fusion devices provide granularity comparable to gate arrays. the fu sion device core consists of a sea-of-versatiles architecture. as illustrated in figure 2-2 , there are four inputs in a logic versatile cell, and each versatile can be configured using the appropriat e flash switch connections: ? any 3-input logic function ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set (on a 4th input) versatiles can flexibly map the logic and sequenti al gates of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and th e output of the tile can connect to high-speed, very-long-line routing re sources. versatiles and larger function s are connected with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-f lop, the set/clr signal is supported by a fourth input, which can only be routed to the core cell over the versanet (global) network.
core architecture v2.0 2-3 the output of the versatile is f2 wh en the connection is to the ultra-fast loca l lines, or yl when the connection is to the ef ficient long-line or ve ry-long-line resources ( figure 2-2 ). note: *this input can only be connected to the global clock distribution network. figure 2-2 ? fusion core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc* f2 yl
fusion family of mi xed-signal flash fpgas device architecture 2-4 v2.0 versatile characteristics sample versatile specifications?combinatorial module the fusion library offers all combin ations of lut-3 combinatorial functions. in this section, timing characteristics are presented fo r a sample of the library ( figure 2-3 ). for more details, refer to the fusion, igloo/e and proasi c3/e macro library guide . figure 2-3 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
core architecture v2.0 2-5 figure 2-4 ? combinatorial timing model and waveforms t pd t pd t pd v cca v cca t pd t pd v cca t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell nand2 or any combinatorial logic a b y (rr) a, b, c out 50% gnd (ff) 50% 50% 50% gnd (rf) 50% (fr) 50% out gnd
fusion family of mi xed-signal flash fpgas device architecture 2-6 v2.0 timing characteristics sample versatile specifications?sequential module the fusion library offers a wide vari ety of sequential cells, includin g flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library ( figure 2-5 ). for more details, refer to the fusion, igloo/e and proasi c3/e macro library guide . table 2-1 ? combinatorial cell propagation delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v combinatorial cell equation parameter ?2 ?1 std. units inv y = !a t pd 0.40 0.46 0.54 ns and2 y = a b t pd 0.47 0.54 0.63 ns nand2 y = !(a b) t pd 0.47 0.54 0.63 ns or2 y = a + b t pd 0.49 0.55 0.65 ns nor2 y = !(a + b) t pd 0.49 0.55 0.65 ns xor2 y = a bt pd 0.74 0.84 0.99 ns maj3 y = maj(a, b, c) t pd 0.70 0.79 0.93 ns xor3 y = a b ct pd 0.87 1.00 1.17 ns mux2 y = a !s + b s t pd 0.51 0.58 0.68 ns and3 y = a b c t pd 0.56 0.64 0.75 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
core architecture v2.0 2-7 figure 2-5 ? sample of sequential cells figure 2-6 ? sequential timing model and waveforms dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
fusion family of mi xed-signal flash fpgas device architecture 2-8 v2.0 sequential timing characteristics table 2-2 ? register delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t clkq clock-to-q of the core register 0.55 0.63 0.74 ns t sud data setup time for the core register 0.43 0.49 0.57 ns t hd data hold time for the co re register 0.00 0.00 0.00 ns t sue enable setup time for the core register 0.45 0.52 0.61 ns t he enable hold time for the core register 0.00 0.00 0.00 ns t clr2q asynchronous clear-to-q of th e core register 0.40 0.45 0.53 ns t pre2q asynchronous preset-to-q of the core register 0.40 0.45 0.53 ns t remclr asynchronous clear removal time fo r the core register 0.00 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.22 0.25 0.30 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.22 0.25 0.30 ns t wclr asynchronous clear minimum pulse widt h for the core regi ster 0.22 0.25 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.22 0.25 0.30 ns t ckmpwh clock minimum pulse width high fo r the core regist er 0.32 0.37 0.43 ns t ckmpwl clock minimum pulse width low for the core register 0.36 0.41 0.48 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
core architecture v2.0 2-9 array coordinates during many place-and-route operations in the ac tel designer software tool, it is possible to set constraints that require array coordinates. table 2-3 is provided as a reference. the array coordinates are measured from the lower left (0, 0). they can be used in region constraints for specific logic groups/blocks, designated by a wi ldcard, and can contain co re cells, memories, and i/os. table 2-3 provides array coordinates of core cells and memory blocks. i/o and cell coordinates are used for placement constraints. two coordina te systems are needed because there is not a one-to-one correspondence between i/o cells and edge core cells. in addition, the i/o coordinate syste m changes depending on the die/pa ckage combination. it is not listed in table 2-3 . the designer chipplanner to ol provides array coordinates of all i/o locations. i/o and cell coordinates are used for placement co nstraints. however, i/o placement is easier by package pin assignment. figure 2-7 illustrates the array coordina tes of an afs600 device. fo r more information on how to use array coordinates for region/p lacement constraints, see the designer user's guide or online help (available in the softwar e) for fusion software tools. table 2-3 ? array coordinates device versatiles memory rows all min. max. bottom top min. max. x y x y (x, y) (x, y) (x, y) (x, y) afs090 3 2 98 25 none (3, 26) (0, 0) (101, 29) afs250 3 2 130 49 none (3, 50) (0, 0) (133, 53) afs600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) afs1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 129) note: the vertical i/o tile coordinates are not shown. west side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. figure 2-7 ? array coordinates for afs600 (0, 79) (197, 1) top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (169, 1) to (192, 1) memory blocks memory blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile(core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) i/o tile to analog block
fusion family of mi xed-signal flash fpgas device architecture 2-10 v2.0 routing architecture the routing structure of fusion devices is design ed to provide high perfo rmance through a flexible four-level hierarchy of routing re sources: ultra-fast local resource s; efficient long-line resources; high-speed very-long-line resources; an d the high-performance versanet networks. the ultra-fast local resources are de dicated lines that allo w the output of each versatile to connect directly to every input of the eight surrounding versatiles ( figure 2-8 ). the exception to this is that the set/clr input of a versatile configured as a d-flip-flop is driven only by the versanet global network. the efficient long-line resour ces provide routing for longer distance s and higher-fanout connections. these resour ces vary in length (spanning one, two, or four versatiles), run both vertically and horizontally, and co ver the entire fu sion device ( figure 2-9 on page 2-11 ). each versatile can drive signals onto the efficient lo ng-line resources, which can access every input of every versatile. active buffers are inserted auto matically by routing software to limit loading effects. the high-speed very-long-l ine resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length +/ ?12 versatiles in the vertical direction and length +/?16 in the horizontal direction from a given core versatile ( figure 2-10 on page 2-12 ). very long lines in fusion devices, like those in proasic3 devices, have been enhanced. this provides a significant performance boo st for long-reach signals. the high-performance versanet global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic ( figure 2-11 on page 2-13 ). these nets are typically used to distribute cl ocks, reset signals, an d other high-fanout ne ts requiring minimum skew. the versanet networks are implemented as cl ock trees, and signals can be introduced at any junction. these can be employed hierarchically , with signals accessin g every input on all versatiles. note: input to the core cell for the d-flip-flop set and reset is only available via the versanet global network connection. figure 2-8 ? ultra-fast local lines connected to the eight nearest neighbors l l l l l l inputs output ultra-fast lo c al lines ( c onne c ts a versatile to the a d ja c ent versatile, i/o b uffer, or memory b lo c k) l ll lon g lines
core architecture v2.0 2-11 figure 2-9 ? efficient long-line resources l l llll l lllll l l llll l l llll l l llll spans one versatile spans two versatiles spans four versatiles spans one versatile spans two versatiles spans four versatiles versatile
fusion family of mi xed-signal flash fpgas device architecture 2-12 v2.0 figure 2-10 ? very-long-line resources high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring 1612 block of versatiles sram
core architecture v2.0 2-13 global resources (versanets) fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has six cccs. th e west ccc also contains a pll core. in the two larger devices (afs600 and afs1500), the west and the east cccs each contain a pll. the p lls include delay lines, a phase shifter (0, 90, 180, 270), and clock mu ltipliers/dividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the versanet global network. the east and west cccs each have access to three versanet glob al lines on each side of the chip (six lines total). the cccs at the four co rners each have access to thre e quadrant global lines on each quadrant of the chip. advantages of th e versanet approach one of the architectural benefits of fusion is the set of powe rful and low-delay versanet global networks. fusion offers six chip (main) global netw orks that are distributed from the center of the fpga array ( figure 2-11 ). in addition, fusion devices have th ree regional globals (quadrant globals) in each of the four chip quadran ts. each core versatile has access to nine global network resources: three quadrant and six chip (main) global networks. there are a total of 18 global networks on the device. each of these networks contains spines an d ribs that reach all versatiles in all quadrants ( figure 2-12 on page 2-14 ). this flexible versanet global netw ork architecture allows users to map up to 180 different internal/exter nal clocks in a fusion device. de tails on the versanet networks are given in table 2-4 on page 2-14 . the flexibility of the fusion ve rsanet global network allows the designer to address several design requirements. us er applications that ar e clock-resource-intensive can easily route external or gated internal cl ocks using versanet global routing networks. designers can also drastically re duce delay penalties and minimi ze resource usage by mapping critical, high-fanout nets to the versanet global network. figure 2-11 ? overview of fusion versanet global network main (chip) global network top spine bottom spine pad ring pad ring i/o ring i/o ring chip (main) global pads global pads high-performance versanet global network global spine global ribs spine-selection tree mux quadrant global pads
fusion family of mi xed-signal flash fpgas device architecture 2-14 v2.0 figure 2-12 ? global network architecture table 2-4 ? globals/spines/rows by device afs090 afs250 afs600 afs1500 global versanets (trees)* 9 9 9 9 versanet spines/tree 4 8 12 20 total spines 36 72 108 180 versatiles in each top or bottom spine 384 768 1,152 1,920 total versatiles 2,304 6,144 13,824 38,400 note: *there are six chip (m ain) globals and three globals per quadrant. northwest quadrant global network southeast quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc
core architecture v2.0 2-15 versanet global netwo rks and spine access the fusion architecture contains a total of 18 segmented global networks that can access the versatiles, sram, and i/o tiles on the fusion devi ce. there are 6 chip (main) global networks that access the entire device and 12 quadrant networks (3 in each quadrant). each device has a total of 18 globals. these versanet global networks offer fast, low-skew routing re sources for high-fanout nets, including clock signals. in addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 180 inte rnal/external clocks (in an afs1500 device) or other high -fanout nets in fusion devices. optimal usage of these low-skew networks can result in significant improvement in design performance on fusion devices. the nine spines available in a vert ical column reside in global ne tworks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. note that there are three quadrant spines in each quadrant of the device. there are four quadrant global network regions per device ( figure 2-12 on page 2-14 ). the spines are the vertical branches of the global network tree, shown in figure 2-11 on page 2-13 . each spine in a vertical co lumn of a chip (main) global network is further divided into two equal- length spine segments: one in the top an d one in the bottom half of the die. each spine and its associated ribs cover a certain area of the fusi on device (the "scope" of the spine; see figure 2-11 on page 2-13 ). each spine is accessed by the dedicated global network mux tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or another net defined by the user ( figure 2-13 ). quadrant spines can be driven from user i/os on the north and south sides of the die, via analog i/os configured as direct digital inputs. the ability to drive spines in the quadrant global networks can have a significant effect on system perfor mance for high-fanout inputs to a design. details of the chip (main) global network spine-selection mux are presented in figure 2-13 . the spine drivers for each spine are lo cated in the middle of the die. quadrant spines are driven from a north or south ri b. access to the top and bottom ribs is from the corner ccc or from the i/os on the north and sout h sides of the device. fo r details on using spines in fusion devices, see th e actel application note using global resources in actel fusion devices . figure 2-13 ? spine-selection mux of global tree internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux
fusion family of mi xed-signal flash fpgas device architecture 2-16 v2.0 clock aggregation clock aggregation allows for mu lti-spine clock domains. a mu x tree provides the necessary flexibility to allow long lines or i/os to access do mains of one, two, or four global spines. signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also throug h local resources in the north and south ribs, allowing i/os to feed directly into the clock system. as figure 2-14 indicates, this access system is contiguous. there is no break in the middle of the chip for north and south i/o versanet access. this is different from the quadrant clocks, located in these ribs, whic h only reach the middle of the rib.refer to the using global resources in actel fusion devices application note. figure 2-14 ? clock aggregation tree architecture global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux
core architecture v2.0 2-17 global resource characteristics afs600 versanet topology clock delays are device-specific. figure 2-15 is an example of a global tree used for clock routing. the global tree presented in figure 2-15 is driven by a ccc located on the west side of the afs600 device. it is used to drive all d-flip-flops in the device. figure 2-15 ? example of global tree use in an afs600 device for clock routing central global rib versatile rows global spine ccc
fusion family of mi xed-signal flash fpgas device architecture 2-18 v2.0 versanet timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are dependent upon i/o standard, and the clock may be driven and conditioned internally by the ccc module. table 2-5 , table 2-6 , table 2-7 , and table 2-8 on page 2-19 present minimum and maximum globa l clock delays within the device minimum and maximum delays are measured with minimum and maximum lo ading, respectively. timing characteristics table 2-5 ? afs1500 global resource timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.53 1.75 1.74 1.99 2.05 2.34 ns t rckh input high delay for global cl ock 1.53 1.79 1.75 2.04 2.05 2.40 ns t rcksw maximum skew for global clock 0.26 0.29 0.34 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (singl e element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-f lops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-6 ? afs600 global resource timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global cloc k 1.27 1.49 1.44 1.70 1.69 2.00 ns t rckh input high delay for global clock 1.26 1.54 1.44 1.75 1.69 2.06 ns t rcksw maximum skew for global clock 0.27 0.31 0.36 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the de lay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (singl e element is connected to the global net). 2. value reflects maximum load. the de lay is measured on the clock pin of the farthest se quential element located in a fully loaded row (all available flip-f lops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
core architecture v2.0 2-19 table 2-7 ? afs250 global resource timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global cloc k 0.89 1.12 1.02 1.27 1.20 1.50 ns t rckh input high delay for gl obal clock 0.88 1.14 1.00 1.30 1.17 1.53 ns t rcksw maximum skew for global clock 0.26 0.30 0.35 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the de lay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (singl e element is connected to the global net). 2. value reflects maximum load. the de lay is measured on the clock pin of the farthest se quential element located in a fully loaded row (all available flip-f lops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-8 ? afs090 global resource timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global cloc k 0.84 1.07 0.96 1.21 1.13 1.43 ns t rckh input high delay for gl obal clock 0.83 1.10 0.95 1.25 1.12 1.47 ns t rcksw maximum skew for global clock 0.27 0.30 0.36 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (singl e element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the fa rthest sequential element located in a fully loaded row (all available flip-f lops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-20 v2.0 clocking resources the fusion family has a robust coll ection of clocking peripherals, as shown in the block diagram in figure 2-16 . these on-chip resources enable the creati on, manipulation, and distribution of many clock signals. the fusion integrated rc oscillator produces a 100 mhz clock source with no external components. for systems requiring more precise clock si gnals, the actel fusion family supports an on-chip crystal oscillator ci rcuit. the integrated plls in each fusion device can use the rc oscillator, crystal oscillator, or another on-chip clock sign al as a source. these plls offer a variety of capabilities to modify th e clock source (multiply, divide, synchr onize, advance, or delay). utilizing the ccc found in the popular actel proasic3 fam ily, fusion incorporates six ccc blocks. the cccs allow access to fusion global and local cloc k distribution nets, as described in the "global resources (versanets)" section on page 2-13 . figure 2-16 ? fusion clocking options clock out to fpga core through ccc glint gndosc on-chip off-chip vccosc crystal oscillator clock i/os external crystal external rc xtal clock pll / ccc gla to core clkout ngmux glc from fpga core 100 mhz rc oscillator or xtal1 xtal2
clocking resources v2.0 2-21 rc oscillator the rc oscillator is an on-chip free-running clock source generating a 100 mhz clock. it can be used as a source clock for both on-chip and off-chip resources. when used in conjunction with the fusion pll and ccc circuits, the rc oscillator clock source can be used to generate clocks of varying frequency and phase. the fusion rc oscillator is very accurate at 1% over commercial and industrial temperature ranges. it is an automated clock, requiring no se tup or configuration by the user. it requires only that the power and gndosc pins be connected; no external components are required. the rc oscillator can be used to drive eith er a pll or another internal signal. rc oscillator characteristics table 2-9 ? electrical characteristics of rc oscillator parameter description condi tions min. typ. max. units f rc operating frequency 100 mhz accuracy temperature: 0c to 85c voltage: 3.3 v 5% 1% temperature: ?40c to 125c voltage: 3.3 v 5% 3% output jitter peri od jitter (at 5 k cycles) 100 ps cycle?cycle jitter (at 5 k cycles) 100 ps period jitter (at 5 k cycles) with 1 khz / 300 mv peak-to-peak noise on power supply 150 ps cycle?cycle jitter (at 5 k cycles) with 1 khz / 300 mv peak-to-peak no ise on power supply 150 ps output duty cycle 50 % i dynrc operating current 1 ma
fusion family of mi xed-signal flash fpgas device architecture 2-22 v2.0 crystal oscillator the crystal oscillator (xtlosc) is source that generates the clock from an external crystal. the output of xtlosc clkout signal can be sele cted as an input to the pll. refer to "clock conditioning circuits" section for more details. the xtlosc can operate in normal operations and standby mode (rtc is running and 1.5 v is not present). in normal operation, the internal fpga_en signal is '1' as long as 1.5 v is present for v cc . as such, the internal enable signal, xtl_en, for crystal oscillator is enabled since fpga_en is asserted. the xtl_mode has the option of using mode or rtc_mode, depending on selmode. during standby, 1.5 v is not avai lable, as such, and fpga_en is '0'. selmode must be asserted in order for xtl_en to be enabled; hence xtl_mode relies on rtc_mode. selmode and rtc_mode must be connected to rtcxtlsel and rtcxtlmode fr om the ab respectively for correct operation during standby (refer to the "real-time counter syste m" section on page 2-34 for a detailed description). the crystal oscillator can be conf igured in one of four modes: ? rc network, 32 khz to 4 mhz ? low gain, 32 to 200 khz ? medium gain, 0.20 to 2.0 mhz ? high gain, 2.0 to 20.0 mhz in rc network mode, the xtal1 pin is connected to an rc circuit, as shown in figure 2-17 . the xtal2 pin should be left floating. the rc value can be chosen based on figure 2-18 for any desired frequency between 32 khz and 4 mh z. the rc network mode can also accommodate an external clock source on xtal1 in stead of an rc circuit. in low gain, medium gain, and high gain, an exte rnal crystal component or ceramic resonator can be added onto xtal1 and xtal2, as shown in figure 2-17 . note: *internal signal?does not exist in macro. figure 2-17 ? xtlosc macro xtlo sc c lkout xtl 0 1 mode[1:0] rt c _mode[1:0] s elmode fp g a_en * xtl_en * xtl_mode *
clocking resources v2.0 2-23 figure 2-18 ? crystal oscillator: rc time consta nt values vs. frequency (typical) 0.0 1.00e-0.7 1.00e-0.6 1.00e-0.5 1.00e-0.4 1.00e-0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 rc time constant (sec) frequency (mhz) rc time constant values vs. frequency table 2-10 ? xtlosc signals descriptions signal name width direction function xtl_en* 1 enables the crys tal. active high. xtl_mode* 2 settings for the crysta l clock for different frequency. value modes frequency range b'00 rc network 32 khz to 4 mhz b'01 low gain 32 to 200 khz b'10 medium gain 0.20 to 2.0 mhz b'11 high gain 2.0 to 20.0 mhz selmode 1 in selects the source of xtl_mode and also enables the xtl_en. connect from rtcxtlsel from ab. 0 for normal operation or sleep mode, xtl_en depends on fpga_en, xtl_mode depends on mode 1 for standby mode, xtl_e n is enabled, xtl_mode depends on rtc_mode rtc_mode[1:0] 2 in settings for the crystal clock for different frequency ranges. xtl_mode uses rtc_mode when selmode is '1'. mode[1:0] 2 in settings for the crystal cl ock for different frequency ranges. xtl_mode uses mode when selmode is '0'. in standby, mode inputs will be 0's. fpga_en* 1 in 0 when 1.5 v is not present for v cc 1 when 1.5 v is present for v cc xtl 1 in crystal clock source clkout 1 out crystal clock output note: *internal signal?does not exist in macro.
fusion family of mi xed-signal flash fpgas device architecture 2-24 v2.0 clock conditioning circuits in fusion devices, the cccs are used to impl ement frequency division, frequency multiplication, phase shifting, and delay operations. the cccs are available in six chip locations?each of the four chip corners and the middle of the east and west chip sides. each ccc can implement up to three independent global buffers (with or without programmable delay), or a pll function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximu m of three global ou tputs for a given ccc. a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb, and clkc- glc) of a given ccc. a pll macro uses the clka ccc input to drive its re ference clock. it uses the gla and, optionally, the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) glob al output cannot be reused if the yb (or yc) output is used ( figure 2-19 ). refer to the "pll macro" section on page 2-30 for more information. each global buffer, as well as the pll reference clock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core the ccc block is fully configurab le, either via flash configurat ion bits set in the programming bitstream or through an asynchronous interface . this asynchronous interface is dynamically accessible from inside the fusion device to permit changes of parameters (such as divide ratios) during device operation. to incr ease the versatility and flexibility of the clock conditioning system, the ccc configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicate d shift register during normal devi ce operation. this latter mode allows the user to dynamically reconfigure the ccc without the need fo r core programming. the shift register is accessed through a si mple serial interface. refer to the ujtag applications in actel?s low-power flash devices handbook chapter and the "ccc and pll characteristics" section on page 2-31 for more information.
clocking resources v2.0 2-25 notes: 1. visit the actel website for future application note s concerning dynamic pll reco nfiguration. refer to the "pll macro" section on page 2-30 for signal descriptions. 2. many specific inbuf macros support the wide variety of single-ended and differential i/ o standards for the fusion family. 3. refer to the fusion, igloo/e, and proasi c3/e macro li brary guide for more information. figure 2-19 ? fusion ccc options: global buffers with the pll macro table 2-11 ? available selections of i/ o standards within clkbuf and clkbuf_lvds/lvpecl macros clkbuf macros clkbuf_lvcmos5 clkbuf_lvcmos33 1 clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_lvds 2 clkbuf_lvpecl notes: 1. this is the default macro. fo r more details, refer to the fusion, igloo/e and proasic3/e macro library guide . 2. the blvds and m-lvds standards are supported with clkbuf_lvds. padn padp y pad y input lvds/lvpecl macro inbuf 2 macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) clock source clock conditioning output oadivhalf oadiv[4:0] oamux[2:0] dlygla[4:0] obdiv[4:0] obmux[2:0] dlyyb[4:0] dlyglb[4:0] ocdiv[4:0] ocmux[2:0] dlyyc[4:0] dlyglc[4:0] findiv[6:0] fbdiv[6:0] fbdly[4:0] fbsel[1:0] xdlysel vcosel[2:0] clka extfb powerdown oadivrst gla lock glb yb glc yc
fusion family of mi xed-signal flash fpgas device architecture 2-26 v2.0 global buffers with no programmable delays the clkbuf and clkbuf_lvpecl/lvds macros are composite macros that include an i/o macro driving a global buffer, hardwired together ( figure 2-20 ). the clkint macro provides a global buffer function driven by the fpga core. the clkbuf, clkbuf_lvpecl/lvds, and clkint macr os are pass-through clock sources and do not use the pll or provide any pr ogrammable delay functionality. many specific clkbuf macros support the wide variety of single-ended and differential i/o standards supported by fusion devices. the av ailable clkbuf macros are described in the fusion, igloo/e and proasic3/e macro library guide . figure 2-20 ? global buffers with no programmable delay clkbuf_lvds/lvpecl macro padn padp yy a pad y clkint macro clkbuf macro gla or glb or glc clock source clock conditioning output none
clocking resources v2.0 2-27 global buffers with programmable delay the clkdly macro is a pass-through clock source th at does not use the pll, but provides the ability to delay the clock input using a programmable delay ( figure 2-21 ). the clkdly macro takes the selected clock input and adds a us er-defined delay elemen t. this macro generates an output clock phase shift from the input clock. the clkdly macro can be driven by an inbuf ma cro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. many specific inbuf macros support the wide vari ety of single-ended and differential i/o standards supported by the fusion family. the avai lable inbuf macros are described in the fusion, igloo/e and proasic3/e macro library guide. the clkdly macro can be driven directly from the fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga regular routing fabric. in this case, users must instantiate a sp ecial macro, pllint, to differentiate from the hardwired i/o connection described earlier. the visual clkdly configuration in the smartgen part of the libero ide and designer tools allows the user to select the desired amount of delay and configures the delay elements appropriately. smartgen also allows the user to select the input clock source. smartgen will automatically instantiate the special macro, pllint, when needed. figure 2-21 ? fusion ccc options: global buffers with programmable delay padn padp y pad y input lvds/lvpecl macro inbuf* macro gla or glb or glc clock source clock conditioning output clk dlygl[4:0] gl
fusion family of mi xed-signal flash fpgas device architecture 2-28 v2.0 global input selections each global buffer, as well as the pll reference clock, can be driven from one of the following ( figure 2-22 ): ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core notes: 3. represents the global input pins. globals have direct access to the clock conditioning block and are not routed via the fpga fa bric. refer to the "user i/o naming conventi on" section on page 2-159 for more information. 4. instantiate the routed cloc k source input as follows: a) connect the output of a logic element to the clock input of the pll, clkdly, or clkint macro. b) do not place a clock source i/ o (inbuf or inbuf_lvpecl/lvds) in a relevant global pin location. 5. lvds-based clock sources are available in th e east and west banks on all fusion devices. figure 2-22 ? clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint + + source for ccc (clka or clkb or clkc) each shaded box represents an input buffer called out by the appropriate name: inbuf or inbuf_lvds/lvpecl. to core routed clock (from fpga core) 2 sample pin names gaa0 1 gaa1 1 gaa2 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source.
clocking resources v2.0 2-29 ccc physical implementation the ccc circuit is compos ed of the following ( figure 2-23 ): ? pll core ? 3 phase selectors ? 6 programmable delays and 1 fixed delay ? 5 programmable frequency dividers that provide frequency multiplication/division (not shown in figure 2-23 because they are automatically configured based on the user's required frequencies) ? 1 dynamic shift register that provides ccc dynamic reconfiguration capability (not shown) ccc programming the ccc block is fully configurable. it is configur ed via static flash config uration bits in the array, set by the user in the programming bitstream, or configured through an asynchronous dedicated shift register, dynamically access ible from inside the fusion de vice. the dedicated shift register permits changes of parameters such as pll divide ra tios and delays during device operation. this latter mode allows the user to dynamically reconfigure the pll without the need for core programming. the register file is access ed through a simple serial interface. note: clock divider and multiplier blocks are not shown in this figure or in smartgen. they are automatically configured based on the user's required frequencies. figure 2-23 ? pll block pll core phase select phase select phase select gl a clka glb yb glc yc fixed delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 four-phase output
fusion family of mi xed-signal flash fpgas device architecture 2-30 v2.0 pll macro the pll functionality of the clock conditioning bloc k is supported by the p ll macro. note that the pll macro reference clock uses the clka input of the ccc block, which is only accessible from the global a[2:0] pac kage pins. refer to figure 2-22 on page 2-28 for more information. the pll macro provides five deri ved clocks (three independent) from a single reference clock. the pll feedback loop can be driven either internally or externally. the pll ma cro also provides power- down input and lock output signals. during power-up, powerdown should be asserted low until v cc is up. see figure 2-19 on page 2-25 for more information. inputs: ? clka: selected clock input ? powerdown (active low): disables plls. the de fault state is power-down on (active low). outputs: ? lock (active high): indicates that pll outp ut has locked on the input reference signal ? gla, glb, glc: outputs to respective global networks ? yb, yc: allows output from the ccc to be routed back to the fpga core as previously described, the pll allows up to five flexible and independently configurable clock outputs. figure 2-23 on page 2-29 illustrates the various clock ou tput options and delay elements. as illustrated, the pll supports three distinct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b and c global networks, respectively, and/or routed to the device core (yb and yc). there are five delay elements to support phase con trol on all five outputs (gla, glb, glc, yb, and yc). there is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock. the pll macro reference clock can be driven by an inbuf macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. the pll macro reference clock can be driven directly from the fpga core. the pll macro reference clock can also be driven from an i/o routed through the fpga regular routing fabric. in this case, use rs must instantiate a special macro, pllint, to differentiate it from the hardwired i/o connec tion descri bed earlier. the visual pll configuration in smartgen, available with the libero ide and designer tools, will derive the necessary internal divider ratios based on the input frequ ency and desired output frequencies selected by the user. smartgen allows the user to sele ct the various delays and phase shift values necessary to adjust the phases be tween the reference clock (clka) and the derived clocks (gla, glb, glc, yb, and yc). smartgen also allows the user to select where the input clock is coming from. smartgen automatically instantiates the spec ial macro, pllint, when needed.
clocking resources v2.0 2-31 ccc and pll characteristics timing characteristics table 2-12 ? fusion ccc/pll specification parameter min. typ. max. unit clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1, 2 160 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-p eak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 1.00% 1.00% 24 mhz to 100 mhz 1.50% 1.50% 100 mhz to 250 mhz 2.25% 2.25% 250 mhz to 350 mhz 3.50% 3.50% acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 3 lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 0.6 5.56 ns delay range in block: programmable delay 2 1, 2 0.025 5.56 ns delay range in block: fixed delay 1, 2 2.2 ns notes: 1. this delay is a function of voltage and temperature. see table 3-7 on page 3-9 for deratings. 2. t j = 25c, v cc = 1.5 v 3. tracking jitter is defined as the va riation in clock edge position of p ll outputs with reference to pll input clock edge. tracking jitter does not measure the variat ion in pll output period, which is covered by period jitter parameter.
fusion family of mi xed-signal flash fpgas device architecture 2-32 v2.0 no-glitch mux (ngmux) positioned downstream fro m the pll/ccc blocks, the ngmux provides a special switching sequence between two asynchronous clock do mains that prevents generating any unwanted narrow clock pulses. the ngmux is used to switch the so urce of a global be tween three different clock sources. allowable inputs are either two pll/ccc outputs or a pll/ccc output and a regular net, as shown in figure 2-24 . the glmuxcfg[1:0] configuration bits determine the source of the clk inputs (i.e., internal signal or glc). these are set by smar tgen during design but can also be changed by dynamically reconfiguring the pll. the glmuxsel[1:0] bits control which clock source is passed through the ngmux to the global network (gl). see table 2-13 . figure 2-24 ? ngmux table 2-13 ? ngmux configuration and selection table glmuxcfg[1:0] glmuxsel[1:0] selected input signal mux type 00 x 0 gla 2-to-1 glmux x1glc 01 x 0 gla 2-to-1 glmux x 1 glint crystal oscillator rc oscillator w i/o ring ccc/pll clock i/os from fpga core pll/ ccc glint gla glc ngmux glmuxcfg[1:0] pwr up glmuxsel[1:0] gl to clock rib driver
clocking resources v2.0 2-33 the ngmux macro is simplified to show the two clock options that have been selected by the glmuxcfg[1:0] bits. figure 2-25 illustrates the ngmux macro. during design, the two clock sources are connected to clk0 an d clk1 and are controlled by gl muxsel[1:0] to determine which signal is to be passed through the mux. the sequence of switching between two clock sources (from clk0 to clk1) is as follows ( figure 2-26 ): ? glmuxsel[1:0] transitions to initiate a switch. ? gl drives one last complete clk0 positive pulse (i.e., one rising edge fo llowed by one falling edge). ? from that point, gl stays low until th e second rising edge of clk1 occurs. ? at the second clk1 rising ed ge, gl will begin to continuously deliver the clk1 signal. ? minimum t sw = 0.05 ns at 25c (typical conditions) for examples of ngmux operation, refer to the fusion handbook . figure 2-25 ? ngmux macro figure 2-26 ? ngmux waveform clk0 clk1 gl glmuxsel[1:0] clk0 clk1 glmuxsel[1:0] gl t sw
fusion family of mi xed-signal flash fpgas device architecture 2-34 v2.0 real-time counter system the rtc system enables fusion devi ces to support standby and sleep modes of operation to reduce power consumption in many applications. ? sleep mode, typical 10 a ? standby mode (rtc running) , typical 3 ma with 20 mhz the rtc system is composed of five cores: ? rtc sub-block inside analog block (ab) ? voltage regulator and power system monitor (vrpsm) ? crystal oscillator (xtlosc); refer to the "crystal oscillator" section in fusion clock resources for more detail. ? crystal clock; does not require instantiation in rtl ? 1.5 v voltage regulator; does not require instantiation in rtl all cores are powered by 3.3 v supplies, so the rtc system is operational without a 1.5 v supply during standby mode. figure 2-27 shows their connection. note: *signals are hardwired internally and do not exist in the macro core. figure 2-27 ? real-time counter system (not all the signals are shown for the ab macro) vrpu ptba s e * ptem * pub vrinit s tate rt c p s mmat c h fp g a g ood pu c ore vren * vren * vrp s m 1.5 volta g e re g ulator rt c xtl s el rt c mat c h rt c p s mmat c h xtlo sc real-time c ounter xtal1 xtal2 c lkout rt c _mode[1:0] s elmode rt cc lk external pass transistor 2n2222 3.3 v power-up/-down to gg le c ontrol s wit c h 1.5 v tr s t * external pin internal pin c an be route to pll rt c xtlmode[1:0] c ores d o not re q uire any rtl instantiation c ores re q uire rtl instantiation s u b - b lo c k in c ores d oes not re q uire a dd itional rtl instantiation xtl xtl * c rystal c lo c k mode[1:0] fp g a_en * ab
real-time counter system v2.0 2-35 modes of operation standby mode standby mode allows periodic power-up and power-down of the fpga fabric. in standby mode, the real-time counter and crystal block are on. the fpga is not powered by disabling the 1.5 v voltage regulator. the 1.5 v voltage regulator can be enab led when the preset count is matched. refer to the "real-time counter (part of ab macro)" section for details. to enter standby mode, the rtc must be first configured and enable d. then vrpsm is shut off by deasserting the vrpu signal. the 1.5 v voltage regulator is then disabled, and shuts off the 1.5 v output. sleep mode in sleep mode, the real-time coun ter and crystal blocks are off. the 1.5 v voltage regulator inside the vrpsm can only be enabled by the pub or trst pin. refer to the "voltage regulator and power system monitor (vrpsm)" section on page 2-38 for details on power-up and power-down of the 1.5 v voltage regulator. standby and sleep mode circu it implementation for extra power savings, v jtag and v pp should be at the same voltage as v cc , floated or ground, during standby an d sleep modes. note that when v jtag is not powered, the 1.5 v voltage regulator cannot be enabled through trst. v pp and v jtag can control through an external switch. actel re commends adg839, adg849, or adg841 as possible switches. figure 2-28 shows the implementati on for controlling v pp . the in signal of the switch can be connected to ptbase of the fusion device. v jtag can be controlled in same manner. real-time counter (part of ab macro) the rtc is a 40-bit loadable counter and used as the primary timekeeping element ( figure 2-29 ). the clock source, rtcclk, must come from the clko ut signal of the crystal oscillator. the rtc can be configured to reset itself wh en a count value reaches the match value set in the match register. figure 2-28 ? implementation to control v pp ptba s e ptem external pass transistor 2n2222 3.3 v 1.5 v vpp pin of fusion vpp s upply fusion ad g 841 s in
fusion family of mi xed-signal flash fpgas device architecture 2-36 v2.0 the rtc is part of the analog block (ab) macro. th e rtc is configured by the analog configuration mux (acm). each address contains one byte of data. the circuitry in the rtc is powered by v cc33a , so the rtc can be used in standby mode when the 1.5 v supply is not present. the 40-bit counter can be preloaded with an in itial value as a startin g point by the counter register. the count from th e 40-bit counter can be read through the same set of address space. the count comes from a read-hold register to avoid data changing during read. when the counter value equals the match register value, all match bits register values will be 0xffffffffff. the rtcmatch and rtcpsmmatch sign als will assert. the 40 -bit counter can be configured to automatically reset to 0x0000000 000 when the counter va lue equals the match register value. the automatic re set does not apply if the match register value is 0x0000000000. the rtcclk has a prescaler to divide the clock by 128 before it is us ed for the 40-bit counter. below is an example of how to calculate the off time. figure 2-29 ? rtc block diagram table 2-14 ? rtc signal description signal name width direction function rtcclk 1 in must come from clkout of xtlosc. rtcxtlmode[1:0] 2 out contro lled by xt_mode in ctrl_stat. signal must connect to the rtc_mode signal in xtlosc, as shown in figure 2-27 . rtcxtlsel 1 out controlled by xtal_en from ctrl_stat regi ster. signal must connect to rtc_mode signal in xtlosc in figure 2-27 . rtcmatch 1 out match signal for fpga 0 ? counter value does not equal the match register value. 1 ? counter value equals the match register value. rtcpsmmatch 1 out same signal as rt cmatch. signal must connect to rtcpsmmatch in vrpsm, as shown in figure 2-27 . xt_mo d e[1:0] rt c mat c h rt c p s mmat c h rt cc lk a c m re g isters 1.5 v to 3.3 v level s hifter c ontrol s tatus 40-bit c ounter mat c h re g mat c hbits re g c ounter re g c ounter rea d -hol d re g real-time c ounter c rystal pres c aler f rt cc lk divi d e b y 128 xtal_en rt c xtl s el rt c xtlmode[1:0]
real-time counter system v2.0 2-37 example: calculation for match count to put the fusion device on standby for one ho ur using an external crystal of 32.768 khz: the period of the crystal oscillator is t crystal : t crystal = 1 / 32.768 khz = 30.518 s the period of the counter is t counter : t counter = 30.518 us x 128 = 3.90625 ms the match count for 1 hour is tmatch: tmatch / t counter = (1 hr x 60 min/hr x 60 sec/min) / 3.90625 ms = 921600 or 0xe1000 using a 32.768 khz crystal, the maximum standby time of the 40-bit counter is 4,294,967,296 seconds, which is 136 years. table 2-15 ? memory map for rtc in acm register and description acmaddr register name desc ription use default value 0x40 counter0 counter bits 7:0 use d to preload the counter to a specified start point. 0x00 0x41 counter1 counter bits 15:8 0x00 0x42 counter2 counter bits 23:16 0x00 0x43 counter3 counter bits 31:24 0x00 0x44 counter4 counter bits 39:32 0x00 0x48 matchreg0 match register bits 7:0 the rtc comparison bits 0x00 0x49 matchreg1 match register bits 15:8 0x00 0x4a matchreg2 match register bits 23:16 0x00 0x4b matchreg3 match register bits 31:24 0x00 0x4c matchreg4 match register bits 39:32 0x00 0x50 matchbit0 individual match bits 7:0 the output of the xnor gates 0 ? not matched 1 ? matched 0x00 0x51 matchbit1 individual match bits 15:8 0x00 0x52 matchbit2 individual match bits 23:16 0x00 0x53 matchbit3 individual match bits 31:24 0x00 0x54 matchbit4 individual match bits 29:32 0x00 0x58 ctrl_stat control (write/read) / status (read only) register bits refer to table 2-16 on page 2-38 for details. 0x00
fusion family of mi xed-signal flash fpgas device architecture 2-38 v2.0 voltage regulator and powe r system monitor (vrpsm) the vrpsm macro controls the power-up state of the fpga. the power-up bar (pub) pin can turn on the voltage regulator when se t to 0. trst can enable the vo ltage regulator when deasserted, allowing the fpga to power-up wh en user want access to jtag ports. the inputs vrinitstate and rtcpsmmatch come from the flash bits an d rtc, and can also power up the fpga. table 2-16 ? rtc control/status register bit name description default value 7 rtc_rst rtc reset 1 ? resets the rtc 0 ? deassert reset on after two acm_clk cycle. 6 cntr_en counter enable 1 ? enables the counter; rtc_rst must be deasserted as well. first counter increments after 64 rtcc lk positive edges. 0 ? disables the crystal prescaler but does not reset the counter value. counter value can only be update d when the counter is disabled. 0 5 vr_en_mat voltage regulator enable on match 1 ? enables rtcmatch and rtcpsmmatch to output 1 when the counter value equals the match regi ster value. this enables the 1.5 v voltage regulator when rtcpsmmatc h connects to the rtcpsmmatch signal in vrpsm. 0 ? rtcmatch and rtcpsmmatch output 0 at all times. 0 4:3 xt_mode[1:0] crystal mode controls rtcxtlmode[1:0]. connects to rtc_mode sign al in xtlosc. xtl_mode uses this value wh en xtal_en is 1. see the "crystal oscillator" section on page 2-22 for mode configuration. 00 2 rst_cnt_omat reset counter on match 1 ? enables the sync clear of the co unter when the counter value equals the match register value. the counter clears on th e rising edge of the clock. if all the match registers ar e set to 0, the clear is disabled. 0 ? counter increments indefinitely 0 1 rstb_cnt counter reset, active low 0 - resets the 40-bit counter value 0 0 xtal_en crystal enable controls rtcxtlsel. connects to selmode signal in xtlosc. 0 ? xtlosc enables control by fp ga_en; xt_mode is not used. sleep mode requires this bit to equal 0. 1 ? enables xtlosc, xtl_m ode control by xt_mode standby mode requires this bit to be set to 1. see the "crystal oscillator" section on page 2-22 for further details on selmode configuration. 0
real-time counter system v2.0 2-39 note: *signals are hardwired internally and do not exist in the macro core. figure 2-30 ? vrpsm macro table 2-17 ? vrpsm signal descriptions signal name width direction function vrpu 1 in voltage regulator power-up 0 ? voltage regulator disabled. pub must be floated or pulled up, and the trst pin must be grounded to disable the voltage regulator. 1 ? voltage regulator enabled vrinitstate 1 in voltage regulator initial state defines the voltage regulator statu s upon power-up of the 3.3 v. the signal is configured by actel libero ? integrated design environment (ide) when the vrpsm macro is generated. tie off to 1 ? voltage regulator enables when 3.3 v is powered. tie off to 0 ? voltage regulator disables when 3.3 v is powered. rtcpsmmatch 1 in rtc power system management match connect from rtcpsmatch signal from rtc in ab 0 transition to 1 turns on the voltage regulator pub 1 in external pin, built-in weak pull-up power-up bar 0 ? enables voltage regulator at all times trst* 1 in external pin, jtag test reset 1 ? enables voltage regulator at all times fpgagood 1 out indicator that the fpga is powered and functional no need to connect if it is not used. 1 ? indicates that the fpga is powered up and functional. 0 ? not possible to read by fpga since it has already powered off. pucore 1 out power-up core inverted signal of pub. no need to connect if it is not used. vren* 1 out voltage regulator enable connected to 1.5 v voltage regulato r in fusion device internally. 0 ? voltage regulator disables 1 ? voltage regulator enables note: *signals are hardwired internally a nd do not exist in the macro core. vrpu pub vrinit s tate rt c p s mmat c h fp g a g ood pu c ore vren * vrp s m tr s t *
fusion family of mi xed-signal flash fpgas device architecture 2-40 v2.0 when trst is 1 or pub is 0, the 1.5 v voltage re gulator is always on, putti ng the fusion device in normal operation at all times. th erefore, when the jtag port is no t in reset, the fusion device cannot enter sleep mode or standby mode. to enter standby mode, the fusion device must fi rst power-up into normal operation. the rtc is enabled through the rtc control/sta tus register described in the "real-time counter (part of ab macro)" section on page 2-35 . a match value corre sponding to the wake-up time is loaded into the match register. the 1.5 v voltage regulator is disabled by setting vrpu to 0 to allow the fusion device to enter standby mode, when the 1. 5 v supply is off but the rtc remains on. 1.5 v voltage regulator the 1.5 v voltage regulator uses an external pass transistor to gene rate 1.5 v from a 3.3 v supply. the base of the pass transistor is tied to ptbase, the collector is ti ed to 3.3 v, and an emitter is tied to ptbase and the 1.5 v supp lies of the fusion device. figure 2-27 on page 2-34 shows the hook-up of the 1.5 v voltage regulator to an external pass transistor. actel recommends using a pn2222a or 2n2222a trans istor. the gain of such a transistor is approximately 25, with a maxi mum base current of 20 ma. the maximum current that can be supported is 0.5 a. transistors with different gain can also be used for different current requirements. note: * to enter and exit standby mode without any extern al stimulus on pub or trst, the vr_en_mat in the ctrl_stat register must also be set to 1, so that rtcpsmmatch will assert when a match occurs; hence the device exits standby mode. figure 2-31 ? state diagram for all different power modes normal operation 3.3 v on, vren ena b le s tan db y mo d e 3.3 v on, rt c ena b le d vren disa b le d off s tate 3.3 v off, pub pull-up, tr s t pull-down, vren disa b le d vrpu = 0 an d pub = 1 an d tr s t = 0 pub = 0 or tr s t = 1 vrpu = 0 an d pub = 1 an d tr s t = 0 an d * rt c : c trl_ s tat: xtal_en = 1 * rt c p s mmat c h = 1 or pub = 0 or tr s t = 1 s leep mo d e 3.3 v on, vren disa b le d 3.3 v on, 1.5 v on (vr on) 3.3 v off 3.3 v on 3.3 v power s upply on/off vinit s tate = 0 an d pub = 1 an d tr s t = 0 vrinit s tate = 1 or pub = 0 or tr s t = 1
real-time counter system v2.0 2-41 table 2-18 ? electrical characteristics v cc33a = 3.3 v symbol parameter condition min typical max units v out output voltage tj = 25oc 1.425 1.5 1.575 v i cc33a operation current tj = 25oc i load = 1 ma i load = 100 ma i load = 0.5 a 11 11 30 ma ma ma vout load regulation tj = 25oc i load = 1ma to 0.5a 90 mv vout line regulation tj = 25oc vcc33a = 2.97 v to 3.63 v i load = 1 ma vcc33a = 2.97 v to 3.63 v i load = 100 ma vcc33a = 2.97 v to 3.63 v i load = 500 ma 10.6 12.1 10.6 mv/v mv/v mv/v dropout voltage* tj = 25oc i load = 1 ma i load = 100 ma i load = 0.5 a 0.63 0.84 1.35 v v v i ptbase ptbase current tj = 25oc i load = 1 ma i load = 100 ma i load = 0.5 a 48 736 12 20 a a ma note: *data collected with 2n2222a.
fusion family of mi xed-signal flash fpgas device architecture 2-42 v2.0 embedded memories fusion devices include four type s of embedded memory: flash bl ock, flashrom, sram, and fifo. flash memory block fusion is the first fpga that offers a flash memory block (fb). each fb block stores 2 mbits of data. the flash memory block ma cro is illustrated in figure 2-32 . the port pin name and descriptions are detailed on table 2-19 on page 2-43 . all flash memory block signals are active high, except for clk and active low reset. al l flash memory operations are synchr onous to the risi ng edge of clk. figure 2-32 ? flash memory block addr[17:0] wd[31:0] program clk reset rd[31:0] busy status[1:0] unprotectpage discardpage overwriteprotect pagelossprotect datawidth[1:0] ren wen erasepage sparepage auxblock readnext overwritepage pagestatus pipe lockrequest
embedded memories v2.0 2-43 flash memory block pin names table 2-19 ? flash memory block pin names interface name width d irection description addr[17:0] 18 in byte offset into the fb. byte-based address. auxblock 1 in when asserted, the page addr essed is used to access the auxiliary block within that page. busy 1 out when asserted, indicates that the fb is performing an operation. clk 1 in user interface clock. all operat ions and status are synchronous to the rising edge of this clock. datawidth[1:0] 2 in data width 00 = 1 byte in rd/wd[7:0] 01 = 2 bytes in rd/wd[15:0] 1x = 4 bytes in rd/wd[31:0] discardpage 1 in when asserted, the contents of the page buffer are discarded so that a new page write can be started. erasepage 1 in when asserted, the address page is to be programmed with all zeros. erasepage must transition synchr onously with the rising edge of clk. lockrequest 1 in when asserted, indicate s to the jtag controller that the fpga interface is accessing the fb. overwritepage 1 in when asserted, the page addressed is overwritten with the contents of the page buffer if the page is writable. overwriteprotect 1 in when asserted, all progra m operations will set the overwrite protect bit of the page being programmed. pagestatus 1 in when asserted with ren, initiates a read page status operation. pagelossprotect 1 in when asserted, a modifi ed page buffer must be programmed or discarded before accessing a new page. pipe 1 in adds a pipeline stage to th e output for operation above 50 mhz. program 1 in when asserted, writes the co ntents of the page buffer into the fb page addressed. rd[31:0] 32 out read data; data will be va lid from the first non-busy cycle (busy = 0) after ren has been asserted. readnext 1 in when asserted with ren, initiates a read-next operation. ren 1 in when asserted, initiates a read operation. reset 1 in when asserted, resets the state of the fb (active low). sparepage 1 in when asserted, the sector addr essed is used to access the spare page within that sector.
fusion family of mi xed-signal flash fpgas device architecture 2-44 v2.0 all flash memory block in put signals are active high, except for reset. status[1:0] 2 out status of the last operation completed: 00: successful completion 01: read-/unprotect-pa ge: single error dete cted and corrected write: operation addresse d a write-protected page erase-page: protection violation program: page buffer is unmodified protection violation 10: read-/unprotect-page: tw o or more errors detected 11: write: attempt to write to another page before programming current page erase-page/program: page write count has exceeded the 10-year retention threshold unprotectpage 1 in when asserted, the page ad dressed is copied into the page buffer and the page buffer is made writable. wd[31:0] 32 in write data wen 1in when asserted, stores wd in the page buffer. table 2-19 ? flash memory block pin names (continued) interface name width d irection description
embedded memories v2.0 2-45 flash memory block diagram a simplified diagram of the flash memory block is shown in figure 2-33 . the logic consists of th e following sub-blocks: ? flash array contains all stored data. the flash array contains 64 sectors, and each sector contains 33 pages of data. ? page buffer a page-wide volatile register. a page cont ains 8 blocks of data and an aux block. ? block buffer contains the contents of the last block ac cessed. a block contains 128 data bits. ? ecc logic the fb stores error correction information with each block to perf orm single-bit error correction and double-bit error detection on all data blocks. figure 2-33 ? flash memory block diagram adddr[17:0] datawidth[1:0] ren readnext pagestatus wen erasepage program sparepage auxblock unprotectpage overwritepage discardpage overwriteprotect pagelossprotect pipe lockrequest clk reset status[1:0] busy control logic output mux block buffer (128 bits) ecc logic flash array = 64 sectors rd[31:0] wd[31 :0] page buffer = 8 blocks plus aux block
fusion family of mi xed-signal flash fpgas device architecture 2-46 v2.0 flash memory bl ock addressing figure 2-34 shows a graphical representati on of the flash memory block. each fb is partitioned into sector s, pages, blocks, and bytes. ther e are 64 sectors in an fb, and each sector contains 32 pages and 1 sp are page. each page contains 8 data blocks and 1 auxiliary block. each data block contains 16 bytes of user data, and the auxiliary block contains 4 bytes of user data. addressing for the fb is shown in table 2-20 . when the spare page of a sector is addresse d (sparepage active), addr[11:7] are ignored. when the auxiliary block is addressed (auxblock active), addr[6:2] are ignored. note: the spare page of sector 0 is unavailable for any user data. writes to this page will return an error, and reads will return all zeroes. figure 2-34 ? flash memory block organization byte 0 byte 1 byte 2 byte 3 byte 14 byte 15 block organization user data (32 bits) 140 block 0 1234567 aux block . . . . . . . . sector 0 sector 1 sector n . . . . 33 pages pag e 0 pag e 1 pag e 2 pag e 3 pag e 31 spare pag e 1190 notes: 1 block = 128 bits 1 page = 8 blocks plus the aux block 1 sector = 33 pages 1 flash array = 64 sectors table 2-20 ? fb address bit allocation addr[17:0] 17121176430 sector page block byte
embedded memories v2.0 2-47 data operations are performed in widths of 1 to 4 bytes. a write to a location in a page that is not already in the page buffer will cause the page to be read from the fb array and stored in the page buffer. the block that was addressed during the wr ite will be put into the block buffer, and the data written by wd will overwrite the data in th e block buffer. after the data is written to the block buffer, the block buffer is then written to the page buffer to keep both buffers in sync. subsequent writes to the same block will overwrit e the block buffer and the page buffer. a write to another block in the page will cause the addressed block to be loaded from the page buffer, and the write will be performed as described previously. the data width can be selected dynamically via the datawidth input bus. the truth table for the data width settings is detailed in table 2-21 . the minimum resolvable addr ess is one 8-bit byte. for data widths greater than 8 bits, the co rresponding address bi ts are ignored?when datawidth = 0 (2 bytes), addr[0] is ignored, an d when datawidth = '10' or '11' (4 bytes), addr[1:0] are ignored. data pins are lsb-oriente d and unused wd data pins must be grounded. flash memory block protection page loss protection when the pagelossprotect pin is set to logic 1, it prevents writes to any page other than the current page in the page buffer until the page is either discarded or programmed. a write to another page while the current page is pa ge loss protected will return a status of '11'. overwrite protection any page that is overwrite protec ted will result in the status being set to '01' when an attempt is made to either write, program, or erase it. to se t the overwrite protection state for a page, set the overwriteprotect pin when a program operation is undertaken. to clear the overwrite protect state for a given page, an unprotect page operatio n must be performed on the page, and then the page must be programmed with the overwritepr otect pin cleared to save the new page. lockrequest the lockrequest signal is used to give the user interface control over simultaneous access of the fb from both the user and jtag interfaces. when lockrequest is asserted, the jtag interface will hold off any access attempts until lockrequest is deasserted. flash memory bl ock operations fb operation priority the fb provides for priority of operations when multiple acti ons are requested simultaneously. table 2-22 shows the priority order (p riority 0 is the highest). table 2-21 ? data width settings datawidth[1:0] data width 00 1 byte [7:0] 01 2 byte [15:0] 10, 11 4 bytes [31:0] table 2-22 ? fb operation priority operation priority system initialization 0 fb reset 1 read 2 write 3 erase page 4 program 5 unprotect page 6 discard page 7
fusion family of mi xed-signal flash fpgas device architecture 2-48 v2.0 access to the fb is controlled by the busy signal. the busy output is synchronous to the clk signal. fb operations are only accepted in cycles where busy is logic 0. write operation write operations are initiated with the assertion of the wen signal. figure 2-35 on page 2-48 illustrates the multiple write operations. when a write operation is initiated to a page th at is currently not in the page buffer, the fb control logic will issue a busy signal to the us er interface while the page is loaded from the fb array into the page buffer. (note: the number of clock cycles th at the busy output is asserted during the load of the page buffer is variable.) after loading the page in to the page buffer, the addressed data block is loaded from the page buff er into the block buffer. subsequent writes to the same block of the page will incur no busy cycles. a write to another block in the page will assert busy for four cycles (five cycles when pipe is asserted), to allow the data to be written to the page buffer and have the current bl ock loaded into the block buffer. write operations are considered successful as long as the status output is '00'. a non-zero status indicates that an error was detected during th e operation and the write was not performed. note that the status output is "sticky"; it is unchanged until anothe r operation is started. only one word can be written at a time. write word width is controlled by the datawidth bus. users are responsible for keeping track of the cont ents of the page buffer and when to program it to the array. just like a regular ram, writing to random addresses is poss ible. users can write into the page buffer in any order but will incur additional busy cycles. it is not necessary to modify the entire page buffer before savi ng it to nonvolatile memory. write errors incl ude the following: 1. attempting to write a page that is overwrite protected (status = '01'). the write is not performed. 2. attempting to write to a page that is not in the page buffer when page loss protection is enabled (status = '11'). the write is not performed. program operation a program operation is initiated by asserting the program signal on the interface. program operations save the contents of the page buffer to the fb array. due to the technologies inherent in the fb, a program operation is a time consuming operation (~8 m s). while the fb is writing the data to the array, the busy signal will be asserted. figure 2-35 ? fb write waveform clk wen addr[17:0] wd[31:0] datawidth[1:0] pagelossprotect busy status[1:0] a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 s0 s1 s2 s3 s4 s5 s6
embedded memories v2.0 2-49 during a program operation, the sector and pa ge addresses on addr are compared with the stored address for the page (and sector) in the pa ge buffer. if there is a mismatch between the two addresses, the program operation will be aborted and an error will be reported on the status output. it is possible to write the page buffer to a diff erent page in memory. when asserting the program pin, if overwritepage is asserted as well, the fb will write the contents of the page buffer to the sector and page designated on th e addr inputs if the destination page is not overwrite protected. a program operation can be utilized to either modi fy the contents of the page in the flash memory block or change the protections for the page. se tting the overwriteprotec t bit on the interface while asserting the program pin will put the page addressed into overwrite protect mode. overwrite protect mode safe guards a page from being inad vertently overwritten during subsequent program or erase operations. program operations that result in a status value of '01' do not modify the addressed page. for all other values of status, the addressed page is modified. program errors include the following: 1. attempting to program a page that is overwrite protected (status = '01') 2. attempting to program a page that is not in the page buffe r when the page buffer has entered page loss protecti on mode (status = '01') 3. attempting to perform a program with over writepage set when th e page addressed has been overwrite protected (status = '01') 4. the write count of the page programmed ex ceeding the write threshold defined in the part specification (status = '11') 5. the ecc logic determining th at there is an uncorrectable error within the programmed page (status = '10') 6. attempting to program a page that is not in the page buffer when overwritepage is not set and the page in the page buffer is modified (status = '01') 7. attempting to program the page in the page buffer when the page buffer is not modified the waveform for a program operation is shown in figure 2-36 . note: overwritepage is only sampled when the program or erasepage pins are asserted. overwritepage is ignored in all other operations. figure 2-36 ? fb program waveform clk program addr[17:0] overwritepage overwriteprotect pagelossprotect busy status[1:0] page 0 valid
fusion family of mi xed-signal flash fpgas device architecture 2-50 v2.0 erase page operation the erase page operation is initiated when the erasepage pin is asserted. the erase page operation allows the user to erase (set user data to zero) any page within the fb. the use of the overwritepage and pagelossprotect pins is the same for erase as for a program page operation. as with the program page operation, a status of '01' indicates that th e addressed page is not erased. a waveform for an erase page operation is shown in figure 2-37 . erase errors include the following: 1. attempting to erase a page that is overwrite protected (status = '01') 2. attempting to erase a page that is not in the page buffer when the page buffer has entered page loss protection mode (status = '01') 3. the write count of the erased page exceed ing the write threshold defined in the part specification (status = '11') 4. the ecc logic determining that there is an uncorrectable error wi thin the erased page (status = '10') figure 2-37 ? fb erase page waveform clk erase addr[17:0] overwriteprotect pagelossprotect busy status[1:0] page valid
embedded memories v2.0 2-51 read operation read operations are designed to read data from the fb array, page buffer, block buffer, or status registers. read operations supp ort a normal read and a read-a head mode (done by asserting readnext). also, the timing for read operat ions is dependent on the setting of pipe. the following diagrams illustrate represen tative timing for non-pipe mode ( figure 2-38 ) and pipe mode ( figure 2-39 ) reads of the flash memory block interface. figure 2-38 ? read waveform (non-pipe mode, 32-bit access) figure 2-39 ? read waveform (pipe mo de, 32-bit access) clk ren addr[17:0] datawidth[1:0] busy status[1:0] rd[31:0] a0 a1 a2 a3 a4 0 s0s1s2 s4 0d0d1d20 d3 0 s3 d4 0 a0 a1 a2 a3 a4 0s0s1s2 d2 s4 0 0 d0 d1 d4 x0 clk ren addr[17:0] datawidth[1:0] busy status[1:0] rd[31:0] s3 0 d3
fusion family of mi xed-signal flash fpgas device architecture 2-52 v2.0 the following error indi cations are possible for read operations: 1. status = '01' when a single-bit data error was detected and correct ed within the block addressed. 2. status = '10' when a double-bit error was detected in the bl ock addressed (note that the error is uncorrected). in addition to data reads, users can read the sta tus of any page in the fb by asserting pagestatus along with ren. the format of the data returned by a page status read is shown in table 2-23 , and the definition of the page status bits is shown in table 2-24 . table 2-23 ? page status read data format 31 8 7 4 3 2 1 0 write count reserved over threshold read prot ected write protected overwrite protected table 2-24 ? page status bit definition page status bit(s) definition 31?8 the number of times the page ad dressed has been programmed/erased 7?4 reserved; read as 0 3 over threshold indicator (see the "program operation" section on page 2-48 ) 2 read protected; read protect bit for page, which is set via the jtag interface and only affects jtag operations. this bit can be overridden by using the correct user key value. 1 write protected; write protect bit for page, which is set via the jtag interface and only affects jtag operations. this bit can be overridden by using the correct user key value. 0 overwrite protected; designates that the user has set the overwriteprotect bit on the interface while doing a program operation. the page cannot be written without first performing an unprotect page operation.
embedded memories v2.0 2-53 read next operation the read next operation is a feature by which th e next block relative to the block in the block buffer is read from the fb arra y while performing reads from th e block buffer. the goal is to minimize wait states during consecutive sequential read operations. the read next operation is performed in a pr edetermined manner beca use it does look-ahead reads. the general look-ahead function is as follows: ? within a page, the next block fetched will be the next in linear address. ? when reading the last data block of a page, it will fetch the first bl ock of the next page. ? when reading spare pages, it will read the first block of the next sector's spare page. ? reads of the last sector w ill wrap around to sector 0. ? reads of auxiliary blocks will read th e next linear page's auxiliary block. when an address on the addr input does not ag ree with the predetermined look-ahead address, there is a time penalty for this access. the fb wi ll be busy finishing th e current look-ahead read before it can start the next read. the worst case is a total of nine busy cycles before data is delivered. the non-pipe mode and pipe mode waveforms for read ne xt operations are illustrated in figure 2-40 and figure 2-41 . figure 2-40 ? read next waveform (non-pipe mode, 32-bit access) figure 2-41 ? read next waveform (pipe mode, 32-bit access) clk ren readnext addr[17:0] datawidth[1:0] busy status[1:0] rd[31:0] a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 0 s0s1s2 s4s5s6 s8s9 0 d0d1d2 s3 d3 0 0 s7 d7 0 0 d4 d5 d6 d8 d9 clk ren readnext addr[17:0] busy status[1:0] rd[31:0] a0 a1 a2 a3 a4 a5 a6 a7 a8 s0 s1 s2 s4 s5 s6 0d0d1d2 s3 d3 0 0d4d5d6 s7 0 0 d7
fusion family of mi xed-signal flash fpgas device architecture 2-54 v2.0 unprotect page operation an unprotect page operation will clear the protec tion for a page addressed on the addr input. it is initiated by setting the unprotectpage signal on the interface along with the page address on addr. if the page is not in the page buffer, the unprot ect page operation will copy the page into the page buffer. the copy page operation occurs only if the current page in the page buffer is not page loss protected. the waveform for an unprotect page operation is shown in figure 2-42 . the unprotect page operation can incu r the following error conditions: 1. if the copy of the page to the page buffer determines that the page has a single-bit correctable error in the data, it will report a status = '01'. 2. if the address on addr does not match the address of the page bu ffer, pagelossprotect is asserted, and the page buffer has been modified, then status = '11' and the addressed page is not loaded into the page buffer. 3. if the copy of the page to the page buffer dete rmines that at least on e block in the page has a double-bit uncorrectable error, status = ' 10' and the page buffer will contain the corrupted data. discard page operation if the contents of the modified page buffer have to be discarded, the discardpage signal should be asserted. this command re sults in the page buffer being marked as unmodified. the timing for the operation is shown in figure 2-43 . the busy signal will re main asserted until the operation has completed. figure 2-42 ? fb unprotected page waveform clk unprotectpage addr[17:0] busy status[1:0] page valid figure 2-43 ? fb discard page waveform clk discardpage busy
embedded memories v2.0 2-55 flash memory bloc k characteristics figure 2-44 ? reset timing diagram table 2-25 ? flash memory block timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t clk2rd clock-to-q in 5-cycle read mode of the read data 7.99 9.10 10.70 ns clock-to-q in 6-cycle read mode of the read data 5.03 5.73 6.74 ns t clk2busy clock-to-q in 5-cycle read mo de of busy 4.95 5.63 6.62 ns clock-to-q in 6-cycle read mo de of busy 4.45 5.07 5.96 ns t clk2status clock-to-status in 5-cycle r ead mode 11.24 12.81 15.06 ns clock-to-status in 6-cycle read mode 4.48 5.10 6.00 ns t dsunvm data input setup time for the control logi c 1.92 2.19 2.57 ns t dhnvm data input hold time for the control logic 0.00 0.00 0.00 ns t asunvm address input setup ti me for the control lo gic 2.76 3.14 3.69 ns t ahnvm address input hold ti me for the control logic 0.00 0.00 0.00 ns t sudwnvm data width setup time for the control logic 1.85 2.11 2.48 ns t hddwnvm data width hold time for the control logic 0.00 0.00 0.00 ns t surennvm read enable setup time for the control logic 3.85 4.39 5.16 ns t hdrennvm read enable hold time for the control logic 0.00 0.00 0.00 ns t suwennvm write enable setup time for the control logic 2.37 2.69 3.17 ns t hdwennvm write enable hold time for th e control logic 0.00 0.00 0.00 ns t suprognvm program setup time for the co ntrol logic 2.16 2.46 2.89 ns t hdprognvm program hold time for the control logic 0.00 0.00 0.00 ns t susparepage sparepage setup time for the control logic 3.74 4.26 5.01 ns t hdsparepage sparepage hold time for the control logic 0.00 0.00 0.00 ns t suauxblk auxiliary block setup time for th e control logic 3.74 4.26 5.00 ns t hdauxblk auxiliary block hold time for the control logic 0.00 0.00 0.00 ns t surdnext readnext setup time for the control logic 2.17 2.47 2.90 ns t hdrdnext readnext hold time for the control logic 0.00 0.00 0.00 ns t suerasepg erase page setup time for the control logic 3.76 4.28 5.03 ns t hderasepg erase page hold time for the control logic 0.00 0.00 0.00 ns t suunprotectpg unprotect page setup time for th e control logic 2.01 2.29 2.69 ns t hdunprotectpg unprotect page hold time for th e control logic 0.00 0.00 0.00 ns t sudiscardpg discard page setup time for th e control logic 1.88 2.14 2.52 ns t hddiscardpg discard page hold time for th e control logic 0.00 0.00 0.00 ns t suoverwrpro overwrite protect setup time for the control logic 1.64 1.86 2.19 ns clk reset active low, asynchronous busy
fusion family of mi xed-signal flash fpgas device architecture 2-56 v2.0 t hdoverwrpro overwrite protect hold time for the control logic 0.00 0.00 0.00 ns t supglosspro page loss protect setup time for the control logic 1.69 1.93 2.27 ns t hdpglosspro page loss protect hold time for the control logic 0.00 0.00 0.00 ns t supgstat page status setup time for the control logic 2.49 2.83 3.33 ns t hdpgstat page status hold time for the control logic 0.00 0.00 0.00 ns t suoverwrpg over write page setup time for th e control logic 1.88 2.14 2.52 ns t hdoverwrpg over write page hold time for the control logic 0.00 0.00 0.00 ns t sulockrequest lock request setup time for th e control logic 0.87 0.99 1.16 ns t hdlockrequest lock request hold time for th e control logic 0.00 0.00 0.00 ns t recarnvm reset recovery time 0.94 1.07 1.25 ns t remarnvm reset removal time 0.00 0.00 0.00 ns t mpwarnvm asynchronous reset minimum pulse width for the control logic 10.00 12.50 12.50 ns t mpwclknvm clock minimum pulse width for the control logic 4.00 5.00 5.00 ns t fmaxclknvm maximum frequency for cloc k for the control logic ? for afs1500/afs600 80.00 80.00 80.00 mhz maximum frequency for cloc k for the control logic ? for afs250/afs090 100.00 80.00 80.00 mhz table 2-25 ? flash memory block timing (continued) commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units
embedded memories v2.0 2-57 flashrom fusion devices have 1 kbit of on-chip nonvolatil e flash memory that can be read from the fpga core fabric. the flashrom is arranged in eight ba nks of 128 bits during programming. the 128 bits in each bank are addressable as 16 bytes during the read-back of the flashrom from the fpga core ( figure 2-45 ). the flashrom can only be programmed via the ieee 1532 jtag port. it cannot be programmed directly from the fpga core. when programming, each of the eight 128-bit banks can be selectively reprogrammed. the flashrom ca n only be reprogrammed on a bank boundary. programming involves an automatic, on-chi p bank erase prior to reprogramming the bank. the flashrom supports a synchronous read and can be read on byte boundaries. the upper three bits of the flashrom address from the fpga co re define the bank that is be ing accessed. the lower four bits of the flashrom address from the fpga core defi ne which of the 16 bytes in the bank is being accessed. the maximum flashrom access clock is 20 mhz. figure 2-46 shows the timing behavior of the flashrom access cycle?the address has to be set up on the rising edge of the clock for dout to be valid on the next falling edge of the clock. if the address is unch anged for two cycles: ? d0 becomes invalid 10 ns after the second rising edge of the clock. ? d0 becomes valid again 10 ns a fter the second falling edge. if the address unchanged for three cycles: ? d0 becomes invalid 10 ns after the second rising edge of the clock. ? d0 becomes valid again 10 ns a fter the second falling edge. ? d0 becomes invalid 10 ns after the third rising edge of the clock. ? d0 becomes valid again 10 ns after the third falling edge. figure 2-45 ? flashrom architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
fusion family of mi xed-signal flash fpgas device architecture 2-58 v2.0 flashrom characteristics figure 2-46 ? flashrom timing diagram table 2-26 ? flashrom access time commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t su address setup time 0.53 0.61 0.71 ns t hold address hold time 0.00 0.00 0.00 ns t ck2q clock to out 21.42 24.40 28.68 ns f max maximum clock frequency 15.00 15.00 15.00 mhz t su t hold address a0 t ck2q d0 d0 a1 t su t hold t ck2q d1 t su t hold t ck2q
embedded memories v2.0 2-59 sram and fifo all fusion devices have sram blocks along the north side of the device. additionally, afs600 and afs1500 devices have an sram block on the south side of the device. to meet the needs of high- performance designs, the memory blocks operate s trictly in synchronous mo de for both read and write operations. the read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 mh z. the following config urations are available: ? 4k1, 2k2, 1k4, 5129 (dual-port ram?two read, two write or one read, one write) ? 5129, 25618 (two-port ra m?one read and one write) ? sync write, sync pipelined/nonpipelined read the fusion sram memory block includes dedica ted fifo control logic to generate internal addresses and external flag logic (full, empty, afull, aempty). during ram operation, addresses are sourced by the user logic, and the fifo controller is ignored. in fifo mode, the internal addresses are generate d by the fifo controller and routed to the ram array by internal muxes. refer to figure 2-47 for more information ab out the implementation of the embedded fi fo controller. the fusion architecture enables the read and write sizes of rams to be organized independently, allowing for bus conversion. this is done with th e ww (write width) and rw (read width) pins. the different dw configurations are 25618, 5129, 1k 4, 2k2, and 4k1. for example, the write size can be set to 25618 and the read size to 5129. both the write and read widths for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. the different dw configurat ions are 25618, 5129, 1k4, 2k2, and 4k1. refer to the allowable rw and ww values su pported for each of the ram macro types in table 2-27 on page 2-61 . when a width of one, two, or four is selected, the ninth bit is unused. for example, when writing 9- bit values and reading 4-bit values, only the first four bits and the second four bits of each 9-bit value are addressable for read operat ions. the ninth bit is not accessible. conversely, when writing 4-bit values and reading 9-bit values, the ninth bi t of a read operation will be undefined. the ram blocks employ little-en dian byte order for read and write operations. figure 2-47 ? fusion ram block with embedded fifo controller rclk wd wclk reset rblk ren estop wblk wen fstop rd[17:0] wd[17:0] rclk wclk radd[j:0] wadd[j:0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram cnt 12 e = e = afval aeval sub 12 cnt 12
fusion family of mi xed-signal flash fpgas device architecture 2-60 v2.0 ram4k9 description figure 2-48 ? ram4k9 addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 reset
embedded memories v2.0 2-61 the following signals are used to co nfigure the ram4k9 memory element: widtha and widthb these signals en able the ram to be configured in one of four allowable aspect ratios ( table 2-27 ). blka and blkb these signals are active low and wi ll enable the respecti ve ports when asserted. when a blkx signal is deasserted, the corresp onding port?s outputs hold the previous value. wena and wenb these signals switch th e ram between read and write mode for the respective ports. a low on these signals indicates a write operat ion, and a high indicates a read. clka and clkb these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. pipea and pipeb these signals are used to specify pipelined read on the output. a low on pipea or pipeb indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. a high indicates a pipelined, read and data appears on the corresponding output in the next clock cycle. wmodea and wmodeb these signals are used to config ure the behavior of the output when the ram is in write mode. a low on these signals makes the output retain data from the previous read. a high indicates pass- through behavior, wherein the data being writte n will appear immediately on the output. this signal is overridden when the ram is being read. reset this active low signal re sets the output to zero, disables read s and writes from th e sram block, and clears the data hold registers when asserted. it does not reset the contents of the memory. addra and addrb these are used as read or write addresses, and th ey are 12 bits wide. when a depth of less than 4 k is specified, the unused high-order bits must be grounded ( table 2-28 ). table 2-27 ? allowable aspect ratio settings for widtha[1:0] widtha1, widtha0 widthb1, widthb0 dw 00 00 4k1 01 01 2k2 10 10 1k4 11 11 5129 note: the aspect ratio settings are consta nt and cannot be changed on the fly. table 2-28 ? address pins unused/used for various supported bus widths dw addrx unused used 4k1 none [11:0] 2k2 [11] [10:0] 1k4 [11:10] [9:0] 5129 [11:9] [8:0] note: the "x" in addrx implies a or b.
fusion family of mi xed-signal flash fpgas device architecture 2-62 v2.0 dina and dinb these are the input data signals, and they are ni ne bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused hi gh-order signals must be grounded ( table 2-29 ). douta and doutb these are the nine-bit output data signals. not all nine bits are valid in all configurations. as with dina and dinb, high-order bits may not be used ( table 2-29 ). the output data on unused pins is undefined. table 2-29 ? unused/used input and output data pins for various supported bus widths dw dinx/doutx unused used 4k1 [8:1] [0] 2k2 [8:2] [1:0] 1k4 [8:4] [3:0] 5129 none [8:0] note: the "x" in dinx and doutx implies a or b.
embedded memories v2.0 2-63 ram512x18 description figure 2-49 ? ram512x18 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset
fusion family of mi xed-signal flash fpgas device architecture 2-64 v2.0 ram512x18 exhibits slightly differ ent behavior from ram4k9, as it has dedicated read and write ports. ww and rw these signals en able the ram to be configured in one of the two allowable aspect ratios ( table 2-30 ). wd and rd these are the input an d output data signals, and they are 18 bits wide. when a 5129 aspect ratio is used for write, wd[17:9] are unused and must be grounded. if this aspect ratio is used for read, then rd[17:9] are undefined. waddr and raddr these are read and write addresse s, and they are nine bits wide . when the 25618 aspect ratio is used for write or read, waddr[8] or r addr[8] are unused and must be grounded. wclk and rclk these signals are the write and read clocks, respectively. they are both active high. wen and ren these signals are the write and read enables, resp ectively. they are both active low by default. these signals can be conf igured as active high. reset this active low signal resets th e output to zero, disables reads and/or writes from the sram block, and clears the data hold registers when asserted. it does not reset the contents of the memory. pipe this signal is used to specify pipelined read on the output. a low on pi pe indicates a nonpipelined read, and the data appears on the output in th e same clock cycle. a high indicates a pipelined read, and data appears on the ou tput in the next clock cycle. clocking the dual-port sram blocks are only clocked on the rising edge. smartgen allows falling-edge- triggered clocks by adding inverters to the netlist, hence achieving dual-port sram blocks that are clocked on either edge (rising or falling). for dual-port sram, each port can be clocked on either edge or by separate clocks, by port. fusion devices support inversion (bubble pushing) throughout the fpga architecture, including the clock input to the sram modules. inversions added to the sram clock pin on the design schematic or in the hdl code will be automatically acco unted for during design compile with out incurring additional delay in the clock path. the two-port sram can be cloc ked on the rising edge or fa lling edge of wclk and rclk. if negative-edge ram and fifo clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the fusion development tools, without performance penalty. table 2-30 ? aspect ratio settings for ww[1:0] ww[1:0] rw[1:0] dw 01 01 5129 10 10 25618 00, 11 00, 11 reserved
embedded memories v2.0 2-65 modes of operation there are two read modes and one write mode: ? read nonpipelined (synchronous?1 clock edge ): in the standard read mode, new data is driven onto the rd bus in the same clock cycle following ra and ren valid. the read address is registered on the read port clock active edge, and data appears at rd after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchronous?2 clock edges): the pipelined mode incurs an additional clock delay from the address to the data but enables operation at a much higher frequency. the read address is registered on the read port acti ve clock edge, and the read data is registered and appears at rd after the se cond read clock edge . setting pipe to on enables this mode. ? write (synchronous?1 clock edge ): on the write clock active ed ge, the write data is written into the sram at the write ad dress when wen is hi gh. the setup times of the write address, write enables, and write data are minimal with resp ect to the write clock. write and read transfers are described with timing requirements in the "sram characteristics" section on page 2-66 and the "fifo characteristics" section on page 2-77 . ram initialization each sram block can be individually initialized on power-up by means of the jtag port using the ujtag mechanism (refer to the "jtag ieee 1532" section on page 2-229 and the fusion sram/fifo blocks application note). the shift regi ster for a target block can be selected and loaded with the proper bit configuration to enable serial loading. the 4,608 bits of data can be loaded in a single operation.
fusion family of mi xed-signal flash fpgas device architecture 2-66 v2.0 sram characteristics timing waveforms figure 2-50 ? ram read for flow-through output figure 2-51 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
embedded memories v2.0 2-67 figure 2-52 ? ram write, output retained (wmode = 0) figure 2-53 ? ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (flow-through) do (pipelined) di 0 di 1 d n di 0 di 1 d n di 1 di 2 d 0
fusion family of mi xed-signal flash fpgas device architecture 2-68 v2.0 figure 2-54 ? one port write / other port read same figure 2-55 ? write access after write onto same address a 0 a 2 a 3 a 0 a 1 a 4 clk1 add1 clk2 add2 di1 d 0 d 2 d 3 d 0 d 1 d 0 do2 (flow-through) do2 (pipelined) t ckq2 t ckq1 t wro t as t ah t ds t dh t as t ah d n d n clk1 add1 wen_b2 di1 wen_b1 clk2 add2 di2 d 3 do2 (pass-through) t as t ah a 0 d 1 a 1 d n d 4 a 3 t cckh t ckq1 a 0 a 0 a 4 d 0 t as t ah do2 (pipelined) t ds t dh d 2 d n d 0 d 0 t ckq2
embedded memories v2.0 2-69 figure 2-56 ? read access after write onto same address clk1 add1 wen_b2 di1 wen_b1 clk2 add2 do2 (pass-through) d 3 do2 (pipelined) t as t ah t wro a 0 d 0 a 2 d n a 3 a 0 a 1 a 4 t as t ah d 2 t ds t dh t ckq1 d 0 d 1 d n d 0 t ckq2
fusion family of mi xed-signal flash fpgas device architecture 2-70 v2.0 figure 2-57 ? write access after read onto same address figure 2-58 ? ram reset clk1 add1 clk2 wen_b1 do1 (pipelined) do1 (pass-through) add2 di2 t ckq1 wen_b2 t as t ah d n a 0 t ckq1 a 1 d 1 d 2 d 3 d n a 0 d 0 d 0 t ckq2 t cckh a 0 a 1 a 3 d 1 t as t ah clk reset_b do d n t cyc t ckh t ckl t rstbq d m
embedded memories v2.0 2-71 timing characteristics table 2-31 ? ram4k9 commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren_b, wen_b setup ti me 0.14 0.16 0.19 ns t enh ren_b, wen_b hold ti me 0.10 0.11 0.13 ns t bks blk_b setup time 0.23 0.27 0.31 ns t bkh blk_b hold time 0.02 0.02 0.02 ns t ds input data (di) setup time 0.18 0.21 0.25 ns t dh input data (di) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (out put retained, wmode = 0) 1.79 2.03 2.39 ns clock high to new data valid on do (f low-through, wmode = 1) 2.36 2.68 3.15 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 ns t c2cwwh address collision clk-to-clk delay for reliable write after write on same address?applicable to rising edge 0.30 0.26 0.23 ns t c2crwh address collision clk-to-clk delay fo r reliable read access after write on same address?applicable to opening edge 0.45 0.38 0.34 ns t c2cwrh address collision clk-to-clk delay fo r reliable write access after read on same address? applicable to opening edge 0.49 0.42 0.37 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 ns t remrstb reset_b removal 0.29 0.33 0.38 ns t recrstb reset_b recovery 1.50 1.71 2.01 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-72 v2.0 table 2-32 ? ram512x18 commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren_b, wen_b setup time 0.09 0.10 0.12 ns t enh ren_b, wen_b hold time 0.06 0.07 0.08 ns t ds input data (di) setup time 0.18 0.21 0.25 ns t dh input data (di) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (out put retained, wmode = 0) 2.16 2.46 2.89 ns t ckq2 clock high to new data valid on do (pipelined) 0.90 1.02 1.20 ns t c2crwh address collision clk-to-clk delay fo r reliable read access after write on same address?applicable to opening edge 0.50 0.43 0.38 ns t c2cwrh address collision clk-to-clk delay fo r reliable write access after read on same address? applic able to opening edge 0.59 0.50 0.44 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 ns t remrstb reset_b removal 0.29 0.33 0.38 ns t recrstb reset_b recovery 1.50 1.71 2.01 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
embedded memories v2.0 2-73 fifo4k18 description figure 2-59 ? fifo4kx18 fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
fusion family of mi xed-signal flash fpgas device architecture 2-74 v2.0 the following signals are used to co nfigure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( table 2-33 ). wblk and rblk these signals are active low and w ill enable the respective ports when low. when the rblk signal is high, the corresponding port?s outputs hold the previous value. wen and ren read and write enables. wen is active low and ren is active high by default. these signals can be configured as active high or low. wclk and rclk these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. rpipe this signal is used to specify pipelined r ead on the output. a lo w on rpipe indicates a nonpipelined read, and the data ap pears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. reset this active low signal re sets the output to zero when asserted . it resets the fifo counters. it also sets all the rd pins low, the full and afull pins low, and the empty and aempty pins high ( table 2-34 ). wd this is the input data bus and is 18 bits wide. not all 18 bits are valid in al l configurations. when a data width less than 18 is specified, unus ed higher-order signals must be grounded ( table 2-34 ). rd this is the output data bus and is 18 bits wide. not all 18 bits are va lid in all configurations. like the wd bus, high-order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( table 2-34 ). table 2-33 ? aspect ratio settings for ww[2:0] ww2, ww1, ww0 rw2, rw1, rw0 d w 000 000 4k 1 001 001 2k 2 010 010 1k 4 011 011 512 9 100 100 256 18 101, 110, 111 101, 110, 111 reserved table 2-34 ? input data signal usage fo r different aspect ratios dw wd/rd unused 4k 1 wd[17:1], rd[17:1] 2k 2 wd[17:2], rd[17:2] 1k 4 wd[17:4], rd[17:4] 512 9 wd[17:9], rd[17:9] 256 18 ?
embedded memories v2.0 2-75 estop, fstop estop is used to stop the fifo re ad counter from further counting on ce the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. fstop is used to stop th e fifo write counter from further coun ting once the fifo is full (i.e., the full flag goes high). a high on this signal inhibits the counting. for more information on th ese signals, refer to the "estop and fstop usage" section on page 2-76 . full, empty when the fifo is full and no more data can be written, the full flag asse rts high. the full flag is synchronous to wclk to inhibit writing immediately upon detection of a full condition and to prevent overflows. since the write address is co mpared to a resynchron ized (and thus time- delayed) version of the read addr ess, the full flag will remain asserted until two wclk active edges after a read operation el iminates the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immediately upon detection of an empty condition and to prevent underflows. since th e read address is compared to a resynchronized (and thus time- delayed) version of the write address, the empt y flag will remain asserted until two rclk active edges after a write operation removes the empty condition. for more information on these signals, refer to the "fifo flag usage cons iderations" section on page 2-76 . afull, aempty these are programmable flags and will be asse rted on the threshold specified by afval and aeval, respectively. when the number of words store d in the fifo reaches the am ount specified by aeval while reading, the aempty output will go high. likewis e, when the number of words stored in the fifo reaches the amount specified by afval while writing, the afull output will go high.
fusion family of mi xed-signal flash fpgas device architecture 2-76 v2.0 afval, aeval the aeval and afval pins are used to specify the almost-empty and almost-full threshold values, respectively. they are 12-bit signals. fo r more information on these signals, refer to "fifo flag usage considerations" section . estop and fstop usage the estop pin is used to stop th e read counter from co unting any further once the fifo is empty (i.e., the empty flag goes high). likewise, the fstop pin is used to stop the wr ite counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the fusion device start the count at 0, reach the maximum depth for the configuration (e.g., 511 for a 51 29 configuration), and then resta rt at 0. an exam ple application for the estop, where the read counter keeps coun ting, would be writing to the fifo once and reading the same content over and over without doing another write. fifo flag usage considerations the aeval and afval pins are used to specify the 12-bit aempty and afull threshold values, respectively. the fifo contains separate 12-bi t write address (waddr) and read address (raddr) counters. waddr is incremente d every time a write operation is performed, and raddr is incremented every time a read operation is pe rformed. whenever the difference between waddr and raddr is greater than or equal to afval, the afull out put is asserted. likewise, whenever the difference between waddr and raddr is less than or equal to aeval, the aempty output is asserted. to handle different read and write aspect ratios, afval and aeval are expressed in terms of total data bits instead of total data wo rds. when users specify afval and aeval in terms of read or write words, the smartgen tool transl ates them into bit addre sses and configures these signals automaticall y. smartgen configures the afull flag to assert when the write address exceeds the read address by at least a predefined value. in a 2k8 fifo, for example, a value of 1,500 for afval means that the afull flag will be asserted after a write when the difference between the write address and the read address re aches 1,500 (there have been at least 1500 more writes than reads). it will stay asserted until the difference be tween the write and read addresses drops below 1,500. the aempty flag is asserted when the difference between the write address and the read address is less than a predefined value. in the exampl e above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. it will stay asserted un til that difference rises above 200. note that the fifo can be configured with different read and write widths; in this case, the afval setting is based on the number of write data entries and the aeval setting is based on the number of read data entries. for aspect ratios of 5129 and 25618, only 4,096 bits can be addressed by the 12 bits of afval and aeval. the number of words must be multiplied by 8 and 16, instead of 9 and 18. the smartgen tool automatically uses the proper values. to avoid halfwords being written or read, which could happen if different read and write aspect ratios are spec ified, the fifo will assert full or empty as soon as at least a minimum of one wo rd cannot be written or read. for example, if a two-bit word is written and a four-bit word is be ing read, the fifo will remain in the empty state when the first word is written. this occurs even if the fifo is not completely empty, because in this case, a complete word cannot be read. the same is applicable in the full state. if a four-bit word is written and a two-bit word is read , the fifo is full and one word is read. the full flag will remain asserted because a complete word cannot be written at this point.
embedded memories v2.0 2-77 fifo characteristics timing waveforms figure 2-60 ? fifo reset figure 2-61 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b ef aef wa/ra (address counter) t rstfg t rstaf ff aff rclk no match no match dist = aef_th match (empty) t ckaf t rckef ef aef t cyc wa/ra (address counter)
fusion family of mi xed-signal flash fpgas device architecture 2-78 v2.0 figure 2-62 ? fifo full and afu ll flag assertion figure 2-63 ? fifo empty flag and ae mpty flag deassertion figure 2-64 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk ff aff wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk ef 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aef rclk wa/ra (address counter) match (full) no match no match no match dist = aff_th - 1 no match wclk ff 1st rising edge after 1st read 1st rising edge after 2nd read t wckf t ckaf aff
embedded memories v2.0 2-79 timing characteristics table 2-35 ? fifo commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t ens ren_b, wen_b setup time 1.34 1.52 1.79 ns t enh ren_b, wen_b hold time 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 ns t bkh blk_b hold time 0.00 0.00 0.00 ns t ds input data (di) setu p time 0.18 0.21 0.25 ns t dh input data (di) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.17 2.47 2.90 ns t ckq2 clock high to new data valid on do (pipelined) 0.94 1.07 1.26 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 ns t wckff wclk high to full fl ag valid 1.63 1.86 2.18 ns t ckaf clock high to almost empty/fu ll flag valid 6.19 7.05 8.29 ns t rstfg reset_b low to empty/full flag valid 1.69 1.93 2.27 ns t rstaf reset_b low to almo st-empty/full flag valid 6.13 6.98 8.20 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 ns t remrstb reset_b removal 0.29 0.33 0.38 ns t recrstb reset_b recovery 1.50 1.71 2.01 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency for fifo 310 272 231 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-80 v2.0 analog block with the fusion family, actel has introduced the wo rld's first mixed-mo de fpga solution. supporting a robust analog pe ripheral mix, fusion devices will support a wide variety of applications. it is this analog block that se parates fusion from all other fpga solutions on the market today. by combining both flash and high-speed cmos processes in a single chip, these devices offer the best of both worlds. the high-pe rformance cmos is used for building ram resources. these high- performance structures support device operation up to 350 mhz. additionally, the advanced actel 0.13 m flash process incorporates high-voltage tra nsistors and a high-isolati on, triple-well process. both of these are suited for the flash-ba sed programmable logic and nonvolatile memory structures. high-voltage transistors support th e integration of analog technology in seve ral ways. they aid in noise immunity so that the analog portions of th e chip can be better isolated from the digital portions, increasing analog accuracy. because they support high voltages, actel flash fpgas can be connected directly to high-voltage input signals, el iminating the need for external resistor divider networks, reducing component count, and increasing accuracy. by supporting higher internal voltages, the actel advanced flash process enab les high dynamic range on analog circuitry, increasing precision and signal?noise ratio. acte l flash fpgas also driv e high-voltage outputs, eliminating the need for external level shifters and drivers. the unique triple-well process en ables the integration of high-p erformance analog features with increased noise immunity and better isolation. by increasing the efficiency of analog design, the triple-well process also enables a smaller overal l design size, reducing die size and cost. the analog block consi sts of the analog quad i/o structure, rtc (for details refer to the "real-time counter system" section on page 2-34 ), adc, and acm. all of these elements are combined in the single analog block macro, with which th e user implements this functionality ( figure 2-65 ). the analog block needs to be reset/reinitialized after the core powers up or the device is programmed. an external reset/initialize sign al, which can come from the internal voltage regulator when it powers up, must be applied.
analog block v2.0 2-81 figure 2-65 ? analog block macro varef gndref av0 ac0 at0 av9 ac9 at9 atreturn01 atreturn9 denav0 denac0 davout0 dacout0 datout0 dacout9 davout9 datout9 ag1 ag0 ag9 denat0 denav0 denac0 denat0 cmstb0 csmtb9 gdon0 gdon9 tmstb0 tmstb9 mode[3:0] tvc[7:0] stc[7:0] chnumber[4:0] tmstint adcstart varefsel pwrdwn adcreset busy calibrate datavalid sample result[11:0] rtcmatch rtcxtlmode rtcxtlsel rtcpsmmatch rtcclk sysclk acmwen acmrdata[7:0] acmreset acmwdata acmaddr acmclk ab
fusion family of mi xed-signal flash fpgas device architecture 2-82 v2.0 table 2-36 describes each pin in the analog block. each function within the analog block will be explained in detail in the following sections. table 2-36 ? analog block pin description signal name number of bits direction function location of details varef 1 input/output voltage reference for adc adc gndref 1 input external ground reference adc mode[3:0] 4 input adc operating mode adc sysclk 1 input external system clock tvc[7:0] 8 input clock divide control adc stc[7:0] 8 input sample time control adc adcstart 1 input start of conversion adc pwrdwn 1 input adc comparator power-down if 1. when asserted, the adc will stop functioning, and the digital portion of the analog block will continue operating. this may result in invalid status flags from the analog block. therefore, actel does not recommend asserting the pwrdwn pin. adc adcreset 1 input adc resets and disables analog quad ? active high adc busy 1 output 1 ? running conversion adc calibrate 1 output 1 ? power-up calibration adc datavalid 1 output 1 ? valid conversion result adc result[11:0] 12 output conversion result adc tmstbint 1 input internal temp. monitor strobe adc sample 1 output 1 ? an analog signal is actively being sampled (stays hi gh during signal acquisition only) 0 ? no analog signal is being sampled adc varefsel 1 input 0 = output internal voltage reference (2.56 v) to varef 1 = input external voltage reference from varef and gndref adc chnumber[4:0] 5 input analog input channel select input multiplexer acmclk 1 input acm clock acm acmwen 1 input acm write en able ? acti ve high acm acmreset 1 input acm reset ? active low acm acmwdata[7:0] 8 input acm write data acm acmrdata[7:0] 8 output acm read data acm acmaddr[7:0] 8 input acm address acm
analog block v2.0 2-83 cmstb0 to cmstb9 10 input current monitor strobe ? 1 per quad, active high analog quad gdon0 to gdon9 10 input control to power mos ? 1 per quad analog quad tmstb0 to tmstb9 10 input tempera ture monitor strobe ? 1 per quad; active high analog quad davout0, dacout0, datout0 to davout9, dacout9, datout9 30 output digital outputs ? 3 per quad analog quad denav0, denac0, denat0 to denav9, denac9, denat9 30 input digital input enable s ? 3 per quad analog quad av0 1 input analog quad 0 analog quad ac0 1 input analog quad ag0 1 output analog quad at0 1 input analog quad atreturn01 1 input temperatur e monitor return shared by analog quads 0 and 1 analog quad av1 1 input analog quad 1 analog quad ac1 1 input analog quad ag1 1 output analog quad at1 1 input analog quad av2 1 input analog quad 2 analog quad ac2 1 input analog quad ag2 1 output analog quad at2 1 input analog quad atreturn23 1 input temperatur e monitor return shared by analog quads 2 and 3 analog quad av3 1 input analog quad 3 analog quad ac3 1 input analog quad ag3 1 output analog quad at3 1 input analog quad av4 1 input analog quad 4 analog quad ac4 1 input analog quad ag4 1 output analog quad at4 1 input analog quad atreturn45 1 input temperatur e monitor return shared by analog quads 4 and 5 analog quad av5 1 input analog quad 5 analog quad ac5 1 input analog quad ag5 1 output analog quad at5 1 input analog quad table 2-36 ? analog block pin description (continued) signal name number of bits direction function location of details
fusion family of mi xed-signal flash fpgas device architecture 2-84 v2.0 analog quad with the fusion family, actel intro duces the analog quad, shown in figure 2-66 on page 2-85 , as the basic analog i/o structure. th e analog quad is a four-channel sy stem used to precondition a set of analog signals before sending it to the adc for conversion into a digital signal. to maximize the usefulness of the analog quad, th e analog input signals can also be configured as lvttl digital input signals. the analog quad is divided into four sections. the first section is called the vo ltage monitor block, and its input pin is named av. it contains a two-channel analog multiplexer that allows an incoming analog signal to be routed directly to the adc or allows the signal to be routed to a pr escaler circuit before being sent to the adc. the prescaler can be configured to accept analog si gnals between ?12 v and 0 or between 0 and +12 v. the prescaler circuit scales the voltage applied to the adc input pad such that it is compatible with the adc input voltage range. the av pin can also be used as a digital input pin. the second section of the analog quad is called the current monitor block. its input pin is named ac. the current moni tor block contains all th e same functions as the voltage monitor block with one addition, which is a current monitoring func tion. a small external current sensing resistor (typically less than 1 ) is connected between the av and ac pins and is in series with a power av6 1 input analog quad 6 analog quad ac6 1 input analog quad ag6 1 output analog quad at6 1 input analog quad atreturn67 1 input temperatur e monitor return shared by analog quads 6 and 7 analog quad av7 1 input analog quad 7 analog quad ac7 1 input analog quad ag7 1 output analog quad at7 1 input analog quad av8 1 input analog quad 8 analog quad ac8 1 input analog quad ag8 1 output analog quad at8 1 input analog quad atreturn89 1 input temperatur e monitor return shared by analog quads 8 and 9 analog quad av9 1 input analog quad 9 analog quad ac9 1 input analog quad ag9 1 output analog quad at9 1 input analog quad rtcmatch 1 output match rtc rtcpsmmatch 1 output match connected to vrpsm rtc rtcxtlmode[1:0] 2 output drives xtlosc rtcmode[1:0] pins rtc rtcxtlsel 1 output drives xtlosc modesel pin rtc rtcclk 1 input rtc clock input rtc table 2-36 ? analog block pin description (continued) signal name number of bits direction function location of details
analog block v2.0 2-85 source. the current monitor block contains a cu rrent monitor circuit th at converts the current through the external resistor to a voltage that can then be read using the adc. the third part of the analog quad is called the gate driver block, and its output pin is named ag. this section is used to drive an external fet. there are two modes availabl e: a high current drive mode and a current source control mode. both negative and positive voltage polarities are available, and in the current source control mode , four different current levels are available. the fourth section of th e analog quad is called the temperat ure monitor block, and its input pin name is at. this block is similar to the voltage monitor block, except th at it has an additional function: it can be used to monitor the temperat ure of an external diode-connected transistor. it has a modified prescaler and is lim ited to positive voltages only. the analog quad can be configured during design time by actel libero ide; however, the acm can be used to change the parameters of any of th ese i/os during runtime. this type of change is referred to as a context switch. the analog quad is a modular structure th at is replicated to generate the analog i/o resource s. each fusion device supports between 5 and 10 analog quads. the analog pads are numb ered to clearly identify both the type of pad (voltage, current, gate driver, or temperature pad) and its corresponding analog quad (a v0, ac0, ag0, at0, av1, ?, ac9, ag9, and at9). there are three types of input pads (avx, acx, and atx) and one type of analog output pad (agx). since there can be up to 10 analog quads on a device, there can be a maximum of 30 analog input pads an d 10 analog output pads. figure 2-66 ? analog quad analog quad av ac at voltage monitor block current monitor block ag prescaler prescaler prescaler digital input power mosfet gate driver current monitor/instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
fusion family of mi xed-signal flash fpgas device architecture 2-86 v2.0 voltage monitor the fusion analog quad offers a robust set of voltage-monitori ng capabilities unique in the fpga industry. the analog quad comprises three an alog input pads? analog voltage (av), analog current (ac), and analog temperature (at)?and a single gate driver output pad, analog gate (ag). there are many common charac teristics among the analog inpu t pads. each an alog input can be configured to connect directly to the input mux of the adc. when configured in this manner ( figure 2-67 ), there will be no prescaling of the input signal. care must be taken in this mode not to drive the adc into sa turation by applying an input voltag e greater than the reference voltage. the internal reference voltage of the adc is 2.56 v. optionally , an external reference can be supplied by the us er. the external reference ca n be a maximum of 3.3 v dc. figure 2-67 ? analog quad direct connect prescaler prescaler prescaler analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
analog block v2.0 2-87 the analog quad offers a wide variety of prescali ng options to enable the adc to resolve the input signals. figure 2-68 shows the path through the analog quad for a signal that is to be prescaled prior to conversion. the adc inte rnal reference voltage and the pr escaler factors were selected to make both prescaling and postscaling of the signals easy binary calculations (refer to table 2-54 on page 2-131 for details). when an analog input pad is co nfigured with a prescaler, there will be a 1m resistor to ground. this occurs even when the device is in power-down mode. in low power standby or sleep mode (v cc is off, v cc33a is on, v cci is on) or when the resource is not used, analog inputs are pulled down to ground through a 1 m resistor. the gate driver output is floating (or tristated), and ther e is no extra current on v cc33a . these scaling factors hold true whether the particular pad is configured to accept a positive or negative voltage. note that whereas the av and ac pads support the same prescaling factors, the at pad supports a reduced set of prescaling factors and supports posi tive voltages only. typical scaling factors are given in table 2-54 on page 2-131 , and the gain error (which contributes to the minimum and maximum) is in table 2-46 on page 2-118 . figure 2-68 ? analog quad prescaler input configuration prescaler prescaler prescaler analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analo g mux to analo g mux to analo g mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
fusion family of mi xed-signal flash fpgas device architecture 2-88 v2.0 terminology bw ? bandwidth bw is a range of frequencie s that a channel can handle. channel a channel is define as an an alog input configured as one of the prescaler range shown in table 2-54 on page 2-131 . the channel includ es the prescaler circuit and the adc. channel gain channel gain is a measured of the deviation of th e actual slope from the ideal slope. the slope is measured from the 20% and 80% point. eq 2-1 channel gain error channel gain error is a deviation from the ideal slope of the transfer function. the prescaler gain error is expressed as the percent difference between the actual and ideal, as shown in eq 2-2 . eq 2-2 channel input offset error channel offset error is measured as the input voltage that causes the transition from zero to a count of one. an ideal prescaler will have offset equal to ? of lsb voltage. offset error is a positive or negative when the first transition point is higher or lower than ideal. offset error is expressed in lsb or input voltage. total channel error total channel error is defined as the total erro r measured compared to the ideal value. total channel error is the sum of gain error and offset error combined. figure 2-69 shows how total channel error is measured. total channel error is defined as the difference between the actual ad c output and ideal adc output. in the example shown in figure 2-69 , the total channel error wo uld be a negative number. figure 2-69 ? total channel error example gain gain actual gain ideal ----------------------- - = error gain (1-gain) 100% = adc output code ideal output input voltage to prescaler total channel error channel gain actual output c hannel input offset error }
analog block v2.0 2-89 direct digital input the av, ac, and at pads can also be configured as high-voltage digital inputs ( figure 2-70 ). as these pads are 12 v?tolerant, the digital input can also be up to 12 v. however, the frequency at which these pads can operate is limited to 10 mhz. to enable one of these analog input pads to oper ate as a digital input, its corresponding digital input enable (dena xy ) pin on the analog block mu st be pulled high, where x is either v, c, or t (for av, ac, or at pads, respectively) and y is in the range 0 to 9, co rresponding to the appropriate analog quad. when the pad is configured as a digital input, th e signal will come out of the analog block macro on the appropriate da x out y pin, where x represents the pad type (v for av pad, c for ac pad, or t for at pad) and y represents the appropriat e analog quad number. ex ample: if the at pad in analog quad 5 is configured as a digital input, it will come out on the datout5 pin of the analog block macro. figure 2-70 ? analog quad direct digital input configuration analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx) prescaler prescaler prescaler
fusion family of mi xed-signal flash fpgas device architecture 2-90 v2.0 current monitor the fusion analog quad is an excellent element for voltage- and current-monitoring applications. in addition to supporting the same functionality offered by the av pad, the ac pad can be configured to monitor current acro ss an external sense resistor ( figure 2-71 ). to support this current monitor function, a differential amplifier with 10x ga in passes the amplified voltage drop between the av and ac pads to the adc. the amplifier enables the user to use very small resistor values, thereby limiting an y impact on the circuit. this function of the ac pad does not limit av pad operation. the av pad can still be configured for use as a direct voltage input or scaled through the av prescaler independently of it?s use as an input to the ac pad?s differential amplifier. figure 2-71 ? analog quad current monitor configuration prescaler prescaler prescaler analog quad av ac at voltage monitor block current monitor block ag power digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
analog block v2.0 2-91 to initiate a current measuremen t, the appropriate curr ent monitor strobe (c mstb) signal on the ab macro must be asserted low for at least t cmslo in order to discharge the previous measurement. then cmstb must be assert ed high for at least t cmset prior to asserting the adcstart signal. the cmstb must remain high un til after the sample signal is de-ass erted by the ab macro. note that the minimum sample time cannot be less than t cmshi . figure 2-72 shows the timing diagram of cmstb in relationship with the adc con trol signals. figure 2-73 illustrates positive current monitor operation. the differen tial voltage between av and ac goes into the 10 amplifier and is then conve rted by the adc. for exampl e, a current of 1.5 a is drawn from a 10 v supply an d is measured by the voltage drop across a 0.050 sense resistor, the voltage drop is amplified by ten times by the am plifier and then measured by the adc. the 1.5 a current creates a differential vo ltage across the sense resistor of 75 mv. this becomes 750 mv after amplification. thus, the adc meas ures a current of 1.5 a as 7 50 mv. using an adc with 8-bit resolution and varef of 2.56 v, the adc result is decimal 75. eq 2-3 shows how to compute the current from the adc result. eq 2-3 where i is the current flowing th rough the sense resistor adc is the result from the adc varef is the reference voltage n is the number of bits rsense is the resistance of the sense resistor figure 2-72 ? timing diagram for current monitor strobe v adc t cmset cmstbx adcstart can be asserted after this point to start adc sampling. t cmshi adcstart t cmslo i adc v aref () 10 2 n r sense () ? =
fusion family of mi xed-signal flash fpgas device architecture 2-92 v2.0 care must be taken when choosi ng the right re sistor for current measur ement application. note that because of the 10 amplification, the maxi mum measurable difference between the av and ac pads is v aref / 10. a larger av-to-ac voltage drop will result in adc saturation; that is, the digital code put out by the adc will stay fixed at the full scale value. therefore, the user must select the external sense resistor appropriately. table 2-38 shows recommended resistor values for different current measurement range s. when choo sing resistor values for a system, there is a trade- off between measurement accuracy and power co nsumption. choosing a large resistor will increase the voltage drop and he nce increase accuracy of the measurement; however the larger voltage drop dissipate s more power (p = i 2 r). the current monitor is a unipolar system, meaning that the diff erential voltage swing must be from 0 v to v aref /10. therefore, the current monitor only supports differential voltage where |v av -v ac | is greater than 0 v. this results in the re quirement that the potent ial of the av pad must be larger than the potential of the ac pad. this is straightforward for positive voltage systems. for a negative voltage system, it means that the av pad must be "more negative" than the ac pad. this is shown in figure 2-74 . in this case, both the av pad and the ac pad are configured for negati ve operations and the output of the differen tial amplifier still falls between 0 v and v aref as required . figure 2-73 ? positive current monitor 0-12 v r sense i acx avx cmstbx 10 x current monitor v adc to analog mux (refer table 2-36 for mux channel number)
analog block v2.0 2-93 terminology accuracy the accuracy of fusion current monitor is 2 mv minimum plus 5% of the differential voltage at the input. the input accuracy can be transla ted to error at the adc output by using eq 2-4 . the 10 v/v gain is the gain of the current monitor circuit, as described in the "current monitor" section on page 2-90 . for 8-bit mode, n = 8, v aref = 2.56 v, zero differential voltage between av and ac, the error ( e adc ) is equal to 2 lsbs. eq 2-4 where n is the number of bits v aref is the reference voltage v av is the voltage at av pad v ac is the voltage at ac pad table 2-37 ? recommended resistor for differe nt current range measurement current range recommended minimum resistor value (ohms) > 5 ma ? 10 ma 10 ? 20 > 10 ma ? 20 ma 5 ? 10 > 20 ma ? 50 ma 2.5 ? 5 > 50 ma ? 100 ma 1 ? 2 > 100 ma ? 200 ma 0.5 ? 1 > 200 ma ? 500 ma 0.3 ? 0.5 > 500 ma ? 1 a 0.1 ? 0.2 > 1 a ? 2 a 0.05 ? 0.1 > 2 a ? 4 a 0.025 ? 0.05 > 4 a ? 8 a 0.0125 ? 0.025 > 8 a ? 12 a 0.00625 ? 0.02 figure 2-74 ? negative current monitor i r sense 0 to ?10.5 v avx acx cmstbx 10 x v adc current monitor to analog mux (refer table 2-36 for mux channel number) e adc 2 mv 0.05 v av v ac ? + () 10 v () v ? 2 n v aref -------------- - =
fusion family of mi xed-signal flash fpgas device architecture 2-94 v2.0 gate driver the fusion analog quad includes a gate driver connected to the quad's ag pin ( figure 2-75 ). designed to work with external p- or n-channel mosfets, the gate driver is a configurable current sink or source and requires an external pull-up or pull-down resi stor. the ag supports 4 selectable gate drive levels: 1 a, 3 a, 10 a, and 30 a ( figure 2-76 on page 2-95 ). the ag also supports a high current drive mode in which it can sink 20 ma; in this mode the switching rate is approximately 1.3 mhz with 100 ns turn-on time and 600 ns turn-off time. modeled on an open- drain-style output, it does not output a voltage level without an appropriate pull-up or pull-down resistor. if 1 v is forced on the drain, the current sinking/sourcing will exceed the ability of the transistor, and the device could be damaged. the ag pad is turned on via the corresponding gdon x pin in the analog block macro, where x is the number of the corresp onding analog quad for the ag pad to be enabled (gdon0 to gdon9). the gate-to-source voltage (v gs ) of the external mosfet is li mited to the programmable drive current times the external pull-up or pull-down resistor value ( eq 2-5 ). v gs i g (r pullup or r pulldown ) eq 2-5 the rate at which the gate volt age of the external mosfet slews is determined by the current, i g , sourced or sunk by the ag pin and the gate-to-source capacitance, c gs , of the external mosfet. as an approximation, the slew rate is given by eq 2-6 . dv/dt = i g / c gs eq 2-6 figure 2-75 ? gate driver analog quad av ac at voltage monitor block current monitor block ag power line side load side digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip r pullup from fpga (gdonx) prescaler prescaler prescaler
analog block v2.0 2-95 c gs is not a fixed capacitance but, depending on th e circuitry connected to its drain terminal, can vary significantly during the course of a turn-on or turn-o ff transient. thus, eq 2-6 on page 2-94 can only be used for a first-order estimate of the switching speed of the external mosfet. figure 2-76 ? gate driver example ag high current high current 1 a 3 a 10 a 30 a 1 a 3 a 10 a 30 a
fusion family of mi xed-signal flash fpgas device architecture 2-96 v2.0 temperature monitor the final pin in the analog quad is the analog temperature (at) pin. the at pin is used to implement an accurate temperature monitor in conjunction with an external diode-connected bipolar transistor ( figure 2-77 ). for improved temperature measurement accuracy, it is important to use the atrtn pin for the retu rn path of the current sourced by the at pin. each atrtn pin is shared between two ad jacent analog quads. additionally, if not used for temp erature monitoring, the at pin can provide functionality similar to that of the av pad. however, in this mode only positive voltages can be applied to the at pin, and only two pr escaler factors are available (16 v and 4 v ranges?refer to table 2-54 on page 2-131 ). figure 2-77 ? temperature monitor quad analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx) prescaler prescaler prescaler atrtn discrete bipolar transistor
analog block v2.0 2-97 fusion uses a remote diode as a temperature sensor. the fusion temp erature monitor uses a differential input; the at pin and atrtn (at return) pin are the diff erential inputs to the temperature monitor. there is one temperature mo nitor in each quad. a simplified block diagram is shown in figure 2-78 . the fusion approach to measurin g temperature is forcing two diff erent currents th rough the diode with a ratio of 10:1. the switch that contro ls the different currents is controlled by the temperature monitor strobe sign al, tmstb. setting tmstb to '1 ' will initiate a temperature reading. the tmstb should remain '1' until th e adc finishes sampling the vo ltage from the temperature monitor. the minimum sample time for the temperature moni tor cannot be less than the minimum strobe high ti me minus the setup time. figure 2-79 shows the timing diagram. the diode?s voltage is measured at each current level and the temperature is calculated based on eq 2-7 . eq 2-7 where i tmslo is the current when the temperature strobe is low, typically 100 a i tmshi is the current when the temperat ure strobe is high, typically 10 a figure 2-78 ? block diagram for tempera ture monito r circuit figure 2-79 ? timing diagram for the temperature monitor strobe signal tmstbx vdd33a atrtnxy atx 12.5 x ? v to analog mux (refer table 2-36 for mux channel number) v adc 100 a 10 a + ? + ? v adc tmstbx adc should start sampling at this point adcstart t tmslo t tmshi t tmsset v tmslo v tmshi ? n kt q ----- - ln i tmslo i tmshi --------------- ?? ?? =
fusion family of mi xed-signal flash fpgas device architecture 2-98 v2.0 v tmslo is diode voltage while temperature strobe is low v tmshi is diode voltage while temperature strobe is high n is the non-ideality factor of the diode-connecte d transistor. it is typically 1.004 for the actel- recommended transistor type 2n3904. k = 1.3806 x 10 -23 j/k is the boltzman constant q = 1.602 x 10 -19 c is the charge of a proton when i tmslo / i tmshi = 10, the equation can be simplified as shown in eq 2-8 . eq 2-8 in the fusion tmb, the ideality factor n for 2n3904 is 1.004 and v is amplified 12.5 times by an internal amplifier; hence the voltage be fore entering the adc is as given in eq 2-9 . eq 2-9 this means the temperature to vo ltage relationship is 2.5 mv per degree kelvin. the unique design of fusion has made the temperature monitor sys tem simple for the user. when the 10-bit mode adc is used, each lsb represents 1 degree kelvin, as shown in eq 2-10 . that is, e. 25c is equal to 293k and is represented by decimal 293 counts from the adc. eq 2-10 if 8-bit mode is used for the adc resolution, eac h lsb represents 4 degrees kelvin; however, the resolution remains as 1 degree kelvin per lsb , even for 12-bit mode, due to the temperature monitor design. an example of the temperature data format for 10-bit mode is shown in table 2-38 . terminology resolution resolution defines the sma llest temperature change fusion te mperature monitor can resolve. for adc configured as 8-bit mode, each lsb represents 4c, and 1c per lsb for 10-bit mode. with 12- bit mode, the temperature monitor can still only resolve 1c due to temp erature monitor design. offset the fusion temperature monitor has a systematic offset of +5c, excluding error due board resistance and ideality factor of the external diod e, between the operation range of ?40c to +85c. for instance, 25c will be read by the temp erature monitor as 30c pl us error. the user can remove any offset error thr ough hardware or software du ring the calibration routine. table 2-38 ? temperature data format temperature temperature (k) digital output (adc 10-bit mode) ?40c 233 00 1110 1001 ?20c 253 00 1111 1101 0c 273 01 0001 0001 1c 274 01 0001 0010 10 c 283 01 0001 1011 25c 298 01 0010 1010 50 c 323 01 0100 0011 85 c 358 01 0110 0110 vv tmslo v tmshi ? 1.986 10 4 ? nt == v adc v 12.5 2.5 mv kt () ? == 1 k 2.5 mv 2 10 2.56 v ---------------- - 1 lsb ==
analog block v2.0 2-99 analog-to-digital converter block at the heart of the fusi on analog system is a programmable successive approximation register (sar) adc. the adc can support 8-, 10-, or 12-bit modes of operation. in 12-bit mode, the adc can resolve 500 ksps. all results are msb-justified in the adc. the input to the adc is a large 32:1 analog input multiplexer. a simplified block diagram of the analog quads, analog input multiplexer, and adc is shown in figure 2-80 . the adc offers multiple self-calibrating modes to ensure consistent high performance both at power-up and during runtime. figure 2-80 ? adc block diagram adc 12 analog mux (32 to 1) temperature monitor pads internal diode digital output to fpga av0 ac0 ag0 at0 av1 ac1 ag1 at1 av2 ac2 ag2 at2 av3 ac3 ag3 at3 av4 ac4 ag4 at4 av5 ac5 ag5 at5 av6 ac6 ag6 at6 av7 ac7 ag7 at7 av8 ac8 ag8 at8 av9 ac9 ag9 at9 atreturn89 atreturn67 atreturn45 atreturn23 atreturn01 analog quad 0 analog quad 4 analog quad 5 analog quad 6 analog quad 7 analog quad 8 analog quad 9 analog quad 3 analog quad 2 analog quad 1 v cc (1.5 v) 0 1 31 these are hardwired connections within analog quad. chnumber[4:0]
fusion family of mi xed-signal flash fpgas device architecture 2-100 v2.0 adc input multiplexer at the input to the fusion adc is a 32:1 multiplexer. of the 32 input channels, up to 30 are user definable. two of these channels are hardwire d internally. channel 31 connects to an internal temperature diode so the temperature of the fusion device itself can be monitored. channel 0 is wired to the fpga?s 1.5 v v cc supply, enabling the fusion device to monitor its own power supply. doing this internally makes it unnecessary to use an analog i/ o to support these functions. the balance of the mux inputs are conn ected to analog quads (see the "analog quad" section on page 2-84 ). table 2-39 defines which analog quad inputs are associated with which specific analog mux channels. the number of anal og quads present is de vice-dependent; refer to the family list in the "fusion family" table on page i of this datasheet for the number of quads per device. regardless of the number of quads populated in a device, the internal connections to both v cc and the internal temperature diode remain on channels 0 and 31, respectively. to sample the internal temperature monitor, it must be strobed (similar to the at pads). the tmstbint pin on the analog block macro is the control for strobing th e internal temperature measurement diode. to determine which channel is sele cted for conversion, there is a five-pin interface on the analog block, chnumber[4:0], defined in table 2-40 on page 2-101 . table 2-39 shows the correlation between the analog mux input channels and the analog input pins. table 2-39 ? analog mux channels analog mux channel signal analog quad number 0 vcc_analog 1 av0 analog quad 0 2ac0 3at0 4 av1 analog quad 1 5ac1 6at1 7 av2 analog quad 2 8ac2 9at2 10 av3 analog quad 3 11 ac3 12 at3 13 av4 analog quad 4 14 ac4 15 at4 16 av5 analog quad 5 17 ac5 18 at5 19 av6 analog quad 6 20 ac6 21 at6
analog block v2.0 2-101 22 av7 analog quad 7 23 ac7 24 at7 25 av8 analog quad 8 26 ac8 27 at8 28 av9 analog quad 9 29 ac9 30 at9 31 internal temperature monitor table 2-40 ? channel selection channel number chnumber[4:0] 0 00000 1 00001 2 00010 3 00011 . . . . . . 30 11110 31 11111 table 2-39 ? analog mux channels (continued) analog mux channel signal analog quad number
fusion family of mi xed-signal flash fpgas device architecture 2-102 v2.0 adc description the actel fusion adc is a 12-bit sar adc. it offers a wide variet y of features for different use models. figure 2-81 shows a block diagram of the fusion adc. ? configurable resolution: 8-bit, 10-bit, and 12-bit mode ? dnl: 0.6 lsb for 10-bit mode ? inl: 0.4 lsb for 10-bit mode ? no missing code ? internal varef = 2.56 v ? maximum sample rate = 600 ksps ? power-up calibration and dynamic calibration after every sample to compensate for temperature drift over time adc configuratio n description the fusion adc can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion, and dynamic calibration. this is controlled by mode[3:0], as defined in table 2-41 on page 2-103 . the output of the adc is the result[11:0] si gnal. in 8-bit mode, th e most significant 8 bits result[11:4] are used as the adc value and the least significant 4 bi ts result[3:0] are logical '0's. in 10-bit mode, result[11:2] are used the adc value and result[1:0] are logical '0's. figure 2-81 ? adc simplified block diagram tvc sysclk adcclk signals from analog quads chnumber sar adc stc mode result datavalid busy status sample calibrate varef analog mux 32 12
analog block v2.0 2-103 the speed of the adc depends on its internal cloc k, adcclk, which is not accessible to users. the adcclk is derived from sysclk. input signal tvc[7:0], time divider control, determines the speed of the adcclk in relationship to sysclk, based on eq 2-11 . eq 2-11 tvc: time divider control (0?255) t adcclk is the period of adcclk, and must be between 0.5 mhz and 10 mhz t sysclk is the period of sysclk the frequency of adcclk, f adcclk , must be within 0.5 hz to 10 mhz. the inputs to the adc are synchronized to sysc lk. a conversion is init iated by asserting the adcstart signal on a rising edge of sysclk. figure 2-83 on page 2-107 and figure 2-84 on page 2-108 show the timing diagram for the adc. a conversion is performed in three phases. in the first phase, the analog input voltage is sampled on the input capacitor. this phase is called sa mple phase. during the sample phase, the output signals busy and sample change from '0' to '1', indicating the adc is busy and sampling the analog signal. the sample time can be controlled by input signals stc[7:0]. the sample time can be calculated by eq 2-12 . when controlling the sample time for the adc along with the use of prescaler or current monitor or temperature moni tor, the minimum sample time for each must be obeyed. refer to the co rresponding section and table 2-43 for further information. eq 2-12 stc: sample time co ntrol value (0?255) t sample is the sample time sample time is computed ba sed on the period of adcclk. the second phase is called the distribution phase. during distribution phase, the adc computes the equivalent digital value from the value stored in the input capacito r. in this phase, the output table 2-41 ? mode bits function name bits function mode 3 0 ? internal calibration after ever y conversion; two adcclk cycles are used after the conversion. 1 ? no calibration after every conversion mode 2 0 ? power-down after conversion 1 ? no power-down after conversion mode 1:0 00 ? 10-bit 01 ? 12-bit 10 ? 8-bit 11 ? unused table 2-42 ? tvc bits function name bits function tvc [7:0] sysclk divider control table 2-43 ? stc bits function name bits function stc [7:0] sample time control t adcclk 4 1 tvc + () t sysclk = t sample 2 stc + () t adcclk =
fusion family of mi xed-signal flash fpgas device architecture 2-104 v2.0 signal sample goes back to '0', indicating the sample is comple ted; but the busy signal remains '1', indicating the adc is still busy for distribu tion. the distribution time depends strictly on the number of bits. if the adc is configured as a 10-bit adc, then 10 adc clk cycles are needed. eq 2-13 describes the distribution time. eq 2-13 n: number of bits the last phase is the post-calibratio n phase. this is an optional phase. the post-calibration phase takes two adcclk cycles. the output busy signal will remain '1' un til the post-calibration phase is completed. if the post-calibrati on phase is skipped, then the busy signal goes to '0' after distribution phase. as soon as busy signal goes to '0', the datavalid signal goes to '1', indicating the digital result is available on the result output signals. data vaild will remain '1' until the next adcstart is asserted. actel recommends enab ling post-calibration to compensate for drift and temperature-dependent effects. this ensures that the adc remains consistent over time and with temperature. the post-calibration phase is enabled by bit 3 of the mode register. eq 2-14 describes the post-calibration time. eq 2-14 mode[3]: bit 3 of the mode register, described in table 2-41 on page 2-103 . the calculation for the conversion time for the adc is summarized in eq 2-15 . t conv = t sync_read + t sample + t distrib + t post-cal + t sync_write eq 2-15 t conv : conversion time t sync_read : maximum time for a signal to synchronize with sysclk. for calculation purposes, the worst case is a period of sysclk, t sysclk . t sample : sample time t distrib : distribution time t post-cal : post-calibration time t sync_write : maximum time for a signal to synchronize with sysclk. for calc ulation purposes, the worst case is a period of sysclk, t sysclk . example this example shows how to choose the correct settin gs to achieve the fastest sample time in 10-bit mode for a system that runs at 66 mhz. the period of sysclk: t sysclk = 1/66 mhz = 0.015 s choosing tvc between 1 and 33 will meet th e maximum and minimum period for the adcclk requirement. a higher tvc lead s to a higher adcclk period. the minimum tvc is chosen so that t distrib and t post-cal can be run faster. the period of adcclk with a tvc of 1 can be computed by eq 2-16 . eq 2-16 from table 2-47 on page 2-121 , minimum conver sion for 10-bit mode is 1.8 s. to compute stc, the calculation will first compute the po st-calibration time, second the di stribution time, and finally the stc setting. t distrib nt adcclk = t post-cal mode 3 [] 2t adcclk () = t adcclk 4 1 tvc + () t sysclk 411 + () 0.015 s 0.12 s ===
analog block v2.0 2-105 since actel recommends post-calibr ation for temperature drift over time, post-calibration shall be enabled and the post-calibration time, t post-cal , can be computed by eq 2-17 . the post-calibration time is 0.24 s. eq 2-17 the distribution time, t distrib , is equal to 1.2 s and can be computed using eq 2-18 . eq 2-18 the stc value can now be computed through eq 2-19 . the sample time is equal to 0.32 s. by rearranging eq 2-12 on page 2-103 with a t sample of 0.35 s, the stc can be computed. t sample = t conv ? t post-cal ? t distrib ? t sync_read ? t sync_write = 1.8 s ? 0.24 s ? 1.2 s ? 0.15 s ? 0.15 s = 0.32 s eq 2-19 and so, stc will be rounded up to 3 to ensure the minimum conversion time is met. the sample time, t sample , with an stc of 3, is now equal to 0.36 s. the total sample time, using eq 2-20 , can now be summated. t sync_read + t sample + t distrib + t post-cal + tsync_write = 0.015 s + 0.36 s + 1.2 s + 0.24 s + 0.015 s = 1.85 s eq 2-20 the optimal setting for the system running at 66 mhz with an adc fo r 10-bit mode chosen is listed as follows: *note that no power-down after ever y conversion is chosen in this case; however, if the application is power-sensitive, the mode[2] ca n be set to '0', as described abov e, and it will not affect any performance. integrated voltage reference the fusion device has an integrat ed on-chip 2.56 v reference voltag e for the adc. the value of this reference voltage was chosen to make the presca ling and postscaling fa ctors for the prescaler blocks change in a binary fashion. however, if de sired, an external refere nce voltage of up to 3.3 v can be connected between the va ref and gndref pins. the varefsel control pin is used to select the reference voltage. tvc[7:0] = 1 = 0x01 stc[7:0] = 3 = 0x03 mode[3:0] = b'0100 = 0x4* table 2-44 ? varef bit function name bit function varef 0 reference voltage selection 0 ? internal voltage reference selected. varef pin outputs 2.56 v. 1 ? input external voltage re ference from varef and gndref t post-cal 2t adcclk 0.24 s == t distrib nt adcclk 10 0.12 1.2 s === stc t sample t adcclk ------------------- 2 ? 0.35 s 0.12 s ------------------ - 2 ? 2.85 ===
fusion family of mi xed-signal flash fpgas device architecture 2-106 v2.0 adc operation description the adc can be powered down independently of the fpga core, as an additional control or for power-saving considerations, via the pwrdwn pin of the analog block. the pwrdwn pin controls only the comparat ors in the adc. once the adc has powered up and been released from reset, adcreset, the adc will initiate a calibration routine designed to provide optimal adc performance. the fusi on adc offers a robust calibration scheme to reduce integrated offset an d linearity errors. the offset and linearity errors of the main capacitor array are compensated for with an 8-bit calibration capacitor array. the offset/linearity error calibration is carried out in two ways. first, a power-up calibration is carried out when the adc comes ou t of reset. this is initiated by the calibrate output of the analog block macro and is a fixed number of adc_c lk cycles (3,840 cy cles), as shown in figure 2-82 on page 2-107 . in this mode, the linearity and offset errors of the capacitors are calibrated. to further compensate for drift and temperature- dependent effects, every conversion is followed by post-calibration of either the offset or a bi t of the main capacitor array. the post-calibration ensures that, over time and with temp erature, the adc remains consistent. after both calibration and the se tting of the appropriate configur ations, as explai ned above, the adc is ready for operation. settin g the adcstart signal high for on e clock period will initiate the sample and conversion of the an alog signal on the channel as configured by chnumber[4:0]. the status signals sample and busy will show wh en the adc is sampling and converting ( figure 2-84 on page 2-108 ). both sample and busy will initially go high. after the adc has sampled and held the analog signal, sample will go low. after the entire operat ion has completed and the analog signal is converted, busy will go low and datavalid will go high. this indicates that the digital result is available on the result[11:0] pins. datavalid will remain high until a subsequent adc_start is issued. the datavalid goes low on the rising edge of sysclk as shown in figure 2-83 on page 2-107 . the result signals will be kept constant until the adc fi nishes the subsequent sample. the next sampled result will be available when datavalid goes high again. it is ideal to read the result when datavalid is '1'. the result is latched and remains unchanged until the next datavlaid rising edge. intra-conversion performing a conversion during power-up, calibration is possible but should be avoided, since the performance is not guaranteed, as shown in table 2-46 on page 2-118 . this is described as intra- conversion. figure 2-85 on page 2-108 shows intra-conversion (conve rsion that starts before a conversion is finished). injected conversion a conversion can be interrupted by another conversi on. before the current co nversion is finished, a second conversion can be started by issuing a pulse on signal adcstart. when a second conversion is issued be fore the current conversi on is completed, the current conversion would be dropped and the adc would start the second conversion on the rising edge of the sysclk. this is known as injected conversion. since the adc is synchronous, the minimum time to issue a second conversion is two clock cycles of sysclk after the previous one. figure 2-86 on page 2-109 shows injected conversion (conversion th at starts during the power-up calibration). the total time for calibration still remain s 3,840 adcclk cycles.
analog block v2.0 2-107 timing diagram note: *refer to eq 2-11 on page 2-103 for the calculation on the period of adcclk, t adcclk . figure 2-82 ? power-up calibration stat us signal timing diagram figure 2-83 ? input setup time sysclk adcreset calibrate t remclr t ck2qcal t ck2qcal tvc[7:0] t sutvc t hdtvc t cal = 3,840 t adcclk * t recclr sysclk adcstart t minsysclk t mpwsysclk t hdadcstart t suadcstart mode[3:0] tvc[7:0] stc[7:0] varef chnumber[7:0] t sumode t sutvc t sustc t suchnum t suvarefsel t hdmode t hdtvc t hdstc t hdvarefsel t hdchnum
fusion family of mi xed-signal flash fpgas device architecture 2-108 v2.0 notes: 1. refer to eq 2-12 on page 2-103 for the calculation on the sample time, t sample . 2. see eq 2-20 on page 2-105 for calculation on the conversion time, t conv . 3. minimum time to issue an adcstart after datavalid is 1 sysclk period figure 2-84 ? standard conversion status signal timing diagram note: *t conv represents the conversion time of the second conversion. see eq 2-10 on page 2-98 for calculation of the conversion time, t conv . figure 2-85 ? intra-conversion timing diagram s y sc lk ad cs tart bu s y s ample datavalid t hdad cs tart t s uad cs tart t c k2qbu s y t c k2q s ample t c k2qval t s ample 1 t c onv 2 ad c _ re s ult[11: 0] t c lk2re s ult 1 st s ample result t c k2qval 2 n d s ample result t data2 s tart 3 s y sc lk ad cs tart bu s y s ample datavalid t c k2q s ample t c k2qval t c onv * 1st c onversion 1st s tart 2n d s tart 1st c onversion c an c elle d , 2n d c onversion t c k2qval t c k2qbu s y t c k2q s ample
analog block v2.0 2-109 note: * see eq 2-10 on page 2-98 for calculation on the conversion time, t conv . figure 2-86 ? injected-conversio n timing diagram s y sc lk ad cs tart bu s y s ample datavalid t c k2q s ample t c k2q s ample t c k2qval t c onv * t c lr2qval t c k2qbu s y ad c re s et c alibrate t c k2q c al t c k2q c al interrupts power-up c ali b ration resumes power-up c ali b ration
fusion family of mi xed-signal flash fpgas device architecture 2-110 v2.0 adc interface timing table 2-45 ? adc interface timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t sumode mode pin setup time 0.56 0.64 0.75 ns t hdmode mode pin hold time 0.26 0.29 0.34 ns t sutvc clock divide control (tvc) setup time 0.68 0.77 0.90 ns t hdtvc clock divide control (tvc) hold time 0.32 0.36 0.43 ns t sustc sample time control (stc) setup time 1.58 1.79 2.11 ns t hdstc sample time control (stc) hold time 1.27 1.45 1.71 ns t suvarefsel voltage reference select (varefsel) setup time 0.00 0.00 0.00 ns t hdvarefsel voltage reference select (varefsel) hold time 0.67 0.76 0.89 ns t suchnum channel select (chnumber) setup time 0.90 1.03 1.21 ns t hdchnum channel select (chnumber) hold time 0.00 0.00 0.00 ns t suadcstart start of conversion (adcstart) setup time 0.75 0.85 1.00 ns t hdadcstart start of conversion (adcstart) hold time 0.43 0.49 0.57 ns t ck2qbusy busy clock-to-q 1.33 1.51 1.78 ns t ck2qcal power-up calibration clock-to-q 0.63 0.71 0.84 ns t ck2qval valid conversion result cl ock-to-q 3.12 3.55 4.17 ns t ck2qsample sample clock-to-q 0.22 0.25 0.30 ns t ck2qresult conversion result clock-to-q 2.53 2.89 3.39 ns t clr2qbusy busy clear-to-q 2.06 2.35 2.76 ns t clr2qcal power-up calibration clea r-to-q 2.15 2.45 2.88 ns t clr2qval valid conversion result clear-to-q 2.41 2.74 3.22 ns t clr2qsample sample clear-to-q 2.17 2.48 2.91 ns t clr2qresult conversion result clear-to-q 2.25 2.56 3.01 ns t recclr recovery time of clear 0.00 0.00 0.00 ns t remclr removal time of clear 0.63 0.72 0.84 ns t mpwsysclk clock minimum pulse width for the adc 4.00 4.00 4.00 ns t fmaxsysclk clock maximum frequency for the adc 100.00 100.00 100.00 mhz
analog block v2.0 2-111 terminology conversion time conversion time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one lsb of a new input value. dnl ? differential non-linearity for an ideal adc, the analog-input levels that trigger any two succes sive output codes should differ by one lsb (dnl = 0). any deviation from one lsb in defined as dnl ( figure 2-87 ). enob ? effective number of bits enob specifies the dynamic perfo rmance of an adc at a specific input frequency and sampling rate. an ideal adc?s error consists only of quanti zation of noise. as the input frequency increases, the overall noise (particularly in the distortion compon ents) also increases, thereby reducing the enob and sinad (also see ?signa l-to-noise and distorti on ratio (sinad)?.) enob for a full-scale, sinusoidal inpu t waveform is computed using eq 2-21 . eq 2-21 fs error ? full-scale error full-scale error is the difference between the actual value that trig gers that transition to full-scale and the ideal analog full-scale trans ition value. full-scale error equa ls offset error plus gain error. figure 2-87 ? differential non-linearity (dnl) adc output code input voltage to prescaler error = ?0.5 lsb error = +1 lsb ideal output actual output enob sinad 1.76 ? 6.02 ---------------------------------- - =
fusion family of mi xed-signal flash fpgas device architecture 2-112 v2.0 gain error the gain error of an adc indicates how well the sl ope of an actual transf er function matches the slope of the ideal transfer function. gain error is usually expressed in lsb or as a percent of full- scale (%fsr). gain error is the full-scale error minus the offset error ( figure 2-88 ). gain error drift gain-error drift is the variation in gain error du e to a change in ambien t temperature, typically expressed in ppm/c. figure 2-88 ? gain error adc output code input voltage to prescaler ideal output actual output gain = 2 lsb 1...11 0...00 fs voltage
analog block v2.0 2-113 inl ? integral non-linearity inl is the deviation of an actual transfer function from a straight line. after nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the end points of the transfer function ( figure 2-89 ). lsb ? least significant bit in a binary number, the lsb is the least weighted bit in the group. typically, the lsb is the furthest right bit. for an adc, the weight of an lsb equals the full-scale voltage range of the converter divided by 2 n , where n is the converter?s resolution. eq 2-22 shows the calculation for a 10-bit adc wi th a unipolar full-scale voltage of 2.56 v: 1 lsb = (2.56 v / 2 10 ) = 2.5 mv eq 2-22 no missing codes an adc has no missing codes if it produces all po ssible digital codes in re sponse to a ramp signal applied to the analog input. offset error offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. for an ideal adc, th e first transition occurs at 0.5 lsb above zero. the offset voltage is measured by applying an analog input such that the adc outputs all zeroes and increases until the first transition occurs ( figure 2-90 ). figure 2-89 ? integral non-linearity (inl) adc output code input voltage to prescaler in l = +0.5 lsb in l = +1 lsb ideal output actual output
fusion family of mi xed-signal flash fpgas device architecture 2-114 v2.0 resolution adc resolution is the number of bits used to represent an analog input signal. to more accurately replicate the analog signal, reso lution needs to be increased. sampling rate sampling rate or sample frequency, specified in samples per second (sps), is the rate at which an adc acquires (samples ) the analog input. snr ? signal-to-noise ratio snr is the ratio of the amplitude of the desired si gnal to the amplitude of the noise signals at a given point in time. for a waveform perfectly reco nstructed from digital samples, the theoretical maximum snr ( eq 2-23 ) is the ratio of the full-scale an alog input (rms value) to the rms quantization error (res idual error). the ideal, theoretical minimum adc noise is caused by quantization erro r only and results directly from the adc?s resolution (n bits): eq 2-23 sinad ? signal-to-noise and distortion sinad is the ratio of the rms amplitude to the m ean value of the root-sum-square of the all other spectral components, in cluding harmonics, but excluding dc. sinad is a good indication of the overall dynamic performance of an adc because it includes all compon ents which make up noise and distortion. total harmonic distortion thd measures the distortion content of a signal, and is specified in decibels relative to the carrier (dbc). thd is the ratio of the rms sum of the selected harmonics of th e input signal to the fundamental itself. only harmonics within the nyquist limit are includ ed in the measurement. tue ? total unadjusted error figure 2-90 ? offset error adc output code input voltage to prescaler ideal output offset error = 1.5 lsb actual output 0...00 0...01 snr db[max] 6.02 db n 1.76 db + =
analog block v2.0 2-115 tue is a comprehensive specification that includes linearity errors, gain error, and offset error. it is the worst-case deviation from the ideal device performance. tue is a static specification ( figure 2-91 ). figure 2-91 ? total unadjusted error (tue) adc output code input voltage to prescaler ideal output t u e = 0.5 lsb
fusion family of mi xed-signal flash fpgas device architecture 2-116 v2.0 typical performance characteristics figure 2-92 ? temperature error figure 2-93 ? effect of external sensor capacitance 0 0.5 1 1.5 2 2.5 3 3.5 ?40 10 6 0 110 temperature errror vs. die temperature temperature error ( c ) temperature ( c ) temperature error vs. inter c onne c t c apa c itan c e -7 - 6 -5 -4 -3 -2 -1 0 1 0 500 1000 1500 2000 c apa c itan c e (pf ) temperature error ( c )
analog block v2.0 2-117 figure 2-94 ? temperature readin g noise when averaging is used 0 2 4 6 8 10 12 temperature rea d in g noise rm s vs. avera g in g num b er of avera g es noise rm s ( c ) 1 10 100 1000 10000
fusion family of mi xed-signal flash fpgas device architecture 2-118 v2.0 analog system characteristics table 2-46 ? analog channel specifications commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: v cc33a = 3.3 v, v cc = 1.5 v parameter description condition min. typ. max. units voltage monitor using analog pads av, ac and at (using prescaler) input voltage (prescaler) refer to table 3-2 on page 3-3 v inap uncalibrated gain and offset errors refer to table 2-48 on page 2-123 calibrated gain and offset errors refer to table 2-49 on page 2-124 bandwidth1 100 khz input resistance refer to table 3-3 on page 3-4 scaling factor pr escaler modes ( table 2-54 on page 2-131 ) sample time 10 s current monitor using analog pads av and ac v rsm 1 maximum differential input voltage varef / 10 mv resolution refer to "current monitor" section common mode range ? 10.5 to +12 v cmrr common mode rejection ratio dc ? 1 khz 60 db 1 khz - 10 khz 50 db > 10 khz 30 db t cmshi strobe high time adc conv. time 200 s t cmshi strobe low time 5 s t cmshi settling time 0.02 s accuracy input differential voltage > 50 mv ?2 ?(0.05 x v rsm ) to +2 + (0.05 x v rsm ) mv notes: 1. v rsm is the maximum voltage drop ac ross the current sense resistor. 2. analog inputs used as digital inpu ts can tolerate the same voltage limi ts as the corresponding analog pad. there is no reliability concern on digital inputs as long as v ind does not exceed these limits. 3. v ind is limited to v cc33a + 0.2 to allow reaching 10 mhz input frequency. 4. an averaging of 1,024 samples (lpf setting in analog system builder) is required and the maximum capacitance allowed across the at pins is 500 pf. 5. the temperature offset is a fixed positive value. 6. the high current mode has a maxi mum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 7. when using smartgen analog system builder, calibip is required to ob tain 0 offset. for further details on calibip, refer to the temperature, voltage, and curren t calibration in fusion fpgas application note.
analog block v2.0 2-119 temperature monitor using analog pad at external temperature monitor (external diode 2n3904, t j = 25c) 4 resolution 8-bit adc 4 c 10-bit adc 1 c 12-bit adc 0.25 c offset 5 afs090, afs250 5 c afs600, afs1500 uncalibrated 7 11 c afs600, afs1500 calibrated 7 0c accuracy 3 5 c external sensor source current high level, tmstbx = 0 10 a low level, tmstbx = 1 100 a max capacitance on at pad 1.3 nf internal temperature monitor resolution 8-bit adc 4 c 10-bit adc 1 c 12-bit adc 0.25 c offset 5 afs090, afs250 5 c afs600, afs1500 uncalibrated 7 11 c afs600, afs1500 calibrated 7 0c accuracy 3 5 c t tmshi strobe high time 10 105 s t tmslo strobe low time 5 s t tmsset settling time 5 s table 2-46 ? analog channel specifications (continued) commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: v cc33a = 3.3 v, v cc = 1.5 v parameter description condition min. typ. max. units notes: 1. v rsm is the maximum voltage drop ac ross the current sense resistor. 2. analog inputs used as digital inpu ts can tolerate the same voltage limi ts as the corresponding analog pad. there is no reliability concern on digital inputs as long as v ind does not exceed these limits. 3. v ind is limited to v cc33a + 0.2 to allow reaching 10 mhz input frequency. 4. an averaging of 1,024 samples (lpf setting in analog system builder) is required and the maximum capacitance allowed across the at pins is 500 pf. 5. the temperature offset is a fixed positive value. 6. the high current mode has a maxi mum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 7. when using smartgen analog system builder, calibip is required to ob tain 0 offset. for further details on calibip, refer to the temperature, voltage, and curren t calibration in fusion fpgas application note.
fusion family of mi xed-signal flash fpgas device architecture 2-120 v2.0 digital input using analog pads av, ac and at v ind 2,3 input voltage refer to table 3-2 on page 3-3 v hysdin hysteresis 0.3 v v ihdin input high 1.2 v v ildin input low 0.9 v v mpwdin minimum pulse with 50 ns f din maximum freq uency 10 mhz i stbdin input leakage current 2 a i dyndin dynamic current 20 a t indin input delay 10 ns gate driver output using analog pad ag v g voltage range refer to table 3-2 on page 3-3 i g output current drive high current mode 6 at 1.0 v 20 ma low current mode: 1 a 0.8 1.0 1.3 a low current mode: 3 a 2.0 2.7 3.3 a low current mode: 10 a 7.4 9.0 11.5 a low current mode: 30 a 21.0 27.0 32.0 a i offg maximum off current 100 na f g maximum switching rate high current mode 6 at 1.0 v, 1 k resistive load 1.3 mhz low current mode: 1 a, 3 m resistive load 3khz low current mode: 3 a, 1 m resistive load 7khz low current mode: 10 a, 300 k resistive load 25 khz low current mode: 30 a, 105 k resistive load 78 khz table 2-46 ? analog channel specifications (continued) commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: v cc33a = 3.3 v, v cc = 1.5 v parameter description condition min. typ. max. units notes: 1. v rsm is the maximum voltage drop ac ross the current sense resistor. 2. analog inputs used as digital inpu ts can tolerate the same voltage limi ts as the corresponding analog pad. there is no reliability concern on digital inputs as long as v ind does not exceed these limits. 3. v ind is limited to v cc33a + 0.2 to allow reaching 10 mhz input frequency. 4. an averaging of 1,024 samples (lpf setting in analog system builder) is required and the maximum capacitance allowed across the at pins is 500 pf. 5. the temperature offset is a fixed positive value. 6. the high current mode has a maxi mum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 7. when using smartgen analog system builder, calibip is required to ob tain 0 offset. for further details on calibip, refer to the temperature, voltage, and curren t calibration in fusion fpgas application note.
analog block v2.0 2-121 table 2-47 ? adc characteristics in direct input mode commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: v cc33a = 3.3 v, v cc = 1.5 v parameter description condition min. typ. max. units direct input using analog pad av, ac, at v inadc input voltage (direct input) refer to table 3-2 on page 3-3 c inadc input capacitance channel not selected 7 pf channel selected but not sampling 8pf channel selected and sampling 18 pf z inadc input impedance 8-bit mode 2 k 10-bit mode 2 k 12-bit mode 2 k analog reference voltage varef varef accuracy t j = 25c 2.537 2.56 2.583 v temperature drift of internal reference 65 ppm / c external reference 2.527 v cc33a + 0.05 v adc accuracy (using external reference) 1,2 dc accuracy tue total unadjusted error 8-bit mode 0.29 lsb 10-bit mode 0.72 lsb 12-bit mode 1.8 lsb inl integral non-linearity 8-bit mode 0.20 0.25 lsb 10-bit mode 0.32 0.43 lsb 12-bit mode 1.71 1.80 lsb dnl differential non-linearity (no missing code) 8-bit mode 0.20 0.24 lsb 10-bit mode 0.60 0.65 lsb 12-bit mode 2.40 2.48 lsb offset error 8-bit mode 0.01 0.17 lsb 10-bit mode 0.05 0.20 lsb 12-bit mode 0.20 0.40 lsb gain error 8-bit mode 0.0004 0.003 lsb 10-bit mode 0.002 0.011 lsb 12-bit mode 0.007 0.044 lsb gain error (with internal reference) all modes 2 % fsr notes: 1. accuracy of the external reference is 2.56 v 4.6 mv. 2. data is based on characterization. 3. the sample rate is time-sha red among active analog inputs.
fusion family of mi xed-signal flash fpgas device architecture 2-122 v2.0 dynamic performance snr signal-to-noise ratio 8-bit mode 48.0 49.5 db 10-bit mode 58.0 60.0 db 12-bit mode 62.9 64.5 db sinad signal-to-noise distortion 8-bit mode 47.6 49.5 db 10-bit mode 57.4 59.8 db 12-bit mode 62.0 64.2 db thd total harmonic distortion 8-bit mode ?74.4 ?63.0 dbc 10-bit mode ?78.3 ?63.0 dbc 12-bit mode ?77.9 ?64.4 dbc enob effective number of bits 8-bit mode 7.6 7.9 bits 10-bit mode 9.5 9.6 bits 12-bit mode 10.0 10.4 bits conversion rate conversion time 8-bit mode 1.7 s 10-bit mode 1.8 s 12-bit mode 2 s sample rate 8-bit mode 600 ksps 10-bit mode 550 ksps 12-bit mode 500 ksps table 2-47 ? adc characteristics in direct input mode (continued) commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: v cc33a = 3.3 v, v cc = 1.5 v parameter description condition min. typ. max. units notes: 1. accuracy of the external reference is 2.56 v 4.6 mv. 2. data is based on characterization. 3. the sample rate is time-sha red among active analog inputs.
analog block v2.0 2-123 table 2-48 ? uncalibrated analog channel accuracy* worst-case industrial conditions, t j = 85c total channel error (lsb) channel input offset error (lsb) channel input offset error (mv) channel gain error (%fsr) analog pad prescaler range (v) neg. max. med. pos. max. neg max med. pos. max. neg. max. med. pos. max. min. typ. max. positive range adc in 10-bit mode av, ac 16 ?22 ?2 12 ?11 ?2 14 ?169 ?32 224 3 0 ?3 8 ?40 ?5 17 ?11 ?5 21 ?87 ?40 166 2 0 ?4 4 ?45 ?9 24 ?16 ?11 36 ?63 ?43 144 2 0 ?4 2 ?70 ?19 33 ?33 ?20 66 ?66 ?39 131 2 0 ?4 1 ?25 ?7 5 ?11 ?3 26 ?11 ?3 26 3 ?1 ?3 0.5 ?41 ?12 8 ?12 ?7 38 ?6 ?4 19 3 ?1 ?3 0.25 ?53 ?14 19 ?20 ?14 40 ?5 ?3 10 5 0 ?4 0.125 ?89 ?29 24 ?40 ?28 88 ?5 ?4 11 7 0 ?5 at 16 ?3 9 15 ?4 0 4 ?64 5 64 1 0 ?1 4 ?10 2 15 ?11 ?2 11 ?44 ?8 44 1 0 ?1 negative range adc in 10-bit mode av, ac 16 ?35 ?10 9 ?24 ?6 9 ?383 ?96 148 5 ?1 ?6 8 ?65 ?19 12 ?34 ?12 9 ?268 ?99 75 5 ?1 ?5 4 ?86 ?28 21 ?64 ?24 19 ?254 ?96 76 5 ?1 ?6 2 ?136 ?53 37 ?115 ?42 39 ?230 ?83 78 6 ?2 ?7 1 ?98 ?35 8 ?39 ?8 15 ?39 ?8 15 10 ?3 ?10 0.5 ?121 ?46 7 ?54 ?14 18 ?27 ?7 9 10 ?4 ?11 0.25 ?149 ?49 19 ?72 ?16 40 ?18 ?4 10 14 ?4 ?12 0.125 ?188 ?67 38 ?112 ?27 56 ?14 ?3 7 16 ?5 ?14 note: *channel accuracy includes prescaler and adc accuraci es. for 12-bit mode, multiply the lsb count by 4. for 8-bit mode, divide the lsb count by 4. gain remains the same.
fusion family of mi xed-signal flash fpgas device architecture 2-124 v2.0 table 2-49 ? calibrated analog channel accuracy 1,2,3 worst-case industrial conditions, t j = 85c condition total channel error (lsb) analog pad prescaler range (v) input voltage 4 (v) negative max. me dian positive max. positive range adc in 10-bit mode av, ac 16 0.300 to 12.0 ?6 1 6 8 0.250 to 8.00 ?6 0 6 4 0.200 to 4.00 ?7 ?1 7 2 0.150 to 2.00 ?7 0 7 1 0.050 to 1.00 ?6 ?1 6 at 16 0.300 to 16.0 ?5 0 5 4 0.100 to 4.00 ?7 ?1 7 negative range adc in 10-bit mode av, ac 16 ?0.400 to ?10.5 ?7 1 9 8 ?0.350 to ?8.00 ?7 ?1 7 4 ?0.300 to ?4.00 ?7 ?2 9 2 ?0.250 to ?2.00 ?7 ?2 7 1 ?0.050 to ?1.00 ?16 ?1 20 notes: 1. channel accuracy includes prescale r and adc accuracies. for 12-bit mode, multiply the lsb count by 4. for 8-bit mode, divide the lsb count by 4. overall accuracy remains the same. 2. requires enabling analog calibrat ion using smartgen analog system builder. for fu rther details, refer to the temperature, voltage, and curren t calibration in fusion fpgas application note. 3. calibrated with two-point calibration methodology, using 20% and 80% full-scale points. 4. the lower limit of the input voltage is determined by the prescaler input offset.
analog block v2.0 2-125 examples calculating accuracy for an uncalibrated analog channel formula for a given prescaler range, eq 2-24 gives the output voltage. output voltage = (channel output offset in v) + (input voltage x channel gain) eq 2-24 where channel output offset in v = channel output offset in lsbs x equivalent voltage per lsb channel gain factor = 1+ (% channel gain / 100) example input voltage = 5 v chosen prescaler range = 8 v range refer to table 2-48 on page 2-123 . max. output voltage = (max po sitive output offset) + (input voltage x max gain factor) max. positive output offset = (8 ls b) x (8mv per lsb in 10-bit mode) max. positive output offset = 64 mv max. gain = 1 + (2/100) max. gain = 1.02 max. output voltage = (64 mv) + (5 v x 1.02) max. output voltage = 5.164 v table 2-50 ? analog channel accuracy: monitoring standard positive voltages typical conditions, t a = 25c input voltage (v) calibrated typical error per positive prescaler setting 1 (%fsr) direct adc 2,3 (%fsr) 16 v (at) 16 v (12 v) (av/ac) 8 v (av/ac) 4 v (at) 4 v (av/ac) 2 v (av/ac) 1 v (av/ac) varef = 2.56 v 15 1 14 1 12 1 1 5221 3.3 2 2 1 1 1 2.5 3 2 1 1 1 1 1.8 4 4 1 1 1 1 1 1.5 5 5 2 2 2 1 1 1.2 7 6 2 2 2 1 1 0.9 9 9 4 3 3 1 1 1 notes: 1. requires enabling analog calibrat ion using smartgen analog system builder. for fu rther details, refer to the temperature, voltage, and curren t calibration in fusion fpgas application note. 2. direct adc mode using an external varef of 2.56v4.6mv, without analog calibration macro. 3. for input greater than 2.56 v, th e adc output will saturate. a hi gher varef or prescaler usage is recommended.
fusion family of mi xed-signal flash fpgas device architecture 2-126 v2.0 similarly, min. output voltage = (min. negative outp ut offset) + (input voltage x min. gain) = (?136 mv) + (5 v x 0.98) = 4.764 v calculating accuracy for a calibrated analog channel formula for a given prescaler range, eq 2-25 gives the output voltage. output voltage = channel tue in v + input voltage eq 2-25 where channel tue in v = channel tue in lsbs x equivalent voltage per lsb example input voltage = 5 v chosen prescaler range = 8 v range refer to table 2-49 on page 2-124 . max. output voltage = max. ch annel tue in v + input voltage max. channel tue in v = (6 lsb) (8 mv per lsb in 10-bit mode) = 48 mv max. output voltage = 48 mv + 5 v = 5.048 v similarly, min output voltage = min channel tue in v + input voltage = (-48 mv) + 5 v = 4.952 v calculating lsbs from a given error budget formula for a given prescaler range, lsb count = (input voltag e required % error) / (e quivalent voltage per lsb) example input voltage = 5 v required error margin= 1% refer to table 2-49 on page 2-124 . equivalent voltag e per lsb = 16 mv for a 16v prescaler, with adc in 10-bit mode lsb count = (5.0 v 1%) / (0.016) lsb count = 3.125 equivalent voltag e per lsb = 8 mv for an 8 v prescaler, with adc in 10-bit mode lsb count = (5.0 v 1%) / (0.008) lsb count = 6.25 the 8 v prescaler satisfies the calculat ed lsb count accuracy requirement (see table 2-49 on page 2-124 ).
analog configuration mux v2.0 2-127 analog configuration mux the acm is the interface between the fpga, the analog block configurations, and the real-time counter. actel libero ide will generate ip that will load and configure the analog block via the acm. however, users are not limited to using the libero ide ip. this section provides a detailed description of the acm's register map, truth tabl es for proper configuration of the analog block and rtc, as well as timing wave forms so users can access and con trol the acm directly from their designs. the analog block contains four 8-bit latches pe r analog quad that are initialized through the acm. these latches act as config uration bits for analog quads. the acm block ru ns from the core voltage supply (1.5 v). access to the acm is achieved via 8-bit addres s and data busses with enables. the pin list is provided in table 2-36 on page 2-82 . the acm clock speed is limited to a maximum of 10 mhz, more than sufficient to handle the low-bandwidth requirements of configuring the analog block and the rtc (sub-block of the analog block). table 2-51 decodes the acm address space and maps it to the correspondin g analog quad and configuration byte for that quad. table 2-51 ? acm address decode ta ble for analog quad acmaddr [7:0] in decimal name description associated peripheral 0 ? ? analog quad 1 aq0 byte 0 analog quad 2 aq0 byte 1 analog quad 3 aq0 byte 2 analog quad 4 aq0 byte 3 analog quad 5 aq1 byte 0 analog quad . . . . . . . . . analog quad 36 aq8 byte 3 analog quad 37 aq9 byte 0 analog quad 38 aq9 byte 1 analog quad 39 aq9 byte 2 analog quad 40 aq9 byte 3 analog quad 41 undefined analog quad . . . . . . undefined analog quad 63 undefined rtc 64 counter0 counter bits 7:0 rtc 65 counter1 counter bits 15:8 rtc 66 counter2 counter bits 23:16 rtc 67 counter3 counter bits 31:24 rtc 68 counter4 counter bits 39:32 rtc 72 matchreg0 match register bits 7:0 rtc
fusion family of mi xed-signal flash fpgas device architecture 2-128 v2.0 acm characteristics 1 73 matchreg1 match register bits 15:8 rtc 74 matchreg2 match register bits 23:16 rtc 75 matchreg3 match register bits 31:24 rtc 76 matchreg4 match register bits 39:32 rtc 80 matchbits0 individual match bits 7:0 rtc 81 matchbits1 individual match bits 15:8 rtc 82 matchbits2 individual match bits 23:16 rtc 83 matchbits3 individual match bits 31:24 rtc 84 matchbits4 individual match bits 39:32 rtc 88 ctrl_stat control (write) / status (read) register bits 7:0 rtc note: acmaddr bytes 1 to 40 pertain to the analog qu ads; bytes 64 to 89 pertain to the rtc. 1. when addressing the rtc addresses (i.e., acmaddr 64 to 89), there is no timing generator, and the rc_osc, byte_en, an d aq_wen signals have no impact. table 2-51 ? acm address decode table fo r analog quad (continued) acmaddr [7:0] in decimal name description associated peripheral figure 2-95 ? acm write waveform figure 2-96 ? acm read waveform d1 a1 t sueacm t heacm t sudacm t hdacm t suaacm t haacm a0 d0 acmclk acmwen acmwdata acmaddress a0 a1 rd0 rd1 t mpwclkacm t clkqacm acmclk acmaddress acmrdata
analog configuration mux v2.0 2-129 timing characteristics table 2-52 ? analog configuration mu ltiplexer (acm) timing commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t clkqacm clock-to-q of the acm 19.73 22.48 26.42 ns t sudacm data setup time for the acm 4.39 5.00 5.88 ns t hdacm data hold time for the acm 0.00 0.00 0.00 ns t suaacm address setup time for the acm 4.73 5.38 6.33 ns t haacm address hold time for the acm 0.00 0.00 0.00 ns t sueacm enable setup time for the acm 3.93 4.48 5.27 ns t heacm enable hold time for the acm 0.00 0.00 0.00 ns t mpwaracm asynchronous reset mini mum pulse width for the acm 10.00 10.00 10.00 ns t remaracm asynchronous reset removal time for the acm 12.98 14.79 17.38 ns t recaracm asynchronous reset recovery time for the acm 12.98 14.79 17.38 ns t mpwclkacm clock minimum pulse width for the acm 45.00 45.00 45.00 ns t fmaxclkacm lock maximum frequency fo r the acm 10.00 10.00 10.00 mhz
fusion family of mi xed-signal flash fpgas device architecture 2-130 v2.0 analog quad acm description table 2-53 maps out the acm space associated with co nfiguration of the analog quads within the analog block. table 2-53 shows the byte assignment within eac h quad and the function of each bit within each byte. subsequent tables will explain each bit setting and how it corresponds to a particular configuration. after 3. 3 v and 1.5 v are applied to fusion, analog quad configuration registers are loaded with defaul t settings until the initializatio n and configuration state machine changes them to us er-defined settings. table 2-53 ? analog quad acm byte assignment byte bit signal (bx) fu nction default setting byte 0 (av) 0 b0[0] scaling factor control ? prescaler highest voltage range 1 b0[1] 2 b0[2] 3 b0[3] analog mux select prescaler 4 b0[4] current mo nitor switch off 5 b0[5] direct analog input switch off 6 b0[6] selects v-pad polarity positive 7 b0[7] prescaler op amp mode power-down byte 1 (ac) 0 b1[0] scaling factor control ? prescaler highest voltage range 1 b1[1] 2 b1[2] 3 b1[3] analog mux select prescaler 4 b1[4] 5 b1[5] direct analog input switch off 6 b1[6] selects c-pad polarity positive 7 b1[7] prescaler op amp mode power-down byte 2 (ag) 0 b2[0] internal chip temperature monitor off 1 b2[1] spare ? 2 b2[2] current drive control lowest current 3 b2[3] 4 b2[4] spare ? 5 b2[5] spare ? 6 b2[6] selects g-pad polarity positive 7 b2[7] selects low/high drive low drive byte 3 (at) 0 b3[0] scaling factor control ? prescaler highest voltage range 1 b3[1] 2 b3[2] 3 b3[3] analog mux select prescaler 4 b3[4] 5 b3[5] direct analog input switch off 6 b3[6] ? ? 7 b3[7] prescaler op amp mode power-down
analog configuration mux v2.0 2-131 table 2-54 details the settings available to control the prescaler values of the av, ac, and at pins. note that the at pin has a reduced nu mber of available prescaler values. table 2-55 details the settings availabl e to control the mux within each of the av, ac, and at circuits. this mux determi nes whether the signal routed to the adc is the direct analog input, prescaled signal, or output of either the curren t monitor block or the temperature monitor block. table 2-56 details the settings available to control the direct analog input switch for the av, ac, and at pins. table 2-57 details the settings available to control the polarity of the signals coming to the av, ac, and at pins. note that th e only valid setting for the at pin is logic 0 to support positive voltages. table 2-54 ? prescaler control truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[2:0] scaling factor, pad to adc input lsb for an 8-bit conversion 2 (mv) lsb for a 10-bit conversion 2 (mv) lsb for a 12-bit conversion 2 (mv) full-scale voltage range name 000 1 0.15625 64 16 4 16.368 v 16 v 001 0.3125 32 8 2 8.184 v 8 v 010 1 0.625 16 4 1 4.092 v 4 v 011 1.25 8 2 0.5 2.046 v 2 v 100 2.5 4 1 0.25 1.023 v 1 v 101 5.0 2 0.5 0.125 0.5115 v 0.5 v 110 10.0 1 0.25 0.0625 0.25575 v 0.25 v 111 20.0 0.5 0.125 0.03125 0.127875 v 0.125 v notes: 1. these are the only valid ranges for the temperature monitor block prescaler. 2. lsb voltage equivalences assume varef = 2.56 v. table 2-55 ? analog multiplexer truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[4] control lines bx[3] adc connected to 0 0 prescaler 0 1 direct input 1 0 current amplifier temperature monitor 1 1 not valid table 2-56 ? direct analog input switch control truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[5] direct input switch 0 off 1 on table 2-57 ? voltage polarity control truth table?av (x = 0), ac (x = 1), and at (x = 3)* control lines bx[6] input signal polarity 0 positive 1 negative note: *the b3[6] signal for the at pad should be kept at logic 0 to accept only positive voltages.
fusion family of mi xed-signal flash fpgas device architecture 2-132 v2.0 table 2-58 details the settings available to either po wer down or enable the prescaler associated with the analog inputs av, ac, and at. table 2-59 details the settings available to enable the current monitor block associated with the ac pin. table 2-60 details the settings available to configure th e drive strength of the gate drive when not in high-drive mode. table 2-61 details the settings available to set the pola rity of the gate driver (either p-channel- or n-channel-type devices). table 2-62 details the settings available to turn on the gate driver and set whether high-drive mode is on or off. table 2-63 details the settings available to turn on and off the chip internal temperature monitor. table 2-58 ? prescaler op amp power-down truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[7] prescaler op amp 0 power-down 1 operational table 2-59 ? current monitor input switch control truth table?av (x = 0) control lines b0[4] current monitor input switch 0 off 1 on table 2-60 ? low-drive gate driver current truth table (ag) control lines b2[3] control lines b2[2] current (a) 0 0 1 0 1 3 1 0 10 1 1 30 table 2-61 ? gate driver polarity truth table (ag) control lines b2[6] gate driver polarity 0 positive 1 negative table 2-62 ? gate driver control truth table (ag) control lines b2[7] g don gate driver 0 0 off 0 1 low drive on 1 0 off 1 1 high drive on table 2-63 ? internal temperature monitor control truth table control lines b2[0] pdtmb chip internal temperature monitor 00off 11on
user i/os v2.0 2-133 user i/os introduction fusion devices feature a flexible i/o structure, su pporting a range of mixed voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v) through a bank-selectable voltage. table 2-65 , table 2-66 , table 2-67 , and table 2-68 on page 2-136 show the voltages and the compatible i/o standards. i/os provide programmable slew rates, drive stre ngths, weak pull-up, and weak pull-down circuits . 3.3 v pci and 3.3 v pci-x are 5 v?tolerant. see the "5 v input tolerance" section on page 2-145 for possible implementations of 5 v tolerance. all i/os are in a known state during power-up, and any power-up sequence is allowed without current impact. refer to the "i/o power-up and supply voltag e thresholds for power-on reset (commercial and industrial )" section on page 3-5 for more information. in low power standby or sleep mode (v cc is off, v cc33a is on, v cci is on) or when the resource is not used, digital inputs are tristated, digital outputs are tristated, and digital bibufs (input/output) are tristated. i/o tile the fusion i/o tile prov ides a flexible, programmable structure for implementing a large number of i/o standards. in addition, the registers available in the i/o tile in selected i/o banks can be used to support high-performance regist er inputs and outpu ts, with register enable if desired ( figure 2-97 on page 2-134 ). the registers can also be used to supp ort the jesd-79c ddr standard within the i/o structure (see the "double data rate (ddr) support" section on page 2-140 for more information). as depicted in figure 2-98 on page 2-139 , all i/o registers share one clr port. the output register and output enable re gister share one clk port. refer to the "i/o registers" se ction on page 2-139 for more information. i/o banks and i/o standards compatibility the digital i/os are grouped into i/o voltage bank s. there are three digital i/o banks on the afs090 and afs250 devices and four digital i/o ba nks on the afs600 and afs1500 devices. figure 2-111 on page 2-160 and figure 2-112 on page 2-160 show the bank configurati on by device. the north side of the i/o in the afs600 and afs1500 devices comp rises two banks of actel pro i/os. the actel pro i/os support a wide number of voltage-referenced i/o standards in addition to the multitude of single-ended and differ ential i/o standards common throug hout all actel digital i/os. each i/o voltage bank has dedicated i/o supply and ground voltages (v cci /gndq for input buffers and v cci /gnd for output buffers). because of these de dicated supplies, only i/os with compatible standards can be assigned to the same i/o voltage bank. table 2-66 and table 2-67 on page 2-135 show the required voltage compatibilit y values for each of these voltages. for more information about i/o and global assignmen ts to i/o banks, refer to the specific pin table of the device in the "package pin assignments" on page 4-1 and the "user i/o naming convention" section on page 2-159 . each pro i/o bank is divided into minibanks. any user i/o in a v ref minibank (a minibank is the region of scope of a v ref pin) can be configured as a v ref pin ( figure 2-97 on page 2-134 ). only one v ref pin is needed to control the entire v ref minibank. the location and scope of the v ref minibanks can be determined by the i/o name. for details, see the "user i/o naming convention" section on page 2-159 . table 2-67 on page 2-135 shows the i/o standards supporte d by fusion devices and the corresponding voltage levels. i/o standards are compatible if the following are true: ? their v cci values are identical. ? if both of the standards need a v ref , their v ref values must be identical (pro i/o only).
fusion family of mi xed-signal flash fpgas device architecture 2-134 v2.0 figure 2-97 ? fusion pro i/o bank detail showing v ref minibanks (north side ofafs600 and afs1500) table 2-64 ? i/o standards supported by bank type i/o bank single-ended i/o standards differential i/o standards voltage-referenced hot- swap standard i/o lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v ?? yes advanced i/o lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v, 3.3 v pci / 3.3 v pci-x lvpecl and lvds ? ? pro i/o lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v, 3.3 v pc i / 3.3 v pci-x lvpecl and lvds gtl+ 2.5 v / 3.3 v, gtl 2.5 v / 3.3 v, hstl class i and ii, sstl2 class i and ii, sstl3 class i and ii yes bank 1 bank 0 i/o i/o gnd i/o i/o i/o i/o gnd i/o i/o i/o pad if needed, the v ref for a given minibank can be provided by any i/o within the minibank. ccc ccc ccc up to five v ref minibanks within an i/o bank v ref signal scope is between 8 and 18 i/os. common v ref signal for all i/os in v ref minibanks v cci v cc v cci v cc
user i/os v2.0 2-135 table 2-65 ? i/o bank support by device i/o bank afs090 afs250 afs600 afs1500 standard i/o n n ? ? advanced i/o e, w e, w e, w e, w pro i/o ? ? n n analog quad s s s s note: e = east side of the device w = west side of the device n = north side of the device s = south side of the device table 2-66 ? fusion v cci voltages and comp atible standards v cci (typical) compatible standards 3.3 v lvttl/lvcmos 3.3, pci 3. 3, sstl3 (class i and ii),* gtl+ 3.3, gtl 3.3,* lvpecl 2.5 v lvcmos 2.5, lvcmos 2.5/5.0, sstl2 (class i an d ii),* gtl+ 2.5,* gtl 2.5,* lvds, blvds, m-lvds 1.8 v lvcmos 1.8 1.5 v lvcmos 1.5, hstl (class i),* hstl (class ii)* note: *i/o standard supported by pro i/o banks. table 2-67 ? fusion v ref voltages and comp atible standards* v ref (typical) compatible standards 1.5 v sstl3 (class i and ii) 1.25 v sstl2 (class i and ii) 1.0 v gtl+ 2.5, gtl+ 3.3 0.8 v gtl 2.5, gtl 3.3 0.75 v hstl (class i), hstl (class ii) note: *i/o standards supported by pro i/o banks.
fusion family of mi xed-signal flash fpgas device architecture 2-136 v2.0 table 2-68 ? fusion standard and advanced i/o features i/o bank voltage (typical) minibank voltage (typical) lvttl/lvcmos 3.3 v lvcmos 2.5 v lvcmos 1.8 v lvcmos 1.5 v 3.3 v pci / pci-x gtl + (3.3 v) gtl + (2.5 v) gtl (3.3 v) gtl (2.5 v) hstl class i and ii (1.5 v) sstl2 class i and ii (2.5 v) sstl3 class i and ii (3.3 v) lvds (2.5 v 5%) lvpecl (3.3 v) 3.3 v ? 0.80 v 1.00 v 1.50 v 2.5 v ? 0.80 v 1.00 v 1.25 v 1.8 v ? 1.5 v ? 0.75 v note: white box: allowable i/o standard combinations gray box: illegal i/o standard combinations
user i/os v2.0 2-137 features supported on pro i/os table 2-69 lists all features supported by transmitter /receiver for single-ended and differential i/os. table 2-69 ? fusion pro i/o features feature description single-ended and voltage- referenced transmitter features ? hot insertion in every mode except pc i or 5 v input tolerant (these modes use clamp diodes and do not allow hot insertion) ? activation of hot insertion (disabling the clamp diode) is selectable by i/os. ? weak pull-up and pull-down ? two slew rates ? skew between output buffer enable/d isable time: 2 ns delay (rising edge) and 0 ns delay (falling edge); see "selectable skew be tween output buffer enable/disable time" on page 2-150 for more information ? five drive strengths ? 5 v?tolerant receiver ( "5 v input tolerance" section on page 2-145 ) ? lvttl/lvcmos 3.3 v outputs comp atible with 5 v ttl inputs ( "5 v output tolerance" section on page 2-149 ) ? high performance ( table 2-73 on page 2-144 ) single-ended receiver features ? schmitt trigger option ? esd protection ? programmable delay: 0 ns if bypassed , 0.625 ns with '000' setting, 6.575 ns with '111' setting , 0.85-ns intermediate delay increments (at 25c, 1.5 v) ? high performance ( table 2-73 on page 2-144 ) ? separate ground planes, gnd/gndq, for input buffers only to avoid output-induced noise in the input circuitry voltage-referenced differential receiver features ? programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns with '111' setting , 0.85-ns intermediate delay increments (at 25c, 1.5 v) ? high performance ( table 2-73 on page 2-144 ) ? separate ground planes, gnd/gndq, for input buffers only to avoid output-induced noise in the input circuitry cmos-style lvds, blvds, m-lvds, or lvpecl transmitter ? two i/os and external resistors are used to provide a cmos-style lvds, blvds, m-lvds, or lvpecl transmitter solution. ? activation of hot insertion (disabling the clamp diode) is selectable by i/os. ? weak pull-up and pull-down ? fast slew rate lvds/lvpecl differential receiver features ? esd protection ? high performance ( table 2-73 on page 2-144 ) ? programmable delay: 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25c, 1.5 v) ? separate input buffer ground and power planes to avoid output-induced noise in the input circuitry
fusion family of mi xed-signal flash fpgas device architecture 2-138 v2.0 table 2-70 ? maximum i/o frequency for single-ended, vo ltage-referenced, a nd differential i/os; all i/o bank types (maximum drive strength and high slew selected) specification performance up to lvttl/lvcmos 3.3 v 200 mhz lvcmos 2.5 v 250 mhz lvcmos 1.8 v 200 mhz lvcmos 1.5 v 130 mhz pci 200 mhz pci-x 200 mhz hstl-i 300 mhz hstl-ii 300 mhz sstl2-i 300 mhz sstl2-ii 300 mhz sstl3-i 300 mhz sstl3-ii 300 mhz gtl+ 3.3 v 300 mhz gtl+ 2.5 v 300 mhz gtl 3.3 v 300 mhz gtl 2.5 v 300 mhz lvds 350 mhz lvpecl 300 mhz
user i/os v2.0 2-139 i/o registers each i/o module contains several input, output, and enable registers. refer to figure 2-98 for a simplified representation of the i/o block. the number of input registers is selected by a set of switches (not shown in figure 2-98 ) between registers to implement single or differential data transmission to and from the fpga core. the designer software sets these switches for the user. a common clr/pre signal is employed by all i/o registers when i/o register combining is used. input register 2 does not have a clr/pre pin, as this register is used fo r ddr implementation. the i/o register combining must satisfy some rules. note: fusion i/os have registers to support ddr functionality (see the "double data rate (ddr) support" section on page 2-140 for more information). figure 2-98 ? i/o block logical representation input reg e = enable pin a y pad 1 2 3 4 5 6 oce ice ice input reg input reg clr/pre clr/pre clr/pre clr/pre clr/pre pull-up/down resistor control signal drive strength and slew-rate control output reg output reg to fpga core from fpga core output enable reg oce i/o / clr or i/o / pre / oce i/o / q0 i/o / q1 i/o / iclk i/o / d0 i/o / d1 / ice i/o / oclk i/o / oe
fusion family of mi xed-signal flash fpgas device architecture 2-140 v2.0 double data rate (ddr) support fusion pro i/os support 350 mhz ddr inputs and outputs. in ddr mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidths and signal integrity requirements, making it very efficient for implemen ting very high-speed systems. ddr interfaces can be implemented using hstl, sstl, lvds, and lvpecl i/o standards. in addition, high-speed ddr interfaces can be implemented using lvds i/o. input support for ddr the basic structure to suppor t a ddr input is shown in figure 2-99 . three input registers are used to capture incoming data, which is presented to the co re on each rising edge of the i/o register clock. each i/o tile on fusion devices supports ddr inputs. output support for ddr the basic ddr output structure is shown in figure 2-100 on page 2-141 . new data is presented to the output every half clock cycl e. note: ddr macros and i/o regi sters do not require additional routing. the combiner automatically recognizes the ddr macro and pushes its registers to the i/o register area at the edge of the chip. the routing delay from the i/o registe rs to the i/o buffers is already taken into account in the ddr macro. refer to the actel application note using ddr for fusion devices for more information. figure 2-99 ? ddr input register support in fusion devices input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
user i/os v2.0 2-141 figure 2-100 ? ddr output support in fusion devices data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out ff1 0 1 a b d e c c b outbuf data_r (from core)
fusion family of mi xed-signal flash fpgas device architecture 2-142 v2.0 hot-swap support hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered- up system. the levels of hot-swap support and examples of related applications are described in table 2-71 . the i/os also need to be configured in hot insertion mode if hot plugging compliance is required. table 2-71 ? levels of hot-swap support hot swapping level description power applied to device bus state card ground connection device circuitry connected to bus pins example of application with cards that contain fusion devices compliance of fusion devices 1 cold-swap no ? ? ? system and card with actel fpga chip are powered down, then card gets plugged into system, then power supplies are turned on for system but not for fpga on card. compliant i/os can but do not have to be set to hot insertion mode. 2 hot-swap while reset yes held in reset state must be made and maintained for 1 ms before, during, and after insertion/ removal ? in pci hot plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. compliant i/os can but do not have to be set to hot insertion mode. 3 hot-swap while bus idle yes held idle (no ongoing i/o processes during insertion/re moval) same as level 2 must remain glitch-free during power-up or power- down board bus shared with card bus is "frozen," and there is no toggling activity on bus. it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. compliant with cards with two levels of staging. i/os have to be set to hot insertion mode. 4 hot-swap on an active bus yes bus may have active i/o processes ongoing, but device being inserted or removed must be idle. same as level 2 same as level 3 there is activity on the system bus, and it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. compliant with cards with two levels of staging. i/os have to be set to hot insertion mode.
user i/os v2.0 2-143 for fusion devices requiring level 3 and/or le vel 4 compliance, the board drivers connected to fusion i/os need to have 10 k (or lower) output drive resistance at hot insertion, and 1 k (or lower) output drive resistance at hot removal. this is the resistance of the transmitter sending a signal to the fusion i/o, and no additional resistance is need ed on the board. if that cannot be assured, three levels of staging can be used to meet level 3 and/or leve l 4 compliance. cards with two levels of staging should have the following sequence: 1. grounds 2. powers, i/os, other pins cold-sparing support cold-sparing means that a subsyste m with no power applied (usually a circuit board) is electrically connected to the system that is in operation. th is means that all input buffers of the subsystem must present very high input impedance with no po wer applied so as not to disturb the operating portion of the system. pro i/o banks and standard i/o banks fully support cold-sparing. for pro i/o banks, standards such as pci that requi re i/o clamp diodes, can also achieve cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 v. for advanced i/o banks, since the i/o clamp diode is always active , cold-sparing can be accomplished either by employing a bus switch to isolate the device i/os from the rest of the system or by driving each advanced i/o pin to 0 v. if standard i/o banks are used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. this can be done with a discharge resistor or a switched resistor. this is necessa ry because the standard i/o buffers do not have built-in i/o clamp diodes. if a resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitor is in parallel with the resistor). the rc time constant should ensure full discharge of supplies be fore cold-sparing func tionality is required. the resistor is necessary to ensure that the power pins are discharg ed to ground every time there is an interruption of power to the device. i/o cold-sparing may add additional current if the pin is configured with either a pull-up or pull down resistor and driven in the op posite direction. a small static cu rrent is induced on each io pin when the pin is driven to a voltage opposite to the weak pull resistor. the current is equal to the voltage drop across the input pin divided by the pull resistor. please refer to table 2-92 on page 2-171 , table 2-93 on page 2-171 , and table 2-94 on page 2-173 for the specific pull resistor value for the corresp onding i/o standard. for example, assuming an lvttl 3.3 v input pin is configured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven low. for an lvttl 3.3 v, pull- up resistor is ~45 k and the resulting current is equal to 3.3 v / 45 k = 73 a for the i/o pin. this is true also when a weak pull-down is chosen and the input pin is driven high. avoiding this current can be done by driving the input low when a weak pull-down resistor is used, and driving it high when a weak pull-up resistor is used. in active and static modes, this curren t draw can occur in the following cases: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers with pull-up, driven low ? bidirectional buffers with pull-down, driven high ? output buffers with pull-up, driven low ? output buffers with pull-down, driven high ? tristate buffers with pull-up, driven low ? tristate buffers with pull-down, driven high
fusion family of mi xed-signal flash fpgas device architecture 2-144 v2.0 electrostatic discharge (esd) protection fusion devices are tested per jedec standard jesd22-a114-b. fusion devices contain clamp diodes at every i/o, global, and power pad. clamp diodes protect all device pads against damage from esd as we ll as from excessive voltage transients. each i/o has two clamp diodes. one diode has its positive (p) side connected to the pad and its negative (n) side connected to v cci . the second diode ha s its p side connected to gnd and its n side connected to the pad. during oper ation, these diodes are normally biased in the off state, except when transient voltage is significantly above v cci or below gnd levels. by selecting the appropriate i/o configuration, the diode is turned on or off. refer to table 2-72 and table 2-73 on page 2-144 for more information about i/ o standards and the clamp diode. the second diode is always connected to the pa d, regardless of the i/o configuration selected. table 2-72 ? fusion standard and advanced i/o ? hot- swap and 5 v input tolerance capabilities i/o assignment clamp diode hot insertion 5 v input tolerance 1 input buffer output buffer standard i/o advanced i/o standard i/o advanced i/o standard i/o advanced i/o 3.3 v lvttl/lvcmos no yes yes no yes 1 yes 1 enabled/disabled 3.3 v pci, 3.3 v pci-x n/a yes n/a no n/a yes 1 enabled/disabled lvcmos 2.5 v no yes yes no no no enabled/disabled lvcmos 2.5 v / 5.0 v n/a yes n/a no n/a yes 2 enabled/disabled lvcmos 1.8 v no yes yes no no no enabled/disabled lvcmos 1.5 v no yes yes no no no enabled/disabled differential, lvds/blvds/m-lvds/ lvpecl 3 n/a yes n/a no n/a no enabled/disabled notes: 1. can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor. 2. can be implemented with an external resistor and an in ternal clamp diode. 3. bidirectional lvpecl buffers are not supported. i/os can be configured as either input buffers or output buffers. table 2-73 ? fusion pro i/o ? hot-swap and 5 v input tolerance capabilities i/o assignment clamp diode hot insertion 5 v input tolerance input buffer output buffer 3.3 v lvttl/lvcmos no yes yes 1 enabled/disabled 3.3 v pci, 3.3 v pci-x yes no yes 1 enabled/disabled lvcmos 2.5 v 3 no yes no enabled/disabled lvcmos 2.5 v / 5.0 v 3 yes no yes 2 enabled/disabled lvcmos 1.8 v no yes no enabled/disabled lvcmos 1.5 v no yes no enabled/disabled voltage-referenced input buffer no yes no enabled/disabled differential, lvds/b lvds/m-lvds/lvpecl 4 no yes no enabled/disabled notes: 1. can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor. 2. can be implemented with an external resistor and an in ternal clamp diode. 3. in the smartgen, flashrom, flash memory system build er, and analog system builder user's guide , select the lvcmos5 macro for the lvcmos 2.5 v / 5.0 v i/o standard or the lvcmos25 macro for the lvcmos 2.5 v i/o standard. 4. bidirectional lvpecl buffers are not supported. i/os can be configured as either input buffers or output buffers.
user i/os v2.0 2-145 5 v input tolerance i/os can support 5 v input tolerance when lvttl 3.3 v, lvcmos 3.3 v, lvcmos 2.5 v / 5 v, and lvcmos 2.5 v configurations are used (see table 2-74 on page 2-148 for more details). there are four recommended solutions (see figure 2-101 to figure 2-104 on page 2-147 for details of board and macro setups) to achieve 5 v receiver toleranc e. all the solutions meet a common requirement of limiting the voltage at the in put to 3.6 v or less. in fact, the i/o absolute maximum voltage rating is 3.6 v, and any voltage above 3.6 v may cause long-term gate oxide failures. solution 1 the board-level design needs to ensure that the reflected waveform at the pad does not exceed the limits provided in table 3-4 on page 3-4 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci / pci-x configuration, bu t the internal diode should not be used for clamping, and the vo ltage must be limited by the two external resistors, as explained below. relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. the following are some examples of possible re sistor values (based on a simplified simulation model with no line effects and 10 transmitter output resistance, where rtx_out_high = (v cci ? v oh )/i oh , rtx_out_low = v ol /i ol ). example 1 (high spee d, high current): rtx_out_high = rtx_out_low = 10 r1 = 36 (5%), p(r1)min = 0.069 r2 = 82 (5%), p(r2)min = 0.158 imax_tx = 5.5 v / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 ma t rise =t fall = 0.85 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise =t fall = 4 ns at c_pad_load = 50 pf (inclu des up to 25% safety margin) example 2 (low?medium sp eed, medium current): rtx_out_high = rtx_out_low = 10 r1 = 220 (5%), p(r1)min = 0.018 r2 = 390 (5%), p(r2)min = 0.032 imax_tx = 5.5 v / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 ma t rise =t fall = 4 ns at c_pad_load = 10 pf (inclu des up to 25% safety margin) t rise =t fall = 20 ns at c_pad_load = 50 pf (includes up to 25% safety margin) other values of resistors are also allowed as long as the resistors ar e sized appropriat ely to limit the voltage at the receiving end to 2.5 v < vin(rx) < 3 .6 v when the transmitter sends a logic 1. this range of vin_dc(rx) must be assured for an y combination of transmitter supply (5 v 0.5 v), transmitter output resistance, and board resistor tolerances.
fusion family of mi xed-signal flash fpgas device architecture 2-146 v2.0 temporary overshoots are allowed according to table 3-4 on page 3-4 . solution 2 the board-level design must ensure that the refl ected waveform at the pad does not exceed limits provided in table 3-4 on page 3-4 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci/pci-x configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and zener, as shown in figure 2-102 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 2-101 ? solution 1 figure 2-102 ? solution 2 on-chip off-chip solution 1 5.5 v 3.3 v requires two board resistors, lvcmos 3.3 v i/os fusion i/o input rext1 rext2 solution 2 5.5 v 3.3 v requires one board resistor, one zener 3.3 v diode, lvcmos 3.3 v i/os fusion i/o input rext1 zener 3.3 v on-chip off-chip
user i/os v2.0 2-147 solution 3 the board-level design must ensure that the refl ected waveform at the pad does not exceed limits provided in table 3-4 on page 3-4 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci/pcix configuration, but the internal diode should not be used for clamping, an d the voltage must be limited by the bus switch, as shown in figure 2-103 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. solution 4 figure 2-103 ? solution 3 figure 2-104 ? solution 4 solution 3 requires a bus switch on the board, lvttl/lvcmos 3.3 v i/os. fusion i/o input 3.3 v 5.5 v 5.5 v bus switch idtqs32x23 on-chip off-chip solution 4 2.5 v on-chip clamp diode requires one board resistor. available for lvcmos 2.5 v / 5.0 v. on-chip off-chip 5.5 v 2.5 v fusion i/o input rext1
fusion family of mi xed-signal flash fpgas device architecture 2-148 v2.0 table 2-74 ? comparison table for 5 v?compliant receiver scheme scheme board components speed current limitations 1 two resistors low to high 1 limited by transmitter's drive strength 2 resistor and zener 3.3 v medium limit ed by transmitter's drive strength 3bus switch highn/a 4 minimum resistor value 2 r = 47 at t j = 70c r = 150 at t j = 85c r = 420 at t j = 100c medium maximum diode current at 100% duty cycle, signal constantly at '1' 52.7 ma at t j =70c / 10-year lifetime 16.5 ma at t j = 85c / 10-year lifetime 5.9 ma at t j = 100c / 10-year lifetime for duty cycles other than 100%, the currents can be increased by a factor = 1 / (duty cycle). example: 20% duty cycle at 70c maximum current = (1 / 0.2) * 52.7 ma = 5 * 52.7 ma = 263.5 ma notes: 1. speed and current consumption increase as the board resistance values decrease. 2. resistor values ensure i/o diode long-term reliability.
user i/os v2.0 2-149 5 v output tolerance fusion i/os must be set to 3.3 v lvttl or 3.3 v lv cmos mode to reliably drive 5 v ttl receivers. it is also critical that there be no ex ternal i/o pull-up resistor to 5 v, since this resistor would pull the i/o pad voltage beyond the 3.6 v absolute maximu m value and consequently cause damage to the i/o. when set to 3.3 v lvttl or 3.3 v lvcmos mode, fusion i/os can directly drive signals into 5 v ttl receivers. in fact, v ol =0.4v and v oh = 2.4 v in both 3.3 v lvttl and 3.3 v lvcmos modes exceed the v il =0.8v and v ih = 2 v level requirements of 5 v ttl receivers. therefor e, level '1' and level '0' will be recognized correc tly by 5 v ttl receivers. simultaneously switchin g outputs and pcb layout ? simultaneously switching outpu ts (ssos) can produce signal integrity problems on adjacent signals that are not part of th e sso bus. both inductive and capacitive coupling parasitics of bond wires inside packages and of traces on pcbs will transfer noise from sso busses onto signals adjacent to those busses. additionally, ssos can produce ground bounce noise and v cci dip noise. these two noise types are caused by rapidly changing currents through gnd and v cci package pin inductances during switching activities: ? ground bounce noise vo ltage = l(gnd) * di/dt ?v cci dip noise voltage = l(v cci ) * di/dt any group of four or more input pins switching on the same clock edge is considered an sso bus. the shielding should be done both on the board and inside the package unless otherwise described. in-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to sso bus are lvttl/lvcmos inputs, lvttl/lvcmos outputs, or gtl/sstl/hstl/lvds/lvpecl inputs and outputs. board traces in the vicinity of the sso bus have to be adequately shielded from mutu al coupling and inductive noise that can be generated by the sso bus. also, noise generated by the sso bus needs to be reduced inside the package. pcbs perform an important function in feeding sta ble supply voltages to the ic and, at the same time, maintaining signal integrity between devices. key issues that need to considered are as follows: ? power and ground plane design and decoupling network design ? transmission line reflections and terminations
fusion family of mi xed-signal flash fpgas device architecture 2-150 v2.0 selectable skew between output buffer enable/disable time the configurable skew block is used to delay the output buffer assertion (e nable) without affecting deassertion (disable) time. figure 2-105 ? block diagram of output enable path figure 2-106 ? timing diagram (option1: bypasses skew circuit) figure 2-107 ? timing diagram (option 2: enables skew circuit) enable (out) skew circuit output enable (from fpga core) i/o output buffers enable (in) mux skew select enable (in) enable (out) less than 0.1 ns less than 0.1 ns enable (in) enable (out) 1.2 ns (typical) less than 0.1 ns
user i/os v2.0 2-151 at the system level, the skew circuit can be used in applications where tr ansmission activities on bidirectional data lines need to be coordinated. this circuit, when selected, provides a timing margin that can prevent bus cont ention and subsequent data loss or transmitter overstress due to transmitter-to-transmitter current shorts. figure 2-108 presents an example of the skew circuit implementation in a bidirect ional communica tion system. figure 2-109 shows how bus contention is created, and figure 2-110 on page 2-152 shows how it can be avoided with the skew circuit. figure 2-108 ? example of implementation of skew circuits in bidirectional transmission systems using fusion devices figure 2-109 ? timing diagram (byp asses skew circuit) transmitter 1: fusion i/o transmitter 2: generic i/o enable(t2) en(b1) en(b2) en(r1) enable(t1) bidirectional data bus transmitter enable/ disable skew or bypass skew routing delay (t1) routing delay (t2) en (b1) en (b2) enable (r1) transmitter 1: on enable (t2) transmitter 2: on enable (t1) bus contention transmitter 1: off transmitter 1: off transmitter 2: off
fusion family of mi xed-signal flash fpgas device architecture 2-152 v2.0 weak pull-up and weak pull-down resistors fusion devices support optional weak pull-up and pull-down resistors for each i/o pin. when the i/o is pulled up, it is connected to the v cci of its corresponding i/o bank . when it is pulled down, it is connected to gnd. refer to table 2-94 on page 2-173 for more information. slew rate control and drive strength fusion devices support output sl ew rate control: high and low. the high slew rate option is recommended to minimize the propagation delay. this high-speed option may introduce noise into the system if appropriate sign al integrity measures are not ad opted. selecting a low slew rate reduces this kind of noise but adds some delays in the system. low slew rate is recommended when bus transients are expected. drive strength shou ld also be selected according to the design requirements and noise immunity of the system. the output slew rate and multiple drive strength controls are available in lvttl/lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 2.5 v / 5.0 v input, lvcmos 1.8 v, and lvcmos 1.5 v. all other i/o standards have a high output slew rate by default. for fusion slew rate and drive strength specificat ions, refer to the approp riate i/o bank table: ? fusion standard i/o ( table 2-75 on page 2-153 ) ? fusion advanced i/o ( table 2-76 on page 2-153 ) ? fusion pro i/o ( table 2-77 on page 2-153 ) table 2-80 on page 2-156 lists the default values for the above selectable i/o attributes as well as those that are preset for each i/o standard. figure 2-110 ? timing diagram (with skew circuit selected) en (b1) en (b2) transmitter 1: on enable (t2) transmitter 2: on transmitter 2: off enable (t1) result: no bus contention transmitter 1: off transmitter 1: off
user i/os v2.0 2-153 refer to table 2-75 , table 2-76 , and table 2-77 on page 2-153 for slew and out_drive settings. table 2-78 on page 2-154 and table 2-79 on page 2-155 list the i/o default attributes. table 2-80 on page 2-156 lists the voltages for the supported i/o standards. table 2-75 ? fusion standard i/o stan dards?out_drive settings i/o standards out_drive (ma) 2 4 6 8 slew lvttl/lvcmos 3.3 v ???? high low lvcmos 2.5 v ???? high low lvcmos 1.8 v ?? ? ? high low lvcmos 1.5 v ? ???highlow table 2-76 ? fusion advanced i/o standards? slew and out_drive settings i/o standards out_drive (ma) 2 4 6 8 12 16 slew lvttl/lvcmos 3.3 v ????? ? high low lvcmos 2.5 v ????? ? high low lvcmos 1.8 v ???? ? ? high low lvcmos 1.5 v ?? ? ? ? ? high low table 2-77 ? fusion pro i/o standards?slew and out_drive settings i/o standards out_drive (ma) slew 2 4 6 8 12 16 24 lvttl/lvcmos 3.3 v ??? ? ? ? ? high low lvcmos 2.5 v ??? ? ? ? ? high low lvcmos 2.5 v/5.0 v ??? ? ? ? ? high low lvcmos 1.8 v ??? ? ? ? ?highlow lvcmos 1.5 v ??? ? ? ? ? high low
fusion family of mi xed-signal flash fpgas device architecture 2-154 v2.0 table 2-78 ? fusion pro i/o default attributes i/o standards slew (output only) out_drive (output only) skew (tribuf and bibuf only) res_pull out_load (output only) combine_register in_delay (input only) in_delay_val (input only) schmitt_trigger (input only) lvttl/lvcmos 3.3 v refer to the following tables for more information: table 2-75 on page 2-153 table 2-76 on page 2-153 table 2-77 on page 2-153 refer to the following tables for more information: table 2-75 on page 2-153 table 2-76 on page 2-153 table 2-77 on page 2-153 off none 35 pf ? off 0 off lvcmos 2.5 v off none 35 pf ? off 0 off lvcmos 2.5/5.0 v off none 35 pf ? off 0 off lvcmos 1.8 v off none 35 pf ? off 0 off lvcmos 1.5 v off none 35 pf ? off 0 off pci (3.3 v) off none 10 pf ? off 0 off pci-x (3.3 v) off none 10 pf ? off 0 off gtl+ (3.3 v) off none 10 pf ? off 0 off gtl+ (2.5 v) off none 10 pf ? off 0 off gtl (3.3 v) off none 10 pf ? off 0 off gtl (2.5 v) off none 10 pf ? off 0 off hstl class i off none 20 pf ? off 0 off hstl class ii off none 20 pf ? off 0 off sstl2 class i and ii off none 30 pf ? off 0 off sstl3 class i and ii off none 30 pf ? off 0 off lvds, blvds, m-lvds off none 0 pf ? off 0 off lvpecl off none 0 pf ? off 0 off
user i/os v2.0 2-155 table 2-79 ? advanced i/o default attributes i/o standards slew (output on ly) out_drive (output only) skew (tribuf and bibuf only) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v refer to the following tables for more information: table 2-75 on page 2-153 table 2-76 on page 2-153 table 2-77 on page 2-153 refer to the following tables for more information: table 2-75 on page 2-153 table 2-76 on page 2-153 table 2-77 on page 2-153 off none 35 pf ? lvcmos 2.5 v off none 35 pf ? lvcmos 2.5/5.0 v off none 35 pf ? lvcmos 1.8 v off none 35 pf ? lvcmos 1.5 v off none 35 pf ? pci (3.3 v) off none 10 pf ? pci-x (3.3 v) off none 10 pf ? lvds, blvds, m-lvds off none ? ? lvpecl off none ? ?
fusion family of mi xed-signal flash fpgas device architecture 2-156 v2.0 table 2-80 ? fusion pro i/o supported standards and corresponding v ref and v tt voltages i/o standard input/output supply voltage (v cci_typ ) input reference voltage (v ref_typ ) board termination voltage (v tt_typ ) lvttl/lvcmos 3.3 v 3.30 v ? ? lvcmos 2.5 v 2.50 v ? ? lvcmos 2.5 v / 5.0 v input 2.50 v ? ? lvcmos 1.8 v 1.80 v ? ? lvcmos 1.5 v 1.50 v ? ? pci 3.3 v 3.30 v ? ? pci-x 3.3 v 3.30 v ? ? gtl+ 3.3 v 3.30 v 1.00 v 1.50 v gtl+ 2.5 v 2.50 v 1.00 v 1.50 v gtl 3.3 v 3.30 v 0.80 v 1.20 v gtl 2.5 v 2.50 v 0.80 v 1.20 v hstl class i 1.50 v 0.75 v 0.75 v hstl class ii 1.50 v 0.75 v 0.75 v sstl3 class i 3.30 v 1.50 v 1.50 v sstl3 class ii 3.30 v 1.50 v 1.50 v sstl2 class i 2.50 v 1.25 v 1.25 v sstl2 class ii 2.50 v 1.25 v 1.25 v lvds, blvds, m-lvds 2.50 v ? ? lvpecl 3.30 v ? ?
user i/os v2.0 2-157 i/o software support in the fusion development softw are, default settings have be en defined for the various i/o standards supported. changes can be made to th e default settings via the use of attributes; however, not all i/o attributes are applicable for all i/o standards. table 2-81 and table 2-82 list the valid i/o attributes that can be manipula ted by the user for each i/o standard. single-ended i/o standards in fusion supp ort up to five different drive strengths. table 2-81 ? fusion standard and advanced i/o attr ibutes vs. i/o standard applications i/o standards slew (output only) out_drive (output only) skew (all macros with oe)* res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v ?? ? ? ? ? lvcmos 2.5 v ?? ? ? ? ? lvcmos 2.5/5.0 v ?? ? ? ? ? lvcmos 1.8 v ?? ? ? ? ? lvcmos 1.5 v ?? ? ? ? ? pci (3.3 v) ??? pci-x (3.3 v) ???? lvds, blvds, m-lvds ?? lvpecl ? note: *this feature does not apply to the standard i/o banks, which are the north i/o banks of afs090 and afs250 devices
fusion family of mi xed-signal flash fpgas device architecture 2-158 v2.0 table 2-82 ? fusion pro i/o attributes vs. i/o standard applications i/o standards slew (output only) out_drive (output only) skew (all macros with oe) res_pull out_load (output only) combine_register in_delay (input only) in_delay_val (input only) schmitt_trigger (input only) hot_swappable lvttl/lvcmos 3.3 v ?? ???????? lvcmos 2.5 v ?? ???????? lvcmos 2.5/5.0 v ?? ???????? lvcmos 1.8 v ?? ???????? lvcmos 1.5 v ?? ???????? pci (3.3 v) ?? ? ?? pci-x (3.3 v) ??? ? ?? gtl+ (3.3 v) ?? ? ?? ? gtl+ (2.5 v) ?????? gtl (3.3 v) ?????? gtl (2.5 v) ?????? hstl class i ?????? hstl class ii ?????? sstl2 class i and ii ?????? sstl3 class i and ii ?????? lvds, blvds, m-lvds ????? lvpecl ?? ? ?
user i/os v2.0 2-159 user i/o naming convention due to the comprehensive and flexible nature of fu sion device user i/os, a naming scheme is used to show the details of the i/o ( figure 2-111 on page 2-160 and figure 2-112 on page 2-160 ). the name identifies to which i/o bank it belongs, as well as the pairin g and pin polarity for differential i/os. i/o nomenclature = gmn/iouxwbyvz gmn is only used for i/os that also have ccc access?i.e., global pins. g=global m = global pin location associated with each ccc on th e device: a (northwest corner ), b (northeast corner), c (east middle), d (southeast corner), e (southwest corner ), and f (west middle). n = global input mux and pin number of the associated gl obal location m, either a0, a1, a2, b0, b1, b2, c0, c1, or c2. figure 2-22 on page 2-28 shows the three input pins per cl ock source mux at ccc location m. u = i/o pair number in the bank, starting at 00 from the northwest i/o bank and proceeding in a clockwise direction. x = p (positive) or n (negative) for di fferential pairs, or r (regular ? si ngle-ended) for the i/os that support single-ended and voltage-referenced i/o standards only. u (positive-lvds only) or v (negative-lvds only) restrict the i/o differential pair from being selected as an lvpecl pair. w = d (differential pair), p (pair), or s (single-ended). d (differential pair) if both members of the pair are bonded out to adjacent pins or are separated only by one gnd or nc pin; p (pair) if both members of the pair are bonded out but do not meet the adjacency requir ement; or s (single-ended) if the i/o pair is not bonded out. for differential (d) pairs, adjacency for ball grid packages means only vertical or horizontal. diagonal adjacency does no t meet the requirements fo r a true differential pair. b = bank y = bank number (0?3). the bank number starts at 0 from the northwest i/o bank and proceeds in a clockwise direction. v = reference voltage z = minibank number
fusion family of mi xed-signal flash fpgas device architecture 2-160 v2.0 figure 2-111 ? naming conventions of fusion devi ces with three digital i/o banks figure 2-112 ? naming conventions of fusion devices with four i/o banks ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c" afs090 standard i/o bank analog quads advanced i/o bank advanced i/o bank afs250 bank 3 bank 3 bank 1 bank 1 bank 2 (analog) bank 0 afs600 afs1500 bank 4 bank 4 bank 2 bank 2 bank 3 (analog) bank 0 bank 1 ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc/pll "c" pro i/o bank analog quads advnaced i/o bank advanced i/o bank
user i/os v2.0 2-161 user i/o characteristics timing model figure 2-113 ? timing model operating conditions: ?2 speed, commercial temperature range (t j =70c), worst-case v cc = 1.425 v dq y y dq dq dq y combinational cell combinational cell combinational cell register cell register cell i/o module (non-registered) lvpecl (pro io banks) lvpecl (pro io banks) lvds, blvds, m-lvds (pro io banks) gtl+ 3.3 v y combinational cell y combinational cell y combinational cell lvttl/lvcmos 3.3 v (pro i/o banks) output drive strength = 24 ma high slew rate lvcmos 1.5 v (pro io banks) output drive strength = 12 ma high slew lvttl/lvcmos 3.3 v (pro i/o banks) output drive strength = 12 ma high slew rate iinput lvttl/lvcmos 3.3 v (pro io banks) input lvttl/lvcmos 3.3 v (pro io banks) input lvttl/lvcmos 3.3 v (pro io banks) i/o module (non-registered) i/o module (non-registered) i/o module (non-registered) i/o module (registered) i/o module (registered) i/o module (non-registered) t pd = 0.56 ns t pd = 0.49 ns t dp = 1.60 ns t pd = 0.87 ns t dp = 2.74 ns t pd = 0.51 ns t pd = 0.47 ns t pd = 0.47 ns t oclkq = 0.59 ns t osud = 0.31 ns t py = 0.90 ns t dp = 1.53 ns t dp = 3.30 ns t dp = 2.39 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 0.90 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 1.36 ns t py = 0.90 ns t py = 1.22 ns t iclkq = 0.24 ns t isud = 0.26 ns
fusion family of mi xed-signal flash fpgas device architecture 2-162 v2.0 figure 2-114 ? input buffer timing model and delays (example) t py = max(t py (r), t py (f)) t pys = max(t pys (r), t pys (f)) t din = max(t din (r), t din (f)) t py (r) pad y v trip gnd t py (f) v trip 50% 50% v ih v cc v il t pys (r) t pys (f) t dout (r) din gnd t dout (f) 50% 50% v cc pad y t py t pys d clk q i/o interface din t din to array
user i/os v2.0 2-163 figure 2-115 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) v trip v trip v oh v cc d 50% 50% v cc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
fusion family of mi xed-signal flash fpgas device architecture 2-164 v2.0 figure 2-116 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl v trip 50% t hz 90% v cci t zh v trip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50% t zhs v trip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% v cc v cc v cc v cci v cc v v cc v oh v ol v ol cc t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r). t eout (f))
user i/os v2.0 2-165 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-83 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions applicable to pro i/os i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min., v max., v min., v max., v max., v min., v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65* v cci 3.6 0.45 v cci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65* v cci 3.6 0.25 * v cci 0.75 * v cci 12 12 3.3 v pci per pci specification 3.3 v pci-x per pci-x specification 3.3 v gtl 25 ma 2 high ?0.3 v ref ? 0.05 v ref + 0.05 3.6 0.4 ? 25 25 2.5 v gtl 25 ma 2 high ?0.3 v ref ? 0.05 v ref + 0.05 3.6 0.4 ? 25 25 3.3 v gtl+ 35 ma high ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.6 ? 51 51 2.5 v gtl+ 33 ma high ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.6 ? 40 40 hstl (i) 8 ma high ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cci ? 0.4 8 8 hstl (ii) 15 ma 2 high ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cci ? 0.4 15 15 sstl2 (i) 15 ma high ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.54 v cci ? 0.62 15 15 sstl2 (ii) 18 ma high ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.35 v cci ? 0.43 18 18 sstl3 (i) 14 ma high ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.7 v cci ? 1.1 14 14 sstl3 (ii) 21 ma high ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.5 v cci ? 0.9 21 21 notes: 1. currents are measured at 85c junction temperature. 2. output drive strength is below jedec specification. 3. output slew rate can be ex tracted by the ibis models. table 2-84 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions applicable to advanced i/os i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min., v max., v min., v max., v max., v min., v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 12 12 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature.
fusion family of mi xed-signal flash fpgas device architecture 2-166 v2.0 table 2-85 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions applicable to standard i/os i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min., v max., v min., v max., v max., v min., v ma ma 3.3 v lvttl / 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 1.5 v lvcmos 2 ma high ?0.3 0.35 * v cci 0.65* v cci 3.6 0.25 * v cci 0.75 * v cci 22 note: currents are measured at 85c junction temperature. table 2-86 ? summary of maximum and minimum dc input leve ls applicable to commercial and industrial conditions applicable to all i/o bank types dc i/o standards commercial 1 industrial 2 i il 3 i ih 4 i il 3 i ih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 3.3 v pci 10 10 15 15 3.3 v pci-x 10 10 15 15 3.3 v gtl 10 10 15 15 2.5 v gtl 10 10 15 15 3.3 v gtl+ 10 10 15 15 2.5 v gtl+ 10 10 15 15 hstl (i) 10 10 15 15 hstl (ii) 10 10 15 15 sstl2 (i) 10 10 15 15 sstl2 (ii) 10 10 15 15 sstl3 (i) 10 10 15 15 sstl3 (ii) 10 10 15 15 notes: 1. commercial range (0c < t j < 85c) 2. industrial range (?40c < t j < 100c) 3. i il is the input leakage current pe r i/o pin over recommended operat ion conditions where ?0.3 v < v in < v il . 4. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges.
user i/os v2.0 2-167 summary of i/o timing characterist ics ? default i/o software settings table 2-87 ? summary of ac measuring points applicable to all i/o bank types standard input reference voltage (v ref_typ ) board termination voltage (v tt_ref ) measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos ? ? 1.4 v 2.5 v lvcmos ? ? 1.2 v 1.8 v lvcmos ? ? 0.90 v 1.5 v lvcmos ? ? 0.75 v 3.3 v pci ? ? 0.285 * v cci (rr) 0.615 * v cci (ff)) 3.3 v pci-x ? ? 0.285 * v cci (rr) 0.615 * v cci (ff) 3.3 v gtl 0.8 v 1.2 v v ref 2.5 v gtl 0.8 v 1.2 v v ref 3.3 v gtl+ 1.0 v 1.5 v v ref 2.5 v gtl+ 1.0 v 1.5 v v ref hstl (i) 0.75 v 0.75 v v ref hstl (ii) 0.75 v 0.75 v v ref sstl2 (i) 1.25 v 1.25 v v ref sstl2 (ii) 1.25 v 1.25 v v ref sstl3 (i) 1.5 v 1.485 v v ref sstl3 (ii) 1.5 v 1.485 v v ref lvds ? ? cross point lvpecl ? ? cross point table 2-88 ? i/o ac paramete r definitions parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer with schmitt trigger disabled t dout data to output buffer dela y through the i/o interface t eout enable to output buffer tristate control delay throug h the i/o interface t din input buffer to data dela y through the i/o interface t pys pad to data delay through the input buffer with schmitt trigger enabled t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay throug h the output buffer with delayed enable?z to high t zls enable to pad delay throug h the output buffer with delayed enable?z to low
fusion family of mi xed-signal flash fpgas device architecture 2-168 v2.0 table 2-89 ? summary of i/o timing characteris tics ? software default settings commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = i/o standard dependent applicable to pro i/os i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor (ohm) t dout t dp t din t py t py s t eout t zl t zh t lz t hz t zls t zhs units 3.3 v lvttl/ 3.3 v lvcmos 12 ma high 35 ? 0.49 2.74 0.03 0.90 1. 17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns 2.5 v lvcmos 12 ma high 35 ? 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns 1.8 v lvcmos 12 ma high 35 ? 0.49 2.83 0. 03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns 1.5 v lvcmos 12 ma high 35 ? 0.49 3.30 0. 03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns 3.3 v pci per pci spec high 10 25 2 0.49 2.09 0.03 0.78 1.25 0.32 2. 13 1.49 2.45 2.70 3.80 3.16 ns 3.3 v pci-x per pci-x spec high 10 25 2 0.49 2.09 0.03 0.77 1.17 0.32 2. 13 1.49 2.45 2.70 3.80 3.16 ns 3.3 v gtl 25 ma high 10 25 0.49 1.55 0.03 2.19 ? 0.32 1.52 1.55 0.00 0.00 3.19 3.22 ns 2.5 v gtl 25 ma high 10 25 0.49 1.59 0.03 1.83 ? 0.32 1.61 1.59 0.00 0.00 3.28 3.26 ns 3.3 v gtl+ 35 ma high 10 25 0.49 1.53 0.03 1.19 ? 0.32 1.56 1.53 0.00 0.00 3.23 3.20 ns 2.5 v gtl+ 33 ma high 10 25 0.49 1.65 0.03 1.13 ? 0.32 1.68 1.57 0.00 0.00 3.35 3.24 ns hstl (i) 8 ma high 20 50 0.49 2.37 0.03 1.59 ? 0.32 2.42 2.35 0.00 0.00 4.09 4.02 ns hstl (ii) 15 ma high 20 25 0.49 2.26 0.03 1.59 ? 0.32 2.30 2.03 0.00 0.00 3.97 3.70 ns sstl2 (i) 17 ma high 30 50 0.49 1.59 0.03 1.00 ? 0.32 1.62 1.38 0.00 0.00 3.29 3.05 ns sstl2 (ii) 21 ma high 30 25 0.49 1.62 0.03 1.00 ? 0.32 1.65 1.32 0.00 0.00 3.32 2.99 ns sstl3 (i) 16 ma high 30 50 0.49 1.72 0.03 0.93 ? 0.32 1.75 1.37 0.00 0.00 3.42 3.04 ns sstl3 (ii) 24 ma high 30 25 0.49 1.54 0.03 0.93 ? 0.32 1.57 1.25 0.00 0.00 3.24 2.92 ns lvds 24 ma high ? ? 0.49 1.57 0.03 1.36 ? ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 0.49 1.60 0.03 1.22 ? ? ? ? ? ? ? ? ns notes: 1. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-7 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-121 on page 2-198 for connectivity. this resistor is no t required during normal operation.
user i/os v2.0 2-169 table 2-90 ? summary of i/o timing characteris tics ? software default settings commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = i/o standard dependent applicable to advanced i/os i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor (ohm) t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 3.3 v lvttl/ 3.3 v lvcmos 12 ma high 35 pf ? 0.49 2.64 0.03 0.90 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns 2.5 v lvcmos 12 ma high 35 pf ? 0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 1.8 v lvcmos 12 ma high 3 5pf ? 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns 1.5 v lvcmos 12 ma high 35 pf ? 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns 3.3 v pci per pci spec high 10 pf 25 2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns 3.3 v pci-x per pci- x spec high 10 pf 25 2 0.49 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns lvds 24 ma high ? ? 0.49 1.37 0. 03 1.20 n/a n/a n/a n/a n/a n/a n/a ns lvpecl 24 ma high ? ? 0.49 1.34 0. 03 1.05 n/a n/a n/a n/a n/a n/a n/a ns notes: 1. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-7 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-121 on page 2-198 for connectivity. this resistor is no t required during normal operation.
fusion family of mi xed-signal flash fpgas device architecture 2-170 v2.0 table 2-91 ? summary of i/o timing characteris tics ? software default settings commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = i/o standard dependent applicable to standard i/os i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor (ohm) t dout t dp t din t py t eout t zl t zh t lz t hz units 3.3 v lvttl/ 3.3 v lvcmos 8 ma high 35 pf ? 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns 2.5 v lvcmos 8 ma high 35pf ? 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns 1.8 v lvcmos 4 ma high 35pf ? 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns 1.5 v lvcmos 2 ma high 35pf ? 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-7 for derating values.
user i/os v2.0 2-171 detailed i/o dc characteristics table 2-92 ? input capacitance symbol definition condi tions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 2-93 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down (ohms) 2 r pull-up (ohms) 3 applicable to pro i/o banks 3.3 v lvttl / 3.3 v lvcmos 4 ma 100 300 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 4 ma 100 200 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 3.3 v gtl 25 ma 11 ? 2.5 v gtl 25 ma 14 ? 3.3 v gtl+ 35 ma 12 ? notes: 1. these maximum values are provided for informatio nal reasons only. minimum output buffer resistance values depend on v cc , drive strength selection, temperature, an d process. for board design considerations and detailed output buffer resistances, use the corres ponding ibis models located on the actel website at http://www.actel.com/tech docs/models /ibis.html . 2. r (pull-down-max) = v olspec / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
fusion family of mi xed-signal flash fpgas device architecture 2-172 v2.0 2.5 v gtl+ 33 ma 15 ? hstl (i) 8 ma 50 50 hstl (ii) 15 ma 25 25 sstl2 (i) 17 ma 27 31 sstl2 (ii) 21 ma 13 15 sstl3 (i) 16 ma 44 69 sstl3 (ii) 24 ma 18 32 applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 table 2-93 ? i/o output buffer maximum resistances 1 (continued) standard drive strength r pull-down (ohms) 2 r pull-up (ohms) 3 notes: 1. these maximum values are provided for informatio nal reasons only. minimum output buffer resistance values depend on v cc , drive strength selection, temperature, an d process. for board design considerations and detailed output buffer resistances, use the corres ponding ibis models located on the actel website at http://www.actel.com/tech docs/models /ibis.html . 2. r (pull-down-max) = v olspec / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
user i/os v2.0 2-173 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 applicable to standard i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 table 2-94 ? i/o weak pull-up/pull-down resistances minimum and maximum we ak pull-up/pull-down resistance values v cci r (weak pull-up) 1 (ohms) r (weak pull-down) 2 (ohms) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-down-max) = v olspec / i weak pull-down-min 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i weak pull-up-min table 2-93 ? i/o output buffer maximum resistances 1 (continued) standard drive strength r pull-down (ohms) 2 r pull-up (ohms) 3 notes: 1. these maximum values are provided for informatio nal reasons only. minimum output buffer resistance values depend on v cc , drive strength selection, temperature, an d process. for board design considerations and detailed output buffer resistances, use the corres ponding ibis models located on the actel website at http://www.actel.com/tech docs/models /ibis.html . 2. r (pull-down-max) = v olspec / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
fusion family of mi xed-signal flash fpgas device architecture 2-174 v2.0 table 2-95 ? i/o short currents i osh /i osl drive strength i osh (ma)* i osl (ma)* applicable to pro i/o banks 3.3 v lvttl / 3.3 v lvcmos 4 ma 25 27 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 2.5 v lvcmos 4 ma 16 18 8 ma 32 37 12 ma 65 74 16 ma 83 87 24 ma 169 124 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 45 51 12 ma 91 74 16 ma 91 74 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 6 ma 32 39 8 ma 66 55 12 ma 66 55 applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 note: *t j = 100c
user i/os v2.0 2-175 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 36 ma i/o setting, whic h is the worst case for this type of analysis. for example, at 100c, the short current condition would have to be sustained for more than six months to cause a reliability concern. the i/o desi gn does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 12 ma 65 74 16 ma 83 87 24 ma 169 124 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 45 51 12 ma 91 74 16 ma 91 74 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 6 ma 32 39 8 ma 66 55 12 ma 66 55 3.3 v pci/pci-x per pci/pci-x specification 103 109 applicable to standard i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 1.5 v lvcmos 2 ma 13 16 table 2-95 ? i/o short currents i osh /i osl (continued) drive strength i osh (ma)* i osl (ma)* note: *t j = 100c
fusion family of mi xed-signal flash fpgas device architecture 2-176 v2.0 table 2-96 ? short current event duration before failure temperature time before failure ?40c >20 years 0c >20 years 25c >20 years 70c 5 years 85c 2 years 100c 6 months table 2-97 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer configuration hysteresis value (typ.) 3.3 v lvttl/lvcmos/pci/pci-x (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmi tt trigger mode) 80 mv 1.5 v lvcmos (schmi tt trigger mode) 60 mv table 2-98 ? i/o input rise time, fall time, and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos (schmitt trigger disabled) no requirement 10 ns* 20 years (100c) lvttl/lvcmos (schmitt trigger enabled) no requirement no requirement, but input noise voltage cannot exceed schmitt hysteresis 20 years (100c) hstl/sstl/gtl no requirement 10 ns* 10 years (100c) lvds/blvds/m-lvds/lvpecl no requ irement 10 ns* 10 years (100c) note: *the maximum input rise/fall time is related only to the noise induced into the input buffer trace. if the noise is low, the rise time and fall time of input bu ffers, when schmitt trigger is disabled, can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals.
user i/os v2.0 2-177 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. the 3.3 v lvcmos standard is supported as part of the 3.3 v lvttl support. table 2-99 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 applicable to pro i/o banks 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 applicable to standard i/o banks 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation condit ions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-117 ? ac loading test point test point enable path data path 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zhs /t zl /t zls 5 pf for t hz /t lz
fusion family of mi xed-signal flash fpgas device architecture 2-178 v2.0 timing characteristics table 2-100 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 03.31.4?35 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. table 2-101 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29 ns ?1 0.56 9.36 0.04 1.02 1.33 0. 36 9.54 7.70 2.29 2.08 11.44 9.60 ns ?2 0.49 8.22 0.03 0.90 1.17 0. 32 8.37 6.76 2.01 1.82 10.04 8.43 ns 8 ma std. 0.66 7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68 ns ?1 0.56 6.69 0.04 1.02 1.33 0. 36 6.81 5.48 2.58 2.61 8.71 7.38 ns ?2 0.49 5.87 0.03 0.90 1.17 0. 32 5.98 4.81 2.27 2.29 7.65 6.48 ns 12 ma std. 0.66 6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26 ns ?1 0.56 5.13 0.04 1.02 1.33 0. 36 5.22 4.27 2.79 2.95 7.12 6.17 ns ?2 0.49 4.50 0.03 0.90 1.17 0. 32 4.58 3.75 2.45 2.59 6.25 5.42 ns 16 ma std. 0.66 5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96 ns ?1 0.56 4.78 0.04 1.02 1.33 0. 36 4.87 4.02 2.83 3.04 6.77 5.92 ns ?2 0.49 4.20 0.03 0.90 1.17 0. 32 4.27 3.53 2.48 2.67 5.94 5.20 ns 24 ma std. 0.66 5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93 ns ?1 0.56 4.46 0.04 1.02 1.33 0. 36 4.54 3.99 2.88 3.37 6.44 5.89 ns ?2 0.49 3.92 0.03 0.90 1.17 0. 32 3.99 3.50 2.53 2.96 5.66 5.17 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-179 table 2-102 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 7.88 0. 04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94 ns ?1 0.56 6.71 0.04 1. 02 1.33 0.36 6.83 5.70 2. 29 2.20 8.73 7.60 ns ?2 0.49 5.89 0.03 0. 90 1.17 0.32 6.00 5.01 2. 01 1.93 7.67 6.67 ns 8 ma std. 0.66 5.08 0. 04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38 ns ?1 0.56 4.32 0.04 1. 02 1.33 0.36 4.40 3.52 2. 59 2.73 6.30 5.43 ns ?2 0.49 3.79 0.03 0. 90 1.17 0.32 3.86 3.09 2. 28 2.40 5.53 4.76 ns 12 ma std. 0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11 ns ?1 0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34 ns ?2 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns 16 ma std. 0.66 3.46 0. 04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84 ns ?1 0.56 2.95 0.04 1. 02 1.33 0.36 3.00 2.22 2. 83 3.17 4.90 4.12 ns ?2 0.49 2.59 0.03 0. 90 1.17 0.32 2.63 1.95 2. 49 2.78 4.30 3.62 ns 24 ma std. 0.66 3.21 0. 04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39 ns ?1 0.56 2.73 0.04 1. 02 1.33 0.36 2.78 1.83 2. 88 3.51 4.68 3.74 ns ?2 0.49 2.39 0.03 0. 90 1.17 0.32 2.44 1.61 2. 53 3.08 4.11 3.28 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-180 v2.0 table 2-103 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 10.26 0.04 1.20 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns ?1 0.56 8.72 0.04 1.02 0.36 8. 89 7.57 2.25 2.09 10.79 9.47 ns ?2 0.49 7.66 0.03 0.90 0.32 7. 80 6.64 1.98 1.83 9.47 8.31 ns 8 ma std. 0.66 7.27 0.04 1.20 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns ?1 0.56 6.19 0.04 1.02 0.36 6. 30 5.35 2.54 2.59 8.20 7.25 ns ?2 0.49 5.43 0.03 0.90 0.32 5. 53 4.69 2.23 2.27 7.20 6.36 ns 12 ma std. 0.66 5.58 0.04 1.20 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns ?1 0.56 4.75 0.04 1.02 0.36 4. 84 4.14 2.73 2.91 6.74 6.05 ns ?2 0.49 4.17 0.03 0.90 0.32 4. 24 3.64 2.39 2.55 5.91 5.31 ns 16 ma std. 0.66 5.21 0.04 1.20 0.43 5.30 4.56 3.26 3.51 7.54 6.80 ns ?1 0.56 4.43 0.04 1.02 0.36 4. 51 3.88 2.77 2.99 6.41 5.79 ns ?2 0.49 3.89 0.03 0.90 0.32 3. 96 3.41 2.43 2.62 5.63 5.08 ns 24 ma std. 0.66 4.85 0.04 1.20 0.43 4. 94 4.54 3.32 3.88 7.18 6.78 ns ?1 0.56 4.13 0.04 1.02 0.36 4. 20 3.87 2.82 3.30 6.10 5.77 ns ?2 0.49 3.62 0.03 0.90 0.32 3. 69 3.39 2.48 2.90 5.36 5.06 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-181 table 2-104 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 7.66 0.04 1.20 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns ?1 0.56 6.51 0.04 1.02 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns ?2 0.49 5.72 0.03 0.90 0.32 5. 82 4.92 1.98 1.95 7.49 6.59 ns 8 ma std. 0.66 4.91 0.04 1.20 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns ?1 0.56 4.17 0.04 1.02 0.36 4. 25 3.46 2.54 2.73 6.15 5.36 ns ?2 0.49 3.66 0.03 0.90 0.32 3. 73 3.04 2.23 2.39 5.40 4.71 ns 12 ma std. 0.66 3.53 0.04 1.20 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns ?1 0.56 3.00 0.04 1.02 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns ?2 0.49 2.64 0.03 0.90 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns 16 ma std. 0.66 3.33 0.04 1.20 0.43 3.39 2.56 3.26 3.68 5.63 4.80 ns ?1 0.56 2.83 0.04 1.02 0.36 2. 89 2.18 2.77 3.13 4.79 4.08 ns ?2 0.49 2.49 0.03 0.90 0.32 2. 53 1.91 2.44 2.75 4.20 3.58 ns 24 ma std. 0.66 3.08 0.04 1.20 0.43 3.13 2.12 3.32 4.06 5.37 4.35 ns ?1 0.56 2.62 0.04 1.02 0.36 2. 66 1.80 2.83 3.45 4.57 3.70 ns ?2 0.49 2.30 0.03 0.90 0.32 2. 34 1.58 2.48 3.03 4.01 3.25 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-105 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns ?1 0.56 8.05 0.04 0.85 0. 36 8.20 7.27 1.76 1.73 ns ?2 0.49 7.07 0.03 0.75 0. 32 7.20 6.38 1.55 1.52 ns 4 ma std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns ?1 0.56 8.05 0.04 0.85 0. 36 8.20 7.27 1.76 1.73 ns ?2 0.49 7.07 0.03 0.75 0. 32 7.20 6.38 1.55 1.52 ns 6 ma std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns ?1 0.56 5.59 0.04 0.85 0. 36 5.69 5.09 2.04 2.19 ns ?2 0.49 4.91 0.03 0.75 0. 32 5.00 4.47 1.79 1.92 ns 8 ma std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns ?1 0.56 5.59 0.04 0.85 0. 36 5.69 5.09 2.04 2.19 ns ?2 0.49 4.91 0.03 0.75 0. 32 5.00 4.47 1.79 1.92 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-182 v2.0 table 2-106 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns ?1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns ?2 2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns 4 ma std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns ?1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns ?2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns 6 ma std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns ?1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns ?2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns 8 ma std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns ?1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns ?2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-183 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. it uses a 5 v?tolerant input buffer and push-pull output buffer. table 2-107 ? minimum and maximum dc input and output levels 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 applicable to pro i/o banks 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 10 10 applicable to standard i/o banks 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation condit ions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommend ed operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-118 ? ac loading test point test point enable path data path 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zhs /t zl /t zls 5 pf for t hz /t lz
fusion family of mi xed-signal flash fpgas device architecture 2-184 v2.0 timing characteristics table 2-108 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 02.51.2?35 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. table 2-109 ? 2.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 12.00 0.04 1.51 1.66 0. 43 12.23 11.61 2.72 2.20 14.46 13.85 ns ?1 0.51 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78 ns ?2 0.45 8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34 ns 8 ma std. 0.60 8.73 0.04 1.51 1.66 0. 43 8.89 8.01 3.10 2.93 11.13 10.25 ns ?1 0.51 7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72 ns ?2 0.45 6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65 ns 12 ma std. 0.66 6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34 ns ?1 0.56 5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10 ns ?2 0.49 5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23 ns 16 ma std. 0.66 6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96 ns ?1 0.56 5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77 ns ?2 0.49 4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95 ns 24 ma std. 0.66 5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94 ns ?1 0.56 5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75 ns ?2 0.49 4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-185 table 2-110 ? 2.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 8.82 0.04 1.51 1.66 0. 43 8.13 8.82 2.72 2.29 10.37 11.05 ns ?1 0.51 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40 ns ?2 0.45 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25 ns 8 ma std. 0.60 5.27 0.04 1.51 1.66 0. 43 5.27 5.27 3.10 3.03 7.50 7.51 ns ?1 0.51 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38 ns ?2 0.45 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61 ns 12 ma std. 0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73 ns ?1 0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87 ns ?2 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns 16 ma std. 0.66 3.53 0.04 1.51 1.66 0. 43 3.59 3.12 3.42 3.62 5.83 5.35 ns ?1 0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55 ns ?2 0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00 ns 24 ma std. 0.66 3.26 0.04 1.51 1.66 0. 43 3.32 2.48 3.49 4.11 5.56 4.72 ns ?1 0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01 ns ?2 0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-111 ? 2.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns ?1 0.56 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns ?2 0.49 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns 8 ma std. 0.66 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns ?1 0.56 6.77 0.04 1.11 0.36 6. 90 6.65 2.59 2.46 8.80 8.55 ns ?2 0.49 5.94 0.03 0.98 0.32 6. 05 5.84 2.28 2.16 7.72 7.50 ns 12 ma std. 0.66 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.56 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.49 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns 16 ma std. 0.66 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.56 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.49 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns 24 ma std. 0.66 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.56 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.49 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-186 v2.0 table 2-112 ? 2.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 8.66 0.04 1.31 0.43 7. 83 8.66 2.68 2.30 10.07 10.90 ns ?1 0.56 7.37 0.04 1.11 0.36 6. 66 7.37 2.28 1.96 8.56 9.27 ns ?2 0.49 6.47 0.03 0.98 0.32 5. 85 6.47 2.00 1.72 7.52 8.14 ns 8 ma std. 0.66 5.17 0. 04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns ?1 0.56 4.39 0.04 1.11 0.36 4. 28 4.39 2.59 2.55 6.19 6.30 ns ?2 0.49 3.86 0.03 0.98 0.32 3. 76 3.86 2.28 2.24 5.43 5.53 ns 12 ma std. 0.66 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns ?1 0.56 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns ?2 0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 16 ma std. 0.66 3.35 0. 04 1.31 0.43 3.41 3.06 3.36 3.55 5.65 5.30 ns ?1 0.56 2.85 0.04 1.11 0.36 2. 90 2.60 2.86 3.02 4.81 4.51 ns ?2 0.49 2.50 0.03 0.98 0.32 2. 55 2.29 2.51 2.65 4.22 3.96 ns 24 ma std. 0.66 3.56 0. 04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns ?1 0.56 3.03 0.04 1.11 0.36 3. 08 2.92 2.81 2.92 4.99 4.82 ns ?2 0.49 2.66 0.03 0.98 0.32 2. 71 2.56 2.47 2.57 4.38 4.23 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-113 ? 2.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns ?1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns ?2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns 4 ma std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns ?1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns ?2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns 6 ma std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns ?1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns ?2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns 8 ma std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns ?1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns ?2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-187 table 2-114 ? 2.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns ?1 0.56 6.98 0.04 1.10 0. 36 6.16 6.98 1.73 1.62 ns ?2 0.49 6.13 0.03 0.96 0. 32 5.41 6.13 1.52 1.43 ns 4 ma std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns ?1 0.56 6.98 0.04 1.10 0. 36 6.16 6.98 1.73 1.62 ns ?2 0.49 6.13 0.03 0.96 0. 32 5.41 6.13 1.52 1.43 ns 6 ma std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns ?1 0.56 4.05 0.04 1.10 0. 36 3.87 4.05 2.03 2.17 ns ?2 0.49 3.56 0.03 0.96 0. 32 3.40 3.56 1.78 1.91 ns 8 ma std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns ?1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns ?2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-188 v2.0 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and push-pull output buffer. table 2-115 ? minimum and maximum dc input and output levels 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 applicable to pro i/o banks 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 16 16 74 91 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 16 16 74 91 10 10 applicable to standard i/o banks 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation condit ions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommend ed operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-119 ? ac loading test point test point enable path data path 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zhs /t zl /t zls 5 pf for t hz /t lz
user i/os v2.0 2-189 timing characteristics table 2-116 ? ac waveforms, measuring points, and capacitive loads input low (v) input low (v) measuring point* (v) v ref (typ.) (v) c load (pf) 01.80.9?35 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. table 2-117 ? 1.8 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07 ns ?1 0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37 ns ?2 0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50 ns 4 ma std. 0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99 ns ?1 0.56 9.69 0.04 1.23 1.62 0.36 9. 87 9.15 2.77 2.36 11.77 11.05 ns ?2 0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70 ns 8 ma std. 0.66 8.97 0.04 1.45 1.91 0. 43 9.14 8.10 3.57 3.36 11.37 10.33 ns ?1 0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79 ns ?2 0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72 ns 12 ma std. 0.66 8.35 0.04 1.45 1.91 0. 43 8.50 7.59 3.64 3.52 10.74 9.82 ns ?1 0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35 ns ?2 0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33 ns 16 ma std. 0.66 7.94 0.04 1.45 1.91 0. 43 8.09 7.56 3.74 4.11 10.32 9.80 ns ?1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns ?2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-190 v2.0 table 2-118 ? 1.8 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 12.10 0.04 1.45 1.91 0. 43 9.59 12.10 2.78 1. 64 11.83 14.34 ns ?1 0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20 ns ?2 0.49 9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71 ns 4 ma std. 0.66 7.05 0.04 1.45 1.91 0. 43 6.20 7.05 3.25 2.86 8.44 9.29 ns ?1 0.56 6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90 ns ?2 0.49 5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94 ns 8 ma std. 0.66 4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76 ns ?1 0.56 3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75 ns ?2 0.49 3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05 ns 12 ma std. 0.66 4.12 0.04 1.45 1.91 0.43 4.20 3.99 3.63 3.62 6.43 6.23 ns ?1 0.56 3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30 ns ?2 0.49 3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65 ns 16 ma std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns ?1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns ?2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-191 table 2-119 ? 1.8 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 15.53 0.04 1.31 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns ?1 0.56 13.21 0.04 1.11 0.36 12. 01 13.21 2.36 1.36 13.91 15.11 ns ?2 2 0.49 11.60 0.03 0.98 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns 4 ma std. 0.66 10.48 0.04 1.31 0.43 10.41 10.48 3.23 2.73 12.65 12.71 ns ?1 0.56 8.91 0.04 1. 11 0.36 8.86 8.91 2.75 2. 33 10.76 10.81 ns ?2 0.49 7.82 0.03 0.98 0.32 7. 77 7.82 2.41 2.04 9.44 9.49 ns 8 ma std. 0.66 8.05 0. 04 1.31 0.43 8.20 7.84 3.54 3.27 10.43 10.08 ns ?1 0.56 6.85 0.04 1.11 0.36 6. 97 6.67 3.01 2.78 8.88 8.57 ns ?2 0.49 6.01 0.03 0.98 0.32 6. 12 5.86 2.64 2.44 7.79 7.53 ns 12 ma std. 0.66 7.50 0. 04 1.31 0.43 7.64 7.30 3. 61 3.41 9.88 9.53 ns ?1 0.56 6.38 0.04 1.11 0.36 6. 50 6.21 3.07 2.90 8.40 8.11 ns ?2 0.49 5.60 0.03 0.98 0.32 5. 71 5.45 2.69 2.55 7.38 7.12 ns 16 ma std. 0.66 7.29 0. 04 1.31 0.43 7.23 7.29 3. 71 3.95 9.47 9.53 ns ?1 0.56 6.20 0.04 1.11 0.36 6. 15 6.20 3.15 3.36 8.06 8.11 ns ?2 0.49 5.45 0.03 0.98 0.32 5. 40 5.45 2.77 2.95 7.07 7.12 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-192 v2.0 table 2-120 ? 1.8 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77 1.66 11.37 14.10 ns ?1 0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns ?2 0.49 8.86 0.03 0.91 0.32 6. 82 8.86 2.07 1.24 8.49 10.53 ns 4 ma std. 0.66 6.91 0.04 1.22 0.43 5.86 6.91 3.22 2.84 8.10 9.15 ns ?1 0.56 5.88 0.04 1.04 0.36 4.99 5.88 2.74 2.41 6.89 7.78 ns ?2 0.49 5.16 0.03 0.91 0.32 4.38 5.16 2.41 2.12 6.05 6.83 ns 8 ma std. 0.66 4.45 0.04 1.22 0.43 4.18 4.45 3.53 3.38 6.42 6.68 ns ?1 0.56 3.78 0.04 1.04 0.36 3.56 3.78 3.00 2.88 5.46 5.69 ns ?2 0.49 3.32 0.03 0.91 0.32 3.12 3.32 2.64 2.53 4.79 4.99 ns 12 ma std. 0.66 3.92 0.04 1.22 0.43 3.93 3.92 3.60 3.52 6.16 6.16 ns ?1 0.56 3.34 0.04 1.04 0.36 3.34 3.34 3.06 3.00 5.24 5.24 ns ?2 0.49 2.93 0.03 0.91 0.32 2.93 2.93 2.69 2.63 4.60 4.60 ns 16 ma std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns ?1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns ?2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-121 ? 1.8 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 15.01 0.04 1.20 0.43 13.15 15.01 1.99 1.99 ns ?1 0.56 12.77 0.04 1.02 0.36 11.19 12.77 1.70 1.70 ns ?2 0.49 11.21 0.03 0.90 0.32 9.82 11.21 1.49 1.49 ns 4 ma std. 0.66 10.10 0.04 1.20 0.43 9.55 10.10 2.41 2.37 ns ?1 0.56 8.59 0.04 1.02 0. 36 8.13 8.59 2.05 2.02 ns ?2 0.49 7.54 0.03 0.90 0. 32 7.13 7.54 1.80 1.77 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-193 table 2-122 ? 1.8 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 11.21 0.04 1.20 0.43 8.53 11.21 1.99 1.21 ns ?1 0.56 9.54 0.04 1.02 0.36 7.26 9.54 1.69 1.03 ns ?2 0.49 8.37 0.03 0.90 0.32 6.37 8.37 1.49 0.90 ns 4 ma std. 0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48 ns ?1 0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11 ns ?2 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-194 v2.0 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and push-pull output buffer. table 2-123 ? minimum and maximum dc input and output levels 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 applicable to pro i/o banks 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 16 13 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 33 25 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 6 6 39 32 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 8 8 55 66 10 10 12 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 12 12 55 66 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 2 2 16 13 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 4 4 33 25 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 6 6 39 32 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 8 8 55 66 10 10 12 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 12 12 55 66 10 10 applicable to pro i/o banks 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 16 13 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation condit ions where ?0.3 v < v in < v il . 2. i ih is the input leakage curren t per i/o pin over recommend ed operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-120 ? ac loading table 2-124 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 1.5 0.75 ? 35 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point test point enable path data path 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zhs /t zl /t zls 5 pf for t hz /t lz
user i/os v2.0 2-195 timing characteristics table 2-125 ? 1.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 14.11 0.04 1.70 2.14 0 .43 14.37 13.14 3.40 2. 68 16.61 15.37 ns ?1 0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08 ns ?2 0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48 ns 4 ma std. 0.66 11.23 0.04 1.70 2.14 0 .43 11.44 9.87 3.77 3.36 13.68 12.10 ns ?1 0.56 9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29 ns ?2 0.49 8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04 ns 8 ma std. 0.66 10.45 0.04 1.70 2.14 0 .43 10.65 9.24 3.84 3.55 12.88 11.48 ns ?1 0.56 8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76 ns ?2 0.49 7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57 ns 12 ma std. 0.66 10.02 0.04 1.70 2.14 0 .43 10.20 9.23 3.97 4.22 12.44 11.47 ns ?1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns ?2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-126 ? 1.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 8.53 0.04 1.70 2.14 0. 43 7.26 8.53 3.39 2.79 9.50 10.77 ns ?1 0.56 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16 ns ?2 0.49 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04 ns 4 ma std. 0.66 5.41 0.04 1.70 2.14 0. 43 5.22 5.41 3.75 3.48 7.45 7.65 ns ?1 0.56 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50 ns ?2 0.49 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71 ns 8 ma std. 0.66 4.80 0.04 1.70 2.14 0. 43 4.89 4.75 3.83 3.67 7.13 6.98 ns ?1 0.56 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94 ns ?2 0.49 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21 ns 12 ma std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns ?1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns ?2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-196 v2.0 table 2-127 ? 1.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 12.78 0.04 1.31 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns ?1 0.56 10.87 0.04 1. 11 0.36 10.90 10.87 2.89 2. 25 12.80 12.78 ns ?2 0.49 9.55 0.03 0. 98 0.32 9.57 9.55 2.54 1. 97 11.24 11.22 ns 4 ma std. 0.66 10.01 0.04 1.31 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns ?1 0.56 8.51 0.04 1. 11 0.36 8.67 8.12 3.19 2. 78 10.57 10.02 ns ?2 0.49 7.47 0.03 0.98 0.32 7. 61 7.13 2.80 2.44 9.28 8.80 ns 8 ma std. 0.66 9.33 0.04 1.31 0.43 9.51 8.89 3.83 3.43 11.74 11.13 ns ?1 0.56 7.94 0.04 1.11 0.36 8. 09 7.56 3.26 2.92 9.99 9.47 ns ?2 0.49 6.97 0.03 0.98 0.32 7. 10 6.64 2.86 2.56 8.77 8.31 ns 12 ma std. 0.66 8.91 0.04 1.31 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns ?1 0.56 7.58 0.04 1.11 0.36 7. 72 7.57 3.36 3.44 9.62 9.47 ns ?2 0.49 6.65 0.03 0.98 0.32 6. 78 6.64 2.95 3.02 8.45 8.31 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-128 ? 1.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 8.36 0. 04 1.44 0.43 6.82 8.36 3. 39 2.77 9.06 10.60 ns ?1 0.56 7.11 0.04 1.22 0.36 5. 80 7.11 2.88 2.35 7.71 9.02 ns ?2 0.49 6.24 0.03 1.07 0.32 5. 10 6.24 2.53 2.06 6.76 7.91 ns 4 ma std. 0.66 5.31 0. 04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns ?1 0.56 4.52 0.04 1.22 0.36 4. 13 4.52 3.18 2.89 6.03 6.42 ns ?2 0.49 3.97 0.03 1.07 0.32 3. 62 3.97 2.79 2.54 5.29 5.64 ns 8 ma std. 0.66 4.67 0. 04 1.44 0.43 4.55 4.67 3.82 3.56 6.78 6.90 ns ?1 0.56 3.97 0.04 1.22 0.36 3. 87 3.97 3.25 3.03 5.77 5.87 ns ?2 0.49 3.49 0.03 1.07 0.32 3. 40 3.49 2.85 2.66 5.07 5.16 ns 12 ma std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns ?1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns ?2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-197 table 2-129 ? 1.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns ?1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns ?2 0.49 9.21 0.03 1.06 0. 32 8.81 9.21 1.83 1.73 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-130 ? 1.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns ?1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns ?2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-198 v2.0 3.3 v pci, 3.3 v pci-x the peripheral component interface for 3.3 v st andard specifies suppor t for 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pc i/pci-x specifications for the da tapath; actel loadings for enable path characterization are described in figure 2-121 . ac loadings are defined per pci/pci-x specificatio ns for the data path; actel loading for tristate is described in table 2-132 . table 2-131 ? minimum and maximum dc input and output levels 3.3 v pci/pci-x v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 per pci specification per pci curves 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-121 ? ac loading test point enable path r = 1 k test point data path r = 25 r to v cci for t dp (f) r to gnd for t dp (r) r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 10 pf for t zh /t zhs /t zl /t zls 5 pf for t hz /t lz table 2-132 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) c load (pf) 0 3.3 0.285 * v cci for t dp(r) 0.615 * v cci for t dp(f) ?10 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points.
user i/os v2.0 2-199 timing characteristics table 2-133 ? 3.3 v pci/pci-x commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to pro i/os speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.81 0.04 1.05 1.67 0. 43 2.86 2.00 3.28 3.61 5.09 4.23 ns ?1 0.56 2.39 0.04 0.89 1.42 0. 36 2.43 1.70 2.79 3.07 4.33 3.60 ns ?2 0.49 2.09 0.03 0.78 1.25 0. 32 2.13 1.49 2.45 2.70 3.80 3.16 ns note: for the derating values at specific junction te mperature and voltage s upply levels, refer to table 3-7 on page 3-9 . table 2-134 ? 3.3 v pci/pci-x commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/os speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.68 0.04 0.86 0.43 2. 73 1.95 3.21 3.58 4.97 4.19 0.66 ns ?1 0.56 2.28 0.04 0.73 0.36 2. 32 1.66 2.73 3.05 4.22 3.56 0.56 ns ?2 0.49 2.00 0.03 0.65 0.32 2. 04 1.46 2.40 2.68 3.71 3.13 0.49 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-200 v2.0 voltage referenced i/o characteristics 3.3 v gtl gunning transceiver logic is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an op en-drain output buffer. the v cci pin should be connected to 3.3 v. timing characteristics table 2-135 ? minimum and maximum dc input and output levels 3.3 v gtl v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 25 ma 3 ?0.3 v ref ? 0.05 v ref + 0.05 3.6 0.4 ? 25 25 181 268 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation condit ions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-122 ? ac loading table 2-136 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.05 v ref + 0.05 0.8 0.8 1.2 10 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 10 pf 25 gtl v tt table 2-137 ? 3.3 v gtl commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v, v ref = 0.8 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.08 0.04 2.93 0.43 2.04 2.08 4.27 4.31 ns ?1 0.56 1.77 0.04 2.50 0.36 1.73 1.77 3.63 3.67 ns ?2 0.49 1.55 0.03 2.19 0.32 1.52 1.55 3.19 3.22 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-201 2.5 v gtl gunning transceiver logic is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the v cci pin should be connected to 2.5 v. timing characteristics table 2-138 ? minimum and maximum dc input and output levels 2.5 gtl v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 25 ma 3 ?0.3 v ref ? 0.05 v ref + 0.05 3.6 0.4 ? 25 25 124 169 10 10 notes: 1. i il is the input leakag e current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended oper ating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-123 ? ac loading table 2-139 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.05 v ref + 0.05 0.8 0.8 1.2 10 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 10 pf 25 gtl v tt table 2-140 ? 2.5 v gtl commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v, v ref = 0.8 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.13 0.04 2.46 0.43 2.16 2.13 4.40 4.36 ns ?1 0.56 1.81 0.04 2.09 0.36 1.84 1.81 3.74 3.71 ns ?2 0.49 1.59 0.03 1.83 0.32 1.61 1.59 3.28 3.26 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-202 v2.0 3.3 v gtl+ gunning transceiver logic plus is a high-speed bu s standard (jesd8-3). it provides a differential amplifier input buffer and an op en-drain output buffer. the v cci pin should be connected to 3.3 v. timing characteristics table 2-141 ? minimum and maximum dc input and output levels 3.3 v gtl+ v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v m a m a max., ma 3 max., ma 3 a 4 a 4 35 ma ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.6 ? 35 35 181 268 10 10 notes: 1. i il is the input leakage current pe r i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-124 ? ac loading table 2-142 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.1 v ref + 0.1 1.0 1.0 1.5 10 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 10 pf 25 gtl+ v tt table 2-143 ? 3.3 v gtl+ commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v, v ref = 1.0 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.06 0.04 1.59 0.43 2.09 2.06 4.33 4.29 ns ?1 0.56 1.75 0.04 1.35 0.36 1.78 1.75 3.68 3.65 ns ?2 0.49 1.53 0.03 1.19 0.32 1.56 1.53 3.23 3.20 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-203 2.5 v gtl+ gunning transceiver logic plus is a high-speed bu s standard (jesd8-3). it provides a differential amplifier input buffer and an op en-drain output buffer. the v cci pin should be connected to 2.5 v. timing characteristics table 2-144 ? minimum and maximum dc input and output levels 2.5 v gtl+ v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., vmama max., ma 3 max., ma 3 a 4 a 4 33 ma ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.6 ? 33 33 124 169 10 10 notes: 1. i il is the input leakage current pe r i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-125 ? ac loading table 2-145 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.1 v ref + 0.1 1.0 1.0 1.5 10 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 10 pf 25 gtl+ v tt table 2-146 ? 2.5 v gtl+ commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v, v ref = 1.0 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.21 0.04 1.51 0.43 2.25 2.10 4.48 4.34 ns ?1 0.56 1.88 0.04 1.29 0.36 1.91 1.79 3.81 3.69 ns ?2 0.49 1.65 0.03 1.13 0.32 1.68 1.57 3.35 4.34 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-204 v2.0 hstl class i high-speed transceiver logic is a general-purpos e high-speed 1.5 v bus standard (eia/jesd8-6). fusion devices support class i. this provides a di fferential amplifier inpu t buffer and a push-pull output buffer. timing characteristics table 2-147 ? minimum and maximum dc input and output levels hstl class i v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 8 ma ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cci ? 0.4 8 8 39 32 10 10 notes: 1. i il is the input leakage current per i/o pin over re commended operation condit ions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-126 ? ac loading table 2-148 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.1 v ref + 0.1 0.75 0.75 0.75 20 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 20 pf 50 hstl class i v tt table 2-149 ? hstl class i commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v, v ref = 0.75 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 3.18 0.04 2.12 0.43 3.24 3.14 5.47 5.38 ns ?1 0.56 2.70 0.04 1.81 0.36 2.75 2.67 4.66 4.58 ns ?2 0.49 2.37 0.03 1.59 0.32 2.42 2.35 4.09 4.02 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-205 hstl class ii high-speed transceiver logic is a general-purpos e high-speed 1.5 v bus standard (eia/jesd8-6). fusion devices support class ii. this provides a di fferential amplifier inpu t buffer and a push-pull output buffer. timing characteristics table 2-150 ? minimum and maximum dc input and output levels hstl class ii v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 15 ma 3 ?0.3 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cci ? 0.4 15 15 55 66 10 10 note: 1. i il is the input leakage current per i/o pin over re commended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. output drive strength is below jedec specification. figure 2-127 ? ac loading table 2-151 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.1 v ref + 0.1 0.75 0.75 0.75 20 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 20 pf 25 hstl class ii v tt table 2-152 ? hstl class ii commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v, v ref = 0.75 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 3.02 0.04 2.12 0.43 3.08 2.71 5.32 4.95 ns ?1 0.56 2.57 0.04 1.81 0.36 2.62 2.31 4.52 4.21 ns ?2 0.49 2.26 0.03 1.59 0.32 2.30 2.03 3.97 3.70 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-206 v2.0 sstl2 class i stub-speed terminated logic for 2.5 v memory bu s standard (jesd8-9). fusion devices support class i. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-153 ? minimum and maximum dc input and output levels sstl2 class i v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 15 ma ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.54 v cci ? 0.62 15 15 87 83 10 10 notes: 1. i il is the input leakage current pe r i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-128 ? ac loading table 2-154 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.2 v ref + 0.2 1.25 1.25 1.25 30 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 30 pf 50 25 sstl2 class i v tt table 2-155 ? sstl 2 class i commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v, v ref = 1.25 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.13 0.04 1.33 0.43 2.17 1.85 4.40 4.08 ns ?1 0.56 1.81 0.04 1.14 0.36 1.84 1.57 3.74 3.47 ns ?2 0.49 1.59 0.03 1.00 0.32 1.62 1.38 3.29 3.05 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-207 sstl2 class ii stub-speed terminated logic for 2.5 v memory bu s standard (jesd8-9). fusion devices support class ii. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-156 ? minimum and maximum dc input and output levels sstl2 class ii v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 18 ma ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.35 v cci ? 0.43 18 18 124 169 10 10 notes: 1. i il is the input leakage current pe r i/o pin over recommended operat ion conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-129 ? ac loading table 2-157 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.2 v ref + 0.2 1.25 1.25 1.25 30 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 30 pf 25 25 sstl2 class ii v tt table 2-158 ? sstl 2 class ii commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v, v ref = 1.25 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.17 0.04 1.33 0.43 2.21 1.77 4.44 4.01 ns ?1 0.56 1.84 0.04 1.14 0.36 1.88 1.51 3.78 3.41 ns ?2 0.49 1.62 0.03 1.00 0.32 1.65 1.32 3.32 2.99 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-208 v2.0 sstl3 class i stub-speed terminated logic for 3.3 v memory bu s standard (jesd8-8). fusion devices support class i. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-159 ? minimum and maximum dc input and output levels sstl3 class i v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 14 ma ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.7 v cci ? 1.1 14 14 54 51 10 10 notes: 1. i il is the input leakag e current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended oper ating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-130 ? ac loading table 2-160 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.2 v ref + 0.2 1.5 1.5 1.485 30 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 30 pf 50 25 sstl3 class i v tt table 2-161 ? sstl3 class i commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v, v ref = 1.5 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.31 0.04 1.25 0.43 2.35 1.84 4.59 4.07 ns ?1 0.56 1.96 0.04 1.06 0.36 2.00 1.56 3.90 3.46 ns ?2 0.49 1.72 0.03 0.93 0.32 1.75 1.37 3.42 3.04 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-209 sstl3 class ii stub-speed terminated logic for 3.3 v memory bu s standard (jesd8-8). fusion devices support class ii. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-162 ? minimum and maximum dc input and output levels sstl3 class ii v il v ih v ol v oh i ol i oh i osl i osh i il 1 i ih 2 drive strength min., v max., v min., v max., v max. , v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 21 ma ?0.3 v ref ? 0.2 v ref + 0.2 3.6 0.5 v cci ? 0.9 21 21 109 103 10 10 notes: 1. i il is the input leakage current pe r i/o pin over recommended operat ion conditions where ?0.3 v < v in < v il . 2. i ih is the input leakage current per i/o pin over recommended operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 3. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-131 ? ac loading table 2-163 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v ) measuring point* (v) v ref (typ.) (v) v tt (typ.) (v) c load (pf) v ref ? 0.2 v ref + 0.2 1.5 1.5 1.485 30 note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. test point 30 pf 25 25 sstl3 class ii v tt table 2-164 ? sstl3- class ii commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v, v ref = 1.5 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.07 0.04 1.25 0.43 2.10 1.67 4.34 3.91 ns ?1 0.56 1.76 0.04 1.06 0.36 1.79 1.42 3.69 3.32 ns ?2 0.49 1.54 0.03 0.93 0.32 1.57 1.25 3.24 2.92 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-210 v2.0 differential i/o characteristics configuration of the i/o modules as a differential pair is handled by the actel designer software when the user in stantiates a differential i/o macro in the design. differential i/os can also be used in conjunction with the embedded input register (inreg), output register (outreg), enable register (enreg), and double data rate (ddr). however, there is no support for bidirectional i/os or tristates with these standards. lvds low-voltage differential signal (ansi/tia/eia-644) is a high-speed differential i/o standard. it requires that one data bit be carried through tw o signal lines, so two pi ns are needed. it also requires external resistor termination. the full implementation of the lvds transmitt er and receiver is shown in an example in figure 2-132 . the building blocks of the lvds transmitt er?receiver are one transmitter macro, one receiver macro, three board resistors at the transm itter end, and one resistor at the receiver end. the values for the three driv er resistors are different from those used in the lvpecl implementation because the output standar d specifications are different. figure 2-132 ? lvds circuit diagram and board-level implementation table 2-165 ? minimum and maximum dc input and output levels dc parameter descripti on min. typ. max. units v cci supply voltage 2.375 2.5 2.625 v v ol output low voltage 0.9 1.075 1.25 v v oh input high voltage 1.25 1.425 1.6 v i ol 3 output low voltage 0.65 0.91 1.16 ma i oh 3 output high voltage 0.65 0.91 1.16 ma v i input voltage 0 2.925 v i il 4,5 input low voltage 10 a i ih 4,6 input high voltage 10 a v odiff differential output voltage 250 350 450 mv v ocm output common mode voltag e 1.125 1.25 1.375 v v icm input common mode voltage 0.05 1.25 2.35 v v idiff input differential voltage 100 350 mv notes: 1. 5% 2. differential input voltage = 350 mv 3. i ol /i oh defined by v odiff /(resistor network) 4. currents are measured at 85c junction temperature. 5. i il is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < v in < v il . 6. i ih is the input leakage current per i/o pin over recomme nded operating conditions v ih < v in < v cci . input current is larger when operat ing outside reco mmended ranges. 140 100 zo = 50 zo = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12
user i/os v2.0 2-211 timing characteristics blvds/m-lvds bus lvds (blvds) and multipoint lvds (m-lvds) sp ecifications extend the existing lvds standard to high-performance multipoint bus applications. multidrop and multipoint bus configurations can contain any combin ation of drivers, receivers, and transce ivers. actel lvds drivers provide the higher drive current required by blvds and m-lvds to accommodate the loading. the driver requires series terminations for better signal qu ality and to control voltage swing. termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. these configurations can be implemented using tribuf_lvds and bibuf_lvds macros along with appropriate terminations. multipoint designs usin g actel lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sa mple application is given in figure 2-133 . the input and output buffer delays are available in the lvds section in table 2-168 . example: for a bus consisting of 20 equidistant loads, the following te rminations provide the required differential voltage, in worst-case industrial operating co nditions at the farthest receiver: r s =60 and r t =70 , given z 0 =50 (2") and z stub =50 (~1.5"). table 2-166 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) 1.075 1.325 cross point ? note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. table 2-167 ? lvds commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to pro i/os speed grade t dout t dp t din t py units std. 0.66 2.10 0.04 1.82 ns ?1 0.56 1.79 0.04 1.55 ns ?2 0.49 1.57 0.03 1.36 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 . figure 2-133 ? blvds/m-lvds multipoint application using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0
fusion family of mi xed-signal flash fpgas device architecture 2-212 v2.0 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differential i/o standard. it requires that one data bit be carried through two signal lines. like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitt er and receiver is shown in an example in figure 2-134 . the building blocks of the lvpecl transm itter?receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for th e three driver resistors are differ ent from those used in the lvds implementation because the output stand ard specifications are different. timing characteristics figure 2-134 ? lvpecl circuit diagram and board-level implementation table 2-168 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units v cci supply voltage 3.0 3.3 3.6 v v ol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v v oh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v v il , v ih input low, input high voltages 0 3.3 0 3.6 0 3.9 v v odiff differential output voltage 0.625 0. 97 0.625 0.97 0.625 0.97 v v ocm output common mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 v v icm input common mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v v idiff input differential voltage 300 300 300 mv table 2-169 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ.) (v) 1.64 1.94 cross point ? note: *measuring point = v trip . see table 2-87 on page 2-167 for a complete table of trip points. 187 w 100 zo = 50 zo = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12 table 2-170 ? lvpecl commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to pro i/os speed grade t dout t dp t din t py units std. 0.66 2.14 0.04 1.63 ns ?1 0.56 1.82 0.04 1.39 ns ?2 0.49 1.60 0.03 1.22 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-213 i/o register specifications fully registered i/o buffers with synchronous enable and asynchronous preset figure 2-135 ? timing model of registered i/o buffers with synchronous enable an d asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive edge triggered data output register and enable output register with: active high enable active high preset postive edge triggered p a d o ut clk e nable preset data_out data x x x x x x x x x x x x x x eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
fusion family of mi xed-signal flash fpgas device architecture 2-214 v2.0 table 2-171 ? parameter definitions and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of th e output data register l,dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset re covery time for the ou tput data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the ou tput enable register j, h t oesue enable setup time for the ou tput enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of th e output enable register i, eout t oerempre asynchronous preset re moval time for the output enable register i, h t oerecpre asynchronous preset reco very time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset re moval time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 2-135 on page 2-213 for more information.
user i/os v2.0 2-215 fully registered i/o buffers with synchronous enable and asynchronous clear figure 2-136 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear core array data input i/o register with active high enable active high clear positive edge triggered data output register and enable output register with active high enable active high clear positive edge triggered enable clk pad out clk enable clr data_out data y aa eout dout dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf
fusion family of mi xed-signal flash fpgas device architecture 2-216 v2.0 table 2-172 ? parameter definitions and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time fo r the output data register ll, hh t orecclr asynchronous clear reco very time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the ou tput enable register kk, hh t oehe enable hold time for the ou tput enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recove ry time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear reco very time for the input data register dd, aa note: *see figure 2-136 on page 2-215 for more information.
user i/os v2.0 2-217 input register timing characteristics figure 2-137 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-173 ? input data register propagation delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t iclkq clock-to-q of the input da ta register 0.24 0.27 0.32 ns t isud data setup time for the inpu t data register 0.26 0.30 0.35 ns t ihd data hold time for the inpu t data register 0.00 0.00 0.00 ns t isue enable setup time fo r the input data re gister 0.37 0.42 0.50 ns t ihe enable hold time for the input data register 0.00 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the in put data register 0.45 0.52 0.61 ns t ipre2q asynchronous preset-to-q of the input data register 0.45 0.52 0.61 ns t iremclr asynchronous clear removal time for the input data register 0.00 0.00 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.22 0.25 0.30 ns t irempre asynchronous preset removal time for the input data register 0.00 0.00 0.00 ns t irecpre asynchronous preset recovery time fo r the input data re gister 0.22 0.25 0.30 ns t iwclr asynchronous clear minimum pu lse width for the input data register 0.22 0.25 0.30 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.22 0.25 0.30 ns t ickmpwh clock minimum pulse width high for th e input data register 0.36 0.41 0.48 ns t ickmpwl clock minimum pulse width low for th e input data regi ster 0.32 0.37 0.43 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-218 v2.0 output register timing characteristics figure 2-138 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-174 ? output data register propagation delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t oclkq clock-to-q of the output data register 0.59 0.67 0.79 ns t osud data setup time for the output data register 0.31 0.36 0.42 ns t ohd data hold time for the output data register 0.00 0.00 0.00 ns t osue enable setup time fo r the output data register 0.44 0.50 0.59 ns t ohe enable hold time for the output data register 0.00 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 0.80 0.91 1.07 ns t opre2q asynchronous preset-to-q of the output data register 0.80 0.91 1.07 ns t oremclr asynchronous clear removal time for th e output data register 0.00 0.00 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.22 0.25 0.30 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.22 0.25 0.30 ns t owclr asynchronous clear minimum pulse width for the output data register 0.22 0.25 0.30 ns t owpre asynchronous preset minimum pu lse width for the output data register 0.22 0.25 0.30 ns t ockmpwh clock minimum pulse width high for the output data register 0.36 0.41 0.48 ns t ockmpwl clock minimum pulse width low for the output data register 0.32 0.37 0.43 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
user i/os v2.0 2-219 output enable register timing characteristics figure 2-139 ? output enable register timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-175 ? output enable register propagation delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t oeclkq clock-to-q of the output enable regi ster 0.44 0.51 0.59 ns t oesud data setup time for the output enable register 0.31 0.36 0.42 ns t oehd data hold time for the output enable register 0.00 0.00 0.00 ns t oesue enable setup time for the output enable register 0.44 0.50 0.58 ns t oehe enable hold time for the output enable register 0.00 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the outp ut enable register 0.67 0.76 0.89 ns t oepre2q asynchronous preset-to-q of the ou tput enable regi ster 0.67 0.76 0.89 ns t oeremclr asynchronous clear removal time for th e output enable register 0.00 0.00 0.00 ns t oerecclr asynchronous clear recovery time for th e output enable re gister 0.22 0.25 0.30 ns t oerempre asynchronous preset removal time for th e output enable re gister 0.00 0.00 0.00 ns t oerecpre asynchronous preset recovery time for the output enable re gister 0.22 0.25 0.30 ns t oewclr asynchronous clear minimum puls e width for the output enable register 0.22 0.25 0.30 ns t oewpre asynchronous preset minimum pu lse width for the output enable register 0.22 0.25 0.30 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.36 0.41 0.48 ns t oeckmpwl clock minimum pulse width low for the output enable regi ster 0.32 0.37 0.43 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-220 v2.0 ddr module specifications input ddr module figure 2-140 ? input ddr timing model table 2-176 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
user i/os v2.0 2-221 timing characteristics figure 2-141 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-177 ? input ddr propagation delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.39 0.44 0.52 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.27 0.31 0.37 ns t ddrisud data setup for inpu t ddr 0.28 0.32 0.38 ns t ddrihd data hold for input ddr 0.00 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_ qr for input ddr 0.57 0.65 0.76 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.46 0.53 0.62 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 0.00 ns t ddrirecclr asynchronous clear recovery ti me for input ddr 0.22 0.25 0.30 ns t ddriwclr asynchronous clear mi nimum pulse width for input ddr 0.22 0.25 0.30 ns t ddrickmpwh clock minimum pulse width hi gh for input ddr 0.36 0.41 0.48 ns t ddrickmpwl clock minimum pulse width lo w for input ddr 0.32 0.37 0.43 ns f ddrimax maximum frequency for input ddr 1,404 1,048 1,232 mhz note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-222 v2.0 output ddr figure 2-142 ? output ddr timing model table 2-178 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
user i/os v2.0 2-223 timing characteristics figure 2-143 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddrosud1 t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-179 ? output ddr propagation delays commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.70 0.80 0.94 ns t ddrosud1 data_f data setup for output ddr 0.38 0.43 0.51 ns t ddrosud2 data_r data setup for ou tput ddr 0.38 0.43 0.51 ns t ddrohd1 data_f data hold for output ddr 0. 00 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 0.80 0.91 1.07 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 0.00 ns t ddrorecclr asynchronous clear recovery ti me for output ddr 0.22 0.25 0.30 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.22 0.25 0.30 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.36 0.41 0.48 ns t ddrockmpwl clock minimum pulse width low fo r the output ddr 0.32 0.37 0.43 ns f ddomax maximum frequency for the output ddr 1,048 1,232 1,404 mhz note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mi xed-signal flash fpgas device architecture 2-224 v2.0 pin descriptions supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. with in the package, the gndq plane is decoupled from the simultaneous switching noi se originated from the output buffer ground domain. this minimizes the noise transfer within the pa ckage and improves in put signal integrity. gndq needs to always be conn ected on the board to gnd. note : in fg256, fg484, and fg676 packages, gndq and gnd pins are connected with in the package and are labeled as gnd pins in the respective package pin assignment tables. adcgndref analog reference ground analog ground reference used by the adc. this pad should be connected to a quiet analog ground. gnda ground (analog) quiet ground supply voltage to th e analog block of fusion device s. the use of a separate analog ground helps isolate the analog functionality of the fusion device from any digital switching noise. a 0.2 v maximum differential voltage between gnd and gnda/gndq should apply to system implementation. gndaq ground (analog quiet) quiet ground supply voltage to the analog i/o of fusion devices. the use of a separate analog ground helps isolate the analog functionality of the fusion device from any digital switching noise. a 0.2 v maximum differential voltage between gnd and gnda/gndq should apply to system implementation. note: in fg 256, fg484, and fg676 packages, gndaq and gnda pins are connected within the package and are labeled as gnda pins in the respective package pin assignment tables. in fg256 and gndnvm flash memory ground ground supply used by the fusion de vice's flash memory block module(s). gndosc oscillator ground ground supply for both in tegrated rc oscillator and crystal oscillator circuit. v cc15a analog power supply (1.5 v) 1.5 v clean analog power supply input for use by the 1.5 v portion of the analog circuitry. v cc33a analog power supply (3.3 v) 3.3 v clean analog power supply input for use by the 3.3 v portion of the analog circuitry. v cc33n negative 3.3 v output this is the ?3.3 v output from the voltage conv erter. a 2.2 f capacitor must be connected from this pin to ground. v cc33pmp analog power supply (3.3 v) 3.3 v clean analog power supply in put for use by the analog charge pump. to avoid high current draw, v cc33pmp should be powered up simultaneously with or after v cc33a . v ccnvm flash memory block power supply (1.5 v) 1.5 v power supply input used by the fusion device's flash memory block module(s). to avoid high current draw, v cc should be powered up before or simultaneously with v ccnvm . v ccosc oscillator power supply (3.3 v) power supply for both integrated rc oscillator and crystal oscillator circuit. the internal 100 mhz oscillator, powered by the v ccosc pin, is needed for device programming, operation of the v ddn33
pin descriptions v2.0 2-225 pump, and envm operation. v ccosc is off only when v cca is off. v ccosc must be powered whenever the fusion devi ce needs to function. v cc core supply voltage supply voltage to the fpga core, nominally 1.5 v. v cc is also required fo r powering the jtag state machine, in addition to v jtag . even when a fusion device is in bypass mode in a jtag chain of interconnected devices, both v cc and v jtag must remain powered to al low jtag signals to pass through the fusion device. v cci b x i/o supply voltage supply voltage to the bank's i/o output buffers and i/o logic. b x is the i/o bank number. there are either four (afs090 and afs250) or five (afs600 and afs1500) i/o banks on the fusion devices plus a dedicated v jtag bank. each bank can have a separate v cci connection. all i/os in a bank will run off the same v cci bx supply. v cci can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding v cci pins tied to gnd. v ccpla/b pll supply voltage supply voltage to analog pll, no minally 1.5 v, where a and b refe r to the pll. afs090 and afs250 each have a single pll. the afs600 and afs1500 devices each have two plls. actel recommends tying v ccplx to v cc and using proper filtering circuits to decouple v cc noise from pll. if unused, v ccpla/b should be tied to gnd. v compla/b ground for west and east pll v compla is the ground of the west pll (ccc location f) and v complb is the ground of the east pll (ccc location c). v jtag jtag supply voltage fusion devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simp lifies power supply and pcb design. if the jtag interface is neither used nor planned to be used, the v jtag pin together with the trst pin could be tied to gnd. it should be noted that v cc is required to be powe red for jtag operation; v jtag alone is insufficient. if a fusion device is in a jtag chain of interconnected boards and it is desired to power down the board containing the fusion device, this may be done provided both v jtag and v cc to the fusion part remain powe red; otherwise, jtag signals will not be able to transition the fusion device, even in bypass mode. v pump programming supply voltage fusion devices support single-voltage isp progra mming of the configuration flash and flashrom. for programming, v pump should be in the 3.3 v +/-5% range. during normal device operation, v pump can be left floating or can be tied to any voltage between 0 v and 3.6 v. when the v pump pin is tied to ground, it shuts off the ch arge pump circuitry, resu lting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacito rs (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. user-defined supply pins v ref i/o voltage reference reference voltage for i/o minibanks. both afs600 and afs1500 (north bank only) support actel pro i/o. these i/o banks support voltag e reference standard i/o. the v ref pins are configured by the user from regular i/os, and any i/o in a bank, except jtag i/os, can be designated as the voltage reference i/o. only certain i/o standards require a voltage reference?hstl (i ) and (ii), sstl2 (i) and (ii), sstl3 (i) and (ii), and gtl/gtl+. one v ref pin can support the number of i/os available in its minibank.
fusion family of mi xed-signal flash fpgas device architecture 2-226 v2.0 varef analog reference voltage the fusion device can be configured to generate a 2.56 v internal reference voltage that can be used by the adc. while using the internal reference, the reference voltage is output on the varef pin for use as a system reference. if a different reference voltage is required, it can be supplied by an external source and applied to this pin. the valid range of values that can be supplied to the adc is 1.0 v to 3.3 v. when varef is internally generated by the fusion device, a bypass capacitor must be connected from this pin to ground. the value of the bypass capacitor should be between 3.3 f and 22 f, which is based on the needs of th e individual designs. the choice of the capacitor value has an impact on the settling time it takes the varef signal to reach the required specification of 2.56 v to initiate valid conve rsions by the adc. if the lower capacitor value is chosen, the settling time required for varef to achieve 2.56 v will be shorter than when selecting the larger capacitor value. the above range of capa citor values supports th e accuracy specification of the adc, which is detailed in the datasheet. designers choosing the smaller capacitor value will not obtain as much marg in in the accuracy as that achieved with a larger capacitor value. depending on the capacitor value selected in the analog system builder, a to ol in libero ide, an automatic delay circuit will be generated using logi c tiles available within the fpga to ensure that varef has achieved the 2.56 v value. actel recomme nds customers use 10 f as the value of the bypass capacitor. designers choosing to use an external varef need to ensure that a stable and clean varef source is supplied to the varef pin before initiating conversions by the adc. designers should also make sure that the adcreset signal is d easserted before initiating valid conversions. 2 user pins i/o user input/output the i/o pin functions as an input, output, tristate , or bidirectional buffer. input and output signal levels are compatible with the i/o standard selected . unused i/o pins are co nfigured as inputs with pull-up resistors. during programming, i/os become tri stated and weakly pulled up to v cci . with the v cci and v cc supplies continuously powered up, when the devi ce transitions from programming to operating mode, the i/os get instantly configured to the desired user configuration. a xy analog input/output analog i/o pin, where x is the analog pad type (c = current pad, g = gate driver pad, t = temperature pad, v = voltage pad) and y is the analog qu ad number (0 to 9). there is a minimum 1 m to ground on av, ac, and at. this pin can be left floating when it is unused. atrtn x temperature monitor return at returns are the returns for the temperature senso rs. the cathode terminal of the external diodes should be connected to these pins. ther e is one analog return pin for every two analog quads. the x in the atrtn x designator indicates the quad pairing ( x = 0 for aq1 and aq2, x =1 for aq2 and aq3, ..., x = 4 for aq8 and aq9). the signals that drive these pins are called out as atreturn xy in the software (where x and y refer to the quads that shar e the return signal). atrtn is internally connected to ground. it can be left floating when it is unused. the maximum capacitance allowed across the at pins is 500 pf. gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as pro i/os since they have identical capabilities. unused gl pins are config ured as inputs with pu ll-up resistors. see more detailed descriptions of global i/o connectivity in the "clock conditioning circuits" section on page 2-24 . 2. the adc is functional with an external refere nce down to 1v, however to meet the performance parameters highlighted in the datasheet refer to the varef specification in table 3-2 on page 3-3 .
pin descriptions v2.0 2-227 refer to the "user i/o naming convention" section on page 2-159 for a description of naming of global pins. jtag pins fusion devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). v cc must also be powered for the jtag state machine to operate, even if the devi ce is in bypass mode; v jtag alone is insufficient. both v jtag and v cc to the fusion part must be supplied to allow jtag signals to transition the fusion device. isolating the jtag power supply in a separate i/o bank gives greater flexibility with supply selection and simplifies power supp ly and pcb design. if the jtag interface is neither used nor planned to be used, the v jtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used , actel recommends tyin g off tck to gnd or v jtag through a resistor placed close to the fpga pin. this prevents jt ag operation in case tms enters an undesired state. note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. refer to table 2-180 for more information. tdi test data input serial input for jtag boundary sc an, isp, and ujtag usage. ther e is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jt ag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of th e ieee1532 boundary scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up re sistor on the tms pin. trst boundary scan reset pin the trst pin functions as an acti ve low input to asynch ronously initialize (o r reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the tr st pin. if jtag is not used, an external pull-down resistor could be included to en sure the tap is held in reset mode. the resistor values must be chosen from table 2-180 and must satisfy the parallel resistance value requirement. the values in table 2-180 correspond to the resistor recommende d when a single device is used and to the equivalent parallel resistor when mu ltiple devices are conn ected via a jtag chain. in critical applications, an upse t in the jtag circuit co uld allow entering an undesired jtag state. in such cases, actel recommends tyin g off trst to gnd through a resi stor placed close to the fpga pin. table 2-180 ? recommended tie-off values for the tck and trst pins v jtag tie-off resistance 2, 3 v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k notes: 1. equivalent parallel resistance if mo re than one device is on jtag chain. 2. the tck pin can be pulled up/down. 3. the trst pin can only be pulled down.
fusion family of mi xed-signal flash fpgas device architecture 2-228 v2.0 note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. special function pins nc no connect this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effe ct on the operation of the device. dc don't connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. ncap negative capacitor negative capacitor is where the negative terminal of the charge pump capacitor is connected. a capacitor, with a 2.2 f recommended value, is required to connect between pcap and ncap. pcap positive capacitor positive capacitor is where the positi ve terminal of the charge pump capacitor is connected. a capacitor, with a 2.2 f recommended value, is required to connect between pcap and ncap. pub push button push button is the connection for the exte rnal momentary switch used to turn on the 1.5 v voltage regulator and can be fl oating if not used. ptbase pass transistor base pass transistor base is the control signal of the voltage regulator. this pin should be connected to the base of the external pass transistor used with the 1.5 v internal voltage regulator and can be floating if not used. ptem pass transistor emitter pass transistor emitter is the feedback input of the voltage regulator. this pin should be connected to the emitter of the external pass transistor used with the 1.5 v internal voltage regulator and can be floating if not used. xtal1 crystal oscillator circuit input input to crystal oscillator circuit. pin for connecti ng external crystal, cerami c resonator, rc network, or external clock input. when usin g an external crystal or ceramic oscillator, external capacitors are also recommended (please refer to the crystal osci llator manufacturer for proper capacitor value). if using external rc network or clock input, xt al1 should be used and xtal2 left unconnected. xtal2 crystal oscillator circuit input input to crystal oscillator circuit. pin for connecti ng external crystal, cerami c resonator, rc network, or external clock input. when usin g an external crystal or ceramic oscillator, external capacitors are also recommended (please refer to the crystal osci llator manufacturer for proper capacitor value). if using external rc network or clock input, xt al1 should be used and xtal2 left unconnected. security fusion devices have a built-in 128-bit aes decryption core. the decryption core facilitates secure, in- system programming of the fpga core array fabr ic and the flashrom. the flashrom and the fpga core fabric can be programmed independently from each other, allowing the flashrom to be updated without the n eed for change to the fpga core fabric. the aes master key is stored in on- chip nonvolatile memory (flash). the aes master key can be preloaded into parts in a secure programming environment (such as the actel in-house programming center), and then "blank" parts can be shipped to an un trusted programming or manufacturing center for final personalization with an aes-encrypted bitstream. late stage product changes or personalization can be implemented easily and securely by simply sending a stapl file wi th aes-encrypted data.
security v2.0 2-229 secure remote field updates over public networks (such as the inte rnet) are possible by sending and programming a stapl file with aes-encrypted data. for more information, refer to the fusion security application note. 128-bit aes decryption the 128-bit aes standard (fips-1 97) block cipher is the nation al institute of standards and technology (nist) replacement for des (data encryption stan dard fips46-2). aes has been designed to protect sensitive go vernment information well into th e 21st century. it replaces the aging des, which nist adopted in 1977 as a federal inform ation processing standard used by federal agencies to protect sensitive, unclassi fied information. the 128-bit aes standard has 3.4 10 38 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit aes cipher text using exhau stive techniques. keys are stored (securely) in fusion devices in nonvolatile flash memory. all programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programmi ng verification is performed on- chip, ensuring that the contents of fusion devices remain secure. aes decryption can also be used on the 1,024-bit flashrom to allow for secure remote updates of the flashrom contents. th is allows for easy, secure support for subscription mo del products. see the application note fusion security for more details. aes for flash memory aes decryption can also be used on the flash memory blocks. this allows for the secure update of the flash memory blocks. during runtime, the encrypted data can be clocked in via the jtag interface. the data can be passed through the in ternal aes decryption en gine, and the decrypted data can then be stored in the flash memory block. programming programming can be performed using various programming to ols, such as silicon sculptor ii (bp micro systems) or flashpro3 (actel). the user can generate stp progra mming files from the designer so ftware and can use these files to program a device. fusion devices can be programmed in-system. during programming, v ccosc is needed in order to power the internal 100 mhz oscillator . this oscillator is used as a source for the 20 mhz oscillator that is used to drive the charge pump for programming. isp fusion devices support ieee 1532 isp via jtag and require a single v pump voltage of 3.3 v during programming. in addition, programming via a microc ontroller in a target system can be achieved. refer to the standard or the in-system programming (isp) of acte l's low-power flash devices using flashpro3 document for more details. jtag ieee 1532 programming with ieee 1532 fusion devices support the jtag-based ieee1532 standar d for isp. as part of this support, when a fusion device is in an unprogrammed state, all user i/o pins are disabl ed. this is achieved by keeping the global io_en signal d eactivated, which also has the effect of disabling the input buffers. consequently, the sample instruction will have no effect wh ile the fusion device is in this unprogrammed state?different beha vior from that of the proasic plus ? device family. this is done because sample is defined in the ieee1532 specific ation as a noninvasive in struction. if the input buffers were to be enabled by sample temporarily turning on the i/os, th en it would not truly be a noninvasive instruction. refer to the standard or the in-system programming (isp) of actel's low- power flash devices using flashpro3 document for more details. boundary scan fusion devices are compatible wi th ieee standard 1149.1, which defines a hardware architecture and the set of mechanisms for boun dary scan testing. the basic fusi on boundary scan logic circuit is composed of the test access port (tap) controller, test data regi sters, and instruction register
fusion family of mi xed-signal flash fpgas device architecture 2-230 v2.0 ( figure 2-144 on page 2-231 ). this circuit supports all mandatory ieee 1149.1 instructions (extest, sample/preload, and bypass) and th e optional idco de instruction ( table 2-182 on page 2-231 ). each test section is accessed through the tap, which has five associated pins : tck (test clock input), tdi, tdo (test data input and output), tms (test mo de selector), and trst (test reset input). tms, tdi, and trst are equipped with pu ll-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated fo r boundary scan test usage. refer to the "jtag pins" section on page 2-227 for pull-up/-down recommendations for tdo and tck pins. the tap controller is a 4-bit state machine (16 states) that operates as shown in figure 2-144 on page 2-231 . the 1s and 0s represent the values that must be present on tm s at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and gene rates control and clock signals for the rest of the test lo gic architecture. on power-up, th e tap controller enters the test- logic-reset state. to guarantee a reset of the co ntroller from any of the possible states, tms must remain high for five tck cycles. the trst pin can also be us ed to asynchronously place the tap controller in the test-logic-reset state. fusion devices support three types of test data registers: bypass, devi ce identification, and boundary scan. the bypass register is selected when no other regi ster needs to be accessed in a device. this speeds up test data transfer to othe r devices in a test data path. the 32-bit device identification register is a shift re gister with four fields (lsb, id number, part number, and version). the boundary scan register observes and controls th e state of each i/o pin. each i/o cell has three boundary scan register cells, each with a serial-i n, serial-out, parallel-in, and parallel-out pin. the serial pins are used to serial ly connect all the boundary scan register cells in a device into a boundary scan register chain, wh ich starts at the tdi pin and ends at the tdo pin. the parallel ports are connected to the internal core logic i/o tile and the inpu t, output, and co ntrol ports of an i/o buffer to capture and load data into the regi ster to control or observe the logic state of each i/o. table 2-181 ? trst and tck pull-down recommendations v jtag tie-off resistance* v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k note: *equivalent parallel resistance if more than one device is on jtag chain.
security v2.0 2-231 figure 2-144 ? boundary scan chain in fusion table 2-182 ? boundary scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers
fusion family of mi xed-signal flash fpgas device architecture 2-232 v2.0 ieee 1532 characteristics jtag timing delays do not include jtag i/os. to obtain complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/os" section on page 2-133 for more details. timing characteristics table 2-183 ? jtag 1532 commercial temperature range conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time 0.50 0.57 0.67 ns t dihd test data input hold time 1.00 1.13 1.33 ns t tmssu test mode select setup time 0.50 0.57 0.67 ns t tmdhd test mode select hold time 1.00 1.13 1.33 ns t tck2q clock to q (data out) 6.00 6.80 8.00 ns t rstb2q reset to q (data out) 20.00 22.67 26.67 ns f tckmax tck maximum frequenc y 25.00 22.00 19.00 mhz t trstrem resetb removal time 0.00 0.00 0.00 ns t trstrec resetb recovery time 0.20 0.23 0.27 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
part number and revision date v2.0 2-233 part number and revision date part number 51700092-014-1 revised july 2009 list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v2.0) page preliminary v1.7 (october 2008) the microblade and fusion datasheets have been combin ed. pigeon point information is new. coremp7 support was removed sinc e it is no longer offered. ?f was removed from the datasheet since it is no longer offered. the operating temperature was changed from ambient to junction to better reflect actual condit ions of operations. commercial: 0c to 85c industrial: ?40c to 100c the version number category was changed from preliminary to production, which means the datasheet contai ns information based on final characterization. the version number ch anged from preliminary v1.7 to v2.0. n/a the phrase "commercial-case conditions" in timing table ti tles was changed to "commercial temperatur e range conditions." n/a the "crystal oscillator" section was updated significantly. please review carefully. 2-22 the "real-time counter (part of ab macro)" section was updated significantly. please review carefully. 2-35 there was a typo in table 2-19 ? flash memory block pin names for the erasepage description; it was the same as discardpage. as as a result, the erasepage description was updated. 2-43 the t fmaxclknvm parameter was updated in table 2-25 ? flash memory block timing . 2-55 table 2-31 ? ram4k9 and table 2-32 ? ram512x18 were updated. 2-71 to 2-71 in table 2-36 ? analog block pin description , the function description for pwrdwn was changed from "comparator power-down if 1" to "adc comparator power-down if 1. when asserted, the adc will stop functioning, and the digital portion of the analog block will continue operating. this may result in invali d status flags from the analog block. therefore, actel does not recommend asserting the pwrdwn pin." 2-82 figure 2-76 ? gate driver example was updated. 2-95 the "adc configuration description" section was updated. please review carefully. 2-102 figure 2-85 ? intra-con version timing diagram and figure 2-86 ? injected- conversion timing diagram are new. 2-108 the "typical performance characteristics" section is new. 2-116 table 2-46 ? analog channel specifications was significantly updated. 2-118
fusion family of mi xed-signal flash fpgas device architecture 2-234 v2.0 preliminary v1.7 (continued) table 2-47 ? adc characteristics in direct input mode was significantly updated. 2-124 in table 2-50 ? analog ch annel accuracy: monitori ng standard positive voltages , note 1 was updated. 2-125 in table 2-49 ? calibrated analog channel accuracy 1,2,3 , note 2 was updated. in table 2-51 ? acm address de code table for analog quad , bit 89 was removed. 2-127 the data in the 2.5 v lcmos and lvcmos 2.5 v / 5.0 v rows were updated in table 2-72 ? fusion stan dard and advanced i/o ? hot-swap and 5 v input tolerance capabilities . 2-144 in table 2-75 ? fusion standard i/o standards?out_drive settings , lvcmos 1.5 v, for out_drive 2, was chan ged from a dash to a checkmark. 2-153 the "v cc15a analog power supply (1.5 v)" definition was changed from "a 1.5 v analog power supply input should be used to provide this input" to "1.5 v clean analog power supply inpu t for use by the 1.5 v portion of the analog circuitry." 2-224 in the "v cc33pmp analog power supply (3.3 v)" pin description, the following text was changed from "v cc33pmp should be powered up before or simultaneously with v cc33a " to "v cc33pmp should be powered up simultaneously with or after v cc33a ." 2-224 the "v ccosc oscillator power supply (3.3 v)" section was updated to include information about when to power the pin. 2-224 in the "128-bit aes decryption" section , fips-192 was incorrect and changed to fips-197. 2-229 the note in table 2-81 ? fusion standard and advanced i/o attributes vs. i/o standard applications was updated. 2-157 for 1.5 v lvcmos, the v il and v ih parameters, 0.30 * v cci was changed to 0.35 * v cci and 0.70 * v cci was changed to 0.65 * v cci in table 2-83 ? summary of maximum and minimum dc in put and output levels ap plicable to commercial and industrial conditions , table 2-84 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions , and table 2-85 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions . in table 2-84 ? summary of maximum and minimum dc input and output levels applicable to commerci al and industrial conditions , the v ih max column was updated. 2-165 to 2-166 table 2-86 ? summary of maximum and mi nimum dc input levels applicable to commercial and industrial conditions was updated to include notes 3 and 4. the temperature ranges were also updated in notes 1 and 2. 2-166 the titles in table 2-89 ? summary of i/o ti ming characteristics ? software default settings to table 2-91 ? summary of i/ o timing characteristics ? software default settings were updated to "v cci = i/o standard dependent." 2-168 to 2-170 below table 2-95 ? i/o short currents iosh/iosl , the paragraph was updated to change 110c to 100c and three mo nths was changed to six months. 2-174 previous version changes in current version (v2.0) page
part number and revision date v2.0 2-235 preliminary v1.7 (continued) table 2-96 ? short current ev ent duration before failure was updated to remove 110c data. 2-176 in table 2-98 ? i/o input rise time, fall time, and related i/o reliability , lvttl/lvcmos rows were changed from 110c to 100c. 2-176 advance v1.6 (august 2008) for the v il and v ih parameters, 0.30 * v cci was changed to 0.35 * v cci and 0.70 * v cci was changed to 0.65 * v cci in table 2-123 ? minimum and maximum dc input and output levels . 2-194 the version number category was change d from advance to preliminary, which means the datasheet contains informatio n based on simulation and/or initial characterization. the information is be lieved to be correct, but changes are possible. n/a the following updates were made to table 2-38 ? temperature data format : temperature digital output 213 00 1111 1101 283 01 0001 1011 358 01 0110 0110 ? only the digital output was updated. temperature 358 remains in the temperature column. 2-98 in advance v1.2, the "v aref analog reference voltage" pin description was significantly updated but the change was not noted in the change table. 2-226 advance v1.5 (july 2008) the references to the peripherals user?s guide in the "no-glitch mux (ngmux)" section and "voltage regulator power supply monitor (vrpsm)" section were changed to fusion handbook . 2-32 , 2-42 advance v1.4 (july 2008) the title of the datasheet changed fr om actel programmable system chips to actel fusion mixed- signal fpgas. in addition, all instances of programmable system chip were changed to mixed-signal fpga. n/a advance v1.2 (june 2008) the "adc description" section was significantly updated. please review carefully. 2-102 advance v1.1 (may 2008) table 2-25 ? flash memory block timing was significantly updated. 2-55 the "v aref analog reference voltage" pin description section was significantly update. please review it carefully. 2-226 table 2-45 ? adc interface timing was significantly updated. 2-110 table 2-56 ? direct analog input switch control truth table?av (x = 0), ac (x = 1), and at (x = 3) was significantly updated. 2-131 the following sentence was deleted from the "voltage monitor" section : the analog quad inputs are tolerant up to 12 v + 10%. 2-86 advance v1.0 (january 2008) the following text was incorrect and therefore deleted: vcc33a analog power filter analog power pin for the analog power supply low-pass filter. an external 100 pf capacitor should be connected between this pin and ground. there is still a description of v cc33a on page 2-224 . 2-204 advance v0.9 (october 2007) all timing characteristics tables were updated. for the differential i/o standards, the standard i/ o support tables are new. n/a table 2-3 ? array coordinates was updated to change the max x and y values 2-9 table 2-12 ? fusion ccc/pll spec ification was updated. 2-31 a note was added to table2-16rtc acm memory map . 2-37 previous version changes in current version (v2.0) page
fusion family of mi xed-signal flash fpgas device architecture 2-236 v2.0 advance v0.9 (continued) a reference to the peripheral?s user?s guide was added to the "voltage regulator power supply mo nitor (vrpsm)" section . 2-42 in table 2-25 ? flash memory block timing , the commercial conditions were updated. 2-55 in table 2-26 ? flashrom access time , the commercial conditions were missing and have been added below the title of the table. 2-58 in table 2-36 ? analog block pin description , the function description was updated for the adcreset. 2-82 in the "voltage monitor" section , the following sentence originally had 10% and it was changed to +10%. the analog quad inputs are tolerant up to 12 v + 10%. in addition, this statement was deleted from the datasheet: each i/o will draw power when co nnected to power (3 ma at 3 v). 2-86 the "terminology" section is new. 2-88 the "current moni tor" section was significantly updated. figure 2-72 ? timing diagram for current monitor strobe to figure 2-74 ? negati ve current monitor and table 2-37 ? recommended resistor for different current range measurement are new. 2-90 the "adc description" section was updated to add the "terminology" section . 2-93 in the "gate driver" section , 25 ma was changed to 20 ma and 1.5 mhz was changed to 1.3 mhz. in addition, th e following sentence was deleted: the maximum ag pad switchin g frequency is 1.25 mhz. 2-94 the "temperature monitor" section was updated to rewrite most of the text and add figure 2-78 , figure 2-79 , and table 2-38 ? temperature data format . 2-96 in table 2-38 ? temperature data format , the temperature k column was changed for 85c from 538 to 358. 2-98 in table 2-45 ? adc interface timing , "typical-case" was changed to "worst- case." 2-110 the "adc interface timing" section is new. 2-110 table 2-46 ? analog channel specifications was updated. 2-118 the "v cc15a analog power supply (1.5 v)" section was updated. 2-224 the "v ccpla/b pll supply voltage" section is new. 2-225 in "v ccnvm flash memory block power supply (1.5 v)" section , supply was changed to supply input. 2-224 the "v ccpla/b pll supply voltage" pin description was updated to include the following statement: actel recommends tying v ccplx to v cc and using proper filtering circuits to decouple v cc noise from pll. 2-225 the "v compla/b ground for west and east pll" section was updated. 2-225 in table 2-47 ? adc characteristi cs in direct input mode , the commercial conditions were updated and note 2 is new. 2-121 the v cc33acap signal name was changed to "xtal1 crystal oscillator circuit input" . 2-228 table 2-48 ? uncalibrated analog channel accuracy* is new. 2-123 table 2-49 ? calibrated analog channel accuracy 1,2,3 , is new. 2-124 previous version changes in current version (v2.0) page
part number and revision date v2.0 2-237 advance v0.9 (continued) table 2-50 ? analog channel accuracy: monitoring standard positive voltages is new. 2-125 in table 2-57 ? voltage polarity control truth table?av (x = 0), ac (x = 1), and at (x = 3)* , the following i/o bank names were changed: hot-swap changed to standard lvds changed to advanced 2-131 in table 2-58 ? prescaler op amp power-do wn truth table?av (x = 0), ac (x = 1), and at (x = 3) , the following i/o bank names were changed: hot-swap changed to standard lvds changed to advanced 2-132 in the title of table 2-64 ? i/o standards supported by bank type , lvds i/o was changed to advanced i/o. 2-134 the title was changed from "fusion standard, lvds, and standard plus hot- swap i/o" to table 2-68 ? fusion standard and advanced i/o features . in addition, the table headings were all updated. the heading used to be standard and lvds i/o and was changed to advanced i/o. standard hot-swap was changed to just standard. 2-136 this sentence was deleted from the "slew rate control and drive strength" section : the standard hot-swap i/os do not support slew rate control. in addition, these references were changed: ? from: fusion hot-swap i/o (table 2-69 on page 2-122) to: fusion standard i/o ? from: fusion lvds i/o (table 2-70 on page 2-122) to: fusion advanced i/o 2-152 the "cold-sparing support" section was significantly updated. 2-143 in the title of table 2-75 ? fusion standard i/o standards?out_drive settings , hot-swap was chan ged to standard. 2-153 in the title of table 2-76 ? fusion advanc ed i/o standards?slew and out_drive settings , lvds was changed to advanced. 2-153 in the title of table 2-81 ? fusion standard an d advanced i/o attributes vs. i/o standard applications , lvds was changed to advanced. 2-157 in figure 2-111 ? naming conv entions of fusion device s with three digital i/o banks and figure 2-112 ? naming conventions of fusion devices with four i/o banks the following names were changed: hot-swap changed to standard lvds changed to advanced 2-160 the figure 2-113 ? timing model was updated. 2-161 in the notes for table 2-86 ? summary of ma ximum and mini mum dc input levels applicable to commerc ial and industri al conditions , t j was changed to t a . 2-166 advance v0.7 (january 2007) figure 2-16 ? fusion clocking options and the "rc oscillator" section were updated to change gnd_osc and vcc_osc to gndosc and vccosc. 2-20 , 2-21 figure 2-19 ? fusion ccc options: global buffers with the pll macro was updated to change the positions of oadivrst and oadivhalf, and a note was added. 2-25 the "crystal oscill ator" section was updated to include information about controlling and enabling/disabling the crystal oscillator. 2-22 previous version changes in current version (v2.0) page
fusion family of mi xed-signal flash fpgas device architecture 2-238 v2.0 advance v0.7 (continued) table 2-11 electrical characteri stics of the crystal oscillator was updated to change the typical value of i dynxtal for 0.032?0.2 mhz to 0.19. 2-24 the "1.5 v voltage regulator" section was updated to add "or floating" in the paragraph stating that an external pull -down is required on trst to power down the vr. 2-41 the "1.5 v voltage regu lator" section was updated to include information on powering down with the vr. 2-41 this sentence was updated in the "no-glitch mux (ngmux)" section to delete gla: the glmuxcfg[1:0] configuration bits de termine the source of the clk inputs (i.e., internal signal or glc). 2-32 in table 2-13 ? ngmux configuration and selection table , 10 and 11 were deleted. 2-32 the method to enable sleep mo de was updated for bit 0 in table 2-16 ? rtc control/status register . 2-38 s2 was changed to d2 in figure 2-39 ? read wa veform (pipe mode, 32-bit access) for rd[31:0] was updated. 2-51 the definitions for bits 2 and 3 were updated in table 2-24 ? page status bit definition . 2-52 figure 2-46 ? flashr om timing diagram was updated. 2-58 table 2-26 ? flashrom access time is new. 2-58 figure 2-55 ? write access a fter write onto same address , figure 2-56 ? read access after write onto same address , and figure 2-57 ? write access after read onto same address are new. 2-68 ? 2-70 table 2-31 ? ram4k9 and table 2-32 ? ram512x18 were updated. 2-71 , 2-72 the varef and sample functions were updated in table 2-36 ? analog block pin description . 2-82 the title of figure 2-72 ? timing diagra m for current monitor strobe was updated to add the word "positive." 2-91 the "gate driver" section was updated to give information about the switching rate in high current drive mode. 2-94 the "adc description" section was updated to include information about the sample and busy signals and the ma ximum frequencies for sysclk and adcclk. eq 2-12 was updated to add parentheses around the entire expression in the denominator. 2-102 table 2-46 analog channel specifications and table 2-47 adc characteristics in direct input mode were updated. 2-118 , 2-121 the note was removed from table 2-55 ? analog multiplexer truth table?av (x = 0), ac (x = 1), and at (x = 3) . 2-131 table 2-63 ? internal temperat ure monitor control truth table is new. 2-132 the "cold-sparing support" section was updated to add information about cases where current draw can occur. 2-143 figure 2-104 ? solution 4 was updated. 2-147 table 2-75 ? fusion standard i/o standards?out_drive settings was updated. 2-153 previous version changes in current version (v2.0) page
part number and revision date v2.0 2-239 advance v0.7 (continued) the "gnda ground (analog)" section and "gndaq ground (analog quiet)" section were updated to add information about maximum differential voltage. 2-224 the "v aref analog reference voltage" section and "vpump programming supply voltage" section were updated. 2-226 the "v ccpla/b pll supply voltage" section was updated to include information about the east and west plls. 2-225 the v complf pin description was deleted. n/a the "axy analog input/output" section was updated with information about grounding and floating the pin. 2-226 the voltage range in the "vpump programming supply voltage" section was updated. the parenthetical reference to "pulled up" was removed from the statement, " v pump can be left floating or can be tied (pulled up) to any voltage between 0 v and 3.6 v." 2-225 the "atrtnx temperature monitor return" section was updated with information about grounding and floating the pin. 2-226 the following text was deleted from the "v ref i/o voltage reference" section : (all digital i/o). 2-225 the "ncap negative capacitor" section and "pcap positive capacitor" section were updated to include information about the type of capacitor that is required to connect the two. 2-228 1 f was changed to 100 pf in the "xtal1 crystal oscillator circuit input" . 2-228 the "programming" section was updated to include information about v ccosc . 2-229 advance v0.5 (june 2006) the second paragraph of the "pll macro" section was updated to include information about powerdown. 2-30 the description for bit 0 was updated in table 2-17 rtc control/status register . 2-38 3.9 was changed to 7.8 in the "crystal oscillator (xtal osc)" section . 2-40 . all function descriptions in table 2-18 signals for vrpsm macro . 2-42 in table 2-19 ? flash memo ry block pin names , the rd[31:0] description was updated. 2-43 the "reset" section was updated. 2-61 the "reset" section was updated. 2-64 table 2-35 ? fifo was updated. 2-79 the varef function description was updated in table 2-36 ? analog block pin description . 2-82 the "voltage monitor" section was updated to include information about low power mode and sleep mode. 2-86 the text in the "current monitor" section was changed from 2 mv to 1 mv. 2-90 the "gate driver" section was updated to include in formation about forcing 1 v on the drain. 2-94 the "analog-to-digital converter block" section was updated with the following statement: "all results are msb justified in the adc." 2-99 the information about the adcsta rt signal was updated in the "adc description" section . 2-102 previous version changes in current version (v2.0) page
fusion family of mi xed-signal flash fpgas device architecture 2-240 v2.0 advance v0.5 (continued) table 2-46 analog channel specifications was updated. 2-118 table 2-47 adc characterist ics in direct input mode was updated. 2-121 table 2-51 ? acm address deco de table for analog quad was updated. 2-127 in table 2-53 ? analog quad acm byte assignment , the function and default setting for bit 6 in byte 3 was updated. 2-130 the "introduction" section was updated to include information about digital inputs, outputs, and bibufs. 2-133 in table 2-69 ? fusion pro i/o features , the programmable delay descriptions were updated for the following features: single-ended receiver voltage-referenced differential receiver lvds/lvpecl differential receiver features 2-137 the "user i/o naming co nvention" section was updated to include "v" and "z" descriptions 2-159 the "v cc33pmp analog power supply (3.3 v)" section was updated to include information about avoiding high current draw. 2-224 the "v ccnvm flash memory block power supply (1.5 v)" section was updated to include information about avoiding high current draw. 2-224 the "vmvx i/o supply voltage (quiet)" section was updated to include this statement: vmv and v cci must be connected to th e same power supply and v cci pins within a given i/o bank. 2-185 the "pub push button" section was updated to include information about leaving the pin floating if it is not used. 2-228 the "ptbase pass transistor base" section was updated to include information about leaving the pin floating if it is not used. 2-228 the "ptem pass transistor emitter" section was updated to include information about leaving the pin floating if it is not used. 2-228 advance v0.4 (april 2006) the "voltage regulator power supp ly monitor (vrpsm)" section was updated. 2-42 advance v0.2 (april 2006) figure 2-46 ? flashr om timing diagram was updated. 2-58 the "flashrom" section was updated. 2-57 the "reset" section was updated. 2-61 the "reset" section was updated. 2-64 figure 2-27 real-time counter system was updated. 2-35 table 2-19 ? flash memory block pin names was updated. 2-43 figure 2-33 ? flash memory block diagram was updated to include aux block information. 2-45 figure 2-34 ? flash memory block organization was updated to include aux block information. 2-46 the note in the "program operation" section was updated. 2-48 figure 2-76 ? gate driver example was updated. 2-95 the "analog quad acm description" section was updated. 2-130 previous version changes in current version (v2.0) page
part number and revision date v2.0 2-241 advance v0.2 (continued) information about the maximum pad input frequency was added to the "gate driver" section . 2-94 figure 2-65 ? analog block macro was updated. 2-81 figure 2-65 ? analog block macro was updated. 2-81 the "analog quad" section was updated. 2-84 the "voltage monitor" section was updated. 2-86 the "direct digital input" section was updated. 2-89 the "current monitor" section was updated. 2-90 information about the maximum pad input frequency was added to the "gate driver" section . 2-94 the "temperature monitor" section was updated. 2-96 eq 2-12 is new. 2-103 the "adc description" section was updated. 2-102 figure 2-16 ? fusion clocking options was updated. 2-20 table 2-46 analog channel specifications was updated. 2-118 the notes in table 2-72 ? fusion standard an d advanced i/o ? hot-swap and 5 v input tolerance capabilities were updated. 2-144 the "simultaneously switching outp uts and pcb layout" section is new. 2-149 lvpecl and lvds were updated in table 2-81 ? fusion standard and advanced i/o attributes vs. i/o standard applications . 2-157 lvpecl and lvds were updated in table 2-82 ? fusion pro i/o attributes vs. i/o standard applications . 2-158 the "timing model" was updated. 2-161 all voltage-referenced minimum and maximum dc input and output level tables were updated. n/a all timing characteristic tables were updated n/a table 2-83 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions was updated. 2-165 table 2-79 ? summary of i/o timing char acteristics ? software default settings was updated. 2-134 table 2-93 ? i/o output buffer maximum resistances 1 was updated. 2-171 the "blvds/m-lvds" section is new. blvds and m-lvds are two new i/o standards included in the datasheet. 2-211 the "coremp7 and cortex-m1 software tools" section is new. 2-257 table 2-83 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions was updated. 2-165 table 2-79 ? summary of i/o timing char acteristics ? software default settings was updated. 2-134 table 2-93 ? i/o output buffer maximum resistances 1 was updated. 2-171 the "blvds/m-lvds" section is new. blvds and m-lvds are two new i/o standards included in the datasheet. 2-211 previous version changes in current version (v2.0) page
fusion family of mi xed-signal flash fpgas device architecture 2-242 v2.0
v2.0 3-1 3 ? dc and power characteristics general specifications operating conditions stresses beyond those listed in table 3-1 may cause permanent damage to the device. exposure to absolute ma ximum rated conditions for extended pe riods may affect device reliability. devices should not be operat ed outside the recommended op erating ranges specified in table 3-2 on page 3-3 . table 3-1 ? absolute maxi mum ratings symbol parameter commercial industrial units v cc dc core supply voltage ?0. 3 to 1.65 ?0.3 to 1.65 v v jtag jtag dc voltage ?0.3 to 3.75 ?0.3 to 3.75 v v pump programming voltage ?0.3 to 3.75 ?0.3 to 3.75 v v ccpll analog power supply (pll) ?0 .3 to 1.65 ?0.3 to 1.65 v v cci dc i/o output buffer supply vo ltage ?0.3 to 3.75 ?0.3 to 3.75 v vi i/o input voltage 1 ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (v cci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v v cc33a +3.3 v power supply ?0.3 to 3.75 2 ?0.3 to 3.75 2 v v cc33pmp +3.3 v power supply ?0.3 to 3.75 2 ?0.3 to 3.75 2 v varef voltage reference for adc ?0.3 to 3.75 ?0.3 to 3.75 v v cc15a digital power supply for the analog system ?0.3 to 1.65 ?0.3 to 1.65 v v ccnvm embedded flash power supply ?0 .3 to 1.65 ?0.3 to 1.65 v v ccosc oscillator power supply ?0.3 to 3.75 ?0.3 to 3.75 v notes: 1. the device should be operated within the limits specified by th e datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 3-4 on page 3-4 . 2. analog data not valid beyond 3.65 v. 3. the high current mode has a maximum power limit of 20 mw. appropriate curr ent limit resistors must be used, based on voltage on the pad. 4. for flash programming and rete ntion maximum li mits, refer to table 3-5 on page 3-5 . for recommended operating limits refer to table 3-2 on page 3-3 .
dc and power characteristics 3-2 v2.0 av, ac unpowered, adc reset asserted or unconfigured ?11.0 to 12.6 ?11.0 to 12.0 v analog input (+16 v to +2 v prescale r range) ?0.4 to 12.6 ?0.4 to 12.0 v analog input (+1 v to +0.125 v prescaler range) ?0.4 to 3.75 ?0.4 to 3.75 v analog input (?16 v to ?2 v prescale r range) ?11.0 to 0.4 ?11.0 to 0.4 v analog input (?1 v to ?0.125 v prescaler range) ?3.75 to 0.4 ?3.75 to 0.4 v analog input (direct input to adc) ?0.4 to 3.75 ?0.4 to 3.75 v digital input ?0.4 to 12.6 ?0.4 to 12.0 v ag unpowered, adc reset asserted or unconfigured ?11.0 to 12.6 ?11.0 to 12.0 v low current mode (1 a, 3 a, 10 a , 30 a) ?0.4 to 12.6 ?0.4 to 12.0 v low current mode (?1 a, ?3 a, ?10 a, ?30 a) ?11.0 to 0.4 ?11.0 to 0.4 v high current mode 3 ?11.0 to 12.6 ?11.0 to 12.0 v at unpowered, adc reset asserted or unconfigured ?0.4 to 16.0 ?0.4 to 15.0 v analog input (+16 v, 4 v prescaler range) ?0.4 to 16.0 ?0.4 to 15.0 v analog input (direct input to adc) ?0.4 to 3.75 ?0.4 to 3.75 v digital input ?0.4 to 16.0 ?0.4 to 15.0 v t stg 4 storage temperature ?65 to +150 c t j 4 junction temperature +125 c table 3-1 ? absolute maximum ra tings (continued) symbol parameter commercial industrial units notes: 1. the device should be operated within the limits specified by th e datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 3-4 on page 3-4 . 2. analog data not valid beyond 3.65 v. 3. the high current mode has a maximum power limit of 20 mw. appropriate curr ent limit resistors must be used, based on voltage on the pad. 4. for flash programming and rete ntion maximum li mits, refer to table 3-5 on page 3-5 . for recommended operating limits refer to table 3-2 on page 3-3 .
actel fusion mixed-signal fpgas v2.0 3-3 table 3-2 ? recommended operating conditions symbol parameter commercial industrial units t j junction temperature 0 to +85 ?40 to +100 c v cc 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v v jtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v v pump programming voltage programming mode 3.15 to 3.45 3.15 to 3.45 v operation 3 0 to 3.6 0 to 3.6 v v ccpll analog power supply (pll) 1.4 25 to 1.575 1.425 to 1.575 v v cci 1.5 v dc supply voltage 1.4 25 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3.0 to 3.6 3.0 to 3.6 v v cc33a +3.3 v power supply 2.97 to 3.63 2.97 to 3.63 v v cc33pmp +3.3 v power supply 2.97 to 3.63 2.97 to 3.63 v varef voltage reference for adc 2.527 to 2.593 2.527 to 2.593 v v cc15a 6 digital power supply for the analog system 1.425 to 1.575 1.425 to 1.575 v v ccnvm embedded flash power supply 1. 425 to 1.575 1.425 to 1.575 v v ccosc oscillator power supply 2. 97 to 3.63 2.97 to 3.63 v av, ac 4 unpowered, adc reset asserted or un configured ?10.5 to 12.0 ?10.5 to 11.6 v analog input (+16 v to +2 v prescale r range) ?0.3 to 12.0 ?0.3 to 11.6 v analog input (+1 v to + 0.125 v prescaler range) ?0.3 to 3.6 ?0.3 to 3.6 v analog input (?16 v to ?2 v prescale r range) ?10.5 to 0.3 ?10.5 to 0.3 v analog input (?1 v to ?0.125 v prescaler range) ?3.6 to 0.3 ?3.6 to 0.3 v analog input (direct input to adc) ?0.3 to 3.6 ?0.3 to 3.6 v digital input ?0.3 to 12.0 ?0.3 to 11.6 v ag 4 unpowered, adc reset asserted or un configured ?10.5 to 12.0 ?10.5 to 11.6 v low current mode (1 a, 3 a, 10 a , 30 a) ?0.3 to 12.0 ?0.3 to 11.6 v low current mode (?1 a, ?3 a, ?10 a, ?30 a) ?10.5 to 0.3 ?10.5 to 0.3 v high current mode 5 ?10.5 to 12.0 ?10.5 to 11.6 v at 4 unpowered, adc reset asserted or unconfigured ?0.3 to 15.5 ?0.3 to 14.5 v analog input (+16 v, +4 v prescaler range) ?0.3 to 15.5 ?0.3 to 14.5 v analog input (direct input to adc) ?0.3 to 3.6 ?0.3 to 3.6 v digital input ?0.3 to 15.5 ?0.3 to 14.5 v notes: 1. the ranges given here are for powe r supplies only. the recommended inpu t voltage ranges specific to each i/o standard are given in table 2-82 on page 2-158 . 2. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 3. v pump can be left floating during normal operation (not programming mode). 4. the input voltage may overshoot by up to 500 mv above the recommended ma ximum (150 mv in direct mode), provided the duration of the overshoot is le ss than 50% of the operating lifetime of the device. 5. the ag pad should also conform to the limits as specified in table 2-45 on page 2-110 . 6. violating the v cc15a recommended voltage supply during an embedded flash program cycle can corrupt the page being programmed.
dc and power characteristics 3-4 v2.0 table 3-3 ? input resistance of analog pads pads pad configuration prescaler range input resistance to ground av, ac analog input (direct in put to adc) +16 v to +2 v 1 m (typical) +1 v to +0.125 v > 10 m analog input (positive prescaler) +16 v to +2 v 1 m (typical) +1 v to +0.125 v > 10 m analog input (negative prescaler) ?16 v to ?2 v 1 m (typical) ?1 v to ?0.125 v > 10 m digital input +16 v to +2 v 1 m (typical) current monitor +16 v to +2 v 1 m (typical) ?16 v to ?2 v 1 m (typical) at analog input (direct inpu t to adc) +16 v, +4 v 1 m (typical) analog input (positive prescaler) +16 v, +4 v 1 m (typical) digital input +16 v, +4 v 1 m (typical) temperature monitor +16 v, +4 v > 10 m table 3-4 ? overshoot and undershoot limits 1 v cci average v cci ?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3.0 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at a junction temperature of 85c. 2. the duration is allowed at one cycle out of six clock cycle. if the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/unde rshoot has to be reduced by 0.15 v.
actel fusion mixed-signal fpgas v2.0 3-5 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into ev ery fusion device. these circuits ensure easy transition from the powered off state to the powered up state of the device. the many different supplies can power up in any sequence with minimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 3-1 on page 3-6 . there are five regions to consider during power-up. fusion i/os are activated only if all of the following three conditions are met: 1. v cc and v cci are above the minimum specified trip points ( figure 3-1 ). 2. v cci > v cc ? 0.75 v (typical). 3. chip is in the operating mode. v cci trip point: ramping up: 0.6 v < tr ip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < tr ip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v v cc and v cci ramp-up trip points are about 100 mv hi gher than ramp-dow n trip points. this specifically built-in hysteresis pr events undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tri stated and weakly pulled up to v cci . ? jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns de lay from input buffer activation pll behavior at br ownout condition actel recommends using monotonic power supplies or voltage regula tors to ensure proper power- up behavior. power ramp-up should be monotonic at least until v cc and v ccplx exceed brownout activation levels. the v cc activation level is specified as 1.1 v worst-case (see figure 3-1 on page 3-6 for more details). table 3-5 ? fpga programming, storag e, and operating limits product grade storage temperature element grade programming cycles retention commercial min. t j = 0c fpga/flashrom 500 20 years min. t j = 85c embedded flash < 1,000 20 years < 10,000 10 years < 15,000 5 years industrial min. t j = ?40c fpga/flashrom 500 20 years min. t j = 100c embedded flash < 1,000 20 years < 10,000 10 years < 15,000 5 years
dc and power characteristics 3-6 v2.0 when pll power supply voltage and/or v cc levels drop below th e vcc brownout levels (0.75 v 0.25 v), the pll output lock signal go es low and/or the output clock is lost. figure 3-1 ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cc = v cci + vt v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification
actel fusion mixed-signal fpgas v2.0 3-7 thermal characteristics introduction the temperature variable in the actel designer software refers to the junction temperature, not the ambient, case, or board temperatures. this is an important distinction because dynamic and static power consumption will cause the chip's ju nction temperature to be higher than the ambient, case, or board temperatures. eq 3-1 through eq 3-3 give the relationship between thermal resistance, temperature gradient, and power. eq 3-1 eq 3-2 eq 3-3 where ja = junction-to-air thermal resistance jb = junction-to-board thermal resistance jc = junction-to-case thermal resistance t j = junction temperature t a = ambient temperature t b = board temperature (measured 1.0 mm away from the package edge) t c = case temperature p = total power dissipated by the device table 3-6 ? package thermal resistance product die size ja jc jb units (mm) still air 1.0 m/s 2.5 m/s afs090-qn108 x = 3.4; y = 4.8 34.5 30.0 27.7 8.1 16.7 c/w afs090-qn180 x = 3.4; y = 4.8 33.3 27.6 25.7 9.2 21.2 c/w afs250-qn180 x = 4.0; y = 5.6 32.2 26.5 24.7 5.7 15.0 c/w afs090-fg256 x = 3.4; y = 4. 8 37.7 33.9 32.2 11.5 29.7 c/w afs250-fg256 x = 4.0; y = 5.6 33.7 30.0 28.3 9.3 24.8 c/w afs600-fg256 x = 5.10; y = 7.3 28.9 25.2 23.5 6.8 19.9 c/w afs1500-fg256 x = 7.62; y = 9.98 23.3 19.6 18.0 4.3 14.2 c/w afs600-fg484 x = 5.10; y = 7.3 21.8 18.2 16.7 7.7 16.8 c/w afs1500-fg484 x = 7.62; y = 9.98 21.6 16.8 15.2 5.6 14.9 c/w ja t j a ? p ---------------- - = jb t j t b ? p ---------------- = jc t j t c ? p ---------------- - =
dc and power characteristics 3-8 v2.0 theta-ja junction-to-ambient thermal resistance ( ja ) is determined under standar d conditions specified by jedec (jesd-51), but it has little relevance in actual performance of the product. it should be used with caution but is useful for comparing the thermal performance of one package to another. a sample calculation showing the maximum power di ssipation allowed for the afs600-fg484 package under forced convection of 1.0 m/s and 75c ambient temperature is as follows: eq 3-4 where eq 3-5 the power consumption of a device can be calculat ed using the actel power calculator. the device's power consumption must be lower than the ca lculated maximum powe r dissipation by the package. if the power consumption is higher than the device's ma ximum allowable power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be increased. theta-jb junction-to-board th ermal resistance ( jb ) measures the ability of th e package to dissipate heat from the surface of the chip to the pcb. as defined by the jede c (jesd-51) standard, the thermal resistance from junction to board uses an isothe rmal ring cold plate zone concept. the ring cold plate is simply a means to generate an isothe rmal boundary condition at the perimeter. the cold plate is mounted on a jedec standard board with a minimum distance of 5.0 mm away from the package edge. theta-jc junction-to-case thermal resistance ( jc ) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. it is appl icable for packages used with external heat sinks. constant temperature is applied to the surface in consideration and acts as a boundary condition. this only applies to si tuations where all or n early all of the heat is dissipated through the su rface in consideration. calculation for heat sink for example, in a design implem ented in an afs600-fg484 package with 2.5 m/s ai rflow, the power consumption value using the power calcul ator is 3.00 w. the user-dependent t a and t j are given as follows: from the datasheet: ja = 19.00c/w (taken from table 3-6 on page 3-7 ). t a = 75.00c t j = 100.00c t a = 70.00c ja = 17.00c/w jc = 8.28c/w maximum power allowed t j(max) t a(max) ? ja ------------------------------------------ = maximum power allowed 100.00c 75.00c ? 19.00c/w --------------------------------------------------- - 1.3 w ==
actel fusion mixed-signal fpgas v2.0 3-9 eq 3-6 the 1.76 w power is less than the re quired 3.00 w. the design therefor e requires a heat sink, or the airflow where the device is moun ted should be increased. the desi gn's total junction-to-air thermal resistance requirement can be estimated by eq 3-7 : eq 3-7 determining the heat sink's therma l performance proceeds as follows: eq 3-8 where eq 3-9 a heat sink with a thermal resist ance of 5.01c/w or better shou ld be used. thermal resistance of heat sinks is a function of airflow. the heat si nk performance can be significantly improved with increased airflow. carefully estimating thermal resistance is importan t in the long-term reliab ility of an actel fpga. design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device. note: the junction-to-air and junction-to-board thermal resistances are based on jedec standard (jesd-51) and assumptions made in building the mode l. it may not be realized in actual application and therefore should be used with a degree of caution. junction-to- case thermal resistance assumes that all power is dissipated through the case. temperature and voltage derating factors ja = 0.37c/w = thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer sa = thermal resistance of the heat sink in c/w table 3-7 ? temperature and voltage derating factors for timing delays (normalized to t j = 70c, worst-case v cc = 1.425 v) array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 100c 1.425 0.88 0.93 0.95 1.00 1.02 1.05 1.500 0.83 0.88 0.90 0.95 0.96 0.99 1.575 0.80 0.85 0.87 0.91 0.93 0.96 p t j t a ? ja ---------------- - 100c 70c ? 17.00 w ----------------------------------- 1.76 w == = ja(total) t j t a ? p ---------------- - 100c 70c ? 3.00 w ----------------------------------- 10.00c/w == = ja(total) jc cs sa ++ = sa ja(total) jc ? cs ? = sa 13.33c/w 8.28c/w ? 0.37c/w ? 5.01c/w ==
dc and power characteristics 3-10 v2.0 calculating power dissipation quiescent supply current table 3-8 ? afs1500 quiescent supply current characteristics parameter description condi tions temp. min. typ. max. unit i cc 1 1.5 v quiescent curren t operational standby 4 , v cc =1.575v t j =25c 20 40 ma t j =85c 32 65 ma t j = 100c 59 120 ma standby mode 5 or sleep mode 6 , v cc = 0 v 00 a i cc33 2 3.3 v analog supplies current operational standby 4 , v cc33 =3.63v t j =25c 9.8 13 ma t j = 85c 10.7 14 ma t j = 100c 10.8 15 ma operational standby, only analog quad and ?3.3 v output on, v cc33 = 3.63 v t j =25c 0.31 2 ma t j =85c 0.35 2 ma t j = 100c 0.45 2 ma standby mode 5 , v cc33 = 3.63 v t j = 25c 2.9 3.6 ma t j =85c 2.9 4 ma t j = 100c 3.3 6 ma sleep mode 6 , v cc33 = 3.63 v t j =25c 17 19 a t j =85c 18 20 a t j = 100c 24 25 a i cci 3 i/o quiescent current operational standby 4 , standby mode, and sleep mode 6 , v cci x = 3.63 v t j = 25c 417 649 a t j = 85c 417 649 a t j = 100c 417 649 a notes: 1. i cc is the 1.5 v power supplies, i cc and i cc15a . 2. i cc33a includes i cc33a , i cc33pmp , and i ccosc . 3. i cci includes all i cci0 , i cci1 , i cci2 , and i cci4 . 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0v. 6. sleep mode, v cc =v jtag =v pp =0v.
actel fusion mixed-signal fpgas v2.0 3-11 i jtag jtag i/o quiescent current operational standby 4 , v jtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , v jtag = 0 v 00a i pp programming supply current non-programming mode, v pp = 3.63 v t j =25c 39 80 a t j =85c 40 80 a t j = 100c 40 80 a standby mode 5 or sleep mode 6 , v pp = 0 v 00a i ccnvm embedded nvm current reset asserted, v ccnvm = 1.575 v t j = 25c 50 150 a t j =85c 50 150 a t j = 100c 50 150 a i ccpll 1.5 v pll quiescent current operational standby , v ccpll =1.575v t j = 25c 130 200 a t j = 85c 130 200 a t j = 100c 130 200 a table 3-8 ? afs1500 quiescent supply curren t characteristics (continued) parameter description condi tions temp. min. typ. max. unit notes: 1. i cc is the 1.5 v power supplies, i cc and i cc15a . 2. i cc33a includes i cc33a , i cc33pmp , and i ccosc . 3. i cci includes all i cci0 , i cci1 , i cci2 , and i cci4 . 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0v. 6. sleep mode, v cc =v jtag =v pp =0v.
dc and power characteristics 3-12 v2.0 table 3-9 ? afs600 quiescent supply current characteristics parameter description conditions temp. min typ max unit i cc 1 1.5 v quiescent current operational standby 4 , v cc = 1.575 v t j =25c 13 25 ma t j =85c 20 45 ma t j =100c 25 75 ma standby mode 5 or sleep mode 6 , v cc = 0 v 00a i cc33 2 3.3 v analog supplies current operational standby 4 , v cc33 = 3.63 v t j = 25c 9.8 13 ma t j = 85c 10.7 14 ma t j = 100c 10.8 15 ma operational standby, only analog quad and ?3.3 v output on, v cc33 = 3.63 v t j =25c 0.31 2 ma t j =85c 0.35 2 ma t j = 100c 0.45 2 ma standby mode 5 , v cc33 = 3.63 v t j = 25c 2.8 3.6 ma t j =85c 2.9 4 ma t j = 100c 3.5 6 ma sleep mode 6 , v cc33 = 3.63 v t j =25c 17 19 a t j =85c 18 20 a t j = 100c 24 25 a i cci 3 i/o quiescent current operational standby 4 , v cci x = 3.63 v t j = 25c 417 648 a t j = 85c 417 648 a t j = 100c 417 649 a i jtag jtag i/o quiescent current operational standby 4 , v jtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , v jtag = 0 v 00a notes: 1. i cc is the 1.5 v power supplies, i cc and i cc15a . 2. i cc33a includes i cc33a , i cc33pmp , and i ccosc . 3. i cci includes all i cci0 , i cci1 , i cci2 , and i cci4 . 4. operational standby is when the fu sion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0v. 6. sleep mode, v cc =v jtag =v pp =0v.
actel fusion mixed-signal fpgas v2.0 3-13 i pp programming supply current non-programming mode, v pp = 3.63 v t j =25c 36 80 a t j =85c 36 80 a t j = 100c 36 80 a standby mode 5 or sleep mode 6 , v pp = 0 v 00a i ccnvm embedded nvm current reset asserted, v ccnvm = 1.575 v t j =25c 22 80 a t j =85c 24 80 a t j = 100c 25 80 a i ccpll 1.5 v pll quiescent curre nt operational standby, v ccpll = 1.575 v t j = 25c 130 200 a t j = 85c 130 200 a t j = 100c 130 200 a table 3-9 ? afs600 quiescent supply current characteristics (continued) parameter description conditions temp. min typ max unit notes: 1. i cc is the 1.5 v power supplies, i cc and i cc15a . 2. i cc33a includes i cc33a , i cc33pmp , and i ccosc . 3. i cci includes all i cci0 , i cci1 , i cci2 , and i cci4 . 4. operational standby is when the fu sion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0v. 6. sleep mode, v cc =v jtag =v pp =0v.
dc and power characteristics 3-14 v2.0 table 3-10 ? afs250 quiescent supply current characteristics parameter description conditions temp. min typ max unit i cc 1 1.5 v quiescent current operational standby 4 , v cc = 1.575 v t j = 25c 4.8 10 ma t j = 85c 8.2 30 ma t j = 100c 15 50 ma standby mode 5 or sleep mode 6 , v cc = 0 v 00a i cc33 2 3.3 v analog supplies current operational standby 4 , v cc33 = 3.63 v t j = 25c 9.8 13 ma t j = 85c 9.8 14 ma t j = 100c 10.8 15 ma operational standby, only analog quad and ?3.3 v output on, v cc33 = 3.63 v t j =25c 0.29 2 ma t j =85c 0.31 2 ma t j = 100c 0.45 2 ma standby mode 5 , v cc33 = 3.63v t j = 25c 2.9 3.0 ma t j = 85c 2.9 3.1 ma t j = 100c 3.5 6 ma sleep mode 6 , v cc33 = 3.63 v t j =25c 19 18 a t j =85c 19 20 a t j = 100c 24 25 a i cci 3 i/o quiescent current operational standby 6 , v cci x = 3.63 v t j = 25c 266 437 a t j = 85c 266 437 a t j = 100c 266 437 a i jtag jtag i/o quiescent current operational standby 4 , v jtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , v jtag = 0 v 00a notes: 1. i cc is the 1.5 v power supplies, i cc , i ccpll , i cc15a , i ccnvm . 2. i cc33a includes i cc33a , i cc33pmp , and i ccosc . 3. i cci includes all i cci0 , i cci1 , and i cci2 . 4. operational standby is when the fu sion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0v. 6. sleep mode, v cc =v jta g =v pp =0v.
actel fusion mixed-signal fpgas v2.0 3-15 i pp programming supply current non-programming mode, v pp = 3.63 v t j =25c 37 80 a t j =85c 37 80 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , v pp = 0 v 00a i ccnvm embedded nvm current reset asserted, v ccnvm = 1.575 v t j =25c 10 40 a t j =85c 14 40 a t j = 100c 14 40 a i ccpll 1.5 v pll quiescent curre nt operational standby, v ccpll = 1.575 v t j = 25c 65 100 a t j = 85c 65 100 a t j = 100c 65 100 a table 3-10 ? afs250 quiescent supply current characteristics (continued) parameter description conditions temp. min typ max unit notes: 1. i cc is the 1.5 v power supplies, i cc , i ccpll , i cc15a , i ccnvm . 2. i cc33a includes i cc33a , i cc33pmp , and i ccosc . 3. i cci includes all i cci0 , i cci1 , and i cci2 . 4. operational standby is when the fu sion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0v. 6. sleep mode, v cc =v jta g =v pp =0v.
dc and power characteristics 3-16 v2.0 table 3-11 ? afs090 quiescent supply current characteristics parameter description conditions temp. min typ max unit i cc 1 1.5 v quiescent current operational standby 4 , v cc = 1.575 v t j = 25c 5 7.5 ma t j = 85c 6.5 20 ma t j = 100c 14 48 ma standby mode 5 or sleep mode 6 , v cc = 0 v 00a i cc33 2 3.3 v analog supplies current operational standby 4 , v cc33 = 3.63 v t j = 25c 9.8 12 ma t j = 85c 9.8 12 ma t j = 100c 10.7 15 ma operational standby, only analog quad and ?3.3 v output on, v cc33 = 3.63 v t j =25c 0.30 2 ma t j =85c 0.30 2 ma t j = 100c 0.45 2 ma standby mode 5 , v cc33 = 3.63 v t j = 25c 2.9 2.9 ma t j = 85c 2.9 3.0 ma t j = 100c 3.5 6 ma sleep mode 6 , v cc33 = 3.63 v t j = 25c 17 18 a t j =85c 18 20 a t j = 100c 24 25 a i cci 3 i/o quiescent current operational standby 6 , v cci x = 3.63 v t j = 25c 260 437 a t j = 85c 260 437 a t j = 100c 260 437 a i jtag jtag i/o quiescent current operational standby 4 , v jtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , v jtag = 0 v 00a i pp programming supply current non-programming mode, v pp = 3.63 v t j =25c 37 80 a t j =85c 37 80 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , v pp = 0 v 00a notes: 1. i cc is the 1.5 v power supplies, i cc , i ccpll , i cc15a , i ccnvm . 2. i cc33a includes i cc33a , i cc33pmp, and i ccosc . 3. i cci includes all i cci0 , i cci1 , and i cci2 . 4. operational standby is when the fu sion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0 v. 6. sleep mode, v cc =v jtag =v pp =0v.
actel fusion mixed-signal fpgas v2.0 3-17 i ccnvm embedded nvm current reset asserted, v ccnvm = 1.575 v t j =25c 10 40 a t j =85c 14 40 a t j = 100c 14 40 a i ccpll 1.5 v pll quiescent curre nt operational standby, v ccpll = 1.575 v t j = 25c 65 100 a t j = 85c 65 100 a t j = 100c 65 100 a table 3-11 ? afs090 quiescent supply current characteristics (continued) parameter description conditions temp. min typ max unit notes: 1. i cc is the 1.5 v power supplies, i cc , i ccpll , i cc15a , i ccnvm . 2. i cc33a includes i cc33a , i cc33pmp, and i ccosc . 3. i cci includes all i cci0 , i cci1 , and i cci2 . 4. operational standby is when the fu sion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is lo aded with 200 ma, v cc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, v cc =v jtag =v pp =0 v. 6. sleep mode, v cc =v jtag =v pp =0v.
dc and power characteristics 3-18 v2.0 power per i/o pin table 3-12 ? summary of i/o input buffer power (per pin)?default i/o software settings v cci (v) static power p dc7 (mw) 1 dynamic power p ac9 (w/mhz) 2 applicable to pro i/o banks single-ended 3.3 v lvttl/lvcmos 3.3 ? 17.39 3.3 v lvttl/lvcmos ? schmitt trigger 3.3 ? 25.51 2.5 v lvcmos 2.5 ? 5.76 2.5 v lvcmos ? schmitt trigger 2.5 ? 7.16 1.8 v lvcmos 1.8 ? 2.72 1.8 v lvcmos ? schmitt trigger 1.8 ? 2.80 1.5 v lvcmos (jesd8-11) 1.5 ? 2.08 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 ? 2.00 3.3 v pci 3.3 ? 18.82 3.3 v pci ? schmitt trigger 3.3 ? 20.12 3.3 v pci-x 3.3 ? 18.82 3.3 v pci-x ? schmitt trigger 3.3 ? 20.12 voltage-referenced 3.3 v gtl 3.3 2.90 8.23 2.5 v gtl 2.5 2.13 4.78 3.3 v gtl+ 3.3 2.81 4.14 2.5 v gtl+ 2.5 2.57 3.71 hstl (i) 1.5 0.17 2.03 hstl (ii) 1.5 0.17 2.03 sstl2 (i) 2.5 1.38 4.48 sstl2 (ii) 2.5 1.38 4.48 sstl3 (i) 3.3 3.21 9.26 sstl3 (ii) 3.3 3.21 9.26 differential lvds 2.5 2.26 1.50 lvpecl 3.3 5.71 2.17 notes: 1. p dc7 is the static power (where applicable) measured on v cci . 2. p ac9 is the total dynamic power measured on v cc and v cci .
actel fusion mixed-signal fpgas v2.0 3-19 applicable to advanced i/o banks single-ended 3.3 v lvttl/lvcmos 3.3 ? 16.69 2.5 v lvcmos 2.5 ? 5.12 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.45 3.3 v pci 3.3 ? 18.11 3.3 v pci-x 3.3 ? 18.11 differential lvds 2.5 2.26 1.20 lvpecl 3.3 5.72 1.87 applicable to standard i/o banks 3.3 v lvttl/lvcmos 3.3 ? 16.79 2.5 v lvcmos 2.5 ? 5.19 1.8 v lvcmos 1.8 ? 2.18 1.5 v lvcmos (jesd8-11) 1.5 ? 1.52 table 3-12 ? summary of i/o input buffer power (per pin) ?default i/o software settings (continued) v cci (v) static power p dc7 (mw) 1 dynamic power p ac9 (w/mhz) 2 notes: 1. p dc7 is the static power (where applicable) measured on v cci . 2. p ac9 is the total dynamic power measured on v cc and v cci .
dc and power characteristics 3-20 v2.0 table 3-13 ? summary of i/o output buffer power (p er pin)?default i/o software settings 1 c load (pf) v cci (v) static power p dc8 (mw) 2 dynamic power p ac10 (w/mhz) 3 applicable to pro i/o banks single-ended 3.3 v lvttl/lvcmos 35 3.3 ? 474.70 2.5 v lvcmos 35 2.5 ? 270.73 1.8 v lvcmos 35 1.8 ? 151.78 1.5 v lvcmos (jesd8-11) 35 1.5 ? 104.55 3.3 v pci 10 3.3 ? 204.61 3.3 v pci-x 10 3.3 ? 204.61 voltage-referenced 3.3 v gtl 10 3.3 ? 24.08 2.5 v gtl 10 2.5 ? 13.52 3.3 v gtl+ 10 3.3 ? 24.10 2.5 v gtl+ 10 2.5 ? 13.54 hstl (i) 20 1.5 7.08 26.22 hstl (ii) 20 1.5 13.88 27.22 sstl2 (i) 30 2.5 16.69 105.56 sstl2 (ii) 30 2.5 25.91 116.60 sstl3 (i) 30 3.3 26.02 114.87 sstl3 (ii) 30 3.3 42.21 131.76 differential lvds ? 2.5 7.70 89.62 lvpecl ? 3.3 19.42 168.02 applicable to advanced i/o banks single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 149.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 103.12 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 notes: 1. dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. p dc8 is the static power (where applicable) measured on v cci . 3. p ac10 is the total dynamic power measured on v cc and v cci .
actel fusion mixed-signal fpgas v2.0 3-21 differential lvds ? 2.5 7.74 88.92 lvpecl ? 3.3 19.54 166.52 applicable to standard i/o banks single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 431.08 2.5 v lvcmos 35 2.5 ? 247.36 1.8 v lvcmos 35 1.8 ? 128.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 89.46 table 3-13 ? summary of i/o output buffer power (p er pin)?default i/o software settings 1 (continued) c load (pf) v cci (v) static power p dc8 (mw) 2 dynamic power p ac10 (w/mhz) 3 notes: 1. dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. p dc8 is the static power (where applicable) measured on v cci . 3. p ac10 is the total dynamic power measured on v cc and v cci .
dc and power characteristics 3-22 v2.0 dynamic power consumption of various internal resources table 3-14 ? different components contributing to the dynamic power consumption in fusion devices parameter definition power supply device-specific dynamic contributions units name setting afs1500 afs600 afs250 afs090 p ac1 clock contribution of a global rib v cc 1.5 v 14.5 12.8 11 11 w/mhz p ac2 clock contribution of a global spine v cc 1.5 v 2.5 1.9 1.6 0.8 w/mhz p ac3 clock contribution of a versatile row v cc 1.5 v 0.81 w/mhz p ac4 clock contribution of a versatile used as a sequential module v cc 1.5 v 0.11 w/mhz p ac5 first contribution of a versatile used as a sequential module v cc 1.5 v 0.07 w/mhz p ac6 second contribution of a versatile used as a sequential module v cc 1.5 v 0.29 w/mhz p ac7 contribution of a versatile used as a combinatorial module v cc 1.5 v 0.29 w/mhz p ac8 average contribution of a routing net v cc 1.5 v 0.70 w/mhz p ac9 contribution of an i/o input pin (standard dependent) v cci see table 3-12 on page 3-18 p ac10 contribution of an i/o output pin (standard dependent) v cci see table 3-13 on page 3-20 p ac11 average contribution of a ram block during a read operation v cc 1.5 v 25 w/mhz p ac12 average contribution of a ram block during a write operation v cc 1.5 v 30 w/mhz p ac13 dynamic contribution for pll v cc 1.5 v 2.6 w/mhz p ac15 contribution of nvm block during a read operation (f < 33mhz) v cc 1.5 v 358 w/mhz p ac16 1st contribution of nvm block during a read operation (f > 33mhz) v cc 1.5 v 12.88 mw
actel fusion mixed-signal fpgas v2.0 3-23 p ac17 2nd contribution of nvm block during a read operation (f > 33mhz) v cc 1.5 v 4.8 w/mhz p ac18 crystal oscillator contribution v cc33a 3.3 v 0.63 mw p ac19 rc oscillator contribution v cc33a 3.3 v 3.3 mw p ac20 analog block dynamic power contribution of adc v cc 1.5 v 3 mw table 3-14 ? different components contributing to the dynamic power consumption in fusion devices parameter definition power supply device-specific dynamic contributions units name setting afs1500 afs600 afs250 afs090
dc and power characteristics 3-24 v2.0 static power consumption of various internal resources table 3-15 ? different components contributing to the st atic power consumption in fusion devices parameter definition power supply device-specific static contributions units afs1500 afs600 afs250 afs090 p dc1 core static power contribution in operating mode v cc 1.5 v 18 7.5 4.50 3.00 mw p dc2 device static power contribution in standby mode v cc33a 3.3 v 0.66 mw p dc3 device static power contribution in sleep mode v cc33a 3.3 v 0.03 mw p dc4 nvm static power contribution v cc 1.5 v 1.19 mw p dc5 analog block static power contribution of adc v cc33a 3.3 v 8.25 mw p dc6 analog block static power contribution per quad v cc33a 3.3 v 3.3 mw p dc7 static contribution per input pin ? standard dependent contribution v cci see table 3-12 on page 3-18 p dc8 static contribution per input pin ? standard dependent contribution v cci see table 3-13 on page 3-20 p dc9 static contribution for pll v cc 1.5 v 2.55 mw
actel fusion mixed-signal fpgas v2.0 3-25 power calculation methodology this section describes a simplified method to estimate power consumptio n of an application. for more accurate and detailed power estimations, use the smartpower tool in the libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number and the frequency of each output clock generated ? the number of combinatorial and se quential cells used in the design ?the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? the number of nvm blocks used in the design ? the number of analog quads used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 3-16 on page 3-29 . ? enable rates of output buffers?guidelines are provided for typical applications in table 3-17 on page 3-29 . ? read rate and write rate to the ram?guidelin es are provided for typical applications in table 3-17 on page 3-29 . ? read rate to the nvm blocks the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total operating mode, standb y mode, and sleep mode p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat operating mode p stat = p dc1 + (n nvm-blocks * p dc4 ) + p dc5 + (n quads * p dc6 ) + (n inputs * p dc7 ) + (n outputs * p dc8 ) + (n plls * p dc9 ) n nvm-blocks is the number of nvm blocks available in the device. n quads is the number of analog quads used in the design. n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. n plls is the number of plls available in the device. standby mode p stat = p dc2 sleep mode p stat = p dc3 total dynamic power consumption?p dyn operating mode p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll + p nvm + p xtl-osc + p rc-osc + p ab
dc and power characteristics 3-26 v2.0 standby mode p dyn = p xtl-osc sleep mode p dyn = 0 w global clock dynamic contribution?p clock operating mode p clock = (p ac1 + n spine * p ac2 + n row * pac3 + n s-cell * p ac4 ) * f clk n spine is the number of global sp ines used in the user desi gn?guidelines are provided in table 3-16 on page 3-29 . n row is the number of versatile rows used in the design?guidelines are provided in table 3-16 on page 3-29 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. standby mode and sleep mode p clock = 0 w sequential cells dynamic contribution?p s-cell operating mode p s-cell = n s-cell * (p ac5 + ( 1 / 2) * p ac6 ) * f clk n s-cell is the number of versatiles used as sequ ential modules in the design. when a multi- tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-16 on page 3-29 . f clk is the global clock signal frequency. standby mode and sleep mode p s-cell = 0 w combinatorial cells dynamic contribution?p c-cell operating mode p c-cell = n c-cell * ( 1 / 2) * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-16 on page 3-29 . f clk is the global clock signal frequency. standby mode and sleep mode p c-cell = 0 w routing net dynamic contribution?p net operating mode p net = (n s-cell + n c-cell ) * ( 1 / 2) * p ac8 * f clk n s-cell is the number versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-16 on page 3-29 . f clk is the global clock signal frequency.
actel fusion mixed-signal fpgas v2.0 3-27 standby mode and sleep mode p net = 0 w i/o input buffer dynamic contribution?p inputs operating mode p inputs = n inputs * ( 2 / 2) * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 3-16 on page 3-29 . f clk is the global clock signal frequency. standby mode and sleep mode p inputs = 0 w i/o output buffer dynamic contribution?p outputs operating mode p outputs = n outputs * ( 2 / 2) * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 3-16 on page 3-29 . 1 is the i/o buffer enable rate?guidelines are provided in table 3-17 on page 3-29 . f clk is the global clock signal frequency. standby mode and sleep mode p outputs = 0 w ram dynamic contribution?p memory operating mode p memory = (n blocks * p ac11 * 2 * f read-clock ) + (n blocks * p ac12 * 3 * f write-clock ) n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read op erations?guidelines are provided in table 3-17 on page 3-29 . 3 the ram enable rate for write oper ations?guidelines are provided in table 3-17 on page 3-29 . f write-clock is the memory write clock frequency. standby mode and sleep mode p memory = 0 w pll/ccc dynamic contribution?p pll operating mode p pll = p ac13 * f clkout f clkin is the input clock frequency. f clkout is the output clock frequency. 1 standby mode and sleep mode p pll = 0 w 1. the pll dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution.
dc and power characteristics 3-28 v2.0 nonvolatile memory dynamic contribution?p nvm operating mode the nvm dynamic power consumption is a piecewise linear function of frequency. p nvm = n nvm-blocks * 4 * p ac15 * f read-nvm when f read-nvm 33 mhz, p nvm = n nvm-blocks * 4 *(p ac16 + p ac17 * f read-nvm ) when f read-nvm > 33 mhz n nvm-blocks is the number of nvm blocks us ed in the design (2 inafs600). 4 is the nvm enable rate for read operations . default is 0 (nvm mainly in idle state). f read-nvm is the nvm read clock frequency. standby mode and sleep mode p nvm = 0 w crystal oscillator dynamic contribution?p xtl-osc operating mode p xtl-osc = p ac18 standby mode p xtl-osc = p ac18 sleep mode p xtl-osc = 0 w rc oscillator dynamic contribution?p rc-osc operating mode p rc-osc = p ac19 standby mode and sleep mode p rc-osc = 0 w analog system dynamic contribution?p ab operating mode p ab = p ac20 standby mode and sleep mode p ab = 0 w
actel fusion mixed-signal fpgas v2.0 3-29 guidelines toggle rate definition a toggle rate defines the frequency of a net or logi c element relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that the net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8. enable rate definition output enable rate is the average percentage of time during which tris tate outputs are enabled. when non-tristate output buffers are us ed, the enable rate should be 100%. table 3-16 ? toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10% table 3-17 ? enable rate guidelines reco mmended for power calculation component defini tion guideline 1 i/o output buffer enable rate 100% 2 ram enable rate for read operations 12.5% 3 ram enable rate for wr ite operations 12.5% 4 nvm enable rate for read operations 0%
dc and power characteristics 3-30 v2.0 example of power calculation this example considers a shift register with 5,0 00 storage tiles, including a counter and memory that stores analog information. the shift regist er is clocked at 50 mhz and stores and reads information from a ram. the device used is a commercial afs600 device operating in typical conditions. the calculation below uses the power calculation methodology pr eviously presented and shows how to determine the dynamic and static power cons umption of resources us ed in the application. also included in the example is the calculation of power consumption in operating, standby, and sleep modes to illustrate the be nefit of power-saving modes. global clock contribution?p clock f clk = 50 mhz number of sequential versatiles: n s-cell = 5,000 estimated number of spines: n spines = 5 estimated number of rows: n row = 313 operating mode p clock = (p ac1 + n spine * p ac2 + n row * pac3 + n s-cell * p ac4 ) * f clk p clock = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50 p clock = 41.28 mw standby mode and sleep mode p clock = 0 w logic?sequential cells, combinationa l cells, and routing net contributions?p s-cell , p c-cell , and p net f clk = 50 mhz number of sequential versatiles: n s-cell = 5,000 number of combinatorial versatiles: n c-cell = 6,000 estimated toggle rate of versatile outputs: 1 = 0.1 (10%) operating mode p s-cell = n s-cell * (p ac5 + ( 1 / 2) * p ac6 ) * f clk p s-cell = 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50 p s-cell = 21.13 mw p c-cell = n c-cell * ( 1 / 2) * p ac7 * f clk p c-cell = 6,000 * (0.1 / 2) * 0.00029 * 50 p c-cell = 4.35 mw p net = (n s-cell + n c-cell ) * ( 1 / 2) * p ac8 * f clk p net = (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50 p net = 19.25 mw p logic = p s-cell + p c-cell + p net p logic = 21.13 mw + 4.35 mw + 19.25 mw p logic = 44.73 mw standby mode and sleep mode
actel fusion mixed-signal fpgas v2.0 3-31 p s-cell = 0 w p c-cell = 0 w p net = 0 w p logic = 0 w i/o input and output buffer contribution?p i/o this example uses lvttl 3.3 v i/o cells. the ou tput buffers are 12 ma?capable, configured with high output slew and driving a 35 pf output load. f clk = 50 mhz number of input pins used: n inputs = 30 number of output pins used: n outputs = 40 estimated i/o buffer toggle rate: 2 = 0.1 (10%) estimated io buffer enable rate: 1 = 1 (100%) operating mode p inputs = n inputs * ( 2 / 2) * p ac9 * f clk p inputs = 30 * (0.1 / 2) * 0.01739 * 50 p inputs = 1.30 mw p outputs = n outputs * ( 2 / 2) * 1 * p ac10 * f clk p outputs = 40 * (0.1 / 2) * 1 * 0.4747 * 50 p outputs = 47.47 mw p i/o = p inputs + p outputs p i/o = 1.30 mw + 47.47 mw p i/o = 48.77 mw standby mode and sleep mode p inputs = 0 w p outputs = 0 w p i/o = 0 w ram contribution?p memory frequency of read clock: f read-clock = 10 mhz frequency of write clock: f write-clock = 10 mhz number of ram blocks: n blocks = 20 estimated ram read enable rate: 2 = 0.125 (12.5%) estimated ram write enable rate: 3 = 0.125 (12.5%) operating mode p memory = (n blocks * p ac11 * 2 * f read-clock ) + (n blocks * p ac12 * 3 * f write-clock ) p memory = (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10) p memory = 1.38 mw standby mode and sleep mode p memory = 0 w pll/ccc contribution?p pll pll is not used in this application.
dc and power characteristics 3-32 v2.0 p pll = 0 w nonvolatile memory?p nvm nonvolatile memory is not used in this application. p nvm = 0 w crystal oscillator?p xtl-osc the application utilizes standby mode. the cry stal oscillator is assumed to be active. operating mode p xtl-osc = p ac18 p xtl-osc = 0.63 mw standby mode p xtl-osc = p ac18 p xtl-osc = 0.63 mw sleep mode p xtl-osc = 0 w rc oscillator?p rc-osc operating mode p rc-osc = p ac19 p rc-osc = 3.30 mw standby mode and sleep mode p rc-osc = 0 w analog system?p ab number of quads used: n quads = 4 operating mode p ab = p ac20 p ab = 3.00 mw standby mode and sleep mode p ab = 0 w total dynamic power consumption?p dyn operating mode p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll + p nvm + p xtl-osc + p rc- osc + p ab p dyn = 41.28 mw + 21.1 mw + 4.35 mw + 19.25 mw + 1.30 mw + 47.47 mw + 1.38 mw + 0 + 0 + 0.63 mw + 3.30 mw + 3.00 mw p dyn = 143.06 mw standby mode p dyn = p xtl-osc p dyn = 0.63 mw sleep mode p dyn = 0 w
actel fusion mixed-signal fpgas v2.0 3-33 total static power consumption?p stat number of quads used: n quads = 4 number of nvm blocks available (afs600): n nvm-blocks = 2 number of input pins used: n inputs = 30 number of output pins used: n outputs = 40 operating mode p stat = p dc1 + (n nvm-blocks * p dc4 ) + p dc5 + (n quads * p dc6 ) + (n inputs * p dc7 ) + (n outputs * p dc8 ) p stat = 7.50 mw + (2 * 1.19 mw) + 8.25 mw + (4 * 3.30 mw) + (30 * 0.00) + (40 * 0.00) p stat = 31.33 mw standby mode p stat = p dc2 p stat = 0.03 mw sleep mode p stat = p dc3 p stat = 0.03 mw total power consumption?p total in operating mode, the total power cons umption of the device is 174.39 mw: p total = p stat + p dyn p total = 143.06 mw + 31.33 mw p total = 174.39 mw in standby mode, the total powe r consumption of the device is limited to 0.66 mw: p total = p stat + p dyn p total = 0.03 mw + 0.63 mw p total = 0.66 mw in sleep mode, the total power consumption of the device drops as low as 0.03 mw: p total = p stat + p dyn p total = 0.03 mw
dc and power characteristics 3-34 v2.0 power consumption table 3-18 ? power consumption parameter description condition min. typical max. units crystal oscillator i stbxtal standby current of crystal oscillator 10 a i dynxtal operating current rc 0.6 ma 0.032?0.2 0.19 ma 0.2?2.0 0.6 ma 2.0?20.0 0.6 ma rc oscillator i dynrc operating current 1 ma acm operating current (fixed clock) 200 a/mhz operating current (user clock) 30 a nvm system nvm array operating power idle 795 a read operation see table 3-15 on page 3-24 . see table 3-15 on page 3-24 . erase 900 a write 900 a p nvmctrl nvm controller operating power 20 w/mhz
actel fusion mixed-signal fpgas v2.0 3-35 part number and revision date part number 51700092-015-1 revised july 2009 list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v2.0) page preliminary v1.7 (october 2008) the microblade and fusion datasheets have been combined. pigeon point information is new. coremp7 support was removed since it is no longer offered. ?f was removed from the datasheet since it is no longer offered. the operating temperature was changed from ambient to junction to better reflect actual conditions of operations. commercial: 0c to 85c industrial: ?4 0c to 100c the version number category was chan ged from preliminary to production, which means the datasheet contai ns information based on final characterization. th e version number changed from preliminary v1.7 to v2.0. n/a v cc33pmp was added to table 3-1 absolute maximum ratings . in addition, conditions for av, ac, ag, and at were also updated. 3-1 v cc33pmp was added to table 3-2 recommended operating conditions . in addition, conditions for av, ac, ag, and at were also updated. 3-3 table 3-5 fpga programming, st orage, and operating limits was updated to include new data and the temperature ranges were changed. the notes were removed from the table. 3-5 table 3-6 package thermal resistance was updated to include new data. 3-7 in eq 3-4 to eq 3-6 , the junction temperature wa s changed from 110c to 100c. 3-8 to 3-9 table 3-8 afs1500 quiescent supply current characteristics through table 3-11 afs090 quiescent su pply current characteristics are new and have replaced the quiescent supply cu rrent characteristi cs (iddq) table. 3-10 to 3-16 in table 3-14 different components contributing to the dynamic power consumption in fusion devices , the power su pply for p ac9 and p ac10 were changed from vmv/v cc to v cci . 3-22 in table 3-15 different components con tributing to the static power consumption in fusion devices , the power supply for p dc7 and p dc8 were changed from vmv/v cc to v cci . p dc1 was updated from tbd to 18. 3-24 advance v1.6 (august 2008) the version number category was change d from advance to preliminary, which means the datasheet contains information based on simulation and/or initial characterization. th e information is believed to be correct, but changes are possible. n/a advance v1.4 (july 2008) the title of the datasheet changed fr om actel programmable system chips to actel fusion mixed- signal fpgas. in addition, all instances of programmable system chip were changed to mixed-signal fpga. n/a advance v1.3 (july 2008) in table 3-8 quiescent supply cu rrent characteristics (iddq)1 , footnote references were updated for i dc2 and i dc3 . footnote 3 and 4 were updated and footnote 5 is new. 3-11
dc and power characteristics 3-36 v2.0 advance v1.1 table 3-6 package thermal resistance was significantly updated 3-7 table 3-14 different components con tributing to th e dynamic power consumption in fusion devices was signific antly updated. 3-22 table3-16toggle rate guidelines recommended for po wer calculation was significantly updated. 3-29 advance v0.9 in table 3-1 absolute maximum ratings , the at for the unpowered, adc reset asserted or unconfigured parame ter, ?11 was changed to ?0.4. 3-1 the units column of table 3-2 recommended operating conditions was incomplete in the previous version. v was added to all the rows. in addition, at for the unpowered, adc reset asserted or unconfigured parameter, ?10.5 was changed to ?0.3. note 6 was updated to include v cc15a . 3-3 in the title of table 3-3 input resistance of analog pads , impedance was changed to resistance. 3-4 in table 3-5 fpga programming, st orage, and operating limits , note 2 is new. "program" was removed from the table heading in the retention column. 3-5 the "pll behavior at browno ut condition" section is new. 3-5 table 3-7 temperature and voltage de rating factors for timing delays was updated. 3-9 in the table 3-12 summary of i/o input buff er power (per pin)?default i/o software settings , the hstl (i) for the static power pdc7 (mw) was changed from 0.1 to 0.17. 3-18 the table 3-14 different components co ntributing to th e dynamic power consumption in fusion devices was updated. 3-22 the table 3-15 different components contributing to the static power consumption in fusion devices was updated. 3-24 in the "pll/ccc dynamic contribution?p pll " section , p ac14 was deleted. 3-27 advance v0.8 (june 2007) in table 3-6 package thermal resistance , the data for the following device/packages were updated: afs090-fg256 afs250-fg256 afs600-fg256 afs1500-fg256 afs600-fg484 afs1500-fg484 afs1500-fg676 3-7 advance v0.7 (january 2007) the vmv pins have now been tied internally with the v cci pins. n/a the v complf pin description was deleted. n/a table 3-1 absolute maximum ratings , table 3-2 recommended operating conditions , and table 3-3 input resistance of analog pads were updated. 3-1 to 3-4 table 3-5 fpga programming, st orage, and operating limits was updated. 3-5 p ac13 and p ac14 were updated in table3-14different co mponents contributing to the dynamic power consumption in fusion devices . 3-22 the operating mode for the "pll/ccc dynamic contribution?p pll " section was updated. 3-27 table 3-18 power consumption was updated to change the typical value of i dynxtal for 0.032?0.2 mhz to 0.19. 3-34 previous version changes in current version (v2.0) page
actel fusion mixed-signal fpgas v2.0 3-37 advance v0.5 (june 2006) table 3-3 input resistance of analog pads is new. 3-4 advance v0.4 (april 2006) the low power modes of operation were updated and clarified. n/a advance v0.2 (april 2006) table 3-8 quiescent supply current characteristics (iddq)1 was updated. 3-11 table 3-14 different components con tributing to th e dynamic power consumption in fusion devices was updated. 3-22 table 3-14 different components con tributing to th e dynamic power consumption in fusion devices was updated. 3-22 the "example of power calculation" was updated. 3-30 the analog system info rmation was deleted from table3-18power consumption . 3-34 previous version changes in current version (v2.0) page
dc and power characteristics 3-38 v2.0 actel safety critical, life support, and high-reliability applications policy the actel products described in this advance st atus datasheet may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information.
v2.0 4-1 actel fusion mixed-signal fpgas 4 ? package pin assignments 108-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/so lutions/package/default.aspx . note: the die attach paddle center of th e package is tied to ground (gnd). a1 b41 b52 a44 a56 b26 b14 a28 a15 a14 b1 b13 a43 a29 b40 b27 pin a1 mark
actel fusion family of mixed-sign al fpgas package pin assignments 4-2 v2.0 108-pin qfn pin number afs090 function a1 nc a2 gndq a3 gaa2/io52pdb3v0 a4 gnd a5 gfa1/io47pdb3v0 a6 geb1/io45pdb3v0 a7 vccosc a8 xtal2 a9 gea1/io44ppb3v0 a10 gea0/io44npb3v0 a11 geb2/io42pdb3v0 a12 v ccnvm a13 v cc15a a14 pcap a15 nc a16 gnda a17 av0 a18 ag0 a19 atrtn0 a20 at1 a21 ac1 a22 av2 a23 ag2 a24 at2 a25 at3 a26 ac3 a27 gndaq a28 adcgndref a29 nc a30 gnda a31 ptem a32 gndnvm a33 v pump a34 tck a35 tms a36 trst a37 gdb1/io39psb1v0 a38 gdc1/io38pdb1v0 a39 gnd a40 gcb1/io35pdb1v0 a41 gcb2/io33pdb1v0 a42 gba2/io31pdb1v0 a43 nc a44 gba1/io30rsb0v0 a45 gbb1/io28rsb0v0 a46 gnd a47 v cc a48 gbc1/io26rsb0v0 a49 io21rsb0v0 a50 io19rsb0v0 a51 io09rsb0v0 a52 gac0/io04rsb0v0 a53 v cci b0 a54 gnd a55 gab0/io02rsb0v0 a56 gaa0/io00rsb0v0 b1 v compla b2 v cci b3 b3 gab2/io52ndb3v0 b4 v cci b3 b5 gfa0/io47ndb3v0 b6 geb0/io45ndb3v0 b7 xtal1 b8 gndosc b9 gec2/io43psb3v0 b10 gea2/io42ndb3v0 b11 v cc b12 gndnvm b13 ncap b14 v cc33pmp b15 v cc33n b16 gndaq b17 ac0 b18 at0 b19 ag1 b20 av1 108-pin qfn pin number afs090 function b21 ac2 b22 atrtn1 b23 ag3 b24 av3 b25 v cc33a b26 varef b27 pub b28 v cc33a b29 ptbase b30 v ccnvm b31 v cc b32 tdi b33 tdo b34 v jtag b35 gdc0/io38ndb1v0 b36 v cci b1 b37 gcb0/io35ndb1v0 b38 gcc2/io33ndb1v0 b39 gbb2/io31ndb1v0 b40 v cci b1 b41 gndq b42 gba0/io29rsb0v0 b43 v cci b0 b44 gbb0/io27rsb0v0 b45 gbc0/io25rsb0v0 b46 io20rsb0v0 b47 io10rsb0v0 b48 gac1/io05rsb0v0 b49 gab1/io03rsb0v0 b50 v cc b51 gaa1/io01rsb0v0 b52 v ccpla 108-pin qfn pin number afs090 function
180-pin qfn v2.0 4-3 180-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/so lutions/package/default.aspx . note: the die attach paddle center of th e package is tied to ground (gnd). a1 b1 c1 a16 b15 c14 a48 pin a1 mark optional corner pad (4x) a49 a64 a32 a17 b45 b46 b60 b30 b16 c42 c43 c56 c28 c15 a33 b31 c29 d4 d3 d1 d2
actel fusion family of mixed-sign al fpgas package pin assignments 4-4 v2.0 180-pin qfn pin number afs090 func tion afs250 function a1 gndq gndq a2 v cci b3 v cci b3 a3 gab2/io52ndb3v0 io74ndb3v0 a4 gfa2/io51ndb3v0 io71ndb3v0 a5 gfc2/io50ndb3v0 io69npb3v0 a6 v cci b3 v cci b3 a7 gfa1/io47ppb3v0 gfb1/io67ppb3v0 a8 geb0/io45ndb3v0 nc a9 xtal1 xtal1 a10 gndosc gndosc a11 gec2/io43ppb3v0 gea1/io61ppb3v0 a12 io43npb3v0 gea0/io61npb3v0 a13 nc v cci b3 a14 gndnvm gndnvm a15 pcap pcap a16 v cc33pmp v cc33pmp a17 nc nc a18 av0 av0 a19 ag0 ag0 a20 atrtn0 atrtn0 a21 ag1 ag1 a22 ac1 ac1 a23 av2 av2 a24 at2 at2 a25 at3 at3 a26 ac3 ac3 a27 av4 av4 a28 ac4 ac4 a29 at4 at4 a30 nc ag5 a31 nc av5 a32 adcgndref adcgndref a33 v cc33a v cc33a a34 gnda gnda a35 ptbase ptbase a36 v ccnvm v ccnvm a37 v pump v pump a38 tdi tdi a39 tdo tdo a40 v jtag v jtag a41 gdb1/io39ppb1v0 gda1/io54ppb1v0 a42 gdc1/io38pdb1v 0 gdb1/io53pdb1v0 a43 v cc v cc a44 gcb0/io35npb1v0 gcb0/io48npb1v0 a45 gcc1/io34pdb1v0 gcc1/io47pdb1v0 a46 v cci b1 v cci b1 a47 gbc2/io32ppb1v 0 gbb2/io41ppb1v0 a48 v cci b1 v cci b1 a49 nc nc a50 gba0/io29rsb0v0 gbb1/io37rsb0v0 a51 v cci b0 v cci b0 a52 gbb0/io27rsb0v0 gbc0/io34rsb0v0 a53 gbc1/io26rs b0v0 io33rsb0v0 a54 io24rsb0v0 io29rsb0v0 a55 io21rsb0v0 io26rsb0v0 a56 v cci b0 v cci b0 a57 io15rsb0v0 io21rsb0v0 a58 io10rsb0v0 io13rsb0v0 a59 io07rsb0v0 io10rsb0v0 a60 gac0/io04rsb0v0 io06rsb0v0 a61 gab1/io03rsb0 v0 gac1/io05rsb0v0 a62 v cc v cc a63 gaa1/io01rsb0v0 gab0/io02rsb0v0 a64 nc nc b1 v compla v compla b2 gaa2/io52pdb3v0 gac2/io74pdb3v0 b3 gac2/io51pdb3v0 gfa2/io71pdb3v0 b4 gfb2/io50pdb3v0 gfb2/io70psb3v0 b5 v cc v cc b6 gfc0/io49ndb3v0 gfc0/io68ndb3v0 b7 geb1/io45pdb3v0 nc b8 v ccosc v ccosc 180-pin qfn pin number afs090 func tion afs250 function
180-pin qfn v2.0 4-5 b9 xtal2 xtal2 b10 gea0/io44ndb3v0 gfa0/io66ndb3v0 b11 geb2/io42pdb3v0 io60ndb3v0 b12 v cc v cc b13 v ccnvm v ccnvm b14 v cc15a v cc15a b15 ncap ncap b16 vcc33n vcc33n b17 gndaq gndaq b18 ac0 ac0 b19 at0 at0 b20 at1 at1 b21 av1 av1 b22 ac2 ac2 b23 atrtn1 atrtn1 b24 ag3 ag3 b25 av3 av3 b26 ag4 ag4 b27 atrtn2 atrtn2 b28 nc ac5 b29 v cc33a v cc33a b30 varef varef b31 pub pub b32 ptem ptem b33 gndnvm gndnvm b34 v cc v cc b35 tck tck b36 tms tms b37 trst trst b38 gdb2/io41psb1v0 gda2/io55psb1v0 b39 gdc0/io38ndb1v0 gdb0/io53ndb1v0 b40 v cci b1 v cci b1 b41 gca1/io36pdb1v0 gca1/io49pdb1v0 b42 gcc0/io34ndb1v 0 gcc0/io47ndb1v0 b43 gcb2/io33psb1v 0 gbc2/io42psb1v0 b44 v cc v cc 180-pin qfn pin number afs090 func tion afs250 function b45 gba2/io31pdb1v0 gba2/io40pdb1v0 b46 gndq gndq b47 gba1/io30rsb0v0 gba0/io38rsb0v0 b48 gbb1/io28rsb0v0 gbc1/io35rsb0v0 b49 v cc v cc b50 gbc0/io25rsb0v0 io31rsb0v0 b51 io23rsb0v0 io28rsb0v0 b52 io20rsb0v0 io25rsb0v0 b53 v cc v cc b54 io11rsb0v0 io14rsb0v0 b55 io08rsb0v0 io11rsb0v0 b56 gac1/io05rsb0v0 io08rsb0v0 b57 v cci b0 v cci b0 b58 gab0/io02rsb0v0 gac0/io04rsb0v0 b59 gaa0/io00rsb0v0 gaa1/io01rsb0v0 b60 v ccpla v ccpla c1 nc nc c2 nc v cci b3 c3 gnd gnd c4 nc gfc2/io69ppb3v0 c5 gfc1/io49pdb3v0 gfc1/io68pdb3v0 c6 gfa0/io47npb3v0 gfb0/io67npb3v0 c7 v cci b3 nc c8 gnd gnd c9 gea1/io44pdb3v0 gfa1/io66pdb3v0 c10 gea2/io42ndb3v0 gec2/io60pdb3v0 c11 nc gea2/io58psb3v0 c12 nc nc c13 gnd gnd c14 nc nc c15 nc nc c16 gnda gnda c17 nc nc c18 nc nc c19 nc nc c20 nc nc 180-pin qfn pin number afs090 func tion afs250 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-6 v2.0 c21 ag2 ag2 c22 nc nc c23 nc nc c24 nc nc c25 nc at5 c26 gndaq gndaq c27 nc nc c28 nc nc c29 nc nc c30 nc nc c31 gnd gnd c32 nc nc c33 nc nc c34 nc nc c35 gnd gnd c36 gdb0/io39npb1v0 gda0/io54npb1v0 c37 gda1/io37nsb1v0 gdc0/io52nsb1v0 c38 gca0/io36ndb1v0 gca0/io49ndb1v0 c39 gcb1/io35ppb1v 0 gcb1/io48ppb1v0 c40 gnd gnd c41 gca2/io32npb1v0 io41npb1v0 c42 gbb2/io31ndb1v0 io40ndb1v0 c43 nc nc c44 nc gba1/io39rsb0v0 c45 nc gbb0/io36rsb0v0 c46 gnd gnd c47 nc io30rsb0v0 c48 io22rsb0v0 io27rsb0v0 c49 gnd gnd c50 io13rsb0v0 io16rsb0v0 c51 io09rsb0v0 io12rsb0v0 c52 io06rsb0v0 io09rsb0v0 c53 gnd gnd c54 nc gab1/io03rsb0v0 c55 nc gaa0/io00rsb0v0 c56 nc nc 180-pin qfn pin number afs090 func tion afs250 function d1 nc nc d2 nc nc d3 nc nc d4 nc nc 180-pin qfn pin number afs090 func tion afs250 function
208-pin pqfp v2.0 4-7 208-pin pqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/so lutions/package/default.aspx . 208-pin pqfp 1 208
actel fusion family of mixed-sign al fpgas package pin assignments 4-8 v2.0 208-pin pqfp pin number afs250 function afs600 function 1v ccpla v ccpla 2v compla v compla 3 gndq gaa2/io85pdb4v0 4v cci b3 io85ndb4v0 5 gaa2/io76pdb3v0 gab2/io84pdb4v0 6 io76ndb3v0 io84ndb4v0 7 gab2/io75pdb3v0 gac2/io83pdb4v0 8 io75ndb3v0 io83ndb4v0 9 nc io77pdb4v0 10 nc io77ndb4v0 11 v cc io76pdb4v0 12 gnd io76ndb4v0 13 v cci b3 v cc 14 io72pdb3v0 gnd 15 io72ndb3v0 v cci b4 16 gfa2/io71pdb3v0 gfa2/io75pdb4v0 17 io71ndb3v0 io75ndb4v0 18 gfb2/io70pdb3v0 gfc2/io73pdb4v0 19 io70ndb3v0 io73ndb4v0 20 gfc2/io69pdb3v0 v ccosc 21 io69ndb3v0 xtal1 22 v cc xtal2 23 gnd gndosc 24 v cci b3 gfc1/io72pdb4v0 25 gfc1/io68pdb3v0 gfc0/io72ndb4v0 26 gfc0/io68ndb3v0 gfb1/io71pdb4v0 27 gfb1/io67pdb3v0 gfb0/io71ndb4v0 28 gfb0/io67ndb3v0 gfa1/io70pdb4v0 29 v ccosc gfa0/io70ndb4v0 30 xtal1 io69pdb4v0 31 xtal2 io69ndb4v0 32 gndosc v cc 33 geb1/io62pdb3v0 gnd 34 geb0/io62ndb3v0 v cci b4 35 gea1/io61pdb3v0 gec1/io63pdb4v0 36 gea0/io61ndb3v0 gec0/io63ndb4v0 37 gec2/io60pdb3v0 geb1/io62pdb4v0 38 io60ndb3v0 geb0/io62ndb4v0 39 gnd gea1/io61pdb4v0 40 v cci b3 gea0/io61ndb4v0 41 geb2/io59pdb3v0 gec2/io60pdb4v0 42 io59ndb3v0 io60ndb4v0 43 gea2/io58pdb3v0 v cci b4 44 io58ndb3v0 gndq 45 v cc v cc 45 v cc v cc 46 v ccnvm v ccnvm 47 gndnvm gndnvm 48 gnd gnd 49 v cc15a v cc15a 50 pcap pcap 51 ncap ncap 52 v cc33pmp v cc33pmp 53 vcc33n vcc33n 54 gnda gnda 55 gndaq gndaq 56 nc av0 57 nc ac0 58 nc ag0 59 nc at0 60 nc atrtn0 61 nc at1 62 nc ag1 63 nc ac1 64 nc av1 65 av0 av2 66 ac0 ac2 67 ag0 ag2 68 at0 at2 69 atrtn0 atrtn1 70 at1 at3 71 ag1 ag3 208-pin pqfp pin number afs250 function afs600 function
208-pin pqfp v2.0 4-9 72 ac1 ac3 73 av1 av3 74 av2 av4 75 ac2 ac4 76 ag2 ag4 77 at2 at4 78 atrtn1 atrtn2 79 at3 at5 80 ag3 ag5 81 ac3 ac5 82 av3 av5 83 av4 av6 84 ac4 ac6 85 ag4 ag6 86 at4 at6 87 atrtn2 atrtn3 88 at5 at7 89 ag5 ag7 90 ac5 ac7 91 av5 av7 92 nc av8 93 nc ac8 94 nc ag8 95 nc at8 96 nc atrtn4 97 nc at9 98 nc ag9 99 nc ac9 100 nc av9 101 gndaq gndaq 102 v cc33a v cc33a 103 adcgndref adcgndref 104 varef varef 105 pub pub 106 v cc33a v cc33a 107 gnda gnda 208-pin pqfp pin number afs250 function afs600 function 108 ptem ptem 109 ptbase ptbase 110 gndnvm gndnvm 111 v ccnvm v ccnvm 112 v cc v cc 112 v cc v cc 113 v pump v pump 114 gndq nc 115 v cci b1 tck 116 tck tdi 117 tdi tms 118 tms tdo 119 tdo trst 120 trst v jtag 121 v jtag io57ndb2v0 122 io57ndb1v0 gdc2/io57pdb2v0 123 gdc2/io57pdb1v0 io56ndb2v0 124 io56ndb1v0 gdb2/io56pdb2v0 125 gdb2/io56pdb1v0 io55ndb2v0 126 v cci b1 gda2/io55pdb2v0 127 gnd gda0/io54ndb2v0 128 io55ndb1v0 gda1/io54pdb2v0 129 gda2/io55pdb1v0 v cci b2 130 gda0/io54ndb1v0 gnd 131 gda1/io54pdb1v0 v cc 132 gdb0/io53ndb1v0 gca0/io45ndb2v0 133 gdb1/io53pdb1v0 gca1/io45pdb2v0 134 gdc0/io52ndb1v0 gcb0/io44ndb2v0 135 gdc1/io52pdb1v0 gcb1/io44pdb2v0 136 io51nsb1v0 gcc0/io43ndb2v0 137 v cci b1 gcc1/io43pdb2v0 138 gnd io42ndb2v0 139 v cc io42pdb2v0 140 io50ndb1v0 io41ndb2v0 141 io50pdb1v0 gcc2/io41pdb2v0 142 gca0/io49ndb1v0 v cci b2 208-pin pqfp pin number afs250 function afs600 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-10 v2.0 143 gca1/io49pdb1v0 gnd 144 gcb0/io48ndb1v0 v cc 145 gcb1/io48pdb1v0 io40ndb2v0 146 gcc0/io47ndb1v0 gcb2/io40pdb2v0 147 gcc1/io47pdb1v0 io39ndb2v0 148 io42ndb1v0 gca2/io39pdb2v0 149 gbc2/io42pdb1v0 io31ndb2v0 150 v cci b1 gbb2/io31pdb2v0 151 gnd io30ndb2v0 152 v cc gba2/io30pdb2v0 153 io41ndb1v0 v cci b2 154 gbb2/io41pdb1v0 gndq 155 io40ndb1v0 v complb 156 gba2/io40pdb1v0 v ccplb 157 gba1/io39rsb0v0 v cci b1 158 gba0/io38rsb0v0 gndq 159 gbb1/io37rsb0v0 gbb1/io27ppb1v1 160 gbb0/io36rsb0v0 gba1/io28ppb1v1 161 gbc1/io35rsb0v0 gbb0/io27npb1v1 162 v cci b0 gba0/io28npb1v1 163 gnd v cci b1 164 v cc gnd 165 gbc0/io34rsb0v0 v cc 166 io33rsb0v0 gbc1/io26pdb1v1 167 io32rsb0v0 gbc0/io26ndb1v1 168 io31rsb0v0 io24ppb1v1 169 io30rsb0v0 io23ppb1v1 170 io29rsb0v0 io24npb1v1 171 io28rsb0v0 io23npb1v1 172 io27rsb0v0 io22ppb1v0 173 io26rsb0v0 io21ppb1v0 174 io25rsb0v0 io22npb1v0 175 v cci b0 io21npb1v0 176 gnd io20psb1v0 177 v cc io19psb1v0 178 io24rsb0v0 io14nsb0v1 208-pin pqfp pin number afs250 function afs600 function 179 io23rsb0v0 io12pdb0v1 180 io22rsb0v0 io12ndb0v1 181 io21rsb0v0 v cci b0 182 io20rsb0v0 gnd 183 io19rsb0v0 v cc 184 io18rsb0v0 io10ppb0v1 185 io17rsb0v0 io09ppb0v1 186 io16rsb0v0 io10npb0v1 187 io15rsb0v0 io09npb0v1 188 v cci b0 io08ppb0v1 189 gnd io07ppb0v1 190 v cc io08npb0v1 191 io14rsb0v0 io07npb0v1 192 io13rsb0v0 io06ppb0v0 193 io12rsb0v0 io05ppb0v0 194 io11rsb0v0 io06npb0v0 195 io10rsb0v0 io04ppb0v0 196 io09rsb0v0 io05npb0v0 197 io08rsb0v0 io04npb0v0 198 io07rsb0v0 gac1/io03pdb0v0 199 io06rsb0v0 gac0/io03ndb0v0 200 gac1/io05rsb0v0 v cci b0 201 v cci b0 gnd 202 gnd v cc 203 v cc gab1/io02pdb0v0 204 gac0/io04rsb0v0 gab0/io02ndb0v0 205 gab1/io03rsb0v0 gaa1/io01pdb0v0 206 gab0/io02rsb0v0 gaa0/io01ndb0v0 207 gaa1/io01rsb0v0 gndq 208 gaa0/io00rsb0v0 v cci b0 208-pin pqfp pin number afs250 function afs600 function
256-pin fbga v2.0 4-11 256-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/so lutions/package/default.aspx . 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
actel fusion family of mixed-sign al fpgas package pin assignments 4-12 v2.0 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function a1 gnd gnd gnd gnd a2 v cci b0 v cci b0 v cci b0 v cci b0 a3 gab0/io02rsb0v0 gaa0/io00rsb0v0 gaa0/io01ndb0v0 gaa0/io01ndb0v0 a4 gab1/io03rsb0v0 gaa1/io01rsb0v0 gaa1/io01pdb0v0 gaa1/io01pdb0v0 a5 gnd gnd gnd gnd a6 io07rsb0v0 io11rsb0v0 io10pdb0v1 io07pdb0v1 a7 io10rsb0v0 io14rsb0v0 io12pdb0v1 io13pdb0v2 a8 io11rsb0v0 io15rsb0v0 io12ndb0v1 io13ndb0v2 a9 io16rsb0v0 io24rsb0v0 io22ndb1v0 io24ndb1v0 a10 io17rsb0v0 io25rsb0v0 io22pdb1v0 io24pdb1v0 a11 io18rsb0v0 io26rsb0v 0 io24ndb1v1 io29ndb1v1 a12 gnd gnd gnd gnd a13 gbc0/io25rsb0v0 gba0/io38rsb0v0 gba0/io28ndb1v1 gba0/io42ndb1v2 a14 gba0/io29rsb0v0 io32rsb 0v0 io29ndb1v1 io43ndb1v2 a15 v cci b0 v cci b0 v cci b1 v cci b1 a16 gnd gnd gnd gnd b1 v compla v compla v compla v compla b2 v ccpla v ccpla v ccpla v ccpla b3 gaa0/io00rsb0v0 io07rsb0v0 io00ndb0v0 io00ndb0v0 b4 gaa1/io01rsb0v0 io06rsb0v0 io00pdb0v0 io00pdb0v0 b5 nc gab1/io03rsb0v0 gab1/io 02ppb0v0 gab1/io02ppb0v0 b6 io06rsb0v0 io10rsb0v0 io10ndb0v1 io07ndb0v1 b7 v cci b0 v cci b0 v cci b0 v cci b0 b8 io12rsb0v0 io16rsb0v0 io18ndb1v0 io22ndb1v0 b9 io13rsb0v0 io17rsb0v0 io18pdb1v0 io22pdb1v0 b10 v cci b0 v cci b0 v cci b1 v cci b1 b11 io19rsb0v0 io27rsb0v0 io24pdb1v1 io29pdb1v1 b12 gbb0/io27rsb0v0 gbc0/io34rsb0v 0 gbc0/io26npb1v1 gbc0/io40npb1v2 b13 gbc1/io26rsb0v0 gba1/io39rsb0v 0 gba1/io28pdb1v1 gba1/io42pdb1v2 b14 gba1/io30rsb0v0 io33rsb0v0 io29pdb1v1 io43pdb1v2 b15 nc nc v ccplb v ccplb b16 nc nc v complb v complb c1 v cci b3 v cci b3 v cci b4 v cci b4 c2 gnd gnd gnd gnd c3 v cci b3 v cci b3 v cci b4 v cci b4 c4 nc nc v cci b0 v cci b0 c5 v cci b0 v cci b0 v cci b0 v cci b0 c6 gac1/io05rsb0v0 gac1/ io05rsb0v0 gac1/io03pdb 0v0 gac1/io03pdb0v0
256-pin fbga v2.0 4-13 c7 io09rsb0v0 io12rsb0v0 io06ndb0v0 io09ndb0v1 c8 io14rsb0v0 io22rsb0v0 io16pdb1v0 io23pdb1v0 c9 io15rsb0v0 io23rsb0v0 io16ndb1v0 io23ndb1v0 c10 io22rsb0v0 io30rsb0v 0 io25ndb1v1 io31ndb1v1 c11 io20rsb0v0 io31rsb0v0 io25pdb1v1 io31pdb1v1 c12 v cci b0 v cci b0 v cci b1 v cci b1 c13 gbb1/io28rsb0v0 gbc1/io35rsb0v 0 gbc1/io26ppb1v1 g bc1/io40ppb1v2 c14 v cci b1 v cci b1 v cci b2 v cci b2 c15 gnd gnd gnd gnd c16 v cci b1 v cci b1 v cci b2 v cci b2 d1 gfc2/io50npb3v0 io75ndb 3v0 io84ndb4v0 io124ndb4v0 d2 gfa2/io51ndb3v0 gab2/io75pdb3 v0 gab2/io84pdb4v0 gab2/io124pdb4v0 d3 gac2/io51pdb3v0 io76ndb3v0 io85ndb4v0 io125ndb4v0 d4 gaa2/io52pdb3v0 gaa2/io76pdb3v0 g aa2/io85pdb4v0 gaa2/io125pdb4v0 d5 gab2/io52ndb3v0 gab0/ io02rsb0v0 gab0/io02npb 0v0 gab0/io02npb0v0 d6 gac0/io04rsb0v0 gac0/ io04rsb0v0 gac0/io03ndb0v0 gac0/io03ndb0v0 d7 io08rsb0v0 io13rsb0v0 io06pdb0v0 io09pdb0v1 d8 nc io20rsb0v0 io14ndb0v1 io15ndb0v2 d9 nc io21rsb0v0 io14pdb0v1 io15pdb0v2 d10 io21rsb0v0 io28rsb0v0 io23pdb1v1 io37pdb1v2 d11 io23rsb0v0 gbb0/io36rsb0v0 g bb0/io27ndb1v1 gbb0/io41ndb1v2 d12 nc nc v cci b1 v cci b1 d13 gba2/io31pdb1v0 gba2/io40pdb1v0 gba2/io30pdb2v0 gba2/io44pdb2v0 d14 gbb2/io31ndb1v0 io40ndb 1v0 io30ndb2v0 io44ndb2v0 d15 gbc2/io32pdb1v0 gbb2/io41pdb1 v0 gbb2/io31pdb2v0 gbb2/io45pdb2v0 d16 gca2/io32ndb1v0 io41ndb 1v0 io31ndb2v0 io45ndb2v0 e1 gnd gnd gnd gnd e2 gfb0/io48npb3v0 io73ndb 3v0 io81ndb4v0 io118ndb4v0 e3 gfb2/io50ppb3v0 io73pdb3v0 io81pdb4v0 io118pdb4v0 e4 v cci b3 v cci b3 v cci b4 v cci b4 e5 nc io74npb3v0 io83npb4v0 io123npb4v0 e6 nc io08rsb0v0 io04npb0v0 io05npb0v1 e7 gnd gnd gnd gnd e8 nc io18rsb0v0 io08pdb0v1 io11pdb0v1 e9 nc nc io20ndb1v0 io27ndb1v1 e10 gnd gnd gnd gnd e11 io24rsb0v0 gbb1/io37rsb0v0 g bb1/io27pdb1v1 gbb1/io41pdb1v2 e12 nc io50ppb1v0 io33psb2v0 io48psb2v0 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-14 v2.0 e13 v cci b1 v cci b1 v cci b2 v cci b2 e14 gcc2/io33ndb1v0 io42ndb 1v0 io32ndb2v0 io46ndb2v0 e15 gcb2/io33pdb1v0 gbc2/io42pdb1 v0 gbc2/io32pdb2v0 gbc2/io46pdb2v0 e16 gnd gnd gnd gnd f1 nc nc io79ndb4v0 io111ndb4v0 f2 nc nc io79pdb4v0 io111pdb4v0 f3 gfb1/io48ppb3v0 io72ndb3v0 io76ndb4v0 io112ndb4v0 f4 gfc0/io49ndb3v0 io72pdb3v0 io76pdb4v0 io112pdb4v0 f5 nc nc io82psb4v0 io120psb4v0 f6 gfc1/io49pdb3v0 gac2/ io74ppb3v0 gac2/io83ppb 4v0 gac2/io123ppb4v0 f7 nc io09rsb0v0 io04ppb0v0 io05ppb0v1 f8 nc io19rsb0v0 io08ndb0v1 io11ndb0v1 f9 nc nc io20pdb1v0 io27pdb1v1 f10 nc io29rsb0v0 io23ndb1v1 io37ndb1v2 f11 nc io43ndb1v0 io36ndb2v0 io50ndb2v0 f12 nc io43pdb1v0 io36pdb2v0 io50pdb2v0 f13 nc io44ndb1v0 io39ndb2v0 io59ndb2v0 f14 nc gca2/io44pdb1v0 gca2/io39pdb2v0 gca2/io59pdb2v0 f15 gcc1/io34pdb1v0 gcb2/io45pdb1 v0 gcb2/io40pdb2v0 gcb2/io60pdb2v0 f16 gcc0/io34ndb1v0 io45ndb 1v0 io40ndb2v0 io60ndb2v0 g1 gec0/io46npb3v0 io70npb3v0 io74npb4v0 io109npb4v0 g2 v cci b3 v cci b3 v cci b4 v cci b4 g3 gec1/io46ppb3v0 gfb2/io70ppb3v0 g fb2/io74ppb4v0 gfb2/io109ppb4v0 g4 gfa1/io47pdb3v0 gfa2/io71pdb3v0 gfa2/io75pdb4v0 gfa2/io110pdb4v0 g5 gnd gnd gnd gnd g6 gfa0/io47ndb3v0 io71ndb3v0 io75ndb4v0 io110ndb4v0 g7 gnd gnd gnd gnd g8 v cc v cc v cc v cc g9 gnd gnd gnd gnd g10 v cc v cc v cc v cc g11 gda1/io37ndb1v0 gcc0/io47ndb1v0 g cc0/io43ndb2v0 gcc0/io62ndb2v0 g12 gnd gnd gnd gnd g13 io37pdb1v0 gcc1/io47pdb1v0 gcc1/io43pdb2v0 gcc1/io62pdb2v0 g14 gcb0/io35npb1v0 io46npb 1v0 io41npb2v0 io61npb2v0 g15 v cci b1 v cci b1 v cci b2 v cci b2 g16 gcb1/io35ppb1v0 gcc2/io46ppb1v0 gcc2/io41ppb2v0 gcc2/io61ppb2v0 h1 geb1/io45pdb3v0 gfc2/io69pdb3v0 g fc2/io73pdb4v0 gfc2/io108pdb4v0 h2 geb0/io45ndb3v0 io69ndb3v0 io73ndb4v0 io108ndb4v0 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function
256-pin fbga v2.0 4-15 h3 xtal2 xtal2 xtal2 xtal2 h4 xtal1 xtal1 xtal1 xtal1 h5 gndosc gndosc gndosc gndosc h6 v ccosc v ccosc v ccosc v ccosc h7 v cc v cc v cc v cc h8 gnd gnd gnd gnd h9 v cc v cc v cc v cc h10 gnd gnd gnd gnd h11 gdc0/io38ndb1v0 io51ndb 1v0 io47ndb2v0 io69ndb2v0 h12 gdc1/io38pdb1v0 io51pdb1v0 io47pdb2v0 io69pdb2v0 h13 gdb1/io39pdb1v0 gca1/io49pdb1v0 gca1/io45pdb2v0 gca1/io64pdb2v0 h14 gdb0/io39ndb1v0 gca0/io49ndb1v 0 gca0/io45ndb2v0 gca0/io64ndb2v0 h15 gca0/io36ndb1v0 gcb0/io48ndb1v 0 gcb0/io44ndb2v0 gcb0/io63ndb2v0 h16 gca1/io36pdb1v0 gcb1/io48pdb1 v0 gcb1/io44pdb2v0 gcb1/io63pdb2v0 j1 gea0/io44ndb3v0 gfa0/io66ndb3v 0 gfa0/io70ndb4v0 gfa0/io105ndb4v0 j2 gea1/io44pdb3v0 gfa1/io66pdb3v0 gfa1/io70pdb4v0 gfa1/io105pdb4v0 j3 io43ndb3v0 gfb0/io67ndb3v0 gfb 0/io71ndb4v0 gfb0/io106ndb4v0 j4 gec2/io43pdb3v0 gfb1/io67pdb3v0 g fb1/io71pdb4v0 gfb1/io106pdb4v0 j5 nc gfc0/io68ndb3v0 gfc0/io 72ndb4v0 gfc0/io107ndb4v0 j6 nc gfc1/io68pdb3v0 gfc1/io 72pdb4v0 gfc1/io107pdb4v0 j7 gnd gnd gnd gnd j8 v cc v cc v cc v cc j9 gnd gnd gnd gnd j10 v cc v cc v cc v cc j11 gdc2/io41npb1v0 io56np b1v0 io56npb2v0 io83npb2v0 j12 nc gdb0/io53npb1v0 gdb0/ io53npb2v0 gdb0/io80npb2v0 j13 nc gda1/io54pdb1v0 gda1/io54pdb2v0 gda1/io81pdb2v0 j14 gda0/io40pdb1v0 gdc1/io52ppb1v0 gdc1/io52ppb2v0 gdc1/io79ppb2v0 j15 nc io50npb1v0 io51nsb2v0 io77nsb2v0 j16 gda2/io40ndb1v0 gdc0/io52npb1v0 gdc0/io52npb2v0 gdc0/io79npb2v0 k1 nc io65npb3v0 io67npb4v0 io92npb4v0 k2 v cci b3 v cci b3 v cci b4 v cci b4 k3 nc io65ppb3v0 io67ppb4v0 io92ppb4v0 k4 nc io64pdb3v0 io65pdb4v0 io96pdb4v0 k5 gnd gnd gnd gnd k6 nc io64ndb3v0 io65ndb4v0 io96ndb4v0 k7 v cc v cc v cc v cc k8 gnd gnd gnd gnd 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-16 v2.0 k9 v cc v cc v cc v cc k10 gnd gnd gnd gnd k11 nc gdc2/io57ppb1v0 gdc2 /io57ppb2v0 gdc2/io84ppb2v0 k12 gnd gnd gnd gnd k13 nc gda0/io54ndb1v0 gda0/io 54ndb2v0 gda0/io81ndb2v0 k14 nc gda2/io55ppb1v0 gda2/io55ppb2v0 gda2/io82ppb2v0 k15 v cci b1 v cci b1 v cci b2 v cci b2 k16 nc gdb1/io53ppb1v0 gdb1 /io53ppb2v0 gdb1/io80ppb2v0 l1 nc gec1/io63pdb3v0 gec1/io63pdb4v0 gec1/io90pdb4v0 l2 nc gec0/io63ndb3v0 gec0/ io63ndb4v0 gec0/io90ndb4v0 l3 nc geb1/io62pdb3v0 geb1/io62pdb4v0 geb1/io89pdb4v0 l4 nc geb0/io62ndb3v0 geb0/ io62ndb4v0 geb0/io89ndb4v0 l5 nc io60ndb3v0 io60ndb4v0 io87ndb4v0 l6 nc gec2/io60pdb3v0 gec2/io60pdb4v0 gec2/io87pdb4v0 l7 gnda gnda gnda gnda l8 ac0 ac0 ac2 ac2 l9av2av2av4av4 l10 ac3 ac3 ac5 ac5 l11 ptem ptem ptem ptem l12 tdo tdo tdo tdo l13 v jtag v jtag v jtag v jtag l14 nc io57npb1v0 io57npb2v0 io84npb2v0 l15 gdb2/io41ppb1v0 gdb2/ io56ppb1v0 gdb2/io56ppb2v0 gdb2/io83ppb2v0 l16 nc io55npb1v0 io55npb2v0 io82npb2v0 m1 gnd gnd gnd gnd m2 nc gea1/io61pdb3v0 gea1/io61pdb4v0 gea1/io88pdb4v0 m3 nc gea0/io61ndb3v0 gea0/io61ndb4v0 gea0/io88ndb4v0 m4 v cci b3 v cci b3 v cci b4 v cci b4 m5 nc io58npb3v0 io58npb4v0 io85npb4v0 m6 nc nc av0 av0 m7 nc nc ac1 ac1 m8 ag1 ag1 ag3 ag3 m9 ac2 ac2 ac4 ac4 m10 ac4 ac4 ac6 ac6 m11 nc ag5 ag7 ag7 m12 v pump v pump v pump v pump m13 v cci b1 v cci b1 v cci b2 v cci b2 m14 tms tms tms tms 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function
256-pin fbga v2.0 4-17 m15 trst trst trst trst m16 gnd gnd gnd gnd n1 geb2/io42pdb3v0 geb2/io59pdb3v0 geb2/io59pdb4v0 geb2/io86pdb4v0 n2 gea2/io42ndb3v0 io59ndb 3v0 io59ndb4v0 io86ndb4v0 n3 nc gea2/io58ppb3v0 gea2/ io58ppb4v0 gea2/io85ppb4v0 n4 v cc33pmp v cc33pmp v cc33pmp v cc33pmp n5 v cc15a v cc15a v cc15a v cc15a n6 nc nc ag0 ag0 n7 ac1 ac1 ac3 ac3 n8 ag3 ag3 ag5 ag5 n9av3av3av5av5 n10 ag4 ag4 ag6 ag6 n11 nc nc ac8 ac8 n12 gnda gnda gnda gnda n13 v cc33a v cc33a v cc33a v cc33a n14 v ccnvm v ccnvm v ccnvm v ccnvm n15 tck tck tck tck n16 tdi tdi tdi tdi p1 v ccnvm v ccnvm v ccnvm v ccnvm p2 gndnvm gndnvm gndnvm gndnvm p3 gnda gnda gnda gnda p4 nc nc ac0 ac0 p5 nc nc ag1 ag1 p6 nc nc av1 av1 p7 ag0 ag0 ag2 ag2 p8 ag2 ag2 ag4 ag4 p9 gnda gnda gnda gnda p10 nc ac5 ac7 ac7 p11 nc nc av8 av8 p12 nc nc ag8 ag8 p13 nc nc av9 av9 p14 adcgndref adcgndref adcgndref adcgndref p15 ptbase ptbase ptbase ptbase p16 gndnvm gndnvm gndnvm gndnvm r1 v cci b3 v cci b3 v cci b4 v cci b4 r2 pcap pcap pcap pcap r3 nc nc at1 at1 r4 nc nc at0 at0 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-18 v2.0 r5av0av0av2av2 r6 at0 at0 at2 at2 r7av1av1av3av3 r8 at3 at3 at5 at5 r9av4av4av6av6 r10 nc at5 at7 at7 r11 nc av5 av7 av7 r12 nc nc at9 at9 r13 nc nc ag9 ag9 r14 nc nc ac9 ac9 r15 pub pub pub pub r16 v cci b1 v cci b1 v cci b2 v cci b2 t1 gnd gnd gnd gnd t2 ncap ncap ncap ncap t3 vcc33n vcc33n vcc33n vcc33n t4 nc nc atrtn0 atrtn0 t5 at1 at1 at3 at3 t6 atrtn0 atrtn0 atrtn1 atrtn1 t7 at2 at2 at4 at4 t8 atrtn1 atrtn1 atrtn2 atrtn2 t9 at4 at4 at6 at6 t10 atrtn2 atrtn2 atrtn3 atrtn3 t11 nc nc at8 at8 t12 nc nc atrtn4 atrtn4 t13 gnda gnda gnda gnda t14 v cc33a v cc33a v cc33a v cc33a t15 varef varef varef varef t16 gnd gnd gnd gnd 256-pin fbga pin number afs090 function afs250 func tion afs600 function afs1500 function
484-pin fbga v2.0 4-19 484-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/so lutions/package/default.aspx . a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
actel fusion family of mixed-sign al fpgas package pin assignments 4-20 v2.0 484-pin fbga pin number afs600 functi on afs1500 function a1 gnd gnd a2 v cc nc a3 gaa1/io01pdb0v0 gaa1/io01pdb0v0 a4 gab0/io02ndb0v0 gab0/io02ndb0v0 a5 gab1/io02pdb0v0 gab1/io02pdb0v0 a6 io07ndb0v1 io07ndb0v1 a7 io07pdb0v1 io07pdb0v1 a8 io10pdb0v1 io09pdb0v1 a9 io14ndb0v1 io13ndb0v2 a10 io14pdb0v1 io13pdb0v2 a11 io17pdb1v0 io24pdb1v0 a12 io18pdb1v0 io26pdb1v0 a13 io19ndb1v0 io27ndb1v1 a14 io19pdb1v0 io27pdb1v1 a15 io24ndb1v1 io35ndb1v2 a16 io24pdb1v1 io35pdb1v2 a17 gbc0/io26ndb1v1 gbc0/io40ndb1v2 a18 gba0/io28ndb1v1 gba0/io42ndb1v2 a19 io29ndb1v1 io43ndb1v2 a20 io29pdb1v1 io43pdb1v2 a21 v cc nc a22 gnd gnd aa1 v cc nc aa2 gnd gnd aa3 v cci b4 v cci b4 aa4 v cci b4 v cci b4 aa5 pcap pcap aa6 ag0 ag0 aa7 gnda gnda aa8 ag1 ag1 aa9 ag2 ag2 aa10 gnda gnda aa11 ag3 ag3 aa12 ag6 ag6 aa13 gnda gnda aa14 ag7 ag7 aa15 ag8 ag8 aa16 gnda gnda aa17 ag9 ag9 aa18 varef varef aa19 v cci b2 v cci b2 aa20 ptem ptem aa21 gnd gnd aa22 v cc nc ab1 gnd gnd ab2 v cc nc ab3 nc io94nsb4v0 ab4 gnd gnd ab5 vcc33n vcc33n ab6 at0 at0 ab7 atrtn0 atrtn0 ab8 at1 at1 ab9 at2 at2 ab10 atrtn1 atrtn1 ab11 at3 at3 ab12 at6 at6 ab13 atrtn3 atrtn3 ab14 at7 at7 ab15 at8 at8 ab16 atrtn4 atrtn4 ab17 at9 at9 ab18 v cc33a v cc33a ab19 gnd gnd ab20 nc io76npb2v0 ab21 v cc nc ab22 gnd gnd b1 v cc nc b2 gnd gnd b3 gaa0/io01ndb0v0 gaa0/io01ndb0v0 b4 gnd gnd 484-pin fbga pin number afs600 function afs1500 function
484-pin fbga v2.0 4-21 b5 io05ndb0v0 io04ndb0v0 b6 io05pdb0v0 io04pdb0v0 b7 gnd gnd b8 io10ndb0v1 io09ndb0v1 b9 io13pdb0v1 io11pdb0v1 b10 gnd gnd b11 io17ndb1v0 io24ndb1v0 b12 io18ndb1v0 io26ndb1v0 b13 gnd gnd b14 io21ndb1v0 io31ndb1v1 b15 io21pdb1v0 io31pdb1v1 b16 gnd gnd b17 gbc1/io26pdb1v1 gbc1/io40pdb1v2 b18 gba1/io28pdb1v1 gba1/io42pdb1v2 b19 gnd gnd b20 v ccplb v ccplb b21 gnd gnd b22 v cc nc c1 io82pdb4v0 io121pdb4v0 c2 nc io122psb4v0 c3 io00ndb0v0 io00ndb0v0 c4 io00pdb0v0 io00pdb0v0 c5 v cci b0 v cci b0 c6 io06ndb0v0 io05ndb0v1 c7 io06pdb0v0 io05pdb0v1 c8 v cci b0 v cci b0 c9 io13ndb0v1 io11ndb0v1 c10 io11pdb0v1 io14pdb0v2 c11 v cci b0 v cci b0 c12 v cci b1 v cci b1 c13 io20ndb1v0 io29ndb1v1 c14 io20pdb1v0 io29pdb1v1 c15 v cci b1 v cci b1 c16 io25ndb1v1 io37ndb1v2 c17 gbb0/io27ndb1v1 gbb0/io41ndb1v2 484-pin fbga pin number afs600 functi on afs1500 function c18 v cci b1 v cci b1 c19 v complb v complb c20 gba2/io30pdb2v0 gba2/io44pdb2v0 c21 nc io48psb2v0 c22 gbb2/io31pdb2v 0 gbb2/io45pdb2v0 d1 io82ndb4v0 io121ndb4v0 d2 gnd gnd d3 io83ndb4v0 io123ndb4v0 d4 gac2/io83pdb4v0 gac2/io123pdb4v0 d5 gaa2/io85pdb4v0 gaa2/io125pdb4v0 d6 gac0/io03ndb0v0 gac0/io03ndb0v0 d7 gac1/io03pdb0v0 gac1/io03pdb0v0 d8 io09ndb0v1 io10ndb0v1 d9 io09pdb0v1 io10pdb0v1 d10 io11ndb0v1 io14ndb0v2 d11 io16ndb1v0 io23ndb1v0 d12 io16pdb1v0 io23pdb1v0 d13 nc io32npb1v1 d14 io23ndb1v1 io34ndb1v1 d15 io23pdb1v1 io34pdb1v1 d16 io25pdb1v1 io37pdb1v2 d17 gbb1/io27pdb1v 1 gbb1/io41pdb1v2 d18 v cci b2 v cci b2 d19 nc io47ppb2v0 d20 io30ndb2v0 io44ndb2v0 d21 gnd gnd d22 io31ndb2v0 io45ndb2v0 e1 io81ndb4v0 io120ndb4v0 e2 io81pdb4v0 io120pdb4v0 e3 v cci b4 v cci b4 e4 gab2/io84pdb4v0 gab2/io124pdb4v0 e5 io85ndb4v0 io125ndb4v0 e6 gnd gnd e7 v cci b0 v cci b0 e8 nc io08ndb0v1 484-pin fbga pin number afs600 function afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-22 v2.0 e9 nc io08pdb0v1 e10 gnd gnd e11 io15ndb1v0 io22ndb1v0 e12 io15pdb1v0 io22pdb1v0 e13 gnd gnd e14 nc io32ppb1v1 e15 nc io36npb1v2 e16 v cci b1 v cci b1 e17 gnd gnd e18 nc io47npb2v0 e19 io33pdb2v0 io49pdb2v0 e20 v cci b2 v cci b2 e21 io32ndb2v0 io46ndb2v0 e22 gbc2/io32pdb2v0 gbc2/io46pdb2v0 f1 io80ndb4v0 io118ndb4v0 f2 io80pdb4v0 io118pdb4v0 f3 nc io119nsb4v0 f4 io84ndb4v0 io124ndb4v0 f5 gnd gnd f6 v compla v compla f7 v ccpla v ccpla f8 v cci b0 v cci b0 f9 io08ndb0v1 io12ndb0v1 f10 io08pdb0v1 io12pdb0v1 f11 v cci b0 v cci b0 f12 v cci b1 v cci b1 f13 io22ndb1v0 io30ndb1v1 f14 io22pdb1v0 io30pdb1v1 f15 v cci b1 v cci b1 f16 nc io36ppb1v2 f17 nc io38npb1v2 f18 gnd gnd f19 io33ndb2v0 io49ndb2v0 f20 io34pdb2v0 io50pdb2v0 f21 io34ndb2v0 io50ndb2v0 484-pin fbga pin number afs600 functi on afs1500 function f22 io35pdb2v0 io51pdb2v0 g1 io77pdb4v0 io115pdb4v0 g2 gnd gnd g3 io78ndb4v0 io116ndb4v0 g4 io78pdb4v0 io116pdb4v0 g5 v cci b4 v cci b4 g6 nc io117pdb4v0 g7 v cci b4 v cci b4 g8 gnd gnd g9 io04ndb0v0 io06ndb0v1 g10 io04pdb0v0 io06pdb0v1 g11 io12ndb0v1 io16ndb0v2 g12 io12pdb0v1 io16pdb0v2 g13 nc io28ndb1v1 g14 nc io28pdb1v1 g15 gnd gnd g16 nc io38ppb1v2 g17 nc io53pdb2v0 g18 v cci b2 v cci b2 g19 io36pdb2v0 io52pdb2v0 g20 io36ndb2v0 io52ndb2v0 g21 gnd gnd g22 io35ndb2v0 io51ndb2v0 h1 io77ndb4v0 io115ndb4v0 h2 io76pdb4v0 io113pdb4v0 h3 v cci b4 v cci b4 h4 io79ndb4v0 io114ndb4v0 h5 io79pdb4v0 io114pdb4v0 h6 nc io117ndb4v0 h7 gnd gnd h8 v cc v cc h9 v cci b0 v cci b0 h10 gnd gnd h11 v cci b0 v cci b0 h12 v cci b1 v cci b1 484-pin fbga pin number afs600 function afs1500 function
484-pin fbga v2.0 4-23 h13 gnd gnd h14 v cci b1 v cci b1 h15 gnd gnd h16 gnd gnd h17 nc io53ndb2v0 h18 io38pdb2v0 io57pdb2v0 h19 gca2/io39pdb2v0 gca2/io59pdb2v0 h20 v cci b2 v cci b2 h21 io37ndb2v0 io54ndb2v0 h22 io37pdb2v0 io54pdb2v0 j1 nc io112ppb4v0 j2 io76ndb4v0 io113ndb4v0 j3 gfb2/io74pdb4v0 gfb2/io109pdb4v0 j4 gfa2/io75pdb4v0 gfa2/io110pdb4v0 j5 nc io112npb4v0 j6 nc io104pdb4v0 j7 nc io111pdb4v0 j8 v cci b4 v cci b4 j9 gnd gnd j10 v cc v cc j11 gnd gnd j12 v cc v cc j13 gnd gnd j14 v cc v cc j15 v cci b2 v cci b2 j16 gcb2/io40pdb2v0 gcb2/io60pdb2v0 j17 nc io58ndb2v0 j18 io38ndb2v0 io57ndb2v0 j19 io39ndb2v0 io59ndb2v0 j20 gcc2/io41pdb2v0 gcc2/io61pdb2v0 j21 nc io55psb2v0 j22 io42pdb2v0 io56pdb2v0 k1 gfc2/io73pdb4v0 gfc2/io108pdb4v0 k2 gnd gnd k3 io74ndb4v0 io109ndb4v0 484-pin fbga pin number afs600 functi on afs1500 function k4 io75ndb4v0 io110ndb4v0 k5 gnd gnd k6 nc io104ndb4v0 k7 nc io111ndb4v0 k8 gnd gnd k9 v cc v cc k10 gnd gnd k11 v cc v cc k12 gnd gnd k13 v cc v cc k14 gnd gnd k15 gnd gnd k16 io40ndb2v0 io60ndb2v0 k17 nc io58pdb2v0 k18 gnd gnd k19 nc io68npb2v0 k20 io41ndb2v0 io61ndb2v0 k21 gnd gnd k22 io42ndb2v0 io56ndb2v0 l1 io73ndb4v0 io108ndb4v0 l2 v ccosc v ccosc l3 v cci b4 v cci b4 l4 xtal2 xtal2 l5 gfc1/io72pdb4v0 gfc1/io107pdb4v0 l6 v cci b4 v cci b4 l7 gfb1/io71pdb4v0 gfb1/io106pdb4v0 l8 v cci b4 v cci b4 l9 gnd gnd l10 v cc v cc l11 gnd gnd l12 v cc v cc l13 gnd gnd l14 v cc v cc l15 v cci b2 v cci b2 l16 io48pdb2v0 io70pdb2v0 484-pin fbga pin number afs600 function afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-24 v2.0 l17 v cci b2 v cci b2 l18 io46pdb2v0 io69pdb2v0 l19 gca1/io45pdb2v0 gca1/io64pdb2v0 l20 v cci b2 v cci b2 l21 gcc0/io43ndb2v0 gcc0/io62ndb2v0 l22 gcc1/io43pdb2v0 gcc1/io62pdb2v0 m1 nc io103pdb4v0 m2 xtal1 xtal1 m3 v cci b4 v cci b4 m4 gndosc gndosc m5 gfc0/io72ndb4v0 gfc0/io107ndb4v0 m6 v cci b4 v cci b4 m7 gfb0/io71ndb4v0 gfb0/io106ndb4v0 m8 v cci b4 v cci b4 m9 v cc v cc m10 gnd gnd m11 v cc v cc m12 gnd gnd m13 v cc v cc m14 gnd gnd m15 v cci b2 v cci b2 m16 io48ndb2v0 io70ndb2v0 m17 v cci b2 v cci b2 m18 io46ndb2v0 io69ndb2v0 m19 gca0/io45ndb2v0 gca0/io64ndb2v0 m20 v cci b2 v cci b2 m21 gcb0/io44ndb2v0 gcb0/io63ndb2v0 m22 gcb1/io44pdb2v0 gcb1/io63pdb2v0 n1 nc io103ndb4v0 n2 gnd gnd n3 io68pdb4v0 io101pdb4v0 n4 nc io100npb4v0 n5 gnd gnd n6 nc io99pdb4v0 n7 nc io97pdb4v0 484-pin fbga pin number afs600 functi on afs1500 function n8 gnd gnd n9 gnd gnd n10 v cc v cc n11 gnd gnd n12 v cc v cc n13 gnd gnd n14 v cc v cc n15 gnd gnd n16 gdb2/io56pdb2v0 gdb2/io83pdb2v0 n17 nc io78pdb2v0 n18 gnd gnd n19 io47ndb2v0 io72ndb2v0 n20 io47pdb2v0 io72pdb2v0 n21 gnd gnd n22 io49pdb2v0 io71pdb2v0 p1 gfa1/io70pdb4v0 gfa1/io105pdb4v0 p2 gfa0/io70ndb4v0 gfa0/io105ndb4v0 p3 io68ndb4v0 io101ndb4v0 p4 io65pdb4v0 io96pdb4v0 p5 io65ndb4v0 io96ndb4v0 p6 nc io99ndb4v0 p7 nc io97ndb4v0 p8 v cci b4 v cci b4 p9 v cc v cc p10 gnd gnd p11 v cc v cc p12 gnd gnd p13 v cc v cc p14 gnd gnd p15 v cci b2 v cci b2 p16 io56ndb2v0 io83ndb2v0 p17 nc io78ndb2v0 p18 gda1/io54pdb2v0 gda1/io81pdb2v0 p19 gdb1/io53pdb2v0 gdb1/io80pdb2v0 p20 io51ndb2v0 io73ndb2v0 484-pin fbga pin number afs600 function afs1500 function
484-pin fbga v2.0 4-25 p21 io51pdb2v0 io73pdb2v0 p22 io49ndb2v0 io71ndb2v0 r1 io69pdb4v0 io102pdb4v0 r2 io69ndb4v0 io102ndb4v0 r3 v cci b4 v cci b4 r4 io64pdb4v0 io91pdb4v0 r5 io64ndb4v0 io91ndb4v0 r6 nc io92pdb4v0 r7 gnd gnd r8 gnd gnd r9 v cc33a v cc33a r10 gnda gnda r11 v cc33a v cc33a r12 gnda gnda r13 v cc33a v cc33a r14 gnda gnda r15 v cc v cc r16 gnd gnd r17 nc io74ndb2v0 r18 gda0/io54ndb2v0 gda0/io81ndb2v0 r19 gdb0/io53ndb2v0 gdb0/io80ndb2v0 r20 v cci b2 v cci b2 r21 io50ndb2v0 io75ndb2v0 r22 io50pdb2v0 io75pdb2v0 t1 nc io100ppb4v0 t2 gnd gnd t3 io66pdb4v0 io95pdb4v0 t4 io66ndb4v0 io95ndb4v0 t5 v cci b4 v cci b4 t6 nc io92ndb4v0 t7 gndnvm gndnvm t8 gnda gnda t9 nc nc t10 av4 av4 t11 nc nc 484-pin fbga pin number afs600 functi on afs1500 function t12 av5 av5 t13 ac5 ac5 t14 nc nc t15 gnda gnda t16 nc io77ppb2v0 t17 nc io74pdb2v0 t18 v cci b2 v cci b2 t19 io55ndb2v0 io82ndb2v0 t20 gda2/io55pdb2v0 gda2/io82pdb2v0 t21 gnd gnd t22 gdc1/io52pdb2v0 gdc1/io79pdb2v0 u1 io67pdb4v0 io98pdb4v0 u2 io67ndb4v0 io98ndb4v0 u3 gec1/io63pdb4v0 gec1/io90pdb4v0 u4 gec0/io63ndb4v0 gec0/io90ndb4v0 u5 gnd gnd u6 v ccnvm v ccnvm u7 v cci b4 v cci b4 u8 v cc15a v cc15a u9 gnda gnda u10 ac4 ac4 u11 v cc33a v cc33a u12 gnda gnda u13 ag5 ag5 u14 gnda gnda u15 pub pub u16 v cci b2 v cci b2 u17 tdi tdi u18 gnd gnd u19 io57ndb2v0 io84ndb2v0 u20 gdc2/io57pdb2v0 gdc2/io84pdb2v0 u21 nc io77npb2v0 u22 gdc0/io52ndb2v0 gdc0/io79ndb2v0 v1 geb1/io62pdb4v0 geb1/io89pdb4v0 v2 geb0/io62ndb4v0 geb0/io89ndb4v0 484-pin fbga pin number afs600 function afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-26 v2.0 v3 v cci b4 v cci b4 v4 gea1/io61pdb4v0 gea1/io88pdb4v0 v5 gea0/io61ndb4v0 gea0/io88ndb4v0 v6 gnd gnd v7 v cc33pmp v cc33pmp v8 nc nc v9 v cc33a v cc33a v10 ag4 ag4 v11 at4 at4 v12 atrtn2 atrtn2 v13 at5 at5 v14 v cc33a v cc33a v15 nc nc v16 v cc33a v cc33a v17 gnd gnd v18 tms tms v19 v jtag v jtag v20 v cci b2 v cci b2 v21 trst trst v22 tdo tdo w1 nc io93pdb4v0 w2 gnd gnd w3 nc io93ndb4v0 w4 geb2/io59pdb4v0 geb2/io86pdb4v0 w5 io59ndb4v0 io86ndb4v0 w6 av0 av0 w7 gnda gnda w8 av1 av1 w9 av2 av2 w10 gnda gnda w11 av3 av3 w12 av6 av6 w13 gnda gnda w14 av7 av7 w15 av8 av8 484-pin fbga pin number afs600 functi on afs1500 function w16 gnda gnda w17 av9 av9 w18 v cci b2 v cci b2 w19 nc io68ppb2v0 w20 tck tck w21 gnd gnd w22 nc io76ppb2v0 y1 gec2/io60pdb4v0 gec2/io87pdb4v0 y2 io60ndb4v0 io87ndb4v0 y3 gea2/io58pdb4v0 gea2/io85pdb4v0 y4 io58ndb4v0 io85ndb4v0 y5 ncap ncap y6 ac0 ac0 y7 v cc33a v cc33a y8 ac1 ac1 y9 ac2 ac2 y10 v cc33a v cc33a y11 ac3 ac3 y12 ac6 ac6 y13 v cc33a v cc33a y14 ac7 ac7 y15 ac8 ac8 y16 v cc33a v cc33a y17 ac9 ac9 y18 adcgndref adcgndref y19 ptbase ptbase y20 gndnvm gndnvm y21 v ccnvm v ccnvm y22 v pump v pump 484-pin fbga pin number afs600 function afs1500 function
676-pin fbga v2.0 4-27 676-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/so lutions/package/default.aspx . a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
actel fusion family of mixed-sign al fpgas package pin assignments 4-28 v2.0 676-pin fbga pin number afs1500 function a1 nc a2 gnd a3 nc a4 nc a5 gnd a6 nc a7 nc a8 gnd a9 io17ndb0v2 a10 io17pdb0v2 a11 gnd a12 io18ndb0v2 a13 io18pdb0v2 a14 io20ndb0v2 a15 io20pdb0v2 a16 gnd a17 io21pdb0v2 a18 io21ndb0v2 a19 gnd a20 io39ndb1v2 a21 io39pdb1v2 a22 gnd a23 nc a24 nc a25 gnd a26 nc aa1 nc aa2 v cci b4 aa3 io93pdb4v0 aa4 gnd aa5 io93ndb4v0 aa6 geb2/io86pdb4v0 aa7 io86ndb4v0 aa8 av0 aa9 gnda aa10 av1 aa11 av2 aa12 gnda aa13 av3 aa14 av6 aa15 gnda aa16 av7 aa17 av8 aa18 gnda aa19 av9 aa20 v cci b2 aa21 io68ppb2v0 aa22 tck aa23 gnd aa24 io76ppb2v0 aa25 v cci b2 aa26 nc ab1 gnd ab2 nc ab3 gec2/io87pdb4v0 ab4 io87ndb4v0 ab5 gea2/io85pdb4v0 ab6 io85ndb4v0 ab7 ncap ab8 ac0 ab9 v cc33a ab10 ac1 ab11 ac2 ab12 v cc33a ab13 ac3 ab14 ac6 ab15 v cc33a ab16 ac7 ab17 ac8 ab18 v cc33a ab19 ac9 ab20 adcgndref 676-pin fbga pin number afs1500 function ab21 ptbase ab22 gndnvm ab23 v ccnvm ab24 v pump ab25 nc ab26 gnd ac1 nc ac2 nc ac3 nc ac4 gnd ac5 v cci b4 ac6 v cci b4 ac7 pcap ac8 ag0 ac9 gnda ac10 ag1 ac11 ag2 ac12 gnda ac13 ag3 ac14 ag6 ac15 gnda ac16 ag7 ac17 ag8 ac18 gnda ac19 ag9 ac20 varef ac21 v cci b2 ac22 ptem ac23 gnd ac24 nc ac25 nc ac26 nc ad1 nc ad2 nc ad3 gnd ad4 nc 676-pin fbga pin number afs1500 function
676-pin fbga v2.0 4-29 ad5 io94npb4v0 ad6 gnd ad7 vcc33n ad8 at0 ad9 atrtn0 ad10 at1 ad11 at2 ad12 atrtn1 ad13 at3 ad14 at6 ad15 atrtn3 ad16 at7 ad17 at8 ad18 atrtn4 ad19 at9 ad20 v cc33a ad21 gnd ad22 io76npb2v0 ad23 nc ad24 gnd ad25 nc ad26 nc ae1 gnd ae2 gnd ae3 nc ae4 nc ae5 nc ae6 nc ae7 nc ae8 nc ae9 gnda ae10 nc ae11 nc ae12 gnda ae13 nc ae14 nc 676-pin fbga pin number afs1500 function ae15 gnda ae16 nc ae17 nc ae18 gnda ae19 nc ae20 nc ae21 nc ae22 nc ae23 nc ae24 nc ae25 gnd ae26 gnd af1 nc af2 gnd af3 nc af4 nc af5 nc af6 nc af7 nc af8 nc af9 v cc33a af10 nc af11 nc af12 v cc33a af13 nc af14 nc af15 v cc33a af16 nc af17 nc af18 v cc33a af19 nc af20 nc af21 nc af22 nc af23 nc af24 nc 676-pin fbga pin number afs1500 function af25 gnd af26 nc b1 gnd b2 gnd b3 nc b4 nc b5 nc b6 v cci b0 b7 nc b8 nc b9 v cci b0 b10 io15ndb0v2 b11 io15pdb0v2 b12 v cci b0 b13 io19ndb0v2 b14 io19pdb0v2 b15 v cci b1 b16 io25ndb1v0 b17 io25pdb1v0 b18 v cci b1 b19 io33ndb1v1 b20 io33pdb1v1 b21 v cci b1 b22 nc b23 nc b24 nc b25 gnd b26 gnd c1 nc c2 nc c3 gnd c4 nc c5 gaa1/io01pdb0v0 c6 gab0/io02ndb0v0 c7 gab1/io02pdb0v0 c8 io07ndb0v1 676-pin fbga pin number afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-30 v2.0 c9 io07pdb0v1 c10 io09pdb0v1 c11 io13ndb0v2 c12 io13pdb0v2 c13 io24pdb1v0 c14 io26pdb1v0 c15 io27ndb1v1 c16 io27pdb1v1 c17 io35ndb1v2 c18 io35pdb1v2 c19 gbc0/io40ndb1v2 c20 gba0/io42ndb1v2 c21 io43ndb1v2 c22 io43pdb1v2 c23 nc c24 gnd c25 nc c26 nc d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io01ndb0v0 d6 gnd d7 io04ndb0v0 d8 io04pdb0v0 d9 gnd d10 io09ndb0v1 d11 io11pdb0v1 d12 gnd d13 io24ndb1v0 d14 io26ndb1v0 d15 gnd d16 io31ndb1v1 d17 io31pdb1v1 d18 gnd 676-pin fbga pin number afs1500 function d19 gbc1/io40pdb1v2 d20 gba1/io42pdb1v2 d21 gnd d22 v ccplb d23 gnd d24 nc d25 nc d26 nc e1 gnd e2 io122npb4v0 e3 io121pdb4v0 e4 io122ppb4v0 e5 io00ndb0v0 e6 io00pdb0v0 e7 v cci b0 e8 io05ndb0v1 e9 io05pdb0v1 e10 v cci b0 e11 io11ndb0v1 e12 io14pdb0v2 e13 v cci b0 e14 v cci b1 e15 io29ndb1v1 e16 io29pdb1v1 e17 v cci b1 e18 io37ndb1v2 e19 gbb0/io41ndb1v2 e20 v cci b1 e21 v complb e22 gba2/io44pdb2v0 e23 io48ppb2v0 e24 gbb2/io45pdb2v0 e25 nc e26 gnd f1 nc f2 v cci b4 676-pin fbga pin number afs1500 function f3 io121ndb4v0 f4 gnd f5 io123ndb4v0 f6 gac2/io123pdb4v0 f7 gaa2/io125pdb4v0 f8 gac0/io03ndb0v0 f9 gac1/io03pdb0v0 f10 io10ndb0v1 f11 io10pdb0v1 f12 io14ndb0v2 f13 io23ndb1v0 f14 io23pdb1v0 f15 io32npb1v1 f16 io34ndb1v1 f17 io34pdb1v1 f18 io37pdb1v2 f19 gbb1/io41pdb1v2 f20 v cci b2 f21 io47ppb2v0 f22 io44ndb2v0 f23 gnd f24 io45ndb2v0 f25 v cci b2 f26 nc g1 nc g2 io119ppb4v0 g3 io120ndb4v0 g4 io120pdb4v0 g5 v cci b4 g6 gab2/io124pdb4v0 g7 io125ndb4v0 g8 gnd g9 v cci b0 g10 io08ndb0v1 g11 io08pdb0v1 g12 gnd 676-pin fbga pin number afs1500 function
676-pin fbga v2.0 4-31 g13 io22ndb1v0 g14 io22pdb1v0 g15 gnd g16 io32ppb1v1 g17 io36npb1v2 g18 v cci b1 g19 gnd g20 io47npb2v0 g21 io49pdb2v0 g22 v cci b2 g23 io46ndb2v0 g24 gbc2/io46pdb2v0 g25 io48npb2v0 g26 nc h1 gnd h2 nc h3 io118ndb4v0 h4 io118pdb4v0 h5 io119npb4v0 h6 io124ndb4v0 h7 gnd h8 v compla h9 v ccpla h10 v cci b0 h11 io12ndb0v1 h12 io12pdb0v1 h13 v cci b0 h14 v cci b1 h15 io30ndb1v1 h16 io30pdb1v1 h17 v cci b1 h18 io36ppb1v2 h19 io38npb1v2 h20 gnd h21 io49ndb2v0 h22 io50pdb2v0 676-pin fbga pin number afs1500 function h23 io50ndb2v0 h24 io51pdb2v0 h25 nc h26 gnd j1 nc j2 v cci b4 j3 io115pdb4v0 j4 gnd j5 io116ndb4v0 j6 io116pdb4v0 j7 v cci b4 j8 io117pdb4v0 j9 v cci b4 j10 gnd j11 io06ndb0v1 j12 io06pdb0v1 j13 io16ndb0v2 j14 io16pdb0v2 j15 io28ndb1v1 j16 io28pdb1v1 j17 gnd j18 io38ppb1v2 j19 io53pdb2v0 j20 v cci b2 j21 io52pdb2v0 j22 io52ndb2v0 j23 gnd j24 io51ndb2v0 j25 v cci b2 j26 nc k1 nc k2 nc k3 io115ndb4v0 k4 io113pdb4v0 k5 v cci b4 k6 io114ndb4v0 676-pin fbga pin number afs1500 function k7 io114pdb4v0 k8 io117ndb4v0 k9 gnd k10 v cc k11 v cci b0 k12 gnd k13 v cci b0 k14 v cci b1 k15 gnd k16 v cci b1 k17 gnd k18 gnd k19 io53ndb2v0 k20 io57pdb2v0 k21 gca2/io59pdb2v0 k22 v cci b2 k23 io54ndb2v0 k24 io54pdb2v0 k25 nc k26 nc l1 gnd l2 nc l3 io112ppb4v0 l4 io113ndb4v0 l5 gfb2/io109pdb4v0 l6 gfa2/io110pdb4v0 l7 io112npb4v0 l8 io104pdb4v0 l9 io111pdb4v0 l10 v cci b4 l11 gnd l12 v cc l13 gnd l14 v cc l15 gnd l16 v cc 676-pin fbga pin number afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-32 v2.0 l17 v cci b2 l18 gcb2/io60pdb2v0 l19 io58ndb2v0 l20 io57ndb2v0 l21 io59ndb2v0 l22 gcc2/io61pdb2v0 l23 io55ppb2v0 l24 io56pdb2v0 l25 io55npb2v0 l26 gnd m1 nc m2 v cci b4 m3 gfc2/io108pdb4v0 m4 gnd m5 io109ndb4v0 m6 io110ndb4v0 m7 gnd m8 io104ndb4v0 m9 io111ndb4v0 m10 gnd m11 v cc m12 gnd m13 v cc m14 gnd m15 v cc m16 gnd m17 gnd m18 io60ndb2v0 m19 io58pdb2v0 m20 gnd m21 io68npb2v0 m22 io61ndb2v0 m23 gnd m24 io56ndb2v0 m25 v cci b2 m26 io65pdb2v0 676-pin fbga pin number afs1500 function n1 nc n2 nc n3 io108ndb4v0 n4 v ccosc n5 v cci b4 n6 xtal2 n7 gfc1/io107pdb4v0 n8 v cci b4 n9 gfb1/io106pdb4v0 n10 v cci b4 n11 gnd n12 v cc n13 gnd n14 v cc n15 gnd n16 v cc n17 v cci b2 n18 io70pdb2v0 n19 v cci b2 n20 io69pdb2v0 n21 gca1/io64pdb2v0 n22 v cci b2 n23 gcc0/io62ndb2v0 n24 gcc1/io62pdb2v0 n25 io66pdb2v0 n26 io65ndb2v0 p1 nc p2 nc p3 io103pdb4v0 p4 xtal1 p5 v cci b4 p6 gndosc p7 gfc0/io107ndb4v0 p8 v cci b4 p9 gfb0/io106ndb4v0 p10 v cci b4 676-pin fbga pin number afs1500 function p11 v cc p12 gnd p13 v cc p14 gnd p15 v cc p16 gnd p17 v cci b2 p18 io70ndb2v0 p19 v cci b2 p20 io69ndb2v0 p21 gca0/io64ndb2v0 p22 v cci b2 p23 gcb0/io63ndb2v0 p24 gcb1/io63pdb2v0 p25 io66ndb2v0 p26 io67pdb2v0 r1 nc r2 v cci b4 r3 io103ndb4v0 r4 gnd r5 io101pdb4v0 r6 io100npb4v0 r7 gnd r8 io99pdb4v0 r9 io97pdb4v0 r10 gnd r11 gnd r12 v cc r13 gnd r14 v cc r15 gnd r16 v cc r17 gnd r18 gdb2/io83pdb2v0 r19 io78pdb2v0 r20 gnd 676-pin fbga pin number afs1500 function
676-pin fbga v2.0 4-33 r21 io72ndb2v0 r22 io72pdb2v0 r23 gnd r24 io71pdb2v0 r25 v cci b2 r26 io67ndb2v0 t1 gnd t2 nc t3 gfa1/io105pdb4v0 t4 gfa0/io105ndb4v0 t5 io101ndb4v0 t6 io96pdb4v0 t7 io96ndb4v0 t8 io99ndb4v0 t9 io97ndb4v0 t10 v cci b4 t11 v cc t12 gnd t13 v cc t14 gnd t15 v cc t16 gnd t17 v cci b2 t18 io83ndb2v0 t19 io78ndb2v0 t20 gda1/io81pdb2v0 t21 gdb1/io80pdb2v0 t22 io73ndb2v0 t23 io73pdb2v0 t24 io71ndb2v0 t25 nc t26 gnd u1 nc u2 nc u3 io102pdb4v0 u4 io102ndb4v0 676-pin fbga pin number afs1500 function u5 v cci b4 u6 io91pdb4v0 u7 io91ndb4v0 u8 io92pdb4v0 u9 gnd u10 gnd u11 v cc33a u12 gnda u13 v cc33a u14 gnda u15 v cc33a u16 gnda u17 v cc u18 gnd u19 io74ndb2v0 u20 gda0/io81ndb2v0 u21 gdb0/io80ndb2v0 u22 v cci b2 u23 io75ndb2v0 u24 io75pdb2v0 u25 nc u26 nc v1 nc v2 v cci b4 v3 io100ppb4v0 v4 gnd v5 io95pdb4v0 v6 io95ndb4v0 v7 v cci b4 v8 io92ndb4v0 v9 gndnvm v10 gnda v11 nc v12 av4 v13 nc v14 av5 676-pin fbga pin number afs1500 function v15 ac5 v16 nc v17 gnda v18 io77ppb2v0 v19 io74pdb2v0 v20 v cci b2 v21 io82ndb2v0 v22 gda2/io82pdb2v0 v23 gnd v24 gdc1/io79pdb2v0 v25 v cci b2 v26 nc w1 gnd w2 io94ppb4v0 w3 io98pdb4v0 w4 io98ndb4v0 w5 gec1/io90pdb4v0 w6 gec0/io90ndb4v0 w7 gnd w8 v ccnvm w9 vccib4 w10 v cc15a w11 gnda w12 ac4 w13 v cc33a w14 gnda w15 ag5 w16 gnda w17 pub w18 v cci b2 w19 tdi w20 gnd w21 io84ndb2v0 w22 gdc2/io84pdb2v0 w23 io77npb2v0 w24 gdc0/io79ndb2v0 676-pin fbga pin number afs1500 function
actel fusion family of mixed-sign al fpgas package pin assignments 4-34 v2.0 w25 nc w26 gnd y1 nc y2 nc y3 geb1/io89pdb4v0 y4 geb0/io89ndb4v0 y5 v cci b4 y6 gea1/io88pdb4v0 y7 gea0/io88ndb4v0 y8 gnd y9 v cc33pmp y10 nc y11 v cc33a y12 ag4 y13 at4 y14 atrtn2 y15 at5 y16 v cc33a y17 nc y18 v cc33a y19 gnd y20 tms y21 v jtag y22 vccib2 y23 trst y24 tdo y25 nc y26 nc 676-pin fbga pin number afs1500 function
part number and revision date v2.0 4-35 part number and revision date part number 51700092-016-1 revised july 2009 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v2.0) page preliminary v1.7 (october 2008) the version number category was change d from preliminary to production, which means the datasheet contai ns information based on final characterization. the versio n number changed from pr eliminary v1.7 to v2.0. n/a "180-pin qfn" table was updated to remove the du plicates of pins b12 and b34. 4-4 advance v1.6 (august 2008) the version number catego ry was changed from advance to preliminary, which means the datasheet contains information based on simulation and/or initial characterization. the information is be lieved to be correct, but changes are possible. n/a advance v1.4 (july 2008) the title of the datasheet changed fro m actel programmable system chips to actel fusion mixed-signal fpgas. in addition, all instances of programmable system chip were change d to mixed-signal fpga. n/a advance v1.1 (may 2008) the "108-pin qfn" figure was updated. d1 to d4 are new and the figure was changed to bottom view. the no te below the figure is new. 4-1 the "180-pin qfn" figure was updated. d1 to d4 are new and the figure was changed to bottom view. the no te below the figure is new. 4-3 advance v0.9 october 2007 this change table states that in the "208-pin pqfp" table listed under the advance v0.8 changes, the afs090 device ha d a pin change. that is incorrect. pin 102 was updated for afs250 and afs 600. the function name changed from v cc33acap to v cc33a . 4-8 advance v0.8 (june 2007) in the "108-pin qfn" table , the function changed from v cc33acap to v cc33a for the following pin: b25 4-2 in the "180-pin qfn" table , the function changed from v cc33acap to v cc33a for the following pins: afs090: b29 afs250: b29 4-4 in the "208-pin pqfp" table , the function changed from v cc33acap to v cc33a for the following pins: afs090: 102 afs250: 102 4-8 in the "256-pin fbga" table , the function changed from v cc33acap to v cc33a for the following pins: afs090: t14 afs250: t14 afs600: t14 afs1500: t14 4-12
actel fusion family of mixed-sign al fpgas package pin assignments 4-36 v2.0 advance v0.8 (continued) in the "484-pin fbga" table , the function changed from v cc33acap to v cc33a for the following pins: afs600: ab18 afs1500: ab18 4-20 in the "676-pin fbga" table , the function changed from v cc33acap to v cc33a for the following pins: afs1500: ad20 4-28 advance v0.7 (january 2007) the vmv pins have now been tied internally with the v cci pins. n/a the afs090 "108-pin qfn" table was updated. 4-2 the afs090 and afs250 devices were updated in the "108-pin qfn" table . 4-2 the afs250 device was updated in the "208-pin pqfp" table . 4-8 advance v0.7 (continued) the afs600 device was updated in the "208-pin pqfp" table . 4-8 the afs090, afs250, afs600, and afs 1500 devices were updated in the "256-pin fbga" table . 4-12 the afs600 and afs1500 devices were updated in the "484-pin fbga" table . 4-20 the afs600 device was updated in the "676-pin fbga" table . 4-28 advance v0.5 (june 2006) the heading was incorrect in the "208-pin pqfp" table . it should be afs250 and not afs090. 4-8 advance v0.4 (april 2006) the "256-pin fbga" table for the afs1500 is new. 4-12 advance v0.2 (april 2006) the "108-pin qfn" table for the afs090 device is new. 4-2 the "180-pin qfn" table for the afs090 device is new. 4-4 the "208-pin pqfp" table for the afs090 device is new. 4-8 the "256-pin fbga" table for the afs090 device is new. 4-12 the "256-pin fbga" table for the afs250 device is new. 4-12 previous version changes in current version (v2.0) page
datasheet categories v2.0 4-37 datasheet categories categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are designated as ?produ ct brief,? ?advance,? and ?production?. the definition of these categories are as follows: product brief the product brief is a summarized version of a datashee t (advance or production) and contains general product information. this document give s an overview of specific de vice and family information. advance this version contains initial estima ted information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but no t for production. this label only applies to the dc and switching characteristics chapter of the datasheet and will only be used when the data ha s not been fully characterized. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subject to the export administration regu lations (ear). they could require an approved export license prio r to export from the united states. an export includes release of product or disclosure of technology to a foreign na tional inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have comp leted actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functi onality or performance. it is the resp onsibility of each customer to ensure the fitness of any actel product (but especially a new product) for a particular purpose, including appropriateness for safety-cri tical, life-support, and othe r high-reliabili ty applications. consult actel?s terms and conditions for specific liability exclusions relating to lif e-support applications. a reliab ility report covering all of actel?s products is available on the actel website at http://www.actel.com/doc uments/ort_report.pdf . actel also offers a variety of enhanced qua lification and lot acceptance screening procedures. contact your local actel sales office for additional reliability information.

section ii ? user?s guide

low-power flash technology

v1.4 1-1 1 ? fpga array architecture in low-power flash devices device architecture advanced flash switch unlike sram fpgas, the low-power flash devices use a live-at-power- up isp flash switch as their programming element. flash cell s are distributed throug hout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate versatile inputs and outputs. in the flash switch, two transistors shar e the floating gate, whic h stores the programming information ( figure 1-1 ). one is the sensing transistor, which is only used for writing and verification of the floating gate voltage. the other is the switchin g transistor. the latter is used to connect or separate routing nets, or to configure versatile logic. it is also used to erase the floating gate. dedicated high-performance li nes are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the device core. maximum core utilization is possible for virtually any design. th e use of the flash switch technolo gy also removes the possibility of firm errors, which are increasingly common in sram-based fpgas. figure 1-1 ? flash-based switch sensing switching switch in switch out word floating gate
fpga array architecture in low-power flash devices 1-2 v1.4 fpga array architecture support the flash fpgas listed in table 1-1 support the architecture featur es described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 1-1 . where the information applie s to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 1-1 . where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 1-1 ? flash-based fpgas series family * description igloo ? igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic ? 3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
fpga array architecture in low-power flash devices v1.4 1-3 device overview the low-power flash devices cons ist of multiple disti nct programmable architectural features ( figure 1-5 on page 1-5 through figure 1-7 on page 1-6 ): ? fpga fabric/core (versatiles) ? routing and clock resources (versanets) ?flashrom ? dedicated sram and/or fifo ? 30 k gate and smaller device densities do not support sram or fifo. ? automotive devices do not support fifo operation. ? i/o structures ? flash*freeze technology and low-power modes notes: * bank 0 for the 30 k devices ? flash*freeze mode is supported on igloo devices . figure 1-2 ? igloo and proasic3 nano device architecture ov erview with two i/o banks (applies to 10 k and 30 k device densities, excluding igloo plus devices) versatile i/os user nonvolatile flashrom flash*freeze ? technology charge pumps bank 1* bank 1 bank 0 bank 1 ccc-gl
fpga array architecture in low-power flash devices 1-4 v1.4 note: ? flash*freeze mode is supported on igloo devices . figure 1-3 ? igloo device architecture overview with two i/o banks with ram and pll (60 k and 125 k gate densities) note: ? flash*freeze mode is supported on igloo devices. figure 1-4 ? igloo device architecture overview with three i/o banks (agln015, agln020, a3pn015, and a3pn020) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom flash*freeze ? technology charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 versatile ccc - g l i/os user nonvolatile flashrom flash * freeze ? te c hnolo g y c har g e pumps bank 1 bank 1 bank 0 bank 1
fpga array architecture in low-power flash devices v1.4 1-5 note: flash*freeze technology only applies to igloo and proasic3l families. figure 1-5 ? igloo, igloo nano, proasic3 nano, and proasic3/l device architecture overview with four i/o banks (agl600 device is shown) note: * aglp030 does not contain a pll or support aes security. figure 1-6 ? igloo plus device architecture overview with four i/o banks isp aes decryption* user nonvolatile flashrom flash*freeze ? technology charge pumps ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 ram block 4,608-bit dual-port sram or fifo block * versatile ccc i/os isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 3 bank 3 bank 2 *
fpga array architecture in low-power flash devices 1-6 v1.4 note: flash*freeze technology only applies to iglooe devices. figure 1-7 ? iglooe and proasic3e device architectu re overview (agle600 device is shown) 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os 4,608-bit dual-port sram or fifo block ram block isp aes decryption user nonvolatile flashrom flash*freeze ? technology charge pumps bank 3 bank 2 bank 0 bank 1 bank 5 bank 4 bank 7 bank 6
fpga array architecture in low-power flash devices v1.4 1-7 core architecture versatile the proprietary igloo and proasic3 device archit ectures provide granularity comparable to gate arrays. the device core consists of a sea-of-versatiles architecture. as illustrated in figure 1-8 , there are four inputs in a logic versatile cell, and each versatile can be configured using the appropriat e flash switch connections: ? any 3-input logic function ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set (on a 4 th input) versatiles can flexibly map the logic and sequenti al gates of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and th e output of the tile can connect to high-speed, very-long-line routing resources. versatiles and larger fu nctions can be connec ted with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-f lop, set/clr is supported by a fourth input. the set/clr signal can only be routed to this fo urth input over the versanet (global) network. however, if, in the user?s design, the set/clr si gnal is not routed over the versanet network, a compile warning message will be given, and the intended logic function will be implemented by two versatiles instead of one. the output of the versatile is f2 wh en the connection is to the ultra-fast loca l lines, or yl when the connection is to the efficient long-l ine or very-long-line resources. * this input can only be connected to the global clock distribution network. figure 1-8 ? low-power flash device core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc * f2 yl
fpga array architecture in low-power flash devices 1-8 v1.4 array coordinates during many place-and-route operations in the ac tel designer software tool, it is possible to set constraints that requir e array coordinates. table 1-2 provides array coordinates of core cells and memory blocks for igloo and proasic3 devices. table 1-3 provides the information for igloo plus devices. table 1-4 on page 1-9 provides the informa tion for igloo nano and proasic3 nano devices. the array coordinates are measured from th e lower left (0, 0). they can be used in region constraints for spec ific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and i/os. i/o and cell coordinates are used for placement constraints. two coordina te systems are needed because there is not a one-to-one correspondence be tween i/o cells and core cells. in addition, the i/o coordinate system changes depending on the die/package combination. it is not listed in table 1-2 . the designer chipplanner tool provides the ar ray coordinates of all i/o locations. i/o and cell coordinates are used for plac ement constraints. however, i/o placement is easier by package pin assignment. figure 1-9 on page 1-9 illustrates the array coordinates of a 600 k gate device. for more information on how to use a rray coordinates for region/pla cement constraints, see the designer user's guide or online help (available in the software) for software tools. table 1-2 ? igloo and proasic3 array coordinates device versatiles memory rows entire die min. max. bottom top min. max. igloo proasic3/ proasic3l x y x y (x, y) (x, y) (x, y) (x, y) agl015 a3p015 3 2 34 13 none none (0, 0) (37, 15) agl030 a3p030 3 3 66 13 none none (0, 0) (69, 15) agl060 a3p060 3 2 66 25 none (3, 26) (0, 0) (69, 29) agl125 a3p125 3 2 130 25 none (3, 26) (0, 0) (133, 29) agl250 a3p250/l 3 2 130 49 none (3, 50) (0, 0) (133, 53) agl400 a3p400 3 2 194 49 none (3, 50) (0, 0) (197, 53) agl600 a3p600/l 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) agl1000 a3p1000/l 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103) agle600 a3pe600 / l , rt3pe600 l 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) a3pe1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 127) agle3000 a3pe3000/l, rt3pe3000l 3 6 450 173 (3, 2) or (3, 4) (3, 174) or (3, 176) (0, 0) (453, 179) table 1-3 ? igloo plus array coordinates device versatiles memory rows entire die min. max. bottom top min. max. igloo plus x y x y (x, y) (x, y) (x, y) (x, y) aglp030 2 3 67 13 none none (0, 0) (69, 15) aglp060 2 2 67 25 none (3, 26) (0, 0) (69, 29) aglp125 2 2 131 25 none (3, 26) (0, 0) (133, 29)
fpga array architecture in low-power flash devices v1.4 1-9 table 1-4 ? igloo nano and proasic3 nano array coordinates device versatiles memory rows entire die min. max. bottom top min. max. igloo nano proasic3 nano (x, y) (x, y) (x, y) (x, y) (x, y) (x, y) agln010 a3p010 (0, 2) (32, 5) none none (0, 0) (34, 5) agln015 a3pn015 (0, 2) (32, 9) none none (0, 0) (34, 9) agln020 a3pn020 (0, 2) 32, 13) none none (0, 0) (34, 13) agln060 a3pn060 (3, 2) (66, 25) none (3, 26) (0, 0) (69, 29) agln125 a3pn125 (3, 2) (130, 25) none (3, 26) (0, 0) (133, 29) agln250 a3pn250 (3, 2) (130, 49) none (3, 50) (0, 0) (133, 49) note: the vertical i/o tile coordinates are not shown. west-s ide coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east-side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. figure 1-9 ? array coordinates for agl600, agle600, a3p600, and a3pe600 top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (169, 1) to (192, 1) i/o tile memory blocks memory blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile (core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) (0, 79) (197, 1)
fpga array architecture in low-power flash devices 1-10 v1.4 routing architecture the routing structure of low-power flash devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast loca l resources; efficient long-line resources; high-speed, very-long-line resource s; and the high-performa nce versanet networks. the ultra-fast local resources are de dicated lines that allo w the output of each versatile to connect directly to every input of th e eight surrounding versatiles ( figure 1-10 on page 1-10 ). the exception to this is that the set/clr input of a vers atile configured as a d-flip-flop is driven only by the versatile global network. the efficient long-line resour ces provide routing for longer distance s and higher-fanout connections. these resour ces vary in length (spanning one, two, or four versatiles), run both vertically and horizontally, an d cover the entire device ( figure 1-11 on page 1-11 ). each versatile can drive signals onto the effici ent long-line resources, which can access every input of every versatile. routing software automatically inse rts active buffers to limit loading effects. the high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length 1 2 versatiles in the vertical direction and length 16 in the horizontal direction from a given core versatile ( figure 1-12 on page 1-11 ). very long lines in low-power flash devices have been enhanc ed over those in previo us proasic families. this provides a significant performance boost for long-reach signals. the high-performance versanet global networks ar e low-skew, high-fanout nets that are accessible from external pins or internal lo gic. these nets are typically used to distribute clocks, resets, and other high-fanout nets requirin g minimum skew. the versanet netw orks are implemented as clock trees, and signals can be introduced at any junc tion. these can be employ ed hierarchically, with signals accessing every input of every versatil e. for more details on versanets, refer to global resources in actel lo w-power flash devices. note: input to the core cell for the d-flip-flop set a nd reset is only available via the versanet global network connection. figure 1-10 ? ultra-fast local lines connected to the eight nearest neighbors l l l l l l inputs output ultra-fast local lines (connects a versatile to the adjacent versatile, i/o buffer, or memory block) l ll long lines
fpga array architecture in low-power flash devices v1.4 1-11 figure 1-11 ? efficient long-line resources figure 1-12 ? very-long-line resources l l llll l lllll l l llll l l llll l l llll spans 1 versatile spans 2 versatiles spans 4 versatiles spans 1 versatile spans 2 versatiles spans 4 versatiles versatile high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring pad ring 1612 block of versatiles sram
fpga array architecture in low-power flash devices 1-12 v1.4 related documents handbook documents global resources in actel low-power flash devices http://www.actel.com/documents/lpd_glorbal_hbs.pdf user?s guides designer user's guide http://www.actel.com/documents/designer_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-002-4 revised december 2008
fpga array architecture in low-power flash devices v1.4 1-13 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 1-1 flash-based fpgas . 1-2 figure 1-2 igloo and proasic3 nano devi ce architecture overview with two i/o banks (applies to 10 k and 30 k device densities, excluding igloo plus devices) through figure 1-5 igloo, igloo nano, proasic3 nano, and proasic3/l device architecture overview with four i/o banks (agl600 device is shown) are new. 1-3 , 1-4 table 1-4 igloo nano and proasic3 nano array coordinates is new. 1-9 v1.2 (june 2008) the title of this document was changed from "core architecture of igloo and proasic3 devices" to "fpga array arch itecture in low-power flash devices." 1-1 the "fpga array architecture support" section was revised to include new families and make the in formation more concise. 1-2 table 1-2 igloo and proasic3 array coordinates was updated to include military proasic3/el and rt proasic3 devices. 1-8 v1.1 (march 2008) the following changes were made to the family descriptions in table 1-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 1-2 v1.0 (january 2008) table 1-1 flash-based fpgas and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "device overview" section are new. 1-2 the "device overview" section was updated to note that 15 k devices do not support sram or fifo. 1-3 figure 1-6 igloo plus device architecture overview with four i/o banks is new. 1-5 table 1-2 igloo and proasic3 array coordinates was updated to add a3p015 and agl015. 1-8 table 1-3 igloo plus array coordinates is new. 1-8

global resources and clock conditioning

v1.4 2-1 2 ? global resources in actel low-power flash devices introduction actel igloo, ? fusion, and proasic ? 3 fpga devices offer a powerful, low-delay versanet global network scheme and have extensiv e support for multiple clock doma ins. in addition to the clock conditioning circuits (cccs) and phase-locked lo ops (plls), there is a co mprehensive global clock distribution network called a versanet global netw ork. each logical elemen t (versatile) input and output port has access to these global networks . the versanet global networks can be used to distribute low-skew clock signals or high-fanout ne ts. in addition, these hi ghly segmented versanet global networks offer users the flexibility to create low-skew local netw orks using spines. this document describes versanet global networks and discusses how to assign signals to these global networks and spines in a design flow. details conc erning low-power flash de vice plls are described in clock conditioning circuits in igloo and proasic3 devices . this document describes the low-power flash devices? global architecture and uses of these global networks in designs. global architecture low-power flash devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has up to six cccs, some with plls. ? in iglooe, proasic3el, and proasic3e devices, all cccs have plls?hence, 6 plls per device. ? in igloo, igloo nano, igloo plus, proasi c3, and proasic3l devices, the west ccc contains a pll core (except in 10 k through 30 k devices). ? in fusion devices, the west cc c also contains a pll core. in the two larger devices (afs600 and afs1500), the west and ea st cccs each contain a pll. each pll includes delay lines, a phase shifter (0, 90, 180, 270), and cl ock multipliers/dividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the versanet global network. the east and west cccs each have access to three versanet global lines on each side of the chip (six global lines total). the cccs at the four corners each have access to three quadrant global lines in ea ch quadrant of the chip (except in 10 k through 30 k gate devices). the nano 10 k, 15 k, and 20 k devices support fo ur versanet global resources, and 30 k devices support six global resources. the 10 k through 30 k devices have simplified cccs called ccc-gls. the flexible use of the versanet global network allows the desi gner to address several design requirements. user applications th at are clock-resource-intensive can easily route external or gated internal clocks using versanet global routing netw orks. designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the versanet global network. the following sections give an overview of the versanet global network, the structure of the global network, and the clock aggregation feature that enables a design to have very low clock skew using spines.
global resources in actel low-power flash devices 2-2 v1.4 global resource support in flash-based devices the flash fpgas listed in table 2-1 support the global resources an d the functions described in this document. igloo terminology in documentation, th e terms igloo series and igloo devices refer to all of the igloo products as listed in table 2-1 . where the information applie s to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 2-1 . where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 2-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities igloo nano the industry?s lowest-power , smallest-size solution proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
global resources in actel low-power flash devices v1.4 2-3 versanet global network distribution one of the architectural benefits of low-power flash architecture is the set of powerful, low-delay versanet global networks that can access the versatiles, sram, an d i/o tiles of the device. each device offers a chip global network with six global lines (except for nano 10 k, 15 k, and 20 k gate devices) that are distributed from th e center of the fpga array. in a ddition, each devi ce (except the 10 k through 30 k gate device) has four quadrant gl obal networks, each with three regional global line resources. these quadrant glob al networks can only drive a signal inside their own quadrant. each core versatile has access to nine global line resources?three quadrant and six chip-wide (main) global networks?and a total of 18 globals are available on the device (3 4 regional from each quadrant and 6 global). figure 2-1 shows an overview of the ve rsanet global network and devi ce architecture for devices 60 k and above. figure 2-2 and figure 2-3 on page 2-4 show simplified versanet global networks. the versanet global networks are segmented and consist of versanet glob al networks, spines, global ribs, and global multiplexers (muxes), as shown in figure 2-1 . the global networks are driven from the global rib at the center of the die or quadrant global networks at the north or south side of the die. the global network uses th e mux trees to access the spine, and the spine uses the clock ribs to ac cess the versatile. access is available to the chip or quadrant global networks and the spines through th e global muxes. access to the spine using the global muxes is explained in the "spine architecture" section on page 2-5 . these versanet global networks offer fast, lo w-skew routing resources for high-fanout nets, including clock signals. in addition, these high ly segmented global networks offer users the flexibility to create low-skew loca l networks using spines for up to 252 internal/external clocks or other high-fanout nets in low-power flash device s. optimal usage of these low-skew networks can result in significant improv ement in design performance. note: not applicable to 10 k through 30 k gate devices figure 2-1 ? overview of versanet global network and device architecture pa d rin g pa d rin g pa d rin g i/o rin g i/orin g c hip (main) g lo b al pa d s g lo b al pa d s hi g h-performan c e g lo b al network g lo b al s pine g lo b al ri b s sc ope of s pine (sha d e d area plus lo c al rams an d i/os) s pine- s ele c tion mux em b e dd e d ram blo c ks lo g i c tiles top s pine bottom s pine t1 b1 t2 b2 t3 b3 qua d rant g lo b al pa d s
global resources in actel low-power flash devices 2-4 v1.4 figure 2-2 ? simplified versanet global ne twork (30 k gates and below) figure 2-3 ? simplified versanet global network (60 k gates and above) global drivers global drivers 22 22 2 2 chip (main) global network north quadrant global network south quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc
global resources in actel low-power flash devices v1.4 2-5 spine architecture the low-power flash device archit ecture allows the versanet glob al networks to be segmented. each of these networks contains spines (the vertical branches of the global network tree) and ribs that can reach all the versatiles inside its region . the nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the ch ip (main) global network, which has six spines. note that the number of quadrant globals and globals/spin es per tree varies depending on the specific device. refer to table 2-2 on page 2-6 for the clocking resources availabl e for each device. th e spines are the vertical branches of the gl obal network tree, shown in figure 2-3 . each spine in a vertical column of a chip (main) global network is further divided into two spine segments of equal lengths: one in the top and one in the bottom half of the di e (except in 10 k through 30 k gate devices). top and bottom spine segments radiating from the center of a device have the same height. however, just as in the proasic plus ? family, signals assigned only to the top and bottom spine cannot access the middle two rows of the die. the spines for quadrant clock networks do not cross the middle of the die and cannot access the middle two rows of the architecture. each spine and its associated ribs cover a certain area of the device (the "scope" of the spine; see figure 2-3 ). each spine is accessed by the dedicated global networ k mux tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or by another net defined by the user. details of the chip (main) global network spine- selection mux are presented in figure 2-5 on page 2-8 . the spine drivers for each spine are located in the middle of the die. quadrant spines can be driven from user i/os on th e north and south sides of the die. the ability to drive spines in the quadrant glob al networks can have a significan t effect on system performance for high-fanout inputs to a design . access to the top quadrant spine regions is from the top of the die, and access to the bottom qu adrant spine regions is from the bottom of the die. the a3pe3000 device has 28 clock trees and each tree has nine spines; this flexible global network architecture enables users to map up to 252 different inte rnal/external clocks in an a3pe3000 device.
global resources in actel low-power flash devices 2-6 v1.4 table 2-2 ? globals/spines/rows for ig loo and proasic3 devices proasic3/ proasic3l devices igloo devices chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine a3pn010 agln010 4 0 1 0 0 260 260 4 a3pn015 agln015 4 0 1 0 0 384 384 6 a3pn020 agln020 4 0 1 0 0 520 520 6 a3pn060 agln060 6 12 4 9 36 384 1,536 12 a3pn125 agln125 6 12 8 9 72 384 3,072 12 a3pn250 agln250 6 12 8 9 72 768 6,144 24 a3p015 agl015 6 0 1 9 9 384 384 12 a3p030 agl030 6 0 2 9 18 384 768 12 a3p060 agl060 6 12 4 9 36 384 1,536 12 a3p125 agl125 6 12 8 9 72 384 3,072 12 a3p250/l agl250 6 12 8 9 72 768 6,144 24 a3p400 agl400 6 12 12 9 108 768 9,216 24 a3p600/l agl600 6 12 12 9 108 1,152 13,824 36 a3p1000/l agl1000 6 12 16 9 144 1,536 24,576 48 a3pe600/l agle600 6 12 12 9 108 1,120 13,440 35 a3pe1500 6 12 20 9 180 1,888 37,760 59 a3pe3000/l agle3000 6 12 28 9 252 2,656 74,368 83 table 2-3 ? globals/spines/rows fo r igloo plus devices igloo plus devices chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine aglp030 6 0 2 9 18 384* 792 12 aglp060 6 12 4 9 36 384* 1,584 12 aglp125 6 12 8 9 72 384* 3,120 12 note: *clock trees that are located at far left and far right will support more versatiles. table 2-4 ? globals/spines/rows for fusion devices fusion device chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine afs090 6 12 6 9 54 384 2,304 12 afs250 6 12 8 9 72 768 6,144 24 afs600 6 12 12 9 108 1,152 13,824 36 afs1500 6 12 20 9 180 1,920 38,400 60
global resources in actel low-power flash devices v1.4 2-7 spine access the physical location of each sp ine is identified by the letter 't' (top) or 'b' (bottom) and an accompanying number (t n or b n ). the number n indicates the horizontal location of the spine; 1 refers to the first spine on the left side of the die. since there are six chip spines in each spine tree, there are up to six spines available fo r each combination of 't' (or 'b') and n (for example, six t1 spines). similarly, there are three quadrant spines available for each combination of 't' (or 'b') and n (for example, four t1 spines), as shown in figure 2-4 . spines are also called local clocks, and are ac cessed by the dedicated global mux architecture. these muxes define how a particu lar spine is driven. refer to figure 2-5 on page 2-8 for the global mux architecture. the muxes for each chip global spine are located in the middle of the die. access to the top and bottom chip global spine is available from the middle of the die. there is no control dependency between the top and bottom spines. if a top spine, t1, of a chip global network is assigned to a net, b1 is not wasted and can be used by the global clock network. the signal assigned only to the top or bottom sp ine cannot access the mi ddle two rows of the architecture. however, if a spin e is using the top and bottom at the same time (t1 and b1, for instance), the previous restriction is lifted. the muxes for each quadrant global spine are located in the north and south sides of the die. access to the top and bottom quadrant global sp ines is available from th e north and south sides of the die. since the muxes for quadrant spines are located in the north and south sides of the die, you should not try to drive t1 and b1 quadrant spines from the same signal. figure 2-4 ? chip global aggregation tn tn+1 tn+2 tn+3 tn+4 a b c global network
global resources in actel low-power flash devices 2-8 v1.4 using clock aggregation clock aggregation allows for multi-spine cloc k domains to be assigned using hardwired connections, with out adding any extra skew . a mux tree, shown in figure 2-5 , provides the necessary flexibility to allow long lines, local reso urces, or i/os to access domains of one, two, or four global spines. signal acce ss to the clock aggregation system is achieved through long-line resources in the central rib in the center of the die, and also through loca l resources in the north and south ribs, allowing i/os to feed directly into the clock system. as figure 2-6 indicates, this access system is contiguous. there is no break in the middle of the chip fo r the north and south i/o versanet access. this is different from the quadrant clocks located in these ribs, which only reach the middle of the rib. figure 2-5 ? spine selection mu x of global tree figure 2-6 ? clock aggregation tree architecture internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux
global resources in actel low-power flash devices v1.4 2-9 clock aggregation architecture this clock aggregation feature allows a balanced clock tree, which improves clock skew. the physical regions for clock aggregation are defined from left to right and shift by one spine. for chip global networks, there are three types of clock aggregation available, as shown in figure 2-7 : ? long lines that can drive up to four adjacent spines ? long lines that can drive up to two adjacent spines ? long lines that can drive one spine there are three types of clock aggregation av ailable for the quadrant spines, as shown in figure 2-7 : ? i/os or local resources that can drive up to four adjacent spines ? i/os or local resources that can drive up to two adjacent spines ? i/os or local resources that can drive one spine ? as an example, a3pe600 and afs600 devices have twelve spine location s: t1, t2, t3, t4, t5, t6, b1, b2, b3, b4, b5, and b6. table 2-5 shows the clock aggreg ation you can have in a3pe600 and afs600. the clock aggregation for the quadrant spines can cross over from the left to right quadrant, but not from top to bottom. the quad rant spine assignment t1:t4 is legal, but the quadrant spine assignment t1:b1 is not legal. no te that this clock aggregation is hardwired. you can always assign signals to spine t1 and b2 by instantiating a buffer, but this may ad d skew in the signal. figure 2-7 ? four spines aggregation tn tn + 1 tn + 2 tn + 4 a b c tn + 3 table 2-5 ? spine aggregation in a3pe600 or afs600 clock aggregation spine 1 spine t1, t2, t3, t4, t5, t6, b1, b2, b3, b4, b5, b6 2 spines t1:t2, t2: t3, t3:t4, t4:t5, t5:t6, b1:b2, b2:b3, b3:b4, b4:b5, b5:b6 4 spines b1:b4, b2:b5, b3:b 6, t1:t4, t2:t5, t3:t6
global resources in actel low-power flash devices 2-10 v1.4 i/o banks and global i/os the following sections give an overview of naming conventions and other related i/o information. naming of global i/os in low-power flash devices, the gl obal i/os have access to certain clock conditioning circuitry and have direct access to the global network. additionally, the global i/os can be used as regular i/os, since they have identical capabilities to thos e of regular i/os. due to the comprehensive and flexible nature of the i/os in low-p ower flash devices, a naming sche me is used to show the details of the i/o. the global i/o uses the generic name gmn/iouxwbyvz. refer to the i/o structure section of the handbook for the device that you ar e using for more information on this naming convention. figure 2-8 represents the global input pins connec tion to the northwest ccc or northwest quadrant global networks for a low-power flash device. each global buffer, as well as the pll reference clock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core since each bank can have a differ ent i/o standard, the user should be careful to choose the correct global i/o for the design. there ar e 54 global pins availa ble to access 18 global networks. for the single-ended and voltage-referenc ed i/o standards, you can use any of these three available i/os to access the global network. for di fferential i/o standards such as lvds and lvpecl, the i/o macro needs to be placed on gaa0 and gaa1 or a simi lar location. the unassi gned global i/os can be used as regular i/os. note that pin names starti ng with gf and gc are associated with the chip global networks, and ga, gb, gd, and ge are used for quadrant global networks. figure 2-8 ? global i/o overview + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2
global resources in actel low-power flash devices v1.4 2-11 unused global i/o configuration the unused clock inputs behave similarly to the unused pro i/ os. the actel designer software automatically conf igures the unused global pins as inputs with pull-up resistors if they are not used as regular i/o. i/o banks and global i/o standards in low-power flash devices, any i/o or internal logic can be used to drive the global network. however, only the global macro placed at the global pins will use the hardwired connection between the i/o and global network. global signal (signal driving a global macro) assignment to i/o banks is no different from regular i/o assignme nt to i/o banks with the exception that you are limited to the pin placem ent location available. only global signals compatible with both the v cci and v ref standards can be assign ed to the same bank. design recommendations the following sections provide design flow recommendations for using a global network in a design. ? "global macros and i/o standards" ? "using global macros in synplicity" on page 2-13 ? "global promotion and demoti on using pdc" on page 2-14 ? "spine assignment" on page 2-15 ? "designer flow for global assignment" on page 2-16 ? "simple design example" on page 2-18 ? "global management in pll design" on page 2-20 ? "using spines of occupied global networks" on page 2-21 global macros and i/o standards low-power flash devices have six chip global networks and four quadrant clock networks. however, the same clock macros are used for assigning signals to chip globals and quadrant globals. depending on th e clock macro placement or assignment in the physical design constraint (pdc) file or multiview navigator (mvn), the signal will use the chip global network or quadrant network. table 2-6 on page 2-12 lists the clock macros available for low-power flash devices. refer to the igloo, fusion and proasi c3 macro library guide for details.
global resources in actel low-power flash devices 2-12 v1.4 use these available macros to assign a signal to the global network. in addition to these global macros, pll and clkdly macros ca n also drive the global networks . use i/o?standard?specific clock macros (clkbuf_x) to instan tiate a specific i/o standar d for the global signals. table 2-7 shows the list of these i/o?standard?specific macros. note that if you use these i/o?standard?specific clock macros, you cannot change the i/ o standard later in the design stage. if you use the regular clkbuf macro, you can use mvn or the pdc file in designer to change the i/o standard. the default i/o standard for clkbuf is lvttl in the current actel libero ? integrated design environment (ide) and designer software. table 2-6 ? clock macros macro name description symbol clkbuf input macro for clock network clkbuf_x input macro for clock network with specific i/o standard clkbuf_lvds/ lvpecl lvds or lvpecl input macro for clock network clkint internal clock interface clkbibuf bidirectional macro with input dedicated to routed clock network y pad clkbuf pad y clkbuf_x padn padp clkbuf_lvpecl y padn padp clkbuf_lvds y ay clkint d y e pad clkbibu f table 2-7 ? i/o standards within clkbuf name description clkbuf_lvcmos5 lvcmos clock buffer with 5.0 v cmos voltage level clkbuf_lvcmos33 lvcmos clock buffer with 3.3 v cmos voltage level clkbuf_lvcmos25 lvcmos clock buffer with 2.5 v cmos voltage level 1 clkbuf_lvcmos18 lvcmos clock buffer with 1.8 v cmos voltage level clkbuf_lvcmos15 lvcmos clock buffer with 1.5 v cmos voltage level clkbuf_lvcmos12 lvcmos clock buffer with 1.2 v cmos voltage level clkbuf_pci pci clock buffer clkbuf_pcix pcix clock buffer clkbuf_gtl25 gtl clock buffer wi th 2.5 v cmos voltage level 1 clkbuf_gtl33 gtl clock buffer wi th 3.3 v cmos voltage level 1 notes: 1. supported in only the iglooe, proa sic3e, afs600, an d afs1500 devices 2. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology.
global resources in actel low-power flash devices v1.4 2-13 the current synthesis tool libraries only infer the clkbuf or clki nt macros in the netlist. all other global macros must be instantiat ed manually into your hdl code . the following is an example of clkbuf_lvcmos25 global macro in stantiations that you can copy and paste into your code: vhdl component clkbuf_lvcmos25 port (pad : in std_logic; y : out std_logic); end component begin -- concurrent statements u2 : clkbuf_lvcmos25 port map (pad => ext_clk, y => int_clk); end verilog module design (______); input _____; output ______; clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk); endmodule using global macros in synplicity the synplify ? synthesis tool automaticall y inserts global buffers for nets with high fanout during synthesis. by default, synplicity ? puts six global macros (clkbuf or clkint) in the netlist, including any global instantiation or pll ma cro. synplify always honors your global macro instantiation. if you have a pll (only primary output is used) in the design, synplify adds five more global buffers in the netlist. synplify uses the following global counting rule to add global macros in the netlist: 1. clkbuf: 1 global buffer 2. clkint: 1 global buffer 3. clkdly: 1 global buffer 4. pll: 1 to 3 global buffers ? gla, glb, glc, yb, and yc are counted as 1 buffer. ? glb or yb is used or bo th are counted as 1 buffer. ? glc or yc is used or bo th are counted as 1 buffer. clkbuf_gtlp25 gtl+ clock buffer with 2.5 v cmos voltage level 1 clkbuf_gtlp33 gtl+ clock buffer with 3.3 v cmos voltage level 1 clkbuf_ hstl _i hstl class i clock buffer 1 clkbuf_ hstl _ii hstl class ii clock buffer 1 clkbuf_sstl2_i sstl2 class i clock buffer 1 clkbuf_sstl2_ii sstl2 cl ass ii clock buffer 1 clkbuf_sstl3_i sstl3 class i clock buffer 1 clkbuf_sstl3_ii sstl3 cl ass ii clock buffer 1 table 2-7 ? i/o standards within clkbuf (continued) name description notes: 1. supported in only the iglooe, proa sic3e, afs600, an d afs1500 devices 2. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology.
global resources in actel low-power flash devices 2-14 v1.4 you can use the syn_global_buffers attribute in synplify to specify a ma ximum number of global macros to be inserted in the netlist. this can also be used to restrict the number of global buffers inserted. in the synplicity 8.1 version, a new attr ibute, syn_global_minfanout, has been added for low-power flash devices. this enables you to promote only the high-fanout signal to global. however, be aware that you can only have six signals assigned to chip global networks, and the rest of the global signals should be assigned to qu adrant global networks. so, if the netlist has 18 global macros, the remaining 12 global macros should have fanout that allows the instances driven by these globals to be placed inside a quadrant. global promotion and demotion using pdc the hdl source file or schematic is the pref erred place for defining which signals should be assigned to a clock network using clock macro instan tiation. this method is preferred because it is guaranteed to be honored by the synthesis tool s and designer software and stop any replication on this net by the synthesis tool. note that a signal with fanout ma y have logic replication if it is not promoted to global during synthesis. in th at case, the user cannot promote that signal to global using pdc. see synplicity help for details on using this attribute. to help you with global management, designer allows you to promote a si gnal to a global network or demote a global macro to a regular macro from th e user netlist using the compile options and/or pdc commands. the following are the pdc constr aints you can use to promote a signal to a global network: 1. pdc syntax to promote a regula r net to a chip global clock: assign_global_clock ?net netname the following will happen during promotion of a regular signal to a global network: ? if the net is external, the net will be dr iven by a clkint in serted automatically by compile. ? the i/o macro will not be changed to clkbuf macros. ? if the net is an internal net, the net will be driven by a clkint inserted automatically by compile. 2. pdc syntax to promote a net to a quadrant clock: assign_local_clock ?net netname ?type quadrant ur|ul|lr|ll this follows the same rule as the chip global clock network. the following pdc comma nd demotes the clock nets to regular nets. unassign_global_clock -net netname note: oavdivrst exis ts only in the fusion pll. figure 2-9 ? plls in low-powe r flash devices c lka g la extfb powerdown oadivr s t lo c k g lb yb g l c y c
global resources in actel low-power flash devices v1.4 2-15 the following will happen during demotion of a global signal to regular nets: ? clkbuf_x becomes inbuf_x; clkint is removed from the netlist. ? the essential global macro, su ch as the output of the clock conditioning circuit, cannot be demoted. ? no automatic buffering will happen. since no automatic buffering happens when a signal is demoted, this net may have a high delay due to large fanout. this may have a negative effect on the quality of the results. actel recommends that the automatic gl obal demotion only be used on small-fanout nets. use clock networks for high-fanout nets to improve timing and routability. spine assignment the low-power flash device archit ecture allows the global networks to be segmented and used as clock spines. these spines, also ca lled local clocks, enable the use of pdc or mvn to assign a signal to a spine. pdc syntax to promote a net to a spine/local clock: assign_local_clock ?net netname ?type [quadrant|chip] tn|bn|tn:bm if the net is driven by a clock macro, designer automatically demotes the cl ock net to a regular net before it is assigned to a spine. nets driven by a pll or clkdly ma cro cannot be assigned to a local clock. when assigning a signal to a sp ine or quadrant global networ k using pdc (pre-compile), the designer software will legalize the shared in stances. the number of shared instances to be legalized can be controlled by compile options . if these networks are created in mvn (only quadrant globals can be created), no legalization is done (as it is post-compile). designer does not do legalization between non-clock nets. as an example, consider two nets, net_clk and net_reset, driving the same flip-flop. the following pdc constraints are used: assign_local_clock ?net net_clk ?type chip t3 assign_local_clock ?net net_reset ?type chip t1:t2 during compile, designer adds a bu ffer in the reset net and places it in the t1 or t2 region, and places the flip-flop in the t3 spine region ( figure 2-10 ). figure 2-10 ? adding a buffer fo r shared instances d clk clr net_clk net_reset t1 t2 t3 d clk clr net_clk net_reset assign_local_clock -net net_clk -type chip t3 assi g n_local_clock -net net_reset -t yp e chi p t1:t2 before compile after compile added buffer
global resources in actel low-power flash devices 2-16 v1.4 you can control the maximum numb er of shared instances allowe d for the legalization to take place using the compile option dialog box shown in figure 2-11 . refer to libero ide / designer online help for details on the co mpile option dialog box. a large number of shared instances most likely indicates a floorplanning problem that you should address. designer flow for global assignment to achieve the desired result, pay special attention to global management during synthesis and place-and-route. the current synplify tool does no t insert more than six global buffers in the netlist by default. thus, the default flow will not assi gn any signal to the qu adrant global network. however, you can use attributes in synplify and in crease the default glob al macro assignment in the netlist. designer v6.2 suppo rts automatic quadrant global a ssignment, which was not available in designer v6.1. layout will ma ke the choice to assign the correct signals to global. however, you can also utilize pdc and perform manual global assignment to overwrite any automatic assignment. the following step-by-step suggestions guide you in the layout of your design and help you improve timing in designer: 1. run compile and check the compile report. th e compile report has global information in the "device utilization" section that describe s the number of chip and quadrant signals in the design. a "net report" section describes chip global nets, quadrant global nets, local clock nets, a list of nets listed by fanout, and net candidates for local clock assignment. review this information. note that yb or yc are counted as global on ly when they are used in isolation; if you use yb only and not glb, this net is not shown in the global/quadrant nets report. instead, it appears in the global utilization report. 2. if some signals have a very high fanout and are candidates for global promotion, promote those signals to global using the compile options or pdc commands. figure 2-12 on page 2-17 shows the globals management section of the compile options. select promote regular nets whose fanout is greater than and enter a reasonable value for fanouts. figure 2-11 ? shared instances in the co mpile option dialog box
global resources in actel low-power flash devices v1.4 2-17 3. occasionally, the synthesis tool assigns a global macro to cloc k nets, even though the fanout is significantly less than othe r asynchronous signals. select demote global nets whose fanout is less than and enter a reasonable value for fa nouts. this frees up some global networks from the signals that have very lo w fanouts. this can also be done using pdc. 4. use local clocks for the signals that do not need to go to the whole chip but should have low skew. this local clocks assignme nt can only be done using pdc. 5. assign the i/o buffer using mvn if you have fixed i/o assignment. as shown in figure 2-7 on page 2-9 , there are three sets of global pins th at have a hardwired connection to each global network. do not try to put multiple clkbuf macros in these three sets of global pins. for example, do not assign two clkbufs to gaa0x and gaa2x pins. 6. you must click commit at the end of mvn assignment. this runs the pre-layout checker and checks the validity of global assignment. 7. always run co mpile with the keep existing physi cal constraints option on. this uses the quadrant clock network assignment in the mv n assignment and checks if you have the desired signals on the global networks. 8. run layout and check the timing. figure 2-12 ? globals management gui in designer
global resources in actel low-power flash devices 2-18 v1.4 simple design example consider a design consisting of six building blocks (shift regi sters) and targeted for an a3pe600- pq208 ( figure 2-10 on page 2-15 ). the example design consists of two plls (pll1 has gla only; pll2 has both gla and glb), a global reset (aclr) , an enable (en_all), an d three external clock domains (qclk1, qclk2, and qclk3) driving the di fferent blocks of the design. note that the pq208 package only has two plls (which access the chip global network). because of fanout, the global reset and enable signals need to be assigned to the chip global resources. there is only one free chip global for the remaining global (qclk1, qclk2, qclk3). pl ace two of these signals on the quadrant global resource. the design example de monstrates manually a ssignment of qclk1 and qclk2 to the quadrant glob al using the pdc command. figure 2-13 ? block diagram of the global management example design reg256_behave reg_pllclk2gla_out reg_qclk1_out reg_qclk2_out reg_pllclk2glb_out reg_qclk3_out reg_pllclk1_out reg_pllclk2gla pdown pllz_clka data_qclk1 data_pllcqclk2 en_all qclk1 data_qclk2 qclk2 aclr data_qclk3 data_pllclk1 pll1_clka qclk3 shhl_in shhl_in adr clock shhl_out reg_qclk1 reg_qclk2 reg_pllclk2glb reg_qclk3 reg_pllclk1 pll1 \$115 power-down clka lock gla power-down clka lock gla glb pll2 \$116 reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out
global resources in actel low-power flash devices v1.4 2-19 step 1 run synthesis with default options. the synplicity log shows the following device utilization: step 2 run compile with the promote regular nets whose fanout is greater than option selected in designer; you will see the following in the compile report: device utilization report: ========================== core used: 1536 total: 13824 (11.11%) io (w/ clocks) used: 19 total: 147 (12.93%) differential io used: 0 total: 65 (0.00%) global used: 8 total: 18 (44.44%) pll used: 2 total: 2 (100.00%) ram/fifo used: 0 total: 24 (0.00%) flashrom used: 0 total: 1 (0.00%) ???????? the following nets have been assigned to a global resource: fanout type name -------------------------- 1536 int_net net : en_all_c driver: en_all_pad_clkint source: auto promoted 1536 set/reset_net net : aclr_c driver: aclr_pad_clkint source: auto promoted 256 clk_net net : qclk1_c driver: qclk1_pad_clkint source: auto promoted 256 clk_net net : qclk2_c driver: qclk2_pad_clkint source: auto promoted 256 clk_net net : qclk3_c driver: qclk3_pad_clkint source: auto promoted 256 clk_net net : $1n14 driver: $1i5/core source: essential 256 clk_net net : $1n12 driver: $1i6/core source: essential 256 clk_net net : $1n10 driver: $1i6/core source: essential designer will promote five more signals to global due to high fanout. there are eight signals assigned to global networks. cell usage: cell count area count*area dfn1e1c1 buff inbuf vcc gnd outbuf clkbuf pll total 1536 278 10 9 9 6 3 2 1853 2.0 1.0 0.0 0.0 0.0 0.0 0.0 0.0 3072.0 278.0 0.0 0.0 0.0 0.0 0.0 0.0 3350.0
global resources in actel low-power flash devices 2-20 v1.4 during layout, designer will assign two of the signals to quadrant global locations. step 3 (optional) you can also assign the qclk1_c and qclk2_c ne ts to quadrant regions using the following pdc commands: assign_local_clock ?net qclk1_c ?type quadrant ul assign_local_clock ?net qclk2_c ?type quadrant ll step 4 import this pdc with the netlist and run compile again. you will see the following in the compile report: the following nets have been assigned to a global resource: fanout type name -------------------------- 1536 int_net net : en_all_c driver: en_all_pad_clkint source: auto promoted 1536 set/reset_net net : aclr_c driver: aclr_pad_clkint source: auto promoted 256 clk_net net : qclk3_c driver: qclk3_pad_clkint source: auto promoted 256 clk_net net : $1n14 driver: $1i5/core source: essential 256 clk_net net : $1n12 driver: $1i6/core source: essential 256 clk_net net : $1n10 driver: $1i6/core source: essential the following nets have been assigned to a quadrant clock resource using pdc: fanout type name -------------------------- 256 clk_net net : qclk1_c driver: qclk1_pad_clkint region: quadrant_ul 256 clk_net net : qclk2_c driver: qclk2_pad_clkint region: quadrant_ll step 5 run layout. global management in pll design this section describes the legal global network co nnections to plls in th e low-power flash devices. for detailed information on using plls, refer to clock conditioning circuits in igloo and proasic3 devices . actel recommends that you use the dedicated gl obal pins to directly drive the reference clock input of the associated pll for reduced propagation delays and clock distortion. however, low-power flash devices offer the fl exibility to connect other signal s to reference clock inputs. each pll is associated with three global networks ( figure 2-8 on page 2-10 ). there are some limitations, such as when trying to use the global and pll at the same time: ? if you use a pll with only primary output, you can still use the remaining two free global networks. ? if you use three globals associ ated with a pll location, yo u cannot use the pll on that location. ? if the yb or yc output is used standalone, it will occupy one global, even though this signal does not go to the global network.
global resources in actel low-power flash devices v1.4 2-21 using spines of occ upied global networks when a signal is assigned to a global network, the flash switches are programmed to set the mux select lines (explained in the "clock aggregation architecture" section on page 2-9 ) to drive the spines of that network wi th the global net. however, if the global net is restricted from reaching into the scope of a spine, the mux drivers of that spine are available for other high-fanout or critical signals ( figure 2-14 ). for example, if you want to limit the clk1_c signal to the left half of the chip and want to use the right side of the same global network for clk2_c, you can add the following pdc commands: define_region -name region1 -type inclusive 0 0 34 29 assign_net_macros region1 clk1_c assign_local_clock ?net clk2_c ?type chip b2 conclusion igloo, fusion, an d proasic3 devices contain 18 global ne tworks: 6 chip glob al networks and 12 quadrant global networks . these global networks can be se gmented into loca l low-skew networks called spines. the sp ines provide low-skew networks for the high-fanout signals of a design. these allow you up to 252 different internal/externa l clocks in an a3pe3000 device. this document describes the architecture for the global network, plus guidelines and methodologies in assigning signals to globals and spines. figure 2-14 ? design example using spines of occupied global networks
global resources in actel low-power flash devices 2-22 v1.4 related documents handbook documents clock conditioning circuits in igloo and proasic3 devices http://www.actel.com /lpd_ccc_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglo oe and proasic3e device s http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf user?s guides igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-005-4 revised december 2008
global resources in actel low-power flash devices v1.4 2-23 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.4) page v1.3 (october 2008) the "global architecture" section was updated to include 10 k devices, and to include information about versanet global support for igloo nano devices. 2-1 the table 2-1 flash-based fpgas was updated to include igloo nano and proasic3 nano devices. 2-2 the "versanet global network distribution" section was updated to include 10 k devices and to note an exceptio n in global lines for nano devices. 2-3 figure 2-2 simplified vers anet global network (30 k gates and below) is new. 2-4 the "spine architecture" section was updated to clarify support for 10 k and nano devices. 2-5 table 2-2 globals/spines/rows fo r igloo and proasic3 devices was updated to include igloo nano and proasic3 nano devices. 2-6 the figure in the clkbuf_lvds/lvpecl row of table 2-6 clock macros was updated to change clkbibuf to clkbuf. 2-12 v1.2 (june 2008) a third bullet was added to the beginning of the "global architecture" section : in fusion devices, the west ccc al so contains a pll core. in the two larger devices (afs600 and afs1500), the west and east cccs each contain a pll. 2-1 the "global resource support in flash-based devices" section was revised to include new families and make the information more concise. 2-2 table 2-2 globals/spines/rows fo r igloo and proasic3 devices was updated to include a3pe600/ l in the device column. 2-6 table note 1 was revised in table 2-7 i/o standards within clkbuf to include afs600 and afs1500. 2-12 v1.1 (march 2008) the following changes were made to the family descriptions in table 2-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 2-2 v1.0 (january 2008) the "global architecture" section was updated to include the igloo plus family. the bullet was revised to incl ude that the west ccc does not contain a pll core in 15 k and 30 k devices. instances of "a3p030 and agl030 devices" were replaced with "15 k and 30 k gate devices." 2-1 table 2-1 flash-based fpgas and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 2-2 the "versanet global networ k distribution" section , "spine architecture" section , the note in figure 2-1 overview of ve rsanet global network and device architecture , and the note in figure 2-3 simplified versanet global network (60 k gates and above) were updated to include mention of 15 k gate devices. 2-3 , 2-4
global resources in actel low-power flash devices 2-24 v1.4 v1.0 (continued) table 2-2 globals/spines/rows fo r igloo and proasic3 devices was updated to add the a3p015 device, and to revise the values for clock trees, globals/spines per tree, and globals/spines per device for the a3p030 and agl030 devices. 2-6 table 2-3 globals/spines/rows for igloo plus devices is new. 2-6 clkbuf_lvcmos12 was added to table 2-7 i/o standards within clkbuf . 2-12 the "handbook documents" section was updated to include the three different i/o structures chapters for proasic3 and igloo device families. 2-22 51900087-1/3.05 figure 2-3 simplified versanet global network (60 k gates and above) was updated. 2-4 the "naming of global i/os" section was updated. 2-10 the "using global macros in synplicity" section was updated. 2-13 the "global promotion and demotion using pdc" section was updated. 2-14 the "designer flow for glob al assignment" section was updated. 2-16 the "simple design example" section was updated. 2-18 51900087-0/1.05 table 2-2 globals/spines/rows fo r igloo and proasic3 devices was updated. 2-6 previous version changes in current version (v1.4) page
v1.4 3-1 3 ? clock conditioning circuits in low-power flash devices and mixed-signal fpgas introduction this document outlines the following device information: clock conditioning circuit (ccc) features, pll core specifications, functional de scriptions, software co nfiguration information, detailed usage information, recommended board- level considerations, an d other considerations concerning clock conditioning circuits and global networks in low-power flash devices or mixed- signal fpgas. overview of clock conditioning circuitry in fusion, igloo, ? and proasic ? 3 devices, the cccs are used to implement freq uency division, frequency multiplication, phase shifting, and dela y operations. the cccs ar e available in six chip locations?each of the four chip corners and th e middle of the east and west chip sides. for device- specific variations, refer to the "device-specific layout" section on page 3-17 . the ccc is composed of the following: ? pll core ? 3 phase selectors ? 6 programmable delays and 1 fixe d delay that advances/delays phase ? 5 programmable frequency dividers that provide frequency multiplication/division (not shown in figure 3-5 on page 3-10 because they are automatically configured based on the user's required frequencies) ? 1 dynamic shift register that provides ccc dynamic reconfiguration capability figure 3-1 provides a simplified block diagram of th e physical implementation of the building blocks in each of the cccs. figure 3-1 ? overview of the cccs offered in fusion, igloo, and proasic3 3 global i/os clka clkb clkc to global network a to global network b to global network c from core to core ccc function block (with or without pll) multiplexer tree 3 global i/os 3 global i/os to core to core from core from core multiple signals single signals
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-2 v1.4 each ccc can implement up to three independent global buffers (with or without programmable delay) or a pll function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximu m of three global ou tputs for a given ccc. ccc programming the ccc block is fully configurab le, either via flash configurat ion bits set in the programming bitstream or through an asynch ronous interface. this asynchro nous dedicated shift register interface is dynamically accessible from inside the low-power flash devices to permit parameter changes, such as pll divide ratios and delays, during device operation. to increase the versatility and flexibility of the clock conditioning system, the ccc configuration is determined either by th e user during the design process, with configuration data being stored in flash memory as part of the devi ce programming procedure, or by writing data into a dedicated shift register during normal device operation. this latter mode allows the user to dynamically reconfigur e the ccc without the need for core programming. the shift register is accessed th rough a simple serial interface. refer to ujtag applications in actel?s low-power flash devices or the application note using global resources in actel fusion devices . global resources low-power flash and mixed-signal devices provide three global routing networks (gla, glb, and glc) for each of the ccc locations. there are potentially many i/o locations; each global i/o location can be chosen from only one of three possi bilities. this is controlled by the multiplexer tree circuitry in each global network. once the i/o location is selected, th e user has the option to utilize the cccs before the signals are connected to the global networks. the ccc in each location (up to six) has the same structure, so generating the ccc macros is always done with an identical software gui. the cccs in the corner locations drive the quadra nt global networks, and the cccs in the middle of the east and west chip sides drive the chip global networks. the quadrant global networks span only a quarter of the device, while the ch ip global networks sp an the entire device. for more details on global resources offe red in low-power flash devices, refer to global resources in actel low-powe r flash devices . a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb, or clkc-glc) of a given ccc. a pll macro uses the clka ccc input to drive its reference clock. it uses the gla and, optionally, the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) global output cannot be reused if the yb (or yc) ou tput is used. refer to the "pll macro signal descriptions" section on page 3-8 for more information. each global buffer, as well as the pll reference cl ock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-3 ccc support in actel?s flash devices the flash fpgas listed in table 3-1 support the ccc feature and th e functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 3-1 . where the information applie s to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 3-1 . where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 3-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities igloo nano the industry?s lowest-power , smallest-size solution proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-4 v1.4 global buffers with no programmable delays access to the global / quadrant global networks can be configured directly from the global i/o buffer, bypassing the ccc functional block (as indicated by the dotted lines in figure 3-1 on page 3-1 ). internal signals driven by the fpga core can use the global / quadrant global networks by connecting via the routed clock input of the multiplexer tree. there are many specific clkbuf macros supporting the wide variety of single-ended i/o inputs (clkbuf) and differential i/o standards (clkbuf_ lvds/lvpecl) in the lo w-power flash families. they are used when connecti ng global i/os directly to the global/quadrant networks. when an internal signal needs to be connected to the global/quadrant network, the clkint macro is used to connect the sign al to the routed clock inpu t of the network's mux tree. to utilize direct connection from global i/os or from internal signals to the global/quadrant networks, clkbuf, clkbuf_lvpecl/lvds, and clkint macros are used ( figure 3-2 ). ? the clkbuf and clkbuf_lvpecl/lvds 1 macros are composite macros that include an i/o macro driving a global buffer, which uses a hardwired connection. ? the clkbuf, clkbuf_lvpecl/lvds 1 and clkint macros are pa ss-through cloc k sources and do not use the pll or provide any programmable delay functionality. ? the clkint macro provides a global buffer function driven internally by the fpga core. the available clkbuf macros are described in the igloo, fusion, and proa sic3 macro library guide . global buffer with programmable delay clocks requiring clock adjustments can utilize th e programmable delay cores before connecting to the global / quadrant global netw orks. a maximum of 18 ccc global buffers can be instantiated in a device?three per ccc and up to six cccs per device. each ccc functional block contains a programmable delay element for each of the global networks (up to three), and users can utilize these features by using the corresponding macro ( figure 3-3 on page 3-5 ). 1. b-lvds and m-lvds are supported with the lvds macro. figure 3-2 ? ccc options: global buffers with no programmable delay none clkbuf_lvds/lvpecl macro padn padp y y y a e d pad pad y clkint macro clkbuf macro clkbibuf macro gla, glb, or glc clock source clock conditioning output clkbibuf
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-5 the clkdly macro is a pass-through clock source th at does not use the pll, but provides the ability to delay the clock input using a programmable delay. the clkdly macro takes the selected clock input and adds a user-defined de lay element. this macro generate s an output clock phase shift from the in put clock. the clkdly macro can be driven by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the software will automatically place the de dicated global i/o in the appropriate locations. many specific inbuf macros support the wide vari ety of single-ended and differential i/o standards supported by the low-power flash family. the available inbuf macros are described in the igloo, fusion, and proasic3 macro library guide. the clkdly macro can be driven directly from th e fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga re gular routing fabric. in this case, users must instantiate a special macro, pllint, to differen tiate the clock input driven by the hardwired i/o connection. the visual clkdly configuration in th e smartgen area of the actel libero ? integrated design environment (ide) and designer to ols allows the user to select the desired amount of delay and configures the delay elem ents appropriately. smartgen also a llows the user to select the input clock source. smartgen will automatically instan tiate the special macro, pllint, when needed. clkdly macro signal descriptions the clkdly macro supports one input and on e output. each signal is described in table 3-2 . note: for inbuf* driving a pll macro or clkd ly macro, the i/o will be hard-routed to the ccc; i.e., will be placed by software to a dedicated global i/o. figure 3-3 ? ccc options: global buffers with programmable delay padn padp y pad y input lvds/lvpecl macro inbuf* macro gla or glb or glc clock source clock conditioning output clk dlygl[4:0] gl table 3-2 ? input and output description of the clkdly macro signal name i/o description clk reference clock input reference clock input gl global output output primary output clock to respective global/quadrant clock networks
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-6 v1.4 clkdly macro usage when a clkdly macro is used in a ccc location, the programmable delay element is used to allow the clock delays to go to the gl obal network. in addition, the user can bypass the pll in a ccc location integrated with a pll, but use the prog rammable delay that is as sociated with the global network by instantiating the clkdly macro. the same is true when using programmable delay elements in a ccc location with no plls (the us er needs to instantiate the clkdly macro). there is no difference between the programmable delay el ements used for the pll and the clkdly macro. the ccc will be configured to use the programma ble delay elements in accordance with the macro instantiated by the user. as an example, if the pll is not used in a partic ular ccc location, the desi gner is free to specify up to three clkdly macros in the ccc, each of wh ich can have its own input frequency and delay adjustment options. if the pll core is used, assuming output to only one global clock network, the other two global clock networks are free to be us ed by either connecting directly from the global inputs or connecting from one or two clkdly macros for programmable delay. the programmable delay elements are shown in the block diagram of the pll block shown in figure 3-5 on page 3-10 . note that any ccc locations with no pll present contain only the programmable delay blocks going to the global networks (labeled "prog rammable delay type 2"). refer to the "clock delay adjustment" section on page 3-25 for a description of the programmable delay types used for the pll. also refer to table 3-13 on page 3-31 for programmable delay type 1 step delay values, and table 3-14 on page 3-32 for programmable delay type 2 step delay values. ccc locations with a pll present can be configured to utilize only the programmable delay blocks (programmable delay type 2) going to the global networks a, b, and c. global network a can be configured to use only th e programmable delay element (bypassing the pll) if the pll is not used in the design. figure 3-5 on page 3-10 shows a block diagram of the pll, where the programmable delay elements are used for the global networks (programmable delay type 2).
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-7 global buffers with pll function clocks requiring frequency sy nthesis or clock adjustments ca n utilize the pll core before connecting to the global / quadrant global networks. a maximum of 18 ccc global buffers can be instantiated in a device?three per ccc and up to six cccs per device. eac h pll core can generate up to three global/quadrant clocks, while a clock delay element provides one. the pll functionality of the clock conditio ning block is supported by the pll macro . the pll macro provides five deri ved clocks (three independent) from a single reference clock. the pll macro also provides power-down input and lo ck output signals. the additional inputs shown on the macro are configuration settings, which are configured through the use of smartgen. for manual setting of these bits refer to the igloo, fusion, and proasi c3 macro library guide for details. figure 3-5 on page 3-10 illustrates the various clock ou tput options and delay elements. notes: 1. for fusion only. 2. refer to the igloo, fusion, and proasi c3 macro library guide for more information. 3. for inbuf* driving a pll macro or cl kdly macro, the i/o will be hard-route d to the ccc; i.e., will be placed by software to a dedicated global i/o. figure 3-4 ? ccc options: global buffers with pll padn padp y pad y input lvds/lvpecl macro pll macro inbuf* macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) clock source clock conditioning output oadivhalf oadiv[4:0] oamux[2:0] dlygla[4:0] obdiv[4:0] obmux[2:0] dlyyb[4:0] dlyglb[4:0] ocdiv[4:0] ocmux[2:0] dlyyc[4:0] dlyglc[4:0] findiv[6:0] fbdiv[6:0] fbdly[4:0] fbsel[1:0] xdlysel vcosel[2:0] clka extfb gla lock glb yb glc yc powerdown oadivrst 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-8 v1.4 pll macro signal descriptions the pll macro supports two in puts and up to six outputs. table 3-3 gives a description of each signal. input clock the inputs to the input re ference clock (clka) of the pll can co me from global input pins, regular i/o pins, or internally from the core. for fusion families, the inpu t reference clock can also be from the embedded rc oscillat or or crystal oscillator. global output clocks gla (primary), glb (secondary 1) , and glc (secondary 2) are the outputs of global multiplexer 1, global multiplexer 2, and global multiplexer 3, respectively. these signal s (glx) can be used to drive the high-speed global and quadrant networks of the low-power flash devices. a global multiplexer block consists of the input ro uting for selecting the in put signal for the glx clock and the output mu ltiplexer, as well as delay elements associated with that clock. core output clocks yb and yc are known as core outputs and can be used to drive internal logic without using global network resources. this is especially helpful when global network resources must be conserved and utilized for other timing-critical paths. table 3-3 ? input and output signals of the pll block signal name i/o description clka reference clock input reference clock in put for pll core; input clock for primary output clock, gla oadivrst reset signal for the output divider a input for fusion only. oadivrst can be used when you bypass the pll core (i.e., oamux = 001). the pu rpose of the o adivrst signals is to reset the output of the final clock divider to synchronize it with the input to that divider when the pll is bypassed. the signal is active on a low to hi gh transition. the signal must be low for at least one divider input. if pll core is used, this signal is "don't care" and the internal circuitry will generate the reset signal for the synchronization purpose. oadivhalf output a division by half input for fusion only. active high . division by half feature. this feature can only be used when users bypass the pll core (i.e., oamux = 001) and the rc oscillator (rcosc) drives the clka input. this can be used to divide the 100 mhz rc oscillator by a factor of 1.5, 2.5, 3.5, 4.5 ... 14.5). refer to table 3-17 on page 3-33 for more information. extfb external feedback input allows an external signal to be co mpared to a reference clock in the pll core's phase detector. powerdown power down input active low input that selects power-down mode and disables the pll. with the powerdown signal asserted, the pll core sends 0 v signals on all of the outputs. gla primary output output prim ary output clock to respective global/quadrant clock networks glb secondary 1 output output secondary 1 output clock to respective global/quadrant clock networks yb core 1 output output core 1 output clock to local routing network glc secondary 2 output output secondary 2 output clock to respective global/quadrant clock networks yc core 2 output output core 2 output clock to local routing network lock pll lock indicator output active high signal indicating that steady-state lock has been achieved between clka and the pll feedback signal
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-9 yb and yc are identical to glb and glc, respectively , with the exception of a higher selectable final output delay. the smartgen pll wizard will configure these outputs according to user specifications and can enable thes e signals with or without the enab ling of global output clocks. the above signals can be enabled in the following output groupings in both internal and external feedback configurati ons of the static pll: ? one output ? gla only ? two outputs ? gla + (glb and/or yb) ? three outputs ? gla + (glb an d/or yb) + (glc and/or yc) pll macro block diagram as illustrated, the pll supports three distinct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b an d c global network acce ss, respectively, and/or routed to the device core (yb and yc). there are five delay elements to support phase con trol on all five outputs (gla, glb, glc, yb, and yc). there are delay elements in the feed back loop that can be used to advance the clock relative to the reference clock. the pll macro reference clock can be driven in the following ways: 1. by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hard wired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. 2. directly from the fpga core. 3. from an i/o that is routed through the fpga regula r routing fabric. in this case, users must instantiate a special macro, pllint, to diff erentiate from the hardwired i/o connection described earlier. during power-up, the pll output s will toggle around the maxi mum frequency of the voltage- controlled oscillator (vco) gear selected. toggl e frequencies can range from 40 mhz to 250 mhz. this will continue as long as the clock input (clka) is constant (high or low). this can be prevented by low assertion of the powerdown signal. the visual pll configuration in smartgen, a component of the libe ro ide and design er tools, will derive the necessary internal divider ratios based on the input frequ ency and desired output frequencies selected by the user.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-10 v1.4 smartgen also allows the user to select the variou s delays and phase shift values necessary to adjust the phases between the reference cl ock (clka) and the derived clocks (gla, glb, glc, yb, and yc). smartgen allows the user to sele ct the input clock source. smartgen automatically instantiates the special macro, pllint, when needed. global input selections low-power flash devices provide the flexibility of choosing one of the three global input pad locations available to conn ect to a ccc functional block or to a global / quadrant global network. figure 3-6 and figure 3-7 on page 3-11 show the detailed architec ture of each global input structure for 30 k gate devices and below, as well as 60 k gate devices and above, respectively. for 60 k gate devices and above ( figure 3-6 ), if the single-ended i/o standard is chosen, there is flexibility to choose one of the global input pads (the first, second, and fou rth input). on ce chosen, the other i/o locations are used as regular i/os. if the differential i/o standard is chosen, the first and second inputs are considered as paired, and the third input is paired with a regular i/o. the user then has the choice of selecting one of th e two sets to be used as the clock input source to the ccc functional block. there is also the option to allow an internal clock signal to feed the global network or the ccc functional block. a multiplexer tree selects the appropriate global input for routing to the desired location . note that the global i/o pads do not need to feed the global network; they can also be used as regular i/o pads. note: clock divider and clock multiplier blocks are not shown in this figure or in smartgen. they are automatically configured based on the user's required frequencies. figure 3-5 ? ccc with pll block pll core phase select phase select phase select gla clka glb yb glc yc programmable delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 four-phase output extfb
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-11 figure 3-6 ? clock input sources (30 k gates devices and below) notes: 1. represents the global input pins. globals have dire ct access to the clock conditioning block and are not routed via the fpga fabric. refer to user i/o naming conventions in i/o structures in igloo and proa sic3 devices . 2. instantiate the routed cloc k source input as follows: a) connect the output of a logic element to the clock input of a pll, clkdly, or clkint macro. b) do not place a clock source i/o (inbuf or inbuf_lvpecl/lvds/b-lvds/m-lvds/ddr) in a relevant global pin location. figure 3-7 ? clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint (60 k gates devices and above) routed clock (from fpga core) drives the global network directly (gla or glc) dedicated i/o pad sample pin names gec0/io37rsb1 to core + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-12 v1.4 each global buffer, as well as the pll reference cl ock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core since the architecture of the devi ces varies as size increases, th e following list details i/o types supported for globals: igloo and proasic3 ? lvds-based clock sources are available only on 250 k gate devices and above. ? 60 k and 125 k gate devices suppo rt single-ended clock sources only. ? 15 k and 30 k gate devices support these in puts for ccc only and do not contain a pll. ? nano devices: ? 10 k, 15 k, and 20 k devices do not contain plls in the cccs, and support only clkbuf and clkint. ? 60 k, 125 k, and 250 k devices support one p ll in the middle left ccc position. in the absence of the pll, this ccc can be used by clkbuf, clkint, and clkdly macros. the corner cccs support clkbuf, clkint, and clkdly. fusion ? afs600 and afs1500: all sing le-ended, differenti al, and voltage-referenced i/o standards (pro i/o). ? afs090 and afs250: all single-ended and differential i/o standards. clock sources for p ll and clkdly macros the input reference clock (clka for a pll macro, clk for a clkdly macro) can be accessed from different sources via the associated clock multiple xer tree. each ccc has the option of choosing the source of the input clock from one of the following: ? hardwired i/o ? external i/o ? core logic ? rc oscillator (fusion only) ? crystal oscillator (fusion only) the smartgen macro builder tool al lows users to easily create the pll and clkdly macros with the desired settings. actel strongl y recommends using smartgen to generate the ccc macros. hardwired i/o clock source hardwired i/o refers to global inpu t pins that are hardwired to th e multiplexer tree, which directly accesses the ccc global buffers. these global input pins have designated pin locations and are indicated with the i/o naming convention gmn ( m refers to any one of the positions where the pll core is available, and n refers to any one of the three glob al input muxes and the pin number of the associated global location, m ). choosing this option provides the benefit of directly connecting to the ccc reference clock input, which provides less delay. see figure 3-8 on page 3-13 for an example illustration of the connecti ons, shown in red. if a clkdly macro is initiated to utilize the programmable delay element of the ccc, the clock input can be placed at one of nine dedicated global input pin locations. in other words, if ha rdwired i/o is chosen as the input source, the user can decide to place the input pin in one of the gma0, gma1, gma2, gmb0, gmb1, gmb2, gmc0, gmc1, or gmc2 locations of the low-power flash de vices. when a pll macro is used to utilize the
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-13 pll core in a ccc location, the clock input of th e pll can only be connected to one of three gma* global pin locations: gma0, gma1, or gma2. external i/o clock source external i/o refers to regular i/o pins. the clock source is instantiated with one of the various inbuf options and accesses th e cccs via internal routing. the user has the option of assigning this input to any of the i/os labeled with the i/o convention iouxwbyvz . refer to user i/o naming conventions in i/o structures in igloo and proasic3 devices, and for fusion, refer to the fusion mixed-signal programmable system chip datasheet for more information . figure 3-10 gives a brief explanation of external i/o usage. choosing this option provides the freedom of selecting any user i/o location but introduces additi onal delay because the signal conn ects to the rout ed clock input through internal routing before connecting to the ccc reference clock input. for the external i/o opti on, the routed signal would be instan tiated with a pllint macro before connecting to the ccc reference cl ock input. this instantiation is conveniently done automatically by smartgen when this option is selected. acte l recommends using the smar tgen tool to generate the ccc macro. the instantiation of the pllint macr o results in the use of the routed clock input of the i/o to connect to the pll cl ock input. if not using smartgen , manually instantiate a pllint macro before the pll reference clock to indicate th at the regular i/o driving the pll reference clock should be used (see figure 3-10 on page 3-14 for an example illustration of the connec tions, shown in red). note: fusion cccs have additional sour ce selections (rcosc, xtal). figure 3-8 ? illustration of hardwired i/o (global input pins ) usage for igloo and proasic3 devices 60 k gates and larger figure 3-9 ? illustration of hardwired i/o (global input pins ) usage for igloo and proasic3 devices 30 k gates and smaller + _ pll or clkdly macro routed clock (from fpga core) gmn0 gmn1 gmn2 to core to global (or local) routing network clka pllint multiplexer tree + _ iouxwbyvz gmn* = global input pin iouxwbyvz = regular i/o pin routed clock (from the fpga core) directly drives global network (gla or glc) dedicated i/o pad sample pin names gec0/io37rsb1 to core
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-14 v1.4 in the above two op tions, the clock s ource must be instantiated with one of the various inbuf macros. the reference clock pins of the ccc functional block core macros must be driven by regular input macros (inbufs), not clock input macros. for fusion devices, the input re ference clock can also be from th e embedded rc oscillator and crystal oscillator. in this case, the ccc configurat ion is the same as the ha rdwired i/o clock source, and users are required to instanti ate the rc oscillator or crystal oscillator macro and connect its output to the input reference clock of the ccc block. figure 3-10 ? illustration of external i/o usage pll or clkdly macro routed clock (from fpga core) gmn* gmn* gmn* to core iouxwbyvz* to global (or local) routing network iouxwbyvz* clka pllint multiplexer tree + _ + _ gmn* = global input pin iouxwbyvz = regular i/o pin
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-15 core logic clock source core logic refers to internal routed ne ts. internal routed signals ac cess the ccc via the fpga core fabric. similar to the external i/o option, whenever the clock source comes internally from the core itself, the routed signal is instantiated with a pllint macro before conn ecting to the ccc clock input (see figure 3-11 for an example illustration of the connecti ons, shown in red). for fusion devices, the input re ference clock can also be from th e embedded rc oscillator and crystal oscillator. in this case, the ccc configurat ion is the same as the ha rdwired i/o clock source, and users are required to instanti ate the rc oscillator or crystal oscillator macro and connect its output to the input reference clock of the ccc block. figure 3-11 ? illustration of core logic usage pll or clkdly macro routed clock (from fpga core) gmn* gmn* gmn* to core iouxwbyvz* to global (or local) routing network from internal signals clka pllint multiplexer tree _ + _ + gmn* = global input pin iouxwbyvz = regular i/o pin
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-16 v1.4 available i/o standards global synthesis constraints the synplify ? synthesis tool, by default, allows six clocks in a de sign for fusion, igloo, and proasic3. when more than six clocks are needed in the design, a user synthe sis constraint attribute, syn_global_buffers, can be used to control the maximum number of clocks (up to 18) that can be inferred by the synthesis engine. high-fanout nets will be inferred with clock buff ers and/or internal cloc k buffers. if the design consists of ccc global buffers, they are incl uded in the count of clocks in the design. the subsections below discuss the clock input source (global buffer s with no programmable delays) and the clock conditioning functional block (global buffers with programmable delays and/or pll function) in detail. table 3-4 ? available i/o stan dards within clkbuf and clkbuf_lvds/lvpecl macros clkbuf_lvcmos5 clkbuf_lvcmos33 1 clkbuf_lvcmos25 2 clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_pcix 3 clkbuf_gtl25 2,3 clkbuf_gtl33 2,3 clkbuf_gtlp25 2,3 clkbuf_gtlp33 2,3 clkbuf_hstl_i 2,3 clkbuf_hstl_ii 2,3 clkbuf_sstl3_i 2,3 clkbuf_sstl3_ii 2,3 clkbuf_sstl2_i 2,3 clkbuf_sstl2_ii 2,3 clkbuf_lvds 4 clkbuf_lvpecl notes: 1. by default, the clkbuf macro uses 3.3 v lvttl i/o technology. for more details, refer to the igloo, fusion, and proasic3 macro library guide . 2. i/o standards only supported in proasic3e and iglooe families. 3. i/o standards only supported in the following fusion devices: afs600 and afs1500. 4. b-lvds and m-lvds standards are supported by clkbuf_lvds.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-17 device-specific layout two kinds of cccs are offered in low-power flas h devices: cccs with in tegrated plls, and cccs without integrated plls (simplified cccs). table 3-5 lists the number of cc cs in various devices. note: nano 10 k, 15 k, and 20 k offer 6 global muxes instead of cccs. table 3-5 ? number of cccs by device size and package device package cccs with integrated plls cccs without integrated plls (simplified ccc) proasic3 igloo a3pn010 agln010 all 0 2 a3pn015 agln015 all 0 2 a3pn020 agln020 all 0 2 agln060 cs81 0 6 a3pn060 agln060 all other packages 15 agln125 cs81 0 6 a3pn125 agln125 all other packages 15 agln250 cs81 0 6 a3pn250 agln250 all other packages 15 a3p015 agl015 all 0 2 a3p030 agl030/aglp030 all 0 2 agl060/aglp060 cs121/cs201 0 6 a3p060 agl060/aglp060 all other packages 15 a3p125 agl125/aglp125 all 1 5 a3p250/l agl250 all 1 5 a3p400 agl400 all 1 5 a3p600/l agl600 all 1 5 a3p1000/l agl1000 all 1 5 a3pe600 agle600 pq208 2 4 a3pe600/l all other packages 60 a3pe1500 pq208 2 4 a3pe1500 all other packages 60 a3pe3000/l pq208 2 4 a3pe3000/l agle3000 all other packages 60 fusion devices afs090 all 1 5 afs250, m1afs250 all 1 5 afs600, m7afs600, m1afs600 all 2 4 afs1500, m1afs1500 all 2 4
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-18 v1.4 this section outlines the following device inform ation: ccc features, pll core specifications, functional descri ptions, software configuration info rmation, detailed usage information, recommended board-level considerations, and other considerations concerning global networks in low-power flash devices. clock conditioning circuits with integrated plls each of the cccs with integrated plls includes the following: ? 1 pll core, which consists of a phase detector , a low-pass filter, and a four-phase voltage- controlled oscillator ? 3 global multiplexer blocks that steer signals fr om the global pads and the pll core onto the global networks ? 6 programmable delays and 1 fixed de lay for time advanc e/delay adjustments ? 5 programmable frequency divider blocks to provide frequency synthesis (automatically configured by the smartgen macro builder tool) clock conditioning circuits without integrated plls there are two types of simplified cccs without integrated plls in low-po wer flash devices. 1. the simplified ccc with programmable de lays, which is composed of the following: ? 3 global multiplexer bloc ks that steer signals from the global pads and the programmable delay elements onto the global networks ? 3 programmable delay elements to provide time delay adjustments 2. the simplified ccc (referred to as ccc-gl) without programmable delay elements, which is composed of the following: ? a global multiplexer block that steer signals from the global pads onto the global networks
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-19 ccc locations cccs located in the middle of the east and west sides of the device access the three versanet global networks on each side (six total networks), while the four cccs located in the four corners access three quadrant global networks (twelve total networks). see figure 3-12 . figure 3-12 ? global network architecture f or 60 k gate devices and above northwest quadrant global networks southeast quadrant global networks chip-wide (main) global networks 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc location a ccc location f ccc location e ccc location d ccc location c ccc location b
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-20 v1.4 the following explains the locations of the cccs in igloo and proasic3 devices: in figure 3-14 on page 3-21 through figure 3-15 on page 3-21 , cccs with integrated plls are indicated in red, and simplified cccs are indicated in yellow. there is a letter associated with each location of the ccc, in clockwise order. the uppe r left corner ccc is name d "a," the upper right is named "b," and so on. these names finish up at the middle left with letter "f." igloo and proasi c3 ccc locations in all igloo and proasic3 devices (except 10 k th rough 30 k gate devices, which do not contain plls), six cccs are located in the same positions as the iglooe and proa sic3e cccs. only one of the cccs has an integrated pll and is located in the middle of the west (middle left) side of the device. the other five cccs are simplified cccs and are located in the four corners and the middle of the east side of the device ( figure 3-13 ). note: the number and architecture of the banks are different for some devices. 10 k through 30 k gate devices do not support pll f eatures. in these devices, there are two ccc-gls at the lower corners (one at the lower right, and one at the lower left). these ccc-gls do not have programmable delays. figure 3-13 ? ccc locations in igloo and proasic3 family devices (except 10 k through 30 k gate devices) ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 a b c d e f = ccc with integrated pll = simplified ccc with programmable delay elements (no pll)
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-21 iglooe and proasic3e ccc locations iglooe and proasic3e devices have six cccs?one in each of the four corners and one each in the middle of the east and we st sides of the device ( figure 3-14 ). all six cccs are integrated with plls, except in pqfp-208 package devi ces. pqfp-208 package devices also have six cccs, of which two include plls and four are simpli fied cccs. the cccs with plls are implemented in the middle of the east and west sides of the de vice (middle right and middle left). the simplified cccs without plls are located in the four corners of the device ( figure 3-15 ). figure 3-14 ? ccc locations in iglooe an d proasic3e family device s (except pqfp-208 package) figure 3-15 ? ccc locations in proasic3e fami ly devices (pqfp-208 package) versatile ram block 4,608-bit dual-port sram or fifo block pro i/os ram block 4,608-bit dual-port sram or fifo block isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps = ccc with integrated pll ccc a b c d e f ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) b c d ccc a e f isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-22 v1.4 fusion ccc locations fusion devices have six cccs: one in each of the four corners and one each in the middle of the east and west sides of the device ( figure 3-16 and figure 3-17 ). the device can have one integrated pll in the middle of the west side of the device or two integrated plls in th e middle of the east and west sides of the device (mid dle right and middle left). figure 3-16 ? ccc locations in fusi on family devices (afs090, afs250, m1afs250) figure 3-17 ? ccc locations in fusion family devi ces (except afs090, afs250, m1afs250) ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 a b c d e f = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) b c d ccc a e f isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-23 pll core specifications pll core specifications can be found in the dc and switching characte ristics chapter of the appropriate family datasheet. loop bandwidth common design practice fo r systems with a low-noise input clock is to have plls with small loop bandwidths to reduce the effects of noise sources at the output. table 3-6 shows the pll loop bandwidth, providing a measure of the pll's ab ility to track the input clock and jitter. pll core operating principles this section briefly describes the basic principles of pll operation. the pll core is composed of a phase detector (pd), a low-pass filter (lpf), an d a four-phase voltage-co ntrolled oscillator (vco). figure 3-18 illustrates a basic single-phase pll core wi th a divider and delay in the feedback path. the pll is an electronic servo loop that phase-aligns the pd fee dback signal with the reference input. to achieve this, the pll dynamically adjusts the vco output signal according to the average phase difference between the input and feedback signals. the first element is the pd, wh ich produces a voltage proporti onal to the phase difference between its inputs. a simple exam ple of a digital phase detector is an exclusive-or gate. the second element, the lpf, extracts the average voltage from the phas e detector and applies it to the vco. this applied voltage alters the resonant fr equency of the vco, th us adjusting its output frequency. consider figure 3-18 with the feedback path bypassing the divider and delay elements. if the lpf steadily applies a voltage to the vco such that the output freque ncy is identical to the input frequency, this steady-state condition is known as lock. note that the inpu t and output phases are also identical. the pll core sets a lock outp ut signal high to in dicate this condition. should the input frequency increase slightly, the pd detects the frequency/phase difference between its reference and feedback input signals. since the pd output is proportional to the phase difference, the change causes the output from th e lpf to increase. this voltage change increases the resonant frequency of the vco and increase s the feedback frequency as a result. the pll dynamically adjusts in this manner until the pd senses two phase- identical signals and steady-state lock is achieved. the opposite (decreasing pd output signal) occurs wh en the input frequency decreases. table 3-6 ? ?3 db frequency of the pll minimum (t a = +125c, v cca = 1.4 v) ty p i c a l (t a = +25c, v cca = 1.5 v) maximum (t a = ? 55c, v cca = 1.6 v) ? 3 db frequency 15 khz 25 khz 45 khz figure 3-18 ? simplified pll core with fe edback divider and delay frequency reference input f in phase detector low-pass filter voltage controlled oscillator divide by m counter delay frequency output m f in
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-24 v1.4 now suppose the feedback divider is inserted in the feedback path. as the division factor m (shown in figure 3-19 ) is increased, the average phase differen ce increases. the average phase difference will cause the vco to increase its frequency until th e output signal is phas e-identical to the input after undergoing division. in other words, lock in both frequency and phase is achieved when the output frequency is m times the input. thus, clock division in the feedback path results in multiplication at the output. a similar argument can be made when the delay element is inserted into the feedback path. to achieve steady-state lock, the vco output signal will be delayed by the input period less the feedback delay. for periodic signals, this is equi valent to time-advancing the output clock by the feedback delay. another key parameter of a pll system is the acqu isition time. acquisition time is the amount of time it takes for the pll to ac hieve lock (i.e., phase- align the feedback si gnal with the input reference clock). for example, su ppose there is no voltage applie d to the vco, allowing it to operate at its free-running frequency. should an input reference clock suddenly appear, a lock would be established within the maximum acquisition time. functional description this section provides detailed descriptions of p ll block functionality: clock dividers and multipliers, clock delay adjustment, phase adjustm ent, and dynamic pll configuration. clock dividers and multipliers the pll block contains five programmable dividers. figure 3-19 shows a simplifi ed pll block. figure 3-19 ? pll block diagram pll core clka fixed delay d1 d2 d2 d1 d2 d1 n m u v w gla glb glc primary secondary 1 secondary 2 yb yc system delay output delay feedback delay output delay output delay output delay output delay 270 180 90 0 d1 = programmable delay type 1 d2 = programmable delay type 2
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-25 dividers n and m (the input divider and feedback divider, respectively) provide integer frequency division factors from 1 to 128. the output dividers u , v , and w provide integer di vision factors from 1 to 32. frequency scaling of the reference cloc k clka is performed acco rding to the following formulas: f gla = f clka m / (n u) ? gla primary pll output clock eq 3-1 f glb = f yb = f clka m / (n v) ? glb secondary 1 pll output clock(s) eq 3-2 f glc = f yc = f clka m / (n w) ? glc secondary 2 pll output clock(s) eq 3-3 smartgen provides a user-friendl y method of generating the configured pll netlist, which includes automatically setting the division factors to achi eve the closest possible match to the requested frequencies. since the five output clocks share the n and m dividers, the achievable output frequencies are inte rdependent and related accord ing to the foll owing formula: f gla = f glb (v / u) = f glc (w / u) eq 3-4 clock delay adjustment there are a total of seven configurable delay elements implemented in the pll architecture. two of the delays are located in the feedback path, entitled system delay and feedback delay. system delay provides a fixed delay of 2 ns (typical), and feedback delay provides se lectable delay values from 0.6 ns to 5.56 ns in 160 ps increments (typical). for plls, dela ys in the feedback path will effectively advance the output signal from the pll core with respect to the reference clock. thus, the system and feedback delays generate nega tive delay on the output clock. additionally, each of these delays can be independently bypassed if necessary. the remaining five delays perform traditional time delay and are located at each of the outputs of the pll. besides the fixed global driver delay of 0.755 ns for each of the global networks, the global multiplexer outputs (gla, glb, an d glc) each feature an addition al selectable delay value from 0.025 ns to 0.76 ns in the first st ep, and then to 5.56 ns in 160 ps increments. the additional yb and yc signals have access to a selectable delay from 0. 6 ns to 5.56 ns in 160 ps increments (typical). this is the same delay value as the clkdly macro. it is similar to clkdly, which bypasses the pll core just to take advantage of the phase adjustment option wi th the delay value. the following parameters must be taken into consideration to achieve minimum delay at the outputs (gla, glb, glc, yb, and yc) relative to the reference clock: routing delays from the pll core to ccc outputs, core output s and global network output delays, and the feedback path delay. the feedback path delay acts as a time advance of the input clock and will offset any delays introduced beyond the pll core output. the routing delays are determined from back-annotated simulation and are configuration-dependent. phase adjustment the output from the pll core can be phase-adju sted with respect to the reference input clock, clka. the user can select a 0, 90, 180, or 270 phase shift independently for each of the outputs ya, glb/yb, and glc/yc. note that each of thes e phase-adjusted signals might also undergo further frequency division and/or time adjustment via the remaining dividers and delays located at the outputs of the pll.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-26 v1.4 dynamic pll configuration the cccs can be configured both statically and dynamically. in addition to the ports available in the static ccc, th e dynamic ccc has the dynamic shift register signals that enab le dynamic reconfiguration of the ccc. with the dynamic ccc, the ports clkb and clkc are also exposed. all three clocks (clka, clkb, and cl kc) can be configured independently. the ccc block is fully configurable. the followin g two sources can act as the ccc configuration bits. flash configuration bits the flash configuration bits are the configuratio n bits associated with pr ogrammed flash switches. these bits are used when the ccc is in static co nfiguration mode. once the device is programmed, these bits cannot be modifi ed. they provide the default operating state of the ccc. dynamic shift register outputs this source does not require core reprog ramming and allows core-driven dynamic ccc reconfiguration. when the dynamic register drives the configuration bits, the user-defined core circuit takes full control over sdin, sdout, sclk , sshift, and supdate. the configuration bits can consequently be dynamically changed through shift and update operations in the serial register interface. access to the logic core is accomplished via the dynamic bi ts in the specific tiles assigned to the plls. figure 3-20 illustrates a simplified block diagram of the mux ar chitecture in the cccs. the selection between the flash configuration bits and the bits from the co nfiguration register is made using the mode signal shown in figure 3-20 . if the mode signal is logic high, the dynamic shift register configuration bits are selected. there are 81 control bits to configure the different functions of the ccc. each group of control bits is assigned a specific lo cation in the configuration shift register. for a list of the 81 configuration bits (c[80:0]) in the ccc and a description of each, refer to "pll configuration bits description" on page 3-28 . the configuration registe r can be serially loaded with the new configuration data and progra mmed into the ccc usin g the following ports: ? sdin: the configuration bits are serially loaded into a shift register thro ugh this port. the lsb of the configuration data bits should be loaded first. ? sdout: the shift register contents can be shi fted out (lsb first) thro ugh this po rt using the shift operation. ? sclk: this port should be driven by the shift clock. ? sshift: the active-high shift enable signal shou ld drive this port. the configuration data will be shifted into the shift register if this si gnal is high. once sshift goes low, the data shifting will be halted. * for fusion, bit <88:81> is also needed. figure 3-20 ? the ccc configuration mux architecture sdin sclk reset_enable sdout sshift mode supdate configuration bits dynamic shift register flash programming configuration bits <80:0>* <80> <79:0> <79:0>*
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-27 ? supdate: the supdate signal is used to conf igure the ccc with the new configuration bits when shifting is complete. to access the configuration ports of the shift regi ster (sdin, sdout, sshift, etc.), the user should instantiate the ccc macro in his design with appropriate ports. actel recommends that users choose smartgen to generate the ccc macros with the required po rts for dynamic reconfiguration. users must familiarize themselves with the architec ture of the ccc core and its input, output, and configuration ports to implement the desired de lay and output frequency in the ccc structure. figure 3-21 shows a model of the ccc with configurable blocks and switches. figure 3-21 ? ccc block control bits ? graphical representation of assignments /w d c<37:35> c<28:24> internal c<60:56> glc d c<70:66> yc clkc clkb internal c<55:51> c<23:19> c<34:32> glb d dyb /v c<44:40> c<45> c<39:38> d d (0) (1) (1) (2) c<13:7> c<6:0> /m /n clka pll core (4) (2) (7) (6) (5) c<18:14> c<31:29> c<50:46> internal gla d /u m u x a 0 270 90 180 m u x b m u x c
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-28 v1.4 loading the confi guration register the most important part of ccc dynamic configuratio n is to load the shift register properly with the configuration bits. there are different ways to access and load the co nfiguration shift register: ? jtag interface ?logic core ? specific i/o tiles jtag interface the jtag interface requires no ad ditional i/o pins. the jtag tap co ntroller is used to control the loading of the ccc configuration shift register. low-power flash devices provide a user interface macro between the jtag pins and the device core logic. this macro is called ujtag. a user should instantiate the uj tag macro in his design to access the configuration register ports via the jtag pins. for more information on ccc dynamic reconfiguration using ujtag, refer to ujtag applications in actel?s low-power flash devices. logic core if the logic core is employed, the user must design a module to provide th e configuration data and control the shifting and updating of the ccc configur ation shift register. in effect, this is a user- designed tap controller, which requ ires additional chip resources. specific i/o tiles if specific i/o tiles are used fo r configuration, the user must prov ide the external equivalent of a tap controller. this does no t require additional core re sources but does use pins. shifting the conf iguration data to enter a new configuration, all 81 bits must shift in via sdin. after all bits are shi fted, sshift must go low and supdate high to enable the new configuration. for simulation purposes, bits <71:73> and <77:80> are "don't care." the supdate signal must be low during any clock cycle where sshift is active. after supdate is asserted, it must go back to the low state until a new update is required. pll configuration bits description table 3-7 ? configuration bit descriptions for the ccc blocks config. bits signal name description <88:87> glmuxcfg [1:0] 1 ngmux configuration the configuratio n bits specify the input clocks to the ngmux (refer to table 3-16 on page 3-32 ). 2 86 ocdivhalf 1 division by half when the p ll is bypassed, the 100 mhz rc oscillator can be divided by the divider factor in table 3-17 on page 3-33 . 85 obdivhalf 1 division by half when the p ll is bypassed, the 100 mhz rc oscillator can be divided by a 0.5 factor (refer to table 3-17 on page 3-33 ). 84 oadivhalf 1 division by half when the p ll is bypassed, the 100 mhz rc oscillator can be divide d by certain 0.5 factor (refer to table 3-15 on page 3-32 ). notes: 1. the <88:81> conf iguration bits are only for the fusion dynamic ccc. 2. this value depends on the input clock source, so layo ut must complete before these bits can be set. after completing layout in designer, generate the "ccc_configuration " report by choosing tools > report > ccc_configuration . the report contains the appr opriate settings for these bits.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-29 83 rxcsel 1 clkc input selection select the clkc input clock source between rc oscillator and crystal oscillator (refer to table 3-15 on page 3-32 ). 2 82 rxbsel 1 clkb input selection select the clkb input clock source between rc oscillator and crystal oscillator (refer to table 3-15 on page 3-32 ). 2 81 rxasel 1 clka input selection select the cl ka input clock source between rc oscillator and crystal oscillator (refer to table 3-15 on page 3-32 ). 2 80 reseten reset enable enables (activ e high) the synchronization of pll output dividers after dynamic reconfiguration (supdate). the reset enable signal is read- only and should not be modified via dynamic reconfiguration. 79 dyncsel clock input c dynamic select configures clock input c to be sent to glc for dynamic control. 2 78 dynbsel clock input b dynamic select configures clock input b to be sent to glb for dynamic control. 2 77 dynasel clock input a dynamic select co nfigures clock input a for dynamic pll configuration. 2 <76:74> vcosel[2:0] vco gear control three- bit vco gear control for four frequency ranges (refer to table 3-18 on page 3-33 and table 3-19 on page 3-33 ). 73 statcsel mux select on input c mux selection for clock input c 2 72 statbsel mux select on input b mux selection for clock input b 2 71 statasel mux select on input a mux selection for clock input a 2 <70:66> dlyc[4:0] yc output delay sets the output delay value for yc. <65:61> dlyb[4:0] yb output delay sets the output delay value for yb. <60:56> dlyglc[4:0] glc output delay sets the output delay value for glc. <55:51> dlyglb[4:0] glb output delay sets the output delay value for glb. <50:46> dlygla[4:0] primary output delay primary gla output delay 45 xdlysel system delay select when se lected, inserts system delay in the feedback path in figure 3-19 on page 3-24 . <44:40> fbdly[4:0] feedback delay sets the feedback delay value for the feedback element in figure 3-19 on page 3-24 . <39:38> fbsel[1:0] primary feedback delay select co ntrols the feedback mux: no delay, include programmable delay element, or use external feedback. <37:35> ocmux[2:0] secondary 2 ou tput select selects from the vc o?s four phase outputs for glc/yc. table 3-7 ? configuration bit descriptions for the ccc blocks (continued) config. bits signal name description notes: 1. the <88:81> conf iguration bits are only for the fusion dynamic ccc. 2. this value depends on the input clock source, so layo ut must complete before these bits can be set. after completing layout in designer, generate the "ccc_configuration " report by choosing tools > report > ccc_configuration . the report contains the appr opriate settings for these bits.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-30 v1.4 table 3-8 to table 3-14 on page 3-32 provide descriptions of th e configuration data for the configuration bits. <34:32> obmux[2:0] secondary 1 ou tput select selects from the vc o?s four phase outputs for glb/yb. <31:29> oamux[2:0] gla output select selec ts from the vco?s four phase outputs for gla. <28:24> ocdiv[4:0] secondar y 2 output divider sets the divide r value for the glc/yc outputs. also known as divider w in figure 3-19 on page 3-24 . the divider value will be ocdiv[4:0] + 1. <23:19> obdiv[4:0] secondar y 1 output divider sets the divide r value for the glb/yb outputs. also known as divider v in figure 3-19 on page 3-24 . the divider value will be obdiv[4:0] + 1. <18:14> oadiv[4:0] primary output divider sets the divider va lue for the gla output. also known as divider u in figure 3-19 on page 3-24 . the divider value will be oadiv[4:0] + 1. <13:7> fbdiv[6:0] feedback divider sets the divider value for the pll core feedback. also known as divider m in figure 3-19 on page 3-24 . the divider value will be fbdiv[6:0] + 1. <6:0> findiv[6:0] input divider input clock divider (/n). sets the divider value for the input delay on clka. the divider value will be findiv[6:0] + 1. table 3-7 ? configuration bit descriptions for the ccc blocks (continued) config. bits signal name description notes: 1. the <88:81> conf iguration bits are only for the fusion dynamic ccc. 2. this value depends on the input clock source, so layo ut must complete before these bits can be set. after completing layout in designer, generate the "ccc_configuration " report by choosing tools > report > ccc_configuration . the report contains the appr opriate settings for these bits. table 3-8 ? input clock divider, findiv[6:0] (/n) findiv<6:0> state divis or new frequency factor 0 1 1.00000 1 2 0.50000 ? ? ? 127 128 0.0078125 table 3-9 ? feedback clock divider, fbdiv[6:0] (/m) fbdiv<6:0> state divisor new frequency factor 011 122 ? ? ? 127 128 128
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-31 table 3-10 ? output frequency dividers a output divider, oadiv <4:0> (/u); b output divider, obdiv <4:0> (/v); c output divider, ocdiv <4:0> (/w) oadiv<4:0>; obdiv<4:0>; cdiv<4:0> state divisor new frequency factor 0 1 1.00000 1 2 0.50000 ? ? ? 31 32 0.03125 table 3-11 ? muxa, muxb, muxc oamux<2:0>; obmux<2:0>; ocmux<2:0> state mux input selected 0 none. six-input mux and pll are bypassed. clock passes only through global mux and goes directly into hc ribs. 1 not available 2 pll feedback delay line output 3not used 4 pll vco 0 phase shift 5 pll vco 90 phase shift 6 pll vco 180 phase shift 7 pll vco 270 phase shift table 3-12 ? 2-bit feedback mux fbsel<1:0> state mux input selected 0 ground. used for power-down mode in power-down logic block. 1 pll vco 0 phase shift 2 pll delayed vco 0 phase shift 3n/a table 3-13 ? programmable delay selection for feedback delay and secondary core output delays fbdly<4:0>; dlyyb<4:0>; dlyyc<4:0> state delay value 0 typical delay = 600 ps 1 typical delay = 760 ps 2 typical delay = 920 ps ? ? 31 typical delay = 5.56 ns
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-32 v1.4 table 3-14 ? programmable delay selection fo r global clock output delays dlygla<4:0>; dlyglb<4:0>; dlyglc<4:0> state delay value 0 typical delay = 225 ps 1 typical delay = 760 ps 2 typical delay = 920 ps ? ? 31 typical delay = 5.56 ns table 3-15 ? fusion dynamic ccc clock source selection rxasel dynasel source of clka 1 0 rc oscillator 1 1 crystal oscillator rxbsel dynbsel source of clkb 1 0 rc oscillator 1 1 crystal oscillator rxbsel dyncsel source of clkc 1 0 rc oscillator 1 1 crystal oscillator table 3-16 ? fusion dynamic ccc ngmux configuration glmuxcfg<1:0> ngmux select signal supported input clocks to ngmux 00 0 gla 1glc 01 0 gla 1glint 10 0 glc 1glint
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-33 table 3-17 ? fusion dynamic ccc division by half configuration oadivhalf / obdivhalf / ocdivhalf oadiv<4:0> / obdiv<4:0> / ocdiv<4:0> (in decimal) divider factor input clock frequency output clock frequency (mhz) 1 2 1.5 100 mhz rc oscillator 66.7 4 2.5 40.0 6 3.5 28.6 8 4.5 22.2 10 5.5 18.2 12 6.5 15.4 14 7.5 13.3 16 8.5 11.8 18 9.5 10.5 20 10.5 9.5 22 11.5 8.7 24 12.5 8.0 26 13.5 7.4 28 14.5 6.9 0 0?31 1?32 other clock sources depends on other divider settings table 3-18 ? configuration bit <76: 75> / vcosel<2:1> selection for all families voltage vcosel[2:1] 00 01 10 11 min. (mhz) max. (mhz) min. (mhz) max. (mhz) min. (mhz) max. (mhz) min. (mhz) max. (mhz) igloo and igloo plus 1.2 v 5% 24 35 30 70 60 140 135 160 1.5 v 5% 24 43.75 30 87.5 60 175 135 250 proasic3l, rt proasic3, and military proasic3/l 1.2 v 5% 24 35 30 70 60 140 135 250 1.5 v 5% 24 43.75 30 70 60 175 135 350 proasic3 and fusion 1.5 v 5% 24 43.75 33.75 87.5 67.5 175 135 350 table 3-19 ? configuration bit <74> / vcose l<0> selection for all families vcosel[0] description 0 fast pll lock acquisition time with high tracking jitter. refer to the co rresponding datasheet for specific value and definition. 1 slow pll lock acquisition time with low tracking jitter. refer to the co rresponding datasheet for specific value and definition.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-34 v1.4 software configuration smartgen automatically generates the desired ccc functional block by configuring the control bits, and allows the user to select two ccc modes: static pll and delayed clock (clkdly). static pll configuration the newly implemented visual p ll configuration wizard feature provides the user a quick and easy way to configure the pll with the desired settings ( figure 3-22 ). the user can invoke smartgen to set the parameters and generate the netlist file with the appropriate flash configuration bits set for the cccs. as mentioned in "pll macro block diagram" on page 3-9 , the input reference clock clka can be configured to be driven by hardwired i/o, external i/o, or core logic. the user enters the desired settings fo r all the parameters (output frequency, output selection, output phase adjustment, clock delay, feed back delay, and system delay). notice that the actual values (divider values, ou tput frequency, delay values, and phase) are shown to aid the user in reaching the desired design fre quency in real time. these values are typical-case data. best- and worst-case data can be observed through static timing analysis in smar ttime within designer. for dynamic configuration, the ccc parameters ar e defined using either the external jtag port or an internally defined serial interface via the bu ilt-in dynamic shift regist er. this feature provides the ability to compensate for chan ges in the external environment. figure 3-22 ? visual pll conf iguration wizard input selection fixed system delay feedback selection (feedback mux) vco clock frequency programmable output delay elements output selection
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-35 feedback configuration the pll provides both internal and external feedback delays. depending on the configuration, various combinations of feedback delays can be achieved. internal feedback configuration this configuration essentially sets the feedback multiplexer to route the vco output of the pll core as the input to the feedback of the pll. the feedback signal can be processed with the fixed system and the adju stable feedback delay, as shown in figure 3-23 . the dividers are automatically configured by smartgen based on the user input. indicated below is the system delay pull-down me nu. the system delay can be bypassed by setting it to 0. when set, it adds a 2 ns delay to the feedback path (wh ich results in delay advancement of the output clock by 2 ns). figure 3-24 shows the controllable feedback delay. if set properly in conjunction with the fixed system delay, the total output dela y can be advanced significantly. figure 3-23 ? internal feedback with selectable system delay figure 3-24 ? internal feedback with se lectable feedback delay
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-36 v1.4 external feedback configuration for certain applications, such as those requiring generation of pcb clocks that must be matched with existing board delays, it is useful to im plement an external feedback, extfb. the phase detector of the pll core will receive clka and extfb as inputs. extfb may be processed by the fixed system delay element as well as the m divider element. the extf b option is currently not supported. after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen gives the option of saving session results and messages in a log file: **************** macro parameters **************** name : test_pll family : proasic3e output format : vhdl type : static pll input freq(mhz) : 10.000 clka source : hardwired i/o feedback delay value index : 1 feedback mux select : 2 xdly mux select : no primary freq(mhz) : 33.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 66.000 use glb : yes use yb : yes glb delay value index : 1 yb delay value index : 1 secondary1 phaseshift : 0 secondary1 mux select : 4 secondary2 freq(mhz) : 101.000 use glc : yes use yc : no glc delay value index : 1 yc delay value index : 1 secondary2 phaseshift : 0 secondary2 mux select : 4 ? ? ? primary clock frequency 33.333 primary clock phase shift 0.000 primary clock output delay from clka 0.180 secondary1 clock frequency 66.667 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clka 0.180 secondary1 clock core output delay from clka 0.625 secondary2 clock frequency 100.000 secondary2 clock phase shift 0.000 secondary2 clock global output delay from clka 0.180 below is an example verilog hdl description of a legal pll core configuration generated by smartgen: module test_pll(powerdown,clka,lock,gla);
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-37 input powerdown, clka; output lock, gla; wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); pll core(.clka(clka), .extfb(gnd), .powerdown(powerdown), .gla(gla), .lock(lock), .glb(), .yb(), .glc(), .yc(), .oadiv0(gnd), .oadiv1(gnd), .oadiv2(gnd), .oadiv3(gnd), .oadiv4(gnd), .oamux0(gnd), .oamux1(gnd), .oamux2(vcc), .dlygla0(gnd), .dlygla1(gnd), .dlygla2(gnd), .dlygla3(gnd) , .dlygla4(gnd), .obdiv0(gnd), .obdiv1(gnd), .obdiv2(gnd), .obdiv3(gnd), .obdiv4(gnd), .obmux0(gnd), .obmux1(gnd), .obmux2(gnd), .dlyyb0(gnd), .dlyyb1(gnd), .dlyyb2(gnd), .dlyyb3(gnd), .dlyyb4(gnd), .dlyglb0(gnd), .dlyglb1(gnd), .dlyglb2(gnd), .dlyglb3(gnd), .dlyglb4(gnd), .ocdiv0(gnd), .ocdiv1(gnd), .ocdiv2(gnd), .ocdiv3(gnd), .ocdiv4(gnd), .ocmux0(gnd), .ocmux1(gnd), .ocmux2(gnd), .dlyyc0(gnd), .dlyyc1(gnd), .dlyyc2(gnd), .dlyyc3(gnd), .dlyyc4(gnd), .dlyglc0(gnd), .dlyglc1(gnd), .dlyglc2(gnd), .dlyglc3(gnd) , .dlyglc4(gnd), .findiv0(vcc), .findiv1(gnd), .findiv2( vcc), .findiv3(gnd), .findiv4(gnd), .findiv5(gnd), .findiv6(gnd), .fbdiv0(vcc), .fbdiv1(gnd), .fbdiv2(vcc), .fbdiv3(gnd), .fbdiv4(gnd), .fbdiv5(gnd), .fbdiv6(gnd), .fbdly0(gnd), .fbdly1(gnd), .fbdly2(gnd), .fbdly3(gnd), .fbdly4(gnd), .fbsel0(vcc), .fbsel1(gnd), .xdlysel(gnd), .vcosel0(gnd), .vcosel1(gnd), .vcosel2(gnd)); defparam core.vcofrequency = 33.000; endmodule the "pll configuration bits descri ption" section on page 3-28 provides descriptions of the pll configuration bits for completeness. the configuration bits are shown as busses only for purposes of illustration. they wi ll actually be broken up into individu al pins in compilati on libraries and all simulation models. for example, the fbsel[1:0] bus will actually appear as pins fbsel1 and fbsel0. the setting of these select lines for the static pll configuration is performed by the software and is completely transpar ent to the user.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-38 v1.4 dynamic pll configuration to generate a dynamically reconfigur able ccc, the user should select dynamic ccc in the configuration section of the smartgen gui ( figure 3-25 ). this will ge nerate both the ccc core and the configuration shift re gister / control bit mux. even if dynamic configuration is selected in smartgen, the user must still specify the static configuration data for the ccc ( figure 3-26 ). the specified static conf iguration is used whenever the mode signal is set to low and the ccc is requ ired to function in th e static mode. the static configuration data can be used as the default behavior of the ccc where required. figure 3-25 ? smartgen gui figure 3-26 ? dynamic ccc configuration in smartgen
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-39 when smartgen is used to define the configuration that will be sh ifted in via the serial interface, smartgen prints out the values of the 81 configurat ion bits. for ease of use, several configuration bits are automatically inferred by smartgen when the dynamic pll core is generated; however, <71:73> (statasel, statbsel, statcsel) and <7 7:79> (dynasel, dynbsel, dyncsel) depend on the input clock source of the corresponding cc c. users must first run layout in designer to determine the exact setting for these ports. after layout is complete, generate the "ccc_configuration" re port by choosing to o l s > reports > ccc_configuration in the designer software. refer to "pll configuration bits description" on page 3-28 for descriptions of the pll configuration bits. for si mulation purposes, bits <71:73> and <78:80> are "don't care." therefore, it is strongly suggested that smartgen be used to generate the correct configuration bit settings for the dynamic pll core. after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen gives the option of saving session results and messages in a log file: **************** macro parameters **************** name : dyn_pll_hardio family : proasic3e output format : verilog type : dynamic ccc input freq(mhz) : 30.000 clka source : hardwired i/o feedback delay value index : 1 feedback mux select : 1 xdly mux select : no primary freq(mhz) : 33.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 40.000 use glb : yes use yb : no glb delay value index : 1 yb delay value index : 1 secondary1 phaseshift : 0 secondary1 mux select : 0 secondary1 input freq(mhz) : 40.000 clkb source : hardwired i/o secondary2 freq(mhz) : 50.000 use glc : yes use yc : no glc delay value index : 1 yc delay value index : 1 secondary2 phaseshift : 0 secondary2 mux select : 0 secondary2 input freq(mhz) : 50.000 clkc source : hardwired i/o configuration bits: findiv[6:0] 0000101 fbdiv[6:0] 0100000 oadiv[4:0] 00100 obdiv[4:0] 00000 ocdiv[4:0] 00000 oamux[2:0] 100 obmux[2:0] 000 ocmux[2:0] 000 fbsel[1:0] 01 fbdly[4:0] 00000 xdlysel 0 dlygla[4:0] 00000
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-40 v1.4 dlyglb[4:0] 00000 dlyglc[4:0] 00000 dlyyb[4:0] 00000 dlyyc[4:0] 00000 vcosel[2:0] 100 primary clock frequency 33.000 primary clock phase shift 0.000 primary clock output delay from clka 1.695 secondary1 clock frequency 40.000 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clkb 0.200 secondary2 clock frequency 50.000 secondary2 clock phase shift 0.000 secondary2 clock global output delay from clkc 0.200 ###################################### # dynamic stream data ###################################### -------------------------------------- |name |sdin |value |type | -------------------------------------- |findiv |[6:0] |0000101 |edit | |fbdiv |[13:7] |0100000 |edit | |oadiv |[18:14] |00100 |edit | |obdiv |[23:19] |00000 |edit | |ocdiv |[28:24] |00000 |edit | |oamux |[31:29] |100 |edit | |obmux |[34:32] |000 |edit | |ocmux |[37:35] |000 |edit | |fbsel |[39:38] |01 |edit | |fbdly |[44:40] |00000 |edit | |xdlysel |[45] |0 |edit | |dlygla |[50:46] |00000 |edit | |dlyglb |[55:51] |00000 |edit | |dlyglc |[60:56] |00000 |edit | |dlyyb |[65:61] |00000 |edit | |dlyyc |[70:66] |00000 |edit | |statasel|[71] |x |masked | |statbsel|[72] |x |masked | |statcsel|[73] |x |masked | |vcosel |[76:74] |100 |edit | |dynasel |[77] |x |masked | |dynbsel |[78] |x |masked | |dyncsel |[79] |x |masked | |reseten |[80] |1 |readonly | below is the resultant verilog hdl description of a legal dynamic pll core configuration generated by smartgen: module dyn_pll_macro(powerdown, clka, lock, gla, glb, glc, sdin, sclk, sshift, supdate, mode, sdout, clkb, clkc); input powerdown, clka; output lock, gla, glb, glc; input sdin, sclk, sshift, supdate, mode; output sdout; input clkb, clkc; wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd));
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-41 dynccc core(.clka(clka), .extfb(gnd), .powerdown(powerdown), .gla(gla), .lock(lock), .clkb(clkb), .glb(glb), .yb(), .clkc(clkc), .glc(glc), .yc(), .sdin(sdin), .sclk(sclk), .sshift(sshift), .supdate(supdate), .mode(mode), .sdout(sdout), .oadiv0(gnd), .oadiv1(gnd), .oadiv2(vcc), .oadiv3(gnd), .oadiv4(gnd), .oamux0(gnd), .oamux1(gnd), .oamux2(vcc), .dlygla0(gnd), .dlygla1(gnd), .dlygla2(gnd), .dlygla3(gnd), .dlygla4(gnd), .obdiv0(gnd), .obdiv1(gnd), .obdiv2(gnd), .obdiv3(gnd), .obdiv4(gnd), .obmux0(gnd), .obmux1(gnd), .obmux2(gnd), .dlyyb0(gnd), .dlyyb1(gnd), .dlyyb2(gnd), .dlyyb3(gnd), .dlyyb4(gnd), .dlyglb0(gnd), .dlyglb1(gnd), .dlyglb2(gnd), .dlyglb3(gnd), .dlyglb4(gnd), .ocdiv0(gnd), .ocdiv1(gnd), .ocdiv2(gnd), .ocdiv3(gnd), .ocdiv4(gnd), .ocmux0(gnd), .ocmux1(gnd), .ocmux2(gnd), .dlyyc0(gnd), .dlyyc1(gnd), .dlyyc2(gnd), .dlyyc3(gnd), .dlyyc4(gnd), .dlyglc0(gnd), .dlyglc1(gnd), .dlyglc2(gnd), .dlyglc3(gnd), .dlyglc4(gnd), .findiv0(vcc), .findiv1(gnd), .findiv2(vcc), .findiv3(gnd), .findiv4(gnd), .findiv5(gnd), .findiv6(gnd), .fbdiv0(gnd), .fbdiv1(gnd), .fbdiv2(gnd), .fbdiv3(gnd), .fbdiv4(gnd), .fbdiv5(vcc), .fbdiv6(gnd), .fbdly0(gnd), .fbdly1(gnd), .fbdly2(gnd), .fbdly3(gnd), .fbdly4(gnd), .fbsel0(vcc), .fbsel1(gnd), .xdlysel(gnd), .vcosel0(gnd), .vcosel1(gnd), .vcosel2(vcc)); defparam core.vcofrequency = 165.000; endmodule delayed clock configuration the clkdly macro can be generated with the desi red delay and input clock source (hardwired i/o, external i/o, or core logic), as in figure 3-27 . after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen gives the option of saving session results and messages in a log file: **************** macro parameters **************** name : delay_macro family : proasic3 output format : verilog type : delayed clock delay index : 2 clka source : hardwired i/o total clock delay = 0.935 ns. the resultant clkdly macro verilog netlist is as follows: module delay_macro(gl,clk); output gl; input clk; figure 3-27 ? delayed clock configuration dialog box
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-42 v1.4 wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); clkdly inst1(.clk(clk), .gl(gl), .dlygl0(vcc), .dlygl1(gnd), .dlygl2(vcc), .dlygl3(gnd), .dlygl4(gnd)); endmodule detailed usage information clock frequency synthesis deriving clocks of various fre quencies from a single reference clock is known as frequency synthesis. the pll has an input frequency range from 1.5 to 350 mh z. this frequency is automatically divided down to a range between 1.5 mhz and 5.5 mhz by input dividers (not shown in figure 3-18 on page 3-23 ) between pll macro inputs and pll phase detector inputs. the vco output is capable of an output range from 24 to 350 mhz. with dividers befo re the input to the pll core and following the vc o outputs, the vco output frequency can be divided to provide the final frequency range from 0.75 to 350 mhz. using smar tgen, the dividers are automatically set to achieve the closest possib le matches to the specified output frequencies. users should be cautious when selecting the de sired pll input and output frequencies and the i/o buffer standard used to connect to the pll input and output clocks. depending on the i/o standards used for the pll input and output cloc ks, the i/o frequencies have different maximum limits. refer to the fami ly datasheets for specifications of maximum i/o frequencies for supported i/o standards. desired p ll input or output frequencies will not be achieved if the selected frequencies are higher than the maximum i/o frequencies allowed by the selected i/o standards. users should be careful when selecting the i/o standards used for pll in put and output clocks. performing post-layout simulation ca n help detect this type of error, which will be identified with pulse width violation errors. use rs are strongly encouraged to pe rform post-layout simulation to ensure the i/o standard used can provide the desi red pll input or output frequencies. users can also choose to cascade p lls together to achieve the high frequ encies needed for their applications. details of cascading plls are discussed in the "cascading cccs" section on page 3-47 . in smartgen, the actual generated frequency (under typical operating conditions) will be displayed beside the requested output frequency value. th is provides the ability to determine the exact frequency that can be generated by smartgen, in real time. the log file generated by smartgen is a useful tool in determining how closely th e requested clock frequencies match the user specifications. for example, assume a user sp ecifies 101 mhz as one of the secondary output frequencies. if the best output frequency that could be achi eved were 100 mhz, the log file generated by smartgen would indicate the actual generated frequency. simulation verification the integration of the generated pll and clkdly modules is similar to any vhdl component or verilog module instantiation in a larger design; i. e., there is no special re quirement that users need to take into account to successf ully synthesize their designs. for simulation purposes, users need to refer to the vital or verilog library that includes the functional descript ion and associated timing parameters. refer to the software tools section of the actel website to obtain the family simulation libraries. if actel desi gner is installed, these libraries are stored in the following locations: \lib\vtl\95\proasic3.vhd \lib\vtl\95\proasic3e.vhd \lib\vlog\proasic3.v \lib\vlog\proasic3e.v
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-43 for libero ide users, there is no need to compil e the simulation libraries, as they are conveniently pre-compiled in the model sim ? actel simulation tool. the following is an example of a pll configuratio n utilizing the clock frequency synthesis and clock delay adjustment features. the ste ps include generating the pll core with smartgen, performing simulation for verifi cation with model sim , and performing stat ic timing analysis with smarttime in designer. parameters of the example pll configuration: input frequency ? 20 mhz primary output requirement ? 20 mhz with clock advancement of 3.02 ns secondary 1 output requirement ? 40 mhz with clock delay of 2.515 ns figure 3-28 shows the smartgen settings. notice that the overall delays are calculated automatically, allowing the user to adjust the delay elements appropriately to obtain the desired delays. after confirming the correct settings, generate a structural netlist of th e pll and verify pll core settings by checking the log file: name : test_pll_delays family : proasic3e output format : vhdl type : static pll input freq(mhz) : 20.000 clka source : hardwired i/o feedback delay value index : 21 feedback mux select : 2 xdly mux select : no primary freq(mhz) : 20.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 40.000 use glb : yes use yb : no figure 3-28 ? smartgen settings
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-44 v1.4 ? ? ? primary clock frequency 20.000 primary clock phase shift 0.000 primary clock output delay from clka -3.020 secondary1 clock frequency 40.000 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clka 2.515 next, perform simulation in model sim to verify the correct delays. figure 3-29 shows the simulation results. the delay values match those reported in the smartgen pll wizard. the timing can also be analyzed using smarttim e in designer. the user should import the synthesized netlist to designer, perform compile and layout, and then invoke smarttime. go to tools > options and change the maximum delay operating conditions to typical case . then expand the clock-to-out paths of gla and glb and the in dividual components of the path delays are shown. the path of gla is shown in figure 3-30 on page 3-45 displaying the sa me delay value. figure 3-29 ? model sim simulation results primary clock output time advancement from clka secondary1 clock global output delay from clka
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-45 place-and-route stage considerations several considerations must be noted to properly place the ccc macros for layout. for cccs with clock inputs configured with the hardwired i/o?driven option: ? pll macros must have the cl ock input pad coming from one of the gma* locations. ? clkdly macros must have the clock input pad coming from one of the global i/os. if a pll with a hardwired i/o in put is used at a ccc location and a hardwired i/o?driven clkdly macro is used at the same ccc location, the clock input of the clkdly macro must be chosen from one of the gmb* or gmc* pin locations. if the pll is not used or is an external i/o?driven or core logic?driven pll, the clock input of the clkd ly macro can be sourced from the gma*, gmb*, or gmc* pin locations. for cccs with clock inputs configured with the ex ternal i/o?driven option, the clock input pad can be assigned to any regular i/o location (io*** ***** pins). note that sinc e global i/o pins can also be used as regular i/os, regardle ss of ccc function (clkdly or pll), clock inputs can also be placed in any of these i/o locations. by default, the designer layout engine will place global nets in the design at one of the six chip globals. when the number of glob als in the design is greater than six, the designer layout engine will automatically assign addition al globals to the quadrant global networks of the low-power flash devices. if the user wishes to decide which global signals should be assigned to chip globals (six available) and which to the quadrant globals (three per quadrant for a total of 12 available), the assignment can be achieved with pineditor, chipplanner, or by importing a placement figure 3-30 ? static timing analysis using smarttime
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-46 v1.4 constraint file. layout will fail if the global assignments are not allocated properly. see the "physical constraints for quadrant clocks" section for information on assi gning global signals to the quadrant clock networks. promoted global signals will be instantiated with clkint macros to drive these signals onto the global network. this is automatically done by designer when the au to-promotion option is selected. if the user wishes to as sign the signals to th e quadrant globals inst ead of the default chip globals, this can done by using chipplanner, by de claring a physical design constraint (pdc), or by importing a pdc file. physical constraints for quadrant clocks if it is necessary to promote global clocks (clkbuf, clkint, pll, clkdly) to quadrant clocks, the user can define pdcs to execute the promotion. pdcs can be created using pdc commands (pre- compile) or the multiview naviga tor (mvn) interface (post-compil e). the advantag e of using the pdc flow over the mvn flow is that the compile st age is able to automati cally promote any regular net to a global net befo re assigning it to a quadrant. there are three options to place a quadrant clock using pdc commands: ? place a clock core (not hardwired to an i/o) into a quadrant clock location. ? place a clock core (hardwired to an i/o) in to an i/o location (set_io) or an i/o module location (set_location) that dr ives a quadrant clock location. ? assign a net driven by a regular net or a cloc k net to a quadrant clock using the following command: assign_local_clock -net -type quadrant where is the name of the net assigned to the local user clock region. defines which quadrant the net should be assigned to. quadrant clock regions are defined as ul (upper left), ur (upper right), ll (low er left), and lr (lower right). note: if the net is a regular net, the software inserts a clkint buffer on the net. for example: assign_local_clock -net localreset -type quadrant ur keep in mind the following when placing quadrant clocks using multiview navigator: hardwired i/o?driven cccs ? find the associated cl ock input port under th e ports tab, and place the input port at one of the gmn* locations using pineditor or i/o attribute editor, as shown in figure 3-31 . figure 3-31 ? port assignment for a ccc with hardwired i/o clock input
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-47 ? use quadrant global region assignments by finding the clock net as sociated with the ccc macro under the nets tab and creating a quadra nt global region for the net, as shown in figure 3-32 . external i/o?driven cccs the above-mentioned recommendation for proper layout techniques wi ll ensure the correct assignment. it is possible that, es pecially with external i/o?driv en ccc macros, placement of the ccc macro in a desired location may not be achieved. for example, assigning an input port of an external i/o?driven ccc near a particular ccc lo cation does not guarante e global assignments to the desired location. this is because the clock inputs of external i/o?driven cccs can be assigned to any i/o location; therefore, it is possible that th e ccc connected to the clock input will be routed to a location other than the one cl osest to the i/o location, depend ing on resource availability and placement constraints. clock placer the clock placer is a placement en gine for low-power flash devices that places global signals on the chip global and quadrant global networks. based on the clock assignment constraints for the chip global and quadrant global clocks, it will try to satisfy all constraints, as well as creating quadrant clock regions when necessary. if th e clock placer fails to create th e quadrant clock regions for the global signals, it will repo rt an error and stop layout. the user must ensure that the co nstraints set to promote clock sign als to quadrant global networks are valid. cascading cccs the cccs in low-power flash devices can be cascaded. cascading cccs can help achieve more accurate pll output frequency resu lts than those achievable with a single ccc. in addition, this technique is useful when the user application requires the output clock of the pll to be a multiple of the reference clock by an integer greater than the maximum feedback divider value of the pll (divide by 128) to achieve the desired frequency. for example, the user application may requir e a 280 mhz output clock using a 2 mhz input reference clock, as shown in figure 3-33 on page 3-48 . figure 3-32 ? quadrant clock assignment for a global net
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-48 v1.4 using internal feedback, we know from eq 3-1 on page 3-25 that the maximum achievable output frequency from the primary output is f gla = f clka m / (n u) = 2 mhz 128 / (1 1) = 256 mhz eq 3-5 figure 3-34 shows the settings of the initial pll. when configuring the initial pll, specify the input to be either hardwired i/o?driven or external i/o?driven. this generates a netlist with the initial pll routed from an i/o. do not sp ecify the input to be core logi c?driven, as this prohibits the connection from the i/o pin to the input of the pll. a second pll can be connected serially to achieve the required frequency. eq 3-1 on page 3-25 to eq 3-3 on page 3-25 are extended as follows: f gla2 = f gla m 2 / (n 2 u 2 ) = f clka1 m 1 m 2 / (n 1 u 1 n 2 u 2 ) ? primary pll output clock eq 3-6 f glb2 = f yb2 = f clka1 m 1 m 2 / (n 1 n 2 v 1 v 2 ) ? secondary 1 pll output clock(s) eq 3-7 f glc2 = f yc2 = f clka1 m 1 m 2 / (n 1 n 2 w 1 w 2 ) ? secondary 2 pll output clock(s) eq 3-8 in the example, the final output frequency (f output ) from the primary output of the second pll will be as follows ( eq 3-9 ): f output = f gla2 = f gla m 2 / (n 2 u 2 ) = 256 mhz 70 / (64 1) = 280 mhz eq 3-9 figure 3-35 on page 3-49 shows the settings of the second p ll. when configuring the second pll (or any subsequent-stage plls), sp ecify the input to be core logic? driven. this gene rates a netlist with the second pll routed internally from the co re. do not specify the in put to be hardwired i/o? driven or external i/o?driven, as these options prohibit the connection from the output of the first pll to the input of the second pll. figure 3-33 ? cascade pll configuration figure 3-34 ? first-stage pll showing input of 2 mhz and output of 256 mhz
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-49 figure 3-36 shows the simulation results, where the first pll?s outp ut period is 3.9 ns (~256 mhz), and the stage 2 (final) output period is 3.56 ns (~280 mhz). figure 3-35 ? second-stage pll showing input of 256 mhz from first stage and final output of 280 mhz figure 3-36 ? model sim simulation results stage 1 output clock period stage 2 output clock period
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-50 v1.4 recommended board-level considerations the power to the pll core is supplied by v ccpla/b/c/d/e/f (v ccplx) , and the associated ground connections are supplied by v compla/b/c/d/e/f (v complx ). when the plls are not used, the actel designer place-and-route tool automatically disables the unused plls to lower power consumption. the user should tie unused v ccplx and v complx pins to ground. optionally, the pll can be turned on/off during normal devi ce operation via the powerdown port (see table 3-3 on page 3-8 ). pll power supply decoupling scheme the pll core is designed to tole rate noise levels on the pll po wer supply as specified in the datasheets. when operated within the noise limits, the pll will meet the ou tput peak-to-peak jitter specifications specified in the datasheets. user applications should al ways ensure the pll power supply is powered from a no ise-free or low-no ise power source. however, in situations where the pll power supply noise level is higher th an the tolerable limits, various decoupling schemes can be designed to suppress noise to th e pll power supply. an example is provided in figure 3-37 . the v ccplx and v complx pins correspond to the pll analog power supply and ground. actel strongly recommends that tw o ceramic capacitors (10 nf in parallel with 100 nf) be placed close to the power pins (less than 1 inch away ). a third generic 10 f electrolytic capacitor is recommended for low-frequency noise and should be placed farther away due to its large physical size. actel recommends that a 6.8 h inductor be placed between the supply source and the capacitors to filter out any low-/medium- and hi gh-frequency noise. in addition, the pcb layers should be controlled so the v ccplx and v complx planes have the minimum separation possible, thus generating a good-quality rf capacitor. for more recommendations, refer to the board-level considerations application note. recommended 100 nf capacitor: ? producer bc components, type x7r, 100 nf, 16 v ? bc components part number: 0603b104k160bt ? digi-key part number: bc1254ct-nd ? digi-key part number: bc1254tr-nd recommended 10 nf capacitor: ? surface-mount ceramic capacitor ? producer bc components, type x7r, 10 nf, 50 v ? bc components part number: 0603b103k500bt ? digi-key part number: bc1252ct-nd ? digi-key part number: bc1252tr-nd figure 3-37 ? decoupling scheme for one pll (should be replicated for each pll used) igloo/e or proasic3/e device power supply v ccplx v complx 10 nf 100 nf 10 f
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-51 conclusion the advanced cccs of the igloo and proasic3 devi ces are ideal for applicat ions requiring precise clock management. they integrat e easily with the inte rnal low-skew clock networks and provide flexible frequency synthesi s, clock deskewing, and/or time-shifting operations. related documents application notes board-level considerations http://www.actel.com/documents/boardlevelcons_an.pdf handbook documents ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf user i/o naming conventions in i/o stru ctures in igloo an d proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf user?s guides igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-006-4 revised december 2008
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 3-52 v1.4 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.4) page v1.3 (october 2008) the "ccc support in actel?s flash devices" section was updated to include igloo nano and proasic3 nano devices. 3-3 figure 3-2 ccc options: global buffers with no programmable delay was revised to add the clkbibuf macro. 3-4 the description of the reference clock was revised in table 3-2 input and output description of the clkdly macro . 3-5 figure 3-6 clock input sources (30 k gates devices and below) is new. figure 3-7 clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint (60 k gates devices and above) applies to 60 k gate devices and above. 3-11 the "igloo and proasic3" section was updated to include information for igloo nano devices. 3-12 a note regarding fusion cccs was added to figure 3-8 illustration of hardwired i/o (global input pins) usage for igloo and proasic3 devices 60 k gates and larger and the name of the figure was changed from figure 4-8 illustration of hardwired i/o (global input pins) usage. figure 3-9 illustration of hardwired i/o (global input pins) usage for igloo and pr oasic3 devices 30 k gates and smaller is new. 3-13 table 3-5 number of cccs by device size and package was updated to include igloo nano and proasic3 nano devices. entries were added to note differences for the cs81, cs121, and cs201 packages. 3-17 the "clock conditioning circuits wi thout integrated plls" section was rewritten. 3-18 the "igloo and proasic3 ccc locations" section was updated for nano devices. 3-20 figure 4-13 ccc locations in th e 15 k and 30 k gate devices was deleted. 4-20 v1.2 (june 2008) this document was updated to incl ude fusion and rt proasic3 device information. please review th e document very carefully. n/a the "ccc support in actel?s flash devices" section was updated. 3-3 in the "global buffer with programmable delay" section , the following sentence was changed from: "in this case, the i/o must be placed in one of the dedicated global i/o locations." to "in this case, the software will automatica lly place the dedicated global i/o in the appropriate locations." 3-4 figure 3-4 ccc options: gl obal buffers with pll was updated to include oadivrst and oadivhalf. 3-7 in figure 3-5 ccc with pll block "fixed delay" was changed to "programmable delay". 3-7 table 3-3 input and output signals of the pll block was updated to include oadivrst and oadivhalf descriptions. 3-8 table 3-7 configuration bit de scriptions for the ccc blocks was updated to include configuration bits 88 to 81. note 2 is new. in addition, the description for bit <76:74> was updated. 3-28 table 3-15 fusion dynamic ccc clock source selection and table3-16fusion dynamic ccc ngmux configuration are new. 3-32
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.4 3-53 v1.2 (continued) table 3-17 fusion dynamic ccc division by half configuration and table 3-18 configuration bit <76:75> / vcosel<2:1> selectio n for all families are new. 3-33 v1.1 (march 2008) the following changes were made to the family descriptions in table 3-1 overview of the cccs offe red in fusion, igloo, and proasic3 : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 3-1 v1.0 (january 2008) table 3-1 flash-based fpgas and the associated text were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 3-3 the "global input selections" section was updated to include 15 k gate devices as supported i/o types for globals, for ccc only. 3-10 table 3-5 number of cccs by device size and package was revised to include proasic3l, igloo plus, a3p015, ag l015, aglp030, aglp060, and aglp125. 3-17 the "igloo and proasic3 ccc locations" section was revised to include 15 k gate devices in the exception statements, as they do not contain plls. 3-20 51900133-0/5.06 information about unlocking the pll was removed from the "dynamic pll configuration" section . 3-26 in the "dynamic pll configuration" section , information was added about running layout and determining the exact setting of the ports. 3-38 in table 3-7 configuration bit descriptions for the ccc blocks , the following bits were updated to delete "transport to the user" and reference the footnote at the bottom of the table: 79 to 71. 3-28 previous version changes in th e current version (v1.4) page

v1.1 4-1 4 ? fusion clock resources the actel fusion ? mixed-signal fpga family of devices has a wide variety of on-chip clocking peripherals, as shown in figure 4-1 . the on-chip resources enable the creation, manipulation, and distribution of clock signals both internally and externally. an integrated internal rc oscillator produces a 100 mhz clock without external comp onents. for systems that require more precise clock signals, the fusion mixed-sign al fpga family also supports an on-chip crystal oscillator circuit. in conjunction with the crystal oscillator circuit, the on-chip real-time counter (rtc) provides timed wake-up or power-up sequ ences and thus the ability to supply time and date stamps. like the proasic ? 3/e family of flash-based fpgas, the flas h-based fusion device integrates up to two phase-locked loop (pll) cores in the embedded clock conditioning circuits (cccs). the pll can be clocked from the internal rc oscillator, crystal oscillator, or any other internal signal. the integrated pll provides the capability to alte r the clock source by multiplying, dividing, synchronizing, advancing, or delaying the signal. the fusion mixed-signal fpga also integrates one no-glitch mux (ngm ux) for each pll. the ngmux enables designers to switch between mult iple clock sources without introducing glitches into the clock network. this chapter includes the following sections: ? "internal rc oscillator" on page 4-2 ? "crystal oscillator (xtlosc)" on page 4-6 ? "no-glitch multiplexer (ngmux)" on page 4-15 ? "real-time counter (rtc)" on page 4-23 note: this is a simplified block diagram of the clocking res ources within the fusion device. for details regarding the global networks and clocki ng resources, refer to the actel fusion mixe d-signal fpgas datasheet. for details regarding the pll/ccc, refer to the clock conditioning circuits in low-power flash devices and mixed-signal fpgas section of the handbook. figure 4-1 ? fusion mixed-signal fpga clocking system clock out to flash memory block clock out to fpga core through ccc glint or internal net gndosc on-chip off-chip vccosc crystal oscillator clock i/os external crystal external rc xtal clock pll/ ccc gla to core clkout ngmux glc from fpga core 100 mhz rc oscillator or xtal1 xtal2 clock out to fpga core must use clksrc xtal clock out to fpga core must use clksrc xtal clock out to rtccclk
fusion clock resources 4-2 v1.1 for information on using the ccc and pll, refer to the clock conditioning circuits in low-power flash devices and mixed-signal fpgas section of the handbook. internal rc oscillator the internal rc oscillator is an on-chip free-running clock source capable of generating a 100 mhz source without external components. using the in ternal rc oscillator in conjunction with the integrated pll enables designers to generate cloc ks of varying frequency and phase, clocking both on- and off-chip resources. the actel fusion mixed-signal fpgas datasheet contains both timing and accuracy characteristics for the internal rc os cillator peripheral. rc oscillator usage the internal rc oscillator is capa ble of driving any of the clock macros (i.e., a static or dynamic pll) directly after instantiation. to drive a macro in th e fpga core, the rc oscillator must first be routed through the clksrc macro. see the examples be low on manually instan tiating the rcosc and clksrc macros. smartgen can also be used to implement these macros. for more information on using smartgen, refer to the smartgen, flashrom, asb, and fl ash memory system builder user's guide . example: rc oscillator driving clock macros the following example manu ally instantiates the internal rc os cillator using the rcosc macro, and connects the 100 mhz clock output to the input pin of a smartgen-generated pll. since the 100 mhz clock output does not connect to fpga core logic, the clksrc macro is not needed. verilog module myclocks ( nsysreset, clk25mhz ); input nsysreset; output clk25mhz; wire clk100; rcosc urcosc ( .clkout (clk100) ); mypll mypll1 ( .powerdown (1'b1), .clka (clk100), .lock (), .gla (clk25mhz), .oadivrst (nsysreset) ); endmodule
fusion clock resources v1.1 4-3 vhdl library ieee; use ieee.std_logic_1164.all; entity myclocks is port ( nsysreset: in std_logic; clk25mhz: out std_logic ); end entity myclocks; architecture myclocks is signal clk100 : std_logic; component rcosc port ( clkout: out std_logic ); component mypll port ( powerdown: in std_logic; clka: out std_logic; lock: out std_logic; gla: out std_logic; oadivrst: in std_logic ); begin urcosc : rcosc port map ( clkout => clk100 ); mypll1 : mypll port map ( powerdown => ?1?, clka => clk100, lock => open, gla => clk25mhz, oadivrst => nsysreset ); end architecture myclocks;
fusion clock resources 4-4 v1.1 example: rc oscillator driv ing fpga core logic the following example manually in stantiates the internal rc osci llator and connects the 100 mhz clock output to the fpga core lo gic, which in turn generates a 25 mhz clock. both the rcosc and clksrc macros are used, rcosc to instantiate the internal rc oscill ator and clksrc to connect the rcosc output to fpga core logic. verilog module myclock ( nsysreset, clk25mhz ); input nsysreset; output clk25mhz; wire clk100, sysclk; reg [1:0] icount; rcosc urcosc ( .clkout (clk100) ); clksrc uclksrc ( .a (clk100), .y (sysclk) ); always @ (negedge nsysreset or posedge sysclk) begin if (nsysreset == 1'b0) icount = 2'b0; else icount = icount + 1'b1; end assign clk25mhz = icount[1]; endmodule
fusion clock resources v1.1 4-5 vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity myclock is port ( nsysreset: in std_logic; clk25mhz: out std_logic ); end entity myclock; architecture myclock is signal clk100 : std_logic; signal sysclk : std_logic; component rcosc port ( clkout: out std_logic ); component clksrc port ( a: in std_logic; y: out std_logic ); begin urcosc : rcosc port map ( clkout => clk100 ); uclksrc : clksrc port map ( a => clk100, y => sysclk ); process (nsysreset, sysclk) variable icount: std_logic_vector(1 downto 0); begin if (nsysreset = ?0?) icount := (others => ?0?); elsif (sysclk'event and sysclk = '1') icount := icount + ?1?; end clk25mhz <= icount(1); end architecture myclock;
fusion clock resources 4-6 v1.1 rc oscillator tips a nd package connections although the internal rc oscillator is only a one-port ma cro, the gndosc an d vccosc package pins must be connected externally to provide a power and ground source for the resource and the crystal oscillator. if neither the rc nor the crystal oscill ator is used, refer to the actel fusion mixed- signal fpgas datasheet for accurate termination guidelines. crystal oscillator (xtlosc) the crystal oscillator (xtlosc) generates the clock from an extern al crystal. the output of the xtlosc clkout signal can be selected as an input to the pll. refer to the clock conditioning circuits in low-power flash de vices and mixed- signal fpgas section of the handbook for more details. the xtlosc can operate in normal operation and standby mode (rtc is running and 1.5 v is not present). in normal operation, the internal fpga_en sign al is 1 as long as 1.5 v is present for v cc. . the internal enable signal for the cr ystal oscillator, xtl_en, is enable d since fpga_en is asserted. the xtl_mode signal can use mode or rtc_mode, depending on selmode. during standby, 1.5 v is not avai lable. fpga_en is 0 and selmode must be asserted in order for xtl_en to be enabled. hence xtl_mode relies on rtc_mode. selmode and rtc_mode must be connected to rtcxtlsel and rtcxtlmode from th e ab, respectively, for correct operation during standby. refer to the "real-time counter (rtc)" section on page 4-23 for a detailed description. note: *internal signal; does not exist in macro. figure 4-2 ? xtlosc macro xtlosc clkout rtc_mode[1:0] selmode xtl mode[1:0] fpga_en* _ xtl_en* xtl_mode 0 1
fusion clock resources v1.1 4-7 table 4-1 ? xtlosc signals description signal name width d irection function xtl_en* 1 enables the cr ystal. active high. xtl_mode* 2 settings for the crysta l clock for different frequencies: value modes frequency range b?00 rc network 32 khz to 4 mhz b?01 low gain 32 to 200 khz b?10 medium gain 0.20 to 2.0 mhz b?11 high gain 2.0 to 20.0 mhz selmode 1 in selects the source of xtl_mode and also enables the xtl_en. connect from rtcxtlsel from ab. 0: for normal operation or sleep mode of operation xtl_en depends on fpga_en, xtl_mode depends on mode 1: for standby mode of operation xtl_en is enabled, xtl_mode depends on rtc_mode rtc_mode[1:0] 2 in settings for the crystal clock for different frequency ranges. xtl_mode uses rtc_ mode when selmode is 1. mode[1:0] 2 in settings for the crys tal clock for different frequency ranges. xtl_mode uses mode when selmode is 0. in standby, mode inputs will be 0s. fpga_en* 1 in 0 when 1.5 v is not present for v cc 1 when 1.5 v is present for v cc xtl 1 in crystal clock source clkout 1 out crystal clock output note: *internal signal and does not exist in macro
fusion clock resources 4-8 v1.1 the crystal oscillator can be config ured in one of the four modes: ? rc network, 32 khz to 4 mhz ? low gain, 32 to 200 khz ? medium gain, 0.20 to 2.0 mhz ? high gain, 2.0 to 20.0 mhz in rc network mode, the xtal1 pin is c onnected to an rc ci rcuit, as shown in figure 4-1 on page 4-1 . the xtal2 pin should be left floating. the rc value can be chosen based on figure 4-3 for any desired frequency between 32 khz and 4 mhz. the rc network mode can also accommodate an external clock source on xtal1 instead of an rc circuit. in low gain, medium gain, and high gain, an external crystal component or ceramic resonator can be added onto xtal1 and xtal2, as shown in figure 4-1 on page 4-1 . example: crystal oscillator driving the real-time counter the following example manually instantiates the crystal oscillator using the xtlosc macro and connects the external 32.768 khz crystal output to the rtc in the analog block (ab). since the 32.768 khz clock output does not connect to fpga core lo gic, the clksrc macro is not needed. the examples below assumes that the analog co nfiguration mux (acm) has been previously configured and is controlling the functionality of the rtc. for more information on the acm, refer to designing the fusion analog system . verilog module myrtc ( clk10mhz, clk32khz ); input clk10mhz; input clk32khz; wire irtcclk, irtcselmode; wire [1:0] irtcmode; wire iacmclk, iacmwen, iacmreset; wire [7:0] iacmaddr, iacmrdata, iacmwdata; figure 4-3 ? crystal oscillator: rc time consta nt values vs. frequency (typical) 0.0 1.00e-0.7 1.00e-0.6 1.00e-0.5 1.00e-0.4 1.00e-0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 rc time constant (sec) frequency (mhz) rc time constant values vs. frequency
fusion clock resources v1.1 4-9 xtlosc uxtlosc ( .xtl (clk32khz), .clkout (irtcclk), .selmode (irtcselmode), .mode (2?b0), .rtcmode (irtcmode) ); ab uab ( // note: several of the analog block signals // have been omitted from this // example, only the critical signals // are present. .sysclk (clk10mhz), .acmclk (iacmclk), .acmwen (iacmwen), .acmreset (iacmreset), .acmwdata (iacmwdata), .acmaddr (iacmaddr), .acmrdata (iacmrdata), .rtcclk (irtcclk), .rtcxtlsel (irtcselmode), .rtcxtlmode (irtcmode), .rtcmatch (), .rtcpsmmatch () ); endmodule vhdl library ieee; use ieee.std_logic_1164.all; entity myrtc is port ( clk10mhz: in std_logic; clk32khz: in std_logic ); end entity myrtc; architecture myrtc is signal irtcclk : std_logic; signal irtcselmode : std_logic; signal irtcmode : std_logic_vector(1 downto 0); signal iacmclk : std_logic; signal iacmreset : std_logic; signal iacmwen : std_logic; signal iacmaddr : std_logic_vector(7 downto 0; signal iacmrdata : std_logic_vector(7 downto 0; signal iacmwdata : std_logic_vector(7 downto 0; component xtlosc port ( xtl: in std_logic; clkout: out std_logic; selmode: in std_logic_vector(1 downto 0); rtcmode: in std_logic_vector(1 downto 0); mode: in std_logic_vector(1 downto 0) );
fusion clock resources 4-10 v1.1 ab -- note: several of the analog block signals -- have been omitted from this -- example, only the critical signals -- are present. port ( sysclk: in std_logic; acmclk: in std_logic; acmwen: in std_logic; acmreset: in std_logic; acmaddr: in std_logic_vector(7 downto 0); acmwdata: in std_logic_vector(7 downto 0); acmrdata: out std_logic_vector(7 downto 0); rtcclk: in std_logic; rtcxtlsel: out std_logic; rtcxtlmode: out std_logic_vector(1 downto 0); rtcmatch: out std_logic; rtcpsmatch: out std_logic ); begin uxtlosc : xtlosc port map ( xtl => clk32khz, clkout => irtcclk, selmode => irtcselmode, mode => ?00?, rtcmode => irtcmode ); uab : ab -- note: several of the analog block signals -- have been omitted from this -- example, only the critical signals -- are present. port map ( sysclk => clk10mhz, acmclk => iacmclk, acmwen => iacmwen, acmreset => iacmreset, acmwdata => iacmwdata, acmaddr => iacmaddr, acmrdata => iacmrdata, rtcclk => irtcclk, rtcxtlsel => irtcselmode, rtcxtlmode => irtcmode, rtcmatch => open, rtcpsmmatch => open ); end architecture myrtc;
fusion clock resources v1.1 4-11 example: crystal oscillato r driving clock macros the following example manually instantiates the crystal oscillator using the xtlosc macro and connects the external crystal to the input pin of a smartg en-generated pll. since the external crystal does not connect to fpga core logic, the clksrc macro is not needed. verilog module myxtal ( clk50mhz, nsysreset, xtal10mhz ); input xtal10mhz; input nsysreset; output clk50mhz; wire ixtlclk; xtlosc uxtlosc ( .xtl (xtal10mhz), .clkout (ixtlclk), .selmode (1?b0), .mode (2?b11), .rtcmode (2?b0) ); mypll mypll1 ( .powerdown (1'b1), .clka (ixtlclk), .lock (), .gla (clk50mhz), .oadivrst (nsysreset) ); endmodule
fusion clock resources 4-12 v1.1 vhdl library ieee; use ieee.std_logic_1164.all; entity myxtal is port ( clk50mhz: out std_logic; nsysreset: in std_logic; xtal10mhz: in std_logic ); end entity myxtal; architecture myxtal is signal ixtlclk : std_logic; component xtlosc port ( xtl: in std_logic; clkout: out std_logic; selmode: in std_logic_vector(1 downto 0); rtcmode: in std_logic_vector(1 downto 0); mode: in std_logic_vector(1 downto 0) ); component mypll port ( powerdown: in std_logic; clka: out std_logic; lock: out std_logic; gla: out std_logic; oadivrst: in std_logic ); begin uxtlosc : xtlosc port map ( xtl => xtal10mhz, clkout => ixtlclk, selmode => ?0?, mode => ?11?, rtcmode => ?00? ); mypll1 : mypll port map ( powerdown => ?1?, clka => ixtlclk, lock => open, gla => clk50mhz, oadivrst => nsysreset ); end architecture myxtal;
fusion clock resources v1.1 4-13 example: crystal oscillator driving fpga core logic the following example manually instantiates the crys tal oscillator and connects the external crystal output to the fpga core logic, which in turn generates a clock divided by four. both the xtlosc and clksrc macros are used, xtlosc to instantiat e the crystal oscillator and clksrc to connect the xtlosc output to fpga core logic. verilog module myclkdiv ( clkdiv4, nsysreset, xtal10mhz ); input xtal10mhz; input nsysreset; output clkdiv4; wire ixtlclk; wire sysclk; reg [1:0] icount; xtlosc uxtlosc ( .xtl (xtal10mhz), .clkout (ixtlclk), .selmode (1?b0), .mode (2?b11), .rtcmode (2?b0) ); clksrc uclksrc ( .a (ixtlclk), .y (sysclk) ); always @ (negedge nsysreset or posedge sysclk) begin if (nsysreset == 1'b0) icount = 2'b0; else icount = icount + 1'b1; end assign clkdiv4 = icount[1]; endmodule
fusion clock resources 4-14 v1.1 vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity myclkdiv is port ( clkdiv4: out std_logic; nsysreset: in std_logic; xtal10mhz: in std_logic ); end entity myclkdiv; architecture myclkdiv is signal ixtlclk : std_logic; signal sysclk : std_logic; component xtlosc port ( xtl: in std_logic; clkout: out std_logic; selmode: in std_logic_vector(1 downto 0); rtcmode: in std_logic_vector(1 downto 0); mode: in std_logic_vector(1 downto 0) ); component clksrc port ( a: in std_logic; y: out std_logic ); begin uxtlosc : xtlosc port map ( xtl => xtal10mhz, clkout => ixtlclk, selmode => ?0?, mode => ?11?, rtcmode => ?00? ); uclksrc : clksrc port map ( a => ixtlclk, y => sysclk ); process (nsysreset, sysclk) variable icount: std_logic_vector(1 downto 0); begin if (nsysreset = ?0?) icount := (others => ?0?); elsif (sysclk'event and sysclk = '1') icount := icount + ?1?; end clkdiv4 <= icount(1); end architecture myclkdiv;
fusion clock resources v1.1 4-15 crystal oscillator tips and package connections when using the crystal oscillator, the gndos c and vccosc external package pins must be connected to provide power and ground sources fo r this resource and the internal rc oscillator ( table 4-2 ). if neither the rc nor the crysta l oscillator is used, refer to the actel fusion mixed-signal fpgas datasheet for accurate termination guidelines. in addition, the xtl pin of the xtlosc macro is connected to the xtal1 package pin, the crystal oscillator circuit input. when us ing an external rc network th e xtal2 package pin must be left unconnected. no-glitch multiplexer (ngmux) up to two no-glitch mult iplexers, positioned downstream from the pll/ccc blocks, are integrated into the fusion device, as shown in figure 4-4 . the ngmux provides a special switching sequence between two asynchronous clock domains, which avoids generating any unwanted narrow glitch pulses. it switches between two different clock sources and the output goes to the global network, as shown in figure 4-5 on page 4-16 . table 4-2 ? crystal oscillator tips and package connections signal name direction description xtal1 input input to crystal oscillator circuit. this pin is used to connect the external crystal, ceramic resonator, rc network, or extern al clock inpu t. when using an external crystal or ceramic oscillator, actel recommend s using external capacitors (refer to the actel fusion mixed-signal fpgas datasheet for the recomme nded capacitor values). if using an external rc network or cl ock input, use xtal1 and leave xtal2 unconnected. xtal2 input input to crystal oscillator circuit. this pin is used to connect the external crystal, ceramic resonator, rc network, or extern al clock inpu t. when using an external crystal or ceramic oscillator, actel recommend s using external capacitors (refer to the actel fusion mixed-signal fpgas datasheet for the recomme nded capacitor values). if using an external rc network or cl ock input, use xtal1 and leave xtal2 unconnected. vccosc input external power supply (3.3 v) for both the integrated rc and cr ystal oscillator circuits gndosc input external ground supply for both the integrated rc and crystal oscillator circuits figure 4-4 ? no-glitch mux glint or internal net gla glc glmuxsel clkout pll/ ccc ngmux to clock rib driver
fusion clock resources 4-16 v1.1 the ngmux allows the following in puts: pll outputs gla and glc, and glint or any internal net. however, there are some restrictions on these signals, whic h are described in "ngmux usage" on page 4-18 . ngmux modes of operation the signals driving ngmux have the same specifications as th e output clock of the pll/ccc. the following examples show variou s scenarios for the switching se quence between two asynchronous clock domains clk0 and clk1. case 1: both clk0 and clk1 active when both the clk0 and clk1 inputs to the ngmux ar e active, the switchin g sequence between the two clock sources (from clk0 to clk1) is as below. an example is shown in figure 4-6 . 1. a transition on s initiates the clock source switch. 2. gl drives one last complete clk0 positive puls e (i.e., one rising edge followed by one falling edge). 3. gl stays low until the second rising edge of clk1 occurs. 4. at the second clk1 rising edge, gl continuously delivers clk1. note: min. t sw = 0.05 ns at 35 c (typical conditions) figure 4-5 ? no-glitch mux macro figure 4-6 ? active clk0/clk1 inputs to ngmux clk0 clk1 s gl clk0 clk1 s gl t sw
fusion clock resources v1.1 4-17 case 2: clk0 stopped or at very low frequency if clk0 stops or runs at a very low frequency af ter s transition, the timeout circuitry inside the fpga is used. the sequence of switching between the two clock sources (from clk0 to clk1) is described and illustrated below. case 2a: no rising clk0 edge if clk0 does not have a rising edge before th e seventh clk1 rising ed ge, the switching sequence between the two clock sources (from clk0 to clk1) is as shown in figure 4-7 . 1. at the seventh clk1 rising edge, gl will go low until the ninth clk1 rising edge. 2. at the ninth clk1 rising edge, gl will continuously deliver the clk1 signal. case 2b: no falling clk0 edge if a clk0 rising edge oc curs before the seventh cl k1 rising edge but a cl k0 falling edge does not occur before the fifteenth clk1 rising edge, th e sequence of switching between the two clock sources (from clk0 to clk1) is as shown in figure 4-8 . 1. at the fifteenth clk1 rising edge, gl will go low until the seventeenth clk1 rising edge. 2. at the seventeenth clk1 rising edge, gl will continuously deliver the clk1 signal. figure 4-7 ? low-frequency clk0 after s transition, no rising clk0 edge before seventh rising clk1 edge clk0 clk1 s gl figure 4-8 ? low-frequency clk0 after s transition, rising clk0 edge before seventh rising clk1 edge clk0 clk1 s gl
fusion clock resources 4-18 v1.1 ngmux usage the software implementation of th e ngmux has been simplified to a 2:1 multiplexer, as shown in figure 4-5 on page 4-16 . the two clock input ports are clk0 and clk1, and the output clock port is gl. the allowable inputs to the ngmux are as follows: ? the gla and glc outputs of a pll ? the gla output of a pll and glint (the fanout of glint must be 1) ? the gla output of a pll and an internal net smartgen can also be used to implement these macros. for more informat ion on using smartgen, refer to the smartgen, flashrom, analog system builder, and flash memory system builder user's guide . the following example manually instantiates the no-glitch multiplexer using the ngmux macro and connects the clk0 and clk1 ports to the output ports of a smartgen-generated pll. verilog module myclkmux ( sysclk, clk75mhz, clksel ); input clksel; input clk75mhz; output sysclk; wire igla, iglc; ngmux ungmux ( .clk0 (igla), .clk1 (iglc), .s (clksel), .gl (sysclk) ); mypll mypll1 ( .powerdown (1'b1), .clka ( clk75mhz), .lock (), .gla ( igla), .glc (iglc), .oadivrst (nsysreset) ); endmodule
fusion clock resources v1.1 4-19 vhdl library ieee; use ieee.std_logic_1164.all; entity my clkmux is port ( sysclk: out std_logic; clk75mhz: in std_logic; clksel: in std_logic ); end entity my clkmux; architecture my clkmux is signal igla : std_logic; signal iglc : std_logic; component ngmux port ( clk0: in std_logic; clk1: in std_logic; s: in std_logic; gl : out std_logic ); component mypll port ( powerdown: in std_logic; clka: out std_logic; lock: out std_logic; gla: out std_logic; gl c: out std_logic; oadivrst: in std_logic ); begin ungmux : ngmux port map ( clk0 => igla, clk1 => iglc, s => clksel, gl => sysclk ); mypll1 : mypll port map ( powerdown => ?1?, clka => clk75mhz, lock => open, gla => igla, gl c => iglc, oadivrst => nsysreset ); end architecture my clkmux;
fusion clock resources 4-20 v1.1 ngmux tips the following design considerations are recommended when using the ngmux: ? the ngmux has a fixed design location and is intended to be plac ed downstream from the pll. ? hardwire the ngmux clk0 input to pll outp ut gla, as gla must drive the ngmux clk0 input. gla can only have a fanout of one, as the gla global driver is used for the ngmux output. ? if the two inputs to the ngmux are pll out puts gla and glc, you may lose the global network driver for glc because it is consumed by the pll output. since the global network in fusion is segmented, loca l clock networks can be used even though the whole global network is not available. ? since the ngmux macro has a fixed location (downstream from the pll), routing delay can occur when the input to ngm ux comes from a regular net. ? the ngmux gl output uses the gla global network. ngmux timing analysis timing analysis verifies the func tionality of the design with timing information. to check the design functionality for ngmux, designers should ch eck both the static and dynamic timing analyses as follows. ngmux static timing analysis static timing analysis on both clock inputs is performed separately using the smarttime tool in designer ( figure 4-9 ). run setup and hold checks on the source pins of clk0 and clk1. figure 4-9 ? static timing an alysis example
fusion clock resources v1.1 4-21 figure 4-9 on page 4-20 shows how the two inputs of th e ngmux are connected from the uclk_divider and uclksrc componen ts. in this instance, setup and hold time checks in smarttime are done for both clocks, uclk_divider /inst1:gl and uclksrc:y, as shown in figure 4-10 . ngmux dynamic timing analysis for dynamic timing analysis, run a back-annotated timing simulation using the modelsim ? tool, and check the ngmux si gnals, as shown in figure 4-11 . a transition of s from high to low initiates a sw itch to clk0, and from lo w to high initiates a switch to clk1. the output of th e ngmux is undefined if s swit ches again before the previous switch operation has completed. figure 4-10 ? checking setup and hold times for clocks figure 4-11 ? dynamic timing analys is for ngmux signals
fusion clock resources 4-22 v1.1 ngmux connections the ngmux has two input ports that are intended to be connected to clock signals. connect the clk0 input to a net driven by a clock signa l. the fanout of the net connecting ccc:gla to ngmux:clk0 should always be one. the driver of th is clock signal will automatically be placed in the gla tile for the ccc location in which the ngmux is placed. there are two possible connecti ons for the ngmux:clk1 input: 1. the clk1 port can be driven by a clock signa l. the fanout of the net connecting ccc:glc to ngmux:clk1 should always be one. the driver will automatically be placed in the ccc:glc tile for the locati on in which the ngmux is placed. 2. the clk1 port can also be driven by a routed net; in this case , there is no re striction on the placement or fanout of the logic/net driving ngmux:clk1. the integrated fusion oscillators cannot drive the ngmux directly, as they do not produce the clock signals. you must connect them to the ngm ux inputs through a valid clock macro (i.e., clksrc), refer to "internal rc oscillator" on page 4-2 and "crystal oscillator (xtlosc)" on page 4-6 for more information. ngmux placement the ngmux macros are placed automatically dur ing layout. the ngmux macros can be manually placed by doing the following: 1. placing ngmux. one of the two available location s for ngmux must be chosen: tile5 of the central ccc locations (shown in yellow in figure 4-12 ). 2. placing the driver for clk0. the driver for clk0 has to be a ccc macro that can be placed in the ccc:gla tile (shown in green in figure 4-12 ). the ccc macros that can be placed here are as follows: ? clkbuf (only non-v ref versions) ? clkbibuf ? clksrc ? clkdly ?clkdivdly ?pll 3. placing the driver for clk1. if the driver for clk1 is a ccc macro, it infers a hardwired connection. this macro must be placed in the ccc:glc tile (shown in pink in figure 4-12 ) and has the same ccc macro restrictions as clk0. when the clk1 port drives a pll:glc instan ce, the pll:gla instance of the same pll must become the driver for clk0. when the ccc macro is driven from the ha rdwired i/o, placing the i/o controls the placement of the ccc macro. figure 4-12 ? ngmux interconnects west ccc east ccc
fusion clock resources v1.1 4-23 real-time counter (rtc) the addition of th e real-time counter enab les the fusion mixed-sign al fpga to support both standby and sleep modes of operation, greatly reducing power consumption in many applications. the rtc also provides implementa tion of a time and date calend ar, enabling embedded systems to log data with time and date stamps. rtc usage the rtc resides within the fusion analog block an d has the following features and requirements: ? the rtc must be driven by th e crystal oscillator circuit, an d the crystal oscillator must be configured to oper ate in rtc mode. ? the match signal on the output of the rtc sy stem asserts when the value in the counter matches the value specified in the match register. ? there is an optional output rtcpsmmatc h that is triggered on a match. the rtcpsmmatch signal can be used to signal the internal voltag e regulator to power up/down and must be connected to the rtcp sm macro so the voltage regulator actives when the match signal is asserted. the match signal asserts when the counter is equal to the value contained in matchreg. matchreg is a 40-bit regi ster located in the acm. the rtc count register (c ounter) can be preloaded with a zero or non-zero start value. the default value is zero. this is also a 40-bit register located in the acm. the control/status register (ctrl_st at) is an 8-bit register located within the acm that defines the operation of the rtc. the control register can rese t the rtc, enabling operation to begin with all zeroes in the counter. the rtc can be configured to clear upon a match with the match register, or it can continue to count while the match signal is still asserted. design ers can also enable the fusion device to power on at a specific time or at periodic intervals. fo r more information on the ctrl_stat register, refer to the actel fusion mi xed-signal fpgas datasheet. smartgen can also be used to implement these macros. for more informat ion on using smartgen, refer to the smartgen, flashrom, analog system builder, and flash memory system builder user's guide . the following example manually instantiates the crystal oscillator using the xtlosc macro and connects the external 32.768 khz crystal output to th e rtc in the ab. sinc e the 32.768 khz clock output is not connected to fpga core logic, th e clksrc macro is not needed. the example below assumes that the acm has been pr eviously configured and is controlling the functionality of the rtc. for more information on the acm refer to the designing the fusion analog system .
fusion clock resources 4-24 v1.1 verilog module myrtc ( clk10mhz, clk32khz ); input clk10mhz; input clk32khz; wire irtcclk, irtcselmode; wire [1:0] irtcmode; wire iacmclk, iacmwen, iacmreset; wire [7:0] iacmaddr, iacmrdata, iacmwdata; xtlosc uxtlosc ( .xtl (clk32khz), .clkout (irtcclk), .selmode (irtcselmode), .mode (2?b0), .rtcmode (irtcmode) ); ab uab ( // note: several of the analog block signals // have been omitted from this // example, only the critical signals // are present. .sysclk (clk10mhz), .acmclk (iacmclk), .acmwen (iacmwen), .acmreset (iacmreset), .acmwdata (iacmwdata), .acmaddr (iacmaddr), (iacmrdata), .rtcclk (irtcclk), .rtcxtlsel (irtcselmode), .rtcxtlmode (irtcmode), .rtcmatch (), .rtcpsmmatch () ); endmodule
fusion clock resources v1.1 4-25 vhdl library ieee; use ieee.std_logic_1164.all; entity myrtc is port ( clk10mhz: in std_logic; clk32khz: in std_logic ); end entity my rtc; architecture my rtc is signal irtcclk : std_logic; signal irtcselmode : std_logic; signal irtcmode : std_logic_vector(1 downto 0); signal iacmclk : std_logic; signal iacmreset : std_logic; signal iacmwen : std_logic; signal iacmaddr : std_logic_vector(7 downto 0; signal iacmrdata : std_logic_vector(7 downto 0; signal iacmwdata : std_logic_vector(7 downto 0; component xtlosc port ( xtl: in std_logic; clkout: out std_logic; selmode: in std_logic_vector(1 downto 0); rtcmode: in std_logic_vector(1 downto 0); mode: in std_logic_vector(1 downto 0) ); component ab -- note: several of the analog block signals -- have been omitted from this -- example, only the critical signals -- are present. port ( sysclk: in std_logic; acmclk: in std_logic; acmwen: in std_logic; acmreset: in std_logic; acmaddr: in std_logic_vector(7 downto 0); acmwdata: in std_logic_vector(7 downto 0); acmrdata: out std_logic_vector(7 downto 0); rtcclk: in std_logic; rtcxtlsel: out std_logic; rtcxtlmode: out std_logic_vector(1 downto 0); rtcmatch: out std_logic; rtcpsmatch: out std_logic ); begin uxtlosc : xtlosc port map ( xtl => clk32khz, clkout => irtcclk, selmode => irtcselmode, mode => ?00?, rtcmode => irtcmode );
fusion clock resources 4-26 v1.1 uab : ab -- note: several of the analog block signals -- have been omitted from this -- example, only the critical signals -- are present. port map ( sysclk => clk10mhz, acmclk => iacmclk, acmwen => iacmwen, acmreset => iacmreset, acmwdata => iacmwdata, acmaddr => iacmaddr, acmrdata => iacmrdata, rtcclk => irtcclk, rtcxtlsel => irtcselmode, rtcxtlmode => irtcmode, rtcmatch => open, rtcpsmmatch => open ); end architecture myrtc;
fusion clock resources v1.1 4-27 rtc tips the following design considerations are advised when using the rtc: ? when the rtc is not configured to reset the counter when a match oc curs, the time interval between active rtcmatch occurrences is equal to the total cumulative time count of the 40-bit rtc. in other words, the counter must overflow and reach the matchreg value again to create an active rtcmatch output. the time required for the coun ter to overflow would not be practical for most app lications; actel recommends that the counter be reset upon a match condition if the rtcmatch signal is needed. ? each bit of the 40-bit counter is compared to each bit of the 40-bit matchreg via xnor gates, and the result is stored in the matchb its register, enabling the designer to check whether an individual bit match has occurred. ? the location of the rtc registers within the acm is shown in table 4-3 . table 4-3 ? location of the rtc within the analog configuration mux acm_addr[7:0] registe r name description 0x40 counter0 counter bits [7:0] 0x41 counter1 counter bits [15:8] 0x42 counter2 counter bits [23:16] 0x43 counter3 counter bits [31:24] 0x44 counter4 counter bits [39:32] 0x48 matchreg0 match register bits [7:0] 0x49 matchreg1 match register bits [15:8] 0x4a matchreg2 match register bits [23:16] 0x4b matchreg3 match register bits [31:24] 0x4c matchreg4 match register bits [39:32] 0x50 matchbits0 individual match bits [7:0] 0x51 matchbits1 individual match bits [15:8] 0x52 matchbits2 individual match bits [23:16] 0x53 matchbits3 individual match bits [31:24] 0x54 matchbits4 individual match bits [39:32] 0x58 ctrl_stat control / status register bits 0x59 test_reg test register
fusion clock resources 4-28 v1.1 rtc interconnection figure 4-13 shows the interconnection between the rt c and the various comp onents in the fusion device. if any hardwired input is not used, connect it to gnd, an d leave unused outputs floating (see the "verilog" section on page 4-24 and the "vhdl" section on page 4-25 for an example of unused outputs left floating). fo r all hardwired connections, the fanout of the net connecting the two hardwired pins must be one. related documents handbook documents actel fusion mixe d-signal fpgas datasheet http://www.actel.com/documents/fusion_ds.pdf clock conditioning circuits in low-power flash devices and mixed-signal fpgas http://www.actel.com/documents/lpd_ccc_hbs.pdf designing the fusion analog system http://www.actel.com/documen ts/fusion_analog_hbs.pdf user?s guides smartgen, flashrom, asb, and flash me mory system builder user's guide http://www.actel.com/documents/genguide_ug.pdf figure 4-13 ? rtc interconnection diagram rtc rtcclk rtcpsmmatch rtcmode [1:0] selmode rtcmatch crystal oscillator xtal2 xtal1 en mode [1:0] clkout 1.5 v voltage regulator fpga fabric vrpu ptbase ptem 1.5 v fpga supply input 0 vr logic vr init pub acm vrinitstate vron rtcpsmmatch flash bits vrpsm fpgagood power-up/-down toggle control switch 1.5 v output external pass transistor 3.3 v 1.5/3.3 v level shift circuitry fpga_vron vcc33up from core flash bits
fusion clock resources v1.1 4-29 part number and revision date part number 51700092-003-1 revised august 2009 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (november 2007) the "crystal oscillator" section was revised to remove table 4-1 rc oscillator tips and package connections and table 4-2 crystal oscillator mode settings. the text of the "crystal oscillator usage" section was replaced with new text and figure 4-2 xtlosc macro was replaced. 4-6 figure 4-3 crystal oscillator: rc time constant values vs. frequency (typical) is new. 4-8

embedded memories

v1.0 5-1 5 ? fusion embedded flash memory blocks actel has not only utilized flash memory technology to configure the actel fusion ? fpga core tiles, but fusion also offers up to fo ur embedded flash blocks (fbs), each 2 mbits in density, for system initialization and general data storage. the embedded fl ash memory blocks are accessible by both on-chip and off-chip resources. in ternally, the fpga core fabric can directly access the fb?s data bus. externally, the embedded flash memory is acce ssible via the jtag port or through interfaces implemented within the fpga fabric: amba ahb (advanced microcontroller bus architecture advanced high-performance bus), corecfi (common flash interface), or a proprietary interface. it can be partitioned along page boundaries, giving designers better control over memory space usage, and the ability to individually protect each memory space against pa ge loss, page overwrite, and external access. it also of fers priority action control of the memory operations during simultaneous access requests. the embedded flash memory can be configured using the flash memory system builder in actel libero ? integrated design environmen t (ide), using the coreconsole ip deployment platform (idp) for microprocessor usage, and ma nually through rtl. the following sections discuss design usage details for each method of configuration. using the embedded flash memory for initialization the flash memory system builder in libero ide en ables designers to easily configure the embedded flash memory via a simple gui in terface. the gui interface provides fpga designers the ability to quickly partition and configure the embedded fl ash memory for initializ ation or general data storage purposes. this section discusses the uses of the initialization ip offered in libero ide as a block within the embedded flash memory system. the flash memory system builder offers the ability to support five types of clients. a client is a design block whose functionality is dependent on or configured by the data stored in the embedded flash memory. these clie nts also utilize the custom ip fu nctionality added to the flash memory control logic, only ava ilable through the flash memory block system builder. two of the client types are used to add general-purpose data storage capability to th e flash memory system. these clients are described in the "using the embedded flash memory for general data storage" section on page 5-22 . the other three clients are described in the following subsections. as clients are added to the flash memory system builder, the flash memory syste m is partitioned and configured accordingly. once each client?s me mory partition is conf igured, the hdl code is generated for the flash memory system and is read y to be interfaced with the design project. figure 5-1 on page 5-2 portrays the embedded flash with init ialization ip system interconnects to its clients. the flash memory block system builder support s the following initialization clients: ? the analog system client is used to config ure the flash memory for the storage of the fusion analog system initialization and conf iguration parameters, which are stored in the spare pages of the flash memory. ? the ram initialization client is used to create and configure a flash memory partition to store ram initialization data to be reloaded at power-up fo r context-saving applications. ? the standalone initialization cl ient is used to create and configure a general-purpose flash memory partition to store initialization data interfaced to , for example, a ram/fifo or rom emulation. the initialization in terface must be custom-designed.
fusion embedded flash memory blocks 5-2 v1.0 each client spans a minimum of one page (128 byte s) and can span up to 2,048 pages, depending on the number of free pages available. the analog system client itself does not take any of the regular pages; it is stored entire ly in the reserved (spare) pages. embedded flash initialization ip interface the flash memory system builder has the capabili ty to generate the embedded flash with an integrated initialization ip circ uit. the initialization circuit was designed to read data from embedded flash and store its co ntents in usable volatile regi sters or ram for quick and easy accesses by the on-chip systems. the initializati on circuit includes a co mmon interface between the flash memory block and its suppor ted clients. specific write enab le or data control signals are included in the circuit to cont rol the write and read accesses between the clients and embedded flash. the analog system client and ra m initialization client are the two key clients that interface directly to the flash initialization circuit. a user design block can also be interfaced to the embedded flash for initialization with the use of the standalone initialization client. however, the initialization interface bridge must be designed by the user and added to the user block design. once the initialization clients and flash memory have been configured, the hdl is generated per the specifications entered in the libero ide gui . the embedded flash memo ry module includes a common initialization interface between all clients and the control signals specific to the client. table 5-1 on page 5-3 includes a list of all the common in itialization interface ports and their descriptions. figure 5-1 ? embedded flash with initializatio n client system interconnects embedded flash with initialization client interface embedded flash memory init/ config ip control standalone initialization init/ config design rtl block ram with initialization init/ config ip ram analog system block analog system soft ip assc ram smev ram smtr ram analog block acm registers rtc rtc registers
fusion embedded flash memory blocks v1.0 5-3 table 5-1 ? flash initialization interface common client ports flash port direction description sys_reset input asynchronous active-low system reset si gnal that w ill hold the flash memory in an initial state un til released. this input is often common to the fpga design?s main reset. init_clk input initialization clock input whose maximum operating frequency is 10 mhz; it is rising-edge-active. for synchronous operation between the flash and its client s, its source clock should be common. init_power_up input active-high input to the flash, used to activate the initialization ip circuitry at power-up. init_power_up must be high at least until init_done transitions from low to high. it can typically be tied high unless performing on-demand updates to the system volatile registers as described in the "managing the initialization process for po wer management" section on page 5-6 . if being controlled, its tr ansitions must be synchronous to init_clk. init_done output active-high initialization-done signal. upon flash sys_reset, init_done defaults to low and remains low during the initialization activity. it transitions high synchronously to init_clk once the initialization process completes. init_addr output this 9-bit initialization ad dress bus is common to the entire flash initialization system. during init ialization and the save-to-flash activity, init_addr synchronously transitions with the rising edge of init_clk. after flash sys_reset, init_addr defaults to 0x000. for each initialization cl ient, init_addr begins at 0x000 and sequentially increments thro ugh all addresses in the flash page(s) assigned to the c lient?s memory partition. init_data output the 9-bit initialization data bus is common to the entire flash initialization system. during the in itialization activity, init_data synchronously transitions with the rising edge of init_clk. after flash sys_reset, init_data defaults to 0x000. depending on the client being initialized, either all nine bits or only the eight least significant bits are utilized as data. init_x_wen output active- high write enable (chip select ) control signal s from flash to the analog system?s volatile registers. in it_x_wen is a generic description for multiple signals to the analog block (ab). refer to the "analog system client" section on page 5-7 for name specifics. each signal is a 1-bi t port from the flas h block. after flash sys_reset, all signals defaul t to low. during initialization activity, each signal synchronou sly transitions with the rising edge of init_clk. only one signal is activated at a time. once activated, it will remain active until all addresses in the defined memory space are accessed.
fusion embedded flash memory blocks 5-4 v1.0 at power-up, after the flash reset is inactive, the initialization circuit reads the partitions from flash and writes the data to volatile memory. the init_power_up sign al must be high, and init_done low, to trigger this process. if all clients are to initialize only at power-up, the init_power_up signal can be tied high. once the initialization process begins , the init_done output flag is asserted low. during its low state, the main sy stem design can use the init_done signal as a mask to prevent the system desi gn from accessing the analog sy stem or the other clients being initialized during this process. none of the initia lization clients should be used, including the on- chip adc, until the initialization process completes. the initialization circuit first initializes the anal og system block, followed by the ram and other clients. for each client being initia lized, a chip select or data valid control signal is produced by the flash memory system. as shown in figure 5-2 on page 5-5 , the init_x_wen si gnal pulses high when the write action to the volatile memo ry can be synchronously executed. once the initialization process completes, the init_done signal transiti ons from low to high, indicating that the process has completed and normal device operation can proceed. figure 5-3 on page 5-5 shows a simplified simulation of the initialization process at power-up. the specific write enable or data valid signals are shown pulsin g, activating the initialization process for each particular client in the system. _x_dat_val output active -high data valid control signal (chip select) from the flash to the ram block(s). _x_dat_val is a generic description for mu ltiple signals to the ra m block. refer to the "ram initialization client" section on page 5-10 for name specifics. each signal is a 1-bi t port from the flas h block. after flash sys_reset, all signals defaul t to low. during initialization or save-to-flash activity, each signal synchronously transitions with the rising edge of init_clk. only one signal is activated at a time. once activated, it will re main active until all addresses in the client?s defined memory space are accessed. _ output activ e-high chip select fo r the initialization cl ient from the flash to the defined bloc k. _ is a generic description for multiple signals to th e block to be initialized. refer to the "standalone initialization client" section on page 5-14 for name specifics. each signal is a 1-bit port from the flash block. after flash sys_reset, all signals default to low. during initialization or save -to-flash activity, each signal synchronously transitions with the rising edge of init_clk. only one signal is activated at a time. once activated, it will remain active until all addresses in the client?s defined memory space are accessed. table 5-1 ? flash initialization interface common client ports (continued) flash port direction description
fusion embedded flash memory blocks v1.0 5-5 figure 5-2 ? basic initialization timing diagram figure 5-3 ? complete initialization process at power-up sys_reset init_clk init_power_up init_done init_data init_addr addr1 data1 addr2 data2 addrn datan ... ... init_x_wen note: init_x_wen is a generic description of the write enable (or chip select) output signal behavior from flash to the volatile memory. refer to the individual client sections for the exact signal names.
fusion embedded flash memory blocks 5-6 v1.0 clock configuration options the initialization process must operate at a frequen cy of 10 mhz or less. for a synchronous design, the flash module init_clk input should also be connected to the flash initialization client?s clock input pins. the fusion no-glitch mux (ngmux) macro can be used to switch between the slower frequency for the init ialization process (init_clk network) and a higher frequency that will utilize the full performance of th e embedded flash block. figure 5-4 shows an example of ngmux usage in a system design. managing the initialization process for power management the initialization process can be managed to pe rform on-demand context (data) save and reload for power management purposes so critical data will not be lost in sleep or standby low-power modes. when entering a low-power mode, the main system design can perform a context save, for example, from ram to flas h. once the context save is complete, the fpga can be powered off or placed in low-power state without losing its critical data. once the fpga is to resume its normal operation, the initialization proc ess begins performing the context reload operation with the preserved data from the last context save. for a co mplete fusion context sa ve and reload reference design, refer to the context save and reload application note. the flash initialization ip circuitr y has the built-in capability to pe rform the context save and reload operations via the ram initiali zation client and standalone initialization client. the client_update input to the flash module is used to co ntrol the context save operation, and the init_power_up signal is used to control the context reload. the "ram initialization client" section on page 5-10 provides details on performing the context save operation. after fpga power-up, if the init_power_up signal is high, the initialization process will occur, performing the context reload. however, if an on -demand context reload operation is needed in the application, the initialization circuitry can be manipulated to perfor m addition context reload operations without powering the device down. th e key is to clear the in it_done signal so the high init_power_up can trigger a new context re load. this can be achieved by creating a controlled flash sys_reset signal (fla sh_reset). flash_reset should be a registered active-low signal with a reset th at is the main system reset for the design. if fusion?s internal voltage regulator power supply monitor (vrpsm) is being used, a power-on reset pulse can be generated by connec ting a simple external rc circuit to the 3.3 v power supply. for an internal powe r-on reset, if the pll is being used in the design, the pll lock signal can also serve as the fpga system reset. after a system reset, the flash_reset should default to high. once a command is received by the control logic to perform a context reload, the flash_reset signal should be synchronously pu lsed low, clearing the init_done signal and triggering a new initialization process, which performs the context relo ad. the initialization figure 5-4 ? analog system and flash memory block ngmux example clk ngmux slowclk fastclk analog system block pll a c lock b sys_clk flash memory block init_clk init_done
fusion embedded flash memory blocks v1.0 5-7 process will, however, initialize all its clients co nnected to the initializati on interface. the write enable or data valid control sign als to those clients th at should not be updated must be masked to low, preventing the writes from occurring. this is especially recommend ed for the analog system module. refer to the context save and reload application note for complete implementation details. the init_done signal should also be masked to high for the analog system. analog system client when creating the an alog system in libero ide using the analog system builder, a configuration file is generated and its data stored in the sp are pages within the embe dded flash memory during fpga programming. the flash memory analog sys tem client is used to create the memory partitions to store this configuration data. the analog system uses the embedded flash memo ry to hold the nonvolatile configuration data for the analog subsystem. after power-up and during the initialization process, the flash memory is read and the data stored in the analog system?s vo latile register or ram blocks within the analog subsystem. the analog subsystem func tions initialized during the initiali zation process are as follows (if selected during the analog system configuration): ? analog configuration mux (acm) ? programmable real-time counter (rtc) ? adc sample sequence controller (assc) ? system monitor evaluation phase state machine (smev) ? system monitor transition phase state machine (smtr) figure 5-5 ? reset and clock connection diagram for on-demand context reload clk ngmux slowclk fastclk analog system block ram block flash memory block pll a c lock b d clk r q flash_reset control flash_reset sys_reset init_clk sys_reset sys_reset sys_clk rwclk init interface ngmux sel control (a function of init_done)
fusion embedded flash memory blocks 5-8 v1.0 analog system and flash memory interconnects the flash initialization ip circuitry includes a common interface connec ted to all clients, as described in table 5-1 on page 5-3 . however, each client includes interconnects that serve purposes specific to the client, such as the write enab le signals to the analog system register and ram blocks. the write enable signals are active only during the initialization process triggered by the high state of init_power_up and the low state of init_done. table 5-2 describes all analog system client?specifi c signals from the flash initialization ip circuit to the analog system block. table 5-2 ? analog system client-specific flash ports flash port direction description init_acm_rtc_wen output active-high rtc peripheral chip select and write enable control signals from flash to the analog syste m?s rtc volatile registers. after flash sys_reset, init_acm_rtc_wen defaults to low. during the initialization activity, init_acm_rtc_wen synchronously tran sitions with the rising edge of init_clk. once activated, it will remain active until all addresses in the rtc memory space are accessed. no other chip select signals will be activated until the init_acm_rtc_wen activity completes. init_acm_wen output active-high ac m registers? chip select and wr ite enable control signals from flash to the analog system?s acm vola tile registers. after flash sys_reset, init_acm_wen defaults to low. duri ng the initialization activity, init_acm_wen synchronously transitions with the rising edge of init_clk. once activated, it will remain active until all addresses in the acm memory space are accessed. no other chip select signals will be activated until the init_acm_wen activity completes. init_assc_wen output active-high assc memory chip select and write enable control signals from flash to the analog system?s acm ram block. after flash sys_reset, init_assc_wen defaults to low. du ring the initialization activity, init_assc_wen synchronousl y transitions with the ri sing edge of init_clk. once activated, it will remain active until all addresses in the acm memory space are accessed. no other chip select signals will be activated until the init_assc_wen acti vity completes. init_ev_wen output active-high smev memory chip select and write enable control signals from flash to the analog system?s smev ram block. after flash sys_reset, init_ev_wen defaults to low. during the initialization activity, init_ev_wen synchronously transitions with the rising edge of init_clk. once activated, it will remain active until all ad dresses in the smev memory space are accessed. no other chip select signals will be activated until the init_ev_wen activity completes. init_tr_wen output active-high smtr memory chip select and write enab le control signals from flash to the analog system?s smtr ram block. after flash sys_reset, init_tr_wen defaults to low. during th e initialization activity, init_tr_wen synchronously transiti ons with the ri sing edge of init_clk. once activated, it will remain active until all addresses in the smtr memory space are accessed. no other chip select signals will be activated until the init_tr_wen activity completes.
fusion embedded flash memory blocks v1.0 5-9 figure 5-6 is a connection diagram showing the inte rconnects between the fl ash memory and the analog system. if other flash memory clients exist in the system, they will al so be connected to the common initialization interface ports. figure 5-7 is a timing diagram showing the write activi ty from flash memory to the analog system?s assc ram block. at the positive edge of clock, the initialization circuit synchronously generates the address of the data to be written. at the fo llowing positive edge of the clock, the data is produced and init_assc_wen is pulsed high. the init_assc_wen signal to the analog system serves as an assc ram chip select and write enab le. the data is then sync hronously written to the assc ram memory on the next positive edge of the clock. note: the above names represent the actual port name s for the flash and analog system hdl modules. figure 5-6 ? analog system and flash memory initia lization interface connection diagram sys_reset init_clk init_power_up init_done init_data init_addr init_acm_wen init_assc_wen init_ev_wen init_rt_wen sys_reset sys_clk init_done init_data init_addr init_acm_wen init_assc_wen init_ev_wen init_tr_wen 9 9 analog system module flash system module design?s system reset 10 mhz clock init_power_up control signal figure 5-7 ? initialization interface writing to assc ram note: the data write to the assc ram occurs synchronously with the rising edge of the clock. the ram is configured to have a write data bus (dataa) pass-through to the read data bus (qa). init_clk init_power_up init_data init_addr addr1 data1 addr2 data2 addrn datan ... ... init_assc_wen analog_assc_ram_inst/blka analog_assc_ram_inst/dataa a nalog_assc_ram_inst/addressa addr1 data1 addr2 data2 addrn datan ... ... analog_assc_ram_inst/rwa analog_assc_ram_inst/qa data1 data2 datan ...
fusion embedded flash memory blocks 5-10 v1.0 ram initialization client the ram initialization client allows the user to create a flash memory partition to permanently store the ram initialization data. a fter power-up, during the initiali zation process, the data stored in the ram initialization flash me mory partition is read, and its data is written to the ram blocks. the flash memory system builder al lows for multiple ram initializa tion flash memory partitions, giving the designer better flexibili ty over the system design?s critic al data. a jtag read and/or write protection option is also availabl e for each ram initialization client. when creating the ram in libero ide, the ram with initialization option must be selected before generating the ram so the initialization ip is included in the ram bloc k. the ram initialization core?s configuration gui allows for the configuration of both tw o-port and dual-port rams with combined or separate read and write clocks. it also provides the ability to save the ram contents back into flash via the enable on-demand save to flash memory option in the ram with initialization configuration gui. the initialization interface for the ram shares the ram?s clocks; therefore, during the initialization or save-to-flash process, the ram clock frequency must be no greater than 10 mhz. ram and flash memory init ialization interconnects the flash initialization ip circuitry includes a common interface connec ted to all clients, as described in table 5-1 on page 5-3 . however, each client includes interconnects that serve purposes specific to the client, such as th e save-to-flash interface signals of the ram with initialization core ip. these signals are active only during the initialization proc ess triggered by the high state of init_power_up while init_done is low, and duri ng a save-to-flash process triggered by a high state of client_update. table 5-3 describes all signals fro m the flash initialization ip circuit specific to ram with initialization. table 5-3 ? ram with initialization c lient-specific flash ports flash port direction description _x_dat_val output active-h igh data valid signal that behaves as a chip select for the ram client. the number of data valid signals (labeled 0 to x ) depends on the number of ram blocks used to satisfy the ram configuration selected in libero ide. each signal is a 1-bit output port of the flash block. after flash sys_r eset, the data valid signal(s) default to low. _x_dat_val synchronou sly transitions with the rising edge of init_clk during initialization and save-to-flash activity. once activated, it will remain active until all addresses in the ram memory space are accessed. no other chip sele ct signals will be activated until all _x_dat_val activity completes. client_update input active-high control input signal used to trigger the save-to-flash process, which reads data from ram and stores it to flash for context saving. client_update is only available if the enable on-demand save to flash memory feature was selected in the libero ide gui. client_update must be low at po wer-up and held low until the initialization process completes (init_done transitions from low to high with init_power_up held hi gh). to trigger the save-to-flash activity, client_update must be transitioned from low to high synchronously with init_clk. it must be held high until the save-to- flash activity completes (save_ complete pulses high). once complete, client_update must then be transitioned low synchronously with init_clk.
fusion embedded flash memory blocks v1.0 5-11 save_complete output active-high output flag used to identify when the on-demand save- to-flash memory operation comp letes. save_complete is only available if the enable on-demand save to flash memory feature was selected in the libero ide gui. after flash sys_reset, save_complete defaults to low. the save-to-flash activity is triggered by the high state of client_update. once complete, save_complete will transition high and back low synchronously with init_clk. _x_avail input ac tive-high data availabl e input that behaves as a chip-select to the ram-initialization flas h memory partition. the number is data valid signals (labeled ?0? to ?x?) depend on the number of ram blocks used to satisfy the ram configuration sele cted in libero ide. each signal is a 1-bit input port of the flash block. _x_avail is only available if the ?enable on-demand save to flash memory? feature was selected in the libero ide gui . these input(s) can be connected directly to the client_u pdate control input port. _x_avail must be low at power-up an d held low the save to flash activity is tri ggered by the high state of client_update. _x_avail must tr ansition high and held high until the save to flash activity completes. once complete, _x_avail must be transitioned low synchronously with init_clk. _block_x_din in put the 9-bit save-to-flash data bus that supplies the data read from ram to be written to flash. _block_x_din is only available if the enable on-demand save to flash memory feature was selected in the libero ide gui. the number of data busses (labeled 0 to x ) depends on the number of ram bl ocks used to satisfy the ram configuration selected in libero ide. each data bus is a 9-bit input port of the flash block. duri ng save-to-flash activity, _block_x_din synchr onously transitions with the rising edge of the ram block?s rwclk, rclk, or port-b clock (depending on the ram configur ation). after flash sys_reset, _block_x_din defaul ts to 0x000. depending on the client configuration, either all ni ne bits or only the eight least significant bits are utilized as data. table 5-3 ? ram with initialization client-s pecific flash ports (continued) flash port direction description
fusion embedded flash memory blocks 5-12 v1.0 figure 5-8 is a connection diagram showing the inte rconnects between the flash memory and ram initialization ports. if other flash memory clients exist in the system, they will also be connected to the common initializati on interface ports. figure 5-9 is a timing diagram showing the write ac tivity from flash memo ry to the ram block through the initialization interfac e. at the positive edge of the clock, the initialization circuit synchronously generates the address of the data to be written. at the following positive edge of the clock, the data is produc ed and the sram_block_0_dat_val signal is pu lsed high. the sram_block_0_dat_val signal to the ram serves as a chip select and write enable. the data is then synchronously written to the ram on the next positive edge of the clock. figure 5-10 on page 5-13 is a simulation exampl e showing the complete save-to-flash process. to start the process, at the positive edge of the cl ock, client_update is transitioned high. the flash initialization circuit provides th e read address from ram on the positive edge of the clock, as shown in figure 5-11 on page 5-13 . at the following positive edge of the clock, the data is read and put out from initdout0. the flash initialization ci rcuit then stores the data in the page buffer at the next positive edge of the clock. once all data has been r ead from ram and stored in flash, the note: the above names represent the actual port names for the flash and ram hdl modules. figure 5-8 ? two-port ram and flash memory initiali zation interface co nnection diagram sys_reset init_clk init_power_up init_done init_data init_addr reset rwclk initdata initaddr init_client_0 saveactive initdout0 ram module flash system module design?s system reset 10 mhz clock init_power_up_control initactive 9 9 9 sram_block_0_din sram_block_0_avail client_update sram_block_0_dat_val save_complete client_update_control figure 5-9 ? ram initialization process timing detail sram_block_0_dat_val init_clk init_power_up init_data init_addr addr1 data1 addr2 data2 addrn datan ... ... note: the data write to the ram occurs synchronously with the rising edge of the clock.
fusion embedded flash memory blocks v1.0 5-13 save_complete signal is synchronously pulsed high at the positive edge of the clock, holding a high state for several clock cycles. two-port vs. dual-port ram with in itialization clock configurations the ram with initialization core ip can be configured with a sing le clock for both read and write operations, or with separate read and write clocks . since the ram initialization ip blocks share the standard ram clock ports, the 10 mhz maximum freq uency of the initialization interface must be considered when defini ng the system clocks. for both the two-port and dual-port ram with initialization core configurations, if a single read and write clock is selected, the ngmux macro can be used to switch between the slower frequency for the initialization or save-to- flash process and the faster frequ ency used to perform normal ram accesses. figure 5-5 on page 5-7 gives a possible clock configuration using the ngmux as described. for the two-port ram with initiali zation core configuration, if sepa rate read and write clock ports are selected, the write clock port is used by the ra m during the initialization process. if the on- demand save-to-flash feature is enabled, the read clock port is used by the ram during the save-to- flash process, and the read data bus is configured as non-pipelined. for the dual-port ram with initialization core co nfiguration, if the separate port-a and port-b clock option is selected, the port-a clock is us ed to perform the ram wr ite actions during the initialization process. if the on-demand save-to-flash feature is enabled, the port-b clock is used to perform the ram read actions during the save-to-flash process, and the output data bus on port-b is configured as non-pipelined. if on-demand save-to-flash is not enabled, port-b is free to run at any desired frequency within the ram operating range. both the initialization an d save-to-flash processes must operate at a frequency no greater than 10 mhz. the ngmux can be used to switch between a slower and a faster clock. for a synchronous figure 5-10 ? complete save-to-flash process figure 5-11 ? save-to-flash timing details client_update init_clk init_addr sram_block_0_dat_val sram_block_0_din note: the data is read from ram synchronously with the rising edge of the clock. addr1 data1 addr2 data2 addrn datan ... ...
fusion embedded flash memory blocks 5-14 v1.0 design, actel recommends that a common clock source be used for all initialization modules, as shown in figure 5-12 . standalone initialization client the standalone flash memory system initialization ip in itializes all its clients with the data stored in the associated flash memory pa rtition during the initialization process at power-up. the initialization client provides th e ability to create a flash memory partition to initialize a desired block?s volatile memory or registers. once the pa rtition has been created, access is given to the flash memory?s initialization ip interface ports specific to the client?s needs. the flash memory system builder?s in itialization client libero ide gui allows the user to specify the client?s name, starting address, word size, an d memory-contents file. the memory-contents file supplies the initialization data values to be sto red in the client?s flas h memory partition during fpga programming. the user can also select the enable on-demand save to flash memory feature, and protect the flash me mory partition from jtag acce ss. and the user can name the client?s chip select and save request ports. initialization client flash memory ports the flash initialization ip circuitry includes a common interface connec ted to all clients, as described in table 5-1 on page 5-3 . however, each client includes interconnects that serve purposes specific to the client, such as th e save-to-flash interface signals. th ese signals are active only during the initialization process trigge red by the high state of init_p ower_up while init_done is low, and during a save-to-flash process triggered by a high state of client_update. table 5-4 on page 5-15 describes all standalone init ialization client?specific signal s from the flash initialization ip circuit. figure 5-12 ? ram initialization two-clock configuration diagram clk ngmux slowclk fastclk flash memory block pll a c lock b init_clk ngmux sel control (a function of init_done) two-/dual-port ram block rclk/clkb wclk/clka init interface
fusion embedded flash memory blocks v1.0 5-15 table 5-4 ? initialization client -specific flash ports flash port direction description _ output act ive-high chip se lect for the stan dalone initiali zation client. after flash sys_reset, _ defaults to low. during initialization and save-to-flash activity, _ sy nchronously transitions with the rising edge of init_clk. once activated, it will remain active until all ad dresses in the client?s memory space are accessed. no other chip select signals will be activated until the _ activity completes. client_update input active-high control input signal used to trigger the save-to- flash process, which reads data from client and stores it to flash for context saving. client _update is only available if the enable on-demand save to flash memory feature was selected in the libero ide gui. client_update must be low at power-up and held low unt il the initialization process completes (init_done transit ions from low to high with init_power_up held high). to trigger the save-to-flash activity, client_update must be transitioned from low to high synchronously with init_c lk. it must be held high until the save-to-flash activity completes (save_complete pulses high). once complete, client_update must then be transitioned low synchron ously with init_clk. save_complete output active-high output flag used to identify when the on-demand save-to-flash memory operatio n completes. save_complete is only available if the enable on-demand save to flash memory feature was selected in the libero ide gui. after flash sys_reset, save_complete defaults to low. save-to- flash activity is triggered by the high state of client_update. once comp lete, save_complete will transition high and back low synchronously wi th init_clk.
fusion embedded flash memory blocks 5-16 v1.0 initialization client usages the standalone initialization client provides desi gners the utmost flexibilit y, providing access to the flash initialization ip interfa ce to set initial values?for example, for the fusion synchronous fifo, for rom emulation, and for coreabc (amba bus controller) ip instru ction memory space. an initialization wrapper for the initialization clie nts must be generated by the designer (except when used with the coreabc ip). an example of th e initialization wrapper design for the fusion synchronous fifo is described in the "fusion fifo with initializ ation example" section on page 5-17 . to perform rom emulation, the flash memory?s init ialization client and ram blocks are required. a wrapper must be created providing th e flash initialization ip interfa ce write access to the ram. the user interface should only incl ude the read access ports of the ram (raddr, rd, rclk, and ren). depending on the data bus width, proper bus wi dth handling must be take n into consideration in the wrapper design, since th e initialization interface writes nine bits of data per chip select. within the wrapper, the ram write access ports may be set to a default state tying the wen port high. the wclk port should be connected to the 10 mhz initialization clock network. in some cases, the ram with initialization core ip may be the simplest approach for rom emulation. the initialization interface ip is already included in the ram core module. when generating the ram with initialization block, the two-port ram with separate read and write clock ports is a recommended configuration. when crea ting the flash memory ra m initialization client partition, the enable on-demand save to flash memory option should be cleared. all user ram write access ports may be set to a default stat e, tying off the wen port to high. the wclk port should be connected to the 10 mhz initialization clock network. coreabc is a simple, low-gate-cou nt controller that uses the fl ash memory system?s initialization client to initialize at power-up the ram used for instruction code execut ion. a complete design example can be found in the design example section of interfacing with the fu sion analog system: processor/microcon troller interface . _ i nput active-high save re quest input that behave s as a chip select to the initialization client?s flash memory partition. the _ si gnal is only available if the enable on-demand save to flash memory feature was selected in the libero id e gui. these input(s) can be connected directly to the cl ient_update control input port. the _ signal must be low at power-up and held low. save-to-flash activity is triggered by the high state of the client_update signal. the _ signal mu st transition high and be held high until the save-to-flash activity completes. _ must be transitioned low synchronously with init_clk once complete. _din input the 9-bi t save-to-flash data bus th at supplies the data read from initialization client to be written to flash. _din is on ly available if the enable on- demand save to flash memory feature was selected in the libero ide gui. during th e save-to-flash activity, _din synchronou sly transitions with the rising edge of init_clk . after flash sys_reset, _din should defa ult to 0x000. depending on the client configuration, either all nine bits or only the eight least significant bits are utilized as data. table 5-4 ? initialization clie nt-specific flash ports (continued) flash port direction description
fusion embedded flash memory blocks v1.0 5-17 fusion fifo with initialization example when creating the fifo wi th initialization design, the flash memory initialization client and synchronous fifo blocks are requ ired. a wrapper must be created providing the flash initialization ip interface write access to the fifo, and the save -to-flash interface read access. depending on the data bus width, proper bus width handling must be taken into consideration in the wrapper design, since the initializati on interface writes nine bits of data per chip select. figure 5-13 shows the selected synchronous fifo conf iguration used in this example. figure 5-13 ? synchronous fifo configuration
fusion embedded flash memory blocks 5-18 v1.0 the flash memory system builder?s initialization client is used to generate the flash memory partition for the fifo. figure 5-14 shows the required initializati on client configuration based on the fifo configuration shown in figure 5-13 on page 5-17 . once the flash memory block with the fifo init ialization partition ha s been generated, the following initialization ports, given in verilog, are added to the flash block: input init_clk; input sys_reset; input init_power_up; output init_done; output [8:0] init_data; output [7:0] init_addr; output fifo_init_cs; input fifo_init_savereq; input [8:0] fifo_init_din; output save_complete; input client_update; figure 5-14 ? initialization client configuration for the fifo
fusion embedded flash memory blocks v1.0 5-19 the fifo with initialization interface wrapper must connect to the abov e ports. the init_addr port is not used in this design, since the flash block is being interfaced to a fifo. figure 5-15 shows the connections between the flash block and the fifo with initialization wrapper. the fifo with initialization wrapper design sh ould multiplex the contro l signals from the flash memory?s initialization ci rcuit with the fifo?s user access ports for a dual read and write access fifo configuration. the following, given in verilog, describes the main wrapper design: assign fifo_data = (init_power_up & !init_done) ? init_data[7:0] : data; assign fifo_wen = (init_power_up & !init_done) ? !fifo_init_cs : we; assign fifo_ren = client_update ? !fifo_init_cs : re; assign init_dout = {1'b0,q}; fifo u_fifo( .data(fifo_data), .q(q), .we(fifo_wen), .re(fifo_ren), .wclock(wclock), .rclock(rclock), .full(full), .empty(empty), .reset(reset), .aempty(aempty), .afull(afull)); note: the above names represent the actual port names for the flash and fifo hdl modules. figure 5-15 ? fifo with initialization interface connection diagram sys_reset init_clk init_power_up init_done init_data init_addr reset wclock init_data fifo memory module with initialization flash system module design?s system reset init_power_up control client_update 9 9 9 fifo_init_din fifo_init_savereq client_update fifo_init_cs save_complete client_update control rclock init_power_up init_done fifo_init_cs init_dout we re data q empty full aempty afull 8 8 clk ngmux slowclk fastclk pll a c lock b ngmux sel control (a function of init_done)
fusion embedded flash memory blocks 5-20 v1.0 figure 5-16 is a simulation example showing the fifo?s complete initialization process. a high state on init_power_up while init_done is low will tri gger the initialization process. during this process, the fifo should be in an empty state. th e fifo_init_cs signal is pulsed with the positive edge of the clock when a fifo write operation should occur, as shown in figure 5-17 . with every high state of fifo_init_cs, init_d ata has valid data to be writte n into the fifo. at the positive edge of the clock while fifo_init_cs is high, the data is synchronously written. once all data values have been written into the fifo, the fifo?s afull flag and the flash memory?s init_done signals synchronously transition high. the user mu st take care not to access the fifo via the user access ports or the save-to-flash interfac e unless the init_done signal is high. figure 5-18 on page 5-21 is a simulation example showing the fifo?s complete save-to-flash process. to start the proc ess, client_update is transitioned high at the positive edge of the clock. figure 5-16 ? complete fifo initialization process figure 5-17 ? fifo initialization write operation timing details sys_clock fifo_init_cs init_power_up fifo_data init_data init_addr fifo_wen note: the data write into the fifo occurs synchronously with the rising edge of the clock. empty full aempty afull addr1 = 0x00 data1 addr2 = 0x01 data2 ... ... datan data1 data2 ... datan addrn
fusion embedded flash memory blocks v1.0 5-21 however, the user must take care not to activate client_update while init _done is low or if the fifo is not full. the afu ll flag should be used to monitor the filled state of the fifo, since the full flag will not transition high unless the entire physical fifo memory has been filled. in this example, although the fifo is configured as 2568 and all loca tions are written, the fifo4k18 macro is instantiated for this conf iguration. the fifo_init_cs signal is pulsed with the positive edge of clock when a fifo read op eration should occur, as shown in figure 5-19 . once all data values have been read from the fifo and stored in flash, the fifo empty signal and the flash memory save_complete signal are synchronously transitioned high at the positive edge of the clock. the save_complete sign al will hold a high state fo r several clock cycles before transitioning low. figure 5-18 ? complete fifo save-to-flash process figure 5-19 ? fifo save-to-flash read operation timing details sys_clock fifo_init_cs client_update q init_dout init_addr fifo_ren *note: the data is read from the fifo synchronously with the rising edge of the clock. empty full aempty afull addr1 = 0x00 data1 addr2 = 0x01 data2 addr(n ? 1) data(n ? 1) ... ... datan ... data1 data2 data(n ? 1) ... datan ... addrn ...
fusion embedded flash memory blocks 5-22 v1.0 using the embedded flash memory for general data storage a key feature of the embedded flash memory is its ab ility to be used as general data storage by the fpga fabric. the nonvolatile nature of the flas h allows for permanent storage of the design system?s key parameters and variables. fusion?s em bedded flash memory blocks can be instantiated in a design for general data st orage via the following methods: ? the embedded flash memory macro can be instan tiated directly into the rtl design in text or through smartdesign. ? the flash memory system builder?s data stor age client in libero ide can be used to configure the embedded flash memory to be used for general-purpose data storage. ? coreconsole idp can be used to interface the embedded flash me mory with the common flash interface via the corecfi ip. the flash memo ry system builder in li bero ide is then used to configure the embedded flash me mory to be paired with corecfi. the following sections discuss th e basic flash memory operations available to fusion?s embedded flash memory, and its three general data storage usages. details related to the silicon implementation of the embedded flash memory bl ock, including timing characteristics, can be found in the fusion family of mixe d-signal flash fpgas datasheet. flash memory macro and interface fusion contains up to four embedded flash memory blocks, each 2 mbits in density. in an rtl design, a single embedded flash memory block corresponds to a single instance of the embedded flash memory block (nvm) macro. the embedded flas h memory block is referenced as ?fb? in this section and in the fusion family of mixe d-signal flash fpgas datasheet. however, the macro used to instantiate an embedded flash memory bl ock in a design is named ?nvm? and will be referenced as such thro ughout this section. the nvm macro can be instantiated directly into an rtl design without th e intervention of libero ide?s flash memory system builder. with the except ion of a reset operation, all operations on an nvm instance are synchronous to the rising edge of the clock. table 5-5 contains a complete list of the input and output po rts for the nvm macro. table 5-5 ? flash block macro port descriptions flash port direction description reset input asynchronous active-low reset i nput signal. holds the flash block?s control logic in an initial state until released. clk input flash memory input clock whose maximum clock period is dictated by t mpwclknvm . all memory operations and stat us are synchronous to the rising edge of this clock. addr[17:0] input the 18-bit byte-based flash block input address bus. addr must transition synchronously with the rising edge of clk. the minimum addressable data size is 8 bits. for a data width of 16 bits, addr[0] is ignored and addr[1] becomes the lowest-order address; for a data width of 32 bits, addr[1:0] is ignored and addr[2] becomes the lowest-order address. wen input active-high write enable control inpu t signal used for wr iting data into the flash memory page buffer. wen must tran sition synchronousl y with the rising edge of clk. program input active-high program operation control input signal used for writing the contents of the page buffer into the flash memory array page addressed. program must transition synchronou sly with the rising edge of clk. ren input active-high read enable control in put signal used for read data from the flash memory array, page buffer, block buffer, or status registers. ren must transition synchronously with the rising edge of clk.
fusion embedded flash memory blocks v1.0 5-23 readnext input active-high read-n ext operation control input si gnal. this feat ure loads the next block relative to that stored in the block buffer fr om the flash memory array while reads from the block buffer are being performed. readnext must be asserted along with ren to in itiate the read-nex t operation, and must transition synchronously wi th the rising edge of clk. rd[31:0] output the 32-bit output read data bus. the data on rd transitions synchronously with the rising edge of cl k. after ren has been asserted, issuing a data read operation, all data must be sampled from rd when busy is not asserted (when low). data put out on rd are lsb-oriented. upon a reset, rd is initialized to zero. wd[31:0] input the 32-bit input write data bus. data put in on wd must be lsb-oriented; any unused pins must be grounded or driven low. the data on wd must transition synchronously with the rising edge of clk. datawidth[1:0] input the 2-bit rd and wd data bus width control input signal. datawidth must transition synchronously with the rising edge of clk. ? if datawidth is '00', the data bu sses contain one byte of data forming an 8-bit word (rd/wd[7:0]). ? if datawidth is '01', the data busse s contain two bytes of data forming a 16-bit word (rd/wd[15:0]). ? if datawidth is '1x', the data busse s contain four bytes of data forming a 32-bit word (rd/wd[31:0]). pipe input active-high pipeline stage contro l input signal. when asserted, a pipeline stage is added to the read data outp ut. read operations complete in five cycles instead of the ty pical four. the ad dition of the pipeline stage is recommended to be used for clk frequencies greater than 50 mhz. pipe must transition synchronously with the rising edge of clk and be asserted along with ren. pagestatus input active-high page status contro l input signal. when asserted, a page status read operation is initiated. pagestat us must transition synchronously with the rising edge of clk and be asserted along with ren. erasepage input active-high page erase control input signal asserted when the addressed page is to be programmed with al l zeros. erasepage must transition synchronously with the rising edge of clk. discardpage input active-high discard page control input signal asserted when the contents of the page buffer are to be discarded so that a new page write can be started. discardpage must transition synchronou sly with the rising edge of clk. auxblock input active-high auxiliary block sele ct input signal asserted when the page address is used to access the auxiliary block within the page addressed. auxblock must transition synchronously with the rising edge of clk. sparepage input active-high spare page sele ct input signal asserted when the sector addressed is used to access the spar e page within that sector. sparepage must transition synchronously wi th the rising edge of clk. unprotectpage input active-high unpr otect page control input signal used to clear the protection of the addressed page. unprotectpage must transition synchronously with the rising edge of clk. table 5-5 ? flash block macro port descriptions (continued) flash port direction description
fusion embedded flash memory blocks 5-24 v1.0 below are the verilog and vhdl representations of an nvm macro instan tiation. for simulation purposes, the nvm macro may reference an actel memory file used to preload the memory with user-defined data. this is achi eved by overriding the memoryfi le parameter in the simulation model during the nvm instantiatio n. the following is the nvm macro instantiation in verilog and vhdl with the memoryfi le parameter override. overwritepage input active-high overwrite page control input signal asserted when the page addressed is to be overwritten, if writable, with the contents of the page buffer. overwritepage must transition synchronously with the rising edge of clk and must be asse rted along with program. overwriteprotect input active-high overwrite protect control input signal used to change the protection bit of the addressed page . overwriteprotect must transition synchronously with the rising edge of clk and must be asserted along with program or erasepage. pagelossprotect input active-high page-loss protect control input signal used to prevent writes to any other page except the current addr essed page in the page buffer, until the page is either discarded or programmed. pagelossprotect must transition synchronously with the rising edge of clk and be asserted along with program or erasepage. lockrequest input active-high lock request con trol input signal asse rted when user access (including jtag) to the fl ash memory array is to be prevented. lockrequest must transition synchronously wi th the rising edge of clk. busy output active-high busy control output signal used to indicate when the flash memory is performing an operation. bu sy transitions sync hronously with the rising edge of clk. upon a reset, bu sy pulses high for several cycles before settling to a low state. status[1:0] output the 2-bit flash memory operatio n status output signals used to indicate the status of the last completed operatio n. status transitions synchronously with the rising edge of clk. upon a reset, status is initialized to 0x00. ? when status is '00', it indicate s that the last operation completed successfully. ? when status is '01' after a read oper ation, it indicates that a single error was detected during the last comp leted operation and was corrected. ? when status is '01' after a write operation, it indicates that the last completed operation addressed a write-protected page. ? when status is '01' after an erase- page/program operation, it indicates that the page buffer was unmodified during the last completed operation. ? when status is '10' after a read op eration, it indicates that two or more errors were detected during the last completed operation. ? when status is '10' after an erase- page/program operation, it indicates that the compare operation failed du ring the last completed operation. ? when status is '11' after a write ope ration, it indicates that the attempt to write to another page before programming the current page was made during the last completed operation. table 5-5 ? flash block macro port descriptions (continued) flash port direction description
fusion embedded flash memory blocks v1.0 5-25 verilog nvm macro instance nvm u_nvm ( .clk (clk), .reset (reset), .addr (addr), .ren (ren), .wen (wen), .readnext (readnext), .erasepage (erasepage), .program (program), .datawidth (datawidth), .rd (rd), .wd (wd), .busy (busy), .status (status), .sparepage (sparepage), .auxblock (auxblock), .unprotectpage (unprotectpage), .discardpage (discardpage), .overwriteprotect (overwriteprotect), .pagelossprotect (pagelossprotect), .pagestatus (pagestatus), .overwritepage (overwritepage), .pipe (pipe), .lockrequest (lockrequest) ); verilog nvm macro instance with memory file nvm #( .memoryfile(".mem") u_nvm ( ... ); vhdl nvm macro instance with memory file architecture def_arch of is component nvm generic (memoryfile:string := ""); port( ... ); end component; begin nvm_inst : nvm generic map(memoryfile => ".mem") port map( ... ); end def_arch;
fusion embedded flash memory blocks 5-26 v1.0 the memory array declared in the simulation model stores data that is one block wide. it is 64k140 bits. the addressing scheme fo r accessing this array consists of 16 bits, as shown in figure 5-20 . addr[17:0] is the embedded fl ash memory interface address; sparepage and auxblock are input signals. the me mory file for preloading the flash array consists of strings of address and data in hexadecimal notation with ad dress delimiters (?@?), and must conform to the rules given below: 1. each line must contain a string of fixed leng th (35 characters) and sta rt with an ?@? if it corresponds to an address. 2. each line following the address line corresponds to a block of data starting at the block address specified in the address line. this applie s until the next line with an address specifier (?@?) is encountered. 3. each data block consists of 35 hex charac ters. hex[31:0] are the data characters corresponding to 16 bytes of user data, where hex[1:0] corresponds to byte0 and hex[31:30] corresponds to byte15. hex[34: 32] are ecc-related bits and must be addressed manually. based on these rules, the form at looks like the following: @block_address_0 block_data_0 ( required ) block_data_1 ( optional ) block_data_2 ( optional ) ... ... block_data_8 ( aux block data for this page, optional ) @block_address_n block_data_n ( required ) block_data_n+1 ( optional ) block_data_n+2 ( optional ) ... ... ... block_data_n+8 ( aux block data for this page, optional ) a typical memory file looks like the following: @000...0000 // beginning with @, start address in hex format. 0s to be padded // between @ and hex address to get a string of length 35. ab101fd01... // 35 hexadecimal characters corresponding to each block of flash memory // block cell eab9c4...... @0004030.... // start address for next data stream c805489e.... // 35 hexadecimal characters corresponding to each block of flash memory // block cell 96986391 figure 5-20 ? addressing scheme for access ing the flash memory array block addr page addr sector addr addr[17:12] sparepage addr[11:7] auxblock addr[6:4]
fusion embedded flash memory blocks v1.0 5-27 data storage client interface the flash memory system builder?s data storage clie nt in libero ide can be used to configure the embedded flash memory to be used as genera l-purpose data storage. the data storage client allows the user to create a flash memory partit ion, configure the addres s and data busses, and select an initialization file containing the flash array?s initial values. jtag read and/or write protections can also be added to prevent extern al access to the embedded flash memory array contents. figure 5-21 shows the data storage configuration window in libero ide. the data storage client spans a minimum of one pa ge (128 bytes) and can go up to 2,048 pages, depending on the number of free pages available. the starting address for the data storage client must be set to a value along the page boundaries?e .g., 0x00, 0x80, 0x100, etc. the word size for the read and write data busses can be either 8, 16, or 32 bits. the total number of words can be anywhere from one to 262,144 for 8-bit words, one to 131,072 for 16-bit words, and one to 65,536 for 32-bit words. once the data storage cl ient configuration is complete and th e flash memory system builder?s ip is generated, the user can then in stantiate the embedded flash memo ry system in the design. the overall ports list for the embedded flash memory system module may vary depending on the total number of clients added to the fl ash memory system. refer to the "using the embedded flash memory for initialization" section on page 5-1 and the "common flash interface data client" section on page 5-31 for additional details regarding the other clients available in the flash memory system builder. table 5-6 on page 5-28 describes the data storage client?specific ports. figure 5-21 ? data storage client configuration window
fusion embedded flash memory blocks 5-28 v1.0 table 5-6 ? data storage client?spe cific port descriptions flash port direction description user_reset input asynchronous active-low reset input signal. holds the flash block?s control logic in an initial state until released. user_clk input flash memo ry input clock whose maximum clock period is dictated by t mpwclknvm . all memory operations and status are synchronous to the rising edge of this clock. user_add[17:0] input the 18-bit byte-based flash block in put address bus. user_add must transition synchron ously with the rising edge of user_clk. for a data width of 16 bits , user_add[0] is ignored and user_add[1] becomes the lowest -order address; for a data width of 32 bits, user_add[1:0] is ignored and user_add[2] becomes the lowest-order address. user_write input active-high write enable control input signal used for writing data into the flash memory page buffer. user_write must transition synchronousl y with the rising edge of user_clk. user_program input active-high program operation control input signal used for writing the contents of the pag e buffer into the flash memory array page addressed. us er_program must transition synchronously with the ri sing edge of user_clk. user_read input active-high read enable co ntrol input signal used for read data from the flash memory array, page buffer, block buffer, or status registers. user_read must transi tion synchronously with the rising edge of user_clk. user_read_next input active-high read-next operation control input signal. this feature loads the next block relative to that stored in the block buffer from the flash memory array whil e reads from the block buffer are being performed. user_read_ next must be asserted along with user_read to initiate th e read-next operation, and must transition synchronousl y with the rising edge of user_clk. user_dout[7:0], [15:0], or [31:0] ou tput the 8-, 16-, or 32-bit output read data bus. the data on user_dout transitions synchronou sly with the rising edge of user_clk. after user_read has been asserted issuing a data read operation, all data must be sampled from user_dout when user_nvm_busy is not asserted (when low). data put out on user_dout are lsb-oriented. upon a reset, rd is initialized to zero. upon a user_reset, rd is initialized to zero. user_data[7:0], [15:0], or [31:0] input the 8-, 16-, or 32-bit input write data bus. data put in on user_data must be lsb-oriented; any unused pins must be grounded or driven low. the data on user_data must transition synchronousl y with the rising edge of user_clk.
fusion embedded flash memory blocks v1.0 5-29 user_width or user_width[1:0] input the 1- or 2-bit user_dout and user_data data bus width control input signal. datawidth must transition synchronously with the rising edge of user_clk. ? if user_width is '00', the data busses contain one byte of data forming an 8-bit word (user_dout/user_data[7:0]). ? if user_width is '01', the data busses contain two bytes of data forming a 16-bit word (user_dout/user_data[15:0]). ? if user_width is '1x', the data busses contain four bytes of data forming a 32-bit word (user_dout/user_data[31:0]). for a 1-bit user_width: if user_w idth is 1, the data busses are 16 bits wide; otherwise, they are 8 bits wide. user_page_status input active-high page stat us control input signal. when asserted, a page status read operation is initiated. user_page_status must transition synchronously with the rising edge of user_clk and must be asserted along with user_read. user_erase_page input active-high page eras e control input signal asserted when the addressed page is to be programmed with all zeros. user_erase_page must transition synchronously with the rising edge of user_clk. user_discard_page input active-high discard page control input signal asserted when the contents of the page bu ffer are to be discarded so a new page write can be started. user_discard_page must transition synchronously with the ri sing edge of user_clk. user_overwrite_page input active-high overwrit e page control input signal asserted when the page addressed is to be over written, if writable, with the contents of the pag e buffer. user_overwrite_page must transition synchronously with the rising edge of user_clk and must be asserted alon g with user_program. user_aux_block input active-high auxiliary block select input signal asserted when the page address is used to access the auxiliary block within the page addressed. user_aux_block mu st transition synchronously with the rising edge of user_clk. user_spare_page input active-high spare page select input signal asserted when the sector addressed is used to ac cess the spare page within that sector. user_spare_page must transition synchronously with the rising edge of user_clk. user_unprot_page input active-high unprotect page control input signal used to clear the protection of the addressed page. user_unprot_page must transition synchronousl y with the rising edge of user_clk. user_overwrite_prot input active-high overwrite protect control input signal used to change the protection bit of the addressed page. user_overwrite_prot must transi tion synchronously with the rising edge of user_clk and must be asserted along with user_program or user_erase_page. table 5-6 ? data storage client?specific port descriptions (continued) flash port direction description
fusion embedded flash memory blocks 5-30 v1.0 user_pageloss_prot input active -high page-loss protect con trol input sign al used to prevent writes to any other pa ge than the current addressed page in the page buffer, until the page is either discarded or programmed. user_pagelo ss_prot must transition synchronously with the rising edge of user_clk and must be asserted along with user_p rogram or user_erase_page. user_lock input active-high lock request control input signal asserted when user access (including jtag) to the flash memory array is to be prevented. user_lock must tran sition synchronously with the rising edge of user_clk. user_nvm_busy output active-high busy control output signal used to indicate when the flash memory is performing an operation. user_nvm_busy transitions synchronously with the rising edge of user_clk. upon a user_reset, user_nvm_b usy pulses high for several cycles before settling to a low state. user_nvm_status[1:0] output the 2-bit flash memo ry operation status output signals used to indicate the status of the last completed operation. user_nvm_status transitions synchronously with the rising edge of user_clk. upon a us er_reset, user_nvm_status is initialized to 0x00. ? when user_nvm_statu s is '00', it indicates that the last operation completed successfully. ? when user_nvm_status is '01' after a read operation, it indicates that a single error was detected during the last completed operation and was corrected. ? when user_nvm_status is '01' after a write operation, it indicates that the last comp leted operation addressed a write-protected page. ? when user_nvm_status is '01' after an erase-page/program operation, it indicates that the page buffer was unmodified during the last completed operation. ? when user_nvm_status is '10' after a read operation, it indicates that two or more errors were detected during the last completed operation. ? when user_nvm_status is '10' after an erase-page/program operation, it indicates that the compare operation failed during the last completed operation. ? when user_nvm_status is '11' after a write operation, it indicates that an attempt to write to another page before programming the current page was made during the last completed operation. table 5-6 ? data storage client?specific port descriptions (continued) flash port direction description
fusion embedded flash memory blocks v1.0 5-31 common flash interface data client the corecfi ip is available to designers through actel?s coreconsole idp. corecfi provides an industry-standard interface to th e embedded flash memory blocks within the fusion family of fpgas. the corecfi ip module is targeted to provide a functional subset of the common flash interface standards with a design emphas is given to minimizing design size. using coreconsole idp to genera te the corecfi ip hdl code, us ers must perform the following steps: 1. open coreconsole idp through libero ide and add corecfi to the coreconsole project. 2. configure the corecfi ip. figure 5-22 shows the corecfi ip configuration gui window in coreconsole. the fpga family selected must be fusion. the size (address width) can be 6 to 18 bits. the number of address bits selected indicates the amount of the embedded flash memory accessible through corecfi?e.g ., 10 bits = 1 kb, 12 bits = 4 kb, 18 bits = 256 kb. 3. using the auto-stitch to top level feature of coreconsole, bring all ports to the top on the block so that corecfi can be interfaced to the embedded flash memory module and other controlling circuits. once the corecfi ip is configured, use the save and generate function to deploy the hdl code and other related files, including the query data memory file. the query data memory file contains the actel-specific 16-bit command set and control inte rface id code as well as the embedded flash memory parameters and interface co nfiguration data. refer to the coreconsole user?s guide and corecfi handbook for additional co nfiguration details. the flash memory system builder?s cfi data client in libero ide is used to store the query data for the corecfi ip into the reserved (spare) pages of the embedded flash memory. this client does not take up any of the 2,048 pages avai lable to designers for initializati on or general data storage use. figure 5-23 on page 5-32 shows the cfi data client configurat ion window in libero ide. using the dialog box, the location of the query data memory file generated by coreconsole during corecfi ip figure 5-22 ? corecfi ip configuration window
fusion embedded flash memory blocks 5-32 v1.0 deployment must be specified. th e memory file format is actel bi nary and should not be modified by the user. coreconsole deploys the query data me mory file to the following directory location: c:\actelprj\\coreconsole\common \corecfi\rtl\vlog\test\user\corecfi_query.mem during corecfi ip deployment, coreconsol e generates a sample hdl top file, named corecfi_chip , that instantiates both corecfi and th e embedded flash memory system. figure 5-24 illustrates an example corecfi ip system, comple te with all interconnects betw een the main system blocks. the interface between corecfi and the embedded flas h memory is through the data storage client interface ports, as listed in table 5-6 on page 5-28 . table 5-7 on page 5-33 describes the corecfi- specific ports. figure 5-23 ? cfi data client configuration window figure 5-24 ? corecfi ip system diagram 1?b0 1?b1 18 32 32 2 2 18 32 internal/external microprocessor with cfi corecfi ip nvm_address nvm_page_status nvm_data_in nvm_discard_page nvm_erase_page nvm_overwrite_protect nvm_program nvm_read nvm_unprotect_page nvm_data_width nvm_write nvm_data_out clk rp_n a ce_n dq_in we_n ry_by_n word_n oe_n dq_oe_n byte_n dq_out nvm_busy nvm_status nvm_spare_page embedded flash memory system embedded flash memory (preloaded with corecfi_query.mem) data storage client interface user_clk user_reset user_add user_aux_block user_data user_discard_page user_erase_page user_overwrite_page user_overwrite_prot user_pageloss_prot user_program user_read user_read_next user_lock user_spare_page user_unprot_page user_width user_write user_dout user_nvm_busy user_nvm_status user_page_status
fusion embedded flash memory blocks v1.0 5-33 table 5-7 ? corecfi-specific port descriptions corecfi port direction description rp_n input asynchronous active-low reset input signal that holds corecfi in an initial state until released. it is recommended that rp_n not be asserted while ry_by_n is asserted; otherwise, the embedded flash memory may be damaged. when rp_n is asserted, corecfi is placed in read array mode, the sta tus register is set to 0x80 (ready), and the data bus ports are tristated. clk input flash memory input clock whose ma ximum clock period is dictated by t mpwclknvm . all operations and status are synchronou s to the rising ed ge of this clock. ce_n input active-low chip enable control input signal. when asserted, corecfi is enabled. ce_n must transition synchronously with the rising edge of clk and must be asserted along with we_n. we_n input active-low write enable control input signal used to initia te a write operation. we_n must transition synchronously with the rising edge of clk and must be asserted along with ce_n. if ce_n and we_n are not both asserted, the write command will be ignored. a write command takes one clock cycle to execute; both ce_n and we_n must be deasserted upon completion. oe_n input active-low output enable control input signal used to contro l the direction of the cfi bidirectional data bus, and asserted during a read co mmand. however, the bidirectional cfi data bus as listed in the cfi specification is sp lit into an input data bus (dq_in) and an output data bus (dq_out) in corecfi. the bidirectional cfi data bus must be formed outside of corecfi, wh ere the direction control signal is an output of corecfi (dq_oe_n), as shown in figure 5-24 on page 5-32 , and is a function of oe_n. oe _n must transition sy nchronously with the rising edge of clk and must be asserted along with ce_n. if ce_n and oe_n are no t both asserted, the read command will be ignored. a[17:0] input active-hi gh 18-bit input address bus used to ad dress a location in the flash array during a command execution. for a data wi dth of 16 bits, a[0] is ignored and a[1] becomes the lowest-order address; for a data width of 32 bits, a[1:0] is ignored and a[2] becomes the lo west-order address. word_n input the 2-bit {word_n, byte_n} data bus width control input signal. both word_n and byte_n must transition synchronously with the rising edge of clk and must be asserted together. ? if 'x0', the data bus contains one byte of data forming an 8-bit word (dq_in/out [7:0]). ? if '01', the data bus contains two bytes of data forming a 16-bit word (dq_in/out [15:0]). ? if '11', the data bus contains four bytes of data forming a 32-bit word (dq_in/out [31:0]). byte_n input dq_oe_n output active-low output enable control output signal used to control the direction of the cfi bidirectional data bus formed extern al to the corecfi ip, as shown in figure 5-24 on page 5-32 . dq_oe_n transitions synchronously wi th the rising edge of clk and is asserted when both ce_n and oe_n are asserted. upon an rp_n assertion, dq_oe_n is initialized to zero.
fusion embedded flash memory blocks 5-34 v1.0 corecfi supports the read query, read, automatic eras e, automatic write, lock, and status cfi operations. the command desc riptions are summarized in table 5-8 and table 5-9 on page 5-35 . refer to the corecfi handbook (available on the actel website or in coreconsole) for the cfi command details. dq_in[31:0] input the 32-bit input data bus used during a write command. the data on dq_in must transition synchronously with the rising edge of clk. data put in on dq_in must be lsb-oriented. configuration de pends on the state of {wor d_n, byte_n}: if in the 8-bit word mode, the dq_in[31:8] ports are ignored; if in the 16-bit word mode, the dq_in[31:16] ports are ig nored. as shown in figure 5-24 on page 5-32 , dq_in should be connected to the cfi bidirectional bus. dq_out[31:0] output the 32-bit output data bus used during a read command. the data on dq_out transitions synchronously with the rising edge of clk. data put out on dq_out is lsb-oriented. configuration de pends on the state of {wor d_n, byte_n}: if in the 8-bit word mode, the dq_out[31:8] ports ar e ignored; if in th e 16-bit word mode, the dq_out[31:16] ports are ignored. as shown in figure 5-24 on page 5-32 , dq_out should be connected to the cfi bi directional bus. upon an rp_n assertion, dq_out is initialized to zero. table 5-7 ? corecfi-specific port descriptions (continued) corecfi port direction description table 5-8 ? supported cfi command descriptions command description read query the read query command causes corecfi to load the query database from a spare page of the embedded flash memory. query data is always supplied on the least significant 8 bits of dq_out. the address of the query data starts at 10h in 32-bit, 20h in 16-bit, or 40h in 8-bit mode. read id codes the read id codes command causes corecfi to load either the manufacturer code, die size code, or page lock status fr om the embedded flash memory onto dq_out. the identifier codes returned are either values stored in the query data spare page or the lock status of a page in the flash array. read array the read array command causes corecfi to be placed in read arra y mode, where the content of the addressed location of the flash array is loaded onto dq_out. upon a reset, corecfi is initialized to the read array mode state. read status the read status command causes corecfi to load the status register onto dq_out. the status register provides the status of the last wr ite, erase, or lock command execution. clear status the clear status command causes co recfi to clear register ed status register bits. erase page the erase page command ca uses corecfi to erase the addressed page of the flash array. a page erase activity fills the co ntents of a page with zeros. single write the single write command causes corecfi to write the data placed on dq_in to the addressed location of the flash array. this command re ads the entire addressed page, modifies the address location, and programs the page into the flash array. if more than one location is to be modified, the multiple write command should be used. multiple write the multiple write command causes corecfi to be placed in the page write mode, where the contents of dq_in are written to the page buffer of the embedd ed flash memory. if the write activity exceeds the page boundary, the data writ ten will wrap to the top of the page. once all values are written into the page, the page is written into the flash array. page lock the page lock command ca uses corecfi to lock the addressed page, preventing any erase or write commands to the page from executing. page unlock the page un lock command causes corecfi to unlock the addressed page, allowing all erase or write commands to the page to execute.
fusion embedded flash memory blocks v1.0 5-35 flash operation priority the embedded flash memory has a built-in priority for operatio ns when multiple actions are requested simultaneously. table 5-10 shows the operation priority order?priority 0 is the highest. access to the embedded flash memory is controll ed by the busy (user_busy in the data storage client interface) signal. the busy output is synchronous to the clk (user_clk in the data storage client interface) signal. the embedd ed flash memory operations are only accepted in cycles where busy is not asserted (low). the system initialization operation is the highest in the priority order. the system initialization occurs upon a system reset of a fusi on fpga. all fpga operations should be halted during the system initialization process. refer to the "using the embedded flash memory for initialization" section on page 5-1 for additional information. if read and write operations ar e performed simultaneously, for exam ple, the read operation takes precedence over the write operation. the write data supplied during this operation is ignored, and the data remains unchanged. also, if an erase page and a write operation are performed table 5-9 ? cfi command algorithm summary command no. of bus cycles first bus cycle second bus cycle operatio naddress dat a operatio naddress data read query 2 write x 0x98 read query address query data read id codes 2 write x 0x90 read identifier address identifier data read array 1 or 2 write x 0xff read array address array data read status 2 write x 0x70 read x status data clear status 1 write x 0x50 ? ? ? erase page 2 write page address 0x20 write page address d0h single-write 2 write page address 0x40 write array address array data multi-write 2 write page address 0xe8 write page address n = num. of elements ? 1 page lock 2 write x 0x60 write page address 0x01 page unlock 2 write x 0x60 write page address 0xd0 table 5-10 ? flash memory operation priority operation priority system initialization 0 (highest) flash memory reset 1 read 2 write 3 erase page 4 program 5 unprotect page 6 discard page 7
fusion embedded flash memory blocks 5-36 v1.0 simultaneously, the write operation takes preceden ce over the erase page operation. the write data supplied during this operation executes. all other priority order situations behave similarly. flash busy signal handling the busy (user_busy in the data storage client interface) signal is one of the most important signals in the embedded flash memory; all oper ations on the embedded flash memory should be designed based on the busy signal. the busy sign al is asserted high whenever a flash operation is in progress, then deasserted after the operation is complete. to shorten simulation run time, the run time of the different operat ions (write/program/erase/read) is shortened in the simulation model. therefore, the system desi gn should be based on the busy signal assertion and deassertion status instead of counting the operation cycles for each oper ation. all flash memory inputs are ignored while busy is asserted. inputs can be upda ted for the next operation at the rising edge of the clock with no ho ld time requirement. during an embedded flash memory reset, the co ntents of the flash memo ry control logic block, such as the contents of the block buffer and page buffer, are cleared. once reset (user_reset in the data storage client interface) is asserted low, the busy signal is asserted high. after reset is deasserted, the busy sign al is deasserted approximately 25 s later. therefore, the system design should accommodate this busy peri od by monitoring the busy sign al status. all operations can be executed only after the bu sy signal is deasserted. for continuous operations, like the continuous read s for microprocessor ins truction executions, the flash clock may be adjusted to compensate fo r the flash memory busy period?for example, during the loading of a new page from the flash array into the page buffer. typically, the flash clock is sourced by the microprocessor system clock in an application. smarttime, actel?s gate-level static timing analysis tool avai lable in actel?s designer soft ware, will provide the maximum frequency for the system design. this maximum frequency will be ad justed to compensate for these busy periods.
fusion embedded flash memory blocks v1.0 5-37 write operations and page programming the embedded flash memory offers a write op erations class of commands. these commands include the page buffer write, discard page, program page, erase page, and overwrite page operations. all write commands are page-based operations. the embedded flash memory write operations modify the contents of both the block and page buffers. as shown in figure 5-25 , the block and page buffers are sub-blocks of the embedded flash memory and consist of volatile registers. a write operation to a location in a page that is not already in the page buffer will cause the page to be read from the flash array an d stored in the page buffer. the number of busy cycles required to complete the page buffer lo ad is variable. the block that was addressed during the write operation will be loaded into the block buffer, and the data written by wd (user_data in the data storage client interface) will overwrite the data in the block buffer. after the data is written to the block buffer, the block buffer is then written to the page buffer to keep both buffers in sync. subsequent writes to the same block will over write both the block an d page buffers without incurring busy cycles. a write operation to another block in the page will cause the addressed block to be loaded from the page buffer and into the block buffer , and the write will be performed as previously described. the bloc k buffer load will incur four busy cycles (five cycles with pipe asserted). the contents of the page buffer will be stored into the flash array only when a program page operation is executed. during the program page operation execution, the busy (user_busy in the data storage client interface) signal will be asserted high for ~8 ms until the page programming completes. figure 5-26 on page 5-38 is the timing diagram for a program page operation. figure 5-25 ? flash memory block diagram rd[31:0] wd[31:0] addr[17:0] datawidth[1:0] ren readnext pagestatus wen erasepage program sparepage auxblock unprotectpage overwritepage discardpage overwriteprotect pagelossprotect pipe lockrequest clk reset status[1:0] busy output mux control logic block buffer (128 bits) ecc logic page buffer = 8 blocks plus aux block flash array = 64 sectors
fusion embedded flash memory blocks 5-38 v1.0 a page write operation is initiated by asserting the wen (user_write in the data storage client interface) signal high. th e page write operation automatically triggers a block or page buffer load operation when a change in the block or page address is detected. during a block buffer load operation, the embedded flash memory logic loads th e contents of the addressed block from the page buffer into the block buffer volatile registers. during a pa ge buffer load operation, the embedded flash memory logic load s the contents of the addressed page from the flash array into the page buffer volatile registers. the busy sign al is asserted high during both loading processes. figure 5-27 is the timing diagram for a page write operation. any page being written using a page write or program page operation that is overwrite- protected will result in the status signals being set to '01'; the page data stored in the page buffe r or flash array are left unchanged. during a page write operation, the protected page is de tected during both the page and block buffer loading processes. writing to more than one page without executing a program page operation before changing the page address will result in the loss of the page buffer data. the page-los s protection option can be enabled to protect against the loss of the page buffer data by asserti ng the pagelossprotect (user_pageloss_prot in the data storage cl ient interface) signal high duri ng a program or erase page operation. any page that is page-loss-protected will result in the status (user_nvm_status in the data storage client interf ace) signals being set to '11' when an attempt is made to write to a new page leaving the page buffer unchanged. the pagelossprotect signal can be tied permanently high; it is only samp led when the program or erasepage signals are asserted high. actel recommends always en abling the page-loss protection option. figure 5-28 on page 5-39 is the timing diagram sh owing the page-loss protection fault status update. figure 5-26 ? program page operation timing diagram clk busy addr page addr program figure 5-27 ? page write operation timing diagram clk busy addr addr1 wen wd data1 addr2 data2 addr3 data3 ... addr17 ... data17 0x00 datawidth addr18 data18 addr19 data19 page buffer load block buffer load
fusion embedded flash memory blocks v1.0 5-39 to discard the contents of the mo dified page buffer, the discard pa ge operation can be initiated by asserting the discardpage (user_ discard_page in the data stor age client interface) signal high for one clock cycle. this co mmand will result in the page buf fer being marked as unmodified. the busy signal will rema in asserted until the discar d page operation completes. the erase page operation erases the addressed flas h array page by filling the page buffer volatile registers with all zeros and issuing a program page operation. it is init iated by asserting the erasepage (user_erase_page in the data storage client interface) sign al high while addressing the page to be erased. during the erase page oper ation execution, the busy signal will be asserted high until the operation completes. both the erase page and page write operations require fewer cycles when executing on the same page rather than a new page. any pa ge that is overwrite- protected will result in the status signals being se t to '01' when an attemp t is made to erase the page, and the addressed page?s data will be left unchanged. the overwrite page operation can be used to overwrite any addressed page in the flash array with the contents of the page buffer. the operation can be initiated by asserting the overwritepage (user_overwrite_page in the data storage client interface) sign al high during a program page operation. any page that is over write-protected will result in th e status signals being set to '01' when an attempt is made to program a page with overwritepage asse rted, and the addressed page?s data will be left unchanged. figure 5-29 is the timing diagram showing the overwrite protection fault status update. figure 5-28 ? page-loss protection fault timing diagram clk busy addr page1-addr1 wen page2-addr1 wd page1-data1 page2-data1 status 0x0 0x3 page2-addr2 page2-data2 page-loss protection fault data in page2 remains unchanged. figure 5-29 ? overwrite protection fault timing diagram clk busy addr page addr status 0x0 0x1 overwrite protection fault data in addressed page remains unchanged. : program overwritepage
fusion embedded flash memory blocks 5-40 v1.0 the overwrite protect mechanism is used to protect the contents of the selected flash array?s pages from being overwritten. assert ing the overwriteprot ect (user_overwrite_ prot in the data storage client interface) signal high when a program page oper ation is undertaken will set the overwrite protection option for the addresse d page. overwriteprotect can be held high if multiple pages are to be overwritten; it is only sampled when the program or erasepage signals are asserted high. overwritepro tect is ignored in all other operations. any page that is overwrite-protected will result in the status sign als being set to '01' when an attempt is made to either write, program, or erase the protected page, as shown in figure 5-30 . to clear the overwrite protect option for a gi ven page, the unprotect page operation must be performed, and the page must be programmed wi th the overwriteprotec t pin cleared to save the new protection settings. an unprotect pa ge operation is initiated by asserting the unprotectpage (user_unprot_page in the data storage client interface) signal high while addressing the page. if the addressed page is not in the page buffer, the unprotect page operation will trigger a page buffer load op eration. the load operation occurs only if the current page in the page buffer was programmed into the flash array or is not page-loss-protected. during the unprotect page operation execution, the busy signal will be asserted high until the operation completes. if either the over writeprotect or unprotec tpage signal is asse rted, the other must be deasserted. the unprotect page operation may result in the status signals being set to '01' when the page has a single-bit correctable error, '10' for a double-bit unco rrectable error, or '11' when the page buffer has encountered a page-los s protection situation, during the operation execution. figure 5-30 is the timing diagram showing the page-loss protection fault status update during an unprotect page operation. read operations read operations are designed to read data from the flash array and page status registers. the read operations support read operations with and with out read-next or pipeline stage enabled. all read commands are page-based operations. the embedd ed flash memory read operation reads the contents of the block buffers, wh ich are loaded from ei ther the page buffer or the flash array. the block and page buffers are sub-blocks of the em bedded flash memory, consisting of volatile registers. refer to figure 5-25 on page 5-37 for the flash memo ry block diagram. a read operation to a location in a page that is not already stored in the page buffer will cause the data from the flash array to be read and sto red directly into the block buffer. the busy (user_busy in the data storage client interface ) signal is asserted high during the block buffer loading process for approximately four or five cl ock cycles. any subsequent blocks addressed within the same page will be filled with data fro m the flash array with the same busy period consequence. however, a read operation to a loca tion already stored in the page buffer is loaded into the block buffer without a busy period. a read operation is initiated by asserting the re n (user_read in the data storage client interface) signal high. if the block buffer load is from the flash array, the busy sign al is asserted high for approximately four or five clock cycles during the block buffer load ing process. the contents of the block that was addressed during the read operation will be placed on the rd (user_dout in the figure 5-30 ? unprotect page operation page-loss protection fault timing diagram clk busy addr page addr unprotectpage status 0x0 0x3 page-loss protection fault during unprotect page operation
fusion embedded flash memory blocks v1.0 5-41 data storage client interface) output data bus. for frequencies greater that 50 mhz, a pipeline stage before the data read is placed on the rd data bus may be added by asserting the pipe signal high along with ren. if the pipeli ne stage is enabled, the busy si gnal is asserted for five clock cycles during each block buffer load process; otherwise, it is asserted for four cycles. figure 5-31 is the timing diagram for a page read operation. the read-next operation is a feature by which th e next block to the current block in the block buffer is read from the flash array while performi ng reads from the block buffer, to minimize busy wait states during a se quential read operatio n. it is enabled by asserting the readnext (user_read_next in the data storage client inte rface) signal high along with ren. since the read-next operation executes look-ahead reads, it is performed in a predetermined manner, as follows: ? when reading within a page, the next block fetched will be the next in linear address. ? when reading the last data block of a page, it will fetch the first bl ock of the next page. ? when reading spare pages, it will read the first block of the next sector's spare page. ? when reading the last sector, it will wrap around to sector 0. ? when reading the auxiliary blocks, it will re ad the next linear page's auxiliary block. when an address on the addr (use r_add in the data storage client interface) bus does not agree with the predetermined look-ahead address, there is a time pena lty for this access. the embedded flash memory must complete the current look-ahead read before starting the next. the worst-case figure 5-31 ? page read operation timing diagram clk busy addr addr1 ren rd {data1: data4} {data5: data8} {data9: data12} {data13: data16} {data17: data20} {data21: data24} addr5 addr9 addr17 0x11 datawidth addr21 addr25 0x00000000 block buffer load block buffer load 4 cycles addr13 addr29 0x00000000 4 cycles note: with 16- and 32-bit rd data bus widths, bytes are placed on the bus in big-endian byte order.
fusion embedded flash memory blocks 5-42 v1.0 busy period is a total of nine cy cles before data is delivered. figure 5-32 is the timing diagram for a pipeline-staged read-next page read operation. the status registers of each page of the embedded flash memory can be read by asserting the pagestatus (user_page_status in the data storage client interface) signal along with ren. the contents of the addressed page?s status register will be driven onto the rd data bus. the format of the data returned by a page status read is shown in table 5-11 . figure 5-33 on page 5-43 is the timing diagram for a page sta tus register read operation. figure 5-32 ? pipeline-staged read-next page re ad operation timing diagram clk busy addr ren rd datawidth readnext pipe addr1 {data1: data4} {data5: data8} {data9: data12} {data13: data16} {data17: data20} {data21: data24} addr5 addr9 addr17 0x11 addr21 addr25 0x00...00 block buffer load block buffer load 5 cycles addr13 addr29 0x00000000 1 cycle note: with 16- and 32-bit rd data bus widths, bytes are placed on the bus in big-endian byte order. table 5-11 ? page status register bit definitions bit(s) name description [31:8] write count the number of times the pa ge addressed has been programmed or erased [7:4] reserved reads as 0. [3] over-threshold over-threshold indicator. see the ?program operation? section of the fusion family of mixed-signal flash fpgas datasheet for details. [2] read protect the read protect bit for the page set via the jtag interface. if 1, the page is read- protected. [1] write protect the write protect bit for the page set via the jtag interface. if 1, the page is write- protected. [0] overwrite protect the overwrite protect bit us ed to protect the page from being inadvertently overwritten. the bit must be set by asse rting the overwriteprotect signal during a program operation. the page cannot be overwritten without first performing an unprotect page operation. refer to the "write operations and page programming" section on page 5-37 for additional information.
fusion embedded flash memory blocks v1.0 5-43 note on updating th e contents of flash the possibility of data corruption due to a programming interruption is common to flash technology, and precautions must be taken when up dating the data contents of any flash memory, including fusion?s embedded flas h memory block. an in terruption may occur, for example, as a result of a loss of power to th e fusion fpga or an unexpected reset operation of the flash block control logic. therefore, it is recommended th at the appropriate measure in the application be taken to prevent such interruptio ns from occurring by adding powe r-down ramp control circuitry, low voltage detection circuitry, et c., to allow for the 8 ms program and erase page operations to complete their execution. if an interruption of the write or read operation occurs, the imme diate data stored in the block or page buffer is lost, but the flash array?s data (a sub-block of flash block holding the nonvolatile data contents, as shown in figure 5-25 on page 5-37 ) remains valid. however, if an interruption of a program or erase operation occurs, the page addr essed during the interruption may be left in a locked state. although it may be that no physic al damage to the flash array will have occurred, data corruption of the page is likely to have occurred, resulting in the possible corruption of the page?s auxiliary block control data. only the page addressed at the time of the interruption may incur data corruption; no other page should be affected. a flash block?s page contains eight blocks of user data and one auxiliary bl ock. the auxiliary block is mostly used for storing control data . the auxiliary block control bits of concern are the write protect, read protect, overwrite protect, and writ e count bits. if the protection bits are corrupted, in most cases, reprogramming the embedded flash memory contents with the programming (stapl) file will restore the protection bits to th eir predefined states; however, the page?s write count will be lost. if the overwrite protection bit is the only bit of concern, the application can set/clear this bit by using th e overwriteprotect or unprotectp age input signal s to the nvm macro, as described in the "write operations and page programming" section on page 5-37 . microprocessor/microcontroller interface the embedded flash memory can be interfaced to a microp rocessor or microcontroller for use as its nonvolatile instruction execution memory space and data storage memory space. to enable the embedded flash memory to comm unicate with the micr oprocessor?s or microcontroller?s bus architecture, an interface bridge must be develo ped and added to the design. actel offers, as a directcore ip through coreconsole idp, the co reahbnvm ip, which contains a hardware bridge between the embedded flash memory block and the industry-standard advanced microcontroller bus architecture?s high-performance system backbone bus (ahb). microprocessors can then access data stored in the flash memory via the software-driven cfi co mmand protocol. the following sections describe core ahbnvm?s design configuration and cfi commands. figure 5-33 ? page status register read operation clk busy addr page addr ren pagestatus rd status data
fusion embedded flash memory blocks 5-44 v1.0 coreahbnvm ip configuration coreconsole idp is used to deve lop a microcontroller design for actel fpgas, utilizing the arm7,? cortex-m1, and coreabc microprocesso r or microcontroller ip offering s, together wi th the various amba-ahb and amba-apb (advanced peripheral bus) ip peripherals. for fusion fpga designs, coreahbnvm can be paired with either the arm7 (coremp7 ip) or cortex-m1 microprocessors. the microprocessors must communicate with coreahbnvm through an ahb master, also available through coreconsole as coreahb and coreahblite. when using coreahbnvm?s embedd ed flash memory as the microp rocessor?s instru ction execution memory, coreahbnvm must be connected as core ahb or coreahblite?s sl ave-0 (ahbmslave0) port. after system reset, coreahbnvm defaults to the cfi?s read-array mode for the continuous reading of the instruction code stored in memory. since data is read from the embedded flash memory?s page buffer, when changing the instruction addres s to a new page in flash, the microprocessor must allow for the time required to load a new flash memory page into its page buffer before capturing the data. therefore, the microprocessor and ahb-maste r system clock must be reduced appropriately, such that cont inuous reads can be performed wi thout needing to pause for page buffer loading. when performing static timing analysis using smarttime, the maximum operating frequency of the microprocessor?s system clock is typically reduced to, fo r example, 15 mhz for the arm7. when using coreahbnvm?s embedded flash memory as the microprocessor?s nonvolatile data storage, coreahbnvm must be connected to an y slave port other than slave-0 (ahbmslave1? ahbmslave15), reserving slave-0 fo r the instruction execution memory. note that the remap input to coreahb and coreahblite is used to swap between the sl ave-0 (ahbmslave0) and slave-1 (ahbmslave1) ports. the remap feature of the ahb architecture is typically used to swap boot memory spaces (from flash to ram and vice vers a). therefore, be sure to plan the ahb system carefully taking all ahb slave configurations into co nsideration. for additional details, refer to the coreahb , coreahblite , and coreremap datasheets. once the entire microc ontroller design is complete, coreco nsole?s ?save & generate? operation will produce the rtl code and testbench for the design and save it in a project directory, which then is imported into libero ide. libero ide can then be used to complete the fu sion fpga design flow. refer to the coreconsole user?s guide and the libero ide user?s guide for additional usage information. figure 5-34 on page 5-45 is an example of a simple fusion coremp7 microcontroller coreconsole project, with coreahbnvm us ed as its instruction execution memory.
fusion embedded flash memory blocks v1.0 5-45 coreconsole allows designers to easily configure the ip though a simple gui. figure 5-35 shows the coreahbnvm ip coreconsole configuration gui window. figure 5-34 ? simple fusion coreconsole project with coreah bnvm used as the instruction execution memory ahbmslave0 connection figure 5-35 ? coreahbnvm coreconsole configuration gui
fusion embedded flash memory blocks 5-46 v1.0 coreahbnvm can be configured to include the embedded flash as a 25 6-kbyte, 512-kbyte, or 1-mbyte flash memory data space. by default, coreahbnvm is configured to in clude a 256-kbyte flash memory. up to four coreahbnvm blocks ca n be instantiated for a single fusion design, depending on the targeted fusion fpga device . be sure to size th e flash memory for each coreahbnvm block appropriately, such that the total number of flash block instances does not exceed the total number available on the targeted fusion fpga device. table 5-12 lists the required number of flash block instances for each flash memory space si ze configuration option. cross- reference the required number of flash block instances wi th the number of bloc ks available in the targeted fusion devi ce, as found in the fusion family of mixe d-signal fl ash fpgas datasheet. the coreahbnvm port signals are described in table 5-13 . if coreahbnvm is paired with either the on-chip arm7 or cortex-m1, coreconsole?s auto stitch feature can be used to make all the required interconnects between coreahbnvm and coreahb/coreahblite. coreahbnvm, however, can also be used as an extension of an extern al microprocessor?s nonvolatile memory space by placing all its ahb interface si gnals at the top of the chip design. coreahbnvm can then be connected and controlled by an external ahb master. table 5-12 ? flash memory space size vs. required number of memory block instances flash memory size option number of flash block instances 256 kbytes 1 512 kbytes 2 1 mbytes 4 table 5-13 ? coreahbnvm port si gnal descriptions signal direction description hclk input bus clock rising-edge-active ahb cloc k, which times all bus transfers and all signal timings hresetn input reset active-low asynchronous bus re set signal used to re set the system and the bus. this is the only active-low ahb signal. htrans[1:0] input transfer control input signals that in dicate the type of the current transfer: 00 ? idle 01 ? busy 10 ? non-sequential 11 ? sequential htrans transitions synchronously with the rising edge of hclk. haddr[19:0] input the 32-bi t ahb system address bus from the ahb master. haddr transitions synchronously with the rising edge of hclk. hwrite input transfe r direction control signal. when hi gh, this signal indicates a write transfer; when low, a read transfer. hwrite transitions synchronously with the rising edge of hclk. hsize[2:0] input indicates the size of the transfer, which can be by te (8-bit), halfword (16-bit), or word (32-bit). hsize transitions synchronously with the rising edge of hclk. hwdata[31:0] input 32-bit write input data bus from the ahb master. hwdata transitions synchronously with the rising edge of hclk. hreadyin input active-high r eady signal input from all other ahb slaves. hreadyin transitions synchronously with the rising edge of hclk. hsel input active-high slave select signal input, which is a combinatorial decode of haddr. indicates that this slave is currently being selected. hsel transitions synchronously with the rising edge of hclk.
fusion embedded flash memory blocks v1.0 5-47 supported cfi commands the data stored within coreahbnvm?s flash me mory blocks for instruction execution or data storage can be accessed by the microprocessor or micr ocontroller via the so ftware-driven common flash interface. the cfi is a command-driven interf ace standard used to sta ndardize the low-level flash software algorithms. the coreahbnvm ip supports a subset of the cfi commands. the supported commands are summarized in table 5-14 . upon a system reset (low on hresetn), coreahbn vm defaults to the read-array operation mode to support the microproce ssor instruction execution usage. no write command is needed to place the coreahbnvm ip in the read -array mode as instructed in table 5-14 . as part of the cfi, a status register is used to pr ovide feedback to the so ftware regarding command execution. during each command, the status regi ster should be read to ensure that the flash memory is not busy executing a command (bit 7 set to 1) and that the command executed appropriately. all new commands are ignored while the flash memory is busy (bit 7 set to 0). the status register also includes the pr ogram/erase, write, a nd read/protection error flags (bits 5, 4, and 1, respectively). all three error fl ags are registered; therefore, once an error is detected, the status register must be cleared using the clear status command. once a cfi command is issued and bit 7 (the ready flag) is set to 1, the error flags sh ould be checked to ensu re that the completed operation did not incur an error. table 5-15 on page 5-48 includes a bit description of the status register flags. hrdata[31:0] output 32-bit read output data bus written back to the ahb master. hrdata transitions synchronously with the risi ng edge of hclk. upon an hresetn reset, the hrdata output is zero. hready output transfer-done control output signal. when high, the hready signal indicates that a transfer has finished on the bus. this signal can be driven low to extend a transfer. hready tran sitions synchronousl y with the rising edge of hclk. upon an hresetn reset, the hr eady output is high. hresp[1:0] output transfer respon se output signals, which have the following meanings: 00 ? okay 01 ? error 10 ? retry 11 ? split hresp transitions synchronously with the rising edge of hclk. upon an hresetn reset, the hresp output is in an okay state (0x00). table 5-13 ? coreahbnvm port signal descriptions (continued) signal direction description table 5-14 ? supported cfi command descriptions command no. of bus cycles first bus cycle second bus cycle operation address data operation address data read status 2 write x 0 x70 read x status data clear status 1 write x 0x50 ? ? ? read array 1 or 2 write x 0xff read array address array data erase page 2 write page address 0x20 write page address d0h single write 2 write page address 0x40 write array address array data multi-write 2 write page address 0xe8 write page address no. of elements ? 1
fusion embedded flash memory blocks 5-48 v1.0 read status command the status register contains flags used to inform the user when the flash is ready for the next operation or when an error occu rred with the last operation performed. prior to issuing any new array write or read commands to the cfi control logi c, the ready flag (bit 7 of the status register) should be checked. if ready is set to 1, the flash memory is ready to receive a new command. if ready is set to 0, the flash memory is busy pe rforming an operation and all new commands issued will be ignored. once the ready flag is set to 1, the program/erase, write, and read/protection error flags (bits 5, 4, and 1, respectively) should be checked to ensure that the completed operation did not incur an error. all three e rror flags are registered; therefore, once an error is detected, the status register must be cleared using the clear status command. read status command execution is performed as follows: 1. issue the read status command by writing th e command value 0x70 to any location in the flash array. [any array address] = 0x70 2. once the command has been is sued, read and store the conten ts of the status register to a temporary variable. to read the contents of the status register, issue a read operation at any address in the flash array. the value read will be the contents of the status register. status_register_contents = [any array address] table 5-15 ? status register bit descriptions bit(s) flag description 7 ready active-high ready flag us ed to indicate when the flas h memory is ready to receive new commands or is busy processing a command ?s operation. if ready is set to 1, the flash memory is ready to receive ne w commands, and the previous command?s operation is complete. if ready is set to 0, the flash memory is busy processing the command?s operation. no new commands should be issued until the ready flag is at 1. upon an hresetn reset, the ready flag defaults to 1. 6? ? 5program or erase error active-high program or erase error flag us ed to indicate whet her an error occurred during a program or erase operation. if the pr ogram or erase error flag is set to 1, the flash memory incurred an erro r during a program or erase operation. a locked page access will cause a program or erase operat ion to fail, triggering the error flag to transition to 1. if the flag tr ansitions to 1, it will remain there until cleared by the clear status command operation. up on an hresetn reset, the program or erase error flag defaults to 0. 4 write error active-high write error flag used to indicate whether an error occurred during a write operation. if the write error flag is set to 1, an error occurred during the page buffer write operation. if the write error flag is se t to 0, the page buffer write operation was successful. if the flag transitions to 1, it will remain there unti l cleared by the clear status command operation. upon an hresetn reset, the write error flag defaults to 0. 3?2 ? ? 1 read or protection error the read or protection error flag is used to indicate whether an error occurred during a read, program, or erase oper ation. if a read operation completed and the read error flag is set to 1, an error occurred during the read op eration. if a program/erase operation completed and the protection erro r flag is set to 1, the page program or erase operation failed because the page being accessed is protected. if the flag is set to 0, the read, program, or erase oper ation completed successfully. if the flag transitions to 1, it will remain there until cleared by the clear status command operation. upon an hresetn reset, the read or protecti on error flag defaults to 0. 0? ?
fusion embedded flash memory blocks v1.0 5-49 clear status command the clear status command clears the program/erase, write, and read/protect ion error flags (bits 5, 4, and 1, respectively) of the status register. clear status comm and execution is performed in a single step: issue the clear status command by writing the command value 0x50 to any location in the flash array. [any array address] = 0x50 read array command the read array command is used to place coreahbnvm in read-a rray mode. once coreahbnvm is in read-array mode, it will remain in this mode until a new cfi command is issued. upon an hresetn reset, coreahbnvm defaults to read-arra y mode to support microprocessor instruction execution usage. when performing a continuous read and a page boundary has been crossed, the embedded flash memory must reload the page bu ffer with the new flash page being accessed. in this situation, either the ready flag of the status register must be monitored or the system clock frequency must be adjusted to al low for the loading of the page buffer. if monitoring the ready flag, once it is at 1, the read error flag should be ch ecked to ensure that the completed operation did not incur an error. the read error flag is regi stered; therefore, once an error is detected, the status register must be cleared using the clear status command. read array command execution is performed as follows: 1. issue the read array command by writing the command value 0xff to any location in the flash array. [any array address] = 0xff 2. once the command has been issued, the contents of the array can be read by issuing a read operation at the selected array address in flash. array_contents = [array address] if monitoring the ready fl ag, perform the following: 3. the ready flag (b it 7) of the status register must be monitored to determi ne when the read operation completes. using the read status command, the status register should be polled until ready flag is set to 1, signaling that the write operat ion has completed. ready = status_register_contents & 0x80 4. the read error flag (bit 1) of the status register should also be checked to determine if an error occurred during the read op eration. once the read y flag is set to 1, the status of the flag can be read. read_error = status_register_contents & 0x02 erase page command the erase page command is used to erase an entire page by writin g 0x00 to all locations of the selected page in the embedded flash memory a rray. once the erase pag e command has completed, the protection and erase error fl ags (bits 1 and 5 of the status register) should be checked to determine whether an erase error occurred and whether the page was protected. erase page command executio n is performed as follows: 1. issue the erase page command by writing the command value 0x20 to any location within the flash array page to be erased. [page address] = 0x20 2. issue the erase confirm comma nd by writing the command value 0xd0, addressing any location within th e flash array page to be erased. any other command issued will abort the erase page command. [page address] = 0xd0 3. the ready flag (bit 7) of th e status register must be monitored to determine when the erase operation completes. using the read status command, the status register should be polled until the ready flag is at 1, signaling that the write operat ion has completed. ready = status_register_contents & 0x80
fusion embedded flash memory blocks 5-50 v1.0 4. the protection and erase erro r flags (bits 1 and 5) of the status register should also be checked to determine whether an error occurred during the write operation. once the ready flag is at 1, the status of both flags can be read. protection_error = status_register_contents & 0x02 erase_error = status_register_contents & 0x20 single write command the single write command is used to write a single byte, halfword, or word to the embedded flash memory. when performing a single write command operation, the entire page buffer will be written to the embedded flash memory. therefore, users should avoid a single write command operation when more than one location in a page must be written; a multi-write command operation should be used wherev er possible. once the write co mmand has completed, the write and program error flags (bits 4 and 5 of the status register) should be ch eck to determine whether an error occurred. single write command executio n is performed as follows: 1. issue the single write command by writing the command value 0x40 to any location within the flash array page. it may be simplest to wr ite the command value to the array address of the data to be written. [page address] = 0x40 2. once the command has been is sued, a second write operation must be issued. the write operation consists of writing the array data contents to the array address. [array address] = new_array_data 3. the ready flag (bit 7) of th e status register must be monito red to determine when the write operation completes. using the read status command, the status register should be polled until the ready flag is at 1, signaling that the write operat ion has completed. ready = status_register_contents & 0x80 4. the write and program error fl ags (bits 4 and 5) of the status register should also be checked to determine whether an error occurred during the write operation. once the ready flag is at 1, the status of both flags can be captured. write_error = status_register_contents & 0x10 program_error = status_register_contents & 0x20 multi-write command the multi-write command is used to write multiple consecutive bytes, half-words, or words to a single page of the embedded flash memory. initiall y, the flash memory page is read from the array and loaded into the flash memory?s page buffer. n , the number of data el ements (bytes, words, or double words) to be written to the array, minus one, is then written to coreahbnvm and serves as the maximum number of data elements used by th e internal counter. the expected n count ranges are n = 00h to n = 7fh (e.g., 1 to 128 bytes) in 8-bit mode, n = 00h to n = 3fh in 16-bit mode, and n = 00h to n = 1fh in 32-bit mode. all data is writ ten into the page buffer sequentially, starting from the first address of the page data is writte n to. if n exceeds the starting address plus n addresses of the selected page, the data writes w ill wrap around onto the top of the current page stored in the page buffer. once all data values ar e written into the page buffer, the program buffer confirm command (0xd0) is expected to be issu ed at the next write cycle after the last data element is written; any other command issued at this point in the sequence will prevent the programming of the page buffer into the array (the multi-write command will be aborted). once the program operation has completed, the write an d program error flags (bits 4 and 5 of the status register) should be checked to de termine whether an error occurred.
fusion embedded flash memory blocks v1.0 5-51 multi-write command execution is performed as follows: 1. issue the multi-write command by writing th e command value 0xe8, addressing the flash page to be written. it may be simplest to wr ite the command value to the starting address of the sequence of data va lues to be written. [page address] = 0xe8 2. the ready flag (bit 7) of th e status register must be moni tored to determine when the page buffer fill operation completes. using the read status command, the status register should be polled until the ready flag is at 1, signaling that the page buffer fill operation has completed. ready = status_register_contents & 0x80 3. issue a write operation, writing the number of elements to be written to the flash array, minus one (n), to the page addr ess. again, it may be simple st to write n to the starting address. [page address] = n // (n = number of elements - 1) 4. once the command and number of elemen ts has been issued, a sequence of write operations must be issued. the write operation consists of writing the array data contents to the array address. all data is written sequenti ally, beginning from the starting address, set by the address of the first data value written. repeat this step until all n elements have been written into the page buffer. [array address] = new_array_data 5. issue the buffer program confirm command by writing the command value 0xd0, addressing the flash page to be written. any other comm and issued will abort the programming of the page buffer. [page address] = 0xd0 6. the ready flag (bit 7) of th e status register must be moni tored to determine when the page buffer write operation comple tes. using the read status command, the status register should be polled until the r eady flag is at 1, signaling that the write operation has completed. ready = status_register_contents & 0x80 7. the write and program error fl ags (bits 4 and 5) of the status register should also be checked to determine whether an error occurred during the write operation. once the ready flag is at 1, the status of both flags can be captured. write_error = status_register_contents & 0x10 program_error = status_register_contents & 0x20 part number and revision date part number 51700092-005-0 revised november 2007

v1.4 6-1 6 ? flashrom in actel?s low-power flash devices introduction the fusion, igloo, ? and proasic ? 3 families of low-power flash-based devices have a dedicated nonvolatile flashrom memory of 1,024 bits, which provides a unique feature in the fpga market. the flashrom can be read, modified, and written using the jtag (or ujtag) interface. it can be read but not modified from the fpga core. only low-power flash devices contain on-chip user nonvolatile memory (nvm). architecture of user nonvolatile flashrom low-power flash devices have 1 kbit of user-acce ssible nonvolatile flash me mory on-chip that can be read from the fpga core fabr ic. the flashrom is arranged in eight banks of 128 bits (16 bytes) during programming. the 128 bits in each bank are addressable as 16 bytes during the read-back of the flashrom from the fpga core. figure 6-1 shows the flashrom logical structure. the flashrom can only be programmed via the ieee 1532 jtag port. it cannot be programmed directly from the fpga core. when programming, each of the eight 128-bit banks can be selectively reprogrammed. the flashrom ca n only be reprogrammed on a bank boundary. programming involves an automatic, on-chi p bank erase prior to reprogramming the bank. the flashrom supports synchronous read. the ad dress is latched on the rising ed ge of the clock, and the new output data is stable after the fa lling edge of the same clock cycl e. for more information, refer to the timing diagrams in the dc an d switching characteri stics chapter of the appropriate datasheet. the flashrom can be read on by te boundaries. the upper three bi ts of the flashrom address from the fpga core define the bank being accessed. th e lower four bits of th e flashrom address from the fpga core define which of the 16 by tes in the bank is being accessed. figure 6-1 ? flashrom architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
flashrom in actel?s lo w-power flash devices 6-2 v1.4 flashrom support in flash-based devices the flash fpgas listed in table 6-1 support the flashrom feature and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 6-1 . where the information applie s to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 6-1 . where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 6-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
flashrom in actel?s lo w-power flash devices v1.4 6-3 figure 6-2 ? fusion device architecture overview (afs600) figure 6-3 ? proasic3 and igloo de vice architecture versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad 4,608-bit dual-port sram or fifo block versatile ram block ccc i/os isp aes decryption nonvolatile memory flashrom charge pumps 4,608-bit dual-port sram or fifo block ram block
flashrom in actel?s lo w-power flash devices 6-4 v1.4 flashrom applications the smartgen core generator is used to configure flashrom content. you can configure each page independently. smartgen enables you to create and modify regions within a page; these regions can be 1 to 16 bytes long ( figure 6-4 ). the flashrom content can be changed independentl y of the fpga core content. it can be easily accessed and programmed via jtag, depending on the security settings of the device. the smartgen core generator enables each region to be independently updated (described in the "programming and accessing flashrom" section on page 6-6 ). this enables you to change the flashrom content on a per-part ba sis while keeping some regions "constant" for all parts. these features allow the flashrom to be used in dive rse system applications. consider the following possible uses of flashrom: ? internet protocol (ip) addressing (wireless or fixed) ? system calibration settings ? restoring configuration after unpredictable system power-down ? device serialization and/or inventory control ? subscription-based business mo dels (e.g., set-top boxes) ? secure key storage ? asset management tracking ? date stamping ? version management figure 6-4 ? flashrom configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte number in page page number
flashrom in actel?s lo w-power flash devices v1.4 6-5 flashrom security low-power flash devices have an on-chip advanc ed encryption standard (aes) decryption core, combined with an enhanced version of the actel flash-based lock technology (flashlock ? ). together, they provide unmatched levels of securi ty in a programmable logi c device. this security applies to both the fpga core and flashrom content. these de vices use the 128-b it aes (rijndael) algorithm to encr ypt programming files for se cure transmission to the on-chip aes decryption core. the same algorithm is then used to decrypt the programming file. this key size provides approximately 3.4 10 38 possible 128-bit keys. a computing sy stem that could find a des key in a second would take approximately 149 trillion years to crack a 128-bit aes key. the 128-bit flashlock feature in low-power flash devices wo rks via a flashlock secu rity pass key mechanism, where the user locks or un locks the device with a us er-defined key. refer to security in low-power flash devices . if the device is locked with cert ain security settings, fu nctions such as device read, write, and erase are disabled. this unique feature helps to pr otect against invasive and noninvasive attacks. without the correct pass key, access to the fpga is denied. to gain access to the fpga, the device first must be unlocked us ing the correct pass key. during pr ogramming of the flashrom or the fpga core, you can generate the security header programming file, which is used to program the aes key and/or flashlock pass key. the security header programming file can also be generated independently of the flashrom and fpga core conten t. the flashlock pass key is not stored in the flashrom. low-power flash devices with aes-based security al low for secure remote field updates over public networks such as the internet, and ensure that va luable intellectual prop erty (ip) remains out of the hands of ip thieves. figure 6-5 shows this flow diagram. figure 6-5 ? programming flashrom using aes flash device aes encryption encrypted data aes-128 decryption core encrypted data flashrom fpga core programming data untrusted medium same aes key
flashrom in actel?s lo w-power flash devices 6-6 v1.4 programming and accessing flashrom the flashrom content can only be programmed via jtag, but it can be read back selectively through the jtag programming interface, the ujtag interface, or via direct fpga core addressing. the pages of the flashrom can be made secure to prevent read-back via jtag. in that case, read- back on these secured pages is only possibl e by the fpga core fabric or via ujtag. a 7-bit address from the fpga core defines which of the eight pages (three msbs) is being read, and which of the 16 bytes with in the selected page (four lsbs) are being read. the flashrom content can be read on a random basis; the access time is 10 ns for a device supporting commercial specifications. the fpga core will be powered down during writing of the flashrom content. fpga power-down during flashrom programming is ma naged on-chip, and fpga core functionality is not available during programming of the flashrom. table 6-2 summarizes various flashrom access scenarios. figure 6-6 shows the accessing of the flashrom using th e ujtag macro. this is similar to fpga core access, where the 7-bit address defines which of the eight pages (three msbs) is being read and which of the 16 bytes within the selected page (four lsbs) are being read. refer to ujtag applications in actel?s low-power flash devices for details on using the ujtag macro to read the flashrom. figure 6-7 on page 6-7 and figure 6-8 on page 6-7 show the flashrom access from the jtag port. the flashrom content can be read on a random ba sis. the three-bit addres s defines which page is being read or updated. table 6-2 ? flashrom read/write capa bilities by access mode access mode flashrom read flashrom write jtag yes yes ujtag yes no fpga core yes no figure 6-6 ? block diagram of using ujtag to read flashrom contents flashrom addr [6:0] data[7:0] clk enable sdo sdi reset addr [6:0] data [7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg [7:0] control ujtag address generation and data serialization
flashrom in actel?s lo w-power flash devices v1.4 6-7 figure 6-7 ? accessing flashrom using fpga core figure 6-8 ? accessing flashrom using jtag port 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 word number in page 4 lsb of addr (read) page number 3 msb of addr (read) 3-bit page address 111 1110000 7-bit address from core 0000 4-bit word address 8-bit data 8-bit data to fpga core 8-bit data from page 7 word 0 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 word number in page 4 lsb of addr (read) page number 3 msb of addr (read) 4-bit page address from jtag interface to/from jtag interface ...........................00001:128 bit data
flashrom in actel?s lo w-power flash devices 6-8 v1.4 flashrom design flow the actel libero ? integrated design environment (ide) software has extensive flashrom support, including flashrom generation, instanti ation, simulation, and programming. figure 6-9 shows the user flow diagram. in the design flow, ther e are three main steps: 1. flashrom generation and instantiation in the design 2. simulation of flashrom design 3. programming file genera tion for flashrom design figure 6-9 ? flashrom design flow simulator flashpoint smartgen programmer synthesis designer security header options programming files ufc file flashrom netlist user design user netlist core map mem file back- annotated netlist
flashrom in actel?s lo w-power flash devices v1.4 6-9 flashrom generation and in stantiation in the design the smartgen core genera tor, available in libero ide and designer, is the only tool that can be used to generate the flashrom content. smartgen has several user-friendly features to help generate the flashrom contents. instead of selecting each byte and assigning values, you can create a region within a page, mo dify the region, and assign properties to that region. the flashrom user interface, shown in figure 6-10 on page 6-9 , includes the configuration grid, existing regions list, and properties field. the properti es field specifies the region-spe cific information and defines the data used for that region. you can assi gn values to the following properties: 1. static fixed data?enables yo u to fix the data so it canno t be changed during programming time. this option is useful when you have fixe d data stored in this region, which is required for the operation of the design in the fpga. key storage is one example. 2. static modifiable data?select this option when th e data in a particular region is expected to be static data (such as a version number, wh ich remains the same for a long duration but could conceivably change in th e future). this op tion enables you to avoid changing the value every time you enter new data. 3. read from file?this provides the full flexibil ity of flashrom usage to the customer. if you have a customized algorithm fo r generating the flashrom data, you can specify this setting. you can then generate a text file with data fo r as many devices as you wish to program, and load that into the flashpoint programming file generation softw are to get programming files that include all the data. smartgen will optionally pass the location of the file where the data is stored if the file is specified in smartgen. each text file has only one type of data format (binary, decimal, hex, or ascii text). the length of each data file must be shorter than or equal to the selected region length. if the data is shorter th an the selected region length, the most signific ant bits will be padded with 0s. fo r multiple text files for multiple regions, the first li nes are for the first device. in smartgen, load sim. value from file allows you to load the first device data in the mem file for simulation. 4. auto increment/decrement?this scenario is useful when you specify the contents of flashrom for a large number of devices in a series. you can specify the step value for the serial number and a maximum value for in ventory control. during programming file generation, the actual number of devices to be programmed is specified and a start value is fed to the software. figure 6-10 ? smartgen gui of the flashrom
flashrom in actel?s lo w-power flash devices 6-10 v1.4 smartgen allows you to generate the flashrom netl ist in vhdl, verilog, or edif format. after the flashrom netlist is generated, the core can be instantiated in the main design like other smartgen cores. note that the macro library name for flashrom is ufrom. the following is a sample flashrom vhdl netlist that can be instantiated in the main design: library ieee; use ieee.std_logic_1164.all; library fusion; entity from_a is port( addr : in std_logic_vector(6 downto 0); dout : out std_logic_vector(7 downto 0)); end from_a; architecture def_arch of from_a is component ufrom generic (memoryfile:string); port(do0, do1, do2, do3, do4, do5, do6, do7 : out std_logic; addr0, addr1, addr2, addr3, addr4, addr5, addr6 : in std_logic := 'u') ; end component; component gnd port( y : out std_logic); end component; signal u_7_pin2 : std_logic ; begin gnd_1_net : gnd port map(y => u_7_pin2); ufrom0 : ufrom generic map(memoryfile => "from_a.mem") port map(do0 => dout(0), do1 => dout(1), do2 => dout(2), do3 => dout(3), do4 => dout(4), do5 => dout(5), do6 => dout(6), do7 => dout(7), addr0 => addr(0), addr1 => addr(1), addr2 => addr(2), addr3 => addr(3), addr4 => addr(4), addr5 => addr(5), addr6 => addr(6)); end def_arch; smartgen generates the following files along with the netlist. th ese are located in the smartgen folder for the li bero ide project. 1. mem (memory initialization) file 2. ufc (user flash configuration) file 3. log file the mem file is used for simulation, as explained in the "simulation of flashrom design" section . the ufc file, generated by smar tgen, has the flashrom configur ation for single or multiple devices and is used during stapl generation. it contains the region properties and simulation values. note that any changes in the mem file will not be reflected in th e ufc file. do not modify the ufc to change flashrom content. instead, use the smartgen gui to modify the flashrom content. see the "programming file generation for fl ashrom design" section on page 6-11 for a description of how the ufc file is used during the programming file gene ration. the log file has information regarding the file type and file location.
flashrom in actel?s lo w-power flash devices v1.4 6-11 simulation of flashrom design the mem file has 128 rows of 8 bits, each repres enting the contents of the flashrom used for simulation. for example, the first row represents page 0, byte 0; the next row is page 0, byte 1; and so the pattern continues. note that the three msbs of the addr ess define the page number, and the four lsbs define the byte number . so, if you send address 0000100 to flashrom, this corresponds to the page 0 and byte 4 location, which is the fifth row in the mem file. smartgen defaults to 0s for any unspecified location of the flashrom. besides using the mem file generated by smartgen, you can create a binary file with 128 rows of 8 bits each and use this as a mem file. actel recommends that you use different file names if you plan to genera te multiple mem files. during simulation, libero ide passes the mem file used as the generic fi le in the netlist, along with the design files and testbench. if you want to use different mem f iles during simulation, you need to modify the generic file reference in the netlist. ??????? ufrom0: ufrom --generic map(memoryfile => "f:\appsnotes\from\test_designs\testa\smartgen\from_a.mem") --generic map(memoryfile => "f:\appsnotes\from\test_designs\testa\smartgen\from_b.mem") ????????. the vital and verilog simulation mo dels accept the generics passed by the netlist, read the mem file, and perform simulation wi th the data in the file. programming file generation for flashrom design flashpoint is the programming software used to generate the programming files for flash devices. depending on the applications, you can use the fl ashpoint software to generate a stapl file with different flashrom contents. in each case, optional aes decryption is available. to generate a stapl file that contains the same fpga core content and different flashrom contents, the flashpoint software needs an array map file fo r the core and ufc file(s ) for the flashrom. this final stapl file represents the combination of the logic of the fpga core and flashrom content. flashpoint generates the stapl files you can use to program the desired flashrom page and/or fpga core of the fpga device contents. flashp oint supports the encryp tion of the flashrom content and/or fpga array configuration data. in the case of using the flashrom for device serialization, a sequence of un ique flashrom contents will be generated. when generating a programming file with mu ltiple unique flashrom contents, yo u can specify in flashpoint whether to include all flashrom content in a single stapl file or generate a different stapl file for each flashrom ( figure 6-11 ). the programming software (flashpro) handles the single stapl file that contains the flashr om content from multiple devices. it enables you to program the flashrom content into a series of devices sequentially ( figure 6-11 ). see the flashpro user?s guide for information on serial programming. figure 6-11 ? single or multiple programming file generation flashpoint fpga array map file fpga array map file security settings security settings ufc file for multiple flashrom contents ufc file for single flashrom contents flashpoint single stapl file single stapl file single stapl file
flashrom in actel?s lo w-power flash devices 6-12 v1.4 figure 6-12 shows the programmin g file generator, which enables different stapl file generation methods. when you select program flashrom and choose the ufc file , the flashrom settings window appears, as shown in figure 6-13 . in this window, you can select the flashrom page you want to program and the data valu e for the configured regions. this enables you to use a different page for different pr ogramming files. the programming hardware and software can load the flashrom with the appropriate stapl file. programming software handles the single stapl file that contains multiple flashrom contents for multiple devices, and programs th e flashrom in sequential order (e .g., for device serialization). figure 6-12 ? programming file generator figure 6-13 ? setting flashrom during pr ogramming file generation
flashrom in actel?s lo w-power flash devices v1.4 6-13 this feature is supported in the programming so ftware. after programming with the stapl file, you can run device_info to check the flashrom content. device_info displays the flashrom content, serial number, design name, and checksum, as shown below: export idcode[32] = 123261cf export silsig[32] = 00000000 user information : checksum: 61a0 design name: top programming method: stapl algorithm version: 1 programmer: unknown ========================================= flashrom information : export region_7_0[128] = ffffffffffffffffffffffffffffffff ========================================= security setting : encrypted flashrom programming enabled. encrypted fpga array programming enabled. ========================================= the libero ide file manager re cognizes the ufc and mem files and displays them in the appropriate view. libero ide also recognizes th e multiple programming f iles if you choose the option to generate multiple fi les for multiple flas hrom contents in de signer. these features enable a user-friendly flow fo r the flashrom generation and programming in libero ide. custom serialization using flashrom you can use flashrom for device serialization or inventory control by using the auto inc region or read from file region. flashpoint will automatica lly generate the serial number sequen ce for the auto inc region with the start value , max value , and step value provided. if you have a unique serial number generation scheme that you prefer, the read from file region allows you to import the file with your serial number scheme programmed into the region. see the flashpro user's guide for custom serialization file format information. the following steps describe ho w to perform device serializatio n or inventory control using flashrom: 1. generate flashrom using smartgen. from the properties section in the flashrom settings dialog box, select the auto inc or read from file region. for the auto inc region, specify the desired step value. you will not be able to modify this value in the flashpoint software. 2. go through the regula r design flow and finish place-and-route. 3. select programming file in designer and open generate programming file ( figure 6-12 on page 6-12 ). 4. click program flashrom , browse to the ufc file, and click next . the flashrom settings window appears, as shown in figure 6-13 on page 6-12 . 5. select the flashrom page you want to pr ogram and the data value for the configured regions. the stapl file generated will contai n only the data that targets the selected flashrom page. 6. modify properties fo r the serialization. ? for the auto inc region, specify the start and max values. ? for the read from file region, select the file name of the custom serialization file. 7. select the flashrom programming file type you want to generate from the two options below: ? single programming file for all devices: generates one programming file with all flashrom values. ? one programming file per device: genera tes a separate programming file for each flashrom value.
flashrom in actel?s lo w-power flash devices 6-14 v1.4 8. enter the number of devices you want to program and generate the required programming file. 9. open the programm ing software and load the pr ogramming file. the programming software, flashpro3 and silicon sc ulptor ii, supports the device serialization feature. if, for some reason, the device fails to program a part during serialization, th e software allows you to reuse or skip the se rial data. refer to the flashpro user?s guide for details. conclusion the fusion, igloo, and proasic3 families are the only fp gas that offer on-chi p flashrom support. this document presents informa tion on the flashrom archit ecture, possible applications, programming, access through the jtag and ujtag in terface, and integration into your design. in addition, the libero ide tool set enables easy creation and mo dification of the flashrom content. the nonvolatile flashrom block in the fpga can be customized, enabling multiple applications. additionally, the security offered by the low-p ower flash devices keep s both the contents of flashrom and the fpga design sa fe from system over-builders, sy stem cloners, and ip thieves. related documents handbook documents security in low-pow er flash devices www.actel.com/documents/lpd_security_hbs.pdf ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf user?s guides flashpro user?s guide http://www.actel.com/documents/flashpro_ug.pdf
flashrom in actel?s lo w-power flash devices v1.4 6-15 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-007-4 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 6-1 flash-based fpgas . 6-2 v1.2 (june 2008) the "flashrom support in flas h-based devices" section was revised to include new families and make the information more concise. 6-2 figure 6-2 fusion device ar chitecture overview (afs600) was replaced. figure 6-5 programming flashrom using aes was revised to change "fusion" to "flash device." 6-3 , 6-5 the flashpoint user?s guide was removed from the "user?s guides" section , as its content is now part of the flashpro user?s guide . 6-14 v1.1 (march 2008) the following changes were made to the family descriptions in table 6-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 6-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. the "igloo terminology" section and "proasic3 terminology" section are new. n/a

v1.5 7-1 7 ? sram and fifo memories in actel's low- power flash devices introduction as design complexity grows, gr eater demands are placed upon an fpga's embedded memory. actel fusion, ? igloo, ? and proasic ? 3 devices provide the flexibility of true dual-port and two-port sram blocks. the embedded memory, along with built-in, dedicated fifo control logic, can be used to create cascading ram blocks and fifos without using additional logic gates. igloo, igloo plus, and proasic3l fpgas contain an additional feature that allows the device to be put in a low-power mode called flash*freeze. in this mode, the core draws minimal power (on the order of 2 to 127 w) and still retains va lues on the embedded sram/fifo and registers. flash*freeze technology allows th e user to switch to active mo de on demand, thus simplifying power management and the use of sram/fifos. device architecture the low-power flash devices feature up to 504 kbits of ram in 4,608-bit blocks ( figure 7-1 on page 7-2 and figure 7-2 on page 7-3 ). the total embedded sram for each device can be found in the datasheets. these memory blocks are arrang ed along the top and bo ttom of the device to allow better access from the core and i/o (in some devices, they are only available on the north side of the device). every ram block has a flexible, hardwired, embedded fifo controller, enabling the user to implement efficient fifo s without sacrificing user gates. in the igloo and proasic3 families of devi ces, the following memories are supported: ? 30 k gate devices and smaller do not support sram and fifo. ? 60 k and 125 k gate devices support memories on the north side of the device only. ? 250 k devices and larger support memories on the north and south sides of the device. in fusion devices, the foll owing memories are supported: ? afs090 and afs250 support memories on the north side of the device only. ? afs600 and afs1500 support memories on th e north and south si des of the device.
sram and fifo memori es in actel's low-p ower flash devices 7-2 v1.5 notes: 1. aes decryption not supported in 30 k gate devices and smaller. 2. flash*freeze is supported in all ig loo devices and the proasic3l devices. figure 7-1 ? igloo and proasic3 device architecture overview isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps 2 ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 1
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-3 figure 7-2 ? fusion device architecture overview (afs600) flash array flash array adc analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad versatile ccc/pll i/os osc ccc isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 4 bank 2 bank 1 bank 3 ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block
sram and fifo memori es in actel's low-p ower flash devices 7-4 v1.5 sram/fifo support in flash-based devices the flash fpgas listed in table 7-1 support sram and fifo blocks and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 7-1 . where the information applie s to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 7-1 . where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 7-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-5 sram and fifo architecture to meet the needs of high-perfo rmance designs, the memo ry blocks operate strictly in synchronous mode for both read and write operations. the r ead and write clocks are completely independent, and each can operate at any desired frequency up to 250 mhz. ? 4k1, 2k2, 1k4, 5129 (dual-port ram?2 read / 2 write or 1 read / 1 write) ? 5129, 25618 (2-port ram?1 read / 1 write) ? sync write, sync pipelined / nonpipelined read automotive proasic3 devices supp ort single-port sram capabilities or dual-port sram only under specific conditions. dual-port mode is supported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the port a clock is the inverse of the port b clock). the actel libero ? integrated design environment (i de) software macro libraries supp ort a dual-port macro only. for use of this macro as a single-port sram, the inputs and clock of one port should be tied off (grounded) to prevent errors du ring design compile. for use in dual-port mode, the same clock with an inversion between the two clock pins of th e macro should be used in the design to prevent errors during compile. the memory block includes dedicated fifo cont rol logic to generate internal addresses and external flag logic (full, empty, afull, aempty). simultaneous dual-port read/write and write/writ e operations at the same address are allowed when certain timing requirements are met. during ram operation, addresses are sourced by the user logic, and the fifo controller is ignored. in fifo mode, the internal addresses are generate d by the fifo controller and routed to the ram array by internal muxes. the low-power flash device architec ture enables the read and write sizes of rams to be organized independently, allowing for bus conversion. for ex ample, the write size can be set to 25618 and the read size to 5129. both the write width and read width for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. th e different dw configurations are 25618, 5129, 1k4, 2k2, and 4k1. when widths of one, two, or four are select ed, the ninth bit is unused. for example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addres sable for read operations. the ninth bit is not accessible. conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. the ram blocks empl oy little-endian byte or der for read and write operations. memory blocks and macros memory blocks can be configured with many diff erent aspect ratios, but are generically supported in the macro libraries as one of two memory elements: ram4k9 or ram512x18. the ram4k9 is configured as a true dual-port memory block, and the ram512x18 is configured as a two-port memory block. dual-port memory allows the ra m to both read from an d write to either port independently. two-port memory allows the ram to read from one port and write to the other using a common clock or independent read and write clocks. if needed, the ram4k9 blocks can be configured as two-port memory blocks. the memory block can be configured as a fifo by combining the basi c memory block with dedicated fifo controller logic. the fifo macro is named fifo4kx18 ( figure 7-3 on page 7-6 ). clocks for the ram blocks can be driven by the versanet (global resource s) or by regular nets. when using local clock segments, the clock segm ent region that encompasses the ram blocks can drive the rams. in the dual-port configuration (ram4k9), each memory block port can be driven by either rising-edge or falling-edge clocks. each po rt can be driven by clocks with different edges. though only a rising-edge clock can drive the physica l block itself, the actel designer software will automatically bubble-push the inve rsion to properly implement th e falling-edge trigger for the ram block.
sram and fifo memori es in actel's low-p ower flash devices 7-6 v1.5 note: automotive proasic3 devices restrict ram4k9 to a single port or to dual ports with the same clock 180 out of phase (inverted) between clock pins. in singl e-port mode, inputs to port b should be tied to ground to prevent errors during compile. for fifo4k18, the sa me clock 180 out of phase (inverted) between clock pins should be used. figure 7-3 ? supported basic ram macros fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-7 sram features ram4k9 macro ram4k9 is the dual-port configuration of the ram block ( figure 7-4 ). the ram4k9 nomenclature refers to both the deepest possibl e configuration and the widest possible configuration the dual- port ram block can assume, and does not denote a possible memory aspect ratio. the ram block can be configured to the following aspect ratios: 4,0961, 2,0482, 1,024 4, and 5129. ram4k9 is fully synchronous and has the following features: ? two ports that allow fully independent r eads and writes at different frequencies ? selectable pipelined or nonpipelined read ? active-low block enables for each port ? toggle control between read and write mode for each port ? active-low asynchronous reset ? pass-through write data or hold existing da ta on output. in pass-through mode, the data written to the write port will imme diately appear on the read port. ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. signal descriptions for ram4k9 note: automotive proasic3 devices support single-port sram capabilities, or dual-port sram only under specific conditions. dual-port mode is s upported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the por t a clock is the inverse of the port b clock). since actel libero ide macro libraries suppo rt a dual-port macro only, certain modifications must be made. these are detailed below. the following signals are used to co nfigure the ram4k9 memory element: widtha and widthb these signals enable the ram to be configured in one of four allowable aspect ratios ( table 7-2 on page 7-8 ). note: when using the sram in single-port mode for automotive proasic3 devices, widthb should be tied to ground. note: for timing diagrams of the ram signals, refer to the appropriate family datasheet. figure 7-4 ? ram4k9 simplified configuration dina douta doutb write data ram4k9 reset write data read data read data dinb addra address address addrb blka blk blk blkb wena wen wen wenb clka clk clk clkb
sram and fifo memori es in actel's low-p ower flash devices 7-8 v1.5 blka and blkb these signals are active-low and will enable the resp ective ports when a sserted. when a blkx signal is deasserted, that port?s outputs hold the previous value. note: when using the sram in single-port mode for automotive proasic3 devices, blkb should be tied to ground. wena and wenb these signals switch the ram between read and write mode s for the respective ports. a low on these signals indicates a write operat ion, and a high indicates a read. note: when using the sram in single-port mode for automotive proasic3 devices, wenb should be tied to ground. clka and clkb these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. note: for automotive proasic3 devices, dual-port mode is supported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the port a clock is the inverse of the port b clock). for use of this macro as a single-port sram, the inputs and clock of one port should be tied off (grounded) to preven t errors during design compile. pipea and pipeb these signals are used to specify pipelined read on the output. a low on pipea or pipeb indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. a high indicates a pipelined read, and data appears on the corresponding output in the next clock cycle. note: when using the sram in single-port mode for automotive proasic3 devices, pipeb should be tied to ground. for use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. wmodea and wmodeb these signals are used to config ure the behavior of the output when the ram is in write mode. a low on these signals makes the output retain data from the previous read. a high indicates pass- through behavior, wherein the data being writte n will appear immediately on the output. this signal is overridden when the ram is being read. note: when using the sram in single-port mode for automotive proasic3 devices, wmodeb should be tied to ground. reset this active-low signal re sets the control logic, fo rces the output hold state registers to zero, disables reads and writes from the sram block, and clears th e data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. addra and addrb these are used as read or write addresses, and th ey are 12 bits wide. when a depth of less than 4 k is specified, the unused high-order bits must be grounded ( table 7-3 on page 7-9 ). table 7-2 ? allowable aspect ratio settings for widtha[1:0] widtha[1:0] widthb[1:0] dw 00 00 4k1 01 01 2k2 10 10 1k4 11 11 5129 note: the aspect ratio settings are consta nt and cannot be changed on the fly.
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-9 note: when using the sram in single-port mode for automotive proasic3 devices, addrb should be tied to ground. dina and dinb these are the input data signals, and they are ni ne bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused hi gh-order signals must be grounded ( table 7-4 ). note: when using the sram in single-port mode for automotive proasic3 devices, dinb should be tied to ground. douta and doutb these are the nine-bit output data signals. not all nine bits are valid in all configurations. as with dina and dinb, high -order bits may not be used ( table 7-4 ). the output data on unused pins is undefined. ram512x18 macro ram512x18 is the two-port configuration of the same ram block ( figure 7-5 on page 7-10 ). like the ram4k9 nomenclature, the ram512x18 nomenc lature refers to both the deepest possible configuration and the widest possible configuration the two-port ram block can assume. in two- port mode, the ram block can be configured to eith er the 5129 aspect ratio or the 25618 aspect ratio. ram512x18 is also fully synchr onous and has the following features: ? dedicated read and write ports ? active-low read and write enables ? selectable pipelined or nonpipelined read ? active-low asynchronous reset ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. table 7-3 ? address pins unused/used for various supported bus widths dw addrx unused used 4k1 none [11:0] 2k2 [11] [10:0] 1k4 [11:10] [9:0] 5129 [11:9] [8:0] note: the "x" in addrx implies a or b. table 7-4 ? unused/used input and output data pins for various supported bus widths dw dinx/doutx unused used 4k1 [8:1] [0] 2k2 [8:2] [1:0] 1k4 [8:4] [3:0] 5129 none [8:0] note: the "x" in dinx or doutx implies a or b.
sram and fifo memori es in actel's low-p ower flash devices 7-10 v1.5 signal descripti ons for ram512x18 ram512x18 has slightly different behavior from ram4k9, as it has dedicated read and write ports. ww and rw these signals en able the ram to be configured in one of the two allowable aspect ratios ( table 7-5 ). wd and rd these are the input an d output data signals, and they are 18 bits wide. when a 5129 aspect ratio is used for write, wd[17:9] are unused and must be grounded. if this aspect ratio is used for read, rd[17:9] are undefined. waddr and raddr these are read and write addresse s, and they are nine bits wide . when the 25618 aspect ratio is used for write or read, waddr[8] and radd r[8] are unused and must be grounded. wclk and rclk these signals are the write and read clocks, respecti vely. they can be clocked on the rising or falling edge of wclk and rclk. wen and ren these signals are the writ e and read enables, respectively. th ey are both active-low by default. these signals can be configured as active-high. reset this active-low signal re sets the control logic, fo rces the output hold state registers to zero, disables reads and writes from the sram block, and clears th e data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. note: for timing diagrams of the ram signals, refer to the appropriate family datasheet. figure 7-5 ? 512x18 two-port ram block diagram table 7-5 ? aspect ratio settings for ww[1:0] ww[1:0] rw[1:0] dw 01 01 5129 10 10 25618 00, 11 00, 11 reserved wd waddr radd r write data read data read address write address rd wen write enable read enable ren wclk write clk read clk rclk ram512x18 reset
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-11 pipe this signal is used to specify pipelined read on the output. a low on pi pe indicates a nonpipelined read, and the data appears on the output in th e same clock cycle. a high indicates a pipelined read, and data appears on the ou tput in the next clock cycle. sram usage the following descri ptions refer to the usage of both ram4k9 and ram512x18. clocking the dual-port sram blocks are only clocked on the rising edge. smartgen allows falling-edge- triggered clocks by adding inverters to the netlist, hence achieving dual-port sram blocks that are clocked on either edge (rising or falling). for dual-port sram, each port can be clocked on either edge and by separate clocks by port. note that for automotive proasic3, the same clock, with an inversion between the two clock pins of the macro, should be used in design to prevent errors during compile. low-power flash devices support inversion (bubbl e-pushing) throughout the fpga architecture, including the clock input to the sram modules. inversions added to the sram clock pin on the design schematic or in the hdl code will be au tomatically accounted for during design compile without incurring additional delay in the clock path. the two-port sram can be clocked on the rising or falling edge of wclk and rclk. if negative-edge ram and fifo clocking is se lected for memory macros, clock edge inversion management (bubble-pushing) is automatically used within th e development tools, without performance penalty. modes of operation there are two read modes and one write mode: ? read nonpipelined (synchronous?1 clock edge ): in the standard read mode, new data is driven onto the rd bus in the same clock cycle following ra and ren valid. the read address is registered on the read port clock active edge, and data appears at rd after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchronous?2 clock edges): the pipelined mode incurs an additional clock delay from address to data but enables oper ation at a much higher frequency. the read address is registered on the read port active cl ock edge, and the read da ta is registered and appears at rd after the second read clock edge. setting pi pe to on enables this mode. ? write (synchronous?1 clock edge ): on the write clock active ed ge, the write data is written into the sram at the write ad dress when wen is hi gh. the setup times of the write address, write enables, and write data are mini mal with respect to the write clock. ram initialization each sram block can be individually initialized on power-up by means of the jtag port using the ujtag mechanism. the shift register for a target block can be selected a nd loaded with the proper bit configuration to enable seri al loading. the 4,608 bits of da ta can be loaded in a single operation. fifo features the fifo4kx18 macro is created by merging the ram block with dedicated fifo logic ( figure 7-6 on page 7-12 ). since the fifo logic can only be used in conjunction with the memory block, there is no separate fifo controller macro. as with th e ram blocks, the fifo4kx18 nomenclature does not refer to a possible aspect rati o, but rather to th e deepest possible data depth and the widest possible data width. fifo4kx18 can be configur ed into the following aspect ratios: 4,0961, 2,0482, 1,0244, 5129, and 25618. in addition to being fully synchronous, the fifo4kx18 also has the following features: ? four fifo flags: empty, full, almost-empty, and almost-full ? empty flag is synchron ized to the read clock ? full flag is synchronized to the write clock ? both almost-empty and almost-full fl ags have programmable thresholds
sram and fifo memori es in actel's low-p ower flash devices 7-12 v1.5 ? active-low asynchronous reset ? active-low block enable ? active-low write enable ? active-high read enable ? ability to configure the fifo to either stop counting after the empty or full states are reached or to allow the fifo counters to continue ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. the fifos maintain a separate read and write addr ess. whenever the difference between the write address and the read address is greater than or equal to the almost-full value (afval), the almost- full flag is asserted. similarly, the almost-empty flag is asserted whenever the difference between the write address and read address is less th an or equal to the al most-empty value (aeval). figure 7-6 ? fifo4kx18 bl ock diagram figure 7-7 ? ram block with embedded fifo controller wd full empty write data fifo4kx18 reset read data empty flag full flag rd afull almost-full flag almost-empty flag aempty wen write enable write clock read enable ren wclk read clock rclk c nt 12 e = e = c nt 12 afval aeval s ub 12 r c lk wd w c lk reset rblk ren e s top wblk wen f s top rd[17:0] wd[17:0] r c lk w c lk radd[ j :0] wadd[ j :0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-13 due to synchronization between the read and write clocks, the empty flag wi ll deassert after the second read clock edge from the po int that the write enable asser ts. however, since the empty flag is synchronized to the read clock, it will assert after the read clock reads the last data in the fifo. also, since the full flag is dependent on the actual hardware configuration, it will assert when the actual physical implementation of the fifo is full. for example, when a user config ures a 12818 fifo, the actual ph ysical implementation will be a 25618 fifo element. since the actu al implementation is 25618, the full flag will not trigger until the 25618 fifo is full, even th ough a 12818 fifo was requested. for this example, the almost- full flag can be used instead of the full flag to signal when the 128th data word is reached. to accommodate different aspect ratios, the almost-full and almo st-empty values are expressed in terms of data bits instead of data words. smartg en translates the user?s input, expressed in data words, into data bits inte rnally. smartgen allows the user to select the threshol ds for the almost- empty and almost-full flags in terms of either the read data words or the write data words, and makes the appropriate conv ersions for each flag. after the empty or full states are reached, the fi fo can be configured so the fifo counters either stop or continue counting. for timing numbers, refer to the appropriate fami ly datasheet. signal descriptions for fifo4k18 the following signals are used to co nfigure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( table 7-6 ). wblk and rblk these signals are acti ve-low and will enable th e respective ports when lo w. when the rblk signal is high, that port?s output s hold the previous value. wen and ren read and write enables. wen is active-low and re n is active-high by defa ult. these signals can be configured as active-high or -low. wclk and rclk these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. note: for the automotive proasic3 fifo4k18, for the same clock, 180 out of phase (inverted) between clock pins should be used. rpipe this signal is used to specify pipelined r ead on the output. a lo w on rpipe indicates a nonpipelined read, and the data ap pears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. reset this active-low signal resets the control logic and forces the output hold state registers to zero when asserted. it does not reset the contents of the memory array ( table 7-7 on page 7-14 ). table 7-6 ? aspect ratio settings for ww[2:0] ww[2:0] rw[2:0] dw 000 000 4k1 001 001 2k2 010 010 1k4 011 011 5129 100 100 25618 101, 110, 111 101, 110, 111 reserved
sram and fifo memori es in actel's low-p ower flash devices 7-14 v1.5 while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care mu st be taken not to assert it too close to the edges of active read and write clocks. wd this is the input data bus and is 18 bits wide. not all 18 bits are valid in al l configurations. when a data width less than 18 is specified, unus ed higher-order signals must be grounded ( table 7-7 ). rd this is the output data bus and is 18 bits wide. not all 18 bits are va lid in all configurations. like the wd bus, high-order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( table 7-7 ). estop, fstop estop is used to stop the fifo re ad counter from further counting on ce the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. fstop is used to stop th e fifo write counter from further coun ting once the fifo is full (i.e., the full flag goes high). a high on this signal inhibits the counting. for more information on th ese signals, refer to the "estop and fstop usage" section on page 7-15 . full, empty when the fifo is full and no more data can be written, the full flag asse rts high. the full flag is synchronous to wclk to inhibit writing immediately upon detection of a full condition and to prevent overflows. since the write address is co mpared to a resynchron ized (and thus time- delayed) version of the read addr ess, the full flag will remain asserted until two wclk active edges after a read operation el iminates the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immediately upon detection of an empty condition and to prevent underflows. since th e read address is compared to a resynchronized (and thus time- delayed) version of the write address, the empt y flag will remain asserted until two rclk active edges after a write operation removes the empty condition. for more information on these signals, refer to the "fifo flag usage cons iderations" section on page 7-15 . afull, aempty these are programmable flags and will be asse rted on the threshold specified by afval and aeval, respectively. when the number of words store d in the fifo reaches the am ount specified by aeval while reading, the aempty output will go high. likewis e, when the number of words stored in the fifo reaches the amount specified by afval while writing, the afull output will go high. afval, aeval the aeval and afval pins are used to specify th e almost-empty and almost -full threshold values. they are 12-bit signals. for more information on thes e signals, refer to the "fifo flag usage considerations" section on page 7-15 . table 7-7 ? input data signal usage fo r different aspect ratios dw wd/rd unused 4k1 wd[17:1], rd[17:1] 2k2 wd[17:2], rd[17:2] 1k4 wd[17:4], rd[17:4] 5129 wd[17:9], rd[17:9] 25618 ?
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-15 fifo usage estop and fstop usage the estop pin is used to stop th e read counter from co unting any further once the fifo is empty (i.e., the empty flag goes high). likewise, the fstop pin is used to stop the wr ite counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the device start the co unt at zero, reach the maximum depth for the configuration (e.g., 511 for a 5129 configurat ion), and then restart at zero. an example application for esto p, where the read counter keeps counti ng, would be writing to the fifo once and reading the same content over an d over without doing another write. fifo flag usage considerations the aeval and afval pins are used to specify th e 12-bit aempty and afull threshold values. the fifo contains separate 12-bit write address (waddr) and read address (raddr) counters. waddr is incremented every time a write operation is pe rformed, and raddr is in cremented every time a read operation is performed. whenever the di fference between waddr and raddr is greater than or equal to afval, the afull output is a sserted. likewise, whenever the difference between waddr and raddr is less than or equal to aeva l, the aempty output is asserted. to handle different read and write aspect ratios, afval and aeval are expressed in terms of total data bits instead of total data words. when users specify afval and aeval in terms of read or write words, the smartgen tool translates them into bit addr esses and configures these signals automatically. smartgen configures the afull flag to assert wh en the write address exceeds the read address by at least a predefined value. in a 2k8 fifo, for example, a value of 1,500 for afval means that the afull flag will be asserted after a write when th e difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). it will stay asserted until the difference between the writ e and read addresses drops below 1,500. the aempty flag is asserted when the difference between the write address and the read address is less than a predefined value. in the exampl e above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. it will stay asserted un til that difference rises above 200. note that the fifo can be configured with different read and write widths; in this case, the afval setting is based on the number of write data entries, and th e aeval setting is based on the number of read data entries. for aspect ratios of 5129 and 25618, only 4,096 bits can be addressed by the 12 bits of afval and aeval. the number of words must be multiplied by 8 an d 16 instead of 9 and 18. the smartgen tool automatically uses the proper values. to avoid halfwords being written or read, which could happen if different read and write as pect ratios were specified, the fifo will assert full or empty as soon as at least one word canno t be written or read. for example, if a two-bit word is written and a four-bit word is being read, the fifo will re main in the empty state when the first word is written. this occurs even if the fifo is not completely empty, because in this case, a complete word cannot be read. the sa me is applicable in the full stat e. if a four-bit word is written and a two-bit word is read, the fi fo is full and one word is read . the full flag will remain asserted because a complete word cannot be written at this point. variable aspect ra tio and cascading variable aspect ratio and cascading allow users to configure the memory in the width and depth required. the memory block can be configured as a fifo by combining the basic memory block with dedicated fifo controller logic. the fifo macro is named fifo4kx18. low-power flash device ram can be configured as 1, 2, 4, 9, or 18 bits wide. by cascading the memory blocks, any multiple of those widths can be created. the ram blocks can be from 256 to 4,096 bits deep, depending on the aspect ratio, and the blocks can also be casc aded to create deeper areas. refer to the aspect ratios available for ea ch macro cell in the "sram features" se ction on page 7-7 . the largest continuous configurable memory area is equal to half the total memory available on the device, because the ram is separated into two groups, one on each side of the device. the actel smartgen core generator will automati cally configure and cascade both ram and fifo blocks. cascading is accomplished using dedicated memory logic and does not consume user gates for depths up to 4,096 bits deep and widths up to 18, depending on the configuration. deeper memory will utilize some user gates to multiplex the outputs.
sram and fifo memori es in actel's low-p ower flash devices 7-16 v1.5 generated ram and fifo macros ca n be created as either structural vhdl or verilog for easy instantiation into the design. us ers of actel libero ide can crea te a symbol for the macro and incorporate it into a design schematic. table 7-10 on page 7-17 shows the number of memory blocks required for each of the supported depth and width memory configurations, and for each depth and width combination. for example, a 256-bit deep by 32-bit wide two-port ram woul d consist of two 25618 ram blocks. the first 18 bits would be stored in the first ram block, and the remaining 14 bits would be implemented in the other 25618 ram block. this second ram block would have four bits of unused storage. similarly, a dual-port memory bloc k that is 8,192 bits d eep and 8 bits wide would be implemented using 16 memory blocks. the dual -port memory would be configur ed in a 4,0961 aspect ratio. these blocks would then be casc aded two deep to achi eve 8,192 bits of depth, and eight wide to achieve the eight bits of width. table 7-8 and table 7-9 show the maximum potential widt h and depth configuration for each device. note that 15 k and 30 k gate devices do not support ram or fifo. table 7-8 ? memory availability per igloo and proasic3 device device ram blocks maximum potential width 1 maximum potential depth 2 igloo igloo nano igloo plus proasic3 proasic3 nano proasic3l depth width depth width agl060 agln060 aglp060 a3p060 a3pn060 4 256 72 (418) 16,384 (4,0964) 1 agl125 agln125 aglp125 a3p125 a3pn125 8 256 144 (818) 32,768 (4,0948) 1 agl250 agln250 a3p250/l a3pn250 8 256 144 (818) 32,768 (4,0968) 1 agl400 a3p400 12 256 216 (1218) 49,152 (4,09612) 1 agl600 a3p600/l 24 256 432 (2418) 98,304 (4,09624) 1 agl1000 a3p1000/l 32 256 576 (3218) 131,072 (4,09632) 1 agle600 a3pe600 24 256 432 (2418) 98,304 (4,09624) 1 a3pe1500 60 256 1,080 (6018) 245,760 (4,09660) 1 agle3000 a3pe3000/l 112 256 2,016 (11218) 458,752 (4,096112) 1 notes: 1. maximum potential width uses the two-port configuration. 2. maximum potential depth uses the dual-port configuration. table 7-9 ? memory availability per fusion device device ram blocks maximum potential width 1 maximum potential depth 2 depth width depth width afs090 6 256 108 (618) 24,576 (4,0946) 1 afs250 8 256 144 (818) 32,768 (4,0948) 1 afs600 24 256 432 (2418) 98,304 (4,09624) 1 afs1500 60 256 1,080 (6018) 245,760 (4,09660) 1 notes: 1. maximum potential width uses the two-port configuration. 2. maximum potential depth uses the dual-port configuration.
v1.5 7-17 sram and fifo memories in ac tel?s low-power flash devices table 7-10 ? ram and fifo memory block consumption depth 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 two-port dual-port dual-port dual-port dual-port du al-port dual-port dual-port dual-port dual-port width 1 number block 1 1 1 1 1 1 2 4 8 16 1 configuration any any any 1,024 4 2,048 2 4,096 1 2 (4,096 1) cascade deep 4 (4,096 1) cascade deep 8 (4,096 1) cascade deep 16 (4,096 1) cascade deep 2 number block 1 1 1 1 1 2 4 8 16 32 configuration any any any 1,0244 2,048 2 2 (4,096 1) cascaded wide 4 (4,096 1) cascaded 2 deep and 2 wide 8 (4,096 1) cascaded 4 deep and 2 wide 16 (4,096 1) cascaded 8 deep and 2 wide 32 (4,096 1) cascaded 16 deep and 2 wide 4 number block 1 1 1 1 2 4 8 16 32 64 configuration any any any 1,024 4 2 (2,048 2) cascaded wide 4 (4,096 1) cascaded wide 4 (4,096 1) cascaded 2 deep and 4 wide 16 (4,096 1) cascaded 4 deep and 4 wide 32 (4,096 1) cascaded 8 deep and 4 wide 64 (4,096 1) cascaded 16 deep and 4 wide 8 number block 1 1 1 2 4 8 16 32 64 configuration any any any 2 (1,024 4) cascaded wide 4 (2,048 2) cascaded wide 8 (4,096 1) cascaded wide 16 (4,096 1) cascaded 2 deep and 8 wide 32 (4,096 1) cascaded 4 deep and 8 wide 64 (4,096 1) cascaded 8 deep and 8 wide 9 number block 1 1 1 2 4 8 16 32 configuration any any any 2 (512 9) cascaded deep 4 (512 9) cascaded deep 8 (512 9) cascaded deep 16 (512 9) cascaded deep 32 (512 9) cascaded deep 16 number block 1 1 1 4 8 16 32 64 configuration 256 18 256 18 256 18 4 (1,024 4) cascaded wide 8 (2,048 2) cascaded wide 16 (4,096 1) cascaded wide 32 (4,096 1) cascaded 2 deep and 16 wide 32 (4,096 1) cascaded 4 deep and 16 wide 18 number block 1 2 2 4 8 18 32 configuration 256 8 2 (512 9) cascaded wide 2 (512 9) cascaded wide 4 (512 9) cascaded 2 deep and 2 wide 8 (512 9) cascaded 4 deep and 2 wide 16 (512 9) cascaded 8 deep and 2 wide 16 (512 9) cascaded 16 deep and 2 wide 32 number block 2 4 4 8 16 32 64 configuration 2 (256 18) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded wide 8 (1,024 4) cascaded wide 16 (2,048 2) cascaded wide 32 (4,096 1) cascaded wide 64 (4,096 1) cascaded 2 deep and 32 wide 36 number block 2 4 4 8 16 32 configuration 2 (256 18) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded 2 deep and 4 wide 16 (512 9) cascaded 4 deep and 4 wide 16 (512 9) cascaded 8 deep and 4 wide 64 number block 4 8 8 16 32 64 configuration 4 (256 18) cascaded wide 8 (512 9) cascaded wide 8 (512 9) cascaded wide 16 (1,024 4) cascaded wide 32 (2,048 2) cascaded wide 64 (4,096 1) cascaded wide 72 number block 4 8 8 16 32 configuration 4 (256 18) cascaded wide 8 (512 9) cascaded wide 8 (512 9) cascaded wide 16 (512 9) cascaded wide 16 (512 9) cascaded 4 deep and 8 wide note: memory configurations represented by grayed cells are not supported.
sram and fifo memori es in actel's low-p ower flash devices 7-18 v1.5 initializing the ram/fifo the sram blocks can be initialized with data to us e as a lookup table (lut). data initialization can be accomplished either by loading the data th rough the design logic or through the ujtag interface. the ujtag macro is used to allow access from the jtag port to the internal logic in the device. by sending the appropriate initializati on string to the jtag test access port (tap) controller, the designer can put th e jtag circuitry into a mode that allows the user to shift data into the array logic through the jtag port using the ujtag macro. for a mo re detailed explanation of the ujtag macro, refer to ujtag applications in acte l?s low-power flash devices . a user interface is required to receive the user command, initiali zation data, and clock from the ujtag macro. the interface must synchronize and lo ad the data into the correct ram block of the design. the main outputs of the user interface block are the following: ? memory block chip select: selec ts a memory block for initializa tion. the chip selects signals for each memory bloc k that can be generated from different user-defined pockets or simple logic, such as a ring counter (see below). ? memory block write address: identifies the ad dress of the memory cell that needs to be initialized. ? memory block write data: the interface block re ceives the data serially from the utdi port of the ujtag macro and loads it in parallel in to the write data ports of the memory blocks. ? memory block write clock: drives the wclk of the memory block and synchronizes the write data, write address, and chip select signals. figure 7-8 shows the user interface between ujtag and the memory blocks. an important component of the interface between the ujt ag macro and the ram blocks is a serial-in/parallel-out shift register. the width of the shift register should equal the data width of the ram blocks. the ram data arrives serially fro m the utdi output of the ujtag macro. the data must be shifted into a shift regi ster clocked by the jtag clock (provided at the udrck output of the ujtag macro). then, after the shift register is fu lly loaded, the data must be tran sferred to the write data port of the ram block. to synchronize the loading of th e write data with the write address and write clock, the output of the shift register can be pipelined before driving the ram block. the write address can be generated in different ways. it can be imported through the tap using a different instruction opcode and another shift re gister, or generated internally using a simple figure 7-8 ? interfacing tap ports and sram blocks trst ujtag tdo tdi tms tck trst tdo tdi tms tck urstb udrupd udrsh udrcap udrck utdi utdo uireg[7:0] ir[7:0] user interface wdata waddr wclk wen1 wen2 wen3 reset dr_update dr_shift dr_capture dr_clk din dout wd waddr wclk wen ram1 wd waddr wclk wen ram2 wd waddr wclk wen ram3
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-19 counter. using a counter to gene rate the address bits and sweep through the address range of the ram blocks is recommended, since it reduces the complexity of the user interface block and the board-level jtag driver. moreover, using an intern al counter for address ge neration speeds up the initialization procedure, since the user only needs to import the data through the jtag port. the designer may use different me thods to select among the multiple ram blocks. using counters along with demultiplexers is one approach to set the write enable signals. basicall y, the number of ram blocks needing initialization determines the mo st efficient approach. for example, if all the blocks are initialized with the same data, one enable signal is enough to activate the write procedure for all of them at the same time. an other alternative is to use different opcodes to initialize each memory block. for a small number of ram blocks, using counters is an optimal choice. for example, a ring counter can be used to select from multiple ram blocks. the clock driver of this counter needs to be con trolled by the address generation process. once the addressing of one block is finished, a clock pulse is sent to the (ring) counter to select the next memory block. figure 7-9 illustrates a simple block diagram of an interface block between ujtag and ram blocks. in the circuit shown in figure 7-9 , the shift register is enabled by the udrsh output of the ujtag macro. the counters and chip sele ct outputs are contro lled by the value of the tap instruction register. the comparison block compares the uire g value with the "start initialization" opcode value (defined by the user). if the result is true, the counters start to generate addresses and activate the wen inputs of appropriate ram blocks. the udrupd output of the ujtag macro, also shown in figure 7-9 , is used for generating the write clock (wclk) and synchronizing the data register and address counter with wclk. udrupd is high when the tap controller is in th e data register update state, which is an indication of completing the loading of one data word. once the tap controller goes into the data register update state, the udrupd output of the ujtag macro goes hi gh. therefore, the pipe line register and the address counter place the proper data and ad dress on the outputs of the interface block. meanwhile, wclk is defined as th e inverted udrupd. this will prov ide enough time (equal to the udrupd high time) for the data and address to be placed at the proper ports of the ram block before the rising ed ge of wclk. the inverter is not required if the ram blocks are clocked at the falling edge of the write clock. an example of this is described in the "example of ram initialization" section on page 7-20 . figure 7-9 ? block diagram of a sample user interface n n m m utdi udrsh udrck utdo udrupdi uireg urstb clk enable sin serial-to-port shift register pout sout d en reset clk en reset clk q q clk wdata wclk wen1 wen2 weni waddr chip select data reg. addr counter ring counter binary counter compare with defined opcode in result
sram and fifo memori es in actel's low-p ower flash devices 7-20 v1.5 example of ram initialization this section of the document presents a sample design in which a 44 ram block is being initialized through the jtag port. a test feature ha s been implemented in the design to read back the contents of the ram after init ialization to verify the procedure. the interface block of th is example performs two major functions: initialization of the ram block and running a test procedure to read back the cont ents. the clock output of the interface is either the write clock (for initialization) or the read cl ock (for reading back the contents). the verilog code for the interface bl ock is included in the "sample verilog code" section on page 7-21 . for simulation purposes, users can declare the input ports of the ujtag macro for easier assignment in the testbench. however, the ujtag input ports should not be declared on the top level during synthesis. if the input ports of the uj tag are declared during synthesis, the synthesis tool will instantiate input buffer s on these ports. the input buffers on the ports will cause compile to fail in designer. figure 7-10 shows the simulation resu lts for the initiali zation step of the example design. the clk_out signal, which is the clock output of the interface bl ock, is the inverted dr_update output of the ujtag macro. it is clear that it give s sufficient time (while the tap controller is in the data register update state) for the write address and data to become stab le before loading them into the ram block. figure 7-11 presents the test procedure of the example. the data read back from the memory block matches the written data, thus ve rifying the design functionality. figure 7-10 ? simulation of initialization step figure 7-11 ? simulation of the test procedure of the example
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-21 the rom emulation application is based on ram bloc k initialization. if the user's main design has access only to the read ports of the ram bloc k (raddr, rd, rclk, and ren), and the contents of the ram are already initialized through the tap, then the memory bloc ks will emulate rom functionality for the core design. in this case, the write ports of the ram blocks are accessed only by the user interface block, and the interface is activated only by the tap instruction register contents. users should note that the contents of the ram blocks are lost in the absence of applied power. however, the 1 kbit of flash memory, flashrom, in low-power flash devices can be used to retain data after power is removed from the device. refer to flashrom in actel?s lo w-power flash devices for more information. sample verilog code interface block `define initialize_start 8'h22 //initialization start command value `define initialize_stop 8'h23 //initialization start command value module interface(ir, rst_n, data_shift, clk_in, data_update, din_ser, dout_ser, test, test_out,test_clk,clk_out,wr_en,rd_en,write_word,read_word,rd_addr, wr_addr); input [7:0] ir; input [3:0] read_word; //ram data read back input rst_n, data_shift, clk_in, data_update, din_ser; //initialization signals input test, test_clk; //test procedure clock and command input output [3:0] test_out; //read data output [3:0] write_word; //write data output [1:0] rd_addr; //read address output [1:0] wr_addr; //write address output dout_ser; //tdo driver output clk_out, wr_en, rd_en; wire [3:0] write_word; wire [1:0] rd_addr; wire [1:0] wr_addr; wire [3:0] q_out; wire enable, test_active; reg clk_out; //select clock for initialization or readback test always @(enable or test_clk or data_update) begin case ({test_active}) 1 : clk_out = test_clk ; 0 : clk_out = !data_update; default : clk_out = 1'b1; endcase end assign test_active = test && (ir == 8'h23); assign enable = (ir == 8'h22); assign wr_en = !enable; assign rd_en = !test_active; assign test_out = read_word; assign dout_ser = q_out[3]; //4-bit sin/pout shift register shift_reg data_shift_reg (.shiften(data_shift), .shiftin(din_ser), .clock(clk_in), .q(q_out)); //4-bit pipeline register d_pipeline pipeline_reg (.data(q_out), .clock(data_update), .q(write_word));
sram and fifo memori es in actel's low-p ower flash devices 7-22 v1.5 // addr_counter counter_1 (.clock(data_update), .q(wr_addr), .aset(rst_n), .enable(enable)); addr_counter counter_2 (.clock(test_clk), .q(rd_addr), .aset(rst_n), .enable( test_active)); endmodule interface block / ujtag wrapper this example is a sample wrap per, which connects the interface block to the ujtag and the memory blocks. // wrapper module top_init (tdi, trstb, tms, tck, tdo, test, test_clk, test_ out); input tdi, trstb, tms, tck; output tdo; input test, test_clk; output [3:0] test_out; wire [7:0] ir; wire reset, dr_shift, dr_cap, init_clk, dr_update, data_in, data_out; wire clk_out, wen, ren; wire [3:0] word_in, word_out; wire [1:0] write_addr, read_addr; ujtag ujtag_u1 (.uireg0(ir[0]), .uireg1(ir[1]), .uireg2(ir[2]), .uireg3(ir[3]), .uireg4(ir[4]), .uireg5(ir[5]), .uireg6(ir[6]), .uireg7(ir[7]), .urstb(reset), .udrsh(dr_shift), .udrcap(dr_cap), .udrck(init_clk), .udrupd(dr_update), .ut-di(data_in), .tdi(tdi), .tms(tms), .tck(tck), .trstb(trstb), .tdo(tdo), .ut-do(data_out)); mem_block ram_block (.do(word_out), .rclock(clk_out), .wclock(clk_out), .di(word_in), .wrb(wen), .rdb(ren), .wad-dr(write_addr), .raddr(read_addr)); interface init_block (.ir(ir), .rst_n(reset), .data_shift(dr_shift), .clk_in(init_clk), .data_update(dr_update), .din_ser(data_in), .dout_ser(data_out), .test(test), .test_out(test_out), .test_clk(test_clk), .clk_out(clk_out), .wr_en(wen), .rd_en(ren), .write_word(word_in), .read_word(word_out), .rd_addr(read_addr), .wr_addr(write_addr)); endmodule address counter module addr_counter (clock, q, aset, enable); input clock; output [1:0] q; input aset; input enable; reg [1:0] qaux; always @(posedge clock or negedge aset) begin if (!aset) qaux <= 2'b11; else if (enable) qaux <= qaux + 1; end assign q = qaux; endmodule
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-23 pipeline register module d_pipeline (data, clock, q); input [3:0] data; input clock; output [3:0] q; reg [3:0] q; always @ (posedge clock) q <= data; endmodule 4x4 ram block (created by sm artgen core generator) module mem_block(di,do,waddr,raddr,wrb,rdb,wclock,rclock); input [3:0] di; output [3:0] do; input [1:0] waddr, raddr; input wrb, rdb, wclock, rclock; wire webp, weap, vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); inv webubbleb(.a(wrb), .y(webp)); ram4k9 ramblock0(.addra11(gnd), .addra10(gnd), .addra9(gnd), .addra8(gnd), .addra7(gnd), .addra6(gnd), .addra5(gnd), .addra4(gnd), .addra3(gnd), .addra2(gnd), .addra1(raddr[1]), .addra0(raddr[0]), .addrb11(gnd), .addrb10(gnd), .addrb9(gnd), .addrb8(gnd), .addrb7(gnd), .addrb6(gnd), .addrb5(gnd), .addrb4(gnd), .addrb3(gnd), .addrb2(gnd), .addrb1(waddr[1]), .addrb0(waddr[0]), .dina8(gnd), .dina7(gnd), .dina6(gnd), .dina5(gnd), .dina4(gnd), .dina3(gnd), .dina2(gnd), .dina1(gnd), .dina0(gnd), .dinb8(gnd), .dinb7(gnd), .dinb6(gnd), .dinb5(gnd), .dinb4(gnd), .dinb3(di[3]), .dinb2(di[2]), .dinb1(di[1]), .dinb0(di[0]), .widtha0(gnd), .widtha1(vcc), .widthb0(gnd), .widthb1(vcc), .pipea(gnd), .pipeb(gnd), .wmodea(gnd), .wmodeb(gnd), .blka(weap), .blkb(webp), .wena(vcc), .wenb(gnd), .clka(rclock), .clkb(wclock), .reset(vcc), .douta8(), .douta7(), .douta6(), .douta5(), .douta4(), .douta3(do[3]), .douta2(do[2]), .douta1(do[1]), .douta0(do[0]), .doutb8(), .doutb7(), .doutb6(), .doutb5(), .doutb4(), .doutb3(), .doutb2(), .doutb1(), .doutb0()); inv webubblea(.a(rdb), .y(weap)); endmodule
sram and fifo memori es in actel's low-p ower flash devices 7-24 v1.5 software support the smartgen core generator is the easiest wa y to select and config ure the memory blocks ( figure 7-12 ). smartgen automatically selects the proper memory block type an d aspect ratio, and cascades the memory blocks based on the user's se lection. smartgen also configures any additional signals that may require tie-off. smartgen will attempt to use the minimum number of blocks required to implement the desired memory. when cascading, smartgen will configure the memory fo r width before configuring for depth. for example, if the user requests a 2568 fifo, smartgen will use a 5129 fifo configuration, not 25618. figure 7-12 ? smartgen core generator interface
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-25 smartgen enables the user to co nfigure the desired ram element to use either a single clock for read and write, or two independent clocks for read and write. the user can select the type of ram as well as the width/depth and several other parameters ( figure 7-13 ). smartgen also has a port mapping option that allows the user to specify the names of the ports generated in the memory block ( figure 7-14 ). figure 7-13 ? smartgen memory configuration interface figure 7-14 ? port mapping interface for smartgen-generated memory
sram and fifo memori es in actel's low-p ower flash devices 7-26 v1.5 smartgen also configures the fifo according to user specifications. users can select no flags, static flags, or dynamic flags. static flag settings are configured using configuration flash and cannot be altered without reprogramming th e device. dynamic flag settings are determined by register values and can be altered without reprogramming the device by reloading the register values either from the design or through the ujtag inte rface described in the "initializing the ram/fifo" section on page 7-18 . smartgen can also configure the fifo to contin ue counting after the fifo is full. in this configuration, the fifo write coun ter will wrap after the counter is full and continue to write data. with the fifo configured to continue to read a fter the fifo is empty, the read counter will also wrap and re-read data that was previously read. this mode can be used to continually read back repeating data patterns stored in the fifo ( figure 7-15 ). fifos configured using smartgen can also make use of the port mapping feature to configure the names of the ports. limitations users should be aware of the following limitatio ns when configuring sram blocks for low-power flash devices: ? smartgen does not track the target device in a family, so it cannot determine if a configured memory block will fit in the target device. ? dual-port rams with different read an d write aspect ratios are not supported. ? cascaded memory blocks can only use a maximum of 64 blocks of ram. ? the full flag of the fifo is sensitive to the maximum depth of the actual physic al fifo block, not the depth requested in the smartgen interface. figure 7-15 ? smartgen fifo configuration interface
sram and fifo memories in ac tel?s low-power flash devices v1.5 7-27 conclusion fusion, igloo, and proasic3 devices provide user s with extremely flexible sram blocks for most design needs, wi th the ability to choose between an ea sy-to-use dual-port memory or a wide-word two-port memory. used with the bu ilt-in fifo controllers, these memory blocks also serve as highly efficient fifos that do not consume user gates when impl emented. the actel smartgen core generator provides a fast and easy way to conf igure these memory elem ents for use in designs. related documents handbook documents ujtag applications in acte l?s low-power flash devices www.actel.com/document s/lpd_ujtag_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-008-5 revised december 2008
sram and fifo memori es in actel's low-p ower flash devices 7-28 v1.5 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.5) page v1.4 (october 2008) igloo nano and proasic3 nano devices were added to table 7-1 flash- based fpgas . 7-4 igloo nano and proasic3 na no devices were added to table 7-8 interfacing tap ports and sram blocks . 7-18 v1.3 (august 2008) the "sram/fifo support in flas h-based devices" section was revised to include new families and make the information more concise. 7-4 the "sram and fifo architecture" section was modified to remove "igloo and proasic3e" from the de scription of what the me mory block includes, as this statement applies to all memory blocks. 7-5 wording in the "clocking" section was revised to change "igloo and proasic3 devices support inversion" to "low-power flash devices support inversion." the reference to igloo an d proasic3 development tools in the last paragraph of the section was chan ged to refer to development tools in general. 7-11 the "estop and fstop usage" section was updated to refe r to fifo counters in devices in general rather than only igloo and proasic3e devices. 7-15 v1.2 (june 2008) the note was removed from figure 7-7 ram block with embedded fifo controller and placed in the wclk and rclk description. 7-12 the "wclk and rclk" description was revised. 7-13 v1.1 (march 2008) the following changes were made to the family descriptions in table 7-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 7-4 v1.0 (january 2008) the "introduction" section was updated to include the igloo plus family. 7-1 the "device architecture" section was updated to state that 15 k gate devices do not supp ort sram and fifo. 7-1 the first note in figure 7-1 igloo and proasi c3 device architecture overview was updated to include mention of 15 k gate devices, and igloo plus was added to the second note. 7-3 table 7-1 flash-based fpgas and associated text we re updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 7-4 the text introducing table 7-8 memory availability per igloo and proasic3 device was updated to replace "a3p030 and agl030" with "15 k and 30 k gate devices." table 7-8 memory availabili ty per igloo and proasic3 device was updated to remove agl400 and agle1500 and include igloo plus and proasic3l devices. 7-16
analog system

v1.0 8-1 8 ? designing the fusion analog system introduction actel fusion ? devices offer robust and flexib le analog mixed-si gnal capability in addition to the high-performance flash fpga fabric and flash memory block. the ma ny built-in analog peripherals include a configurable 32:1 analog mux, up to 10 independent mosfet gate driver outputs, and a configurable analog-to-digital converter (adc). fusion also introduces the analog quad i/o structure; each analog quad consi sts of three analog inputs and one gate driver. each quad can be configured in various built-in circuit combinations , such as prescaler circ uits, three-digital-input circuits, a current mo nitor circuit, or a temperature monito r circuit. each prescaler has multiple scaling factors programmed by fpga signals to support a large range of analog inputs with positive or negative polarity. when the current monitor circuit is selected, two adjacent analog inputs measure the voltage drop across a small external sense resistor. built-in operational amplifiers amplify small voltage signals for accurate current measurement. one anal og input in each quad can be connected to an external temperature mo nitor diode. these comp onents are used as the building blocks in designing an analog system. the analog quad i/o configuration, adc reso lution, channel sampling sequence, and sampling rate are programmable and implemented in the fpga logic using designer and actel libero ? integrated design envi ronment (ide) software tool support. an overview of different design methodologies is covered in the fusion design soluti ons and methodologies chapter. this chapter gives a detailed description of the analog quads, adc, and analog configuration mux (acm). it also covers the details of the analog system with the explanation and sample calculations of accuracy, sample rate, sample sequencing, acquisit ion time, adc clocking, and prescaler selection. analog-to-digital converter background an analog-to-digital converter is used to capture discrete samples of a continuous analog voltage and provide a discrete binary representation of the signal. analog-to-digital converters are gene rally characterized in three ways: ? input voltage range ?resolution ? bandwidth or conversion rate the input voltage range of an adc is determined by its reference voltage (v ref ). actel fusion? devices include an internal 2.56 v reference, or the user can supply an external reference of up to 3.3 v. the following examples use th e internal 2.56 v reference, so th e full-scale input range of the adc is 0 to 2.56 v. for input signal ranges less than or greater than v ref , an analog scaling function such as that built into the fusion analog quad prescaler can be used to amplify or attenuate the input signal, thus matching the input voltage range of the adc. the resolution (lsb) of th e adc is a function of th e number of binary bits in the converter. the adc approximates the value of the input voltage using 2 n ?steps,? where n is the number of bits in the converter. each step therefore represents v ref /2 n volts. in the case of the fusion adc configured for 12-bit operation, the lsb is 2.56 v / 4096 = 0.625 mv. finally, bandwidth is an indication of the ma ximum number of conver sions the adc can perform each second. the bandwidth of an adc is con strained by its architecture and several key performance characteristics. in addi tion, the bandwidth is limited by fusion system considerations. see the "sample rate and sample sequence calculation" sect ion on page 8-8 .
designing the fusi on analog system 8-2 v1.0 there are several popular adc arch itectures, each with its own advantages and limitations. the analog-to-digital converter in fusion devices is a switched-capacitor successive approximation register (sar) adc. it supports 8-, 10-, and 12-b it modes of operation with a cumulative sample rate up to 600 k samples per second (ksps). built -in bandgap circuitry offers 1% internal voltage reference accuracy, or an external reference voltage can be used. as shown in figure 8-1 , a sar adc contains n capacitors with binary-weighted values. to begin a conversion, all of the capa citors are quickly discharged. then v in is applied to all the capacitors for a period of time (a cquisition time) during which the capacitors are charged to a value very close to v in . then all of the capacitors are switched to ground, and thus ?v in is applied across the comparator. now the conversion process begins . first, c is switched to v ref . because of the binary weighting of the capacitors, the voltage at the in put of the comparator is then ?v in +v ref /2. if v in is greater than v ref / 2, the output of the comparator is 1; otherwis e, the comparator output is 0. a register is clocked to retain this valu e as the msb of the result. next, if the msb is 0, c is switched back to ground; otherwise, it remains connected to v ref , and c/2 is connected to v ref . the result at the comparator input is now either ?v in +v ref /4 or ? v in +3v ref / 4 (depending on the state of the msb), an d the comparator output now indicates the value of the next most significant bit. this bit is likewise registered, and the process continues for each subsequent bit until a conversion is completed. the conversion process requires some acquisition time plus n + 1 adc clock cycles to complete. figure 8-1 ? example sar adc architecture comparator c c / 2 c / 4 c / 2 n?2 c / 2 n?1 c / 2 n?1 v ref v in
designing the fusion analog system v1.0 8-3 this process results in a binary approximation of v in . generally, there is a fixed interval t, the sampling period, between the samples. the inverse of the sampli ng period is often referred to as the sampling frequency f s = 1 / t. the combined effe ct is illustrated in figure 8-2 . figure 8-2 demonstrates that if the signal changes fa ster than the sampling rate can accommodate, or if the actual value of v in falls between ?counts? in the result, this information is lost during the conversion. there are several techniques th at can be used to address these issues. first, the sampling rate must be chosen to provide enough samp les to adequately represent the input signal. based on the nyqu ist-shannon sampling th eorem, the minimum sampling rate must be at least twice the frequency of the highest frequency component in the target signal (nyquist frequency). for example, to re-cre ate the frequency conten t of an audio signal with up to 22 khz bandwidth, the user must sa mple it at a minimum of 44 ksps. however, as shown in figure 8-2 , significant post-pr ocessing of the data is required to in terpolate the value of the waveform during the time between each sample. similarly, to re-create the amplitude variation of a signal, the signal must be sampled with adequate resolution. continuing with the audi o example, the dynamic range of the human ear (the ratio of the amplitude of the threshold of hearing to the threshold of pain) is generally accepted to be 135 db, and the dynamic range of a typical symphony orchestra performance is around 85 db. most commercial recording media provide about 96 db of dynamic range using 16-bit sample resolution. but 16-bit fidelity does not necessarily mean th at you need a 16-bit adc. as long as the input is sampled at or above th e nyquist frequency, post-processing techniques can be used to interpolate intermediate values and reconstruct the original input signal to within desired tolerances. if sophisticated digital signal processing (dsp) capabilities are available, the best results are obtained by implementing a reco nstruction filter, which is used to interpolate many intermediate values with higher resolution than the original data. interpol ating many intermediate values, increases the effective number of samples, and hi gher resolution increases the effective number of bits in the sample. in many cases, however, it is not cost-effective or nece ssary to implement such a sophisticated recon struction algorithm. for ap plications that do not require extremely fine reproduction of the input signal, alternative me thods can enhance digital sampling results with relatively simple post-processing . the details of such techniques are out of the scope of this chapter; refer to the improving adc results through oversa mpling and post-p rocessing of data white paper for more information. figure 8-2 ? analog-to-digital conversion example t lsb
designing the fusi on analog system 8-4 v1.0 adc clock when the fusion adc is used, the adc clock de termines the sampling throughput, and the system clock determines the operating speed of the smartgen ip and/or the us er?s design logic. this section examines the relationship between these two cloc ks and how the sampling rate is related to the accuracy. a simplified block diag ram of the adc is given in figure 8-3 . the adc clock has a maximum frequency of 10 mhz and can be derived from the system clock. to generate the adc clock, the system clock is divided by a multiple of four. the exact multiple of four used is determined by the 8-bit us er-configurable tvc[7:0] register ( eq 8-1 ). adc clock frequency (mhz) = system cl ock (mhz) / (4 (tvc_reg + 1)) eq 8-1 where tvc_reg is the tvc register value, from 0 to 255. the tvc register setting is used to ensure that the adc clock frequency does not exceed 10 mhz. note that the 10 mhz maximum fr equency for the adc cl ock implies that a higher system clock frequency does not always result in a higher adc clock frequen cy. for example, a 40 mhz system clock frequency enables a maximum adc clock freq uency of 10 mhz (tvc register value of 0), whereas a 50 mhz system frequency results in a slower maximum adc clock frequency, 6.25 mhz, because a tvc register value of 0 would give an adc clock frequency of 12.5 mhz?above the 10 mhz limit. note that this 10 mhz limit means that a higher sy stem clock frequency does not always result in a higher adc clock frequency . for example, a 40 mhz system clock frequency enables a maximum adc clock frequency of 10 mhz (tvc register value of 0). however, a 50 mhz system frequency results in a slower maximum adc clock frequenc y because a tvc register value of 0 would give an adc clock frequency of 12.5 mhz?above the 10 mhz li mit. setting the tvc register value to 1 in this case gives a maximum adc clock frequency of 6.25 mhz. in general, the performance of the adc is the ra te at which the adc can acquire or sample the analog input and convert it into a digital value. datasheet specifications define this in terms of samples per second (s/sec) or hertz (hz). the inverse of the conversi on time is the sampling rate for the channel. however, the sampli ng rate reported by smartgen includes the adc sample sequence controller (assc) overhead time. this time, the turnaround time, defines how fast an adc client can process data and give anot her start conversion signal. wi th no wait states, the assc turnaround time is 10 system clock cycles. eq 8-2 figure 8-3 ? simplified adc diagram sample rate 1 conversion time turnaround time + -------------------------------------------------------------------------------------------- - (s/sec) = s/h analog quad analog mux adc analog quad analog soft ip t_sample t_conv t_turnaround adcresult startconversion
designing the fusion analog system v1.0 8-5 the conversion time (t_conv) is the total time required to conver t an analog input signal into a digital output ( eq 8-3 ). t_conv = t_sync_read + t_sample + t_ distrib + t_post_cal + t_sync_write eq 8-3 the components of eq 8-3 are defined in table 8-1 . example 1 given that only one channel is used without prescaler, the maximum sample rate of a channel can be calculated as follows: system clock period = 1 / (40 mhz) = 25 ns adc clock period = 1 / (10 mhz) = 100 ns acquisition time = t_sample = 0.4 s resolution = 8 t_conv = t_sync_read + t_sample + t_ distrib + t_post_cal + t_sync_write t_conv = 25 ns + 400 ns + 8 100 ns + 2 100 ns + 25 ns = 1.45 s t_turnaround = 10 sys_clk = 250 ns note: to avoid using the prescaler, the maximum voltage value must be set between 2.01 v and 2.56 v in the smartgen gui to confi gure the peripheral as a direct input. table 8-1 ? adc conversion time formula elements equation description t_sync_read = sys_clk_period ? time to latch the input data ? sys_clk_period is the adc interface clock (10 ns to 250 ns). t_sample = (2 + stc) adc_clock_ period ? stc is the sample time control in the smartgen gui. this changes the acquisitio n time t_sample (sam ple-and-hold time). stc[7:0] ranges from 0 to 255. ? adc_clock_period is the adc internal clock period (100 ns to 2s). t_distrib = resoluti on adc_clock_period ? time of charge redistribution ? adc_clock_period is the adc internal clock period (100 ns to 2s). ? selectable 8-/10-/12-bit resolution mode t_post_cal = 2 adc_clock_peri od ? time for post-calibration ? adc_clock_period is the adc internal clock period. t_sync_write = sys_clk_period ? ti me for latching the output data ? sys_clk_period is the adc in terface clock period (10 ns to 250 ns). sample rate 1 1.45 s 0.25 s + ------------------------------------------- - ns 588 ksps ==
designing the fusi on analog system 8-6 v1.0 example 2 given that only one channel is used with the prescaler, the maximu m sample rate of a channel can be calculated as follows: system clock period = 1 / (80 mhz) = 12.5 ns adc clock period = 1 / (10 mhz) = 100 ns acquisition time = settling time = 10 s (max.) resolution = 8 t_conv = t_sync_read + t_sample + t_ distrib + t_post_cal + t_sync_write t_conv = 12.5 ns + 10000 ns + 8 100 ns + 2 100 ns + 12.5 ns = 11.025 s add turnaround time: 11.025 s + 0.125 s = 11.15 s example 3 given that only one channel is used with the prescaler, the maximu m sample rate of a channel can be calculated as follows: system clock period = 1 / (40 mhz) = 25 ns adc clock = 1 / (10 mhz) = 100 ns acquisition time = settling time = 10 s (max.) resolution = 8 t_conv = t_sync_read + t_sample + t_ distrib + t_post_cal + t_sync_write t_conv = 25 ns + 10000 ns + 8 100 ns + 2 100 ns + 25 ns = 11.05 s add turnaround time: 11.05 s + 0.25 s = 11.3 s note that when the prescaler is used, a 10 s settling/acquisition ti me is recommended for increased accuracy. smartgen automatically comp utes values for the stc, clock divider setting (tvc), and adc clock period. the goal of sm artgen is to meet th e minimum sample time requirement with the highest po ssible adc clock frequency, whic h implies a low tvc value and high stc value. sample rate 1 11.025 s 0.125 s + ----------------------------------------------------- - ns 89.68 ksps == sample rate 1 11.05 s 0.25 s + ----------------------------------------------- ns 88.49 ksps ==
designing the fusion analog system v1.0 8-7 sample sequencing overview as described in the fusion family of mi xed-signal flash fpgas datasheet and illustrated in figure 8-4 , there is one adc in the analog block (ab) and up to ten analog quads, with three analog inputs each: av, ac, and at. the analog input to adc is selected through a mux architecture controlled by the chnumber select input. fpga fabr ic access to th e chnumber input of the ab provides users the flexibility to de fine custom sample sequencing among the analog quads. the flexibility of sample sequenci ng in the fusion ab architecture enables conditional sequences and control of the sampling rate of each channe l. for example, the designer can sample critical inputs (requiring a higher sampling rate) more often than non-critical inputs. it is also feasible for the design to change sampling sequence and/or rate of analog inputs du ring operation whenever required. figure 8-4 ? analog block adc and mux architecture av0 ac0 ag0 at0 av1 ac1 ag1 at1 av2 ac2 ag2 at2 av3 ac3 ag3 at3 av4 ac4 ag4 at4 av5 ac5 ag5 at5 av6 ac6 ag6 at6 av7 ac7 ag7 at7 av8 ac8 ag8 at8 av9 ac9 ag9 at9 analog quad 0 analog quad 1 analog quad 2 analog quad 3 analog quad 4 analog quad 5 analog quad 6 analog quad 7 analog quad 8 analog quad 9 analog mux (32 to 1) temperature monitor internal diode chnnumber[4:0] digital output to fpga adc 12 these are hardwired connections within the analog quad. 31 0 1 v cc (1.5 v) pads atreturn01 atreturn23 atreturn45 atreturn67 atreturn89
designing the fusi on analog system 8-8 v1.0 there is no automatic internal sequen cing in the archit ecture shown in figure 8-4 on page 8-7 . therefore, the chnumber input of the mux must be cont rolled and defined by the user?s design at all points throughout its impl ementation (e.g., smartgen ip, co reai (analog interface) register space, and custom logic). sample rate and sample sequence calculation as the fusion adc can be shared among different ch annels (32 channels in all), the sample rate can be calculated based on the system samplin g rate or per-channel sampling rate ( eq 8-4 and eq 8-5 ). eq 8-4 eq 8-5 example: equal weight an d equal conversion time each channel has a co nversion time of 2 s, as shown in figure 8-5 . in this case, there are 10 samples, which take a total of 20 s. thus, the total system sampling rate is 10 / (20 s) = 500 ksps. channel 1 sampling rate: (2 / 10) 500 ksps = 100 ksps channel 2 sampling rate: (2 / 10) 500 ksps = 100 ksps channel 3 sampling rate: (2 / 10) 500 ksps = 100 ksps channel 4 sampling rate: (2 / 10) 500 ksps = 100 ksps channel 5 sampling rate: (2 / 10) 500 ksps = 100 ksps example: unequal weight and equal conversion time in this example, the channels are not equally weighted in the sampling sequences shown in figure 8-6 . in this case, there are 10 samples that take a tota l of 20 s, giving a tota l system sampling rate of 500 ksps (as above). however, the individu al channel sampling rates are different. channel 1 sampling rate: (5 / 10) 500 ksps = 250 ksps channel 2 sampling rate: (1 / 10) 500 ksps = 50 ksps channel 3 sampling rate: (1 / 10) 500 ksps = 50 ksps channel 4 sampling rate: (1 / 10) 500 ksps = 50 ksps channel 5 sampling rate: (2 / 10) 500 ksps = 100 ksps figure 8-5 ? equal weight and equal conversion time figure 8-6 ? unequal weight and eq ual conversion time system sampling rate total # of samples total (conversion + turnar ound) time of all samples ------------------------------------------------------------------------------------------------------------------------------- ----- - = channel sampling rate total # of samples for a channel total # all samples ----------------------------------------------------------------------------------- - system sampling rate = 2 4 6 8 10 12 14 16 18 20 s 0 s ch 2 ch 3 ch 5 ch 2 ch 4 ch 1 ch 4 ch 1 ch 3 ch 5 2 4 6 8 10 12 14 16 18 20 s 0 s ch 1 ch3 ch 1 ch 5 ch 1 ch 1 ch 2 ch 4 ch 5 ch 1
designing the fusion analog system v1.0 8-9 example: unequal weight and unequal conversion time in this example, channels have different conver sion times and are not eq ually weighted in the sampling sequence, as shown in figure 8-7 . in this case, there are 12 samples in 20 s, gi ving a total system sampling rate of 600 ksps. channel 1 sampling rate: (7 / 12) 600 ksps = 349 ksps channel 2 sampling rate: (2 / 12) 600 ksps = 99.6 ksps channel 3 sampling rate: (1 / 12) 600 ksps = 49.8 ksps channel 4 sampling rate: (1 / 12) 600 ksps = 49.8 ksps channel 5 sampling rate: (1 / 12) 600 ksps = 49.8 ksps acquisition time calculation acquisition time (t_sample) specifies how long an analog input signal ha s to charge the internal capacitor array. figure 8-8 shows a simplified internal input sampling mechanism of a sar adc. the internal impedance (z inad ), external source resistance (r source ), and sample capacitor (c inad ) form a simple rc network. as a result, the accuracy of the adc can be affected if the adc is given insufficient time to charge the ca pacitor. to resolve this problem, the user can either reduce the source resistance or increase the sa mpling time by changing the acquisition time in the design or in the smartgen gui. using the adc with direct input when the fusion adc is driven by a direct inpu t (the prescaler is not used), actel recommends driving the analog input pin with low source impedance (r source ) for fast acquis ition time. high source impedance (r source ) is acceptable, but the acquisition time will be increased. figure 8-7 ? unequal weight and unequal conversion time 2 4 6 8 10 12 14 16 18 20 s 0 s ch 2 ch3 ch 4 ch 5 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 2 ch 1 figure 8-8 ? simplified sample and hold circuitry sample and hold z inad c inad r source
designing the fusi on analog system 8-10 v1.0 eq 8-6 can be used to approximate the acquisition ti me that can be entered in smartgen. in this equation, 5 is used as an example to approximate th e acquisition time, but it is application- dependent. based on the acquisition time, smartgen will provide the sample rate calculation using eq 8-4 on page 8-8 and eq 8-5 on page 8-8 . if the actual acquisition time is higher than the software setting, the settling time error can affect the accuracy of the adc, because the sampling capacitor is only partially charged within the give n sampling cycle, referred to as the acquisition period (t_sample). acquisition time (t_sample) ~ 5 (r source + z inad ) c inad eq 8-6 users can calculate the minimum actual acquisi tion time by using eq 8-7 : v out = v in (1 ? e ?t/rc ) eq 8-7 for 0.5 lsb gain error, v out should be replaced with (v in ? 0.5 lsb value): (v in ? 0.5 lsb value) = v in (1 ? e ?t/rc ) eq 8-8 where v in is the adc reference voltage (v refadc ). solving eq 8-8 , eq 8-9 where r = z inad + r source and c = c inad . examples are given in table 8-2 and table 8-3 . using the adc with built-in prescaler when using the prescaler, the user can achi eve the highest sampling rate by providing a recommended 10 s acquisition time, which is the maximum settling time when prescaler is used with the adc. using smartgen, users can set the acquisition time in th e software gui so the corresponding sampling rate will be calculated automatically. use rs with other de sign flows must ensure the control logic is allocating sufficient time for the adc to perform a conversion that satisfies the accuracy requirement. table 8-2 ? adc parameters ? v in = 2.56 v, r = 4000 ? (r source ~ 0 ? ), and c = 18 pf resolution (bits) lsb value (mv) min. sample/hold time for 0.5 lsb (s) 8 10 0.449 10 2.5 0.549 12 0.625 0.649 table 8-3 ? adc parameters ? v in = 3.3 v, r = 4000 ? (r source ~ 0 ? ), and c = 18 pf resolution (bits) lsb value (mv) min. sample/hold time for 0.5 lsb (s) 8 12.891 0.449 10 3.223 0.549 12 0.806 0.649 trcln v in 0.5 lsb value --------------------------------------- ?? ?? =
designing the fusion analog system v1.0 8-11 prescaler selection as mentioned in the "analog-to-digital converter ba ckground" section on page 8-1 , the analog input signals to the adc must be mapped to the adc reference voltage range. if the maximum value of an analog input voltag e is greater than or less than the adc reference voltage, the embedded prescaler feature can be used to amplif y or attenuate the input voltage signal to match the input voltage range of the adc. in smartgen design flow s, designers can enter the expected voltage range, and the software will configure the ap propriate factors. if a design flow other than smartgen is used, refer to table 2-46, ?prescaler control truth table,? in the fusion family of mixed-signal flash fpgas datasheet to select the appropriate scaling factor. analog configuration mux (acm) the fpga core uses the analog configuration mux to interface with the analog quad configuration settings and real-time counter (rtc ) system. to use the analog quads, appropriate configuration settings (scaling factor, polarity, pres caler usage, etc.) must be set before using these features. each analog quad has on e byte of register space to store its configuration settings, and users can access these registers via the acm, which is part of the analog block macro. similarly, the rtc counter register and match register can be accessed by the fpga core via the acm. table 8-4 shows the acm ports for the fpga core to inte rface with the analog quads and rtc system. in a smartgen design flow, the configuratio n setting in the gui is translated into the corresponding configuration bits for the analog qu ads and rtc registers. the configuration settings data is stored in the embedded flash memo ry, and when the device is powered up or reset, the smartgen ip loads the configuration settin gs from the embedded flash memory into the corresponding registers. the analog quads and rtc systems are functional after this initialization stage; init_done (active high) from the smartgen ip indicates the completion of the initialization stage. with a different design flow, the analog quad s and rtc registers must be configured. the configuration data can be stored in the embedded flashrom, flash memory, or core logic tiles. table 8-4 ? acm interface port name type description acmwdata[7:0] input writing data from the fpga core to the analog system acmrdata[7:0] output reading the data from the analog syste m to the fpga core acmaddress[7:0] input address acmwen input 0 for reading 1 for writing acmclk input clock input from the fpga (maximum frequency = 10 mhz) acmreset input active-low asynchronous reset
designing the fusi on analog system 8-12 v1.0 figure 8-9 and figure 8-10 show the acm read and write operations. refer to table 2-44, ?analog configuration multiplexer (acm) timing,? in the fusion family of mixed-signal flash fpgas datasheet for the corresponding timing parameters. figure 8-11 shows the block diagram of the analog bloc k. the figure shows how the configuration byte (b0?4) is connected to each block and how each block is interfaced wi th the user-accessible analog block macro and the adc. note that the soft ip inte rface to the ab manages the configuration, making connecti vity transparent to the user. figure 8-9 ? acm read waveforms figure 8-10 ? acm write waveforms acmclk acmaddress acmrdata a0 a1 t mpwclkacm t clkqacm rd0 rd1 acmclk acmaddress acmwdata a0 a1 t sudacm t hdacm d0 d1 acmwen t suaacm t haacm t heacm t sueacm figure 8-11 ? analog block 0 2 ac prescaler in out polarity gain 0?2 pwrdn pwrdn g digital input buffer diff amp in + out polarity polarity pwrdn in ? cnvstrb 1 0 2 at prescaler in out gain 0?2 g digital input buffer diff amp in ? out pwrdn in + cnvstrb 1 at rtn 0 1 av prescaler in out polarity gain 0?2 pwrdn g digital input buffer voltage monitor block current monitor block temperature monitor block polarity 0 2 ag out on/off 1 gate driver block 3 polarity drive chip temp monitor note: x = 0 to 9 dv_en dvout b3[5] b3[7] b3[6] b0[3] amux_in[0] b1[2:0] b0[5] b1[3] amux_in[1] b3[2:0] b1[4] cm_str amux_in[2] b2[7] gdonx b3[3] b3[4] b2[6] b2[0] dv_en dvout b1[5] b1[7] b1[6] b2[3:2] b0[4] b0[7] dv_en dvout b0[6] b0[2:0]
designing the fusion analog system v1.0 8-13 refer to the analog quad acm byte assignment table in the fusion family of mixed-signal flash fpgas datasheet for the explanation of each bit se tting and its corresponding configurations. refer to the acm address decode table for analog quad table in the fusion family of mixed- signal flash fpgas datasheet for the corresponding addr ess for each analog quad and rtc register. part number and revision date part number 51700092-002-0 revised november 2007

v1.0 9-1 9 ? fusion design solutions and methodologies with a rich mixture of analog and digital featur es, coupled with the abil ity to build mixed-signal designs either in hdl or with a processor, the actel fusion ? mixed-signal fpga offers designers the ultimate in flexibility. however, with product flexibility comes design complexity. actel offers several design solutions that make th e design process simple for all users. hdl design with analog system soft ip the analog system soft ip design flow is an ip-based desi gn method for hdl designs, which establishes a backbone to interconnect the fusi on fpga fabric, the analog system, the embedded flash memory block, and other peripherals. figure 9-1 on page 9-2 provides an overview of the design flow. the analog system soft ip design flow offers a number of advantages to users. all the required soft ip cores are free. sample sequence control, av eraging/filtering an d threshold response functions are built-in and specified by an intuitive gui in actel libero ? integrated design environment (ide). ip configuration and connectivi ty are tightly integrated into smartdesign and libero ide, enabling users to ra pidly and seamlessly implement th e complete analog and peripheral interface. users do not have to write up their own code to cont rol the analog and flash memory systems. users have several options for integrating the anal og system into their design, but at the heart of it all are the analog system builder and flash me mory system builder from libero ide. the analog system builder creates vhdl or verilog source code and the configuration file to be stored in the embedded flash memory. users can invoke the an alog system builder an d flash memory system builder, along with the generators for other fusion and ip cores, from the cores catalog window in libero ide, or modify an existing configuratio n from within smartdesig n. other fusion-specific core generators in libero ide include the no-glitch mux (ngmux), rc oscillator, crystal oscillator, sram, fifo, flashrom, i/os, and voltage regulator power supply monitor (vrpsm). smartdesign is a unique block-diagram-based design entry tool introduced in libero ide v8.0 that gives users the capability to visu ally create block-level system designs and automatically abstract the result into synthesis-ready so urce code. designers can build thei r entire design in smartdesign. for fusion designs, smartdesign identifies required connections between bl ocks in the analog system and automatically stitches them together. smartd esign also provides a connectivity grid, which enables users to graphically perform port mapping across all th e blocks in the design. if the analog system is used in smartdesign, smartdes ign will audit the conn ections and any updates made to the analog system. for example, if the an alog system is regenerated, the tool will remind the user that the nvm client must be regenerated. if users do not use smartdesign, they can gene rate the analog system and required embedded flash memory clients from the li bero ide cores catalog window. th ey must then manually stitch the fusion blocks together with the user hdl code. note: any time the analog system is regenerated, the analog system client for the embedded flash memory must also be regenerated from the fl ash memory system builder in libero ide. after building the hdl design, user s should take their design thro ugh the rest of the fpga design flow?synthesis, post-synthesis si mulation, and designer functions including compile, place-and- route, package pin assignment, and static timi ng analysis?and then perform back-annotated simulation. once the desi gn is finalized and timing has been verified, the design is ready to be programmed into the fpga using the fl ashpro programmer and software. the "design state management in smartdesign" section on page 9-3 and the "changing memory content" section on page 9-3 discuss how to handle design iterat ions for fusion within libero ide. flashpoint provides the interface to generate pr ogramming files for fusion devices. the flashrom, fusion embedded flash memory, and security settings can be reset and reprogrammed using flashpoint, which is integrated into both designer and the flashpro software.
fusion design solutions and methodologies 9-2 v1.0 with flashpoint integrated with flashpro, users can modify the contents of the embedded flash memory or the flashrom without us ing designer or libero ide. by default, designer?s program file generation from flashpoint gene rates a programming database file (pdb) file instead of a stapl file. a pdb file is required to enable users to make modifications usin g the flashpro software. when users need to change the programming sett ings in flashpro, they can simply click the configure pdb button. all modifications are stored in the pdb file, and flashpro uses the information to program the device with the appropriat e settings. libero id e/designer does not have to be open to make these mo difications. figure 9-1 ? analog system soft ip design flow libero: create project for fusion is there an as in the design? libero analog system builder: generate as as = analog system efm = embedded flash memory from = user flashrom flash memory system builder: generate efm with analog client smartdesign or hdl: create top level and connect all macros waveformer lite: generate analog testbench file run rtl simulation synthesis / post-synthesis simulation flash memory system builder: generate efm with non-analog client changes needed to analog system? yes designer: compile, place-and-route, pin mapping static timing analysis / back-annotated simulation designer: generate pdb programming file flashpoint: program device, from, and efm is there an efm client in the design? no no yes yes no changes needed to efm or from? yes
fusion design solutions and methodologies v1.0 9-3 design state management in smartdesign when any component with instances in a smartdes ign design is changed, all instances of that component detect the change. if th e change only affects the memory content, user changes do not affect the component's behavior or port interface, and the user ?s smartdesign design does not need to be updated. if the change affects th e behavior of the instant iated component but the change does not affect the compon ent's port interface, the design must be resynthesized, but the smartdesign design does not need to be updated. if the port interface of the instantiated componen t is changed, the user must reconcile the new definition for all instances of the component and resolve any mismatches. if a port is deleted, smartdesign will remove that port and clear al l the connections to th at port when the user reconciles all instances. if a new port is added to the component, instance s of that component will contain the new port when the user reconciles all instances. the affe cted instances are identified in the smartdesign design in the conn ectivity grid and the canvas wi th an exclamatio n point. right- click an instance and choose update with latest component . note: for hdl modules instantiated in a smartdesi gn design, if the modification causes syntax errors, smartdesign does not de tect the port changes. the changes will be recognized when the syntax errors are resolved. changing memory content for certain cores such as analog system builder and flash memory, it is possible to change the configuration such that only the memory content used for prog ramming is altered. in this case, libero ide only invalidates the programming f ile, but synthesis, compile, and place-and-route results remain valid. when the user modifies the me mory content of a core?such as analog system builder or ram with initialization?that is used by a flash memory core, the flash memory core indicates that one of its dependent components has changed and that it needs to be regenerate d. this indication is shown in the design hierarchy or files tab. in these cases, libero ide indicates that the programming file is out of date, but synthesis and place-and-route remain valid. the user only needs to regenerate the prog ramming file in flashpoint. if any core is regenerated when the hdl file is not m odified, the libero ide project manager design state will not invalidate synthesis or place-an d-route results. for th ese scenarios, the new embedded nvm data file (efc file ) will be used to update the pr ogramming file wi thin libero ide, or can be imported into flashpro. so me specific cores are listed below: ? ram with initialization core ? the memory content can be modified without invalidating synthesis. ? analog system builder core ? the following can be modified without invalidating synthesis: ? existing flag settings: thre shold levels, assertion/deasse rtion counts, over/under type ? modifying sequence order or adding sequence operations ? changing acquisition times ? resistor value for the current monitor ? rtc time settings ? gate driver source current ? flash memory system builder core ? the fo llowing can be modified without invalidating synthesis: ? modifying memory file or memory content for clients ? jtag protection for initialization clients
fusion design solutions and methodologies 9-4 v1.0 microprocessor/microcontroller design actel offers several microprocessor and microcontro ller solutions for custom ers, all of which are tightly integrated with actel li bero ide, optimized for actel fp ga architecture, and supplied with a complete toolset for code comp ile and debug. here is a summary of actel?s available solutions: ? cortex-m1: the first arm ? processor developed specifically for implementation in fpgas. cortex-m1 is available without license fees or royalties for use in ac tel m1 proasic3/e and fusion devices. ? coremp7: coremp7 is a soft ip version of the arm7tdmi-s? that is optimized for use in actel m7 fusion and proasic3/e flash-based fpgas. coremp7 is available with no license fees or royalties?bringing arm7? to the masses. ? core8051(s): both core8051 and core8051s are code-c ompatible with the industry-standard 8051 architecture, allowing designers to utiliz e existing code while shortening design time. further, both are single-cycle execution architectures, executing one instruction per clock cycle. core8051 has the traditi onal sfr memory space and includes the standard 8051 peripherals, and core8051s re places the tradition al sfr interface with an advanced peripheral bus (apb) interface, allowing the customization of the 8051 peripheral set. ? coreabc: coreabc (amba [advanced microcontroller bus architecture] bus controller) is the smallest and first rtl-programmable soft mi crocontroller available for fpgas. the free controller resides on the apb, can be implemented in as few as 241 tiles, and can be used in the smallest actel devices. ? leon3: leon3 is a 32-bit processor based on the sparc v8 architecture, optimized for use in actel fpgas. a fault-tolerant ve rsion of the leon3 processor is available for system-critical applications. ? amba: actel supplies a full rang e of subsystem ip cores: amba bus interfaces, memory controllers, timers, and others. the subsystem ip connects to the proces sor via the amba bus and is available for free in coreconsole. for the above arm-based processors and coreab c, actel offers coreai (analog interface) to interface with the analog system. coreai allows for simple con trol of the anal og peripherals within fusion. control can be implemented with an internal or external microprocessor or microcontroller, or with user-created custom logi c within the fpga fabr ic. the amba apb slave interface is used as the primary contro l mechanism within co reai, as shown in figure 9-2 . coreai instantiates the analog block (ab) macro, which includes the analog configuration mux (acm) interface, analog quads, and real-time counter (rtc). several aspects of coreai can be configured using top-level parameters (verilog) or generics (vhdl). for a detailed description of the parameters/generics, refer to the coreai handbook . figure 9-2 ? processor system using coreai processor uart gpio interrupt controller static memory controller watchdog ahb2apb bridge ahb apb timers coreai flash memory ab analog i/o ab is logically but not physically implemented inside of coreai. fusion hardware rtl ip components
fusion design solutions and methodologies v1.0 9-5 tools overview actel offers fpga development tools for microp rocessor and microcontro llers, and a complete development and debug environment for actel?s microproce ssor solutions ( figure 9-3 ). with actel solutions, users ca n shorten development time using coreco nsole ip deployment platform (idp), which includes a graphical user interface and a block stitcher to simplify the assembly of ip cores for embedded applications in fpgas. this tool integr ates with actel libero id e, which includes actel designer software for pl ace-and-route. to enable cortex-m 1 and coremp7 users to debug the programs they write fo r their processors, there is option al hardware with in the core that implements jtag debug features, such as breakpoi nts. various third-party tools, like the arm realview ? developer kit and actel?s own free softconsole, provide tools for building, debugging, and managing software development projects that run on the proc essor. the tool kit, available from actel, contains an optimized c compiler, debugger, asse mbler, and instruct ion set simulator. for an overview of the proces sor design flow, refer to the actel processor desi gn flow webcast . with a processor built into the fusion fpga fabric , the fusion embedded flash memory can be used for program storage, which can in tu rn be executed out of internal or external memory. implement the appropriate ip in coreconsole for an internal or external ram interface. use the data storage client from the flash memory system builder in li bero ide to create a parti tion in the flash memory and flashpoint to load program code during device programming. for coreabc-based designs, users ca n choose either a soft or hard implementation of the core. in the soft implementation, coreabc operates on a ssembly instruction code residing in flash memory and executed either dire ctly out of flash or from local sram. in the hard implementation, coreabc becomes a vhdl- or verilog-coded state mach ine derived from assemb ly code. for either implementation, actel recommends that users conf igure and generate the core using coreconsole. with coreconsole, users can easi ly connect the required periph erals and build the subsystem including coreai on the apb. once the coreco nsole component including coreabc and coreai is generated, users should follow a standard hdl fp ga design flow. note th at if coreabc soft mode is used, users must create an initialization clie nt for the ram from the embedded flash memory, using the flash memory system builder in libero ide. the initialization client can be created by loading the memory contents file that is automatically created by coreconsole during generation of coreabc. for more information on building a design with coreabc, refer to the fusion starter kit user?s guide and tutorial . figure 9-3 ? fusion design flow design start stitch system together configure ip cores develop or acquire user ip actel ip vault determine hw and sw requirements fail circuit synthesis behavioral simulation pass timing-driven simulation compile layout back-annotate encrypted pdb/stapl hw design edit sub-block ip and testbench pass sw simulation and debug develop/edit sw program sw design fail fail program fpga device hw sw debug and coverification program sw to fpga device pass design complete development coreconsole softconsole and realview board libero ide c compile microprocessor flow
fusion design solutions and methodologies 9-6 v1.0 part number and revision date part number 51700092-004-0 revised november 2007
v1.0 10-1 10 ? interfacing with the fusion analog system: processor/microcontroller interface objective this chapter describes th e applications in which a microprocessor or microc ontroller is the core of the design that cont rols the fusion analog bl ock (ab). the design?s micr oprocessor/microcontroller interacts with coreai (analog interface) as the analog block interface and does not access the ab macro directly. the design in this chapter uses coreai within actel coreconsol e ip deployment platform (idp). however, the contents and usag e of this chapter are not limited to coreconsole users. coreai introduction coreai is actel?s analog inte rface core designed to facilit ate access to the actel fusion ? analog block (ab) by a micropro cessor/microcontroller. coreai provid es register/address space that can be written to or read from by a microprocessor/microcontroller to configure, control, and interact with the analog block. for more information on coreai specificat ions and usage, refer to the coreai handbook . this section describes ho w the microprocessor/micro controller accesses and configures coreai to implement voltage, current, and temperature monitoring, as well as gate- driving applications. coreai settings in coreconsole coreai can be configured by writing the desired values into all required coreai address spaces. coreai?s parameters and generics, used by the co re?s source code, can be set within coreconsole. refer to the coreai parameter/ge neric descriptions table in the coreai handbook for a complete list of parameters. analog configuration mux (acm) cl ocking, interrupt, and internal temperature monitor configuration the first step of coreai configur ation in coreconsole is the ac m clock divider setting, shown in figure 10-1 . the acm clock (acmclk) maximum frequency is limited to 10 mhz, so the user must select a setting that will ensure th at acmclk is not greater than 10 mhz. figure 10-1 ? acm clock configuration in coreconsole
interfacing with the fusion analog system: processor/ microcontroller interface 10-2 v1.0 in the acm clock divider setting, select th e dividing factor to be used based on eq 10-1 : f acmclk = f pclk / n eq 10-1 where n = 2, 4, 8, or 16; f acmclk is the frequency of the acmclk; and f pclk is the frequency of pclk, the peripheral bus clock usually conn ected to the design main system clock. the pclk frequency is essentially the speed of the advanced peripheral bus (apb) and the clock speed of the design?s mi croprocessor/microcontroll er. for example, if the system clock speed is designed to be more than 20 mh z, the acm clock divider factor cannot be set to two, since it correlates to an ac m clock frequency of more than 10 mhz. analog quad configuration the main part of coreai configuration in coreconsole is dedicated to the analog quad settings ( figure 10-2 ). each quad consists of fo ur settings?av, ac, at, and ag ?and represents the fusion device architecture. the coreconsole gui settings faci litate the configuration of the co re?s internal register space (initialization). the settings in coreconsole set the parameters and generics of the coreai source code and create information to be used in the analog block?s initialization. coreconsole will export all files used for initialization to the software export folder. acm_defines.h contains definitions for the values used to conf igure the acm (defined per user setti ngs in coreconsole) in the analog block of a fusion device. note: for coreabc (amba [advanced microcontroller bus architecture] bus controller) users, if the apbwrt acm command is enabled, a verilog or vhdl file will be generated. this file contains a lookup table that will configure the ac m with user-specified settings. initialization files and their usage are discussed in further detail in "analog configuration mux initialization" on page 10-6 . the user can also configure the acm bus without the coreconsole-generated initialization files. the following describes the anal og quad software gui settings and their effects on coreai parameters/generics: ? avn input: the av configuration drop-down menu lists all supported analog input voltage ranges and polarities for acm initialization purposes. the main categories for av configuration are as follows: ? analog voltage input enabled/disabled : if disabled, the specified analog av input of the analog block will be tied low internally and will not be listed as an accessible coreai port in the code. ? av input used as digital input : if used as a digital input, the corresponding davout output port will be listed as a top-level port of the core, to be connected to the digital input of your design. ? acn input: the ac configuration drop-down menu supports all analog input voltage ranges and polarities. the basic settings are as follows: ? ac pin disabled : if disabled, the specified analog ac input of the analog block will be tied low internally and will not be listed as an accessible coreai port in the code. ? ac pin used as current monitor : if the ac pin is set to be used as a current monitor or voltage monitor, the cf g_acx bits will be set as described in the coreai handbook . in current monitori ng applications, sampling the current from an an alog quad (configured figure 10-2 ? analog quad configuration in coreconsole
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-3 as current monitor) is contro lled by the corresponding cm stb input. coreconsole gives the option to configure the cmstb input of a current monitoring quad to be either register-driven and controlled by the software, or hardware-driven. if configured to be hardware-driven, an hd_cmstb port is added to the coreai input pins and should be controlled by the user logic in the fpga fabric. ? ac pin used as voltage monitor : if the ac pin is set to be used as a voltage monitor, the cfg_acx bits will be set as described in the coreai handbook . ? ac input used as digital input : if used as a digital input, the corresponding dacout output port will be listed as a top-level port of the core, to be connected to the digital input of your design. ? atn input: in the at configuration drop-d own menu, the following parameters can be set: ? at input enabled as temperature monitor or completely disabled : if disabled, the specified analog at input of the analog block will be tied low internally and will not be listed as an accessible coreai port in the code. ? at input used as digital input : if used as a digital input, the corresponding datout output port will be listed as a top-level port of coreai, to be connected the digital input of your design. in temperature monito ring applications, sa mpling temperature fr om the at input pin (configured as temperature monitor) is co ntrolled by the corresponding tmstb input. coreconsole gives the option to configure the tmstb input of a temperature monitoring quad to be either a software-dr iven or a hardware-driven regist er space. if configured to be hardware-driven, an hd_tmstb port is added to the coreai input pins. the hd_tmstb port must be controlled by the user?s logic in the fpga fa bric. a similar implem entation is used in the coreai module for intern al temperature monitoring. ? agn output: in the ag configuration drop-down menu, the following parameters can be set: ? ag output disabled : if disabled, the specified ag ou tput will be unused and omitted from the top-level coreai ports . the corresponding gdon input of the analog block will be tied low internal to the core. ? ag output enabled and driven by softwa re-controlled register (software-driven) : if the ag output is enabled and driven by software , the ag output pin will turn on or off (consequently turning the extern al pmos or nmos on and off) when 1 or 0 is written to the desired location of the analog-to- digital converter (adc) control registers. ? ag output enabled and driven by fp ga core logic (hardware-driven) : if the ag output is enabled and driven by hardware, the corresponding hd_gdonx input of coreai will be added to the top-level ports of the core, an d the ag output pin wi ll follow the logic that drives that hd_gdon input of coreai. in th is case, the appropriate gdon bit in adc control register 5 will be set to 1 (enabl ed) during initialization of the coreai. adc settings the main adc settings can be configured in coreconsole: ?mode ?tvc ? stc (sample time control?used to define sampling time of adc: {2 to 257} adc clock period) ? adcreset ? adcstart ?power down ? varef selection ? adc channel number control the purpose and specific usage of each setting are described in the analog-to-digital converter section of designing the fusion analog system and in the coreai handbook . these settings can be
interfacing with the fusion analog system: processor/ microcontroller interface 10-4 v1.0 controlled in two manners: software- or hardware -driven. when software -driven, these settings are controlled by an apb regist er/address space in coreai ac cording to the address mapping described in the coreai handbook . when hardware driven, these se ttings are controlled by direct inputs (e.g., hd_tvc) to the core and need to be managed accordingly by the user design in the fpga fabric or tied to specific values. when the analog block (adcstart) and adc (adcreset) are configured as software-driven, the adcstart and adcreset registers are self-clearing, and adcstart or adcreset can be initiated by writing 1 to the specific regi ster address. these registers will clear themselves and be ready for the next adcstart or adcreset request with no n eed for the user to set these registers back to 0 prior to the next request. th e self-clearing functionality do es not exist when adcstart or adcreset are hardware-driven, and these inputs must be reset to 0 before issuing the next request. clocking scheme there are four main clock domains in a basic mixed- signal fusion design: th e system clock (sysclk), acmclk, adcclk, and the initialization clock. any basic, functional mixed-signal fusion design that uses analog quads needs to interface with the acm and adc. besides the fr equency requirements of acmc lk and adcclk, there will be areas in which data is transfer red from one clock domain to another between sysclk and acmclk or adcclk. sysclk the system clock (sysclk) is the microprocessor clock. when coreabc (or any other processor/contro ller) and coreai are used together, sysclk and pclk (the apb interface clock) are normally connected together as the overall system clock. acmclk acmclk is the clock input to th e acm used for configuration/in itialization of the analog quads. the acmclk frequency is li mited to 10 mhz. coreai uses an inte rnal clock divider that divides the input sysclk by a user-defined factor and drives it to the acmclk input of the analog block. when coreai is used as an apb peripheral to the micr oprocessor, acmclk will be seamless if the pclk / n factor is set appropriately in the coreai settings to limit the acmclk frequency to below 10 mhz. adcclk adcclk is the clock input to the analog block used by the adc. adcclk is used for internal adc operations and serves as a reference for determini ng the conversion time of the adc (through the stc setting). the adcclk maximum frequency is 10 mhz. an intern al clock divider inside the analog block is used to divide the input system clock (sysclk) and generate the adcclk input to the adc. the internal divider valu e is configurable through the 8- bit tvc register, where tvc can be set from 0 to 255 ( eq 10-2 ): adcclk = sysclk / (4 (1 + tvc)) eq 10-2 setting tvc to 0 sets the adcclk frequency to the sysclk frequency divided by four, and the adcclk-to-sysclk division ratio in creases in steps of four as the tvc value increases. this is important if the design requires adcclk to run at specific speed to ma intain a certain sampling rate. for example, if the adc is required to run at 10 mhz, the sysclk in put to the analog block should be 40 mhz (tvc = 0), 80 mhz (tvc = 1), 12 0 mhz (tvc = 2), etc. if a required sysclk frequency does not result in the dete rmined adcclk frequency (governed by eq 10-2 ), sysclk can be fed to the fusion cc c to generate an auxiliary sysclk si gnal with the desired frequency. this auxiliary sysclk signal can then drive the analog block. use eq 10-2 and appropriate tvc settings
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-5 to determine the appropriate frequency of the au xiliary sysclk that wi ll generate the desired adcclk frequency. initialization clock typically in microprocessor-based applications, the processor?s program code is stored in a nonvolatile memory, used during power-up boots. if the microprocessor program code is stored in the fusion embedded flash memory, clocking the embedded flash memory is an important part of the design?s clocking scheme. if the embedded flash memory is used to store the processor?s program code, there are two general option s for the processor to access the code: ? accessing the embedded flash memory directly. the performance of sysclk is limited by the speed of the embedded flash memory. in this scheme the embedded flash memory clock and sysclk are driven by the same signal. ? initializing embedded sram blocks with the contents of the embedd ed flash memory and running the processor?s prog ram from sram. the contents of the sram should be initialized by the embedded flash memory (power-up initialization). the memory initialization clients can be created using actel libero ? integrated design environment (ide). the dual-port sram ha s one port connected to the embedded flash memory and one port connected to the mi croprocessor. the embedded flash memory (the initialization part of the design) is clocked separately from the operational part of the design. the initialization clock (init_clk) input of the initialization client is limited to 10 mhz maximum frequency. therefore, if the sysclk frequency is more than 10 mhz, init_clk should be driven separately. the fusion ccc can be used to generate init_clk with a frequency less than 10 mhz. when coreabc is the system? s microcontroller, the instruction program srams are instantiated within the co reabc module exported from co reconsole, and the clocking scheme, shown in figure 10-3 , can be used to ensure that the initialization of the sram from flash memory is performed by a clock of less than 10 mhz. once the initialization is completed, init_done will assert (active high ), and the design runs from the high-speed system clock. the clocking archit ecture shown in figure 10-3 uses an ngmux block as the multiplexer to switch between the hi gh- and low-speed clocks. the us age of the ngmux macro is to prevent glitches on the clock output of the mux when switching between the two clock inputs. refer to the no-glitch multip lexer (ngmux) section of fusion clock resources for more information about the ngmux. figure 10-3 ? clocking scheme when initializing sram with coreabc instructions ngmux coreabc flash memory initialization client initialization ports sysclk init_clk init_done high speed clock low speed clock (<10 mhz)
interfacing with the fusion analog system: processor/ microcontroller interface 10-6 v1.0 analog configuration mux initialization the acm is a register space in th e analog block used to configur e the analog quad s and the real- time counter (rtc) architecture with the user?s specification. since the configuration scheme is stored in registers, the acm need s to be initialized after each po wer-up. when using coreai as the interface to the analog block, the initialization of the acm should be done in two steps: 1. reset the acm register space to put un used analog quads into a known mode. 2. configure used analog quads (and rtc if us ed in the design) to desired specification. note: in addition to acm initialization, the adc need s to be calibrated after power-up for correct functionality; see "adc configuration and calibration" on page 10-9 . acm reset the acm registers can be reset by activating the active-high acmreset bit of the coreai register space. 1 when configuring coreai, this input is controlled by bit 0 of the acm control/status register. the acm can be reset by writing 1 to this bit. note that bit 0 of the acm control/status register is self-clearing: wh en written with 1, it will clear itself ; it does not need to be written with 0 to clear it. the acm control/status register is desi gned to be located at address 0x00 of the coreai internal register address map. acm initialization before a design enters the operational phase, the acm must be initialized with the desired configuration for the analog quads and/or rtc registers. when coreconsole generates all the necessary files for a microprocessor-based design, it also generates the file s to be used for acm initialization. there are two files, found in the softwareexport folder of the coreconsol e directory, that can be used for acm initialization: acm_defines.h and quads_acm_cfg.h . these two files contain information on initialization valu es for different acm address spaces per user entries in the coreai settings within coreconsole. thes e files can be referenced by th e general microprocessor program design to be used for initialization pr ior to entry into operational sections. the use of the above-mentioned files is optional. the user can manually write to the desired acm address space (from a mi croprocessor/microcontroller throug h the apb into co reai) with values that will initialize the targeted analog quads and/or rtc registers to the desired configuration. note: when writing to acm registers, the design should check the acm status register to ensure that the previous acm actions (write, read, or reset) are completed and that the acm is ready to be accessed again. 1. note that the acmreset input to the analog block is active low. to reset the acm in the coreai register space, the acm reset bit should be set to 1.
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-7 acm initialization specific to coreabc in addition to the initialization files and me thodology described above, if the apbwrt acm instruction is activated in the co reabc settings in coreconsole, co reconsole will export an hdl file named acmtable.vhd . this file can be found in the coreabc/rtl folder within the libero ide project. below is an example of an amctable.vhd file generated by coreconsole: -- *********************************************************************/ -- copyright 2007 actel corporation. all rights reserved. -- ip solutions group -- -- any use or redistribution in part or in whole must be handled in -- accordance with the actel license agreement and must be approved -- in advance in writing. -- -- file: instructions.vhd -- -- description: simple apb bus controller -- acm lookup table -- -- rev: 2.3 01mar07 ipb : production release -- -- notes: -- -- *********************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.support.all; entity acmtable is generic ( id : integer range 0 to 9; tm : integer range 0 to 99 ); port ( acmaddr : in std_logic_vector(7 downto 0); acmdata : out std_logic_vector(7 downto 0); acmdo : out std_logic ); end acmtable; architecture rtl of acmtable is begin -- this is dummy data used for testing process(acmaddr) variable addrint : integer range 0 to 255; begin addrint := conv_integer(acmaddr); acmdo <= '1'; if tm>0 then case addrint is when 0 to 99 => acmdata <= not acmaddr; when 101 to 255 => acmdata <= not acmaddr; when others => acmdata <= (others =>'-'); acmdo <= '0'; end case; end if; if tm=0 then -- ccdirective insert code
interfacing with the fusion analog system: processor/ microcontroller interface 10-8 v1.0 --acm lookup table for coreabc_00(id=0) with coreai_00 if id=0 then case addrint is when 1 => acmdata <= conv_std_logic_vector(16#83#, 8); when 2 => acmdata <= conv_std_logic_vector(16#82#, 8); when 5 => acmdata <= conv_std_logic_vector(16#82#, 8); when 7 => acmdata <= conv_std_logic_vector(16#80#, 8); when 9 => acmdata <= conv_std_logic_vector(16#83#, 8); when 11 => acmdata <= conv_std_logic_vector(16#80#, 8); when 13 => acmdata <= conv_std_logic_vector(16#82#, 8); when 15 => acmdata <= conv_std_logic_vector(16#80#, 8); when 17 => acmdata <= conv_std_logic_vector(16#82#, 8); when 19 => acmdata <= conv_std_logic_vector(16#80#, 8); when others => acmdata <= (others => '-'); acmdo <= '0'; end case; end if; end if; end process; end rtl; the last portion of the acmtable.vhd file defines the acm address spaces and the corresponding values used to initialize certain an alog quads to user specifications. if the user decides to perform all the initiali zation within the coreabc program code without utilizing any logic tiles from the fpga fabric, this last portion of the acmtable.vhd file can be used to determine the constant valu es in the acm write commands. the following example shows a sample of a coreabc program in wh ich location 1 of the acm addres s space is initialized with 83h, as defined in the above acmtable.vhd : // the following example assumes that coreai is in slot 0 of the apb and coreabc is the // bus master. refer to the table "coreai internal register address map" in the coreai // handbook for acm address mapping. write 1 (as acm address) to address 0x04 of the // coreai register space. apbwrt dat 0 0x04 1 // write 0x83 into acm data of coreai register space. this will result in writing 0x83 // into address 1 of acm address space. apbwrt dat 0 0x08 0x83 call $wait acm_write $wait_acm_write // read acm status register of coreai apbread 0 0x00 // check to see if bit 4 of acm status is cleared (write busy) bittst 4 // remain in the loop if bit 4 is not cleared yet jump ifnot zero $wait_acm_write return in the above example, the wait _acm_write function en sures that the write into acm register space is completed before proceeding to the next acm write instruction. the acmtable.vhd file represents a mux architecture wher e the output value is determined by the corresponding acm address, which acts as the select lines. if the user in tends to use the apbwrt acm command in the design, this mux can be implem ented in the fpga fabric (using tiles) and can be controlled by the coreabc prog ram to initialize acm registers. the following example sh ows the usage of the apbwrt acm in struction in coreabc to initialize the acm using acm table files: // the following example assumes that coreai is in slot 0 of the apb and coreabc is the // bus master. refer to the table "coreai internal register address map" in the coreai // handbook for acm address mapping. // only analog quads are being initialized in this example (no rtc). according to the // "acm address map for configuring analog quads and rtc" table in the coreai // handbook, the maximum acm size for configuration is assumed to be 28h.
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-9 $waitregprog call $waitacmready // write accumulator value in the acm address register of coreai apbwrt acc 0 0x04 // write the value from acmtable file into acm data register and // start an acm write apbwrt acm 0 0x08 // increment accumulator inc // compare accumulator to 0x28 cmp 0x28 jump ifnot zero $waitregprog $waitacmready push $waitacmready1 apbread 0 0x00 and 0x001c jump ifnot zero $waitacmready1 pop return in the above example, the coreabc accumulato r sweeps from address 0x 00 to 0x28 of the acm address space, and for ea ch of these addresses, the apbwrt acm command writes the appropriate values to the acm data register space for initialization of all analog quads. adc configuration and calibration acm initialization is only used to configur e the analog quads and/or rtc block. the adc configuration (mode, tvc, stc, etc.) is done th rough several inputs to the analog block. when configuring coreai in coreconsole, the adc settings can be set to be hardwired or register- controlled. when an adc setting is selected to be hardwired, ther e is no need to initialize that setting before the operational phase of the design . however, when the adc setting is selected to be software register-controlled, the settings are driven by a set of registers generally labeled as adc control registers in coreai. the most important configurat ion settings are in adc contro l registers 1 and 2. the only configuration setting in adc control register 2 is th e stc value. since this register also controls the adcstart and chnumber inputs to the adc, it will be written to during the operational phase. therefore, there is no need for an initialization operation on st c (when selected to be register- controlled) before entering the operational phase of the design. the desired settings need to be written to adc control register 1 to configure (tvc, pwrdown, varefsel, and mode). this only needs to happen once after each power-up, similar to acm initialization. adc will self-calibrate after device power-up an d after deactivation of adcreset, if adcreset is applied. when the adc is in calibra tion, bit 15 of the adc stat us register will be set to 1 to flag that the adc is busy calibrating itself. when the calibrati on is completed, this bit will be reset to 0. note: both adc calibration and acm initialization (see "acm initialization" on page 10-6 ) should be completed after power-up before the anal og block can properly function in the user?s design. it is common design practice to issue an adcreset request and check the status of bit 15 of adc status register before entering th e operation phase of th e design. when this bit is cleared, the design enters the operation phase.
interfacing with the fusion analog system: processor/ microcontroller interface 10-10 v1.0 in the following example, coreab c issues an adcreset request and then checks the status of the adc for completion of calibration: // in this example, adc_status and adc_ctrl1 represent the address of the adc status // register and adc control register 1, respectively, in the coreai address mapping. // it is also assumed that coreai is in slot 0 of the apb. // write 0x0040 into adc_ctrl1 register space of coreai apbwrt 0 adc_ctrl1 0x0040 $waitcalibrate // read adc_status register space of coreai apbread 0 adc_status and 0x8000 jump ifnot zero $waitcalibrate implementing voltage monitoring applications after completion of both acm initialization and adc calibration, the design enters the functional stage. this section describes ho w to implement a voltage monitoring application and provides design techniques to enhance sampling rate. th e voltage monitoring oper ations are as follows: ? selecting the anal og voltage input pi n to be monitored ? sampling the voltage on the selected pin ? translating the adc output result s into application-specific data ? implementing a digital low-pas s filter (or averaging) for voltage monitoring (optional) ? implementing a sampling sequence channel selection, adc sample , and conversion request voltage monitoring channel selection, requesting the adc to start a sample , and conversi on are all implemented through adc con trol register 2 in the coreai register space. this register also controls the stc value input to the adc. if, during the configuration of coreai in coreconsole, the stc input to the adc is set to be hardwired, bits 7? 0 of adc control register 2 will be considered as ?don?t care.? a request to the adc to sample and convert a specified channel is performed by activating adcstart. si nce adcstart and chnumber are both controlled by adc control register 2, these two signals will be fed to adc at the same time. note that the adcstart bit is self- clearing and will be cleared to 0 after the user writ es 1 to it to request an adc start. the following example shows a coreabc in struction in which the adc is requested to samp le and convert channel 2, with stc set to 4: // in this example, adc_ctrl2 represents the address of adc control register 2 in the // coreai address mapping. it is also assumed that coreai is in slot 0 of the apb. apbwrt 0 adc_ctrl2 0x2204
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-11 obtaining results from the adc output the adc status register in coreai contains stat us bits for the adc and the adc output results. immediately after issuing an adcstart request, the adc starts sampling the selected channel. during this period, the sample bit (bit 14) of the adc statu s register will be set high. when sampling is completed, the adc enters conversi on mode. in this mode, the sample bit will be cleared and the busy bit (bit 13) will be set high. when the conversion is completed, the busy bit will be cleared, the adc output will be placed on the results bits (bits 11 to 0), and the datavalid bit (bit 12) will be set high. in a typical voltage monitoring application, the only status bit that needs to be monitored after issuing an adcstart request is the datavalid bit. once datavalid is set high, the results bits are ready to be used by the microprocessor/microcontroller. depending on whet her the adc is configured to operate in 12-, 10-, or 8-bit mode, the adc output will be stored in results[11:0], results[11:2], or results[11:4], respectively. the following example shows a program routine in coreabc instructions that continuously checks the status of the datavalid pin after issuing an adcstart reques t. once datavalid is high, it will clear all bits of the read va lue except the adc results bits. // in this example, adc_status represents the address of adc status register in the // coreai address mapping. it is also assumed that coreai is in slot 0 of the apb and // that adc is configured in 8-bit mode. $adc_wait apbread 0 adc_status // check to see of bit 12 of adc_status register is set or not bittst 12 // remain in the loop if bit 12 is not set to 1 jump if zero $adc_wait and 0x0ff0 return instead of continuous reading of the adc_status register to check datavalid, adc_status can be fed to the microprocessor as an interrupt an d set high. then the micr oprocessor can read from the adc_status register to obtain result s. for more information, refer to the "adc configuration and calibration" section on page 10-9 . sample sequencing when the microprocessor receives the latest results from the adc status register, the microprocessor can issue another adcstart re quest on the same channel (to achieve more sampling on a particular channel) or a differen t channel. the desired sampling sequence can be achieved by writing the appropriate value to the chnumber bit of ad c control register 2 when issuing an adcstart request. refer to the sample sequen cing overview and sample rate and sample sequence calculation sections of the designing the fusi on analog system chapter for background information on sampling theory.
interfacing with the fusion analog system: processor/ microcontroller interface 10-12 v1.0 sample averaging in applications where the measured voltage line is expected to be noisy or where voltage variations are too fast for the application to respond to, it is recommended to take multiple samples from a voltage and use the computed average value of th e measured samples as representative of the sampled voltage. the user can choose the filtering factor by deciding how many samples need to be taken and averaged to acquire a single data point fo r processing. the higher the filtering factor, the lower the effective sampling rate will be. the following example shows a co reabc program in which a low- pass filter on the voltage measured from channel 2 is implemented with a f iltering factor of four. in other words, four samples are taken from the single channel (v1, v2, v3, and v4) and averaged: (v1 + v2 + v3 + v4) / 4. the ultimate result to be used in the rest of the program is sto red in address 0 of the internal memory. // in this example, it is assumed that coreai is in slot 0 of the apb. also, // adc_ctrl2 represents the adc control register 2 address in the coreai register // space. also, this example calls the $adc_wait function as described in // "obtaining results from the adc output" on page 10-11 . in the following example, // the 8-bit output of the adc is averaged using four samples, and the final average // value is stored in internal ram address 0 when the function is completed. // load z register (used as loop counter) with value 4 loadz dat 4 // write 0 to internal ram address 0 ramwrt 0 dat 0 $sample_filter // issue adc sample and conversion request apbwrt 0 adc_ctrl2 0x2204 call $adc_wait // divide by 4 and add to previous values shr0 shr0 // add content of internal ram address 0 to accumulator add ram 0 // write accumulator value to internal ram address 0 ramwrt 0 acc // decrement the z register value (loop counter) decz // check to see of z register (loop counter) is 0 or not jump ifnot zzero $sample_filter $done halt once the four samples are averaged, the samp led values are discarded. depending on the application and sampling sequence, the user can only discard the oldest sampled value and keep the most recent values to be used fo r averaging with the next sampled data. techniques to enhance design performance/throughput after each adcstart request to th e analog block, there is a period of time (duration of adc sample and conversion) during which the design?s microprocessor continuously checks the adc status register to indicate when the adc is done and data is ready to be fetched from results bits. the processing throughput of the design can improve significantly if the microprocessor/microcontroller can perform othe r necessary tasks while waiting for the adc to complete its cycle. ther e are two general methods to do th is, depending on the application?s requirements: ? after activating the adcstar t input to the analog block and requesting an adc sample and conversion to start, the de sign?s microprocessor can go on performing other tasks that do not need the results of the adc conversion. when th ese tasks are completed (or periodically), th e microprocessor can return and ch eck the adc status register for datavalid assertion. the drawback of this me thod is that the adc maximum sampling rate
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-13 capability may be compromised. in other words, the adc migh t complete conversion and sit idle prior to the microprocessor?s checking the adc status register. ? the required flag in the adc status register (datavalid) can be used as an interrupt input to the microprocessor. in this case, it can be assured that the microprocessor will attend to the adc, read the data output, issue another adcstart request, and continue with the rest of the tasks until the next interrupt from th e datavalid bit. the time the adc is idle is reduced to a minimal level, enha ncing the sampling rate of th e adc at the given operating frequency. the maximum frequency of adcclk is 10 mhz, and the relationship between adcclk and sysclk (the system clock) is governed by the tvc setting. therefore, maximum adcclk frequency is achieved at certain frequencies. for example, with a sysclk frequ ency of 40 mhz and tvc set to 0, the user can achieve 10 mhz on the adcclk. on the other hand, if sysc lk is at 50 mhz, the maximum achievable adcc lk frequency is 6.25 mhz (tvc = 1). higher sysclk frequencies do not necessary translate into higher adcclk frequencies. this is due to the fact that adcclk is bounded by a 10 mhz limit and is also governed by the tvc value. implementing current monitor applications regardless of the type of the signal being measur ed (i.e., voltage, curren t, or temperature), the acm needs to be initialized at power-up to conf igure the analog quads. the adc may need to be configured and calibrated on device power-up, a gl obal reset event, or at the user?s discretion. "analog configuration mux initialization" on page 10-6 and "adc configuration and calibration" on page 10-9 still apply when a current monitoring application is being implemented. the current monitori ng procedure is very similar to the voltage monitoring steps described in "implementing voltage monitoring applications" on page 10-10 . the only addition al step required to perform sampling on a current monitor channel is the accurate stimulation of the cmstb inputs to the analog block. for current sampling on a desired channel, cmstb should be kept low for more than the tmpwc value (r efer to the values in the fusion family of mi xed-signal flash fpgas datasheet) to discharge previous measurements, and then high for at least the tmpwc value prior to the adcstart request. figure 10-4 illustrates the assertion/deasse rtion of the cmstb input of a specific channel prior to starting sampling. the user should not assert another adcstart prio r to the completion of current adc conversion. when sampling a current, adcst art cannot be asserted for at least for 2 tmpwc after the previous adcstart. if the next adcstart is al so a current monitor (or temperature monitor), there should be at least another tmpwc waitin g period during which cmstb of the desired channel is kept low before asse rtion of adcstart. the select ed channel?s cmstb should be deasserted after the adc has completed sampling the channel (as shown in figure 10-4 ). cmstb can be kept high (after assertion of adcstart) until datavalid is asserted. figure 10-4 ? assertion/deassertion of cmstb input adcclk tmstb adcstart time >tmpwc >tmpwc don?t care sample
interfacing with the fusion analog system: processor/ microcontroller interface 10-14 v1.0 if coreai is configured in coreconsole to have a hardwired cmstb input for the desired channels (hd_cmstbn input), the user will need to stimulate cmstb to fulfill the requirements discussed in this section. in summary, the following are the necessary operations to implemen t current monitoring: ? selecting the analog curren t input pin to be monitored ? ensuring the corresponding cmstb input pin is low for more than the required tmpwc value ? asserting cmstb high fo r longer than tmpwc ? issuing an adcstart request on the desired chnumber ? ensuring that cmstb remain s high until sampling is completed or until assertion of datavalid ? translating the adc output results into applic ation-specific data once datavalid is asserted ? implementing a digital low-pass filter for voltage monitoring (optional) ? implementing a sampling sequence (selecting the next channel) translating the adc output results to the actual measured curr ent is slightly different from the same operation in voltag e monitoring. as shown in figure 2-56 of the fusion family of mixed- signal flash fpgas datasheet, when configured as current monitor, a fixed 10 prescaler is used to buffer the differenti al voltage measured across the external resistor into the adc. therefore, the maximum differential volt age that can be measured with the adc (before overflow) is limited by the v ref value ( eq 10-3 ): max. differential voltage across resistor = i(max) r = v ref / 10 eq 10-3 where r is the external resistor value in ohms. th erefore, the measured current value, based on the adc mode, can be calculated as shown in table 10-1 . implementing temperature monitor applications regardless of the type of signal being measured (i.e., voltage, current, or temperature), the acm needs to be initialized at powe r-up to configure the analog quads. the adc may need to be configured and calibrated as well at device power-up, a global reset event, or the user?s discretion. therefore, the "analog configuration mux initialization" section on page 10-6 and the "adc configuration and calibration" section on page 10-9 still apply when a current monitoring application is be ing implemented. the temperature monitoring procedure is very simi lar to the current monito ring steps described in the "implementing current monitor applications" section on page 10-13 . the only difference is the stimulation of the tmst b input for the temperat ure monitoring channels instead of cmstb in current monitori ng. for accurate temperature sampling on a desired channel, tmstb should be kept low for longer than the tm pwt value to discharge previous measurements, and then high for longer than the tmpwt value prior to the adc start request. the tmstb input of the selected temperature monitoring input sh ould remain high at least unti l the completion of sampling. figure 10-5 on page 10-15 illustrates the assertio n/deassertion of the tmstb input of a specific channel prior to starting sampling. tmstb can be kept high (after assertion of adcstart) until datavalid is asserted. table 10-1 ? adc output translation in current monitoring applications lsb for 8-bit adc (ma) lsb for 10-bit adc (ma) lsb for 12-bit adc (ma) v ref / (10 r 0.255) v ref / (10 r 1.023) v ref / (10 r 4.095)
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-15 since, in coreai, the tmstb inpu ts and adcstart are in two different register spaces, they cannot be asserted at the same time (see figure 10-5 ). assert tmstb high first and then issue adcstart. if coreai is configured in coreconsole to have a hardwired tmstb inpu t for desired channels (hd_tmstbn input), stimulate tmstb accordingly. in summary, the following are the necessary op erations to implement temperature monitoring: ? selecting the analog temperature input pi n to be monitored ? ensuring the corresponding tmstb input pin is low for more than the minimum value of tmpwt ? asserting tmstb high for more th an the minimum value of tmpwt ? issuing an adcstart request on the desired chnumber ? ensuring that tmstb remains hi gh until completion of sampling or assertion of datavalid ? translating the adc output results into applic ation-specific data once datavalid is asserted ? implementing a digital low-pass filter for voltage monitoring (optional) ? implementing a sampling sequence (selecting the next channel) translating the adc output volt age in temperature monitoring applications depends on the v ref value of the adc, the adc mode, and the characteristics of the external (temperature sensor) diode. the relation ship between the measured voltage and the external temperature is described in the fusion family of mixe d-signal flash fpgas datasheet. implementing gate driver applications implementing gate driver applications is differ ent from implementing volt age, temperature, and current monitoring because gate dr ivers are outputs, and driving th em does not require interaction with the adc. however, the acm initiali zation procedure, described in the "analog configuration mux initialization" section on page 10-6 , is still necessary to config ure the selected analog quads as gate drivers with specific parameters, su ch as drive strength an d polarity. gate driver applications can be implem ented as software-/register- driven or hardware-driven. software-controlled gate drivers when a specific gate driver is configured in co reai to be software-cont rolled, the co rresponding ag output pad (analog gate driver) follows the contents of the corresponding bit in coreai adc control register 5. in this approach, the micropro cessor can turn the extern al mosfet (connected to the ag output pad) off or on by writing 1 or 0 to the corresponding bit of adc control register 5. a typical use model for a software-d riven gate is in power sequenci ng applications, where the system figure 10-5 ? assertion/deassertion of tmstb input adcclk tmstb adcstart time >tmpwt >tmpwt don?t care sample
interfacing with the fusion analog system: processor/ microcontroller interface 10-16 v1.0 management processor turns the voltage rails on/off in the de sired sequence. the following example shows a sample coreabc program in which three gate drivers are turned on sequentially. // in this example, it is assumed that coreai is in slot 0 of the apb. also, adc_ctrl5 // represents the adc control register 5 address in the coreai register space. apbwrt dat 0 adc_ctrl5 0x0001 apbwrt dat 0 adc_ctrl5 0x0002 apbwrt dat 0 adc_ctrl5 0x0003 hardware-controlled gate drivers when a specific gate driver is configured in coreai to be hardware-controlled, the corresponding ag output pad (analog gate driver) follows th e corresponding hdgdon input of coreai. when designing with core console, the selected hdgd on inputs can be added to the top-level ports to be driven by the fpga fabric. in a typical use model for hardware -controlled gate driver s, the ag pad drives the external mosfet gate with a pulse width modulation (pwm) signal. design example this section includes a practica l example of a design using coreabc and coreai to implement the following applications: ? voltage, current, and temperature monitors ? gate drivers functionality figure 10-6 illustrates the top-level functi onality of the example design. figure 10-6 shows two voltage supplies in the system: v15ps supplying 1.5 v and v33ps supplying 3.3 v. two voltage rails (v15l and v33l) drive the power inputs of a load. these voltage rails are powered up through two mosfets that are contro lled by the ag3 and ag4 gate drivers of the fusion device. the current on the 3.3 v supply rail is measured across a 0.1 resistor. figure 10-6 ? top-level functionalit y of the example design r = 0.1 ohm v33ps v15ps v33l v15l load fusion av 0 av 1 ac 1 ag 3 ag 4 at 2 atrtn 1
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-17 figure 10-7 shows the flow chart of th e example design, implemented in fusion using coreabc and coreai. the operational phase of the desi gn starts with measuring the power supplies and ensuring that they satisfy the minimum requirements of the load voltage ra ils. once the power supplies are up and running, the v33l and v15l rails are powered up sequential ly (3.3 v first and 1.5 v second after 10 s). after powering the rails, the design continuously monitors the 3.3 v supply, 1.5 v supply, 3.3 v rail current, and operating temperat ure (defined sampling sequ ence). if no abnormal condition occurs, the design remains in this loop monitoring the operating conditions until one of the supplies is turned of f externally. in case of an abnormal situation (e.g., current being more than 1 a), the design sets error flags, turns off both v33l and v15l, and checks for supply lines, and if they are still up and running, it attempts to power up the load again. figure 10-7 ? flow chart of example design measure temperature v15l and v33l off measure v33ps v33ps > 3.1 v? measure v15ps v15ps > 1.43? power up v33l power up v15l wait 10 s measure v33ps v33ps > 3.1 v? measure v15ps v15ps > 1.43? measure 3.3 v load current i > 1 a? temp > 70c? set error flags start @ reset yes no yes no yes no yes no yes no yes no
interfacing with the fusion analog system: processor/ microcontroller interface 10-18 v1.0 implementation in a fusion device this design example is implemented using coreabc as the core microcontroller and coreai as the interface to the fusion analog block. the steps below describe the core abc and coreai settings and connections and the coreab c program that implements th e flow chart illustrated in figure 10-7 on page 10-17 . building the example desi gn system in coreconsole coreabc and coreai in this example are conn ected together using an apb, as shown in figure 10-8 . the following are the major setti ngs of the coreabc and coreai configuration in coreconsole: coreabc settings: apb address bus width: 8 apb data bus width: 16 number of coreabc outputs: 1 instruction store: soft coreai settings: acm clock divider: 4 av0: 0?2 v analog input av1: 0?4 v analog input ac1: current monitor at2: temperature monitor ag3: software-driven ag4: software-driven varef: internal 2.56 v adc mode: fixed 12-bit mode tvc: fixed to 0 stc: register-controlled apb interface width: 16 bits the above settings result in th e memory address map shown in table 10-2 on page 10-19 . figure 10-8 ? implementation of example design in coreconsole
interfacing with the fusion analog system: processo r/microcontroller interface v1.0 10-19 the memory of the design in coreconsole can be obtained from the following location: /softw areexport//memorymap.html the initialization values for the acm register space used to configure the analog quads can be calculated as discussed in the fusion family of mixed-signal flash fpgas datasheet or obtained from the acmtable.vhd (or acmtable.v ) file. in this example, the acm initialization is performed by using the apbwrt instructi on to write desired values to the corresponding acm register space. as discussed in "acm initialization specific to coreabc" on page 10-7 , designers can take advantage of the apbwrt acm command and write to the acm registers with the va lues defined in the acmtable.vhd (or .v ) file. coreabc instruction program the coreabc program in the fusion handbook design files executes the functionality depicted in figure 10-7 on page 10-17 . the coreconsole project of this example can also be found in the fusion handbook design files . $wait_10us is called wh enever needed to ensure that the elapsed timing for tmstb and cmstb activation/deactivation is mo re than the minimum requirement. inside the function, a loop counter is loaded with a count value an d then decremented until it reaches zero. the count value should be chosen such that the elapsed time afte r exiting the function is 10 s. each of the instructions used in the $wait_10us rout ine takes three clock cycles to execute. assuming sysclk runs at 40 mhz, th e count value can be obtained from eq 10-4 : delay = (3 + 3 + count_value (3 + 3) + 3) / f eq 10-4 where f = 40 mhz. instructions in this example are based on coreab c v2.1. some instructions may vary (e.g., loop instructions used in the $wai t_10us routine) if a differen t version of coreabc is used. in a real application design, the $wait_10us routine can be replaced by a set of instructions that perform part of the design func tionality during the required tmpwc or tmpwt period. this increases the processing performance of the design. hdl implementation after building the core of the de sign in coreconsole, the design has be to be completed in hdl where the microprocessor and the coreai system (alo ng with any other peripherals in the system) are imported into libero ide in hd l format and connected to the rest of the design, to go through table 10-2 ? memory map of the example design address type width reset value name description base address + 0x00 read/write 16 0x0 acm_ctrl_status acm control status register base address + 0x04 read/write 16 0x0 acm_addr acm address register base address + 0x08 read/write 8 0x0 acm_data acm data register base address + 0x0c read/write 16 0x 0 adc_ctrl_1 acm control register 1 base address + 0x10 read/write 16 0x 0 adc_ctrl_2 acm control register 2 base address + 0x14 read/write 16 0x 0 adc_ctrl_3 acm control register 3 base address + 0x18 read/write 16 0x 0 adc_ctrl_4 acm control register 4 base address + 0x1c read/write 16 0x 0 adc_ctrl_5 acm control register 5 base address + 0x20 read-only 16 0 x0 adc_status adc status register base address + 0x24 read-only 16 0x0 read_fi fo_data_output read fifo data output base address + 0x28 read-only 8 0x0 r ead_fifo_status read fifo status base address + 0x2c read/write 16 0x0 i rq_enable interrupt enable register base address + 0x30 read-only 16 0x0 ir q_status interrupt status register
interfacing with the fusion analog system: processor/ microcontroller interface 10-20 v1.0 the rest of the fpga design flow. the hdl code in the fusion handbook design files is the top-level wrapper used in the example design. in this example, the coreabc inst ructions are stored in soft mode. therefore, the instructions can be stored in the fusion embedded flash memory or in external memory. th e instructions are loaded into sram from the flash memory at power-up (initialization), an d the microprocesso r runs off the sram; coreabc offers a feature to run directly off the flash memory as well. in the hdl code, init_block represents the initialization client of the fusion embedded fl ash memory. an embedded ccc is used to generate two clock signals: a 10 mhz clock to drive the embedded flash memory and the initialization process to load the sram with coreabc instructions, and a 40 mhz clock used as the system clock for the operational phase of the design. designing with the rtc coreai enables you to interface wi th the fusion rtc. when configuring coreai in coreconsole, you need to specify the rtc and its parameters. coreai provides the necessary i/os, as described in the coreai handbook . acm address space 0x40 to 0x58 is us ed to read or write specific rtc parameters, such as count or ma tch values. reading from and wr iting to these registers is no different from other acm read /writes descri bed in the "analog configuratio n mux initialization" section on page 10-6 . the only difference is the targeted address of the acm register space. part number and revision date part number 5100092-006-1 revised december 2007 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.0) page 51700092-006-0 corrected the operations given in the "implementing temperature monitor applications" section . 10-14
v1.2 11-1 11 ? interfacing with the fusion analog system: ip interface fusion analog system soft ip design the analog system soft ip design flow is an ip-based design method for hdl designs that establishes a backbone to in terconnect the actel fusion ? fpga fabric, the analog system, the embedded flash memory block, and other peripher als. the analog system soft ip includes an analog-to-digital converter sample sequence controller (assc) that sets up the adc sample sequence, a system monitor evaluation phase stat e machine (smev) that co mpares the adc results to user-defined threshold values, and a system mo nitor transition phase st ate machine (smtr) that asserts threshold flags accordingly. using th e ip configuration catalog in actel libero ? integrated design environment (ide), the user creates and configures the vhdl or verilog analog system soft ip along with the flash memory analog system clie nt. the user can configur e over/under threshold flags, acquisitio n time, filtering factor, and assert/deassert samples for analog inputs. more details are addressed in the "basic analog bloc k settings" section . once the ip is configured, the user instantiates the analog system into hdl or builds the system in a smartdesign project. standard hdl design flow is used to comp lete the design, as described in fusion design solutions and methodologies . when creating the analog syste m in libero ide using the an alog system build er (asb), a configuration file is generated, and its data is st ored in the spare pages within the embedded flash memory during fpga programming. the flash memory analog system client is used to create the memory partitions to store this configuration data. the analog system uses the embedded flash memo ry to hold the nonvolatile configuration data for the analog subsystem. after power-up and during the initialization process, the flash memory is read and the data is stored in th e analog system?s volatile register or ram blocks within the analog subsystem. more information abou t the embedded flash memory sy stem and clients is available in fusion embedded flash memory blocks . note: any time the analog system is regenerated, the analog system client must also be regenerated from the flash memory system builder in libero ide. the analog system soft ip design flow offers a numb er of advantages to users. all the necessary soft ip cores are free. sample sequence contro l, averaging/filtering, and threshold response functions are built-in and specified by an intuitive gui in libero ide. ip configuration and connectivity are tightly integrated into smartdesign and libero ide, enabling users to rapidly and seamlessly implement the complete analog and peripheral interface. users do not have to write up their own code to co ntrol the analog and flash memory systems. for processor- or microcontroller-based designs, a more efficient implementation can be realized through coreai (analog interface) and the methods discussed in interfacing with the fusion analog system: processor/ microcontroller interface .
interfacing with the fusion an alog system: ip interface 11-2 v1.2 system overview ? interface components figure 11-1 gives an overview of the interface betw een the analog system soft ip, the adc, the clock circuitry, the device ram, and th e embedded flash me mory. as shown in figure 11-1 , there are three analog interface soft ip blocks and several blocks that interact directly or indirectly with the analog interface so ft ip blocks. the analog interface soft ip components are listed in table 11-1 on page 11-3 , and the components that in teract with these soft ip components are listed in table 11-2 on page 11-3 . detailed descriptions for each of the components listed in table 11-1 on page 11-3 are included in the "smartgen soft ip blocks" section on page 11-5 . figure 11-1 ? fusion interface compon ents (relative to analog interface soft ip) clock crystal oscillator rc oscillator pll interval gen s ms s external clock clock generation general-purpose digital inputs general-purpose digital outputs this clock signal is distributed to all components in this diagram. jtag 10 adc sample sequence controller 1 system monitor evaluation phase state machine 2 system monitor transition phase state machine 3 5129 dual-port ram 5129 dual-port ram(s) 5129 dual-port ram(s) 4 5 6 init/config ram initializer 7 adc 8 analog mux sar adc user read access user read access user read access analog inputs from quads nvm 9 hard ip soft ip
interfacing with the fusion analog system: ip interface v1.2 11-3 table 11-1 ? fusion analog interfac e soft ip components number description 1 analog-to-digital converter sample sequence controller: the assc is a configurable sequencer that sets up the order of samples from the adc, contro ls various measurement parameters of the adc samples, and sends cont rol commands to the adc. 2 system monitor evaluation phas e state machine: the smev read s adc samples from the result locations in the assc ram and compares the resu lts to user-defined thre shold values. comparison results are stored in smev ram. 3 system monitor transition phase state machine: the smtr reads from smev ram and, for each enabled channel, checks comparison results (previously calculated by the smev block) and generates the threshold flags defined by the us er in the analog system builder. table 11-2 ? fusion components that in teract with analog inte rface soft ip components number description 4, 5, 6 5129 dual-port ram blocks: these ram blocks are used to stor e ?program? sequences for the smtr and smev. they are also used to store data samp les calculated by the adc and data values that control the operation of the assc. they are initialized by the init/config soft ip block, which transfers data from nonvolatile memory (nvm) after a system reset. note that these ram blocks can also be modified while the system is live to allow the user to perform real-time system debugging before committing resources to pr ogramming the nvm. this debugging feature is addressed by synplicity ? identify software. for more information , refer to the identify user?s guide. 7 init/config ram initializer: the sole purpose of this soft ip block is to initialize the system ram blocks after a system reset, by reading data from the nvm. 8 adc: this analog-to-digital converter hard ip co mponent is the ma in interface betw een the external analog voltage, current, and temperature sources, an d the internal digital fpga user logic (soft ip). it is selectable for 8-, 10-, or 12-bit operation. 9 nvm: the nonvolatile memory (flash) will be used, at minimum, to store pr ogram sequences for the assc, smev, and smtr. 10 clock generation: internal or exte rnal clock generation for digital system time base reference. the internal pll, internal rc oscillato r circuit, or external crystal osci llator circuit can be used in this process.
interfacing with the fusion an alog system: ip interface 11-4 v1.2 system operation the analog block (ab) sy stem contains the analog block hard ip and the analog interface soft ip, which includes assc, smev, smtr, and their corr esponding sram blocks. the flash memory system contains the embedded flash memory hard ip bloc k and the interface soft ip, or the init/config ip block. figure 11-2 shows the generic connections between the analog block system and the flash memory system in the smartgen soft ip design flow. initialization the init/config soft ip is used to accomplish the in itialization of the fusion analog block. all user- defined analog block pa rameters are preprogrammed into th e embedded flash memory and are loaded into the co rresponding analog system soft ip ram blocks and analog configuration mux (acm) registers by the init/confi g ip during device power-up. for more information about analog client initialization, refer to fusion embedded fl ash memory blocks . sample and convert once the initialization and cali bration is done, or init_done and calibrate_o are asserted high, the analog system soft ip starts functioning. th e assc ip controls the sample sequence, the smev applies a moving average to the adc conversion output and co mpares the outputs with the preset threshold values, and the smtr checks the comparison results and acts on them based on figure 11-2 ? smartgen soft ip design flow ? generic connections init_clk sys_reset init_power_up init_done init_data init_addr init_acm_wen init_acm_rtc_wen init_assc_wen init_ev_wen init_tr_wen init_done init_data init_addr init_acm_wen init_acm_rtc_wen init_assc_wen init_ev_wen init_tr_wen sys_clk sys_reset varef datavalid assc_done flash memory system analog block system hdl logic threshold flags adc_result averaged adc_result
interfacing with the fusion analog system: ip interface v1.2 11-5 predefined behavior. the user can also probe and process the adc output directly and set up corresponding reactions. the tw o modes are described below. threshold flags operation mode the threshold values are preset during analog sy stem soft ip configuration in libero ide. the values are programmed into the embedded flash through the analog system client, then loaded into the sram during initializati on. smev soft ip does the comp arison between the average adc results and the threshold values, and saves the comparison results to the smev sram. the smtr soft ip reads the results from the smev sram and asserts or deasserts user-defined threshold flags, which are general-purpose outputs (gpos) of the analog system block. the gpos can be used by internal logic in the fpga array, or th ey can trigger external i/os directly. adc result direct access mode instead of reacting on the threshold value comparison result from the smev, users can directly access the adc results and convert them to meaningful voltage, curr ent, or temperature values and process these values for different purposes. to ac complish this, the user first needs to expose the necessary ports from the assc or smev ip through the advanced options in the analog system builder. the corresponding ports are listed in th e assc and smev sections. second, the user needs to build an interface to read ou t the valid adc results from the a ssc or smev ram. the basic logic of the interface is discussed in the coreai section of the interfacing with the fusion analog system: processor/microcon troller interface chapter. sample code for fetchi ng the adc result is located in the "sample code" section on page 11-19 . once the adc result has been fetched, it can be translated back to a voltage, curren t, or temperature value. sample co de for this is also provided in the "sample code" section on page 11-19 . smartgen soft ip blocks adc sample sequence controller (assc) function the assc is a configurable sequ encer that sets up the order of samples from the adc, controls various measurement parameters of the adc samp les, and sends control commands to the adc. it also contains multiplexer logic for reading from and writing to a 5129 dual-port ram block. in addition to controlling sequencing of adc samples, the assc block performs digital post-scaling of the adc samples, and adc saturation detection, functions that were previously handled with additional soft ip blocks. note: the assc does not control the various prescaler and other signals within each analog quad (except for the current monitor and temperature monitor strobe connections). these are defined during soft ip configuration in libero ide and initialized via the init/config soft ip block into the acm.
interfacing with the fusion an alog system: ip interface 11-6 v1.2 interfaces note: all signals are active high (logic 1) unless othe rwise noted. all port width specifications are in verilog notation. any alphabetic text within po rt width brackets indicates that the specified port width is controlled via a generic (vhd l) or parameter (verilog) described in table 11-3 . all i/o signals are synchronous to the rising e dge of the clk signal unless otherwise noted. the signals in table 11-3 are the typical signals users should monitor in the si mulation for the regular adc conversion process. figure 11-3 ? assc i/o signal diagram clk nreset adc_start assc_seqin[ts_width?1:0] assc_xtrig assc_xmode assc_seqjump assc_seqchange assc_seqout[ts_width?1:0] adc_busy adc_calibrate adc_mode[3:0] adc_dvc[7:0] adc_stc[7:0] adc_vrefsel adc_chnr[4:0] adc_pdown adc_reset init_addr[8:0] init_di[8:0] init_assc_wr init_done user_assc_addr[8:0] user_assc_rd assc_ram_do_b[8:0] assc_ram_addr_b[8:0] assc_ram_rw_b assc_ram_csn_b assc_ram_di_b[8:0] user_assc_ram_busy adc_result[11:0] assc_chsat assc_chlatd ev_assc_rd ev_assc_addr[8:0] assc_ram_addr_a[8:0] assc_ram_rw_a assc_ram_csn_a assc_ram_di_a[8:0] assc_done assc_wait cm_stb[9:0] tm_stb[10:0] assc_ram_wr_busy_b ev_evflag ev_done tr_trflag tr_done assc_sampflag table 11-3 ? assc i/o signal descriptions name type description clk input system clock: reference cloc k for all internal logic (100 mhz maximum). this signal is connec ted to the top level as sys_clk. nreset input active-low asynchronous reset. this signal is connected to the top level as sys_reset. init_addr[8:0] input init/config ram addre ss: these address signals come from the init/config soft ip block for writing to the 5129 assc ram. init_done input init/config done: this static signal indicates that the init/config soft ip block has completed loading all of its clients (including the assc ram block) from data stored in the internal fusi on nvm block(s).
interfacing with the fusion analog system: ip interface v1.2 11-7 assc_done output assc done: this output indicates that the assc block has completed the current fu nction and is either waiting for further action (e.g., the power-down or stop function) or is about to transition to the next sequence (e.g., the sample or calibration function). if the assc_done signal is active at the same time that the assc_sampflag signal is active, this indicates that a sample function has just completed and will cause the smev block to commence with evaluation sequences followed by transition sequences within the smtr block; otherw ise, if the assc_done signal is active and th e assc_sampflag signal is inactive (logic 0), the smev block will not have eval uation sequences for the current sequence (timeslot). this output is connected to the smev block and may optionally be used external to the analog interface soft ip blocks by the user. adc_calibrate input adc calibration: this si gnal from the adc indi cates that internal calibration is currently in effe ct. this input connects to the calibrate_o output from the adc. adc_result[11:0] input adc result : these signals comp rise the conversion result from the adc. in 12-bit mode, the adc uses all bits; in 10-bit mode, it uses bits 11:2; and in 8-bit mode, it uses bits 11:4. all unused adc bits are set to logic 0 when in 10-bit or 8-bit mode. these inputs connect to the result_o[11:0] ou tputs from the adc. the following signals are used for jump sequence control. assc_xmode input external trigger mode: if th is input is logic 1, the assc uses the assc_xtrig signal to transition to and complete the current sequence timeslot. if this input is logic 0 (default operation for automated sequencing), the intern al timeslot counter is used to automatically advance to the next sequence number. this input can come from the smtr (from one of the gpo signals) or user logic external to the analog interface soft ip blocks , or can be statically tied off to logic 0 or logic 1. assc_xtrig input external trigger: if the a ssc_xmode input is logic 1 and this input is held at logic 1 for exactly on e clock cycle, th e assc block will transition to and complete the current sequence. if the assc_xmode input is logic 0 (d efault operation for automated sequencing), this input is ignored. this input can come from the smtr (from one of the gpo signals) or user logic external to the analog interface soft ip blocks, or can be statically tied off to logic 0. if this signal is used to contro l external triggering, the user should monitor the assc_done signal to know after which point the assc_xtrig will again have effect. assc_seqjump input sequence jump enable: setting this signal to logic 1 jumps to the sequence number in dicated on the assc_seqin[ts_width?1:0] input pins after the current sequen ce timeslot has completed. this input can come from the smtr (f rom one of the gpo signals) or user logic external to the analog interface soft ip blocks, or can be statically tied off to logic 0. table 11-3 ? assc i/o signal descriptions (continued) name type description
interfacing with the fusion an alog system: ip interface 11-8 v1.2 assc_seqin[ts_width?1:0] input sequence number in: these inputs are used in conjunction with the assc_seqjump signal to jump to a particular sequence number from the current sequence after th e current sequence timeslot has completed. the smtr sets thes e signals. these inputs can come from the smtr (from several of the gpo signals) or user logic external to the analog interface soft ip blocks , or can be statically tied off to any combination of logic 0 and logic 1 values. assc_seqout[ts_width?1:0] ou tput sequence number ou t: these outputs denote the current sequence timeslot. the smev block uses these signals. these outputs are connected to the smev block and may optionally be used external to the analog interface so ft ip blocks by the user. assc_seqchange output sequence change: this output indicates that the outputs assc_seqout[ts_width?1:0] will ch ange after the very next rising edge of clk. this output is co nnected to the sm ev block and may optionally be used external to the analog interface soft ip blocks by the user. users should monito r the following signals if they want to access the adc conversion results from the assc ram. user_assc_ram_busy output assc ra m busy: this output signal indicates that either the init/config soft ip block or the sm ev soft ip block is busy accessing the a-port of the assc ram. this signal can optionally be used by user logic external to the analog interface soft ip blocks, or can be left unconnected if unused. user_assc_addr[8:0] input user ram address: these address signal s can be controlled by the user to allow read access from th e a-port of the 5129 assc ram. if unused, these signals should be tied off to logic 0 or logic 1. user_assc_rd input user ram read enable: this control signal can be controlled by the user to allow read access from the a-port of the 5129 assc dual- port ram (the user will need to connect to the assc_ram_do_a[8:0] port for read data). if unused, this signal should be tied off to logic 0. the user must ensure that the assc_ram_busy signal is inactive at logic 0 while this signal is activated; otherwise, the data read from the a-port of the assc ram will not be from the user_assc_addr[8:0] address. assc_ram_di_a[8:0] outp ut assc ram write data: these signals are connected to the a-port data inputs (write data) of the 5129 assc ram. table 11-3 ? assc i/o signal descriptions (continued) name type description
interfacing with the fusion analog system: ip interface v1.2 11-9 system monitor e valuation phase state machine (smev) function the smev reads adc samples from the result[11:0] locations in the assc ram after each channel sequence has been processed by the assc block, and performs evaluation processing on the adc samples. the smev block performs digital low-pass filtering of th ese samples, compares the low- pass-filtered samples against compare thresholds, and writes the results back into one or more 5129 dual-port ram tiles (the number of 5129 ram tiles required will depend upon how many program sequences are required for each application). although the smev block deals with samples from the adc, there is no direct link between it and the adc ; the assc block writes all raw adc samples into the assc 5129 dual-port ram, which the smev reads during the evaluation phase. interfaces note: all signals are active high (logic 1) unless othe rwise noted. all port width specifications are in verilog notation. any alphabetic text within po rt width brackets indicates that the specified port width is controlled via a generic (vhdl) or parameter (verilog) described in table 11-4 on page 11-10 . to access the adc conversion re sults from the smev ram, user s should monitor the signals in table 11-4 on page 11-10 . figure 11-4 ? smev i/o signal diagram clk nreset assc_seqchange ev_chhold[4:0] assc_seqout[ts_width?1:0] ev_ram_addr_b[ev_asize-1:0] ev_done adc_chnr[4:0] init_addr[ev_asize?1:0] init_di[8:0] init_ev_wr init_done user_ev_addr[ev_asize?1:0] user_ev_rd tr_ev_rd tr_ev_addr[ev_asize?1:0] ev_assc_rd ev_assc_addr[8:0] assc_ram_do_a[8:0] ev_ram_rw_b ev_ram_csn_b ev_ram_di_b[8:0] ev_ram_addr_a[ev_asize-1:0] ev_ram_rw_a ev_ram_csn_a ev_ram_di_a[8:0] user_ev_ram_busy assc_done assc_sampflag ev_evflag ev_ram_do_b[8:0] assc_ram_wr_busy_b ev_ram_wr_busy_b
interfacing with the fusion an alog system: ip interface 11-10 v1.2 table 11-4 ? smev i/o signal descriptions name type description user_ev_addr[ev_asize?1:0] input user ram address: these address sign als can be controlled by the user to allow read access from the 5129 smev ram(s). if unused, these signals should be tied off to logic 0 or logic 1. user_ev_rd input user ram read enable: this control signal can be controlled by the user to allow read access from the a-port of the 5129 smev dual- port ram(s) (the user will need to connect to the ev_ram_do_a[8:0] port for read data). if unused, this signal should be tied off to logic 0. the user must ensure that the us er_ev_ram_busy si gnal is inactive at logic 0 while this sign al is activated; otherwise, the data read from the a-port of the smev ram( s) will not be from the user_ev_addr[ev_asi ze?1:0] address. user_ev_ram_busy output smev ram busy: this output signal indica tes that either the init/config soft ip block or the smtr block is busy accessing the a- port of the smev ram(s). this signal can optionally be used by user logic external to the an alog interface soft ip blocks or can be left unconnected if unused. assc_ram_wr_busy_b input assc busy writing: this active-high si gnal indicates that the assc block is busy writing to the b-port of its dual-port ram (this input is only used for non-fusion/-proasic ? 3 technology implementation, such as proasic plus ? , which has no tru e dual-port ram). ev_ram_wr_busy_b output smev busy writing: this active-high signal is for user status monitoring and indicates that the sm ev block is busy writing to the b-port of its dual-port ram. it must be connected to the smtr block for non-fusion/-proasic3 technology implementation, such as proasic plus ; otherwise, it can be left unconnected. ev_ram_di_a[8:0] output smev ram write data: these signals are conn ected to the a-port data inputs (write data) of the 5129 smev ram(s).
interfacing with the fusion analog system: ip interface v1.2 11-11 system monitor transition phase state machine (smtr) function for each enabled channel, the smtr checks comparison resul ts previously calculated by the smev block and stored in the smev ram, and asserts or deasserts different user-defined threshold flags, which are general purpose outputs (gpos) of the analog system block. the gpos can be used by internal logic in the fpga array, or th ey can trigger external i/os directly. interfaces note: all signals are active high (logic 1) unless otherwise noted. basic analog block settings in the analog system builder ma in window, the user can enter system clock frequency and adc resolution. the system clock is used to drive th e assc, smev, and smtr soft ip blocks. also, adc_clk is derived from the system clock, and has to be equal to or less than 10 mhz. the adc block has a built-in divider (4, minimum divider = 4) to automatically divide the system clock into the appropriate adc _clk range. users can achieve ma ximum rate for adc_clk (10 mhz) by selecting a system clock frequenc y of 40 mhz or 80 mhz. for mo re information about the adc sample rate and accuracy, refer to the analog-to-digital converter background section in the designing the fusion analog system chapter. refer to the fusion starter kit user?s guide and tutorial for a sample design implementing the following settings. av parameter settings to configure a voltage monitor, the user can choose to use either direct analog input or prescaled input. direct analog input limits the inpu t voltage to less than the varef voltage. usually, it is 2.56 v if the internal reference voltage is chosen, or it can be 0 to 3.3 v if an external reference voltage is used. for example, if internal varef (2.56 v) is selected, choosing a direct analog input to sample a signal that swings between 0 to 2.56 v can avoid the gain and offset error that could be introduced by the prescaler. figure 11-5 ? smtr i/o signal diagram clk nreset ev_done tr_ev_rd init_addr[tr_asize?1:0] tr_ev_addr[ev_asize?1:0] gpo[2 gpo_bits 32?1:0] gpi[2 gpi_bits 32?1:0] ev_chhold[4:0] init_di[8:0] init_tr_wr init_done user_tr_addr[tr_asize?1:0] user_tr_rd ev_ram_do_a[8:0] tr_ram_addr_b[tr_asize?1:0] tr_ram_rw_b tr_ram_csn_b tr_ram_di_b[8:0] tr_ram_addr_a[tr_asize-1:0] tr_ram_rw_a tr_ram_csn_a tr_ram_di_a[8:0] user_tr_ram_busy tr_ram_do_b[8:0] ev_ram_wr_busy_b tr_ram_wr_busy_b tr_done tr_trflag
interfacing with the fusion an alog system: ip interface 11-12 v1.2 however, if the inpu t voltage is too small (0 v ? 0.2 v) compar ed to 2.56 v, and if direct input is used, resolution will be degraded. at this time, a prescaler shou ld be used to amplify the signal for better resolution. if the input signal is greater than varef, the pr escaler must be used to sc ale down the input range before the adc can sample and convert it. once the adc fini shes converting the analog signal to a digital value, it filters (averages) the resulting digital output. digital filt ering is a single-pole low-pass filt er built in soft gates, that can be used to improve the signal-to-noise ratio. if th e adc input data is very erratic, the filtering will smooth out the input and reduce the noise. the filtered value is calculated using eq 11-1 : filtering_result n = filtering_result n-1 + (adc_result n / filtering_factor) ? (filtering_result n-1 / filtering_factor) eq 11-1 if the digital filtering factor is set to 1, it is ignored. in some cases where the inputs have very low fr equency and the electrical environment is not very noisy, it may be possible to proceed without any special filtering of input analog signals. however, in most applications it is desirable to at lea st implement a simple post -conversion digital filter inside the fpga by oversa mpling and averaging se veral results to reduce the effects of random noise in the conversion signal path and improve overall accuracy. this simple averaging is automatically handled in the softwa re by setting the digital filter ing factor in the analog system builder to specify how many samples are averaged (when the factor = n , 2 n samples are averaged together). for situations where greater accuracy is required , an external analog f ilter may be needed to eliminate non-random and out-of-band noise sources. if an analog filter is not used to restrict the input signal content to the band of interest, any out-of-band signals or noise will be aliased into the conversion result as random in-band noise. some applications?for example, those that re quire frequency detection?may need both external analog filtering to limit out-of-b and effects, and more sophisticate d digital processing such as a multi-tap finite impulse response (fir) filter. a wide variety of digital filtering methods are available through the fpga gates available in a fusion device. once a digital filter factor is selected, the initial value option is activated. this initial value is used for simulation purposes. the user ca n preset an initial value to imit ate a real situation. for example, let the input signal be a 3.3 v po wer supply that fluctu ates around 3.3 v with a range of 50 mv. the user can set 3.3 v as the in itial value for simulation mode. acquisition time defines how much time the us er gives the adc to co nduct the sampling and conversion. if the acquisition time is too short, the input signal may not even be settled yet, and the adc will just sample some in valid signals. the recommendation is at least 0.2 s for direct analog input, and 10 s for the prescaled input. refer to the analog-to-digital converter background section in the designing the fusion analog system chapter for more info on acquisition time. maximum voltage define s the expected maximu m input voltage on th is particular channel. users can set threshold flags for smev ip to compare against the input voltage, an d smtr ip will trigger the corresponding flags based on the smev comparison results. the assert samples and deassert samples paramete rs define after how many consecutive events a flag should be asserted or deasserted. ac parameter settings besides all the parameters discussed in the volt age monitor configuratio n, a current monitor acquisition time should be at leas t 5 s. users should also define the signal polari ty and make sure that the potential on the adjacent av pad must be greater than the ac pad. a realistic sense resistor value (0.005 ? 100 ) should be entered in the ac peripheral configuration window. the adjacent av channel in the same anal og quad can still be used as a voltage monitor.
interfacing with the fusion analog system: ip interface v1.2 11-13 at parameter settings similar to the current monitor, a 5 s acquisition time and digital fi lter factor value of greater than 512 are recommended for better conversion accuracy. sample sequence setting users can choose to samp le some or all of the analog chan nels. to manually adjust the sample order, select allow manual modification of operating sequence in the sample sequence configuration window. the last operation should always jump back to th e main procedure or jump to another procedure. package pin assignment users can assign the package pin nu mber for the av/ac/at or gate driver peripherals in the analog system builder window, and th is assignment will be hono red in the designer software. soft ip implementation options default implementation (assc, smev, and smtr) the default implementati on for the analog syste m soft ip includes the assc, smev, and smtr ip blocks for the fusion analog system and the init/config ip block for the fusion flash memory system. this section focuses on the analog block soft ip. the init/config ip is discussed in the using the embedded flash memo ry for initialization section in fusion embedded flash memory blocks . figure 11-6 is a view of the ip and the ram blocks in the analog system. the datapath of the system is shown in the figure (m uxes are not show n for clarity). dual-port rams are used in the soft ip. all ip blocks access their co rresponding rams through portb. all ip blocks access each other?s ram th rough porta. all user access is through porta. the sequence of events for proce ssing adc data is as follows: 1. assc reads its opcode from the assc ram for slot n processing. figure 11-6 ? analog system ? ip and ram blocks ab assc assc ram portb porta smev smev ram portb porta smtr smtr ram portb porta init. access assc ram user access smev ram user access 1 6 2 3 4 5 7 iii
interfacing with the fusion an alog system: ip interface 11-14 v1.2 2. assc processes adc for slot n. 3. assc completes slot n processing and writes adc result value to assc ram. 4. assc signals done. 5. smev wakes up and begins reading smev ram for opcodes. 6. assc reads its opcode from the a ssc ram for slot n + 1 processing. 7. smev reads assc ram for adc resu lt value of slot n processing. 8. the smev and smtr state machines do not execute in parallel. the smev state machine finishes its processi ng and then signals the smtr to begin. figure 11-7 is the simulation result ill ustrating the soft ip events: figure 11-8 shows the soft ip process for multip le channels in a pipeline mode: figure 11-7 ? simulation result illustrating soft ip events assc activity smev activity smtr activity figure 11-8 ? soft ip process for multiple channels in pipeline mode assc smev smtr block activity time ch1 ch2 ch3 ch4 ev ev ev tr1 tr2 tr3 123
interfacing with the fusion analog system: ip interface v1.2 11-15 use default implementation and ex pose adc result (assc i/os, smev i/os, and acm i/os) when users want to directly access the raw adc results from the adc or from the assc ram, or access the averaged adc result from the smev ram, they can sele ct the corresponding ports in the advanced options window. they will need to develop corresponding hdl code to access those interfaces. users can also export and ac cess the acm bus, as described in the analog configuration mux (acm) section in the interfacing with the fusion analog system: processo r/microcontroller interface chapter. for sample hdl code, refer to the fusion starter kit user ?s guide and tutorial . user accessing adc_result directly to read adc_result from the adc directly, th e following signals should be monitored closely: assc_done (active-high) datavalid (active-high) adc_chnumber adc_result figure 11-9 shows the timing relati onship among the four signals listed above. assc_done assertion determines which channe l data is available on the adc_result bus. datavalid assertion indicates th at the new adc_result is ready. when both assc_done and datavalid are asserte d, the user should record which channel number is active and then read adc_result for that channel. the time elapsed from the rising edge of datavali d to the next channel number change is at least eight sysclk cycles. if there is concern that adc_result may not be read out and processed as fast as the channel changes, adc_res ult and adc_chnumber should be latched?this is one of the functions of the assc ram. assc and user a ccessing assc ram a signal is exported to in dicate that the assc is reading or writing the sram (user_assc_ram_busy) . the user should not access this interface while that is occurring. figure 11-9 ? how to read valid adc_result assc_done datavalid adc_chnumber adc_result previous data data for channel 1e minimum 8 sysclk cycles 1e 01
interfacing with the fusion an alog system: ip interface 11-16 v1.2 smev and user accessing assc ram the user_assc_ram_busy si gnal indicates that the smev is accessing the ram, and as stated in the documentation, the user should not access this interface while that is occurring. smev and user acce ssing smev ram a signal is exported to in dicate that the smev is reading or writing the sram (user_ev_ram_busy). this indicate s to the user to stop reading. smtr and user accessing smev ram the user_ev_ram_busy sign al indicates that the smtr is access ing the ram, and as stated in the documentation, the user shou ld not access this interface while that is occurring. in general, the user_assc_ram_b usy or user_ev_ram_busy signal indicates that other ip is accessing the corresponding ram, and the user sh ould not access the in terface while that is occurring. in other words, users can only access the ram content while the busy signal is deasserted. for a given channel, the adc result is saved as tw o parts in two consecutive address locations inside the ram. for example: ******************************************************************************** assc memory content report ******************************************************************************** slot channel address bits value -------------------------------------------------------------------------------- 0av0 3| [08:00]| raw adc result [08:00] 4| [02:00]| raw adc result [11:09] -------------------------------------------------------------------------------- ******************************************************************************** smev memory content report ******************************************************************************** channel address bits value -------------------------------------------------------------------------------- av0 75| [08:00]| averaged adc result [08:00] 76| [02:00]| averaged adc result [11:09] -------------------------------------------------------------------------------- when the busy signal is deasse rted, the user must execute two user reads (rd1 and rd2) to read out the whole adc result. if the bu sy signal is asserted after rd1 but before rd2, the user must re- execute rd1 to read the lower address data once th e busy signal is deasse rted again, followed by rd2 to read the higher address data. meanwhile, the user must control the address increment appropriately. for sample hdl codi ng on this topi c, refer to the "sample code" section on page 11-19 . this code is also used in the fusion starter kit tutorial design example. the user interfaces to the assc ram or the smev ram are the same. the glue logic to the interface should keep monitoring the busy signal and sending the right ram address at the appropriate time, then execute the read action. fo r more details, refer to the timing diagrams in figure 11-10 on page 11-17 and figure 11-11 on page 11-17 .
interfacing with the fusion analog system: ip interface v1.2 11-17 use ip cores for adc sequence control only when users do not need the smev (averaging adc results) and smtr (tri ggering thre shold flags) functions, but only need the adc sequence con trol function (assc ip block), they can select the ip cores for adc sequence control only option in the advanced options window. additionally, if they want to directly access the raw adc result from the adc or from the assc ram, or access the acm bus, they can select the corresponding ports in the advanced options window. figure 11-10 ? user read soft ip block rams figure 11-11 ? user read soft ip bl ock rams (continued) ram data lower address data higher address data lower address higher address busy user read rd1 rd2 nreset 000000000 000000000 ram data lower address data higher address data lower address busy user read rd1 rd2 nreset busy lower address higher address rd1 lower address data
interfacing with the fusion an alog system: ip interface 11-18 v1.2 varef capacitor value selection the fusion device can be configured to generate a 2.56 v internal reference voltage (varef) that can be used by the adc. when varef is internally generated by the fusion device, a by-pass capacitor must be connected from this pin to gr ound. for more information, please refer to the ?pin description? section of the fusion family of mi xed-signal flash fpgas datasheet. in the smartgen analog system builder, under advanced option s, users can select the capacitor value based on the system level requirements. depending on the capacitor value, a delay circuitry will be automatically added to ensure the smartg en ip will not perform an adc conversion until the voltage level on the varef is stable. table 11-5 shows the corresponding settling time based on the selectable capacitor value in the software. if the ca pacitor value is differ ent than the selectable values in the software, the user should pick the next higher capacitor va lue to ensure sufficient settling time is added. the addi tional delay will significantly incr ease the simulation time, but the user may consider changing the resolution of th e simulator to speed up the simulation process. note: users who are using the standalone ab macro and build their own control interface need to be aware that there is no hold time check in smarttime for the following signals: varefsel, tvc, stc, mode, chnumber. users need to ensure these signals remain stable for at least one clock cycle after the assertion of adcstart (see figure 11-12 ) and the simulation model provides a check to ensure this requirement is met. analog configuration mux (acm) the acm is an interface between fpga/jtag test registers and analog quad configuration latches, and the real-time counter (rtc). the analog block consists of four 8-bit la tches per analog quad, which get initialized through the acm. these latc hes act as configuration bits for analog quads. the analog system soft ip generated from libero ide configures the acm la tches automatically. if the user does not use the soft ip, the acm can be configured manually. fo r more information, refer to the analog configuration mux (acm) initialization in the interfacing with the fusion analog system: processor/micr ocontroller interface chapter. the acm block ru ns off the core voltage supply (1.5 v). table 11-5 ? settling time for usin g the internal vare f reference voltage capacitor value (f) settling time (ms) 3.3 116.45 10.0 324.73 22.0 750.24 figure 11-12 ? adcstart timing diagram s y sc lk ad cs tart varef s el/tv c / s t c / mode/ c hnumber
interfacing with the fusion analog system: ip interface v1.2 11-19 sample code the following sample vhdl code is used to read out the adc conversion results from either the assc ram or the smev ram. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ram_reader is port ( clk : in std_logic; -- clk nreset : in std_logic; -- active low reset asscdone : in std_logic; evdata : in std_logic_vector( 8 downto 0 ); evbusy : in std_logic; evaddr : out std_logic_vector( 8 downto 0 ); evrd : out std_logic; avgdata : out std_logic_vector( 11 downto 0 ) ); end ram_reader; architecture ctrl of ram_reader is -- constants for acm addresses constant ev_avg_data1 : std_logic_vector( 8 downto 0 ) := "001001011"; --75d constant ev_avg_data2 : std_logic_vector( 8 downto 0 ) := "001001100"; --76d -- state machine type fsm_type is ( idle, rdwait, rd1, rd2 ); signal state : fsm_type; -- internal registers to hold match values signal avgdata_reg : std_logic_vector( 11 downto 0 ); -- internal signals signal evrd_i : std_logic; signal evaddr_i : std_logic_vector( 8 downto 0 ); signal ev_d1en, ev_d2en : std_logic; begin -- toplevel port maps evaddr <= evaddr_i; evrd <= evrd_i; avgdata <= avgdata_reg; ------------------------------------------------------------------------------- -- ev avg data register ------------------------------------------------------------------------------- process(clk, nreset) begin if nreset = '0' then avgdata_reg <= (others=>'0') ;
interfacing with the fusion an alog system: ip interface 11-20 v1.2 elsif rising_edge(clk) then if ( ev_d1en = '1' ) then avgdata_reg( 8 downto 0 ) <= evdata( 8 downto 0 ); else avgdata_reg( 8 downto 0 ) <= avgdata_reg( 8 downto 0); end if; if ( ev_d2en = '1' ) then avgdata_reg( 11 downto 9 ) <= evdata( 2 downto 0 ); else avgdata_reg( 11 downto 9 ) <= avgdata_reg( 11 downto 9 ); end if; end if; end process; ------------------------------------------------------------------------------- -- main state machine ------------------------------------------------------------------------------- process(clk, nreset) begin if nreset = '0' then evaddr_i <= "000000000"; evrd_i <= '0'; ev_d1en <= '0'; ev_d2en <= '0'; state <= idle ; elsif rising_edge(clk) then case state is when idle => ev_d2en <= '0'; if ( asscdone = '1' ) then state <= rdwait; else state <= idle; end if; when rdwait => if ( evbusy = '0' ) then evaddr_i <= ev_avg_data1; evrd_i <= '1'; state <= rd1; end if; when rd1 => if ( evbusy = '1' ) then state <= rdwait; else evaddr_i <= ev_avg_data2; ev_d1en <= '1'; evrd_i <= '1'; state <= rd2; end if; when rd2 => if ( evbusy = '1' ) then state <= rd1; else evaddr_i <= "000000000"; evrd_i <= '0'; ev_d1en <= '0'; ev_d2en <= '1'; state <= idle; end if; when others => state <= idle; end case; end if;
interfacing with the fusion analog system: ip interface v1.2 11-21 end process; end ctrl; the following vhdl code is used to translate the adc result back to a voltage, current, or temperature value. scale: process (reset_n, clock) begin if reset_n = '0' then scaled_input <= (others => '0'); elsif clock'event and clock = '1' then case format_select is when "voltage" => -- 8v full scale, display volts -- need to multiply adc counts x2 scaled_input <= "000" & counts_in & '0'; when "temperature" => -- drop two lsbs to read in deg k scaled_input <= "000000" & counts_in_int_int(11 downto 2); when others => null; end case; end if; end process; note: for the current conversion, the adc result is the differential voltage value across the current sense resistor. to get the final current value, di vide the differential voltage value by the sense resistor value. part number and revision date part number 51700092-007-3 revised november 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.2) page v1.1 (september 2008) eq 11-1 was revised to correctly subscr ipt portions of variable names. 11-12 51700092-007-1 modified adc_r esult[11:0] description. 11-7 51700092-007-0 added "varef capacitor value selection" section . 11-18

v1.0 12-1 12 ? temperature, voltage, and current calibration in fusion fpgas introduction actel fusion ? mixed-signal fpgas integrate configur able analog features, including i/os, prescalers, low-pass filters, and an analog-to-digital conve rter (adc), enabling customers to perform temperature, voltage, and current measurements in their applications. analog components have a specific accuracy for a given set of conditions. the accuracy can have a broad range of definitions and is affected by many parameters in the system. for example, in a temperature measurement applicatio n, the accuracy of the measured temperature is influenced by the accuracy of on-chip elements (temperature sensor, op amps, and adc), use mode l (sample rate, adc resolution setting, post-proces sing, etc.), and board-level considerations. for the purpose of this document, accuracy can be defined as the difference/error between th e actual value and the measured value. for example, in a temperature measurement application, an accuracy of 2c means that the measured value may be up to 2c different from the actual value. if the difference between the measured value and the actual value is too great, you can use calibration to bring the measured value closer to the actual value. calibration assumes a profile for the relationship between the actual value and th e measured value. this profile depends on the characteristics of the components used in the measurement. there are two calibration profiles: one corrects for offset error only, and the second accounts for bo th offset and gain errors. figure 12-1 illustrates these typical profil es that define the calibration implementation methodology. to completely calibrate a system, users can calibra te individual components, or they can calibrate the entire system, taking into account the error of all the individual components working together. many users may decide to perform both levels of calibration. this document provides a description of the factory calibration methodology for voltage inputs on fusion devices, and also provides recommendations on system cali bration methods for voltage, te mperature, and current using fusion. using actel?s device calibration solution , the fusion adc samplin g accuracy for voltage prescalar inputs can be improv ed to 1%, enabling fusion to better meet customers' design requirements. figure 12-1 ? example profiles of measured va lue and actual value variations offset error only i d eal offset an d g ain error a c tual measure d
temperature, voltage, and curren t calibration in fusion fpgas 12-2 v1.0 general calibration concept calibration methods based on the measured-versus-actual profile and the required accuracy, customers can define the most efficient method for translating the measured value into an actual value. in most analog components, including the fusion fpga, the relationship betwee n measured and actual values follows the profiles illustrated in figure 12-1 on page 12-1 . this document describes only calibration methodologies asso ciated with offset-only and offset-and-gain corrections. offset-only calibration offset-only calibration (sometimes known as one- point calibration) is ba sed on the relationship between the measured and actual values given in eq 12-1 : y = x + c eq 12-1 where as shown by eq 12-1 , offset-only calibration accounts fo r the offset between the actual and measured values. offset-and-gain calibration if the correlation between the actual and measured values is defined primarily by an offset, as shown in the offset error line in figure 12-1 on page 12-1 , or if the actual measured value is naturally constrained to a specific region, offset-only calibration ma y be sufficient to achieve a high degree of accuracy. however, in some cases, especially if the range of the meas urement varies widely, the difference between the actual and measured values not only in cludes an offset but is also governed by a gain variation, as shown in figure 12-1 on page 12-1 . in such cases, offset -only calibration may not provide sufficient correction to achieve the accuracy required by the customer's application. in this case, offset-and-gain calibration (also known as two-point calibration) can be implemented to achieve a higher level of accuracy. in two-point calibration, the rela tionship between the measured an d actual values is governed by eq 12-2 : y = mx + c eq 12-2 where choosing between one-point calibration and two- point calibration depend s on many parameters, some of which incl ude the following: ? customer application's required accuracy ? measurement gain and offset error of electr ical components, such as the fusion fpga ? application's operating range y=actual value x = measured value c = offset compensation between measured and actual values y = actual value x = measured value c = offset compensation between measured and actual values m = gain compensation between measured and actual values
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-3 customer application's required accuracy given the required accuracy of an application wi thin its operating range, designers can use the specified gain and offset error of fusion fpgas to determine the suitable calibration method to achieve the desired accuracy. refer to the fusion family of mi xed-signal flash fpgas datasheet for more information. calibration measurements to calculate m or c in eq 12-1 and eq 12-2 on page 12-2 , measurements must be taken in a known environment so measured data can be compared against actual values. the number of required data points depends on the meth od of calibration. one data point would suffice for one-point calibration (determining offset), whereas for two- point calibration, two da ta points are needed to define gain and offset. in calibration measurem ents, a known actual value (temperature, current, or voltage) is supplied to the system, and the measured value is recorded. offset-only calibration measurement in offset-only (or one-point) calibratio n measurement, an actual value of p a1 (e.g., temperature) is applied to the system, and i ts value is measured as p m1 by the system. then, the offset value c in figure 12-1 on page 12-2 can be calculated as shown in eq 12-3 . c = y1 ? x1 eq 12-3 offset-and-gain (two-point ) calibration measurement as shown in figure 12-2 , to calculate m and c in eq 12-2 on page 12-2 , two data points are needed for two-point calibration. figure 12-2 ? two-point calibration fo r offset-and-gain error p a1 p a2 i d eal ad c result p m1 p m2 analo g input output value
temperature, voltage, and curren t calibration in fusion fpgas 12-4 v1.0 therefore, two know n actual values (y 1 and y 2 ) must be applied to the system, and two measured points (x 1 and x 2 ) must be recorded. the m and c values in eq 12-2 on page 12-2 are calculated as shown in eq 12-4 and eq 12-5 . m = (y 2 ? y 1 ) / (x 2 ? x 1 ) eq 12-4 c = (y 1 x 2 ? y 2 x 1 ) / (x 2 ? x 1 ) eq 12-5 choosing calibration data points in one-point calibration, from a practical point of view, actel recommends that the applied actual value be in the middle of the operating range as defined by the application. for example, if the system measures a voltage that operates from 0 v to 5 v, taking the calibration measurement at ~2.5 v will typically give the best results. for two-point calibration measurem ent, actel recommends that th e two data points be taken at 20% and 80% of the operation range. for exampl e, if a temperature measurement application is used in a system that operates from 0c to 50c, actel recommends that the calibration measurements be taken at 10c and 40c. in many voltage or current moni toring applications where the oper ating range includes 0 v or 0 a, customers tend to ch oose 0 v or 0 a as one of their calibr ation measurement data points. this is mainly driven by the simplicity of setup for measurements at the ground level. however, the ground level of the system is ty pically noisy due to the operatio n of the system and other noise factors. in such situations, th e calibration measurement may not be sufficient to achieve the accuracy level required by the overall design . therefore, actel recommends that zero-level measurements be avoided for voltage and current calibration data collection. actel fusion fpgas offer up to 32 analog chan nels for temperature, current, or voltage measurements. many applications, such as system management, use more than one analog channel in their design. though all these channels use a single adc inside fusion, each prescaler circuit within the analog i/o struc ture has a unique set of op amp circ uits. therefore, it is necessary to calibrate each channel that requires the increased level of accuracy independently. in this case, each channel has its own calibration coefficient based on the method used for calibration (one- point or two-point). furthermore, in an analog (voltage/current/tem perature) measurement, application designers exploit other components besides the fusion fpga to sense, transport, or amplify the measured parameters. customers can use two general approa ches in calibrating these systems: 1. calibrate each device used in the measurement individually. 2. calibrate all the utilized devices wh en operating together in the system. in the first approach, the customer calibrates each device individu ally in a controlled setting. in this case, the methods and recommendati ons explained in this document are applicable for the fusion device. for other components, the customer should follow the recommendations and techniques provided by the vendor of each component. in the second approach, all th e system components in the appl ication are used to take the calibration data points. in this case, the total m easurement error can be adjusted by calibrating the measured values after the adc. if this method is used, all the recommendations and techniques in this document can be applied.
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-5 actel calibration solution actel's device-level calibration so lution offers sign ificant improvement in adc accuracy for voltage monitor applications. there are two ways of exer cising the fusion adc for voltage monitoring: sampling prescaled analog input or sampling direct analog input. if a customer design requires better accuracy than the default fusion adc perfo rmance, then calibration is needed. since direct analog input sampling accuracy is well within 1%, the actel calibration solution does not offer any additional benefit, so it is on ly available for prescaled inputs. temperature and current monitor calibratio n are not supported. the actel calibration solution is a two-po int offset-and-gain ca libration scheme. the implementation is performed thro ugh the following two steps: 1. during production test and screening flows, m and c compensation values are determined for each analog voltage channel and stored in th e flash memory block of each fusion device. 2. in actel libero ? integrated design environment (ide) v8 .2 sp1 and later, an rtl calibration ip block is built into the smartgen fusion an alog system builder core. this calibration block reads the m and c values stored in the flash memory and uses them to calibrate data for each analog vo ltage channel. coefficient measurement and programming during the fusion production test flow, in a contro lled environment, actel measures the calibration coefficients, m and c, of every prescaler level of all 30 channels of each device. measurements are done with the fusion adc varef set to 2.56 v. in other words, the coefficients do not apply to any customer designs that use a varef other than 2.56 v. actel calibrat ion implementation is disabled in software when varef is set to another value. then coefficients are programmed into the dedicate d spare page of fusion flash memory block (fb) 0 (afs600 has blocks 0 and 1), from page 50 to 62. customers should avoid overwriting these spare pages. an old design generated prior to libero ide v8.2 sp1 utilizes these spare pages for analog system configuration data. programming an old design to a calibrated device could overwrit e these spare pages and corrupt the coefficients. calibration coefficients of that device would then no longer be available. on the other hand, programming a design with a calibration block generated from libero ide v8.2 sp1 or newer to an uncalibrated device will result in erroneous data from the adc. to avoid this, customers can pre-program the device with the po pulation.stp file provided in the libero ide v8.2 sp1 release. this programming action po pulates the dedicated flash memory area for calibration with m = 1 and c = 0. then customers ca n program the device with the design stapl file. calibration ip deployment to implement actel's calibration solution, custome rs must generate a new analog system and flash memory system using libero ide v8.2 sp1 or newer. actel's calibration ip solution is not available for processor systems that use the coreai to interface to the analog block. analog system builder update through the analog system builder, customers have an option to deploy a calibration ip block named "calibip" into fusion desi gns. the calibip block is seam lessly inserted into the original analog system macro, as shown in figure 12-3 on page 12-6 . figure 12-3 on page 12-6 shows only
temperature, voltage, and curren t calibration in fusion fpgas 12-6 v1.0 the insertion into a full analog system; the same concept applies to the sequence only (without smev and smtr stages) and adc only (wit hout assc, smev, and smtr stages) flows. during power-up, the initialization state machine, init/config ip, loads the coefficients from the flash memory block into a dedicated sram block fo r the calibip core. calibip reads the coefficients from the sram block and applies the m and c values to the raw adcresult, following eq 12-2 on page 12-2 to generate the calibrated adcresult. th e calibrated adcresult then goes through the rest of the process as in the original processing flow. there are two new ports created at the analog block top level to support calibration initialization from the flash memory block: ? init_calibrom_wen ? write enable to rom region, single-bit, active-high ? init_calibcoeff_wen ? write enable to co efficient region, sing le-bit, active-high these are write enables for the init/config interfa ce. connect them to corresponding ports of the flash memory block top level, as shown in figure 12-4 on page 12-7 . figure 12-3 ? full analog system macro with calibip ab c ali b ip a ssc ram s mev ram s mtr ram interfa c e analo g ports a ssc external tri gg er interfa c e a ssc s tatus fla g s ad c re s ult bu s y datavalid ad c re s ult bu s y datavalid c hnumber ad cs tart
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-7 flash memory syste m builder update inside the flash memory system builder (fmsb), customers can generate an analog client to properly initialize the analog system macro with calibip deployed. in addition to the regular analog system configuration data partition, fmsb also creates two other partitions for the analog client: one for the coefficients? storage (calibcoefficien t), from spare page 50 to 62, and one for a lookup table (calibrom) that records which chan nel and prescaler level ne ed to be calibrated, from spare page 43 to 48. because of the new calibration coefficients? sto rage partition, the smtr configuration data is assigned to flash memory block sector 63, from pa ge 2,016 through 2,047 (o r as addresses: 0x3f000 through 0x3ff80). smtr uses up to 32 pages. th e actual number of pages used in this sector depends on whether (and how many) flags are used in the analog sy stem design. the flash memory system builder prevents customers from assigning any other clie nts to these pages. the flash memory maps prior to and after the libero ide v8 .2 sp1 release are shown in figure 12-5 and figure 12-6 on page 12-9 . figure 12-4 ? connectivity between analog system block and flash memory block
temperature, voltage, and curren t calibration in fusion fpgas 12-8 v1.0 figure 12-5 ? flash memory map prior to libero ide v8.2 sp1 s po re s erved s p1 a c m s p2 rt c (only if rt c c onfi g ure d ) s p3 s p4 s e c tor 0 s e c tor 1 s e c tor 2 s e c tor 6 0 s e c tor 6 1 s e c tor 6 2 s e c tor 6 3 s p10 s p11 s p41 s p42 s p43 s p 6 1 s p 6 2 s p 6 3 c ore c fi flash memory blo c k = 6 4 s e c tors s e c tor = 32 pa g es an d 1 s pare pa g e a ssc (fixe d at 8 pa g es) s mev (varia b le, d epen d ent on num b er of fla g s) s mtr (varia b le, d epen d ent on num b er of fla g s) s pare pa g e user area
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-9 there are two new ports created at the flash me mory block top level, corresponding to those created for the analog block: ? init_calibrom_wen ? init_calibcoeff_wen connect these ports to th e analog block top level. figure 12-6 ? flash memory map after libero ide v8.2 sp1 s po re s erved s p1 a c m s p2 rt c (only if rt c c onfi g ure d ) s p3 s p4 s e c tor 0 s e c tor 1 s e c tor 2 s e c tor 6 0 s e c tor 6 1 s e c tor 6 2 s e c tor 6 3 s p10 s p11 s p41 s p42 s p43 s p48 s p49 s p50 s p 6 1 s p 6 2 s p 6 3 c ore c fi s mtr (varia b le, d epen d ent, on num b er of fla g s) flash memory blo c k = 6 4 s e c tors s e c tor = 32 pa g es an d 1 s pare pa g e a ssc (fixe d at 8 pa g es) s mev (varia b le, d epen d ent on num b er of fla g s) c alibrom (fixe d at 6 pa g es) c alib c oeffi c ient s pare pa g e user area
temperature, voltage, and curren t calibration in fusion fpgas 12-10 v1.0 design flow and tips for calibrated fusion de vices, there are several implementation scenarios. scenario 1: brand new design follow the regular design flow to implement th e actel calibration solution in a new design: by default, the calibration ip is enabled in the analog system ma cro, and the flash memory block initializes the ip. the designer software places the corresponding analog client in flash memory block 0. the content of the memory file (* .mem) is different from that of the embedded flash configuration file (*.efc). the *.mem file pr oduced by the flash memory buil der for simulation purposes is populated with m = 1.0 and c = 0 for all channels and all prescaler combinations. calibip can function appropriately during simu lation. the *.efc file for programming file generation does not include the m and c content beca use the coefficients are pre-prog rammed into the device during production test. to disable the calibration ip, uncheck include calibration ip in the advanced options of the analog system builder, as shown in figure 12-7 . for a calibration-enabled design, when bypass calibration on saturated adc input is selected, the saturated adc result is passed to the next level of computation without calibration. if unchecked, the saturated adc result is calibrated before it is passed to the next level. figure 12-7 ? disable calibip from advanced options (libero ide v8.2 sp1)
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-11 scenario 2: update existing design to impl ement calibration solution to update existing fusion designs and utilize the actel calibration solu tion, take th e following steps to regenerate the design: 1. open the design in libero ide v8.2 sp1 or newer. 2. regenerate the analog system macro in analog system builder. open advanced options , select the include calibration ip option, then regenerate the macro. 3. regenerate the flash memory block. 4. make sure the addi tional ports (ini t_calibrom_wen and init_calibcoeff_wen) are properly connected, either through smartdesign ( figure 12-8 ) or hdl coding. go through the rest of the regular design flow (synthesis, compile, and layout with proper simulation and timing analysis). figure 12-8 ? smartdesign connectivity grid in libero v8.2 sp1
temperature, voltage, and curren t calibration in fusion fpgas 12-12 v1.0 scenario 3: existing design for firmware image update only to update the firmware image in the existing design without us ing the calibration ip, regenerate the flash memory block. then go through the rest of design flow (synthes is, compile, and layout with proper simulation and timing analysis). scenario 4: maintain existing desi gn in new software release without using calibrat ion solution actel recommends that all customers regenerate the analog system bloc k and the flash memory block in libero ide v8.2 sp1 or newer software releases, unless the analog system block utilizes less than 20 channels and less th an four flags per channel. programming a calibrated device with designs gene rated prior to libero ide v8.2 sp1 can overwrite and corrupt the pre-prog rammed coefficient data in the de dicated flash memo ry partition. the flashpro software released with libero ide v8.2 sp1 detects whether there is a memory map overlap. if there is a memory overlap, flashpro cancels the programming acti on and asks the user to regenerate the analog system. to program a design with calibration implemented to a targeted device that is uncalibrated, pre- program the device with the po pulation.stp file provided by actel. this programming action populates the dedicated flash memo ry area for calibration with m = 1 and c = 0. then program the device with the de sign stapl file. utilization and performance the total ram block and core ti le utilization to implement calibip and the corresponding initialization proc ess is listed in table 12-1 . calibip and other ips infer registers with enable. when these registers have a set or rese t signal, assign the set or reset signal to a global resource to make sure that the register remains a one-tile implementation (not split into two tiles). the calibip performance is listed in table 12-2 . the performance of calibip is only limited by th e latency introduced by the compute block. the compute block adds a latency of 14 clock cycles. for example, 14 clock cycles of a 40 mhz system clock is 0.35 microseconds. with calibration im plemented, you can expect the adc result 0.35 microseconds later than in a design without ca libration implementation . the sampling rate is degraded by 2%. table 12-1 ? calibration implementation utilization report ram block tile count for calibip optimized for area optimized for speed 1 363 453 table 12-2 ? calibip performance report speed grade calibip performance (mhz) optimized for area optimized for speed std. 45 57 ?2 75 96
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-13 improvement from actel calibration solution table 12-3 shows typical error using ac tel's calibration solution. microprocessor-based design flow in a microprocessor-based design flow, designers can use coreai (analog interface) to interface and control the analog peripherals within the fusi on device family. designers using core8051, coremp7, or cortex?-m1 with coreai can take advantage of the coreai driver (provided in c code) to support the calibration features. the coreai driver provides a set of applicatio n program interface (api) functions to support different calibration modes and au tomatically calculate the final ca librated value, based on the m and c coefficient stored in the spare page of th e fusion flash memory block. currently, the calibration scheme only supports vo ltage monitor applications (avx pins) and is only needed for prescaled voltage inputs . if direct analog input sampling accuracy is well within 1%, the actel calibration solution does no t offer any additional benefits. co reai driver must be used with coreai version 2.1 (or higher ) and coreahbnvm version 1.3. 135 (or higher). refer to the coreai driver user's guide for more information. performing system-level calibration using fusion previous sections of this document describe the general approach to cali bration using the offset- only and offset-plus-gain approaches, and provided a detailed explanation of actel?s calibration solution for fu sion voltage input signals. in addition to this solution, users ma y desire calibration of temperature and current inputs, as well as calibr ation of the entire system working together. a recommended approach to accomplishin g these tasks is provided be low. this methodology may be added in the user?s design on top of the device-level calibration solution. table 12-3 ? fusion analog system typical error with calibip deployed input voltage (v) calibrated typical error per positive prescaler setting 1 (%) direct adc 2, 3 (%) 16 v (at) 16 v (12 v) (av/ac) 8 v (av/ac) 4 v (at) 4 v (av/ac) 2 v (av/ac) 1 v (av/ac) varef = 2.56 v 15 1 14 1 12 1 1 5221 3.3 2 2 111 2.5 3 2 111 1 1.8 4 4 1111 1 1.5 5 5 2221 1 1.2 7 6 2221 1 0.9 9 9 443111 notes: 1. requires enabling analog calibr ation in the actel tool flow. 2. direct adc mode using an external varef of 2.56v4.6mv, without analog calibration macro. 3. for input greater than 2.56 v, the adc output w ill saturate. a higher v aref or prescaler usage is recommended.
temperature, voltage, and curren t calibration in fusion fpgas 12-14 v1.0 the "calibration measurements" section on page 12-3 explains how the calibration coefficients, as described in eq 12-1 and eq 12-2 on page 12-2 , are calculated. eq 12-1 and eq 12-2 on page 12-2 (depending on the calibration method used) are implemented using an adder (one-point calibration) or a combination of an adder and a multiplier (two-point ca libration), as shown in figure 12-9 . the calibration coefficients (m and c in figure 12-9 ) can be stored in the nonvolatile flash memory of each fusion device. therefore, inside the flas h memory architecture, different memory addresses can contain the calibration coef ficients for each channel in the design. depending on which channel in the design is perf orming the measurement at the time, appropriate calibration coefficients can be fetched and fe d into the adder and/or multipli er. for details on writing and reading to the fusion flash memo ry block, refer to the embedded flash memory chapter of the fusion handbook . where and how the adder and mult iplier are implemented depends highly on the application and the user's design. generally, there are three ways designers can implement the arithmetic functions in figure 12-9 to produce the calibrated results of measurement. the following explains each of these implementations an d their pros and cons: implementing a dedicated adder and multiplier using fpga core gates pros ?high speed ? efficient for one-point calibration cons ? multiplier implementation cons umes large number of gates using the design?s micr oprocessor/microcontro ller alu to perform calibration calculations pros ? saves fpga gate resources compared to implementing dedicated multiplier cons ? may slow down microprocessor's performanc e depending on the overall sampling rate implementing the numerical calcul ations in appl ication software pros ? saves fpga gates cons ? depending on the applic ation, may take up a lot of ba ndwidth from the host processor ? only suitable for ap plications where there is softw are communicating with hardware figure 12-9 ? implementation of one-poin t and two-point calibration measure d value c ali b rate d result c (offset) (a) one-point c ali b ration measure d value c ali b rate d result c (offset) ( b ) two-point c ali b ration g ( g ain)
temperature, voltage, and curr ent calibration in fusion fpgas v1.0 12-15 conclusion designers use calibration to increase the accuracy achievable in applications involving analog components. actel fusion mixed-signal fpgas offe r the capability of measuring analog voltage, current, and temperature. if custo mers require more accuracy than is inherent in fusion fpgas, calibration techniques can be used to achiev e these requirements. fusion fpgas offer the advantage of having the calibration design an d coefficients programmed into the fpga itself without a need for any external components. this do cument discusses the typical calibration techniques and the implementation of actel ca libration solutions for fusion fpgas. the result shows that with the actel calib ration implementation , customers can achieve 1% adc sampling accuracy for all fusion devices and all channels. related documents datasheets fusion family of mi xed-signal flash fpgas http://www.actel.com/documents/fusion_ds.pdf handbooks fusion handbook http://www.actel.com/documents/fusion_hb.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700092-019-0 revised october 2008
temperature, voltage, and curren t calibration in fusion fpgas 12-16 v1.0 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.0) page 51900161-3/6.08 the "microprocessor-based design flow" section was added. 12-13 51900161-1/2.08 this statement was added to the "calibration ip deployment" section: actel's calibration ip soluti on is not available for processor systems that use the coreai to interface to the analog block. 12-5 in the "performing system-level ca libration using fusion" section, a reference to the fusion handbook was added. 12-13 51900161-0/2.07 please read th e document very carefully. a lot of helpful and useful information was adde d to the document. n/a the "introductio n" section was updated. 12-1 the heading title "calibration meas urements" section is new and all subsections were significantly updated. please note the variables in all equations were changed. in addition, the variab le g was changed to m throughout the document. 12-3 the "actel calibration solution" section and all subsections are new. 12-5 the heading title "implementing ca libration design" was changed to "performing system-level calibration using fusion" section . in figure 12-9 ?implementation of one-point and two-point calibration , the m was changed to g. 12-13
i/o descriptions and usage

v1.4 13-1 13 ? i/o software control in low-power flash devices actel fusion, ? igloo, ? and proasic ? 3 i/os provide more design flexibility, allowing the user to control specific features by enabling certain i/o standards. some features are selectable only for certain i/o standards, whereas others are available fo r all i/o standards. for example, slew control is not supported by differential i/o standards. conve rsely, i/o register combinin g is supported by all i/o standards. for detailed information about whic h i/o standards and features are available on each device and each i/o type, refer to the i/o structures sectio n of the handbook for the device you are using. figure 13-1 shows the various points in the software design flow where a user can provide input or control of the i/o selection and parameters. a de tailed description is provided throughout this document. figure 13-1 ? user i/o assignment flow chart design entry 1. i/o macro using smartgen 2. i/o buffer cell schematic entry 3. instantiating i/o library macro in hdl code 4. generic buffer using 1, 2, 3 method 5. synthesis 6. compile 6.1 i/o assignments by pdc import 7. i/o assignments by multi-view navigator (mvn) i/o standard selection for generic i/o macro i/o standards and v ref assignment by i/o bank assigner i/o attribute selection for i/o standards 8. layout and other steps
i/o software control in low-power flash devices 13-2 v1.4 flash fpgas i/o support the flash fpgas listed in table 13-1 support i/os and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 13-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 13-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 13-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
i/o software control in low-power flash devices v1.4 13-3 software-controlled i/o attributes users may modify these programmable i/o attribut es using the i/o attribute editor. modifying an i/o attribute may result in a change of state in designer. table 13-2 details which steps have to be re-run as a function of modified i/o attribute. table 13-2 ? designer state (resulting from i/o attribute modification) i/o attribute designer states compile layout fuse timing power slew control no no yes yes yes output drive (ma) no no yes yes yes skew control no no yes yes yes resistor pull no no yes yes yes input delay no no yes yes yes schmitt trigger no no yes yes yes out_load no no no yes yes combine_register yes yes n/a n/a n/a notes: 1. no = remains the same, yes = re-r un the step, n/a = not applicable 2. skew control and input delay do not apply to igloo nano, igloo pl us, and proasic3 nano devices.
i/o software control in low-power flash devices 13-4 v1.4 implementing i/os in actel software actel libero ? integrated design environmen t (ide) is integrated with de sign entry tools such as the smartgen macro builder, the viewdraw schemati c entry tool, and an hdl editor. it is also integrated with the synthesis and designer tools. in this section, all necessary steps to implement the i/os are discussed. design entry there are three ways to implement i/os in a design: 1. use the smartgen macro builder to configure i/os by generating specific i/o library macros and then instantiating th em in top-level code. this is especially useful when creating i/o bus structures. 2. use an i/o buffer cell in a schematic design. 3. manually instantiate specific i/o macros in the top-level code. if technology-specific macros, su ch as inbuf_lvcmos33 and outbu f_pci, are used in the hdl code or schematic, the user will not be able to change the i/ o standard later on in designer. if generic i/o macros are used, such as inbuf, outbuf, tribuf, clkbuf, and bibu f, the user can change the i/o standard using the designer i/o attribute editor tool. using smartgen for i/o configuration the smartgen tool in libero id e provides a gui-based method of configuring the i/o attributes. the user can select certain i/o attributes while co nfiguring the i/o macro in smartgen. the steps to configure an i/o macro with specif ic i/o attributes are as follows: 1. open libero ide. 2. on the left-hand side of the catalog view, select i/o , as shown in figure 13-2 . figure 13-2 ? smartgen catalog
i/o software control in low-power flash devices v1.4 13-5 3. expand the i/o section and do uble-click one of the options ( figure 13-3 ). 4. double-click any of the varieties. the i/o create core window opens ( figure 13-4 ). as seen in figure 13-4 , there are five tabs to configure the i/o macro: input buffers, output buffers, bidirectional buffers, tristate buffers, and ddr. input buffers there are two variations : regular and special. if the regular variation is selected, only the width (1 to 128) needs to be entered. the default value for width is 1. the special variation has width, technology, voltage level, and resistor pull-up/-down options (see figure 13-4 ). all the i/o standards and supply voltages (v cci ) supported for the device family are available for selection. figure 13-3 ? expanded i/o section figure 13-4 ? i/o create core window
i/o software control in low-power flash devices 13-6 v1.4 output buffers there are two variations : regular and special. if the regular variation is selected, only the width (1 to 128) needs to be entered. the default value for width is 1. the special variation has width, technology, output drive, and slew rate options. bidirectional buffers there are two variations : regular and special. the regular variation has enable polarity (active hi gh, active low) in addition to the width option. the special variation has width, technology, output dr ive, slew rate, and resistor pull-up/-down options. tristate buffers same as bidirectional buffers. ddr there are eight variations: ddr wi th regular input buffers, specia l input buffers, regular output buffers, special output buffers, regular trista te buffers, special tristate buffers, regular bidirectional buffers, and special bidirectional buffers. these variations resemble the options of the previous i/o ma cro. for example, the special input buffers variation has width, technology, voltage level, and resistor pull-up/-down options. ddr is not available on igloo plus devices. 5. once the desired configuration is selected, click the generate button. the generate core window opens ( figure 13-5 ). 6. enter a name for the macro. click ok . the core will be generated and saved to the appropriate location with in the project files ( figure 13-6 on page 13-7 ). 7. instantiate the i/o macr o in the top-level code. the user must instantiate the ddr_reg or dd r_out macro in the design. use smartgen to generate both these macros and then instantia te them in your top level. to combine the ddr macros with the i/o, th e following rules must be met: figure 13-5 ? generate core window
i/o software control in low-power flash devices v1.4 13-7 rules for the ddr i/o function ? the fanout between an i/o pin (d or y) and a ddr (ddr_reg or ddr_out) macro must be equal to one for th e combining to happen on that pin. ? if a ddr_reg macro and a ddr_out macro are combined on the same bidirectional i/o, they must share the same clear signal. ? registers will not be combined in an i/o in the presence of ddr combining on the same i/o. using the i/o buffe r schematic cell libero ide includes the viewdraw schematic entry too l. using viewdraw, the user can insert any supported i/o buffer cell in the top-level schematic. figure 13-6 shows a top-level schematic with different i/o buffer cells. when synthesized, the netlist will contain the same i/o macro. figure 13-6 ? i/o buffer schematic cell usage
i/o software control in low-power flash devices 13-8 v1.4 instantiating in hdl code all the supported i/o macros can be instantiat ed in the top-level hdl code (refer to the igloo, fusion, and proasic3 macro library guide for a detailed list of all i/o macros). the following is an example: library ieee; use ieee.std_logic_1164.all; library proasic3e; entity top is port(in2, in1 : in std_logic; out1 : out std_logic); end top; architecture def_arch of top is component inbuf_lvcmos5u port(pad : in std_logic := 'u'; y : out std_logic); end component; component inbuf_lvcmos5 port(pad : in std_logic := 'u'; y : out std_logic); end component; component outbuf_sstl3_ii port(d : in std_logic := 'u'; pad : out std_logic); end component; other component ?.. signal x, y, z??.other signals : std_logic; begin i1 : inbuf_lvcmos5u port map(pad => in1, y =>x); i2 : inbuf_lvcmos5 port map(pad => in2, y => y); i3 : outbuf_sstl3_ii port map(d => z, pad => out1); other port mapping? end def_arch; synthesizing the design libero ide integrates with the synplify ? synthesis tool. other synthesis tools can also be used with libero ide. refer to the actel libero ide user?s guide or libero ide online help for details on how to set up the libero ide tool profile with synthesis tools from other vendors. during synthesis, the following rules apply: ? generic macros: ? users can instantiate generic inbuf, outbuf, tribuf, and bibuf macros. ? synthesis will automatically infer generic i/o macros. ? the default i/o technology for these macros is lvttl. ? users will need to use the i/ o attribute editor in design er to change the default i/o standard if needed (see figure 13-7 on page 13-9 ). ? technology-specific i/o macros: ? technology-specific i/o macros, such as inbuf_lvcmo25 and outbuf_gtl25, can be instantiated in the design. synthesis will infer these i/o macros in the netlist.
i/o software control in low-power flash devices v1.4 13-9 ? the i/o standard of technology-specific i/o macros cannot be changed in the i/o attribute editor (see figure 13-7 ). ? the user must instantiate differential i/o ma cros (lvds/lvpecl) in the design. this is the only way to use these standards in the design. ? to implement the ddr i/o function, the us er must instantiate a ddr_reg or ddr_out macro. this is the only way to use a ddr macro in the design. performing place-and- route on the design the netlist created by the synthe sis tool should now be import ed into designer and compiled. during compile, the user can specify the i/o plac ement and attributes by importing the pdc file. the user can also specify the i/o placement and at tributes using chipplanner and the i/o attribute editor under mvn. defining i/o assignments in the pdc file a pdc file is a tcl script file specifying physic al constraints. this file can be imported to and exported from designer. table 13-3 shows i/o assignment constrain ts supported in the pdc file. figure 13-7 ? assigning a different i/o standa rd to the generic i/o macro table 13-3 ? pdc i/o constraints command action example comment i/o banks setting constraints set_iobank sets the i/o supply voltage, v cci , and the input reference voltage, v ref , for the specified i/o bank. set_iobank bankname [-vcci vcci_voltage] [-vref vref_voltage] set_iobank bank7 -vcci 1.50 -vref 0.75 must use in case of mixed i/o voltage (v cci ) design set_vref assigns a v ref pin to a bank. set_vref -bank [bankname] [pinnum] set_vref -bank bank0 685 704 723 742 761 must use if voltage- referenced i/os are used note: refer to the actel libero ide user?s guide for detailed rules on pdc naming and syntax conventions.
i/o software control in low-power flash devices 13-10 v1.4 set_vref_defaults sets the default v ref pins for the specified bank. this command is ignored if the bank does not need a v ref pin. set_vref_defaults bankname set_vref_defaults bank2 i/o attribute constraint set_io sets the attributes of an i/o set_io portname [-pinname value] [-fixed value] [-iostd value] [-out_drive value] [-slew value] [-res_pull value] [-schmitt_trigger value] [-in_delay value] [-skew value] [-out_load value] [-register value] set_io in2 -pinname 28 -fixed yes -iostd lvcmos15 -out_drive 12 -slew high -res_pull none -schmitt_trigger off -in_delay off ?skew off -register no if the i/o macro is generic (e.g., inbuf) or technology- specific (inbuf_lvcmos25), then all i/o attributes can be assigned using this constraint. if the netlist has an i/o macro that specifies one of its attributes, that attribute cannot be changed using this constraint, though other attributes can be changed. example: outbuf_s_24 (low slew, output drive 24 ma) slew and output drive cannot be changed. i/o region plac ement constraints define_region defines either a rectangular region or a rectilinear region define_region -name [region_name] -type [region_type] x1 y1 x2 y2 define_region -name test -type inclusive 0 15 2 29 if any number of i/os must be assigned to a particular i/o region, such a region can be created with this constraint. assign_region assigns a set of macros to a specified region assign_region [region name] [macro_name...] assign_region test u12 this constraint assigns i/o macros to the i/o regions. when assigning an i/o macro, pdc naming conventions must be followed if the macro name contains special characters; e.g., if the macro name is \\$1i19\\, the correct use of escape characters is \\\\\$1i19\\\\. table 13-3 ? pdc i/o constraints (continued) command action example comment note: refer to the actel libero ide user?s guide for detailed rules on pdc naming and syntax conventions.
i/o software control in low-power flash devices v1.4 13-11 compiling the design during compile, a pdc i/o constraint file can be imported along with the netlist file. if only the netlist file is compiled, certain i/o assignments n eed to be completed before proceeding to layout. all constraints that can be entered in pdc can al so be entered using chipplanner, i/o attribute editor, and pineditor. there are certain rules that must be followed in implementing i/o register combining and the i/o ddr macro (refer to the i/o registers section of the handbook for the device that you are using and the "ddr" section on page 13-6 for details). provided these ru les are met, the user can enable or disable i/o register combin ing by using the pdc command set_io portname ?register yes|no in the i/o attribute editor or selecting a ch eck box in the compile options dialog box (see figure 13-8 ). the compile options dialog box appears when the design is compiled for the first time. it can also be accessed by choosing options > compile during successive runs. i/o register combining is off by default. the pdc command ov errides the setting in th e compile options dialog box. understanding the compile report the i/o bank report is generated during compile and displayed in the log window. this report lists the i/o assignments necessary before layout can proceed. when designer is started, the i/o bank assigner to ol is run automatically if the layout command is executed. the i/o bank assigner takes care of the necessary i/o assignments. however, these assignments can also be made manually with mv n or by importing the pdc file. refer to the "assigning technologies and v ref to i/o banks" section on page 13-14 for further description. the i/o bank report can also be extra cted from designer by choosing to o l s > report and setting the report type to iobank . this report has the following tables: i/o function , i/o technology, i/o bank resource usage, and i/o voltage usage. this report is useful if th e user wants to do i/o assignments manually. figure 13-8 ? setting register combining during compile
i/o software control in low-power flash devices 13-12 v1.4 i/o function figure 13-9 shows an example of the i/o function table included in the i/o bank report: this table lists the number of input i/os, output i/os, bidirectional i/os, and differential input and output i/o pairs that us e i/o and ddr registers. certain rules must be met to implement registe red and ddr i/o functions (refer to the i/o structures section of the handbook for the device you are using and the "ddr" section on page 13-6 ). i/o technology the i/o technology table (shown in figure 13-10 ) gives the values of v cci and v ref (reference voltage) for all the i/o standards used in the design. the user should assign these voltages appropriately. figure 13-9 ? i/o function table figure 13-10 ? i/o technology table
i/o software control in low-power flash devices v1.4 13-13 i/o bank res ource usage this is an important portion of the report. th e user must meet the requirements stated in this table. figure 13-11 shows the i/o bank resource usage table included in the i/o bank report: the example in figure 13-11 shows that none of the i/o macros is assigned to the bank because more than one v cci is detected. i/o voltage usage the i/o voltage usage table provides the number of v ref (e devices only) and v cci assignments required in the design. if the us er decides to make i/o assignme nts manually (pdc or mvn), the issues listed in this ta ble must be resolved be fore proceeding to layout. as stated earlier, v ref assignments must be made if there are any voltage-referenced i/os. figure 13-12 shows the i/o voltage usage table included in the i/o bank report. the table in figure 13-12 indicates that there are two voltage- referenced i/os used in the design. even though both of the voltage-referenc ed i/o technologies have the same v cci voltage, their v ref voltages are different. as a result, tw o i/o banks are needed to assign the v cci and v ref voltages. figure 13-11 ? i/o bank resource usage table figure 13-12 ? i/o voltage usage table
i/o software control in low-power flash devices 13-14 v1.4 in addition, there are six single-end ed i/os used that have the same v cci voltage. since two banks are already assigned with the same v cci voltage and there are enough unused bonded i/os in those banks, the user does not ne ed to assign the same v cci voltage to another ba nk. the user needs to assign the other three v cci voltages to three more banks. assigning technologies and v ref to i/o banks low-power flash devices offer a wide variety of i/o standards, includ ing voltage-referenced standards. before proceeding to layout, each bank must have the required v cci voltage assigned for the correspondin g i/o technologies used for that ba nk. the voltage-referenced standards require the use of a reference voltage (v ref ). this assignment can be done manually or automatically. the following sections describe this in detail. manually assigning technologies to i/o banks the user can import the pdc at this point an d resolve this requirem ent. the pdc command is set_iobank [bank name] ?vcci [vcci value] another method is to use the i/o bank settings dialog box ( mvn > edit > i/o bank settings ) to set up the v cci voltage for the bank ( figure 13-13 ). figure 13-13 ? setting v cci for a bank
i/o software control in low-power flash devices v1.4 13-15 the procedure is as follows: 1. select the bank to which you want v cci to be assigned from the choose bank list. 2. select the i/o standards for that bank. if you select any standard, the tool will automatically show all compatible standar ds that have a common v cci voltage requirement. 3. click apply . 4. repeat steps 1?3 to assign v cci voltages to other banks. refer to figure 13-12 on page 13-13 to find out how many i/o banks are needed for v cci bank assignment. manually assigning v ref pins voltage-referenced inputs require an input reference voltage (v ref ). the user must assign v ref pins before running layout. before assigning a v ref pin, the user must set a v ref technology for the bank to which the pin belongs. v ref rules for the implementation of voltage-referenced i/o standards the v ref rules are as follows: 1. any i/o (except jtag i/os) can be used as a v ref pin. 2. one v ref pin can support up to 15 i/os. it is re commended, but not required, that eight of them be on one side and seven on the other side (in other words, all 15 can still be on one side of v ref ). 3. sstl3 (i) and (ii): up to 40 i/os per north or south bank in any position 4. lvpecl / gtl+ 3.3 v / gtl 3.3 v: up to 48 i/os per north or south bank in any position 5. sstl2 (i) and (ii) / gtl+ 2.5 v / gtl 2.5 v: up to 72 i/os per north or south bank in any position 6. v ref minibanks partition rule: each i/o bank is physically partitioned into v ref minibanks. the v ref pins within a v ref minibank are interconnected internally, and consequently, only one v ref voltage can be used within each v ref minibank. if a bank does not require a v ref signal, the v ref pins of that bank are available as user i/os. 7. the first v ref minibank includes all i/os starting from one end of the bank to the first power triple and eight more i/os after the power triple . therefore, the first v ref minibank may contain (0 + 8), (2 + 8), (4 + 8 ), (6 + 8), or (8 + 8) i/os. the second v ref minibank is adjacent to the first v ref minibank and contains eight i/os, a power triple, and eight mo re i/os after the triple. an analogous rule applies to all other v ref minibanks but the last. the last v ref minibank is adjacent to the previous one but contains eight i/os, a power triple, and all i/os left at th e end of the bank. this bank may also contain (8 + 0), (8 + 2), (8 + 4), (8 + 6), or (8 + 8) available i/os. example: 4 i/os triple 8 i/os, 8 i/os triple 8 i/os, 8 i/os triple 2 i/os that is, minibank a = (4 + 8) i/os, minibank b = (8 + 8) i/os, minibank c = (8 + 2) i/os. assigning the v ref voltage to a bank when importing th e pdc file, the v ref voltage can be assigned to the i/o bank. the pdc command is as follows: set_iobank ?vref [value] another method for assigning v ref is by using mvn > edit > i/o bank settings ( figure 13-14 on page 13-16 ).
i/o software control in low-power flash devices 13-16 v1.4 assigning v ref pins for a bank the user can use default pins for v ref . in this case, select the use default pins for vrefs check box ( figure 13-14 ). this option guarantees full v ref coverage of the bank. the equivalent pdc command is as follows: set_vref_default [bank name] to be able to choose v ref pins, adequate v ref pins must be created to a llow legal placement of the compatible voltage-referenced i/os. to assign v ref pins manually, the pdc command is as follows: set_vref ?bank [bank name] [package pin numbers] for chipplanner/pineditor to show the range of a v ref pin, perform the following steps: 1. assign v cci to a bank using mvn > edit > i/o bank settings . 2. open chipplanner . zoom in on an i/o package pin in that bank. 3. highlight the pin and th en right-click. choose use pin for vref . figure 13-14 ? selecting v ref voltage for the i/o bank v ref for gtl+ 3.3 v
i/o software control in low-power flash devices v1.4 13-17 4. right-click and then choose highlight vref range . all the pins covered by that v ref pin will be highlighted ( figure 13-15 ). using pineditor or chipplanner, v ref pins can also be assigned ( figure 13-16 ). to unassign a v ref pin: 1. select the pin to unassign. 2. right-click and choose use pin for vref. the check mark next to the command disappears. the v ref pin is now a regular pin. resetting the pin may result in una ssigning i/o cores, even if they are locked. in this case, a warning message appears so you can cancel the operation. after you assign the v ref pins, right-click a v ref pin and choose highlight vref range to see how many i/os are covered by that pin. to unhighlight the range, choose unhighlight all from the edit menu. figure 13-15 ? v ref range figure 13-16 ? assigning v ref from pineditor
i/o software control in low-power flash devices 13-18 v1.4 automatically assigning technologies to i/o banks the i/o bank assigner (ioba) to ol runs automatically when you run layout. you can also use this tool from within the multiview navigator ( figure 13-18 ). the ioba tool au tomatically assigns technologies and v ref pins (if required) to every i/o bank that does not currently have any technologies assigned to it. this tool is avai lable when at least one i/o bank is unassigned. to automatically assign techno logies to i/o banks, choose i/o bank assigner from the to o l s menu (or click the i/o bank assigner's toolbar button, shown in figure 13-17 ). messages will appear in the output window informing you when the automatic i/o bank assignment begins and ends. if the assignment is successful, the message "i/o bank assigner completed successfully" appears in the output window, as shown in figure 13-18 . figure 13-17 ? i/o bank assigner?s toolbar button figure 13-18 ? i/o bank assigner displays messages in output window
i/o software control in low-power flash devices v1.4 13-19 if the assignment is not successful, an er ror message appears in the output window. to undo the i/o bank assignments, choose undo from the edit menu. undo removes the i/o technologies assigned by the ioba . it does not remove the i/o te chnologies previously assigned. to redo the changes undone by the undo command, choose redo from the edit menu. to clear i/o bank assignments made before using the undo command, manually unassign or reassign i/o technologies to banks. to do so, choose i/o bank settings from the edit menu to display the i/o bank settings dialog box. conclusion actel fusion, igloo, and proasic3 support for multiple i/o standards minimizes board-level components and makes po ssible a wide variety of applicatio ns. the actel designer software, integrated with actel libe ro ide, presents a clear visual displa y of i/o assignmen ts, allowing users to verify i/o and board-level design requiremen ts before programming the device. the device i/o features and functionalities en sure board designers can produce low-cost and low-power fpga applications fulfilling the complexiti es of contemporary design needs. related documents handbook documents ddr for actel?s low- power flash devices http://www.actel.com/documents/lpd_ddr_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglooe and proasic3e devices http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf power-up/-down behavior of low-power fl ash devices http://www.actel.com/docum ents/lpd_powerup_hbs.pdf proasic3/e sso and pin placement an d guidelines http://www.actel.c om/documents/pa 3_e_sso_hbs.pdf user?s guides actel libero ide user?s guide http://www.actel.com/documents/libero_ug.pdf igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf smartgen core reference guide http://www.actel.com/documents/genguide_ug.pdf
i/o software control in low-power flash devices 13-20 v1.4 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-026-3 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 13-1 flash- based fpgas . 13-2 the notes for table 13-2 designer state (resulting from i/o attribute modification) were revised to indicate that skew control and input delay do not apply to nano devices. 13-3 v1.2 (june 2008) the "flash fpgas i/o support" section was revised to include new families and make the information more concise. 13-2 v1.1 (march 2008) the following changes were made to the family descriptions in table 13-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 13-2 v1.0 (january 2008) this document was previously part of the i/o structures in igloo and proasic3 devices document. the content was se parated and made into a new document. n/a table 13-2 designer state (resulting from i/o attribute modification) was updated to include note 2 for igloo plus. 13-3
v1.4 14-1 14 ? ddr for actel?s low-power flash devices introduction the i/os in fusion, igloo, ? and proasic ? 3 devices support double data rate (ddr) mode. in this mode, new data is present on every transition (or clock edge) of the clock signal. this mode doubles the data transfer rate compared with single data rate (sdr) mode, where new data is present on one transition (or cloc k edge) of the clock signal. low-power flash devices have ddr circuitry built into the i/o tiles. i/os are config ured to be ddr receivers or transmitters by instantiating the appropriate spec ial macros (examples shown in figure 14-4 on page 14-6 and figure 14-5 on page 14-7 ) and buffers (ddr_out or ddr_reg) in the rtl design. this document discusses the opti ons the user can choose to configure the i/os in this mode and how to instantiate them in the design. double data rate (ddr) architecture low-power flash devices support 350 mhz ddr in puts and outputs. in ddr mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidths and signal integrity requirements, making them very ef ficient for implementi ng very high-speed systems. high-speed ddr interf aces can be implemented using lvds. in iglooe, proasic3e, afs600, and afs1500 devices, ddr interfaces can also be implemented using the hstl, sstl, and lvpecl i/o standards. the ddr feature is primarily implemented in the fpga core periphery and is not tied to a specific i/o technology or limited to any i/o standard. figure 14-1 ? ddr support in low-power flash devices dqr qf clr pad y inbuf_sstl2_i ddr_reg pad clk clr d pad dr q clr df datar dataf outbuf_sstl3_i ddr_out
ddr for actel?s low-power flash devices 14-2 v1.4 ddr support in flash-based devices the flash fpgas listed in table 14-1 support the ddr feature and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 14-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 14-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 14-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
ddr for actel?s low-power flash devices v1.4 14-3 i/o cell architecture low-power flash devices support ddr in the i/o ce lls in four different modes: inpu t, output, tristate, and bidirectional pins. for each mode, different i/o stan dards are supported, with most i/o standards having special sub-op tions. for the proasic3 nano and igloo nano devices, ddr is supported only in the 60 k, 125 k, an d 250 k logic densities. refer to table 14-2 for a sample of the available i/o options. additional i/o options ca n be found in the rele vant family datasheet. table 14-2 ? ddr i/o options ddr register type i/o type i/o standard sub-options comments receive register input normal none 3.3 v ttl (default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) pull-up none (default) pci/pci-x none gtl/gtl+ voltage 2.5 v, 3.3 v (3.3 v default) hstl class i / ii (i default) sstl2/sstl3 class i / ii (i default) lvpecl none lvds none transmit register output norma l none 3.3 v ttl (default) lvttl output drive 2, 4, 6, 8, 12, 16, 24, 36 ma (8 ma default) slew rate low/high (high default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) pci/pci-x none gtl/gtl+ voltage 1.8 v, 2.5 v, 3.3 v (3.3 v default) hstl class i / ii (i default) sstl2/sstl3 class i / ii (i default) lvpecl none lvds none
ddr for actel?s low-power flash devices 14-4 v1.4 transmit register (continued) tristate buffer normal enable polarity low/high (low default) lvttl output drive 2, 4, 6, 8, 12,16, 24, 36 ma (8 ma default) slew rate low/high (high default) enable polarity low/ high (low default) pull-up/-down none (default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) output drive 2, 4, 6, 8, 12, 16, 24, 36 ma (8 ma default) slew rate low/high (high default) enable polarity low/ high (low default) pull-up/-down none (default) pci/pci-x enable polarity low/high (low default) gtl/gtl+ voltage 1.8 v, 2.5 v, 3.3 v (3.3 v default) enable polarity low/ high (low default) hstl class i / ii (i default) enable polarity low/ high (low default) sstl2/sstl3 class i / ii (i default) enable polarity low/ high (low default) bidirectional buffer normal enable polarity lo w/high (low default) lvttl output drive 2, 4, 6, 8, 12, 16, 24, 36 ma (8 ma default) slew rate low/high (high default) enable polarity low/ high (low default) pull-up/-down none (default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) enable polarity low/ high (low default) pull-up none (default) pci/pci-x none enable polarity low/ high (low default) gtl/gtl+ voltage 1.8 v, 2.5 v, 3.3 v (3.3 v default) enable polarity low/ high (low default) hstl class i / ii (i default) enable polarity low/ high (low default) sstl2/sstl3 class i / ii (i default) enable polarity low/ high (low default) table 14-2 ? ddr i/o options (continued) ddr register type i/o type i/o standard sub-options comments
ddr for actel?s low-power flash devices v1.4 14-5 input support for ddr the basic structure to suppor t a ddr input is shown in figure 14-2 . three input registers are used to capture incoming data, which is pr esented to the core on each risi ng edge of the i/o register clock. each i/o tile su pports ddr inputs. output support for ddr the basic ddr output structure is shown in figure 14-1 on page 14-1 . new data is presented to the output every half clock cycle. note: ddr macros and i/o registers do not require addi tional routing. the combiner automatically recognizes the ddr macro and pushes its registers to the i/o register area at the edge of the chip. the routing delay from the i/o registers to the i/o buffers is already taken into account in the ddr macro. figure 14-2 ? ddr input register support in low-power flash devices d qr qf clr pad y inbuf_sstl2_i ddr_reg qr qf pad clk clr figure 14-3 ? ddr output register (sstl3 class i) d pad dr q clr df datar dataf clr clk outbuf_sstl3_i ddr_out
ddr for actel?s low-power flash devices 14-6 v1.4 instantiating ddr registers using smartgen is the simplest way to generate the appropriate rtl files for use in the design. figure 14-4 shows an example of using smartgen to ge nerate a ddr sstl2 class i input register. smartgen provides the capability to generate all of the ddr i/o cells as described. the user, through the graphical user interface, can select from among the many supported i/o standards. the output formats supported are verilog, vhdl, and edif. figure 14-5 on page 14-7 through figure 14-8 on page 14-10 show the i/o cell configured for ddr using sstl2 class i technology. for each i/o standard, the i/o pad is buffered by a special primitive that indicates the i/o standard type. figure 14-4 ? example of using smartgen to generate a ddr sstl2 class i input register
ddr for actel?s low-power flash devices v1.4 14-7 ddr input register the corresponding structural representations, as generated by smar tgen, are shown below: verilog module ddr_inbuf_sstl2_i(pad,clr,clk,qr,qf); input pad, clr, clk; output qr, qf; wire y; inbuf_sstl2_i inbuf_sstl2_i_0_inst(.pad(pad),.y(y)); ddr_reg ddr_reg_0_inst(.d(y),.clk(clk),.clr(clr),.qr(qr),.qf(qf)); endmodule vhdl library ieee; use ieee.std_logic_1164.all; --the correct library will be inserted automatically by smartgen library proasic3; use proasic3.all; --library fusion; use fusion.all; --library igloo; use igloo.all; entity ddr_inbuf_sstl2_i is port(pad, clr, clk : in std_logic; qr, qf : out std_logic) ; end ddr_inbuf_sstl2_i; architecture def_arch of ddr_inbuf_sstl2_i is component inbuf_sstl2_i port(pad : in std_logic := 'u'; y : out std_logic) ; end component; component ddr_reg port(d, clk, clr : in std_logic := 'u'; qr, qf : out std_logic) ; end component; signal y : std_logic ; begin inbuf_sstl2_i_0_inst : inbuf_sstl2_i port map(pad => pad, y => y); ddr_reg_0_inst : ddr_reg port map(d => y, clk => clk, clr => clr, qr => qr, qf => qf); end def_arch; figure 14-5 ? ddr input register (sstl2 class i) d qr qf clr pad y inbuf_sstl2_i ddr_reg qr qf pad clk clr
ddr for actel?s low-power flash devices 14-8 v1.4 ddr output register verilog module ddr_outbuf_sstl3_i(datar,dataf,clr,clk,pad); input datar, dataf, clr, clk; output pad; wire q, vcc; vcc vcc_1_net(.y(vcc)); ddr_out ddr_out_0_inst(.dr(datar),.df(dataf),.clk(clk),.clr(clr),.q(q)); outbuf_sstl3_i outbuf_sstl3_i_0_inst(.d(q),.pad(pad)); endmodule vhdl library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity ddr_outbuf_sstl3_i is port(datar, dataf, clr, clk : in std_logic; pad : out std_logic) ; end ddr_outbuf_sstl3_i; architecture def_arch of ddr_outbuf_sstl3_i is component ddr_out port(dr, df, clk, clr : in std_logic := 'u'; q : out std_logic) ; end component; component outbuf_sstl3_i port(d : in std_logic := 'u'; pad : out std_logic) ; end component; component vcc port( y : out std_logic); end component; signal q, vcc_1_net : std_logic ; begin vcc_2_net : vcc port map(y => vcc_1_net); ddr_out_0_inst : ddr_out port map(dr => datar, df => dataf, clk => clk, clr => clr, q => q); outbuf_sstl3_i_0_inst : outbuf_sstl3_i port map(d => q, pad => pad); end def_arch; figure 14-6 ? ddr output register (sstl3 class i) d pad dr q clr df datar dataf clr clk outbuf_sstl3_i ddr_out
ddr for actel?s low-power flash devices v1.4 14-9 ddr tristate output register verilog module ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup(datar, dataf, clr, clk, trien, pad); input datar, dataf, clr, clk, trien; output pad; wire trienaux, q; inv inv_tri(.a(trien),.y(trienaux)); ddr_out ddr_out_0_inst(.dr(datar),.df(dataf),.clk(clk),.clr(clr),.q(q)); tribuff_f_8u tribuff_f_8u_0_inst(.d(q),.e(trienaux),.pad(pad)); endmodule vhdl library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup is port(datar, dataf, clr, clk, trien : in std_logic; pad : out std_logic) ; end ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup; architecture def_arch of ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup is component inv port(a : in std_logic := 'u'; y : out std_logic) ; end component; component ddr_out port(dr, df, clk, clr : in std_logic := 'u'; q : out std_logic) ; end component; component tribuff_f_8u port(d, e : in std_logic := 'u'; pad : out std_logic) ; end component; signal trienaux, q : std_logic ; begin inv_tri : inv figure 14-7 ? ddr tristate output register, low enable, 8 ma, pull-up (lvttl) d pad dr q clr df datar dataf clr clk tribuff_f_8u ddr_out trien ay trienaux inv
ddr for actel?s low-power flash devices 14-10 v1.4 port map(a => trien, y => trienaux); ddr_out_0_inst : ddr_out port map(dr => datar, df => dataf, clk => clk, clr => clr, q => q); tribuff_f_8u_0_inst : tribuff_f_8u port map(d => q, e => trienaux, pad => pad); end def_arch; ddr bidirectional buffer verilog module ddr_bidir_hstl_i_lowenb(datar,dataf,clr,clk,trien,qr,qf,pad); input datar, dataf, clr, clk, trien; output qr, qf; inout pad; wire trienaux, d, q; inv inv_tri(.a(trien), .y(trienaux)); ddr_out ddr_out_0_inst(.dr(datar),.df(dataf),.clk(clk),.clr(clr),.q(q)); ddr_reg ddr_reg_0_inst(.d(d),.clk(clk),.clr(clr),.qr(qr),.qf(qf)); bibuf_hstl_i bibuf_hstl_i_0_inst(.pad(pad),.d(q),.e(trienaux),.y(d)); endmodule figure 14-8 ? ddr bidirectional buffer, low output enable (hstl class ii) d pad dr q clr df datar dataf clr clk bibuf_hstl_i ddr_out trien ay e y d qr qf clr qr qf inv ddr_reg
ddr for actel?s low-power flash devices v1.4 14-11 vhdl library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity ddr_bidir_hstl_i_lowenb is port(datar, dataf, clr, clk, trien : in std_logic; qr, qf : out std_logic; pad : inout std_logic) ; end ddr_bidir_hstl_i_lowenb; architecture def_arch of ddr_bidir_hstl_i_lowenb is component inv port(a : in std_logic := 'u'; y : out std_logic) ; end component; component ddr_out port(dr, df, clk, clr : in std_logic := 'u'; q : out std_logic) ; end component; component ddr_reg port(d, clk, clr : in std_logic := 'u'; qr, qf : out std_logic) ; end component; component bibuf_hstl_i port(pad : inout std_logic := 'u'; d, e : in std_logic := 'u'; y : out std_logic) ; end component; signal trienaux, d, q : std_logic ; begin inv_tri : inv port map(a => trien, y => trienaux); ddr_out_0_inst : ddr_out port map(dr => datar, df => dataf, clk => clk, clr => clr, q => q); ddr_reg_0_inst : ddr_reg port map(d => d, clk => clk, clr => clr, qr => qr, qf => qf); bibuf_hstl_i_0_inst : bibuf_hstl_i port map(pad => pad, d => q, e => trienaux, y => d); end def_arch;
ddr for actel?s low-power flash devices 14-12 v1.4 design example figure 14-9 shows a simple example of a design using both ddr input and ddr output registers. the user can copy the hdl code in actel libero ? integrated design environment (ide) and go through the design flow. figure 14-10 and figure 14-11 on page 14-13 show the netlist and chipplanner views of the ddr_test design. diagrams may vary sl ightly for different families. figure 14-9 ? design example figure 14-10 ? ddr test design as seen by netlistviewer for igloo/e devices dqr qf clr pad y inbuf_sstl2_i ddr_reg pad clk clr d pad dr q clr df datar dataf outbuf_sstl3_i ddr_out
ddr for actel?s low-power flash devices v1.4 14-13 verilog module inbuf_ddr(pad,clr,clk,qr,qf); input pad, clr, clk; output qr, qf; wire y; ddr_reg ddr_reg_0_inst(.d(y), .clk(clk), .clr(clr), .qr(qr), .qf(qf)); inbuf inbuf_0_inst(.pad(pad), .y(y)); endmodule module outbuf_ddr(datar,dataf,clr,clk,pad); input datar, dataf, clr, clk; output pad; wire q, vcc; vcc vcc_1_net(.y(vcc)); ddr_out ddr_out_0_inst(.dr(datar), .df(dataf), .clk(clk), .clr(clr), .q(q)); outbuf outbuf_0_inst(.d(q), .pad(pad)); endmodule figure 14-11 ? ddr input/output cells as seen by chipplanner for igloo/e devices
ddr for actel?s low-power flash devices 14-14 v1.4 module ddr_test(din, clk, clr, dout); input din, clk, clr; output dout; inbuf_ddr inbuf_ddr (.pad(din), .clr(clr), .clk(clk), .qr(qr), .qf(qf)); outbuf_ddr outbuf_ddr (.datar(qr),.dataf(qf), .clr(clr), .clk(clk),.pad(dout)); inbuf inbuf_clr (.pad(clr), .y(clr)); inbuf inbuf_clk (.pad(clk), .y(clk)); endmodule simulation consideration actel ddr simulation models use inertial dela y modeling by default (versus transport delay modeling). as such, pulses that ar e shorter than the actual gate de lays should be avoided, as they will not be seen by the simulator and may be an issue in post-routed simu lations. the user must be aware of the default delay modeling and must set the correct delay model in the simulator as needed. conclusion fusion, igloo, and proasi c3 devices support a wide range of ddr applications with different i/o standards and include built-in ddr macros. the powe rful capabilities provided by smartgen and its gui can simplify the process of including ddr macros in desi gns and minimize design errors. additional considerations should be taken into account by the designer in design floorplanning and placement of i/o flip-flops to minimize datapath skew and to help improve system timing margins. other system-related issues to c onsider include pll and clock partitioning.
ddr for actel?s low-power flash devices v1.4 14-15 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-010-4 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 14-1 flash-based fpgas . 14-2 the "i/o cell architecture" section was updated with info rmation appl icable to nano devices. 14-3 the output buffer (outbu f_sstl3_i) input was changed to d, instead of q, in figure 14-1 ddr support in low-power flash devices , figure 14-3 ddr output register (sstl3 class i) , figure 14-6 ddr output re gister (sstl3 class i) , figure 14-7 ddr tristate output register, low enable, 8 ma, pull-up (lvttl) , and the output from the ddr_out macr o was connected to the input of the tribuff macro in figure 14-7 ddr tristate output register, low enable, 8 ma, pull-up (lvttl) . 14-1 , 14-5 , 14-8 , 14-9 v1.2 (june 2008) the "double data rate (ddr) architecture" section was updated to include mention of the afs600 and afs1500 devices. 14-1 the "ddr support in flash-based devices" section was revised to include new families and make the in formation more concise. 14-2 v1.1 (march 2008) the following changes were made to the family descriptions in table 14-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3e was chan ged from five to six. 14-2 v1.0 (january 2008) the "igloo terminology" section and "proasic3 terminology" section are new. 14-2

design migration

v1.0 15-1 15 ? prototyping with afs600 for smaller devices this document is designed as an aid for customers who may ulti mately wish to use one of the smaller members of the fusion fa mily (afs090 and/or afs250). the first device av ailable in the fusion family is the afs600, which can be used as a development or prot otyping platform for the smaller devices. this document will help high light differences between the afs600 and these smaller devices in order to ease transition to th e targeted device when it becomes available. the actel fusion ? family, based on the highly successful proasic ? 3e and proasic3 flash fpga architecture, has been designed as a high-perfo rmance, programmable, mi xed-signal platform. by combining an advanced flash fp ga core with embedded flash me mory and analog peripherals, fusion devices dramatically simplify system design, and save overall system cost and board space as a result. figure 15-1 shows the fusion device architecture overview. the state-of-the-art embedded flash memory tech nology offers high-den sity integrated flash memory arrays, enabling savings in cost, power, and board area rela tive to external flash solutions, while providing increased fl exibility and performance. fusion devices offer a robust and flexible analog mixed-signal addition to the high-performance flash fpga fabric and embedded flash memory. the many built-in analog peripherals include a configurable 32:1 input analog multiplexer, up to 10 independent metal- oxide semiconductor field- effect transistor (mosfet) gate driver outputs, and a configurable analog-to-digital converter (adc). the analog quad is an i/o structure that contains thre e adjacent analog inputs and a gate driver output. figure 15-1 ? fusion device architecture overview versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad
prototyping with afs 600 for smaller devices 15-2 v1.0 the addition of the real-time co unter (rtc) system enab les fusion devices to support both standby and sleep modes of operation, greatly reducing power consumption in many applications. prototype guideline afs090, afs250, afs60 0, and afs1500 devi ce configuration afs600 is a medium size device in the fusion family. it supports all of the fusion features, as shown in table 15-1 . the smaller devices (afs090 and afs250) in the fusion family ha ve lower gate counts and fewer memory blocks, i/os, and plls. table 15-1 ? afs090, afs250, and af s600 device summary part number afs090 afs250 afs600 afs1500 general information system gates 90,000 250,000 600,000 1,500,000 tiles (d-flip-flop) 2,304 6,144 13,824 38,400 secure (aes) isp yes yes yes yes plls 1 1 2 2 globals 18 18 18 18 memory flash memory blocks (256 kbytes) 11 2 4 flash memory (kbytes) 256 256 512 1,024 flashrom bits 1 k 1 k 1 k 1 k ram blocks (4,608 bits) 6 8 24 60 ram kbits 27 36 108 270 analog analog quads 5 6 10 10 analog input ch annels 15 18 30 30 gate driver outputs 5 6 10 10 i/o i/o types analog/ lvds / std+ analog/ lvds / std+ analog/ lvds / pro analog/ lvds / pro i/o banks (+ jtag) 4 4 5 5 maximum digital i/os 73 114 172 278 analog i/os 20 24 40 40 i/o: digital/analog qn108 36/14 ? ? qn180 48/20 62/24 ? ? pq208 ? 93/24 95/40 ? fg256 73/20 114/24 119/40 119/40 fg484 ? ? 172/40 228/40 fg676 ? ? ? 278/40
prototyping with afs600 for smaller devices v1.0 15-3 table 15-2 shows compatible devices for each package. the fg256 pac kage is designed to support migration across all family members. list of the guidelines for prototyping actel recommends afs600-fg256 as the platform fo r prototyping smaller devices within the same compatible package type. afs600-fg256 is also th e first available fusion silicon in the rollout roadmap and is used in the fusion starter kit, which can serve as a prototype board to demonstrate the majority of fusion features. memory blocks the afs250 and afs090 have a single 256-kbyte block of embedded flas h memory, whereas the afs600 has two 256-kbyte blocks (512 kbytes tota l). therefore, the user must keep the usage less than 256 kbytes while doing prototyping with the afs600. the afs250 has 8 ram blocks, while the afs600 has 24 ram blocks. a sm artgen analog system generated soft ip uses 3 to 9 bl ocks of ram. the user needs to keep track of the ram block usage, especially if the design contains a ram initialization application, data storage application or other applications that utilize extra ra m blocks. usage must be no more than 8 blocks. likewise, if the user is prototyping for afs090, then the ram block usage in afs6 00 should not exceed 6 blocks. plls the afs250 and afs090 have one pll on the we st side of the device, whereas afs600 has two plls?one for each side of the device. during prototyping using afs600, the user should only implement the pll on the west side and use the corresponding pll input pi n, so that the delays from the pll input through the pll to the globa l network have a minimum variation between afs090/afs250 and afs600. i/os all special function i/os (v cc , gnd, jtag, programmin g control, etc.) of the afs250 and afs090 devices are in exactly the same locations as in the afs600 device, with one exception for the afs090 as listed below. the afs250 device has 6 analog quads, whereas the afs600 device has 10 analog quads. the user should only use analog quads 0?5 while doing prototyping in afs600, in order to have exactly the same analog pin map. to prototype afs090, the user should only use analog quads 0?4, since afs090 has 5 analog quads. while the afs250 differential i/os have the same locations as the afs600, the afs090 differential i/o locations are slightly different from those of the afs600. more details on the pin list are available in the fusion datasheet . the user should be aware that if the design has differential i/os, the pinout n eeds to be changed from the afs600 prototype design to an afs090 production design. prototype consideration in software after validating the design in the afs600, the user needs to create a new actel libero ? integrated design environment (ide) projec t for the afs090 or afs250, then recreate the smartgen cores by using the same parameters used for the afs600. al l other source code used in the afs600 project can be directly imported into the afs090 or afs250 project. the same validation process (simulation, static timi ng analysis, and functional test on silicon) should be performed for the afs090 or afs250 design as the user has done for afs600. table 15-2 ? package compatibility table package types pq208 pq208 fg256 fg484 fg676 qn108 qn180 compatible devices afs90 afs600 afs090 afs600 afs1500 afs90 afs090 afs250 afs1500 afs250 afs1500 afs250 afs600 afs1500
prototyping with afs 600 for smaller devices 15-4 v1.0 summary afs600-fg256 is the recommended fusion protot yping vehicle for smalle r devices in the same compatible package. it is also used on the fusi on starter kit board, which can demonstrate most of the fusion family features. part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700092-020-0 revised october 2008
programming and security

v1.3 16-1 16 ? programming flash devices introduction this document provides an over view of the various programming options available for the actel flash families. the electr onic version of this document includes active links to all programming resources, which are available at http://www.actel.com/produc ts/hardware/default.aspx . for actel antifuse devices, refer to the programming anti fuse devices document. summary of programming support flashpro3 is a high-performance in-system prog ramming (isp) tool ta rgeted at the latest generation of low-power flash devices offered by actel: fusion, igloo, ? and proasic ? 3, including arm ? -enabled devices. flashpro3 offers extremely high performance through the use of usb 2.0, is high-speed compliant for full use of the 480 mbps bandwidth, and can program proasic3 devices in under 30 seconds. powered exclusiv ely via usb, flashpro3 provides a v pump voltage of 3.3 v for programming these devices. silicon sculptor 3 is an easy-to-u se, single-site programming tool for actel fpgas that delivers high data throughput and promotes ease of use whil e lowering the overall cost of ownership. silicon sculptor 3 includes a high-speed usb 2.0 interface that allows a customer to connect as many as 12 programmers to a single pc. furthe rmore, silicon sculptor 3 is co mpatible with adapter modules from silicon sculptor ii , thereby preserving a customer's investment and enabling a seamless upgrade to this latest ge neration of the tool. for details of programmer suppo rt for each device, refer to table 16-6 on page 16-10 . figure 16-1 ? flashpro programming setup flashpro software flashpro3 jtag proasic3/e pdb file with security settings
programming flash devices 16-2 v1.3 programming support in flash devices the flash fpgas listed in table 16-1 support flash in-system pr ogramming and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 16-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 16-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 16-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device proasic proasic first generation proasic devices proasic plus second generation proasic devices note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
programming flash devices v1.3 16-3 general flash programming information programming basics when choosing a programming solu tion, there are a number of op tions available. this section provides a brief overview of those options. the next sections provide more detail on those options as they apply to actel fpgas. reprogrammable or one-time-programmable (otp) depending on the technology chosen, devi ces may be reprogrammable or one-time- programmable. as the name impl ies, a reprogrammable device can be programmed many times. generally, the contents of such a device will be completely overwritten wh en it is reprogrammed. all actel flash devices are reprogrammable. an otp device is programmable one time only. once programmed, no more changes can be made to the contents. actel flash devi ces provide the option of disa bling the reprogrammability for security purposes. this combines the convenience of reprogrammabi lity during design verification with the security of an otp techno logy for highly sensitive designs. device programmer or in-system programming there are two fundamental ways to program an fpga: using a device programmer or, if the technology permits, using in-system programming. a device programmer is a piece of equipment in a lab or on the production floor that is used fo r programming devices. th e devices are placed into a socket mounted in a programming adapter modu le, and the appropriate electrical interface is applied. the device can then be placed on the board. a typical programmer, used during development, programs a single device at a time and is referred to as a single-site engineering programmer. with isp, the device is alread y mounted onto the board when pr ogramming occurs, most typically via the jtag pins. the jtag pins can be controlled either by an on-board resource, such as a microprocessor, or by an off-board programmer through a header connection. once mounted, it can be programmed repeatedly. if the applicatio n requires it, the syst em can be designed to reprogram itself using a microprocessor, wi thout the use of any external programmer. for production, high-volume multi-site production programmers handle designs that require device programmers. in addition, actel can preprogram devices for production, negating the need for further programming. this service is re ferred to as in-hou se programming (ihp). live at power-up (l apu) or boot prom utilizing the technology of the fpga significan tly impacts board-level po wer-up considerations. some technologies are nonvolatile and are consid ered functional, or "live," as soon as power reaches the operational level. all actel fpga tech nologies are live at power-up. by contrast, sram technology is volatile, and devices built using sr am cells lose their cont ents when power cycling occurs. these devices must be reprogrammed ever y time power is applied. such a design must include nonvolatile storage for the contents as we ll as the means to reprogram. there is a delay before sram devices are functional; other parts of the board mu st come alive first to reprogram these types of fpgas. therefore, such devices ca n never be part of critical boot circuits. design security design security is a growin g concern for systems designer s. the choice of programming methodology and technology affects system security . use of actel programmi ng technology is the most secure option available, pr oviding much better protection than sram-based devices and asics. actel provides a number of ways to ensu re designs are protected. general information on design security can be fo und on the actel website: http://www.actel.com/products/so lutions/security /default.aspx
programming flash devices 16-4 v1.3 programming features for actel devices actel provides two types of fpgas: flash and antifuse ( table 16-2 ). some progra mming methods are common to both and some are exclusive to flash. this document describes only the programming soluti ons supported for flash devices. flash devices the flash devices su pplied by actel are reprog rammable by either a generic device programmer or isp. actel supports isp using jtag, which is supp orted by the flashpro3, flashpro lite, flashpro, silicon sculptor 3, and silico n sculptor ii programmers. levels of isp support vary de pending on the device chosen: ? all fusion, igloo, and proasic3 devices support isp. ? igloo, iglooe, igloo nano v5, and igloo plus devices can be programmed in-system when the device is using a 1.5 v supply voltage to the fpga core. ? a ll igloo v2 and proasic3l de vices can be operated at any voltage between 1.2 v and 1.5 v; the designer software allows 50 mv incr ements in the voltage. although the device can operate at 1.2 v core voltage, the device can only be reprogrammed when the core voltage is 1.5 v. voltage switching is required in-system to switch from a 1.2 v supply (v cc , v cci , and v jtag ) to 1.5 v for programming. since flash devices are nonvolatile, they are live at power-up. this is different from an sram-based device, which loads its programming information wh en it is powered up. sram devices require a time on the order of hundreds of mil liseconds before the system is active. there are multiple levels of securi ty available in flash devices. us e of a security key will lock the device. the device can then only be reprogra mmed by first unlocking the device with the appropriate security key. it can also be locked permanently, whic h means there is no key that can access the device. the command to secure the device is embedded within the programming file, optionally enabled by the programming software. this is also referred to as the otp version of flash, allowing for only a single programming insta nce. this is discussed in more detail in the implementation of security in actel's proasic and proasic plus flash-based fpgas application note, and in the security in low-power flash devices handbook section. flash devices can also be programmed using single-site or multi-site programmers as well as volume programming services from actel or other vendors. table 16-2 ? programming features for actel devices feature flash antifuse reprogrammable yes no in-system programmable yes no one-time programmable yes (option) yes live at power-up yes yes secure yes yes single-site programmer support yes yes multi-site programmer support yes yes in-house programming support yes yes
programming flash devices v1.3 16-5 types of programming for flash devices the number of devices to be programmed will influence the optimal programming methodology. those available are listed below: ? in-system programming ? using a programmer ? using a microprocesso r or microcontroller ? device programmers ? single-site programmers ? multi-site programmers, batch prog rammers, or gang programmers ? automated production (robotic) programmers ? volume programming services ? actel in-house programming ? programming centers in-system programming device type supported: flash isp refers to programming the fpga after it has been mounted on the syste m board. the fpga may be preprogrammed and later reprogrammed using isp. the advantage of using isp is the ability to update the fpga design many times without any changes to the board. th is eliminates the require ment of using a socket for the fpga, saving cost and improving reliability. it also reduces progra mming hardware expenses, as the isp methodology is die-/packag e-independent. there are two methods of in-system programming: external and internal. ? programmer isp?refer to in-system programming (isp) of actel?s low-power flash devices using flashpro3 for more information. using an external programmer and a cable, the device can be programmed through a header on the system boar d. in actel documentation, this is referred to as external isp. actel provides flashpro3, flashpro lite, flashpro, or silicon sculptor 3 to perform external isp. note that silicon sculptor ii and silicon sculptor 3 can only provide isp for proasic and proasic plus ? families, not for fusion , igloo, or proasic3. ? advantages: allows local control of progra mming and data files for maximum security. the programming algorithms and hardware ar e available from actel. the only hardware required on the board is a programming header. ? limitations: a negligible board space re quirement for the prog ramming header and jtag signal routing ? microprocessor isp?refer to microprocessor programming of actel?s low-power flash devices for more information. using a microprocessor and an external or internal memory, you can store the program in memory and use the microprocessor to perfo rm the programming. in actel documentation, this is referred to as internal isp. both the code for the progra mming algorithm and the fpga programming file must be stored in me mory on the board. programming voltages must also be generated on the board. ? advantages: the programming code is st ored in the system memory. an external programmer is not required during programming. ? limitations: this is the approach that requ ires the most design work, since some way of getting and/or storing the data is needed; a system interface to the device must be designed; and the low-level api to the pr ogramming firmware must be written and linked into the code provided by actel. wh ile there are benefits to this methodology, serious thought and planning should go into the decision.
programming flash devices 16-6 v1.3 device programmers device type supported: flash and antifuse device programmers are used to program a device before it is mounted on the system board. the advantage of using device pr ogrammers is that no programming hardware is required on the system board. therefore, no additional components or board space are required. if devices are to be reprogrammed multiple times, or if the quantity of devices to be programmed is relatively low, a single-site device programmer is the simplest so lution. for applications in which design security is paramount (often the case in military or space desi gns), the use of on-site programming maintains design security at all times. adapter modules are purc hased with the programmers to supp ort the fpga packages used. the fpga is placed in the adapter module and the programming software is run from a pc. actel supplies the programm ing software for all of the actel prog rammers. the softwa re allows for the selection of the correct die/pack age and programming files. it wi ll then program and verify the device. ? single-site programmers a single-site programmer programs one device at a time. actel offers silicon sculptor 3 as a single-site programmer. ? advantages: lower cost than multi-site programmers. no additional overhead for programming on the system board. allows lo cal control of programming and data files for maximum security. allows on-demand programming on-site. ? limitations: only programs one device at a time. ? multi-site programmers often referred to as batch or gang prog rammers, multi-site programmers can program multiple devices at the same time using the sa me programming file. this is often used for large volume programming and by programming houses. the sites of ten have independent processors and memory enabling the sites to operat e concurrently, meaning each site may start programming the same file independently. this enables the operator to change one device while the other sites continue programming, which increases throughput. multiple adapter modules for the same package are required when us ing a multi-site programmer. silicon sculptor i, ii, and 3 pr ogrammers can be cascaded to program multiple devices in a chain. multi-site programmers can also be purchased from bp microsystems. ? advantages: provides the capability of prog ramming multiple devices at the same time. no additional overhead for programming on the system board. allows local control of programming and data files for maximum security. ? limitations: more expensive than a single-site programmer ? automated production (robotic) programmers automated production programmers are based on multi-site programmers. they consist of a large input tray holding multiple parts and a robotic arm to select and place parts into appropriate programming socke ts automatically. when the programming of the parts is complete, the parts are remove d and placed in a finished tray. the automated programmers are often used in volume programming houses to program parts for which the programming time is small.
programming flash devices v1.3 16-7 volume programming services device type supported: flash and antifuse once the design is stable for ap plications with large production volumes, preprogrammed devices can be purchased. table 16-3 describes the volume programming services. advantages: as programming is outs ourced, this solution is easier to implement th an creating a substantial in-house programming capability. as programming hous es specialize in large-volume programming, this is often th e most cost-effective solution. limitations: there are some logistical issues with the use of a programming service provider, such as the transfer of programmi ng files and the approval of fi rst articles. by definition, the programming file must be rel eased to a third-party programming house. nondisclosure agreements (ndas) can be signed to help ensure data protection; however, for extremely security- conscious designs, this may not be an option. ? actel in-house programming when purchasing actel devices in volume, ihp can be requested as part of the purchase. if this option is chosen, there is a small cost adder for each device programmed. each device is marked with a special mark to distinguish it from blank parts. prog ramming files for the design will be sent to actel. sample parts wi th the design programmed , first articles, will be returned for customer approval. once approval of first articles has been received, actel will proceed with programming the remainder of th e order. to request actel ihp, contact your local actel representative. ? distributor programming centers if purchases are made through a distributor, many distributors will provide programming for their customers. cons ult with your preferred dis tributor about this option. ? independent programming centers there are many programming centers that sp ecialize only in programming but are not directly affiliated with actel or our distributo rs. these programming centers must follow the guidelines for programming ac tel devices and use certified programmers to program actel devices. actel does not have recommendat ions for external programming centers. table 16-3 ? volume programming services programmer vendor availability in-house programming actel contact actel sales distributor programming centers me mec unique contact distribution independent programming centers various contact vendor
programming flash devices 16-8 v1.3 programming solutions details for the available programmers can be found in the programmer user's guides listed in the "related documents" section on page 16-15 . refer to table 16-6 on page 16-10 for more information concerning programming solutions. all of the programmers except fl ashpro3, flashpro lite, and fl ashpro require adapter modules, which are designed to support device packages. the modules are all listed on the actel website at http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . they are not listed in this document, sinc e this list is updated frequently with new package options and any upgrades required to improve programming yield or support new families. programmer ordering codes the products shown in table 16-5 can be ordered through actel sales and will be shipped directly from actel. products can also be or dered from actel distributors, bu t will still be shipped directly from actel. table 16-5 includes ordering codes for the full kit, as well as codes for replacement items and any related hardware. some additi onal products can be purchased from external suppliers for use with the prog rammers. ordering codes for ad apter modules used with silicon sculptor are available on the actel website at http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . table 16-4 ? programming solutions programmer vendor isp single device multi-device availability flashpro3 actel only yes yes 1 available flashpro lite actel only yes yes 1 available flashpro actel only yes yes 1 available silicon sculptor 3 actel yes 2 yes cascade option (up to two) available silicon sculptor ii actel yes 2 yes cascade option (up to two) available silicon sculptor actel yes yes cascade option (up to four) discontinued sculptor 6x actel no yes yes discontinued bp microprogrammers bp microsystems no yes yes contact bp microsystems at www.bpmicro.com notes: 1. multiple devices can be connected in the same jtag chain for programming. 2. silicon sculptor ii and silicon sculptor 3 can only provide isp for proasic and proasic plus families, not for fusion, igloo, or proasic3 devices. table 16-5 ? programming ordering codes description vendor ordering code comment flashpro3 isp programmer actel flashpro 3 uses a 25, ra male header connector flashpro lite isp programmer actel flashpro lite supports small pr ogramming header or large header through header converter (not included) flashpro isp programmer actel flash pro supports small prog ramming header or large header through header converter (not included) silicon sculptor 3 actel silicon-sculptor 3 usb 2.0 high-speed production programmer silicon sculptor ii actel silicon-sculptor ii requires add-on adapter modules to support devices silicon sculptor isp module actel smpa-isp-actel-3-kit ships with both large and small header support * a maximum of two silicon sculptor ii programmers can be chained together using a standard ieee 1284 parallel port cable.
programming flash devices v1.3 16-9 concurrent programming cable actel ss-expander used to cascad e silicon sculptor i programmers together* software for silicon sculptor actel sculptor-software-cd http://www.actel.com/download/program_debug/ss/ isp cable for small header actel isp-cable-s supplied with smpa-isp-actel-3-kit isp cable for large header actel pa-isp-cable supplied with smpa-isp-actel-3-kit header converter actel header-converter converts from small to large header small programming header samtec ftsh-113-01-l-d-k supported by flashpro, flashpro lite, and silicon sculptor in migrating to proasic3 /e devices, an fp3-26pin- adapter is required. 10-pin 0.1" pitch cable header (right- angle pcb mount angle) amp 103310-1 supported by flashpro3 10-pin 0.1" pitch cable header (straight pcb mount angle) 3m 2510-6002ub supported by flashpro3 compact programming header (10-pin 0.05" pitch, 2 rows of 5 pins) samtec ftsh-105-01-l-d-k supported by flashpro3, fp3-10pin-adapter-kit required. used for boards where space is at a premium. migration and compact header adapter actel fp3-10pin-adapter-kit compact head er and migration kit. comes with samtec ffsd-05-d-06.00-01-n (6-inch cable for connecting to compac t 10-pin headers). large programming header, 0.062" board thickness 3m 3429-6502 supported by silicon sculptor by default, flashpro and flashpro lite with header converter large programming header, 0.094" to 0.125" board thickness 3m 3429-6503 supported by silicon sculptor by default, flashpro and flashpro lite with header converter plug-in header, small actel smpa-isp-header-s requi red for small header fo r proasic only; not used for proasic plus plug-in header actel smpa-isp-header required for large header for proasic only; not used for proasic plus vacuum pens for pq, tq, vq; <208 pins actel penvac vacuum pens for pq, tq, vq; 208 pins actel penvac-hd heavy-duty, provides stronger vacuum table 16-5 ? programming ordering codes (continued) description vendor ordering code comment * a maximum of two silicon sculptor ii programmers can be chained together using a standard ieee 1284 parallel port cable.
programming flash devices 16-10 v1.3 programmer device support refer to table 16-6 to determine which general-purpose flash devices have programmer device support. to learn more about the different actel families, refer to the actel website: http://www.actel.com/products/devices.aspx. data in table 16-6 also applies to arm-enabled m7 device versions of fusion, igloo, and proasic3 devices. refer to the appropriate family data sheets for information on die/package combinations available as arm- enabled versions. table 16-6 ? programmer device support actel family device arm- enabled silicon sculptor silicon sculptor 6x silicon sculptor ii silicon sculptor 3flashpro flashpro lite flashpro3 fusion afs090 no no yes. no isp support. yes. no isp support. no no yes. isp support afs250 afs600 ? afs1500 ? igloo agl015 no no yes. no isp support. yes. no isp support. no no yes. isp support. agl030 agl060 agl125 agl250 ? agl400 ? agl600 ? agl1000 ? iglooe agle600 agle3000 ? no no yes. no isp support yes. no isp support. no no yes. isp support ? igloo plus aglp030 no no yes. no isp support yes. no isp support. no no yes. isp support aglp060 aglp125 igloo nano agln010 no no yes. no isp support. yes. no isp support. no no yes. isp support agln015 agln020 agln060 agln125 agln250 proasic3 nano a3pn010 no no yes. no isp support. yes. no isp support. no no yes. isp support. a3pn015 a3pn020 a3pn060 a3pn125 a3pn250 proasic3l a3p250l ? no no yes. no isp support. yes. no isp support. no no yes. isp support. a3p600l ? a3p1000l ? a3pe3000l ? * refer to the "certified programming solutions" section on page 16-12 for more information on programmer support.
programming flash devices v1.3 16-11 proasic3 a3p015 no no yes. no isp support. yes. no isp support. no no yes. isp support. a3p030 a3p060 a3p125 a3p250 ? a3p400 ? a3p600 ? a3p1000 ? proasic3e a3pe600 ? no no yes. no isp support. yes. no isp support. no no yes. isp support. a3pe1500 ? a3pe3000 ? proasic plus apa075 yes. isp support. yes. isp support. yes. isp support. yes. isp support. yes. isp support. yes. isp support. no apa150 apa300 apa450 apa600 apa750 apa1000 proasic a500k50 yes yes yes yes yes no no a500k130 a500k180 a500k270 table 16-6 ? programmer device su pport (continued) actel family device arm- enabled silicon sculptor silicon sculptor 6x silicon sculptor ii silicon sculptor 3flashpro flashpro lite flashpro3 * refer to the "certified programming solutions" section on page 16-12 for more information on programmer support.
programming flash devices 16-12 v1.3 certified programming solutions the actel-certified programmers fo r flash devices are flashpro3, flashpro lite, flashpro, silicon sculptor i and ii, and any programmer that is buil t by bp microsystems. all other programmers are considered noncertified programmers. ? flashpro3, flashpro lite, flashpro the actel family of flashpro device progra mmers provides in-system programming in an easy-to-use, compact system that supports all flash families. whether programming a board containing a single device or multiple devices connected in a chain, the actel line of flashpro programmers enables fast programming an d reprogramming. programming with the flashpro series of programmers saves board sp ace and money as it eliminates the need for sockets on the board. there are no built-in al gorithms, so there is no delay between product release and programming support. ? silicon sculptor ii silicon sculptor ii is a robu st, compact, single-d evice programmer with standalone software for the pc. it is designed to enable concurrent programming of multiple units from the same pc with speeds equivalent to or faster than previous actel programmer s. it replaces silicon sculptor i as the actel programmer of choice. ? silicon sculptor i and silicon sculptor 6x actel no longer offers silicon sculptor i or silicon sculptor 6x for sale. both items have been discontinued. actel does support silicon sculptor i and silicon sculptor 6x by continuing to release new software that enables improved programming of previously covered actel devices; new actel devices are only supported on silicon sculptor ii. all software support for silicon sculptor i and silicon sculptor 6x pr ogrammers will be disconnected by the end of 2005; no support for these older programmers will be offered in 2006. actel recommends that all customers upgrade to silicon scul ptor ii or a bp multi-site programmer. ? noncertified programmers actel does not test programmi ng solutions from other vendors, and cannot guarantee programming yield. also, actel will not perform any failure analysis on devices programmed by hardware from other vendors. ? programming centers actel programming hardware policy also applie s to programming centers. actel expects all programming centers to use certified prog rammers to program actel devices. if a programming center uses noncertified pr ogrammers to program actel devices, the " noncertified programmers " policy applies. flash programming guidelines preprogramming setup before programming, several steps are requir ed to ensure an optimal programming yield. use proper handling and electrosta tic discharge (esd) precautions actel fpgas are sensitive electronic devices that are susceptible to damage from esd and other types of mishandling. for more in formation about esd, refer to the actel quality and reliability guide, beginning with page 41. use the latest version of the de signer software to generate your programming file (recommended) the files used to program actel fl ash devices (*.bit, *.stp) contai n important information about the switches that will be programme d in the fpga. find the latest ve rsion and corresponding release notes at http://www.actel.com/download/software/designer/ . also, programming files must always be zipped during file transfer to av oid the possibility of file corruption.
programming flash devices v1.3 16-13 use the latest version of the programming software the programming software is frequently updated to accommodate yield enhancements in fpga manufacturing. these updates ensure maximu m programming yield and minimum programming times. before progra mming, always check the ve rsion of software being used to ensure it is the most recent. depending on the programming software, refer to one of the following: ?flashpro: http://www.actel.com/download/program_debug/flashpro/ ? silicon sculptor: http://www.actel.com/download/program_debug/ss/ use the most recent adapter m odule with silicon sculptor occasionally, actel make s modifications to the adapter modules to impr ove programming yields and programming times. to identi fy the latest version of each mo dule before programming, visit http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . perform routine hardware self-diagnostic test ?flashpro the self-test is only appl icable when programming wi th flashpro and flashpro3 programmers. it is not supported with flashpro lite. to run the self-diagn ostic test, follow the instructions given in the "performing a self-test" section of http://www.actel.com/documents/flashpro_ug.pdf . ? silicon sculptor the self-diagnostic test verifi es correct operation of the pin drivers, power supply, cpu, memory, and adapter module. this test shou ld be performed before every programming session. at minimum, the te st must be executed every week . to perform self-diagnostic testing using the silicon sculptor software, perform the following steps, depending on the operating system: ? dos: from anywhere in the software, type alt + d . ? windows: click device > choose actel diagnostic > select the te s t tab > click ok . programming flash fpgas programming a flash device is a one-step proces s, whether programming is conducted with a socket adapter module or via isp. the execute func tion will automatically erase the device, program the flash cells, and verify that it is programmed correctly. actel recommend s confirming the security status is correct before programming. the following steps ar e required to program actel flash fpgas. programming with flashpro setup properly connect the flashpro ribbon cable with the programming header an d turn on the switch. actel recommends running the self-test be fore programming any devices; see the "perform routine hardware self-diagno stic test" section on page 16-13 . in the programming software, from the file menu, choose connect . in the flashpro connect to programmer dialog box that appears, select the port to which the fl ashpro programmer is connected, and select the device family. disable voltages from the programmer if they are available on the board. click connect . a successful connect or any erro rs appear in the log window. analyze chain and device selection from the file menu, choose analyze chain . chain details appear in the log window. if any failures appear, refer to the error and troubleshooting section of the flashpro user's guide . select the device to be programmed from the device list. if only one device is present in the chain, performing analyze chain sele cts that device automati cally from the device list.
programming flash devices 16-14 v1.3 loading the stapl file flashpro3, flashpro lite , and flashpro programmers use a stapl (*.stp) file to program the device. to load the stapl file, from the file menu, choose open stapl file , or click the open file button on the toolbar. selecting an action after loading the stapl file, sele ct an action from the action list. see the "programming file actions" section in the flashpro user's guide for a definition of each action. programming the device to program the device, in the action li st, select program . make the required selections and click execute to start programming. the progress of th e programming action displays in the log window. the message "exit 0" indicates that the device has successfully been programmed. note: do not interrupt the programming sequence; it may damage the device or programmer. verify correct programming to verify the device is programmed with the corre ct stapl file, load the stapl file and in the action list, click verify . click execute to start the verification proc ess. a successful verification results in "exit 0." note: verification is also performed in the previous "programming the device" step; clicking verify is an additional standalone option. programming failure allowances flash fpgas are reprogrammable, so actel tests the programmability for 100% of the devices shipped. return material authorization (rma) policies actel consistently strives to exceed customer expe ctations by continuing to improve the quality of our products and our quality management system. actel has rma procedures in place to address programming fallout. customers should be mindful of the following rma policies. all devices submitted for an rma must be within the actel warrant y period of one year from date of shipment. actel will reject rmas for devices that are no longer under warranty. rmas will only be authorized fo r current actel devices. devices th at have been discontinued will not receive rmas. all functional failure analysis requests must be initiated by opening a case with actel technical support. devices returned for fail ure analysis against an rma should be in their original packaging and must have an rma number issued by actel. contacting the cust omer support group highly skilled engineers staff the cu stomer applications center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. you can contact the center by one of the following methods: electronic mail you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design pr oblems, you can email your design files to receive assistance. actel monitors the emai l account throughout the day. when sending your request to us, please be sure to incl ude your full name, company name, an d contact information for efficient processing of your request. the technical support email address is tech@actel.com . telephone our technical support hotline answ ers all calls. the center retriev es information, such as your name, company name, telephone nu mber, and question. once this is done, a case number is assigned. then the center forwards the info rmation to a queue wh ere the first available applications engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the customer applications cent er number is (800) 262-1060. european customers can call +44 (0) 1256 305 600.
programming flash devices v1.3 16-15 related documents below is a list of related documents, their loca tion on the actel website, and a brief summary of each document. application notes programming antifuse devices http://www.actel.com/documen ts/antifuseprogram_an.pdf implementation of security in actel's proasic and proasic plus flash-based fpgas http://www.actel.com/documents/flash_security_an.pdf handbook documents security in low-pow er flash devices http://www.actel.com/docum ents/lpd_secu rity_hbs.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf microprocessor programming of actel?s low-power flash devices http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf user?s guides flashpro programmers flashpro3, flashpro lite, and flashpro http://www.actel.com/products/hardware /program_debug/flashpro/default.aspx flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf the flashpro user?s guide incl udes hardware and software setup, self-test instructions, use instructions, and a troubleshooting / error message guide. silicon sculptor 3 and silicon sculptor ii http://www.actel.com/products/hardwa re/program_debug/ss/default.aspx other documents http://www.actel.com/products/solution s/security/default.aspx#flashlock the security resource center descri bes security in actel flash fpgas. actel quality and reliability guide http://www.actel.com/documents/relguide.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-013-3 revised december 2008
programming flash devices 16-16 v1.3 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (october 2008) the "programming support in flash devices" section was updated to include igloo nano and proasic3 nano devices. 16-2 the "flash devices" section was updated to includ e information for igloo nano devices. the following sentence was added: igloo plus devices can also be operated at any voltage between 1.2 v and 1.5 v; the designer software allows 50 mv increments in the voltage. 16-4 table 16-5 programming ordering codes was updated to replace fp3-26pin- adapter with fp3-10pin-adapter-kit. 16-8 table 16-6 programmer device support was updated to add igloo nano and proasic3 nano devices. agl400 was added to the igloo portion of the table. 16-10 v1.1 (march 2008) the "programming support in flash devices" section was revised to include new families and make the information more concise. 16-2 figure 16-1 flashpro programming setup and the "programming support in flash devices" section are new. 16-1 , 16-2 table 16-6 programmer device support was updated to include a3pe600l with the other proasic3l devices, an d the rt proasic3 family was added. 16-10 v1.0 (january 2008) the "flash devices" section was updated to include the igloo plus family. the text, "voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming, " was revised to state, "although the device can operate at 1.2 v core voltage, the devi ce can only be reprogrammed when the core voltage is 1.5 v. voltage switching is required in-system to switch from a 1.2 v supply (v cc , v cci , and v jtag ) to 1.5 v for programming." 16-4 the proasic3l family was added to table 16-6 programmer device support as a separate set of rows rather than combined with proasic3 and proasic3e devices. the igloo plus family wa s included, and agl015 and a3p015 were added. 16-10
v1.5 17-1 17 ? security in low-power flash devices security in programmable logic the need for security on fpga programmable lo gic devices (plds) has never been greater than today. if the contents of the fpga can be read by an external source, the in tellectual property (ip) of the system is vulnerable to un authorized copying. actel fusion, ? igloo, ? and proasic ? 3 devices contain state-of-the-art ci rcuitry to make the flash-based devices secure during and after programming. low-power flash devices have a built-in 128-bit advanced encryption standard (aes) decryption core (except for 30 k ga te devices and smaller). the decryp tion core facilitates secure in- system programming (isp) of the fpga core ar ray fabric, the flashrom , and the flash memory blocks (fbs) in fusion devices. the flashr om, flash blocks, and fp ga core fabric can be programmed independently of each other, allowi ng the flashrom or flash blocks to be updated without the need for change to the fpga core fabric. actel has incorporated the aes decryption core into the low- power flash devices and has also included the actel flash-based lock technology, flashlock. ? together, they provide leading-edge security in a programmable logic device. configurat ion data loaded into a device can be decrypted prior to being written to the fpga core using the aes 128-bit block cipher standard. the aes encryption key is stored in on-chip, nonvolatile flash memory. this document outlines th e security features offered in low-pow er flash devices, some applications and uses, as well as the different so ftware settings for each application. figure 17-1 ? overview on security
security in low-pow er flash devices 17-2 v1.5 security support in flash-based devices the flash fpgas listed in table 17-1 support the security feature a nd the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 17-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 17-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 17-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
security in low-pow er flash devices v1.5 17-3 security architecture fusion, igloo, and proasic3 devices have b een designed with the most comprehensive programming logic design se curity in the industry. in the architec ture of these devices, security has been designed into the very fabric. the flash cells are located beneath seven metal layers, and the use of many device design and layout techniques makes invasive attacks difficult. since device layers cannot be removed withou t disturbing the char ge on the programmed (or erased) flash gates, devices cannot be easily deconstructed to decode the design. low-power flash devices are unique in being reprogrammable and having inhere nt resistance to both in vasive and noninvasive attacks on valuable ip. secure, remote isp is now possible with aes encryp tion capability for the programming file during electronic transfer. figure 17-2 shows a view of th e aes decryption core inside an igloo device; figure 17-3 on page 17-4 shows the aes decryption core inside a fusion device. the aes core is used to decrypt the encrypted programming f ile when programming. note: *isp aes decryption is not supported by 30 k gate devi ces and smaller. for details of other architecture features by device, refer to th e appropriate family datasheet. figure 17-2 ? block representation of th e aes decryption core in igloo and proasic3 devices flash*freeze technology charge pumps user nonvolatile flashrom isp aes decryption* ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
security in low-pow er flash devices 17-4 v1.5 security features igloo and proasic3 devices have two entities in side: flashrom and the fpga core fabric. fusion devices contain three entities: flashrom, fb s, and the fpga core fabric. the parts can be programmed or updated independently with a stapl programming file. the programming files can be aes-encrypted or plaintext. this allows maximum flexibilit y in providing security to the entire device. refer to flashrom in actel?s lo w-power flash devices for information on the flashrom structure. unlike sram-based fpga devices, which require a separate bo ot prom to store programming data, low-power flash devices are nonvolatile, and the secured configuration data is stored in on- chip flash cells that are part of the fpga fabric. once programmed, th is data is an inherent part of the fpga array and does not need to be loaded at system power- up. sram-based fpgas load the configuration bitstream upon power-up; therefore, the configuration is exposed and can be read easily. the built-in fpga core, fbs, and flashrom supp ort programming files en crypted with the 128-bit aes (fips-192) block ciphers. the aes key is stored in dedicated, on-chip flash memory and can be programmed before the device is shipped to other parties (allowin g secure remote field updates). security in arm-enabled low-power flash devices there are slight differences between the regular flash devices and the arm ? -enabled flash devices, which have the m1 and m7 prefix. the aes key is used by actel and preprogrammed into the device to protect the arm ip. as a result, the design is encrypted along with the arm ip, according to the details below. figure 17-3 ? block representation of the aes decr yption core in a fusion afs600 fpga versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad
security in low-pow er flash devices v1.5 17-5 cortex-m1 device security cortex-m1?enabled devices are shipped wi th the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for aes-encrypted write and verify ? fusion embedded flash memory enabled for aes- encrypted write aes encryption of programming files low-power flash devices employ aes as part of th e security mechanism that prevents invasive and noninvasive attacks. the mechanism entails encrypting the pr ogramming file with aes encryption and then passing the programming file through the aes de cryption core, which is embedded in the device. the file is decrypted there, and the devi ce is successfully programmed. the aes master key is stored in on-chip nonvolatile memory (flash). the aes master key can be preloaded into parts in a secure programming environment (such as the actel in-house programming center), and then "blank" parts can be shipped to an untrusted pr ogramming or manufactur ing center for final personalization with an aes-encrypted bitstream. late-stage product changes or personalization can be implemented easily and securely by simply sending a stapl file wi th aes-encrypted data. secure remote field updates over public networks (such as the inte rnet) are possible by sending and programming a stapl file with aes-encrypted data. the aes key protects the programmi ng data for file transfer into the device with 128-bit aes encryption. if aes encryption is used, the aes key is stored or preprogrammed into the device. to program, you must use an aes-en crypted file, and the encryption used on the file must match the encryption key alr eady in the device. the aes key is protected by a flashlock security pas s key that is also impl emented in each device. the aes key is always protected by the flashlock key, and the aes-encrypted file does not contain the flashlock key. this flashlock pass key techno logy is exclusive to the actel flash-based device families. flashlock pass key technology can al so be implemented with out the aes encryption option, providing a choice of different security levels. in essence, security featur es can be categorized into the following three options: ? aes encryption with fl ashlock pass key protection ? flashlock protection only (no aes encryption) ? no protection each of the above options is explained in more detail in the following sections with application examples and software im plementation options. advanced encr yption standard the 128-bit aes standard (fips-192) block cipher is the nist (national insti tute of standards and technology) replacement for des (data encryption standard fips46-2). aes has been designed to protect sensitive government info rmation well into the 21st centur y. it replaces the aging des, which nist adopted in 1977 as a federal information processing standard used by federal agencies to protect sensitive, unclassified inform ation. the 128-bit ae s standard has 3.4 10 38 possible 128-bit key variants, and it has been estimated th at it would take 1,000 trillion years to crack 128-bit aes cipher text using exha ustive techniques. keys are store d (securely) in low-power flash devices in nonvolatile flash memory . all programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programming verifi cation is performed on-chi p, ensuring that the contents of low-power flash devices remain secure. actel has implemented the 128-bit aes (rijndael) algorithm in low-p ower flash devices. with this key size, there are approximately 3.4 10 38 possible 128-bit keys. des has a 56-bit key size, which provides approximately 7.2 10 16 possible keys. in their aes fact sheet, the nati onal institute of standards and technology uses the following hypo thetical example to illustrate the theoretical security provided by aes. if one were to assume that a computing system ex isted that could recover a des key in a second, it would take that same ma chine approximately 149 trillion years to crack a 128-bit aes key. nist continues to make their point by stating the universe is believed to be less than 20 billion years old. 1
security in low-pow er flash devices 17-6 v1.5 the aes key is securely stored on-chip in dedi cated low-power flash device flash memory and cannot be read out. in the first step, the aes key is generated and programmed into the device (for example, at a secure or trusted programming site). the actel designer soft ware tool provides aes key generation capability. after the key has been programmed into the device, the device will only correctly decrypt programming files that have been encrypted with the same key. if the individual programming file content is incorrect, a messag e authentication contro l (mac) mechanism inside the device will fail in authenti cating the programming file. in other words, when an encrypted programming file is being loaded into a device that has a different programmed aes key, the mac will prevent this incorrect data from being lo aded, preventing possible device damage. see figure 17-3 on page 17-4 and figure 17-4 on page 17-7 for graphical repr esentations of this process. it is important to note that the user decides what level of protec tion will be implemented for the device. when aes protection is desired, the fl ashlock pass key must be set. the aes key is a content protection mechanism, whereas the flashl ock pass key is a device protection mechanism. when the aes key is programmed into the device, th e device still needs the pass key to protect the fpga and flashrom contents and the security setti ngs, including the aes key. using the flashlock pass key prevents modification of the design contents by means of simply programming the device with a different aes key. aes decryption and mac authentication low-power flash devices have a built-in 128-bit aes decryption core, whic h decrypts the encrypted programming file and performs a mac check that authenticates the file prior to programming. mac authenticates the entire pr ogramming data stream. after aes decryption, the mac checks the data to make sure it is valid programming data for the device. this can be done while the device is still operating. if th e mac validates the file, the device will be erased and programmed. if the mac fails to validate, th en the device will continue to operate uninterrupted. this will ensure the following: ? correct decryption of th e encrypted programming file ? prevention of erroneous or corrupted data being programmed during the programming file transfer ? correct bitstream passed to the device for decryption 1. national institute of standards and technology, ?advanced encryption standard (aes) questions and answers,? 28 january 2002 (10 january 2005). see http://csrc.nist.gov/archive/aes/index1.html for more information.
security in low-pow er flash devices v1.5 17-7 flashlock additional options for iglo o and proasic3 devices the user also has the option of prohibiting write operations to the fpga array but allowing verify operations on the fpga array and/or read oper ations on the flashrom without the use of the flashlock pass key. this option provides the user the freedom of verifying the fpga array and/or reading the flashrom contents after the device is programmed, without having to provide the flashlock pass key. the user can incorporate aes encryption on the prog ramming files to better enhance the level of security used. figure 17-4 ? example application scen ario using aes in igloo and proasic3 devices figure 17-5 ? example application scenario using aes in fusion devices actel designer software programming file generation with aes encryption igloo and proasic3 decrypted bitstream mac validation aes decryption core transmit medium / public network encrypted bitstream flashrom aes key fpga core actel designer software programming file generation with aes encryption fusion decrypted bitstream mac validation aes decryption core transmit medium / public network encrypted bitstream flashrom aes key fpga core fbs
security in low-pow er flash devices 17-8 v1.5 permanent security setting options in applications where a permanent lock is not desired, yet the security settings should not be modifiable, igloo and proasic3 device s can accommodate th is requirement. this application is partic ularly useful in cases where a device is located at a remote location and must be reprogrammed with a design or data update. refer to the "application 3: nontrusted environment?field updates/upgrades" section on page 17-10 for further discus sion and examples of how this can be achieved. the user must be careful when considering the permanent flashlock or permanent security settings option. once the design is programmed wi th the permanent settings, it is not possible to reconfigure the security settings already employed on the device . therefore, exercise careful consideration before prog ramming permanent settings. permanent flashlock the purpose of the permanent lock feature is to provide the benefits of the highest level of security to igloo and proasic3 devices. if sele cted, the permanent flashlock feature will create a permanent barrier, preventing an y access to the contents of th e device. this is achieved by permanently disabling write and ve rify access to the array, and write and read access to the flashrom. after permanently lock ing the device, it has been ef fectively rendered one-time- programmable. this feature is usef ul if the intended applications do not require design or system updates to the device. security in action this section illustrates some applications of the security advantages of actel?s devices ( figure 17-6 ). note: flash blocks are only used in fusion devices. figure 17-6 ? security options plaintext source file aes encryption cipher text source file public domain aes decryption core flashrom flash blocks flash device application 3 application 2 application 1 fpga core
security in low-pow er flash devices v1.5 17-9 application 1: trusted environment as illustrated in figure 17-7 on page 17-10 , this application allows th e programming of devices at design locations where research and developmen t take place. therefore, encryption is not necessary and is optional to the user. this is of ten a secure way to prot ect the design, since the design program files are not sent elsewhere. in situations where production programming is not available at the design location, programming centers (suc h as actel in-house programming) provide a way of programming designs at an al ternative, secure, and trusted location. in this scenario, the user generates a st apl programming file from the de signer software in plaintext format, containing information on the entire design or the portion of the design to be programmed. the user can choose to employ the flashlock pass key feature with the design. once the design is programmed to unprogrammed devices, the design is protected by this flashlock pass key. if no future programming is needed, the us er can consider permanen tly securing the igloo and proasic3 device, as discussed in the "permanent flashlock" section on page 17-8 . application 2: nontrusted en vironment?unsecured location often, programming of devices is not performe d in the same location as actual design implementation, to redu ce manufacturing cost. overseas programming centers and contract manufacturers are examples of this scenario. to achieve security in this case, the aes key and the flashlock pass key can be initially programmed in-house (trusted environment). this is done by generating a programming file with only the security settings and no design contents. the de sign fpga core, flashrom, and (for fusion) fb contents are generated in a separate programming file. this programming fi le must be set with the same aes key that was used to prog ram to the device previously so the device will correctly decrypt this encrypted programming file. as a result, th e encrypted design content programming file can
security in low-pow er flash devices 17-10 v1.5 be safely sent off-site to nontrusted pr ogramming locations for design programming. figure 17-7 shows a more detailed fl ow for this application. application 3: nontrusted environment?field updates/upgrades programming or reprogramming of devices may occur at remote locations. reconfiguration of devices in consumer products/equipment through public networks is one example. typically, the remote system is already programmed with particul ar design contents. when design update (fpga array contents update) and/or data upgrade (fla shrom and/or fb contents upgrade) is necessary, an updated programming file with aes encryption can be generated, sent across public networks, and transmitted to the remote system. reprogramm ing can then be done using this aes-encrypted programming file, providing easy and secure field upgrades. low-power flash devices support this secure isp using aes. the detailed flow for this application is shown in figure 17-8 on page 17-11 . refer to microprocessor programming of actel?s low-power flash devices for more information. to prepare devices for this scenar io, the user can initially genera te a programming file with the available security setting options. this programming file is programmed into the devices before shipment. during the prog ramming file generation step, the user has the option of making the security settings permanent or not. in situatio ns where no changes to the security settings are necessary, the user can select this feature in the software to generate the programming file with permanent security settings. actel recommends th at the programming file use encryption with an aes key, especially when isp is done via public domain. for example, if the designer wants to use an aes key for the fpga array and the flashrom, permanent needs to be chosen for this setting. at first, the user chooses the options to use an aes key for the fpga array and the flashrom, and then chooses permanently lock the security settings . a unique aes key is chosen. once this pr ogramming file is generated and programmed to notes: 1. programmed portion indi cated with dark gray. 2. programming of fbs applies to fusion only. figure 17-7 ? application 2: device programmin g in a nontrusted environment trusted environment nontrusted manufacturing environment flash device aes and/or pass key protected programming file fpga/flashrom/fbs contents security settings generates design contents encrypted with aes generates and programs security settings only (programming of the security keys) programs design contents to devices ships devices to manufacturer sends file(s) to manufacturer oem customers returns programmed devices to vendor ships programmed devices to end customer flash device flash device oem fpga/flashrom/fbs security settings* fpga/flashrom/fbs security settings
security in low-pow er flash devices v1.5 17-11 the devices, the aes key is permanently stored in the on-chip memory, where it is secured safely. the devices are sent to distant locations for the in tended application. when an update is needed, a new programming file must be generated. the pr ogramming file must use the same aes key for encryption; otherwise, th e authentication will fail and the fi le will not be programmed in the device. flashrom security use models each of the subsequent sections describes in detail the available selections in actel designer as an aid to understanding security ap plications and generating appropriate programming files for those applications. before proceeding, it is helpful to review figure 17-7 on page 17-10 , which gives a general overview of the programming file generati on flow within the desi gner software as well as what occurs during the device programming stage. specific settings are discussed in the following sections. in figure 17-7 on page 17-10 , the flow consists of two sub- flows. sub-flow 1 describes programming security settings to the device only, and sub-flow 2 describes programming the design contents only. in application 1, described in the "application 1: trusted environment" section on page 17-9 , the user does not need to generate separate files but can generate one programming file containing both security settings and design contents. then programming of the secu rity settings and design contents is done in one step. both sub-flow 1 and sub-flow 2 are used. in application 2, described in the "application 2: nontrusted envi ronment?unsecured location" section on page 17-9 , the trusted site should follow sub-fl ows 1 and 2 separately to generate two separate programming files. the programming file from sub-flow 1 will be used at the trusted site to program the device(s) first. the programming fi le from sub-flow 2 will be sent off-site for production programming. figure 17-8 ? application 3: nontrust ed environment?field updates/upgrades remote environment / system trusted environment generates updated design contents encrypted with aes original design contents aes encrypted and flashlock pass key protected oem aes encrypted programming file transmits to remote system update/upgrade flash device
security in low-pow er flash devices 17-12 v1.5 in application 3, described in the "application 3: nontrusted environment?field updates/upgrades" section on page 17-10 , typically only sub-flow 2 will be used, because only updates to the design content portion are needed and no security settings need to be changed. in the event that update of the se curity settings is necessary, see the "reprogramming devices" section on page 17-21 for details. for more information on programming low-power flash devices, refer to in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 . note: if programming the security header only, just perform sub-flow 1. if programming design content on ly, just perform sub-flow 2. figure 17-9 ? security programming flows software generates programming file with desired security settings: ? encrypted with aes and protected with flashlock pass key ? protected with flashlock pass key only program design contents program security settings user 1 2 designer software programming software programming previously secured device(s)? yes no no software generates programming file with desired design contents (fpga array, flashrom, fb, or all) yes no device previously programmed? software performs comparison of flashlock pass key between programming file and device software performs comparison of flashlock pass key between programming file and device encrypted design content passes through mac for authentication software programs selected security settings into device no does flashlock pass key match? does flashlock pass key match? yes no returns error returns error yes correct? yes no aes key used previously? yes user assigns desired security settings to fpga/flashrom/fb/all: ? aes key and flashlock pass key ? flashlock pass key only user must reassign exact flashlock pass key previously programmed into the device user must reassign exact aes key previously programmed into the device software generates programming file with flashlock pass key and design contents design content programmed into device software generates programming file with encrypted design contents design content decrypted and programmed into device
security in low-pow er flash devices v1.5 17-13 generating programming files generation of the programming file in a trusted environment? application 1 as discussed in the "application 1: trusted environment" section on page 17-9 , in a trusted environment, the user can choose to program the device with pl aintext bitstream content. it is possible to use plaintext for programming even when the flashlock pass key option has been selected. in this application, it is not necessary to employ ae s encryption prot ection. for aes encryption settin gs, refer to the next sections. the generated programming file w ill include the security setting (if selected) and the plaintext programming file content for the fpga array, flashrom, and/or fbs. these options are indicated in table 17-2 and table 17-3 . for this scenario, generate th e programming file as follows: 1. select the silicon features to be programmed (security settings, fpga array, flashrom, flash memory blocks), as shown in figure 17-10 on page 17-14 and figure 17-11 on page 17-14 . click next . if security settings is selected (i.e., the flashlock secu rity pass key feature), an additional dialog will be displayed to prompt you to se lect the security level setting. if no security setting is selected, you wi ll be directed to step 3. table 17-2 ? igloo and proasic3 plaintext security options, no aes security protection flashrom only fpga core only both flashrom and fpga no aes / no flashlock ??? flashlock only ??? aes and flashlock ? ? ? table 17-3 ? fusion plaintext security options security protection flashrom only fpga core only fb core only all no aes / no flashlock ???? flashlock ???? aes and flashlock ? ? ? ? note: for all instructions, the programming of flash blocks refers to fusion only.
security in low-pow er flash devices 17-14 v1.5 figure 17-10 ? all silicon features selected fo r igloo and proasic3 devices figure 17-11 ? all silicon features selected for fusion
security in low-pow er flash devices v1.5 17-15 2. choose the appropriate security level setting and enter a flas hlock pass key. the default is the medium security level ( figure 17-12 ). click next . if you want to select different options for the fpga and/or flashrom, this can be set by clicking custom level . refer to the "advanced options" section on page 17-22 for different custom security level options and descriptions of each. figure 17-12 ? medium security level selected for low-power flash devices
security in low-pow er flash devices 17-16 v1.5 3. choose the desired settings for the flashrom configurations to be programmed ( figure 17-13 ). click finish to generate the stapl prog ramming file fo r the design. generation of security head er programming file only? application 2 as mentioned in the "application 2: nontrusted environm ent?unsecured location" section on page 17-9 , the designer may employ flashlock pass key protection or flashl ock pass key with aes encryption on the device before sending it to a nontrusted or unsecured location for device programming. to achieve this, th e user needs to generate a programming file containing only the security settings desired (secur ity header programming file). note: if aes encryption is configured, flashlock pa ss key protection must also be configured. the available security op tions are indicated in table 17-4 and table 17-5 on page 17-17 . figure 17-13 ? flashrom configuration setting s for low-power flash devices table 17-4 ? flashlock security option s for igloo and proasic3 security option flashrom only fpga core only both flashrom and fpga no aes / no flashlock ? ? ? flashlock only ??? aes and flashlock ???
security in low-pow er flash devices v1.5 17-17 for this scenario, generate th e programming file as follows: 1. select only the security settings option, as indicated in figure 17-14 and figure 17-15 on page 17-18 . click next . table 17-5 ? flashlock security options for fusion security option flashrom only fpga core only fb core only all no aes / no flashlock ? ? ? ? flashlock ???? aes and flashlock ???? figure 17-14 ? programming igloo and proasi c3 security settings only
security in low-pow er flash devices 17-18 v1.5 2. choose the desired se curity level se tting and enter the key(s). ?the high security level employs flashlock pass key with aes key protection. ?the medium security level employs flashl ock pass key protection only. figure 17-15 ? programming fusion se curity settings only figure 17-16 ? high security level to implement flas hlock pass key and aes key protection
security in low-pow er flash devices v1.5 17-19 table 17-6 and table 17-7 show all available options. if you want to implement custom levels, refer to the "advanced options" section on page 17-22 for information on each option and how to set it. 3. when done, click finish to generate the security header programming file. generation of programming f iles with aes encryption? application 3 this section discusses how to ge nerate design content programming files needed specifically at unsecured or remote locations to program devices with a security header (flashlock pass key and aes key) already programmed ( "application 2: nontrusted en vironment?unsecured location" section on page 17-9 and "application 3: nontrusted envi ronment?field updates/upgrades" section on page 17-10 ). in this case, the encrypted programm ing file must correspond to the aes key already programmed into the device. if aes encr yption was previously se lected to encrypt the flashrom, fbs, and fpga array, ae s encryption must be set when generating the programming file for them. aes encrypti on can be applied to the flashrom on ly, the fbs only, the fpga array only, or all. the user must ensure both the flashloc k pass key and the aes key match those already programmed to the device(s), and all securi ty settings must matc h what was previously programmed. otherwise, the encryption and/or device unlocking will not be recognized when attempting to program the devi ce with the programming file. the generated programming fi le will be aes-encrypted. in this scenario, generate th e programming file as follows: 1. deselect security settings and select the portion of the device to be programmed ( figure 17-17 on page 17-20 ). select programming previously secured device(s ). click next . table 17-6 ? all igloo and proasic3 head er file security options security option flashrom only fpga core only both flashrom and fpga no aes / no flashlock ??? flashlock only ??? aes and flashlock ??? note: ? = options that may be used table 17-7 ? all fusion header fi le security options security option flashrom only fpga core only fb core only all no aes / no flashlock ???? flashlock ???? aes and flashlock ????
security in low-pow er flash devices 17-20 v1.5 choose the high security level to reprogram devices usin g both the flashlock pass key and aes key protection ( figure 17-18 on page 17-21 ). enter the aes key and click next . a device that has already been secured with fl ashlock and has an aes key loaded must recognize the aes key to program the device and generate a valid bitstream in authen tication. the flashlock key is only required to unlock the device and change the security settings. this is what makes it possible to program in an untrusted environm ent. the aes key is protected inside the device by the flashlock key, so you ca n only program if you have the correct aes key. in fact, the aes key is not in the programming file eith er. it is the key used to encrypt the data in the file. the same key previously programmed with the flashlock key matche s to decrypt the file. an aes-encrypted file programmed to a device without flashlock would not be secure, since without flashlock to protect the aes key, someon e could simply reprogram the aes key first, then program with any aes key desired or no aes key at all. this option is therefore not available in the software. note: the settings in this figure are used to show the ge neration of an aes-encrypted programming file for the fpga array, flashrom, and fb contents. one or all locations may be selected for encryption. figure 17-17 ? settings to program a device secured wi th flashlock and using aes encryption
security in low-pow er flash devices v1.5 17-21 programming with this file is intended for an unsecured enviro nment. the aes key encrypts the programming file with the same aes key already us ed in the device and utilizes it to program the device. reprogramming devices previously programmed devices can be reprogrammed using the steps in the "generation of the programming file in a trusted environm ent?application 1" section on page 17-13 and "generation of security header programming file only?application 2" section on page 17-16 . in the case where a flashlock pass key has been pr ogrammed previously, the user must generate the new programming file with a flashlock pass key that matches the one previously programmed into the device. the software will ch eck the flashlock pass key in th e programming file against the flashlock pass key in the device. the keys must match before the device can be unlocked to perform further progra mming with the new programming file. figure 17-10 on page 17-14 and figure 17-11 on page 17-14 show the option programming previously secured device(s) , which the user should select befo re proceeding. upon going to the next step, the user will be notifi ed that the same flashlock pass key needs to be entered, as shown in figure 17-19 on page 17-22 . figure 17-18 ? security level set high to re program device with aes key
security in low-pow er flash devices 17-22 v1.5 it is important to note that when the security se ttings need to be update d, the user also needs to select the security settings check box in step 1, as shown in figure 17-10 on page 17-14 and figure 17-11 on page 17-14 , to modify the security settings. the user must consid er the following: ? if only a new aes key is necessary, the user must re-enter the same pass key previously programmed into the device in designer and then generate a programming file with the same pass key and a different aes key. this en sures the programming file can be used to access and program the device and the new aes key. ? if a new pass key is necessary, the user can generate a new programming file with a new pass key (with the same or a new aes key if desired). however, for programming, the user must first load the orig inal programming file with the pass key that was previously used to unlock the device. then the ne w programming file can be used to program the new security settings. advanced options as mentioned, there may be app lications where more complicated security setting s are required. the ?custom security levels? section in the flashpro user's guide describes different advanced options available to aid the user in obta ining the best availabl e security settings. figure 17-19 ? flashlock pass key, previously programmed devices
security in low-pow er flash devices v1.5 17-23 programming file header definition in each stapl programming file generated, ther e will be information ab out how the aes key and flashlock pass key are configured. table 17-8 shows the header definitions in stapl programming files for different security levels. example file headers stapl files generated with flashlock key and aes key containing key information ? flashlock key / aes ke y indicated in stapl file header definition ? intended only for secu red/trusted environment programming applications ============================================= note "creator" "designer version: 6.1.1.108"; note "device" "a3pe600"; note "package" "208 pqfp"; note "date" "2005/04/08"; note "stapl_version" "jesd71"; note "idcode" "$123261cf"; note "design" "counter32"; note "checksum" "$edb9"; note "save_data" "fromstream"; note "security" "keyed encrypt "; note "alg_version" "1"; note "max_freq" "20000000"; note "silsig" "$00000000"; note "pass_key" "$00123456789012345678901234567890"; note "aes_key" "$abcdefabcdefabcdefabcdefabcdefab"; ============================================== table 17-8 ? stapl programming fi le header definitions by security level security level stapl f ile header definition no security (no flashlock pass key or aes key) note "security" "disable"; flashlock pass key with no aes key note "security" "keyed "; flashlock pass ke y with aes key note "security" "keyed encrypt "; permanent security settings option enabled note "security" "permlock encrypt "; aes-encrypted fpga array (f or programming updates) note "security" "encrypt core "; aes-encrypted flashrom (for programming updates) note "security" "encrypt from "; aes-encrypted fpga array and flashrom (for programming updates) note "security" "encrypt from core ";
security in low-pow er flash devices 17-24 v1.5 stapl file with aes encryption ? does not contain aes key / flashlock key information ? intended for transmission through web or serv ice to unsecured locations for programming ============================================= note "creator" "designer version: 6.1.1.108"; note "device" "a3pe600"; note "package" "208 pqfp"; note "date" "2005/04/08"; note "stapl_version" "jesd71"; note "idcode" "$123261cf"; note "design" "counter32"; note "checksum" "$ef57"; note "save_data" "fromstream"; note "security" "encrypt from core "; note "alg_version" "1"; note "max_freq" "20000000"; note "silsig" "$00000000"; conclusion the new and enhanced security features offered in actel fusion, igloo, and proasic3 devices provide state-of-the-art security to designs programmed into thes e flash-based devices. actel low- power flash devices employ the encryption standard used by nist and the u.s. government?aes using the 128-bit rijndael algorithm. the combination of an on-chip ae s decryption engine and actel fl ashlock technology provides the highest level of security against invasive attack s and design theft, impl ementing the most robust and secure isp solution. these security features protect ip within the fp ga and protect the system from cloning, wholesale ?black box? copying of a de sign, invasive attacks, and explicit ip or data theft. glossary term explanation security header programming file programming file used to program the flashlock pass ke y and/or aes key into the device to secure the fpga , flashrom, and/or fbs. aes (encryption) key 128-bit key defined by the user wh en the aes encryption option is set in the actel designer software when genera ting the programming file. flashlock pass key 128-bit key defined by the user when the flashlock option is set in the actel designer software when generating the programming file. the flashlock key protects the security se ttings programmed to the device. once a device is programmed with flashlock, whatever settings were chosen at that time are secure. flashlock the combined security features that protect the device content from attacks. these features are the following: ? flash technology that does not require an external bitstream to program the device ? flashlock pass key that secures device co ntent by locking the security settings and preventing access to the device as defined by the user ? aes key that allows secure, encrypted device reprogrammability
security in low-pow er flash devices v1.5 17-25 references national institute of standards and techno logy. ?advanced encryption standard (aes) questions and answers.? 28 january 2002 (10 january 2005). see http://csrc.ni st.gov/archive/ aes/index1.html for more information. related documents handbook documents flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf programming proasic3/e using a microprocessor http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf fusion embedded flash memory blocks http://www.actel.com/documents/fusion_flash_hbs.pdf user?s guides flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf
security in low-pow er flash devices 17-26 v1.5 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-014-5 revised august 2009 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.5) page v1.4 (december 2008) the "coremp7 device security" section was removed from "security in arm- enabled low-power flash devices" , since m7-enabled de vices are no longer supported. 17-4 v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 17-1 flash-based fpgas . 17-2 v1.2 (june 2008) the "security support in flas h-based devices" section was revised to include new families and make the information more concise. 17-2 v1.1 (march 2008) the following changes were made to the family descriptions in table 17-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 17-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 17-2
v1.5 18-1 18 ? in-system programming (isp) of actel?s low- power flash devices using flashpro3 introduction actel's low-power flash devices are all in-syste m programmable. this do cument describes the general requirements for programming a device and specific requirem ents for the flashpro3 programmer. fusion, igloo, ? and proasic ? 3 devices offer a low-power, single -chip, live-at-power-up solution with the asic advantages of security and low unit cost through nonvolatile flash technology. each device contains 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications such as internet protocol (ip) addressing, user system preference storage, device serialization, or subscription-based business mo dels. fusion, igloo, and proasic3 devices offer the best in-system prog ramming (isp) solu tion, flashlock ? security features, and aes- decryption-based isp. isp architecture low-power flash devices support is p via jtag and require a single v pump voltage of 3.3 v during programming. in addition, programming via a microc ontroller in a target sy stem is also supported. refer to microprocessor programming of actel?s low-power flash devices . family-specific support: ? fusion, proasic3, and proasic3e devices support isp. ? proasic3l devices operate using a 1.2 v core voltage and support isp at 1.5 v only. voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming. ? igloo and iglooe v5 devices can be progra mmed in-system when the device is using a 1.5 v supply voltage to the fpga core. ? all igloo v2 and proasic3l de vices can be operated at any voltage between 1.2 v and1.5 v. designer software allows 50 mv increments in the voltage. although devices can operate at 1.2 v core voltage, a device can only be re programmed when the co re voltage is 1.5 v. voltage switching is required in-syste m to switch from a 1.2 v supply (v cc ,v cci , and v jtag ) to 1.5 v for programming. igloo devices cannot be programmed in-system when the device is in flash*freeze mode. the device should exit flash*freeze mode and be in normal operation for programming to start. programming operations in igloo devices can be ac hieved when the device is in normal operating mode and a 1.5 v core voltage is used. jtag 1532 fusion, igloo, and proasic3 devices support the jtag-based ieee 1532 standard for isp. to start jtag operations, the igloo device should exit flash*freeze mode and be in normal operation before starting to send jtag commands to the device . as part of this support, when a device is in an unprogrammed state, all user i/o pins are disabl ed. this is achieved by keeping the global io_en signal deactivated, which also has the effect of disabling the input buffers. th e sample/preload instruction captures the status of pads in parallel and shifts them ou t as new data is shifted in for loading into the boundary scan register (bsr). wh en the device is in an unprogrammed state, the sample/preload instruction has no effect on i/o st atus; however, it will co ntinue to shift in new data to be loaded into the bsr. therefore, when sample/preload is used on an unprogrammed device, the bsr will be loaded with undefined da ta. for jtag timing inform ation on setup, hold, and fall times, refer to the flashpro user?s guide .
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 18-2 v1.5 isp support in flash-based devices the flash fpgas listed in table 18-1 support the isp feature and th e functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 18-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 18-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 18-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.5 18-3 programming voltage (v pump ) and v jtag low-power flash devices support on-chip charge pu mps, and therefore require only a single 3.3 v programming voltage for the v pump pin during programming. when the device is not being programmed, the v pump pin can be left floating or can be ti ed (pulled up) to any voltage between 0 v and 3.6 v. during programming, the target board or the flashpro3 programmer can provide v pump . flashpro3 is capable of supplying v pump to a single device. if more than one device is to be programmed using flashpro3 on a given board, flashpro3 should not be relied on to supply the v pump voltage. low-power flash device i/os support a bank-based, voltage-supply ar chitecture that simultaneously supports multiple i/o voltage standards ( table 18-2 on page 18-3 ). by isolating the jtag power supply in a separate bank from the user i/os, lo w-power flash devices prov ide greater flexibility with supply selection and simpli fy power supply and printed circuit board (pcb) design. the jtag pins can be run at any voltage fro m 1.5 v to 3.3 v (nominal). acte l recommends that tck be tied to gnd or v jtag when not used. this preven ts a possible totemp ole current on the input buffer stage. for tdi, tms, and trst pins, the devi ces provide an internal nominal 10 k pull-up resistor. during programming, all i/o pins, except for jtag inte rface pins, are tristated and weakly pulled up to v cci . this isolates the part and prevents the sign als from floating. the jtag interface pins are driven by the flashpro3 during programming, including the trst pin, which is driven high. ieee 1532 (jtag) interface the supported industry-standard ieee 1532 prog ramming interface buil ds on the ieee 1149.1 (jtag) standard. ieee 1532 defines the standardized process and methodology for isp. both silicon and software issues are addre ssed in ieee 1532 to create a si mplified isp environment. any ieee 1532?compliant programmer can be used to program low-power flash devices. however, only limited security and flashrom fe atures are supported when usin g the ieee 1532 standard. the actel flashpro3 programmer was de veloped exclusively for these de vices and will support all the security and device serialization features. refer to the standard for detail ed information about ieee 1532. security unlike sram-based fpgas that require loading at power-up from an extern al source such as a microcontroller or boot prom, actel nonvolatile devices are live at power-up, and there is no bitstream required to load the device when power is applied. the unique flash-based architecture prevents reverse engineer ing of the programmed code on the device, because the programmed data is stored in nonvolatile memory cells. each nonvolatile memory cell is made up of small capacitors and any physical deconstruction of th e device will disrupt sto red electrical charges. each low-power flash device has a built-in 128-bit advanced encryption st andard (aes) decryption core, except for the 30 k gate devices and smaller. any fpga core or flashrom content loaded into the device can optionally be sent as encrypted bitstream and decrypted as it is loaded. this is table 18-2 ? power supplies power supply programming mode current during programming v cc 1.5 v < 70 ma v cci 1.5 v / 1.8 v / 2.5 v / 3.3 v (bank-selectable) i/os are weakly pulled up. v jtag 1.5 v / 1.8 v / 2.5 v / 3.3 v < 20 ma v pump 3.0 v to 3.6 v < 80 ma note: all supply voltages should be at 1.5 v or hi gher, regardless of the setting during normal operation.
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 18-4 v1.5 particularly suitable for applicatio ns where device updates must be transmitted over an unsecured network such as the internet. th e embedded aes decryption core can prevent sensitive data from being intercepted ( figure 18-1 on page 18-4 ). a single 128-bit aes key (32 hex characters) is used to encrypt fpga core programming data and/or flashr om programming data in the actel tools. the low-power flash devices also decrypt with a single 128-bit aes key. in addition, low-power flash devices support a message authentication code (mac) for authentication of the encrypted bitstream on-chip. this allows the encrypted bitstream to be au thenticated and pr events erroneous data from being programmed into the device. the fpga core, flas hrom, and flash memory blocks (fbs), in fusion only, can be updated independentl y using a programming file that is aes-encrypted (cipher text) or uses plain text. security in arm-enabled low-power flash devices there are slight differences between the regular flash device and the arm ? -enabled flash devices, which have the m1 and m7 prefix. the aes key is used by actel and preprogrammed into the device to protect the arm ip. as a result, the design will be encrypted along with the arm ip, according to the details below. cortex-m1 device security cortex-m1?enabled devices are shipped wi th the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for aes-encrypted write and verify ? fusion embedded flash memory enabled for aes encrypted write figure 18-1 ? aes-128 security features actel designer software programming file generation with aes encryption flash device decrypted bitstream mac validation aes decryption fpga core, flashrom, fbs transmit medium / public network encrypted bistream user encryption aes key
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.5 18-5 figure 18-2 shows different applications for isp programming. 1. in a trusted programming environment, you can program the device using the unencrypted (plaintext) programming file. 2. you can program the aes key in a trusted pr ogramming environment and finish the final programming in an untrusted environment using the aes-encrypted (cipher text) programming file. 3. for the remote isp updating/reprogramming, th e aes key stored in the device enables the encrypted programming bitstream to be tra nsmitted through the untrusted network connection. actel low-power flash devices also provide the uniq ue actel flashlock feature, which protects the pass key and aes key. unless the original flashloc k pass key is used to unlock the device, security settings cannot be modified. low-power flash devices do not su pport read-back of fpga core- programmed data; however, the flashrom contents can selectively be read back (or disabled) via the jtag port based on th e security settings established by the actel designer software. refer to security in low-pow er flash devices for more information. figure 18-2 ? different isp use models source plain text aes encryption source encrypted bitstream tcp/ip flashrom aes decryption fpga core igloo or proasic3 device option 1 option 2 option 3
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 18-6 v1.5 flashrom and programming files each low-power flash device has 1 kbit of on-chip, nonvolatile flash memory that can be accessed from the fpga core. this nonvolatile flashrom is arranged in eight pages of 128 bits ( figure 18-3 ). each page can be programmed independently, wi th or without the 128-bi t aes encryption. the flashrom can only be programmed via the ieee 1532 jtag port and cannot be programmed from the fpga core. in addition, during programming of the flashrom, the fpga core is powered down automatically by the on-chi p programming control logic. using flashrom combined with aes, many subscription-based applic ations or device serialization applications are po ssible. smartgen supports easy manage ment of the flashrom contents even over large numbers of devices. smartgen ca n support flashrom cont ents that contain the following: ?static values ? random numbers ? values read from a file ? independent updates of each page in addition, auto-incrementing of fields is poss ible. in applications where the flashrom content is different for each device, you have the option to generate a single stapl file for all the devices or individual serializatio n files for each device. for more in formation on how to generate the flashrom content for device serialization, refer to flashrom in actel?s lo w-power flas h devices . actel libero ? integrated designed envi ronment (ide) includes a un ique tool to support the generation and management of flashrom and fpga programming files. this tool is called flashpoint. depending on the applications, designers can use th e flashpoint software to generate a stapl file with different contents. in each ca se, optional aes encryption and/or different security settings can be set. in designer, when you click the programming file icon, flashpoint launches, and you can generate stapl file(s) with four different cases ( figure 18-4 on page 18-7 ). when the serial ization feature is used during the configuration of flashrom in smartgen, you can generate a single stapl file that will program all the devices or an individual stapl file for each device. the following cases present the fp ga core and flashrom programming file combinations that can be used for different applications. in each case, yo u can set the optional se curity settings (flashlock pass key and/or aes key) depending on the application. 1. a single stapl file or multiple stapl file s with multiple flashr om contents and the fpga core content. a single stapl file will be gene rated if the device seri alization feature is not used. you can program the whole flashrom or selectively program individual pages. 2. a single stapl file for the fpga core content figure 18-3 ? flashrom architecture 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte number in page page number
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.5 18-7 3. a single stapl file or multiple stapl files wi th multiple flashrom contents. a single stapl file will be generated if the device serializ ation feature is not used. you can program the whole flashrom or selectivel y program individual pages. 4. a single stapl file to config ure the security settings for th e device, such as the aes key and/or pass key. programming solution for device programming, any ieee 1532?complian t programmer can be used; however, the flashpro3 programmer must be used to control the low-power flash device's rich security features and flashrom programming options. the flas hpro3 programmer is a low-cost portable programmer for the actel flash families. it can al so be used with a powered usb hub for parallel programming. general specif ications for the flashpro3 programmer are as follows: ? programming clock ? tck is used with a ma ximum frequency of 20 mhz, and the default frequency is 4 mhz. ? programming file ? stapl ? daisy chain ? supported. you can use the chainbuilder software to build the programming file for the chain. ? parallel programming ? supported. multiple flashpro3 programmers can be connected together using a powered usb hub or through the multiple usb ports on the pc. ? power supply ? the target board must provide v cc , v cci , v pump , and v jtag during programming. however, if there is only on e device on the target board, the flashpro3 programmer can generate the required v pump voltage from the usb port. figure 18-4 ? flexible programming file genera tion for different applications actel's designer software suite fpga core content single/multiple flashrom content(s) flashrom configuration file (*.ufc) smartgen fpga core content security settings single/multiple flashrom content(s) programming file (flashpoint) netlist security settings security settings security settings 1234
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 18-8 v1.5 isp programming header information the flashpro3 programming cabl e connector can be connected with a 10-pin, 0.1"-pitch programming header. the recommended programming headers are manufactured by amp (103310-1) and 3m (2510-6002ub). if you have limited board space, you can use a compact programming header manufactured by samtec (ftsh-105-01-l-d-k). using this compact programming header, you are required to order an additional header adapter manufactured by actel (fp3-26pin-adapter). existing proasic plus family customers who are using the sa mtec small programming header (ftsh- 113-01-l-d-k) and are planning to migrate to igloo or proasic3 devices can order a separate adapter kit from actel (fp3-10pin -adapter-kit), which contains a compact 10-pin adapter kit as well as 26-pin migration capability . table 18-3 ? programming header ordering codes manufacturer part nu mber description amp 103310-1 10-pin, 0.1"-pitch cabl e header (right-angle pcb mount angle) 3m 2510-6002ub 10-pin, 0.1"-pitch ca ble header (straight pcb mount angle) samtec ftsh-113-01-l-d-k small programming header supported by flashpro and silicon sculptor samtec ftsh-105-01-l-d-k com pact programming header samtec ffsd-05-d-06.00-01-n 10-pin cable with 50 mil pitch sockets; included in fp3- 10pin-adapter-kit. actel fp3-10pin-adapter-kit compac t header and migration kit figure 18-5 ? programming header (top view) table 18-4 ? programming header pin numbers and description pin signal source description 1 tck programmer jtag clock 2 gnd 1 ? signal reference 3 tdo target board test data output 4 nc ? no connect 5 tms programmer test mode select 6v jtag target board jtag supply voltage 7v pump 2 programmer/target board programming supply voltage 8 ntrst programmer jtag test reset (hi-z with 10 k pull-down, high, low, or toggling) 9 tdi programmer test data input 10 gnd 1 ? signal reference notes: 1. both gnd pins must be connected. 2. flashpro3 can provide v pump if there is only one device on the target board. 12 34 56 78 9 tck tdo tms v tdi gnd nc trst gnd 10 pump v jtag
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.5 18-9 board-level considerations a bypass capacitor is required from v pump to gnd for all low-po wer flash devices during programming. this bypass capacitor protects the de vices from voltage spikes that may occur on the v pump supplies during th e erase and programming cycles. refer to pin descriptions for specific recommendations. for proper programming, 0.01 f and 0.33 f capaci tors (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. the bypass ca pacitor must be placed within 2.5 cm of the device pins. troubleshooting signal integrity symptoms of a signal integrity problem a signal integrity problem can ma nifest itself in many ways. the problem may show up as extra or dropped bits during serial communication, changing the meaning of the communication. there is a normal variation of threshold voltage and freque ncy response between pa rts even from the same lot. because of this, the effects of signal integrity may not always affect different devices on the same board in the same way. so metimes, replacing a device ap pears to make signal integrity problems go away, but this is just masking the pr oblem. different parts on identical boards will exhibit the same problem sooner or later. it is important to fix signal integrity problems early. unless the signal integrity problems are severe enough to completely block all communication between the device and the programmer, they ma y show up as subtle problems. some of the flashpro3 exit codes that are caus ed by signal integrity problems ar e listed below. signal integrity problems are not the only possible cause of these errors, but this list is intended to show where problems can occur. flashpro3 allows tck to be lowered from 24 mhz down to 1 mhz to allow you to address some signal integrit y problems that may oc cur with impedance mismatching at higher frequencies. chain integrity test error or analyze chain failure normally, the flashpro3 analyze chain command expects to see 0x2 on the tdo pin. if the command reports reading 0x0 or 0x3, it is seeing the tdo pin stuck at 0 or 1. the only time the tdo figure 18-6 ? board layout and progra mming header top view v cc v cci v jtag gnd tck tdo tms v pump tdi c1 c2 trst 1 tck 2 gnd 3 tdo 4 nc 5 tms 6 v jtag 7 v pump 8 trst 9 tdi 10 gnd low-power flash device v cc from the target board v jtag from the target board v cci from the target board polarizing notch
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 18-10 v1.5 pin comes out of tristate is when the jtag tap state machine is in th e shift-ir or shift-dr state. if noise or reflections on the tck or tms lines ha ve disrupted the correct state transitions, the device's tap state controller migh t not be in one of these two sta tes when the programmer tries to read the device. when this happens, the output is floating when it is read and does not match the expected data value. this can also be caused by a broken tdo net. only a small amount of data is read from the device during the analyze chai n command, so marginal problems may not always show up during this command. exit 11 this error occurs during the verify stage of pr ogramming a device. after programming the design into the device, the device is veri fied to ensure it is programmed correctly. the verification is done by shifting the programmi ng data into the device . an internal comparison is performed within the device to verify that all switches are programmed correctly. noise induced by poor signal integrity can disrupt the writes and reads or the verification process and produce a ve rification error. while technically a verification error, the root cause is often related to signal integrity. refer to the flashpro user's guide for other error messages and solu tions. for the most up-to-date known issues and so lutions, refer to http://www.actel.com/support . conclusion fusion, igloo, and proasic3 devices offer a low-cost, single-chip solution that is live at power-up through nonvolatile flash technology. the flashloc k pass key and 128-bit aes key security features enable secure isp in an untrusted environmen t. on-chip flashrom enables a host of new applications, including device serialization, subscription-based applications, and ip addressing. additionally, as the flashrom is nonvolatile, all of these services can be provided without battery backup. related documents handbook documents microprocessor programming of actel?s low-power flash devices http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf security in low-pow er flash devices http://www.actel.com/l pd_security_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf user?s guides flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.5 18-11 part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-015-5 revised august 2009 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.5) page v1.4 (december 2008) the "coremp7 device security" section was removed from "security in arm- enabled low-power flash devices" , since m7-enabled de vices are no longer supported. 18-4 v1.3 (october 2008) the "isp architecture" section was revised to includ e information about core voltage for igloo v2 and proasic3l de vices, as well as 50 mv increments allowable in de signer software. 18-1 igloo nano and proasic3 nano devices were added to table 18-1 flash-based fpgas . 18-2 a second capacitor was added to figure 18-6 board layout and programming header top view . 18-9 v1.2 (june 2008) the "isp support in flash- based devices" section was revised to include new families and make the in formation more concise. 18-2 v1.1 (march 2008) the following changes were made to the family descriptions in table 18-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 18-2 v1.0 (january 2008) the "isp architecture" section was updated to included the igloo plus family in the discussion of family-specific supp ort. the text, "when 1.2 v is used, the device can be reprogrammed in-system at 1.5 v only," was revised to state, "although the device can operate at 1.2 v core voltage, the device can only be reprogrammed when all supplies (v cc , v cci , and v jtag ) are at 1.5 v." 18-1 the "isp support in flash-based devices" section and table 18-1 flash-based fpgas were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 18-2 the "security" section was updated to mention that 15 k gate devices do not have a built-in 128-bit decryption core. 18-3 table18-2power supplies was revised to remove the normal operation column and add a table note stating, "all supply voltages should be at 1.5 v or higher, regardless of the setting during normal operation." 18-3 the "isp programming header information" section was revised to change fp3-26pin-adapter to fp3-10pin-adapter-kit. table 18-3 programming header ordering codes was updated with the same change, as well as adding the part number ffsd-05-d-06.00-01-n, a 10-pin cable with 50-mil-pitch sockets. 18-8 the "board-level consid erations" section was updated to describe connecting two capacitors in parallel across v pump and gnd for proper programming. 18-9
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 18-12 v1.5 51900055-2/7.06 informatio n was added to the "programming voltage (vpump) and vjtag" section about the jtag interface pin. 18-3 51900055-1/1.05 actgen was changed to smartgen. n/a in figure 18-6 board layout and programming header top view , the order of the text was changed to: v jtag from the target board v cci from the target board v cc from the target board 18-9 previous version changes in current version (v1.5) page
v1.4 19-1 19 ? microprocessor programming of actel?s low- power flash devices introduction the fusion, igloo, ? and proasic ? 3 families of flash fpgas supp ort in-system programming (isp) with the use of a microprocessor. flash-based fp gas store their configuration information in the actual cells within the fpga fabric. sram-based devices need an external configuration memory, and hybrid nonvolatile devices store the configurat ion in a flash memory inside the same package as the sram fpga. since the prog ramming of a true flash fpga is si mpler, requiring only one stage, it makes sense that programming with a micropro cessor in-system should be simpler than with other sram fpgas. this reduces bill-of-materials costs and printed circuit board (pcb) area, and increases system reliability. nonvolatile flash technology also gives the low-pow er flash devices the advantage of a secure, low- power, live-at-power-up, and single-chip solution. low-power flash devices are reprogrammable and offer time-to-market benefits at an asic-lev el unit cost. these features enable engineers to create high-density systems using existing asic or fpga design flows and tools. this document is an introduction to microprocessor programming only. to explain the difference between the options avai lable, user's guides for directc and stapl provide more detail on implementing each style. figure 19-1 ? isp using microprocessor mi c ropro c essor internal ram i/o fun c tions j ta g bus flash devi c e internal/external memory running directc on board memory device .dat file
microprocessor programming of actel?s low-power flash devices 19-2 v1.4 microprocessor programming support in flash devices the flash-based fpgas listed in table 19-1 support programming with a microprocessor and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 19-1 . where the information appl ies to only one device or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 19-1 . where the information applies to only one device or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 19-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
microprocessor programming of actel?s low-power flash devices v1.4 19-3 programming algorithm jtag interface the low-power flash families ar e fully compliant with the ieee 1149.1 (jtag) standard. they support all the mandatory bounda ry scan instructions (extest, sample/preload, and bypass) as well as six optional public instructions (usercode, idcode, highz, and clamp). ieee 1532 the low-power flash families ar e also fully compliant with th e ieee 1532 programming standard. the ieee 1532 standard adds progra mming instructions and associat ed data registers to devices that comply with the ieee 1149.1 standard (jtag). these in structions and regi sters extend the capabilities of the ieee 1149.1 standard such th at the test access port (tap) can be used for configuration activities. the ieee 1532 standar d greatly simplifies the programming algorithm, reducing the amount of time needed to implement microprocessor isp. implementation overview to implement device programming with a microprocess or, the user should first download the c- based stapl player or directc code from the actel website . (see the actel website for future updates regarding the stapl player and directc code). using the easy-to-follow actel user's guide, create the low-level application programming interface (api) to provide the necessary basic functions. these api fu nctions act as the interface betwee n the programming software and the actual hardware ( figure 19-2 ). the api is then linked with the stapl player or directc and compiled us ing the microprocessor's compiler. once the en tire code is compiled, the user must do wnload the resulting binary into the mcu system's program memory (s uch as rom, eeprom, or flash). the system is now ready for programming. to program a design into the fpga, the user cr eates a bitstream or stapl file using the actel designer software, downloads it into the mcu system's volatile memory, and activates the stored programming binary file ( figure 19-3 on page 19-4 ). once the programming is completed, the bitstream or stapl file can be removed from the sy stem, as the configuration profile is stored in the flash fpga fabric and does not need to be reloaded at every system power-on. figure 19-2 ? device programming code relationship stapl file stapl player or directc api programming algorithm and data programming software i/o and memory functions
microprocessor programming of actel?s low-power flash devices 19-4 v1.4 flashrom actel low-power flash devices have 1 kbit of user-accessible, nonvolatile, flashrom on-chip. this nonvolatile flashrom can be programmed along with the core or on its own using the standard ieee 1532 jtag programming interface. the flashrom is architected as eight pages of 128 bits. each page can be individually programmed (erased and written). additionally, on-chip aes security decryption can be used selectively to load data securely into the flashrom (e.g., over public or private networks, such as the internet). refer to flashrom in actel?s low-power flash devices . figure 19-3 ? mcu fpga programming model programming software source code microprocessor compiler bin file download to system program device programming file
microprocessor programming of actel?s low-power flash devices v1.4 19-5 stapl vs. directc programming the low-power flash devices is perf ormed using directc or the stapl player. both tools use the stapl file as an input. directc is a compiled language, whereas stapl is an interpreted language. microprocessors will be ab le to load the fpga using directc much more quickly than stapl. this speed advantage becomes more apparent when lower clock speeds of 8- or 16-bit microprocessors are used . directc also requires less memory than stapl, since the programming algorithm is directly implemented. stapl does have one advantage over directc? the ability to upgrade. when a new programming algo rithm is required, the stapl user simply needs to regenerate a stapl file using the latest version of the designer software and download it to the system. the directc user must download the latest versio n of directc from actel, compile everything, and down load the result into the system ( figure 19-4 ). figure 19-4 ? stapl vs. directc stapl flow directc flow directc source code input stapl file microprocessor compiler bin file generate the new stapl file download to system program device download to system program device
microprocessor programming of actel?s low-power flash devices 19-6 v1.4 remote upgrade via tcp/ip transmission control protocol (tcp) provides a reliable bitstream transfer service between two endpoints on a network. tcp depends on intern et protocol (ip) to move packets around the network on its behalf. tcp protects against data lo ss, data corruption, packet reordering, and data duplication by adding checksums and sequence numb ers to transmitted data and, on the receiving side, sending back packets and acknowledging the receipt of data. the system containing th e low-power flash device can be assign ed an ip address when deployed in the field. when the device requires an update (core or flashrom), the programming instructions along with the new programming data (aes-encrypted cipher text) can be sent over the internet to the target system via the tcp/ip protocol. once the mcu receives the instruction and data, it can proceed with the fpga update. low-power flash devices support message authentication code (mac), which can be used to validate data for the target device. more details are given in the "message authentication code (mac) validation/authentication" section on page 19-6 . hardware requirement to facilitate the programming of the low-power flash families, the system must have a microprocessor (with access to the device jtag pins) to process the programming algorithm, memory to store the pr ogramming algorithm, pr ogramming data, and the necessary programming voltage. refer to the relevant da tasheet for programming voltages. security read-back prevention the low-power flash devices are designed with securi ty in mind. even without any security measures (such as flashlock with aes), it is not po ssible to read back the programming data from a programmed device. upon programming completi on, the programming algo rithm will reload the programming data into the device. the device will then use built-in circuitry to determine if it was programmed correctly. as an additional se curity measure, the device s are equipped with aes de cryption. aes works in two steps. the first step is to program a key into the devices in a secure or trusted programming center (such as actel in-house programmi ng (ihp) center). the second step is to encrypt any programming files with the same encryption key. the encrypted programming file will only work with the devices that have the same key. the aes used in the low-p ower flash families is the 128-bit aes decryption engine (rijndael algorithm). message authentication code (mac) validation/authentication as part of the aes decryption flow, the devices are equipped with a mac validation/authentication system. mac is an authentication tag, also called a checksum, derived by applying an on-chip authentication scheme to a stapl file as it is loaded into the fpga. macs are computed and verified with the sa me key so they can only be verified by the intended recipi ent. when the mcu system receives the aes-encrypted programming da ta (cipher text), it can validate the data by loading it into the fpga and perfo rming a mac verification prior to loading the data, via a second programming pass, into the fpga core cells. th is prevents erroneous or corrupt data from getting into the fpga. low-power flash devices with aes and mac are superior to devices with only des or 3des encryption. because the mac veri fies the correctness of the data, the fpga is protected from erroneous loading of invalid programming data that could damage a device ( figure 19-5 on page 19-7 ). the aes with mac enables field updates over public networks without fear of having the design stolen. an encrypted programming file can only work on devices with the correct key, rendering
microprocessor programming of actel?s low-power flash devices v1.4 19-7 any stolen files useless to the thief. to learn more about th e low-power flash devices? security features, refer to security in low-pow er flash devices . conclusion the actel fusion, igloo, and proasi c3 fpgas are ideal for applicatio ns that require field upgrades. the single-chip devices save board space by el iminating the need for eeprom. the built-in aes with mac enables transmission of programming da ta over any network without fear of design theft. fusion, igloo, and proasic3 fpgas are i eee 1532?compliant and support stapl, making the target programming software easy to implement. figure 19-5 ? proasic3 device encryption flow proasic3 aes encryption encrypted stream aes decryption encrypted stream designer software decrypted stream mac validation programming control aes key tcp/ip public network
microprocessor programming of actel?s low-power flash devices 19-8 v1.4 related documents handbook documents flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf security in low-pow er flash devices http://www.actel.com/docum ents/lpd_secu rity_hbs.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-016-4 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 19-1 flash- based fpgas . 19-2 v1.2 (june 2008) the "microprocessor progra mming support in flash devices" section was revised to include new fa milies and make the in formation more concise. 19-2 v1.1 (march 2008) the following changes were made to the family descriptions in table 19-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 19-2 v1.0 (january 2008) the "microprocessor progra mming support in flash devices" section was updated to include information on the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 19-2
boundary scan and ujtag

v1.4 20-1 20 ? boundary scan in low-power flash devices boundary scan low-power flash devices are comp atible with ieee standard 11 49.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. jtag operations are used during boundary scan testing. the basic boundary scan logic circuit is composed of the tap controller, test data registers, and instruction register ( figure 20-2 on page 20-4 ). low-power flash devices support three types of test data registers: bypass , device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device. this speeds up test data transfer to othe r devices in a test data path. the 32-bit device identification register is a shift re gister with four fields (lsb, id number, part number, and version). the boundary scan register observes and controls th e state of each i/o pin. each i/o cell has three boundary scan register cells, each with serial-in, serial-out, parallel-in, and parallel-out pins. tap controller state machine the tap controller is a 4-bit state machin e (16 states) that operates as shown in figure 20-1 . the 1s and 0s represent the values that must be present on tm s at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and gene rates control and clock signals for the rest of the test lo gic architecture. on power-up, th e tap controller enters the test- logic-reset state. to guarantee a reset of the co ntroller from any of the possible states, tms must remain high for five tck cycles. the trst pin can also be us ed to asynchronously place the tap controller in the test-logic-reset state. figure 20-1 ? tap controller state machine 1 test_logic_reset run_test_idle select_dr capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr select_ir capture_ir shift_ir exit1_ir pause_ir exit2_ir update_ir 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1
boundary scan in lo w-power flash devices 20-2 v1.4 actel?s flash devices support the jtag feature the flash-based fpgas listed in table 20-1 support the jtag feature an d the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 20-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 20-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 20-1 ? flash-based fpgas series family * description igloo ? igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proasic ? 3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
boundary scan in low-power flash devices v1.4 20-3 boundary scan support in low-power devices the information in this document applies to all fusion, igloo, and proasi c3 devices. for igloo, igloo plus, and proasic3l devices, the flash*freeze pin must be deasserted for successful boundary scan operations. devices cannot en ter jtag mode directly from flash*freeze mode. boundary scan opcodes low-power flash devices support all ma ndatory ieee 1149.1 instructions (extest, sample/preload, and bypass) and the optional id code instruction ( table 20-2 ). boundary scan chain the serial pins are used to serial ly connect all the boundary scan register cells in a device into a boundary scan register chain ( figure 20-2 on page 20-4 ), which starts at the tdi pin and ends at the tdo pin. the parallel ports are co nnected to the internal core logi c i/o tile and the input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. each test section is accessed through the tap, which has five associated pins : tck (test clock input), tdi, tdo (test data input and output), tms (test mo de selector), and trst (test reset input). tms, tdi, and trst are equipped with pu ll-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary scan test usage. refer to the "jtag pins" description in pin descriptions for pull-up/-down recommendat ions for tdo and tck pins. table 20-2 ? boundary scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff
boundary scan in lo w-power flash devices 20-4 v1.4 board-level recommendations table 20-3 gives pull-down recommendations for the trst and tck pins. figure 20-2 ? boundary scan chain device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers table 20-3 ? trst and tck pull-down recommendations v jtag tie-off resistance* v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k * equivalent parallel resistance if more than one device is on jtag chain ( figure 20-3 )
boundary scan in low-power flash devices v1.4 20-5 related documents handbook documents pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf note: tck is correctly wired with an equivalent tie-off resistance of 500 , which satisfies the table for v jtag of 1.5 v. the resistor values for trst are not appropriate in this case, as the tie-off resistance of 375 is below the recommended minimum for v jtag = 1.5 v, but would be appropriate for a v jtag setting of 2.5 v or 3.3 v. figure 20-3 ? parallel resistance on jtag chain of devices tdi tdi tdi tdi tdo tdo tdo tdo jtag header actel fpga 1 actel fpga 2 actel fpga 3 actel fpga 4 2 k 2 k 2 k 2 k 1.5 v tck trst vjtag gnd 1.5 k 1.5 k 1.5 k 1.5 k
boundary scan in lo w-power flash devices 20-6 v1.4 part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-019-3 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 20-1 flash-based fpgas . 20-2 v1.2 (june 2008) the "boundary scan support in low-power devices" section was revised to include new families and make the information more concise. 20-3 v1.1 (march 2008) the following changes were made to the family descriptions in table 20-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 20-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 20-2
v1.4 21-1 21 ? ujtag applications in actel?s low-power flash devices introduction in fusion, igloo, ? and proasic ? 3 devices, there is bidirectional access from the jtag port to the core versatiles during normal operation of the device ( figure 21-1 ). user jtag (ujtag) is the ability for the design to use the jtag ports for access to the device for up dates, etc. while regular jtag is used, the ujtag tiles, located at the southeast area of the die, are directly connected to the jtag test access port (tap) controller in normal operatin g mode. as a result, all the functional blocks of the device, such as clock conditioning circ uits (cccs) with plls, sram blocks, embedded flashrom, flash memory blocks, and i/o tiles, can be reached via the jtag ports. the ujtag functionality is avai lable by instantiating the ujtag macro dire ctly in the source code of a design. access to the fpga core versatiles from the jtag ports enables users to implement different applications using the tap controller (jtag port). this document introduces the ujtag tile functionality and discusses a few application examples. however, th e possible applications are not limited to what is presented in this document. uj tag can serve different purposes in many designs as an elementary or auxiliary part of the de sign. for detailed usag e information, refer to boundary scan in low-power flash devices . figure 21-1 ? block diagram of using ujtag to read flashrom contents from addr [6:0] data[7:0] clk enable sdo sdi reset addr[6:0] data[7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] control ujtag address generation and data serlialization
ujtag applications in acte l?s low-power flash devices 21-2 v1.4 ujtag support in flash-based devices the flash-based fpgas listed in table 21-1 support the ujtag feature and the functions described in this document. igloo terminology in documentation, the terms igloo series and iglo o devices refer to all of the igloo devices as listed in table 21-1 . where the information appl ies to only one product line or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, the terms proasic3 series a nd proasic3 devices refer to all of the proasic3 devices as listed in table 21-1 . where the information applies to on ly one product line or limited devices, these exclusions will be explicitly stated. to further understand the differences between th e igloo and proasic3 devices, refer to the industry?s lowest power fpgas portfolio . table 21-1 ? flash-based fpgas series family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo nano the industry?s lowest-power , smallest-size solution igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3 nano lowest-cost soluti on with enhanced i/o capabilities proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l automotive proasic3 proasic3 fpgas qualified fo r automotive applications fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft pr ocessors, and flash memory into a monolithic device note: *the device names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
ujtag applications in acte l?s low-power flash devices v1.4 21-3 ujtag macro the ujtag tiles can be instantiated in a design using the ujtag macro from the fusion, igloo, or proasic3 macro library. note that "ujtag" is a reserved name and cannot be used for any other user-defined blocks. a bloc k symbol of the ujtag tile macro is presented in figure 21-2 . in this figure, the ports on the left side of the bloc k are connected to the jt ag tap controller, and the right-side ports are accessib le by the fpga core versatiles. the td i, tms, tdo, tck, and trst ports of ujtag are only provided for design simulation pu rposes and should be treated as external signals in the design netl ist. however, these ports must not be connected to any i/o buffer in the netlist. figure 21-3 on page 21-4 illustrates the correc t connection of the uj tag macro to the user design netlist. actel de signer software will auto matically connect these ports to the tap during place-and-route. table 21-2 gives the port descriptions for the rest of the ujtag ports: table 21-2 ? ujtag port descriptions port description uireg [7:0] this 8-bit bus carries the contents of the jtag instruction regi ster of each device. instruction register values 16 to 127 are not reserved and can be employed as user-defined instructions. urstb urstb is an active-low signal and will be asserted when the ta p controller is in test-logic-reset mode. urstb is asserted at power-up, and a pow er-on reset signal resets the tap controller. urstb will stay asserted until an external tap access changes the tap controller state. utdi this port is directly conn ected to the tap's tdi signal. utdo this port is the user tdo ou tput. inputs to the utdo port are sent to the tap tdo output mux when the ir address is in user range. udrsh active-high sign al enabled in the shiftdr tap state udrcap active-high signal enab led in the capturedr tap state udrck this port is directly conn ected to the tap's tck signal. udrupd active-high sign al enabled in the updatedr tap state figure 21-2 ? ujtag tile block symbol tdi tck tdo tms trst uireg0 uireg1 uireg2 uireg3 uireg4 uireg5 uireg6 uireg7 utdi utdo udrck udrcap udrsh udrupd urstb
ujtag applications in acte l?s low-power flash devices 21-4 v1.4 ujtag operation there are a few basic functions of the ujtag macr o that users must understand before designing with it. the most important fundamental concept of the ujtag design is its connection with the tap controller state machine. tap controller state machine the 16 states of the tap controll er state machine are shown in figure 21-4 on page 21-5 . the 1s and 0s, shown adjacent to the sta te transitions, represent the tm s values that must be present at the time of a rising tck edge for a state transiti on to occur. in the state s that include the letters "ir," the instruct ion register operates; in the states that contain the letters "dr," the test data register operates. the tap controller receives tw o control inputs, tms and tck, and generates control and clock signals for the rest of the test logic. on power-up (or the assertion of trst), the tap controller ente rs the test-logic-reset state. to reset the controller from any other state, tms must be held high for at least five tck cycles. after reset, the tap state changes at the rising edge of tck, based on the value of tms. note: do not connect jtag pins (tdo, tdi, tms, tck, or trst) to i/os in the design. figure 21-3 ? connectivity method of ujtag macro tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] inputs outputs tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] inputs outputs a) correct instantiation b) incorrect instantiation fpga versatiles fpga versatiles
ujtag applications in acte l?s low-power flash devices v1.4 21-5 ujtag port usage uireg[7:0] hold the contents of the jtag instruct ion register. the uireg vector value is updated when the tap controller state mach ine enters the update_ir state. in structions 16 to 127 are user- defined and can be employed to encode multiple applications and commands within an application. loading new instructions into the uireg vector requires users to send appropriate logic to tms to put the tap controll er in a full ir cycle starting from the select ir_scan state and ending with the update_ir state. utdi, utdo, and udrck are directly connected to the jtag tdi, tdo, and tck ports, respectively. the tdi input can be used to provide either data (t ap controller in the shift_dr state) or the new contents of the instruction register (t ap controller in the shift_ir state). udrsh, udrupd, and udrcap are high when the tap controller state machine is in the shift_dr, update_dr, and capture_dr states, respectively. therefore, they act as flags to indicate the stages of the data shift process. these flags are useful fo r applications in which blocks of data are shifted into the design from jtag pins. for example, an active udrsh can indicate that utdi contains the data bitstream, and udrupd is a candida te for the end-of -data-stream flag. as mentioned earlier, users should not connect the tdi, tdo, tck, tms, and trst ports of the ujtag macro to any port or net of the design ne tlist. the designer soft ware will automatically handle the port connection. figure 21-4 ? tap controller state diagram run_test/ idle 0 test_logic_reset 1 0 1 select_ dr_scan update_dr exit2_dr pause_dr exit1_dr shift_dr capture_dr select_ ir_scan update_ir exit2_ir pause_ir exit1_ir shift_ir capture_ir 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1
ujtag applications in acte l?s low-power flash devices 21-6 v1.4 typical ujtag applications bidirectional access to the jtag port from versa tiles?without putting the device into test mode? creates flexibility to implement many different ap plications. this section describes a few of these. all are based on importing/exporting data through the ujtag tiles. clock conditioning circuitry ?dynamic reconfiguration in low-power flash devices, cccs, which include plls, can be configured dynamically through either an 81-bit embedded shift register or static flash programming switches. these 81 bits control all the characteristics of the ccc: routing mux archit ectures, delay values, divider values, etc. table 21-3 lists the 81 configuration bits in the ccc. the embedded 81-bit shift register (for the dynami c configuration of the ccc) is accessible to the versatiles, which, in turn, have access to the uj tag tiles. therefore, the ccc configuration shift register can receive and load the new configuration data stream from jtag. dynamic reconfiguration eliminates the need to reprogram the device when reconfiguration of the ccc functional blocks is needed. the ccc configur ation can be modified wh ile the device continues to operate. employing th e ujtag core requires the user to design a module to provide the configuration data and control the ccc configuratio n shift register. in esse nce, this is a user- designed tap controller re quiring chip resources. table 21-3 ? configuration bits of fusion, igloo, and proasic3 ccc blocks bit number(s) control function 80 reset enable 79 dyncsel 78 dynbsel 77 dynasel <76:74> vcosel [2:0] 73 statcsel 72 statbsel 71 statasel <70:66> dlyc [4:0] <65:61> dlyb {4:0] <60:56> dlyglc [4:0] <55:51> dlyglb [4:0] <50:46> dlygla [4:0] 45 xdlysel <44:40> fbdly [4:0] <39:38> fbsel <37:35> ocmux [2:0] <34:32> obmux [2:0] <31:29> oamux [2:0] <28:24> ocdiv [4:0] <23:19> obdiv [4:0] <18:14> oadiv [4:0] <13:7> fbdiv [6:0] <6:0> findiv [6:0]
ujtag applications in acte l?s low-power flash devices v1.4 21-7 similar reconfiguration capability exists in the actel proasic plus ? family. the only difference is the number of shift register bits controlling the ccc (27 in proasic plus and 81 in igloo, proasic3, and fusion). fine tuning in some applications, design constants or parame ters need to be modifi ed after programming the original design. the tuning process can be done using the ujtag tile without reprogramming the device with new values. if the parameters or constants of a design are stored in distributed registers or embedded sram bloc ks, the new values can be shifted onto the jtag tap controller pins, replacing the old va lues. the ujtag tile is used as the ?bridge? for data tr ansfer between the jtag pins and the fpga versatiles or sram logic. figure 21-5 shows a flow chart example for fine- tuning application steps using the ujtag tile. in figure 21-5 , the tms signal sets the ta p controller state machine to the appropriate states. the flow mainly consists of two steps: a) shifting the defined instructio n and b) shifting the new data. if the target parameter is constantly used in the de sign, the new data can be shifted into a temporary shift register from utdi. the udrsh output of uj tag can be used as a sh ift-enable signal, and udrck is the shift clock to the shift register . once the shift process is completed and the tap controller state is moved to the update_dr state , the udrupd output of the ujtag can latch the new parameter value from the temporary register into a permanent locati on. this avoids any interruption or malfunctioning during the serial shift of the new value. figure 21-5 ? flow chart example of fine-tun ing an application using ujtag yes no tap controller in test_logic_reset state set tap state to shift_ir shift the user-defined instruction of tuning application set tap state to update_ir latch the recorded data onto the location of stored parameter uireg equal to the user-defined instruction set tap state to shift_dr shift data into tdi and record utdi in a shift register set tap state in update_dr
ujtag applications in acte l?s low-power flash devices 21-8 v1.4 silicon testing and debugging in many applications, the design ne eds to be tested, debugged, and veri fied on real si licon or in the final embedded application. to debug and test th e functionality of designs, users may need to monitor some internal logic (or ne ts) during device operation. the approach of adding design test pins to monitor the critical intern al signals has many disadvantages, such as limiting the number of user i/os. furthermore, adding external i/os fo r test purposes may require additional or dedicated board area for testing and debugging. the ujtag tiles of low-power flash devices offer a flexible and cost-effective solution for silicon test and debug applications. in this solution, the signals under test are shifted out to the tdo pin of the tap controller. th e main advantage is that all the te st signals are monito red from the tdo pin; no pins or additional board-level resources are required. figure 21-6 illustrates this technique. multiple test nets are brought into an internal mux architecture. the selection of the mux is done using the contents of the tap cont roller instruction register, wher e individual instr uctions (values from 16 to 127) correspond to di fferent signals under test. the selected test signal can be synchronized with the rising or falling edge of tck (optional) and sent out to utdo to drive the tdo output of jtag. the test and debug procedure is not limited to the example in figure 21-5 on page 21-7 . users can customize the debug and test interf ace to make it appropriate for their applications. for example, multiple test signals can be registered and then se nt out through utdo, each at a different edge of tck. in other words, n signals are samp led with an f tck / n sampling rate. the bandwidth of the information sent out to tdo is always proportional to the frequency of tck. sram initialization users can also initialize embedded srams of the lo w-power flash devices. the initialization of the embedded sram blocks of the design can be done using ujtag tiles, where the initialization data is imported using the tap controller. similar functionality is available in proasic plus devices using jtag. the guidelines for implementation and design examples are given in the ram initialization and rom emulation in proasic plus devices application note. srams are volatile by nature; data is lost in th e absence of power. ther efore, the initialization process should be done at each power-up if necessary. figure 21-6 ? ujtag usage example in tes t and debug applications tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] clk dq internal test nets instruction decode to scope channel
ujtag applications in acte l?s low-power flash devices v1.4 21-9 flashrom read-back using jtag the low-power flash architecture contains a de dicated nonvolatile flashrom block, which is formatted into eight 128-bit pages. for more information on flashrom, refer to flashrom in actel?s low-power flash devices . the contents of flashrom are av ailable to the versatiles during normal operation through a read operation. as a result, the ujtag macro can be used to provide the flashrom contents to the jtag port duri ng normal operation. figure 21-7 illustrates a simple block diagram of using ujtag to read the contents of flashrom during normal operation. the flashrom read address can be provided from outside the fpga throug h the tdi input or can be generated internally using the core logic. in either case, data serialization logic is required ( figure 21-7 ) and should be designed using the versatile core logic. flashrom contents are read asynchronously in parall el from the flash memory and shifted out in a synchronous serial format to tdo. shifting the se rial data out of the seri alization block should be performed while the tap is in udrsh mode. the coordination between tck and the data shift procedure can be done using the tap state machine by monitori ng udrsh, udrcap, and udrupd. conclusion actel low-power flash fpgas offer many unique advantages, such as security, nonvolatility, reprogrammablity, and low power?all in a single chip. in addition, fusion, igloo, and proasic3 devices provide access to the jtag port from core versa tiles while the device is in normal operating mode. a wide range of available user-defined jtag opcodes allows users to implement various types of applications, exploiting this feature of these devices. the connection between the jtag port and core tiles is implemented through an embedded and hardwired ujtag tile. a ujtag tile can be instantiated in designs using the ujtag library cell. this document presents multiple examples of ujtag applications, such as dynamic reconfiguration, silicon test and debug, fine- tuning of the design, and ram initialization. each of these applications offers many useful advantages. figure 21-7 ? block diagram of using ujtag to read flashrom contents from addr [6:0] data[7:0] clk enable sdo sdi reset addr[6:0] data[7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] control ujtag address generation and data serlialization
ujtag applications in acte l?s low-power flash devices 21-10 v1.4 related documents application notes ram initialization and rom emulation in proasic plus devices http://www.actel.com/documents/apa_ram_initd_an.pdf handbook documents boundary scan in lo w-power flash devices http://www.actel.com/documen ts/lpd_boundaryscan_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information part number 51700094-020-4 revised december 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.4) page v1.3 (october 2008) igloo nano and proasic3 nano devices were added to table 21-1 flash-based fpgas . 21-2 v1.2 (june 2008) the "ujtag support in flash-based devices" section was revised to include new families and make the in formation more concise. 21-2 the title of table 21-3 configuration bits of fusion, igloo, and proasic3 ccc blocks was revised to include fusion. 21-6 v1.1 (march 2008) the following changes were made to the family descriptions in table 21-1 flash-based fpgas : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 21-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 21-2
board-level requirements

v1.1 22-1 22 ? fusion board-level design guidelines objective the successful design of pr inted circuit boards (pcbs) incorporating the actel fusion ? mixed-signal fpga requires good understanding of the mixed-si gnal nature of the fusi on chips. good board design practices are required to achieve the expe cted performance from th e pcb and fusion device and are essential to achieve high quality and reliable re sults, such as minimal noise levels, and adequate isolation between digital and analog domain. this chapter presents guidelines for board-level desi gn specific to applications using fusion mixed- signal fpgas. note that th ese guidelines should be treated as a supplement to standard board-level design practices. this document assumes readers are expe rienced in digital and analog board layout and knowledgeable in the electrical characteristics of mixed-signal systems. background information on the key theories and concepts of mixed-signal board-level design is available in high speed digital design: a handbook of black magic 1 , as well as in many reference text books and literature. analog and digital plane isolation since fusion is a mixed-signal product in which both analog and digital components exist, it requires both analog and digital supply and grou nd planes. in addition, there are several voltage supply and ground pins on the device to power different components on the die. this section discusses the layout of the different analog or digital planes and recommends schemes to efficiently isolate different digita l and analog domains from each othe r. this section also describes all ground and supply pins of the fusion device, required to operate the chip, and explains how to connect them to the existing digital or analog supply or ground planes. placement of fusion device and isolation of ground planes in applications using fusion devices, two separate grounds to the device should be provided: gnd (digital ground) and gnda (analog ground). the grou nd pins of the device are to be connected to one of the aforementioned ground plan es appropriately, as discussed in "isolation of ground planes" on page 22-3 . gnd is the digital ground plane that connects to all gnd pins of a fusion device. gnda is the analog grou nd plane that connec ts to all gnda pins of a fusion device. to avoid noise propagation from one plane to another (e.g. from digital to analog ground), the ground planes should be well isolated from each ot her. correct layout of the ground planes on the board for current and return paths in the board will prevent the noise in one plane to affect others. for example if the return path of a digital signal trace on the board passes through the ground analog plane, the anal og ground will be vulnerable to noise induced by the digital signal. therefore, it is critical for digital traces and comp onents on the board to be routed and placed only in the area of their corresponding layer that is covered by digita l ground in the ground plane. similar regulation should be applied to analog traces and components wi th respect to the analog ground as well. figure 22-1 on page 22-2 illustrates the aforem entioned regulation. in figure 22-1 on page 22-2 , digital component c and the traces th at connect to it overlap with the analog ground layout in the ground plane. this may cause some of the digital signaling current and return paths to pass through the analog domain and induce noise in this noise-sensitive domain. figure 22-1 on page 22-2 brings up a critical point: how a mixed-signal device, such as a fusion device, should be placed on the board. 1. johnson, howard, and martin graham, high speed digital design: a handbook of black magic. prentice hall ptr, 1993. isbn-10 0133957241 or isbn-13: 978-0133957242
fusion board-level design guidelines 22-2 v1.1 placement of fusi on device on board fusion devices contain both analog and digital components and can interface with other digital and analog compon ents on the board. a fusion device should be placed on boards such that analog signaling of the system falls within the boundaries of the analog ground and supply domain. similarly, digita l signaling of the system should fall within the boundaries of the digital domain. figure 22-2 shows a simple illustration of the placement of a fusion device on the board. as shown in figure 22-2 , the fusion chip is placed on the boundary of analog and digital domains, so that the analog pins of the fusion device are within the analog ground domain and the digital portion of the chip is placed within the digital ground domain. in complicated system designs a nd more complicated device pack ages, the placement of a fusion device may not be as straight forward as shown in the simplified diagram of figure 22-2 . however, in any board layout, it is critical to keep digital signals and their return paths well isolated from the figure 22-1 ? illustration of analog and digital components placement on boards figure 22-2 ? simple illustration of fusi on device placement on boards
fusion board-level design guidelines v1.1 22-3 analog domain. the "isolation of ground planes" section discusses an example of fusion placement and ground plane layout in a real -world mixed-signal system design. figure 22-2 on page 22-2 also shows that the analog and di gital grounds are to be connected to each other at a single point. the layout of the gr ound planes, as well as the power supp ly planes, plays a key role in reducing th e noise and hence enhancing the pe rformance and accuracy of the system. isolation of ground planes as mentioned in "placement of fusion device and isol ation of ground planes" on page 22-1 , the ground and supply planes should be divided in two main domains: digital (e.g. gnd) and analog (e.g. gnda). though there is no technical limita tion in implementing more ground and supply domains for other necessary ground and supply pins of a fusion device, the rest of the ground and supply pins can be connected to one of the aforementioned domains. in order to isolate the ground of different domains from each other, the ground plane (or planes) of the board should be split into two domains: gnd and gnda, as an example. the components and signaling in each domain should remain within the boundaries of each ground as discussed in "placement of fusion device and isol ation of ground planes" on page 22-1 and "placement of fusion device on board" on page 22-2 . however, since data and co ntrol signals usually exchange between different domains, a common connection between analog and digital grounds is needed to ensure the two planes are at the same pote ntial. connection between two grounds should be made only through a single point as shown figure 22-2 on page 22-2 . more than a single connection point between two grou nds can result in inter-domain current paths that can induce noise from one domain to another. furthermore, the sing le point connection should be as far as possible from the fusion device. figure 22-3 shows a real-world example of a ground plan e layout and the relative placement of the fusion chip. refer to the "analog and digital plane isolation" section on page 22-1 for board layout recommendations. note: blue = gnd, yellow = vcci, and green = gnda figure 22-3 ? example of ground plane layout and fusion device placement
fusion board-level design guidelines 22-4 v1.1 other ground pins of the fusion device can conn ect to one of the two grounds using traces on the board if necessary. however, the length of the trac es should be kep t as short as possible to reduce the trace inductance between ground pins and the ground plane. table 22-1 lists all the ground pins of a fusion device and the ground plane that they connect to. analog and digital voltage supply isolation digital and analog voltage supplies should be isolated from each other similar to the grounds as discussed in "placement of fusion device and isol ation of ground planes" on page 22-1 . there are three main power supplies to fusion devices: vcc33a (3.3 v analog supply), vcc (1.5 v digital core supply), and vcci (digital i/o supply). there may be multiple vcci levels (for digital i/os) since fusion devices offer multiple i/o banks. regardle ss of the number of power supply voltage levels, the layout of the board's power plans should conform to the same specifications as recommended for the ground plane in "placement of fusion device and isol ation of ground planes" on page 22-1 . none of the digital power domains should overlap with the analog power supply domain (vcc33a). this ensures that digital signaling and its return path s are well isolated form the analog power supply, minimizing no ise in the analog domain. figure 22-4 on page 22-5 shows a simple illustration of mixed-signal boar d layers and relative layout of the digita l and analog domains. table 22-1 ? ground pin connections to ground plate on board ground pin name ground domain gnd digital(gnd) gndq digital(gnd) adcgndref analog(gnda) gnda analog(gnda) gndaq analog(gnda) gndnvm digital(gnd) gndosc digital(gnd) vcomppla/b * digital(gnd) note: *older revisions of datasheets referred to a signal called vcomplf. this is now called vcompla/b.
fusion board-level design guidelines v1.1 22-5 as shown in figure 22-4 , no digital grounds or voltage supplies overlap with the analog domain. the ground plane is divided into two domains of analog and digital grou nd. the power planes in the figure 22-4 board stack up follow the same layout as the ground plane. the fusion device is placed on the boundary of the digital and analog domains as recommended in "placement of fusion device and isolation of ground planes" on page 22-1 . digital planes may be split if needed to accommodate ad ditional supplies. for example, the vcci plane can be split into 3.3 v and 2.5 v planes. the addition of another plane just to suppo rt the addition al supply is typically not needed. additionally, figure 22-4 emphasizes the layout of the signal traces in the signal layers of the board stack up. the digital signal traces are laid out within the digital do main and the analog traces are contained within the anal og area of the layer. other power pins of the fusion device can connec t to one of the two doma ins using traces on the board. however, the length of the traces should be kept as short as possible to reduce the trace inductance between power pins and the power plane, induced by board traces, to a minimum. figure 22-2 on page 22-2 shows that the analog and digital grounds are to be connected to each other at a single point. the same technique shou ld be applied to digita l and analog 3.3 v supplies. figure 22-4 ? simplified illustration of a mixed-signal board stack up
fusion board-level design guidelines 22-6 v1.1 table 22-2 lists all the power pins of a fusion device and the power plane that they connect to. similar to any other board-level designs, decoupling/bypass capacitors or other power supply filtering techniques should be used between power supply pins and ground to reduce any potential fluctuation on th e supply lines. actel's board-level considerations application note (http://www.actel.com/documents/boardlevelcons_an.pdf ) provides addition al recommendations on using decoupling capacitors. there are numerous other industry publications and guidelines available on the subject. other special function pins in addition to the general power and ground pins discussed in "analog and digital plane isolation" on page 22-1 , there are a few other special pins that re quire special board considerations to ensure proper functionality of the fusi on device. this section of the document lists these pins and describes their conn ectivity in the board-level design. varef this pin is the voltage reference for fusion?s anal og to digital converter (adc). the fusion device can provide a 2.56 v internal reference voltage. wh ile using the internal re ference, the reference voltage is output on varef for use as a system reference. if a different reference voltage is required, it can be exte rnally supplied to varef and used by the adc. since varef is the reference voltage for the adc, it is critical for varef (either internal or external) to be very clean. noise on varef affects the a ccuracy of the adc and ma y cause the analog system to operate outside the spec ification listed in the fusion family of mi xed-signal flash fpgas datasheet. for internal varef use model, actel recommends an external capacitor to be placed between varef and the analog ground, as close as possible to the vare f pin. actel recommends the capacitor value to be between 3.3 f to 22 f. high capacitor values (up to 22 f) result in better noise filtering and higher adc accuracy. however, the larger the capacitor value, the longer the rise time of varef at power- up. longer time of varef will in turn delay the power-up time to functional of the analog block . smaller capacitor values cause fast er power-up time for varef, but noise filtering will be relatively less. the choice of capacitor values al so depends on the total amount of noise existing on the user?s board. boar ds with relatively higher noise levels may need to table 22-2 ? power pin connections to power plane on board supply pin name supply domain vcc digital (vcc) vcc15a digital (vcc) vcc33a analog (vcc33a) vcc33pmp analog (vcc33a) vccnvm digital (vcc) vccosc digital (3.3v) 1 vccibx digital (vcci) 2 vccpla/b digital (vcc throug h recommended capacitors) 3 notes: 1. can be tied to any digi tal 3.3 v rail available in the applic ation board (e.g. vccibx if the bank requires a 3.3 v supply) 2. if multiple banks are powered with different supply levels, different vcci planes are needed for each voltage level 3. capacitor recommendations for vccpla/b pins are similar to those for the proasic3 family device and can be found at: http://www.actel.com/documents/lpd_ccc_hbs.pdf
fusion board-level design guidelines v1.1 22-7 have capacitor values close to 22 f and a vare f pin, and may not perform to expectation if the capacitor values are close to 3.3 f. when varef is provided by an external source, the source must be clean to ensure the highest accuracy of the adc. refer to the fusion family of mi xed-signal flash fpgas datasheet and the interfacing with th e fusion analog system: proc essor/microcontroller interface chapter for more information on selecting th e right capacitor value for internally generated varef. vcc33n, pcap, and ncap these three pins are asso ciated with the -3.3 v charge pump. this charge pump uses two external capacitors in order to generate the -3.3 v su pply. one capacitor is connected between the ncap and pcap pins, while the other is connected betw een vcc33n and the analog ground. the impulse charging of the capa citors, while the charge pump is in op eration, is a source of electromagnetic interference (emi). to reduce emi, each of these capacitors consist of a 0.1 f ceramic capacitor in parallel with a tantalum capacitor. the ceramic ca pacitors should be mounted as close as possible to the pins, using capacitors of small physical size . for the bga package, these capacitors are to be mounted on the bottom layer, dire ctly underneath the respective pins. the tantalum capacitors can be mounted a little furth er off, but users should try to mini mize the distance. ceramic capacitors are also available in higher values such as 2.2 f . if such a capacitor is used, the 0.1 f capacitor might not be needed. xtal1 and xtal2 these pins are input from external oscillators to fusion devices. very slow rise and fall times of typical oscillator output (input to xtal1 and xtal2 pins) are much more prone to any noise induced by the system, and can resu lt in the oscillator frequency to be misint erpreted by the fusion device. typical crystal oscillators generating low frequency signals, such as 32.768 khz, typically have very slow rise and fall times (sinusoidal si gnal). any small noise on the generated sine wave can result in misinterpretation of the frequency of the sine wave for the fusion device and affect the correct functi onality of the design. therefore, for very low frequency signals, such as 32.768 khz input to xtal inputs of th e fusion device, actel recommends users utilize a digital oscillator (fast rise and fall times) or to use schmitt trigger buffers to shorten the rise and fall time of typical oscillators. for signals at 1 mhz and above, since th e rise and fall times are inherently fast, a typical analog crystal oscillator can be us ed with no specific precaution. for the layout and connection of the external cr ystal and the associated capacitors, keep stray capacitance and inductance to a minimum. it is important to kee p any noise from coupling to the on-chip oscillator by way of the power supply, the crystal, the two load capacitors, or the copper traces used to connect these compon ents. it is also impo rtant to prevent noise from coupling from the oscillator into the analog power supply, affecting the perf ormance and accuracy of other analog circuitry. the following guide lines help achieve these objectives: ? the oscillator power supply pins should be decoupled by a 0.1 f capacitor connected as close as possible betw een the vccosc and gndosc pins of the fusion device. for a bga package, this capacitor can be placed on the bo ttom layer; and if it is size 402, it fits between the pins. ? the crystal should be placed as close as possible to the xtal1 and xtal2 pins. ? the spacing between traces connecting crysta l to xtal1 and xtal2 pins and nearby traces should be increased beyond the minimum spacing dictated by the pcb design rules to prevent any noise from coupling into these trac es. in addition, copper traces carrying high speed digital signal s should not be routed in parallel to the copper trace s connected to the xtal1 and xtal2 pins, eith er on the same layer or on the other layers. ? to reduce electromagnetic emi ssions and provide good mechanic al stability to the crystal, a copper pad slightly larger th an the crystal and grounded to gndosc should be placed on the top layer of the pcb. the metal package of the crystal should be grounded to this pad with a suitable clip. copper traces connected to this grounded pad and extending around the copper traces leading from the crystal to xtal1 and xtal2 pins shield these pins and further increase noise immunity of the oscillator. the shields add a very small amount of stray capacitance and this can be accounted fo r in the selection of the load capacitors.
fusion board-level design guidelines 22-8 v1.1 application-specific recommendations this section of the document discusses some re commendations that are sp ecific to temperature, voltage, or current monitoring applications. these recommendation s are merely for improving the accuracy of the applications. temperature monitor the temperature monitor generates a voltage of ab out 2.5 mv/k (per degree kelvin), as seen by the adc. however, the voltage change that appear s across the extern al discreet bipolar transistor may be much smaller. such low levels mean that precautions should be t aken to not couple noisy signals to the co nductors connecting the transistor to the temperature monitor pins. if the temperature sensing the di ode/transistor is connected to an actel fusion device through cables, actel recommends using a twin lead shielded cable to carry the at and atrtn traces with the shield of the cable grounded at the board. if the connections are made by copper traces on the pcb, at and atrtn traces should be routed in such a way that traces carrying di gital signal are not parallel to them above, below, or on the sides. to achieve this, lay the at and atrtn traces on the top layer, so that the next adjacent layer in the pcb stack is the ground layer. this provides for shielding against digital signals that can couple to the signals on the copper traces co nnected to the at and atrtn pins. if digital signal carrying traces can not be avoide d in the vicinity of the traces connec ting to the transistor, sufficient distance is to be created between the offending trace and the at or atrtn traces. it is important to minimize the resistance of the conductors connecting the external discrete bipolar transistor to the at and at rtn pins of the fusion chip. if pcb copper traces are used as the interconnecting conductors, they should be of such a width that, taking in to account th eir length, they contribute only a negligible voltage drop compared to 200 v. the current through the bipolar transistor used for sensing the temperat ure changes by 90 a du ring the measurement process. this current, multiplied by the total resistance of the copp er trace from the at pin to the transistor and from the transistor back to the atrt n pin, should be negligible compared to 200 v. if a shielded cable is used, the wire gauge of its conductors should be appropriately selected. if the system using the actel fusi on devices is to be operated at ot her than room temperature, the effect of temperature on the resistance of the wire or copper traces should also be taken into account. voltage and current monitor if any of the av channels are used in the direct mo de that is directly conn ecting to th e adc without prescalers, it is recommend that a ceramic capaci tor of the npo or cog variety, or better yet, a polyester capacitor of 2200 pf be placed from the corresponding av channel pin to the analog ground, and as close as possible to the av pin. a resistor of 100 should then be connected between the av pin and whatever point is being monitored by the particula r av channel. if the accuracy requir ements are not stringent, one may be able to get by without using th e above mentioned resistor/capacit or combination. however, it is good practice to at least make provision for these components on the prototype pcb. the adc is a switched capacitor design and needs to be driven from a low impedance. it draws a charging current every time a channel is sampled, and the capacitor helps to mainta in the voltage steady at the particular av pin during such intervals. all copper traces connecting to the av or the ac pins should stay with in the area covered by th e analog ground plane. the power for the adc, voltage and current monitors, and the internal voltage reference is provided from the same pins. these pins are to be adequately decoupled with 0.1 f ceramic x7r diel ectric capacitors in parallel with a tantalum capacitor of 22 f capacity. in applications using current monitor, it is im portant to route the av and ac signals of each channel in parallel and k eep the two traces matched as much as possible. large di fferences in the nets bringing av and ac signals to the device may cause signific ant inaccuracy in differential voltage across the av and ac pin.
fusion board-level design guidelines v1.1 22-9 in current monitor applic ations, the current sense resistor sh ould be chosen carefully so that optimal accuracy and resolu tion can be achieved. the fusion family of mi xed-signal flash fpgas datasheet describes the recommended resi stor values for vari ous current ranges. connection to pll table 22-1 on page 22-4 and table 22-2 on page 22-6 describe the connection of the vccpla/b and vcompla/b pins of the fusion device to the power and ground planes. this section of the document discusses how these pins and the dedica ted clock pins of the fusion device connect to the plls on the chip. connecting external signals into pll and powering them up should be done considering that afs090 and a fs250 devices contain only one pll, while afs600 and afs1500 devices contain two pll blocks. in afs090 and afs250 devices, the p ll is located on the west side of the die. in devices with two plls, the seco nd pll is placed on east side of the die 2 . table 22-3 shows the corresponding power and ground pins for each pll block in addition to hardwire clock pins, fusion device p lls can be driven by any internal net or external i/o pins. although the hardwire i/os can be used as any user i/o, if designers are required to minimize the propagation from external clock to the pll, hard wire clock pins of the pll provide the shortest paths from bo ard to pll clock input. table 22-4 lists the hardwire clock pins for each pll on the device. 2. refer to fusion family of mixed-signal flash fpgas datasheet for more information on clock conditioning circuits and location of plls. table 22-3 ? power and ground pin names for fusion device plls pll/device afs090 afs250 afs600 afs1500 west pll vccpla/vcompla vccpla/vcom pla vccpla/vcompla vccpla/vcompla east pll ? ? vccplb/vcomplb vccplb/vcomplb table 22-4 ? hardwire clock pin connections to pll pll/device afs090 afs250 afs600 afs1500 west pll gfa0/gfa1/gfa2 * gfa0/gfa1/gfa2* gfa0/gfa1/gfa2 gfa0/gfa1/gfa2 east pll ? ? gca0/gca1/gca2 gca0/gca1/gca2 note: * depending on the selected package, not all th ree hardwire clock i/os may be available.
fusion board-level design guidelines 22-10 v1.1 part number and revision date part number 51700092-012-1 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (august 2008) the "temperature monitor" section was revised to remove information about capacitors. 22-8
software design tutorials and examples

v1.0 23-1 23 ? fusion solutions, design examples, and reference designs the unprecedented level of integration of actel fusion ? enables a wide variety of functionality, such as power and thermal management, remote communications, and syste m clocking, in a single mixed-signal fpga. actel, the world leader of mixed-signal fpgas, now offers the only sing le-chip system management solution. the actel fusion mixed-signal fpga integrates configurable analog, large flash memory blocks, comprehensive clock generation and management circuitry, and high-performance programmable logic in a monolithic device. actel has develope d turn-key solutions, including a development kit and a software gui, for sy stem management. this level of integration, configurability, and support establishes fusion as the definitive system management solution. this chapter captures the design examples and reference design information for fusion applications in various aspects. system management applications system management continues to gain importance in the design of all electronic systems. smaller process geometries drive more multivolt devi ces and are more suscep tible to voltage and temperature fluctuations. whereas system manageme nt designs can run into hundreds of discrete components, the actel fusion mi xed-signal fpga solution can in tegrate these system management functions and provide programmable flexibility an d system-level integration?all in a single chip. unprecedented integration in fu sion devices can offer cost and space savings of 50% or greater relative to current implementations. white paper : system management using a mixed-signal fpga power management ? control up to 10 power supplies ? voltage monitoring ? current mo nitoring ? power-on detection and reset ? custom power mode topo logy support for total system power reduction ? power-up sequencing power supply monitoring application note: multi-channel analog voltage comparator in fusion fpgas ? vhdl design files ? verilog design files power sequencing application note: fusion power sequencing and ramp-rate control ? design files
fusion solutions, design ex amples, and reference designs 23-2 v1.0 motor control an obstacle to wide-scale use of electronic moto r control has been the high cost of the computer and power electronics . this obstacle is diminishing due to tremendous technology improvement in semiconductor processes and integration. the actel fusi on mixed-signal fpga offers unprecedented integration by combining mixed-sign al analog, flash memory , and fpga fabric in a monolithic psc. this means that for the first time, engin eers can combine the motor control analog front end, high-speed flash lookup tables, and deterministic algorithm proc essing capabilities of programmable logic in a single-chip solution. reference board: motor control reference board application note: pid control microtca actel provides highly integrat ed solutions for microtca syst em management. actel supports fusion-based solutions with refere nce designs, semiconductor intell ectual property (ip), software, and customization serv ices that enable quicker time to ma rket for actel customers with reduced risk, lower costs, and improved av ailability over existi ng solutions. the high integration of actel microtca solutions also pr ovides increased functional ity in a fixed form factor. nearly every electro nic system needs system management, especially those with telecommunications-driven standard s like microtca, atca, and amc, as well as those with server- driven standards like ipmi. fusion and proasic ? 3 are adept at supporting both proprietary and standards-based implementations. application note: actel fusion fpgas supporting intell igent peripheral management interface (ipmi) applications application note: microtca reference design: microtca power module reference design other applications single chip, live at power-up, embedded flash memory, and low power make fusion suitable for many other applications. application note: context save and reload ? design files application note: real-time calendar applications in actel fusion devices ? design files technical brief: using fusion fifo for generating periodic waveforms ? fusion sine table application note: using fusion ram as multipliers application note: configuring corepwm using rtl blocks ? verilog design files ? vhdl design files application brief: smart battery management applications
fusion solutions, design examples, and reference designs v1.0 23-3 development system fusion starter kit the fusion starter kit is an all-inclusive, low-cost evaluation kit for the actel fusion family. users can utilize this starter kit to explore the voltag e, current, and temperature monitor, real-time counter for low power use model, and embedd ed flash for context-saving applications. user?s guide: fusion starter kit user's guide & tutorial ? design files for fusion starter kit tutorial system management development kit the actel system management development kit pr ovides an excellent platform for developing system management applications and applications with a microprocessor. th e kit includes an arm- enabled fusion device, a system ma nagement gui, and a platform for systems that performs these functions: ? power-up detection ? power sequencing ? thermal management ? sleep modes ? system diagnostics ? remote communications ? clock generation and management ? data logging user?s guide: system management board user's guide part number and revision date part number 51700092-009-0 revised november 2007

v1.0 24-i 24 ? fusion glossary ab ? analog block acm ? analog configuration mult iplexer. stores configuratio n data for the analog quads. acmclk ? the clock input to the acm used for configuration/initialization of the analog quads: 10 mhz max. adc ? analog-to-digital converter adcclk ? the clock input to the ab used by the adc: 10 mhz max. adcstart ? request to the adc to begin sampling and convert a defined channel ahb ? advanced high-performance bu s. the ahb sits above the apb in the amba architecture and implements the features required for high-performance, high-clock-frequency systems, including burst transfers, split transactions, single-cycle bus master handover, single-clock-edge operation, non-tristate implementation, and wider data bus configurations (64/128 bits). amba ? advanced microc ontroller bus architecture . the amba protocol is an open-standard, on- chip bus specificat ion that details a strategy for th e interconnection and management of functional blocks. apb ? advanced peripheral bus. as part of the amba arch itecture, the apb is optimized for reduced interface complexity and is used to interface with low-bandwidth peripherals. asb ? analog system builder assc ? adc sample se quence controller ccc ? clock conditioning circuit, which may include a pll coreabc ? amba bus controller soft ip coreai ? analog interface ip fo r microprocessors/-controllers coreconsole ip deployment platform (idp) ? idp enabling users to c onstruct a processor subsystem and assemble ip blocks within a design ctrl_stat ? 8-bit register located within the ac m that defines the operation of the rtc designer ? actel's place-and-route tool, which allows users to assign i/os, evaluate timing, and generate programming files fpgagood ? signal from vrpsm indicating th e internal voltage regulator is on initclk ? initialization clock used in th e initialization client: 10 mhz max. libero ? integrated design environment (ide) ? actel's fpga design en vironment, integrating synthesis, simulation , place-and-route, design en try, and ip generation tools match ? signal indicating that rtc coun t register (counter) matches matchreg matchreg ? 40-bit register containing a user-defined value to be compared with rtc count register pclk ? apb interface clock pub ? power up (bar). fpga input wi th weak internal pull-up used to force power-up of internal voltage regulator pucore ? inverse of pub rtc ? real-time counter rtcpsmmatch ? match signal from rtc that is passe d to vrpsm to power up voltage regulator smarttime ? actel's static timing analysis tool, integrated into designer smev ? system monitor evaluation phase state machine smtr ? system monitor transi tion phase state machine stc ? sample time control setting for the acquisitio n time in asb
24-ii v1.0 tvc ? 8-bit user-configurable register that determi nes the division value required to bring the system clock to less that 10 mhz for the adc vrinitstate ? defines the voltage regu lator state upon power-up vrpsm ? voltage regulator power supply monitor vrpu ? voltage regulator power-up. internal, user-acc essible signal to turn off internal voltage regulator from fpga core part number and revision date part number 51700092-011-0 revised november 2007

51700092-017-4/8.09 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn actel is the leader in low-power and mixed-signal fp gas and offers the most comprehensive portfolio of system and power management solutions. po wer matters. learn more at www.actel.com. actel, igloo, actel fusion, proasic, libero, pigeon point and the associated logos are trademarks or registered trademarks of actel corporati on. all other trademarks and service marks are the property of their respective owners.

▲Up To Search▲

Price & Availability of AFS090-1FGG256I

	To Download AFS090-1FGG256I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .