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fedl63187b-06 1 semiconductor this version: sep. 2001 previous version: mar. 2000 ml63187b/63189b 4-bit microcontroller with built-in1024-dot matrix lcd drivers and melody circuit, operating at 0.9 v (min.) 1/36 general description the ml63187b and ml63189b are cmos 4-bit microcontroller with built-in 1024-dot matrix lcd drivers and operates at 0.9 v (min.). the ml63187b and 63189b are suitable for applications such as games, toys, watches, etc. which are provided with an lcd display. the ml63187b and ml63189b are m6318x series mask rom-version product of olms-63k family, which employs oki?s original cpu core nx-4/250. features ? rich instruction set 408 instructions transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, rom table reference, stack operations, flag operations, branch, conditional branch, call/return, control ? rich selection of addressing modes indirect addressing of four data memory types, with current bank register, extra bank register, hl register and xy register data memory bank internal direct addressing mode ? processing speed two clocks per machine cycle, with most instructions executed in one machine cycle minimum instruction execution time : 61 s (@32.768 khz system clock) 1 s (@2 mhz system clock) ? clock generation circuit low-speed clock : crystal oscillation or rc oscillation selected with mask option (30 to 80 khz) high-speed clock : ceramic oscillation or rc oscillation selected with software (2 mhz max.) ? program memory space ml63187b : 16 k words ml63189b : 32 k words basic instruction length is 16 bits/1 word ? data memory space ml63187b : 1024 nibbles ml63189b : 1536 nibbles ? stack level call stack level : 16 levels register stack level : 16 levels
fedl63187b-06 1 semiconductor ml63187b/63189b 2/36 ? i/o ports input ports: selectable as input with pull-up resistor/input with pull-down resistor/high-impedance input input-output ports: selectable as input with pull-up resistor/input with pull-down resistor/high-impedance input selectable as p-channel open drain output/n-channel open drain output/cmos output/high-impedance output can be interfaced with external peripherals that use a different power supply than this device uses. v dd is the power supply pin for ports. number of ports: ml63187b input-output port : 2 ports 4 bits ml63189b input port : 1 port 4 bits input-output port : 4 ports 4 bits ? melody output melody frequency : 529 to 2979 hz tone length : 63 types tempo : 15 types melody data : resides in the program memory buzzer driver signal output : 4 khz ? lcd driver number of segments : 1024 max. (64 seg 16 com) duty : 1/1 to 1/16 duty bias : selectable as 1/4 or 1/5 bias regulator circuit built-in frame frequency : 64 hz (at 1/16 duty) , 128 hz (at 1/8 duty ) , 256 hz (at 1/4 duty) , 512hz (at 1/2 duty) , 1024 hz (at 1/1 duty ) contrast : a maximum of 16 levels adjustable display modes : selectable s all-on mode/all-off mode/power down mode/normal display mode adjustable contrast. ? system reset function ? system reset by reset pin (built-in 2 khz reset sampling circuit can be selected by mask option) ? system reset by power-on detection (when not using 2 khz reset sampling circuit) ? system reset by detection that low-speed clock has stopped oscillation ? battery check low-voltage supply check the value of the judgment voltage is selected by the software by setting the ld1 and ld0 bits of bldcon. ld1 ld0 judgment voltage (v) remarks 0 0 1.05 0.10 ta = 25 c 0 1 1.20 0.10 ta = 25 c 1 0 1.80 0.10 ta = 25 c 1 1 2.40 0.10 ta = 25 c ? power supply backup backup circuit (voltage multiplier) enables operation at 0.9 v minimum
fedl63187b-06 1 semiconductor ml63187b/63189b 3/36 ? timers and counter 8-bit timer 4 selectable as auto-reload mode/capture mode/clock frequency measurement mode watchdog timer 1 100 hz timer 1 measurable in steps of 1/100 sec. 15-bit time base counter 1 1, 2, 4, 8, 16, 32, 64, and 128 hz signals can be read ? shift register shift clock : 1 or 1/2 system clock, timer 1 overflow, external clock data length : 8 bits ? interrupt sources ml63187b external interrupt : 2 internal interrupt : 12 (watchdog timer interrupt is a nonmaskable interrupt) ml63189b external interrupt : 3 internal interrupt : 12 (watchdog timer interrupt is a nonmaskable interrupt) ? operating temperature ?20 to +70 c ? operating voltage when backup used : 0.9 to 2.7 v (operating frequency: 30 to 80 khz) 1.2 to 2.7 v (operating frequency: 300 to 500 khz) 1.5 to 2.7 v (operating frequency: 200 khz to 1 mhz) when backup not used : 1.8 to 5.5 v (operating frequency: 200 khz to 2 mhz) ? package: chip (ml63187b: 111 pads , ml63189b: 123 pads): (product name: ml63187b-xxxwa, ml63189b-xxxwa) 128-pin plastic qfp (qfp128-p-1420-0.50-k) : (product name: ml63187b-xxxga, ml63189b-xxxga) xxx indicates a code number.
fedl63187b-06 1 semiconductor ml63187b/63189b 4/36 mask option in the ml63187b and ml63189b use the mask option to specify the following functions: ? low-speeed clock oscillation circuit specify the crystal oscillation circuit or the rc oscillation circuit for the low-speed clock oscillation circuit. ? reset signal sampling specify whether or not the reset signal will be sampled at 2 khz. when specifying ?will carry out 2 khz sampling,? hold the reset pin at a ?h? level for 1 ms or more. to use the mask option, assign mask option data in the application program in accordance with the formats below. the mask option area for each device is an application program execution disabled area. mask option data assignment format function mask option area bit data option to be selected 0 crystal oscillation circuit low-speed clock oscillation circuit (crystal oscillation circuit/rc oscillation circuit) ml63187b:3fe0h bit 0 1 rc oscillation circuit 0 will carry out 2 khz sampling reset signal sampling (will/will not carry out 2 khz sampling) ml63189b:7fe0h bit 1 1 will not carry out 2 khz sampling
fedl63187b-06 1 semiconductor ml63187b/63189b 5/36 block diagram (ml63187b) an asterisk ( * ) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from v ddi (power supply for interface). rom 16 kw bus con- trol mie xt0 xt1 osc0 osc1 osc cbr ebr l cgz alu ra a ir instruction decoder ram 1024n nx-4/250 reset rst v dd1 pc h y x timing con- trol sp rsp stack cal : 16-level reg : 16-level timer 8 bit 4 sclk* sin* sout* 4 int sft tm0cap/tm1cap* tm0ovf/tm1ovf* t02ck* t13ck* 1 int i/o port pb.0-pb.3 pe.0-pe.3 2 int v ddh v dd cb1 cb2 data bus tbc 4 int bld int 100 hztc 1 back up v ss melody md 1 int mdb lcd & dspr com1-16 seg0-63 tst1 tst tst2 int wdt 1 v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddl bias int187 cpu core
fedl63187b-06 1 semiconductor ml63187b/63189b 6/36 block diagram (ml63189b) an asterisk ( * ) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from v ddi (power supply for interface). rom 32 kw bus con- trol mie xt0 xt1 osc0 osc1 osc cbr ebr l cg z alu ra a ir instruction decoder ram 1536n nx-4/250 reset rst v ddi pc h y x timing con- trol sp rsp stack cal : 16-level reg : 16-level timer 8 bit 4 sclk* sin* sout* 4 int sft tm0cap/tm1cap* tm0ovf/tm1ovf* t02ck* t13ck* 1 int i/o port p9.0-p9.3 pa.0-pa.3 pb.0-pb.3 pe.0-pe.3 2 int v ddh v dd cb1 cb2 data bus tbc 4 int bld int 100 hztc 1 back up v ss melody md 1 int mdb 1 int input port p0.0-p0.3 lcd & dspr com1-16 seg0-63 tst1 tst tst2 int wdt 1 v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddl bias int189 cpu core
fedl63187b-06 1 semiconductor ml63187b/63189b 7/36 pin configuration (top view) (ml63187b) 128-pin plastic qfp note: pins marked as (nc) are no-connection pins which are left open. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (nc) (nc) (nc) (nc) seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 reset osc0 osc1 v ddl v dd cb2 cb1 v ddh c2 c1 v dd5 v dd4 v dd3 v dd2 v dd1 v ss com16 com15 com14 com13 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (nc) (nc) (nc) (nc) seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com8 com7 com6 com5 com4 com3 com2 com1 pb.3 pb.2 pb.1 pb.0 pe.3 pe.2 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 31 32 33 34 35 36 37 38 com9 com10 com11 com12 (nc) (nc) (nc) (nc) 72 71 70 69 68 67 66 65 pe.1 pe.0 v ddi (nc) (nc) (nc) (nc) (nc) 64 63 62 61 60 59 mdb md tst2 tst1 xt0 xt1 seg12 seg13 seg14 seg15 seg16 seg17 103 104 105 106 107 108 58
fedl63187b-06 1 semiconductor ml63187b/63189b 8/36 pad configuration (ml63187b) pad layout chip size : 4.238 mm 4.914 mm chip thickness : 350 m (280 m: available as required) coordinate origin : center of chip pad hole size : 100 m 100 m pad size : 110 m 110 m minimum pad pitch : 140 m note: the chip substrate voltage is v ss . 27 seg38 28 seg39 seg11 111 29 seg40 seg10 110 30 seg41 seg9 109 31 seg42 seg8 108 32 seg43 seg7 107 33 seg44 seg6 106 34 seg45 seg5 105 35 seg46 seg4 104 36 seg47 seg3 103 37 seg48 seg2 102 38 seg49 seg1 101 39 seg50 seg0 100 40 seg51 com8 99 41 seg52 com7 98 42 seg53 com6 97 43 seg54 com5 96 44 seg55 com4 95 45 seg56 com3 94 46 seg57 com2 93 47 seg58 com1 92 48 seg59 pb.3 91 49 seg60 pb.2 90 50 seg61 pb.1 89 seg30 19 seg29 18 57 com13 seg28 17 58 com14 seg27 16 59 com15 seg26 15 60 com16 seg25 14 61 v ss seg24 13 62 v dd1 seg23 12 63 v dd2 seg22 11 64 v dd3 seg21 10 65 v dd4 seg20 9 66 v dd5 67 c1 68 c2 69 v ddh 70 cb1 71 cb2 seg14 3 72 v dd seg13 2 73 v ddl seg12 1 74 osc1 75 osc0 76 reset 77 xt1 78 xt0 79 tst1 80 tst2 81 md 82 mdb seg37 26 seg36 25 seg35 24 seg34 23 seg33 22 seg32 21 seg31 20 51 seg62 pb.0 88 52 seg63 pe.3 87 53 com9 pe.2 86 54 com10 pe.1 85 55 com11 pe.0 84 56 com12 v ddi 83 ml63187 seg17 6 seg16 5 seg15 4 seg19 8 seg18 7 y x (0,0)
fedl63187b-06 1 semiconductor ml63187b/63189b 9/36 pad coordinates (ml63187b) center of chip: x = 0, y = 0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 seg12 ?1755 ?2311 42 seg53 1969 70 83 v ddi ?1969 1895 2 seg13 ?1615 ?2311 43 seg54 1969 211 84 pe.0 ?1969 1755 3 seg14 ?1474 ?2311 44 seg55 1969 351 85 pe.1 ?1969 1615 4 seg15 ?1334 ?2311 45 seg56 1969 491 86 pe.2 ?1969 1474 5 seg16 ?1193 ?2311 46 seg57 1969 632 87 pe.3 ?1969 1334 6 seg17 ?1053 ?2311 47 seg58 1969 772 88 pb.0 ?1969 1193 7 seg18 ?913 ?2311 48 seg59 1969 913 89 pb.1 ?1969 1053 8 seg19 ?772 ?2311 49 seg60 1969 1053 90 pb.2 ?1969 913 9 seg20 ?632 ?2311 50 seg61 1969 1193 91 pb.3 ?1969 772 10 seg21 491 ?2311 51 seg62 1969 1334 92 com1 ?1969 632 11 seg22 ?351 ?2311 52 seg63 1969 l 474 93 com2 ?1969 491 12 seg23 ?211 ?2311 53 com9 1969 1615 94 com3 ?1969 351 13 seg24 ?70 ?2311 54 com10 1969 1755 95 com4 ?1969 211 14 seg25 70 ?2311 55 com11 1969 1895 96 com5 ?1969 70 15 seg26 211 ?2311 56 com12 1969 2036 97 com6 ?1969 ?70 16 seg27 351 ?2311 57 com13 1755 2311 98 com7 ?1969 ?211 17 seg28 491 ?2311 58 com14 1615 2311 99 com8 ?1969 ?351 18 seg29 632 ?2311 59 com15 1474 2311 100 seg0 ?1969 ?491 19 seg30 772 ?2311 60 com16 1334 2311 101 seg1 ?1969 ?632 20 seg31 913 ?2311 61 v ss 1193 2311 102 seg2 ?1969 ?772 21 seg32 1053 ?2311 62 v dd1 1053 2311 103 seg3 ?1969 ?913 22 seg33 1193 ?2311 63 v dd2 913 2311 104 seg4 ?1969 ?1053 23 seg34 1334 ?2311 64 v dd3 772 2311 105 seg5 ?1969 ?1193 24 seg35 1474 ?2311 65 v dd4 632 2311 106 seg6 ?1969 ?1334 25 seg36 1615 ?2311 66 v dd5 491 2311 107 seg7 ?1969 ?1474 26 seg37 1755 ?2311 67 c1 351 2311 108 seg8 ?1969 ?1615 27 seg38 1969 ?2036 68 c2 211 2311 109 seg9 ?1969 ?1755 28 seg39 1969 ?1895 69 v ddh 70 2311 110 seg10 ?1969 ?1895 29 seg40 1969 ?1755 70 cb1 ?70 2311 111 seg11 ?1969 ?2036 30 seg41 1969 ?1615 71 cb2 ?211 2311 31 seg42 1969 ?1474 72 v dd ?351 2311 32 seg43 1969 ?1334 73 v ddl ?491 2311 33 seg44 1969 ?1193 74 osc1 ?632 2311 34 seg45 1969 ?1053 75 osc0 ?772 2311 35 seg46 1969 ?913 76 reset ?913 2311 36 seg47 1969 ?772 77 xt1 ?1053 2311 37 seg48 1969 ?632 78 xt0 ?1193 2311 38 seg49 1969 491 79 tst1 ?1334 2311 39 seg50 1969 ?351 80 tst2 ?1474 2311 40 seg51 1969 ?211 81 md ?1615 2311 41 seg52 1969 ?70 82 mdb ?1755 2311
fedl63187b-06 1 semiconductor ml63187b/63189b 10/36 pin configuration (top view) (ml63189b) 128-pin plastic qfp note: pins marked as (nc) are no-connection pins which are left open. 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (nc) seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 osc1 v ddl v dd cb2 cb1 v ddh c2 c1 v dd5 v dd4 v dd3 v dd2 v dd1 v ss com16 com15 com14 com13 com12 com11 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (nc) seg3 seg2 seg1 seg0 com8 com7 com6 com5 com4 com3 com2 com1 p0.3 p0.2 p0.1 p0.0 p9.3 p9.2 p9.1 p9.0 pa.3 pa.2 pa.1 pa.0 pb.3 pb.2 pb.1 pb.0 pe.3 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 31 32 33 34 35 36 37 38 seg59 seg60 seg61 seg62 seg63 com9 com10 (nc) 72 71 70 69 68 67 66 65 pe.2 pe.1 pe.0 v ddi (nc) mdb md (nc) 64 63 62 61 60 59 tst2 tst1 xt0 xt1 reset osc0 seg4 seg5 seg6 seg7 seg8 seg9 103 104 105 106 107 108
fedl63187b-06 1 semiconductor ml63187b/63189b 11/36 pad configuration (ml63189b) pad layout chip size : 4.81 mm 5.20 mm chip thickness : 350 m (280 m: available as required) coordinate origin : center of chip pad hole size : 100 m 100 m pad size : 110 m 110 m minimum pad pitch : 140 m note: the chip substrate voltage is v ss . 64 com10 31 seg32 seg1 123 92 mdb seg2 1 63 com9 seg31 30 32 seg33 seg0 122 33 seg34 com8 121 34 seg35 com7 120 35 seg36 com6 119 36 seg37 com5 118 37 seg38 com4 117 38 seg39 com3 116 39 seg40 com2 115 40 seg41 com1 114 41 seg42 p0.3 113 42 seg43 p0.2 112 43 seg44 p0.1 111 44 seg45 p0.0 110 45 seg46 p9.3 109 46 seg47 p9.2 108 47 seg48 p9.1 107 48 seg49 p9.0 106 49 seg50 pa.3 105 50 seg51 pa.2 104 51 seg52 pa.1 103 52 seg53 pa.0 102 53 seg54 pb.3 101 54 seg55 pb.2 100 55 seg56 pb.1 99 56 seg57 pb.0 98 57 seg58 pe.3 97 58 seg59 pe.2 96 59 seg60 pe.1 95 60 seg61 pe.0 94 61 seg62 62 seg63 v ddi 93 seg30 29 65 com11 seg29 28 66 com12 seg28 27 67 com13 seg27 26 68 com14 seg26 25 69 com15 seg25 24 70 com16 seg24 23 71 v ss seg23 22 72 v dd1 seg22 21 73 v dd2 seg21 20 74 v dd3 seg20 19 75 v dd4 seg19 18 76 v dd5 seg18 17 77 c1 seg17 16 78 c2 seg16 15 79 v ddh seg15 14 80 cb1 seg14 13 81 cb2 seg13 12 82 v dd seg12 11 83 v ddl seg11 10 84 osc1 seg10 9 85 osc0 86 reset seg8 7 87 xt1 seg7 6 88 xt0 89 tst1 seg5 4 90 tst2 91 md seg3 2 ml63189b seg4 3 seg6 5 seg9 8 y x (0,0)
fedl63187b-06 1 semiconductor ml63187b/63189b 12/36 pad coordinates (ml63189b) center of chip: x = 0, y = 0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 seg2 ?2259 ?2438 42 seg43 2259 ?632 83 v ddl ?772 2438 2 seg3 ?1895 ?2438 43 seg44 2259 ?491 84 osc1 ?913 2438 3 seg4 ?1755 ?2438 44 seg45 2259 ?351 85 osc0 ?1053 2438 4 seg5 ?1615 ?2438 45 seg46 2259 ?211 86 reset ?1193 2438 5 seg6 ?1474 ?2438 46 seg47 2259 ?70 87 xt1 ?1334 2438 6 seg7 ?1334 ?2438 47 seg48 2259 70 88 xt0 ?1474 2438 7 seg8 ?1193 ?2438 48 seg49 2259 211 89 tst1 ?1615 2438 8 seg9 ?1053 ?2438 49 seg50 2259 351 90 tst2 ?1755 2438 9 seg10 ?913 ?2438 50 seg51 2259 491 91 md ?1895 2438 10 seg11 ?772 ?2438 51 seg52 2259 632 92 mdb ?2259 2438 11 seg12 ?632 ?2438 52 seg53 2259 772 93 v ddi ?2259 2132 12 seg13 ?491 ?2438 53 seg54 2259 913 94 pe.0 ?2259 1895 13 seg14 ?351 ?2438 54 seg55 2259 1053 95 pe.1 ?2259 1755 14 seg15 ?211 ?2438 55 seg56 2259 1193 96 pe.2 ?2259 1615 15 seg16 ?70 ?2438 56 seg57 2259 1334 97 pe.3 ?2259 1474 16 seg17 70 ?2438 57 seg58 2259 1474 98 pb.0 ?2259 1334 17 seg18 211 ?2438 58 seg59 2259 1615 99 pb.1 ?2259 1193 18 seg19 351 ?2438 59 seg60 2259 1755 100 pb.2 ?2259 1053 19 seg20 491 ?2438 60 seg61 2259 1895 101 pb.3 ?2259 913 20 seg21 632 ?2438 61 seg62 2259 2036 102 pa.0 ?2259 772 21 seg22 772 ?2438 62 seg63 2259 2176 103 pa.1 ?2259 632 22 seg23 913 ?2438 63 com9 2259 2438 104 pa.2 ?2259 491 23 seg24 1053 ?2438 64 com10 1895 2438 105 pa.3 ?2259 351 24 seg25 1193 ?2438 65 com11 1755 2438 106 p9.0 ?2259 211 25 seg26 1334 ?2438 66 com12 1615 2438 107 p9.1 ?2259 70 26 seg27 1474 ?2438 67 com13 1474 2438 108 p9.2 ?2259 ?70 27 seg28 1615 ?2438 68 com14 1334 2438 109 p9.3 ?2259 ?211 28 seg29 1755 ?2438 69 com15 1193 2438 110 p0.0 ?2259 ?351 29 seg30 1895 ?2438 70 com16 1053 2438 111 p0.1 ?2259 ?491 30 seg31 2259 ?2438 71 v ss 913 2438 112 p0.2 ?2259 ?632 31 seg32 2259 ?2176 72 v dd1 772 2438 113 p0.3 ?2259 ?772 32 seg33 2259 ?2036 73 v dd2 632 2438 114 com1 ?2259 ?913 33 seg34 2259 ?1895 74 v dd3 491 2438 115 com2 ?2259 ?1053 34 seg35 2259 ?1755 75 v dd4 351 2438 116 com3 ?2259 ?1193 35 seg36 2259 ?1615 76 v dd5 211 2438 117 com4 ?2259 ?1334 36 seg37 2259 ?1474 77 c1 70 2438 118 com5 ?2259 ?1474 37 seg38 2259 ?1334 78 c2 ?70 2438 119 com6 ?2259 ?1615 38 seg39 2259 ?1193 79 v ddh ?211 2438 120 com7 ?2259 ?1755 39 seg40 2259 ?1053 80 cb1 ?351 2438 121 com8 ?2259 ?1895 40 seg41 2259 ?913 81 cb2 ?491 2438 122 seg0 ?2259 ?2036 41 seg42 2259 ?772 82 v dd ?632 2438 123 seg1 ?2259 ?2176
fedl63187b-06 1 semiconductor ml63187b/63189b 13/36 pin descriptions the basic functions of each pin of the ml63187b, ml63189b are described in table 1. a symbol with a slash (/) denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, ??? denotes a power supply pin, ?i? an input pin, ?o? an output pin, and ?i/o? an input-output pin. table 1 pin descriptions (basic functions) pin no. pad no. function symbol ml63187b m l63189b ml 63187b m l63189b type description v dd 54 56 72 82 ? positive power supply v ss 43 45 61 71 ? negative power supply v dd1 44 46 62 72 v dd2 45 47 63 73 v dd3 46 48 64 74 v dd4 47 49 65 75 v dd5 48 50 66 76 ? power supply pins for lcd bias (internally generated) capacitors (0.1 f) should be connected between these pins and v ss . c1 49 51 67 77 ? c2 50 52 68 78 ? capacitor connection pins for lcd bias generation a capacitor (0.1 f) should be connected between c1 and c2. v ddi 70 69 83 93 ? positive power supply pin for external interface (power supply for input, and input-output ports) v ddl 55 57 73 83 ? positive power supply pin for internal logic (internally generated) a capacitor (0.1 f) should be connected between this pin and v ss . v ddh 51 53 69 79 ? voltage multiplier pin for power supply backup (internally generated) a capacitor (1.0 f) should be connected between this pin and v ss . cb1 52 54 70 80 ? power supply cb2 53 55 71 81 ? pins to connect a capacitor for voltage multiplier a capacitor (1.0 f) should be connected between cb1 and cb2. xt0 60 62 78 88 i xt1 59 61 77 87 o low-speed clock oscillation pins an option for using crystal oscillation or rc oscillation is chosen by the mask option. if the crystal oscillation is chosen, a crystal should be connected between xt0 and xt1, and capacitor (c g ) should be connected between xt0 and v ss . if the rc oscillation is chosen, external oscillation resistor (r osl ) should be connected between xt0 and xt1. osc0 57 59 75 85 i osci- llation osc1 56 58 74 84 o high-speed clock oscillation pins a ceramic resonator and capacitors (c l0 , c l1 ) or external oscillation resistor (r osh ) should be connected to these pins.
fedl63187b-06 1 semiconductor ml63187b/63189b 14/36 table 1 pin descriptions (basic functions) (continued) pin no. pad no. function symbol ml63187b m l63189b ml 63187b m l63189b type description tst1 61 63 79 89 i test tst2 62 64 80 90 i input pins for testing a pull-down resistor is internally connected to these pins. the user cannot use these pins. reset reset 58 60 76 86 i reset input pin setting this pin to ?h? ievel puts this device into a reset state. then, setting this pin to ?l? ievel starts executing an instruction from address 0000h. a pull-down resistor is internally connected to this pin. an option of using reset sampling circuit or not is chosen by the mask option. when using reset sampling circuit, the system reset mode is entered by holding the reset pin at a ?h? ievel for 1 ms or more. md 63 66 81 91 o melody output pin (non-inverted output) melody mdb 64678292o melody output pin (inverted output) p0.0/int5 86 110 p0.1/int5 87 111 p0.2/int5 88 112 p0.3/int5 ? 89 ? 113 i 4-bit input ports pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. applied to the ml63189b only. p9.0 82 106 p9.1 83 107 p9.2 84 108 p9.3 ? 85 ? 109 i/o pa.0 78 102 pa.1 79 103 pa.2 80 104 pa.3 ? 81 ? 105 i/o pb.0/int0/ tm0cap/ tm0ovf 75 74 88 98 pb.1/int0/ tm1cap/ tm1ovf 76 75 89 99 pb.2/int0/ t02ck 77 76 90 100 pb.3/int0/ t13ck 78 77 91 101 i/o pe.0/sin 71 70 84 94 pe.1/sout 72 71 85 95 pe.2/sclk 73 72 86 96 port pe.3/int2 74 73 87 97 i/o 4-bit input-output ports in input mode, pull-up resistor input, pull- down resistor input, or high-impedance input is selectable for each bit. in output mode, p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit. p9.0 to p9.3 and pa.0 to pa.3 are applied to the ml63189b only.
fedl63187b-06 1 semiconductor ml63187b/63189b 15/36 table 1 pin descriptions (basic functions) (continued) pin no. pad no. function symbol ml63187b m l63189b ml 63187b m l63189b type description com1 79 90 92 114 com2 80 91 93 115 com3 81 92 94 116 com4 82 93 95 117 com5 83 94 96 118 com6 84 95 97 119 com7 85 96 98 120 com8 86 97 99 121 com9 31 36 53 63 com1032375464 com1133395565 com1234405666 com13 39 41 57 67 com14 40 42 58 68 com15 41 43 59 69 com1642446070 o lcd common signal output pins seg0 87 98 100 122 seg1 88 99 101 123 seg2 89 100 102 1 seg3 90 101 103 2 seg4 91 103 104 3 seg5 92 104 105 4 seg6 93 105 106 5 seg7 94 106 107 6 seg8 95 107 108 7 seg9 96 108 109 8 seg10 97 109 110 9 seg11 98 110 111 10 seg12 103 111 1 11 seg13 104 112 2 12 seg14 105 113 3 13 seg15 106 114 4 14 seg16 107 115 5 15 seg17 108 116 6 16 seg18 109 117 7 17 seg19 110 118 8 18 seg20 111 119 9 19 seg21 112 120 10 20 seg22 113 121 11 21 seg23 114 122 12 22 lcd seg24 115 123 13 23 o lcd segment signal output pins
fedl63187b-06 1 semiconductor ml63187b/63189b 16/36 table 1 pin descriptions (basic functions) (continued) pin no. pad no. function symbol ml63187b m l63189b ml 63187b m l63189b type description seg25 116 124 14 24 seg26 117 125 15 25 seg27 118 126 16 26 seg28 119 127 17 27 seg29 120 128 18 28 seg30 121 2 19 29 seg31 122 3 20 30 seg32 123 4 21 31 seg33 124 5 22 32 seg34 125 6 23 33 seg35 126 7 24 34 seg36 127 8 25 35 seg37 128 9 26 36 seg38 5 102737 seg39 6 112838 seg40 7 122939 seg41 8 13 30 40 seg42 9 14 31 41 seg43 10 15 32 42 seg44 11 16 33 43 seg45 12 17 34 44 seg46 13 18 35 45 seg4714193646 seg4815203747 seg49 16 21 38 48 seg50 17 22 39 49 seg51 18 23 40 50 seg52 19 24 41 51 seg5320254252 seg5421264353 seg55 22 27 44 54 seg56 23 28 45 55 seg57 24 29 46 56 seg58 25 30 47 57 seg5926314858 seg6027324959 seg61 28 33 50 60 seg62 29 34 51 61 lcd seg63 30 35 52 62 o lcd segment signal output pins
fedl63187b-06 1 semiconductor ml63187b/63189b 17/36 table 2 shows the secondary functions of each pin of the ml63187b, ml63189b. table 2 pin descriptions (secondary functions) pin no. pad no. function symbol ml63187b m l63189b ml 63187b m l63189b type description pb.0/int0 75 74 88 98 pb.1/int0 76 75 89 99 pb.2/int0 77 76 90 100 pb.3/int0 78 77 91 101 i external 0 interrupt input pins the change of input signal level causes an interrupt to occur. the port b interrupt enable register (pbie) enables or disables an interrupt for each bit. pe.3/int2 74 73 87 97 i external 2 interrupt input pin the change of input signal level causes an interrupt to occur. p0.0/int5 86 110 p0.1/int5 87 111 p0.2/int5 88 112 external interrupt p0.3/int5 ? 89 ? 113 i external 5 interrupt input pins the change of input signal level causes an interrupt to occur. the port 0 interrupt enable register (p0ie) enable or disable an interrupt for each bit. applied to the ml63189b only. pb.0/tm0cap 75 74 88 98 i timer 0 capture input pin capture pb.1/tm1cap 76 75 89 99 i timer 1 capture input pin pb.0/tm0ovf 75 74 88 98 o timer 0 overflow flag output pin pb.1/tm1ovf 76 75 89 99 o timer 1 overflow flag output pin pb.2/t02ck 77 76 90 100 i external clock input pin for timer 0 and timer 2 timer pb.3/t13ck 78 77 91 101 i external clock input pin for timer 1 and timer 3 pe.0/sin 71 70 84 94 i shift register receive data input pin pe.1/sout 72 71 85 95 o shift register transmit data output pin shift register pe.2/sclk 73 72 86 96 i/o shift register clock input-output pin clock output when this device is used as a master processor.
fedl63187b-06 1 semiconductor ml63187b/63189b 18/36 absolute maximum ratings (v ss = 0 v) parameter symbol condition rating unit power supply voltage 1 v dd1 ta = 25 c ?0.3 to +1.6 v power supply voltage 2 v dd2 ta = 25 c ?0.3 to +2.9 v power supply voltage 3 v dd3 ta = 25 c ?0.3 to +4.2 v power supply voltage 4 v dd4 ta = 25 c ?0.3 to +5.5 v power supply voltage 5 v dd5 ta = 25 c ?0.3 to +6.8 v power supply voltage 6 v dd ta = 25 c ?0.3 to +6.0 v power supply voltage 7 v ddi ta = 25 c ?0.3 to +6.0 v power supply voltage 8 v ddh ta = 25 c ?0.3 to +6.0 v power supply voltage 9 v ddl ta = 25 c ?0.3 to +6.0 v input voltage 1 v in1 v dd input, ta = 25 c ?0.3 to v dd +0.3 v input voltage 2 v in2 v ddi input, ta = 25 c ?0.3 to v ddi +0.3 v output voltage 1 v out1 v dd1 output, ta = 25 c ?0.3 to v dd1 +0.3 v output voltage 2 v out2 v dd2 output, ta = 25 c ?0.3 to v dd2 +0.3 v output voltage 3 v out3 v dd3 output, ta = 25 c ?0.3 to v dd3 +0.3 v output voltage 4 v out4 v dd4 output, ta = 25 c ?0.3 to v dd4 +0.3 v output voltage 5 v out5 v dd5 output, ta = 25 c ?0.3 to v dd5 +0.3 v output voltage 6 v out6 v dd output, ta = 25 c ?0.3 to v dd +0.3 v output voltage 7 v out7 v ddi output, ta = 25 c ?0.3 to v ddi +0.3 v output voltage 8 v out8 v ddh output, ta = 25 c ?0.3 to v ddh +0.3 v storage temperature t stg ? ?55 to +150 c
fedl63187b-06 1 semiconductor ml63187b/63189b 19/36 recommended operating conditions ? when backup is used (v ss = 0 v) parameter symbol condition range unit operating temperature t op ? ?20 to +70 c v dd ? 0.9 to 2.7 v operating voltage v ddi ? 0.9 to 5.5 v crystal oscillation frequency f xt c g = 5 to 25 pf 32.768 to 76.8 khz r osl = 1.0 m ? 36 30% r osl = 1.1 m ? 33 30% low-speed rc oscillation frequency f rosl r osl = 1.2 m ? 30 30% khz v dd = 0.9 to 1.2 v not applied v dd = 1.2 to 2.7 v 300k to 500k ceramic oscillation frequency f cm v dd = 1.5 to 2.7 v 200k to 1m hz v dd = 0.9 to 1.2 v not applied r osh = 400 k ? 200k 30% r osh = 100 k ? 700k 30% high-speed rc oscillation frequency f rosh v dd = 1.2 to 2.7 v r osh = 75 k ? 1m 30% hz ? when backup is not used (v ss = 0 v) parameter symbol condition range unit operating temperature t op ? ?20 to +70 c v dd ? 1.8 to 5.5 operating voltage v ddi ? 1.8 to 5.5 v crystal oscillation frequency f xt c g = 5 to 25 pf 32.768 to 76.8 khz r osl = 1.0 m ? 36 30% r osl = 1.1 m ? 33 30% low-speed rc oscillation frequency f rosl r osl = 1.2 m ? 30 30% khz ceramic oscillation frequency f cm v dd = 1.8 to 5.5 v 200k to 2m hz r osh = 100 k ? 700k 30% r osh = 75 k ? 1m 30% v dd = 1.8 to 5.5 v r osh = 51 k ? 1.35m 30% high-speed rc oscillation frequency f rosh v dd = 1.8 to 3.5 v, r osh = 30 k ? 2m 30% hz
fedl63187b-06 1 semiconductor ml63187b/63189b 20/36 ? typical characteristics of low-speed rc oscillation when backup is used/backup is not used (v dd = v ddi = 1.5 v/v dd = v ddi = 3.0 v) ? typical characteristics of high-speed rc oscillation when backup is used (v dd = v ddi = 1.5 v) 1000 100 10 100 1000 10000 f rosl [ khz ] r osl [k ? ] reference data 10000 1000 100 10 100 1000 f rosh [ khz ] r osh [k ? ] reference data
fedl63187b-06 1 semiconductor ml63187b/63189b 21/36 ? typical characteristics of high-speed rc oscillation when backup is not used (v dd = v ddi = 3.0 v) 10000 1000 100 10 100 1000 f rosh [ khz ] r osh [k ? ] reference data
fedl63187b-06 1 semiconductor ml63187b/63189b 22/36 electrical characteristics dc characteristics (1) (v dd = v ddi = 0.9 to 5.5 v, v ss = 0 v, ta = ?20 to +70c unless otherwise specified) parameter symbol condition min. typ. max. unit mea- suring circuit v dd2 voltage v dd2 1/5 bias, 1/4 bias (ta = 25c) 1.7 1.8 1.9 v v dd2 voltage temperature deviation ? v dd2 ???4? mv/c v dd1 voltage v dd1 1/5 bias, 1/4 bias typ. ? 0.1 1/2 v dd2 typ. + 0.1 v 1/5 bias typ. ? 0.3 3/2 v dd2 typ. + 0.3 v dd3 voltage v dd3 1/4 bias (connect v dd3 and v dd2 ) typ. ? 0.2 v dd2 typ. + 0.2 v 1/5 bias typ. ? 0.4 2 v dd2 typ. + 0.4 v dd4 voltage v dd4 1/4 bias typ. ? 0.3 3/2 v dd2 typ. + 0.3 v 1/5 bias typ. ? 0.5 5/2 v dd2 typ. + 0.5 v dd5 voltage v dd5 1/4 bias typ. ? 0.4 2 v dd2 typ. + 0.4 v high-speed clock oscillation stopped v dd = 1.5 v 2.8 ? 3.0 v v ddh voltage (backup used) v ddh high-speed clock oscillation (ceramic oscillation, 1 mhz) v dd = 1.5 v 2.0 ? 2.7 v high-speed clock oscillation stopped 1.0 1.5 2.0 v v ddl voltage v ddl high-speed clock oscillation (v dd = 1.2 to 5.5 v) 1.2 ? 5.5 v crystal oscillation start voltage v sta oscillation start time: within 5 seconds 1.2 ? ? v backup 0.9 ? ? v crystal oscillation hold voltage v hold backup not used 1.7 ? ? v crystal oscillation stop detect time t stop ? 0.1 ? 5.0 ms external crystal oscillator capacitance c g ?5?25pf internal crystal oscillator capacitance c d ?202530pf external ceramic oscillator capacitance c l0,1 csa2.00mg (murata mfg.-make) used v dd = 3.0 v ?30?pf internal rc oscillator capacitance c os ? 8 12 16 pf v dd = 1.5 v 0 ? 0.4 v por voltage v por1 v dd = 3.0 v 0 ? 0.7 v v dd = 1.5 v 1.2 ? 1.5 v non-por voltage v por2 v dd = 3.0 v 2.0 ? 3.0 v 1 ld1 = 1, ld0 = 1, ta = 25c 2.30 2.40 2.50 ld1 = 1, ld0 = 0, ta = 25c 1.70 1.80 1.90 ld1 = 0, ld0 = 1, ta = 25c 1.10 1.20 1.30 bld judgment voltage v bldc ld1 = 0, ld0 = 0, ta = 25c 0.95 1.05 1.15 v v bldc = 2.40 v (ld1 = 1, ld0 = 1) ? ?3.5 ? v bldc = 1.80 v (ld1 = 1, ld0 = 0) ? ?2.3 ? v bldc = 1.20 v (ld1 = 0, ld0 = 1) ? ?1.6 ? bld judgment voltage temperature deviation ? v bldc v bldc = 1.05 v (ld1 = 0, ld0 = 0) ? ?1.2 ? mv/c ?
fedl63187b-06 1 semiconductor ml63187b/63189b 23/36 notes: 1. ?t stop ? indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. 2. ?por? denotes power on reset. 3. ?v por1 ? indicates that por occurs when v dd falls from v dd to v por1 and again rises up to v dd . 4. ?v por2 ? indicates that por does not occur when v dd falls from v dd to v por2 and again rises up to v dd .
fedl63187b-06 1 semiconductor ml63187b/63189b 24/36 dc characteristics (2) ? when backup is used (32.768 khz crystal is used for the low-speed clock, v dd = v ddi = 1.5 v, v ss = 0 v, 1/5 bias, lcd contrast (dspcnt) = 0h, ta = ?20 to +70c unless otherwise specified) parameter symbol condition min. typ. max. unit mea- suring circuit ta = ?20 to +50c ? 5 6.5 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) ta = ?20 to +70c ? 5 10 a ta = ?20 to +50c ? 4 5 supply current 2 i dd2 cpu is in halt state. lcd is in power down mood. (high-speed clock oscillation stopped) ta = ?20 to +70c ? 4 8 a ta = ?20 to +50c ? 16 18 supply current 3 i dd3 cpu is in operation at low-speed oscillation. (high-speed clock oscillation stopped) ta = ?20 to +70c ? 16 20 a supply current 4 i dd4 cpu is in operation at high-speed oscillation (approx. 700 khz rc oscillation, r osh = 100 k ? ) ? 800 1000 a supply current 5 i dd5 cpu is in operation at high-speed oscillation (ceramic oscillation, 1 mhz) ? 700 850 a 1 ? when backup is not used (32.768 khz crystal is used for the low-speed clock, v dd = v ddi = 3.0 v, v ss = 0 v, 1/5 bias, lcd contrast (dspcnt) = 0h, ta = ?20 to +70c unless otherwise specified) parameter symbol condition min. typ. max. unit mea- suring circuit ta = ?20 to +50c ? 2.2 3 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) ta = ?20 to +70c ? 2.2 5 a ta = ?20 to +50c ? 1.8 2.5 supply current 2 i dd2 cpu is in halt state. lcd is in power down mood. (high-speed clock oscillation stopped) ta = ?20 to +70c ? 1.8 4 a ta = ?20 to +50c ? 7.5 9 supply current 3 i dd3 cpu is in operation at low-speed oscillation. (high-speed clock oscillation stopped) ta = ?20 to +70c ? 7.5 12 a supply current 4 i dd4 cpu is in operation at high-speed oscillation (approx. 700 khz rc oscillation, r osh = 100 k ? ) ? 550 700 a supply current 5 i dd5 cpu is in operation at high-speed oscillation (ceramic oscillation, 2 mhz) ? 850 1000 a 1
fedl63187b-06 1 semiconductor ml63187b/63189b 25/36 dc characteristics (3) (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = ?20 to +70c unless otherwise specified) parameter symbol condition min. typ. max. unit mea- suring circuit v ddi = 1.5 v ?2.5 ?1.4 ?0.4 ma v ddi = 3.0 v ?6.0 ?3.5 ?1.0 ma i oh1 v oh1 = v ddi ? 0.5 v v ddi = 5.0 v ?8.5 ?5.0 ?1.5 ma v ddi = 1.5 v 0.4 1.4 2.5 ma v ddi = 3.0 v 1.0 3.0 6.0 ma output current 1 (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) i ol1 v ol1 = 0.5 v v ddi = 5.0 v 1.5 3.7 8.5 ma v dd = 1.5 v ?4.0 ?2.0 ?0.5 ma v dd = 3.0 v ?11.0 ?6.0 ?2.0 ma i oh2 v oh2 = v dd ? 0.7 v v dd = v ddh = 5.0 v ?14.0 ?9.0 ?4.0 ma v dd = 1.5 v 0.5 2.0 4.0 ma v dd = 3.0 v 2.0 5.5 11.0 ma output current 2 (md, mdb) i ol2 v ol2 = 0.7 v v dd = v ddh = 5.0 v 4.0 7.0 14.0 ma i oh3 v oh3 = v dd5 ? 0.2 v (v dd5 ievel) ? ? ?4 a i ohm3 v ohm3 = v dd4 + 0.2 v (v dd4 ievel) 4 ? ? a i ohm3s v ohm3s = v dd4 ? 0.2 v (v dd4 ievel) ? ? ?4 a i omh3 v omh3 = v dd3 + 0.2 v (v dd3 ievel) 4 ? ? a i omh3s v omh3s = v dd3 ? 0.2 v (v dd3 ievel) ? ? ?4 a i oml3 v oml3 = v dd2 + 0.2 v (v dd2 ievel) 4 ? ? a i oml3s v oml3s = v dd2 ? 0.2 v (v dd2 ievel) ? ? ?4 a i olm3 v olm3 = v dd1 + 0.2 v (v dd1 ievel) 4 ? ? a i olm3s v olm3s = v dd1 ? 0.2 v (v dd1 ievel) ? ? ?4 a output current 3 (seg0 to seg63) (com1 to com16) i ol3 v ol3 = v ss + 0.2 v (v ss ievel) 4 ? ? a v dd = v ddh = 3.0 v ?2.5 ?1.3 ?0.25 ma i oh4r v oh4r = v ddh ? 0.5 v (rc oscillation) v dd = v ddh = 5.0 v ?3.5 ?1.7 ?0.5 ma v dd = v ddh = 3.0 v 0.25 1.5 2.5 ma i ol4r v ol4r = 0.5 v (rc oscillation) v dd = v ddh = 5.0 v 0.5 1.8 3.5 ma v dd = v ddh = 3.0 v ?500 ?250 ?100 a i oh4c v oh4c = v ddh ? 0.5 v (ceramic oscillation) v dd = v ddh = 5.0 v ?800 ?350 ?200 a v dd = v ddh = 3.0 v 200 500 800 a output current 4 (osc1) i ol4c v ol4c = 0.5 v (ceramic oscillation) v dd = v ddh = 5.0 v 400 700 1000 a i ooh v oh = v ddi ??0.3 a output leakage current (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) i ool v ol = v ss ?0.3 ? ? a 2 *: applied to the ml63189b only.
fedl63187b-06 1 semiconductor ml63187b/63189b 26/36 dc characteristics (4) (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = ?20 to +70c unless otherwise specified) parameter symbol condition min. typ. max. unit mea- suring circuit v ddi = 1.5 v 2 20 45 a v ddi = 3.0 v 30 120 260 a i ih1 v oh1 = v ddi (when pulled up) v ddi = 5.0 v 70 350 650 a v ddi = 1.5 v ?45 ?20 ?2 a v ddi = 3.0 v ?260 ?120 ?30 a i il1 v il1 = v ss (when pulled up) v ddi = 5.0 v ?650 ?350 ?70 a i ih1z v ih1 = v ddi (in a high impedance state) 0 ? 1 a input current 1 (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) i il1z v il1 = v ss (in a high impedance state) ?1 ? 0 a v dd = v ddh = 3.0 v ?350 ?170 ?30 a i il2 v il2 = v ss (when pulled up) v dd = v ddh = 5.0 v ?750 ?450 ?200 a i ih2r v ih2r = v ddh (rc oscillation) 0 ? 1 a i il2r v il2r = v ss (rc oscillation) ?1 ? 0 a v dd = v ddh = 3.0 v 0.5 1.8 4.0 a i ih2c v ih2c = v ddh (ceramic oscillation) v dd = v ddh = 5.0 v 3 6 10 a v dd = v ddh = 3.0 v ?4.0 ?1.8 ?0.5 a input current 2 (osc0) i il2c v il2c = v ss (ceramic oscillation) v dd = v ddh = 5.0 v ?10 ?6 ?3 a v dd = 1.5 v 10 180 350 a v dd = 3.0 v 150 1100 2400 a i ih3 v ih3 = v dd v dd = v ddh = 5.0 v 0.5 2.7 5.0 ma input current 3 (reset) i il3 v il3 = v ss ?1 ? 0 a v dd = 1.5 v 50 750 1500 a v dd = 3.0 v 0.5 3.0 5.5 ma i ih4 v ih4 = v dd v dd = v ddh = 5.0 v 2.0 6.5 11.0 ma input current 4 (tst1, tst2) i il4 v il4 = v ss ?1 ? 0 a 3 *: applied to the ml63189b only.
fedl63187b-06 1 semiconductor ml63187b/63189b 27/36 dc characteristics (5) (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = ?20 to +70c unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit v ddi = 1.5 v 1.2 ? 1.5 v v ddi = 3.0 v 2.4 ? 3.0 v v ih1 v ddi = 5.0 v 4.0 ? 5.0 v v ddi = 1.5 v 0 ? 0.3 v v ddi = 3.0 v 0 ? 0.6 v input voltage 1 (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) v il1 v ddi = 5.0 v 0 ? 1.0 v v dd = v ddh = 3.0 v 2.4 ? 3.0 v v ih2 v dd = v ddh = 5.0 v 4.0 ? 5.0 v v dd = v ddh = 3.0 v 0 ? 0.6 v input voltage 2 (osc0) v il2 v dd = v ddh = 5.0 v 0 ? 1.0 v v dd = 1.5 v 1.35 ? 1.5 v v dd = 3.0 v 2.4 ? 3.0 v v ih3 v dd = 5.0 v 4.0 ? 5.0 v v dd = 1.5 v 0 ? 0.15 v v dd = 3.0 v 0 ? 0.6 v input voltage 3 (reset, tst1, tst2) v il3 v dd = 5.0 v 0 ? 1.0 v v ddi = 1.5 v 0.05 0.1 0.3 v v ddi = 3.0 v 0.2 0.5 1.0 v hysteresis width 1 (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) ? v t1 v ddi = 5.0 v 0.25 1.0 1.5 v v ddi = 1.5 v 0.05 0.1 0.3 v v ddi = 3.0 v 0.2 0.5 1.0 v hysteresis width 2 (reset, tst1, tst2) ? v t2 v ddi = 5.0 v 0.25 1.0 1.5 v 4 input pin capacitance (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) c in ???5pf1 *: applied to the ml63189b only.
fedl63187b-06 1 semiconductor ml63187b/63189b 28/36 measuring circuit 1 c a ,c b ,c c ,c d ,c e ,c l ,c 12 c h ,cb 12 c g c l0 c l1 ceramic resonator v v ca cc v dd3 v dd1 v ddi v ss xt0 xt1 *1 rc oscillator r osh ceramic oscillator c l0 : : : : : : 0.1 f 1 f 15 pf 30 pf 30 pf csa2.00mg (2 mhz) csb1000j (1 mhz) (murata mfg-.make) cb12 cb1 cb2 osc0 osc1 a v dd v cd v dd4 c l1 ceramic resonator *1 c12 c1 c2 v cb v dd2 ce v dd5 v v ch v ddh cl v ddl v *2 *2 rc oscillator r osl crystal oscillator c g crystal 1 2 3 4 1 2 1 2 3 4 3 4
fedl63187b-06 1 semiconductor ml63187b/63189b 29/36 measuring circuit 2 measuring circuit 3 measuring circuit 4 v ss a v ih v ll *2 v dd v ddl v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output *3 v ddl *2 input logic circuit to determine the specified measuring conditions. *3 measured at the specified output pins. v ss v dd v ddl v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output a *4 v ddl v ss v ih v il *4 v dd v ddl v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output *4 measured at the specified input pins. waveform monitoring v ddl
fedl63187b-06 1 semiconductor ml63187b/63189b 30/36 ac characteristics (serial interface, shift register) (v dd = 0.9 to 5.5 v, v ddh = 1.8 to 5.5 v, v ss = 0 v, v ddi = 5.0 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit sclk input fall time t f ???1.0 s sclk input rise time t r ???1.0 s sclk input ?l? level pulse width t cwl ?0.8?? s sclk input ?h? level pulse width t cwh ?0.8?? s sclk input cycle time t cyc v ddi = 5 v to v dd 1.8 ? ? s t cyc1(o) cpu in operation state at 32.768 khz ? 30.5 ? s sclk output cycle time t cyc2(o) cpu in operation at 2 mhz v dd = v ddh = 1.8 to 3.5 v ?0.5? s sout output delay time t ddr output load capacitance 10 pf ? ? 0.4 s sin input setup time t ds ?0.5?? s sin input hold time t dh ?0.8?? s ac characteristics timing (?h? level = 4.0 v, ?l? level = 1.0 v) t cyc sout ( pe.1 ) sin ( pe.0 ) t ddr t r t f t cwh t cwl t ddr t ds t ds t dh 5 v (v ddl ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) sclk ( pe.2 )
fedl63187b-06 1 semiconductor ml63187b/63189b 31/36 application circuits (ml63187b) note: v ddi is the power supply pin for the input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 com1-16 xt1 v ddh v dd cb1 cb2 v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 r osh pb.3 pb.2 pb.1 pb.0 c b12 c v c g c 12 lcd crystal 32.768 khz c h 1.5 v c e c d c c c b c a buzzer ? crystal oscillation is selected as low-speed oscillation by mask option. ? rc oscillation is selected as high-speed oscillation by software. ? ports are powered from external memory power source. ? c v is an ic power supply bypass capacitor. ? values of c a , c b , c c , c d , c e , c l , c b12 , c 12 , c h , and c g , are for reference only. v ddl v ddl c l push sw 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 1.0 f 0.1 f 1.0 f 5 to 25 pf ml63187b pe.3 pe.2 pe.1 pe.0 v dd 1.0 f
fedl63187b-06 1 semiconductor ml63187b/63189b 32/36 note: v ddi is the power supply pin for the input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup xt0 com1-16 xt1 v ddh v dd v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 pb.3 pb.2 pb.1 pb.0 c v c g c 12 lcd crystal 32.768 khz v dd 5.0 v c e c d c c c v c a buzzer ? crystal oscillation is selected as low-speed oscillation by mask option. ? ceramic oscillation is selected as high-speed oscillation by software. ? ports, external memory, and ic share their power supply. ? c v is an ic power supply bypass capacitor. ? values of c a , c b , c c , c d , c e , c l , c 12 , c g , c l0 , and c l1 are for reference only. v ddl v dd c l0 30 pf c l1 30 pf ceramic resonator (example: 1 mhz) cb1 cb2 v ddl c l ml63187b 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f open push sw 5 to 25 pf pe.3 pe.2 pe.1 pe.0 0.1 f
fedl63187b-06 1 semiconductor ml63187b/63189b 33/36 application circuits (ml63189b) note: v ddi is the power supply pin for the input and input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 com1-16 xt1 v ddh v dd cb1 cb2 v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 r osh p9.3 p9.2 p9.1 p9.0 pb.3 pb.2 pb.1 pb.0 pa.3 pa.2 pa.1 pa.0 c b12 c v c g c 12 lcd crystal 32.768 khz c h 1.5 v c e c d c c c b c a buzzer ? crystal oscillation is selected as low-speed oscillation by mask option. ? rc oscillation is selected as high-speed oscillation by software. ? ports are powered from external memory power source. ? c v is an ic power supply bypass capacitor. ? values of c a , c b , c c , c d , c e , c l , c b12 , c 12 , c h , and c g , are for reference only. v ddi v ddl c l push sw 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 1.0 f 0.1 f 1.0 f 5 to 25 pf ml63189b pe.3 pe.2 pe.1 pe.0 p0.3 p0.2 p0.1 p0.0 v dd 1.0 f
fedl63187b-06 1 semiconductor ml63187b/63189b 34/36 note: v ddi is the power supply pin for the input and input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup xt0 com1-16 xt1 v ddh v dd v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 p9.3 p9.2 p9.1 p9.0 pb.3 pb.2 pb.1 pb.0 pa.3 pa.2 pa.1 pa.0 c v c g c 12 lcd crystal 32.768 khz v dd 5.0 v c e c d c c c b c a buzzer ? crystal oscillation is selected as low-speed oscillation by mask option. ? ceramic oscillation is selected as high-speed oscillation by software. ? ports, external memory, and ic share their power supply. ? c v is an ic power supply bypass capacitor. ? values of c a , c b , c c , c d , c e , c l , c 12 , c g , c l0 , and c l1 are for reference only. v ddl v dd c l0 30 pf c l1 30 pf ceramic resonator (example: 1 mhz) cb1 cb2 v ddl c l ml63189b 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f open push sw 5 to 25 pf pe.3 pe.2 pe.1 pe.0 p0.3 p0.2 p0.1 p0.0 0.1 f
fedl63187b-06 1 semiconductor ml63187b/63189b 35/36 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp128-p-1420-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.19 typ. 5 rev. no./last revised 4/nov. 28, 1996 (unit: mm)
fedl63187b-06 1 semiconductor ml63187b/63189b 36/36 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2001 oki electric industry co., ltd .

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