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altera corporation 1 max 7000a programmable logic device family september 1999, ver. 2.03 data sheet a-ds-m7000a-02.03 includes max 7000ae features... n high-performance cmos eeprom-based programmable logic devices (plds) built on second-generation multiple array matrix (max ) architecture (see table 1 ) n 3.3-v in-system programmability (isp) through the built-in ieee std. 1149.1 joint test action group (jtag) interface with advanced pin-locking capability preliminary information n built-in boundary-scan test (bst) circuitry compliant with ieee std. 1149.1-1990 n enhanced isp features enhanced isp algorithm for faster programming (excluding epm7128a and epm7256a devices) isp_done bit to ensure complete programming (excluding epm7128a and epm7256a devices) pull-up resistor on i/o pins during in-system programming n pin-compatible with the popular 5.0-v max 7000s devices n high-density plds ranging from 600 to 10,000 usable gates n 4.5-ns pin-to-pin logic delays with counter frequencies of up to 192.3 mhz f for information on in-system programmable 5.0-v max 7000 or 2.5-v max 7000b devices, see the max 7000 programmable logic device family data sheet or the max 7000b programmable logic device family advance information brief . table 1. max 7000a device features feature epm7032ae epm7064ae epm7128ae epm7128a epm7256ae epm7256a EPM7512AE usable gates 600 1,250 2,500 5,000 10,000 macrocells 32 64 128 256 512 logic array blocks 2 4 8 16 32 maximum user i/o pins 36 68 100 164 212 t pd (ns) 4.5 4.5 5.0 5.5 7.5 t su (ns) 3.0 3.0 3.2 3.5 4.9 t fsu (ns) 2.5 2.5 2.5 2.5 3.0 t co1 (ns) 2.8 2.8 3.0 3.2 4.5 f cnt (mhz) 192.3 192.3 181.8 163.9 119.0
2 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation ...and more features n multivolt tm i/o interface enabling device core to run at 3.3 v, while i/o pins are compatible with 5.0-v, 3.3-v, and 2.5-v logic levels n pin counts ranging from 44 to 256 in a variety of thin quad flat pack (tqfp), plastic quad flat pack (pqfp), bal l-g rid array (bga), space- saving fineline bga tm , and plastic j-lead chip carrier (plcc) packages n supports hot-socketing in max 7000ae devices n programmable interconnect array (pia) continuous routing structure for fast, predictable performance n peripheral component interconnect (pci) compatible n bus friendly architecture including programmable slew-rate control n open-drain output option n programmable macrocell re gi sters with individual clear, preset, clock, and clock enable controls n programmable power-up states for macrocell registers in max 7000ae devices n programmable power-saving mode for 50 % or greater power reduction in each macrocell n configurable expander product-term distribution, allowing up to 32 product terms per macrocell n programmable securi ty bit for protection of proprietary designs n 6 to 10 pin- or logic-driven output enable signals n two global clock signals with optional inversion n enhanced interconnect resources for improved routability n fast input setup times provided by a dedicated path from i/o pin to macrocell registers n programmable output slew-rate control n programmable ground pins n software design support and automatic place-and-route provided by altera? max+p l us i i development system for windows-based pcs and sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations , and the quartus tm development system for windows-based pcs and sun sparcstation and hp 9000 series 700 workstations n additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), verilog h dl , vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and veribest n programming support with altera? master programming unit (mpu), bitblaster tm serial download cable, byteblaster tm parallel port download cable, b yteblastermv tm p arallel port download cable, and m a sterblaster tm serial /un iversal serial bus (usb) communicatio n s cable, as well as programming hardware from third-party manufacturers and any jam tm file ( .jam ), jam byte - code file ( .jbc ), o r serial vector format file - ( .svf ) c apable in- circuit tester (the byteblaster cable is obsolete and is replaced by the byteblastermv cable)
altera corporation 3 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation general description max 7000a (including max 7000ae) devices are high-density, high- performance devices based on altera? second-generation max architecture. fabricated with advanced cmos technology, the eeprom- based max 7000a devices operate with a 3.3-v supply voltage and provide 600 to 10,000 usable gates, isp, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 192.3 mhz. max 7000a devices in the - 4, -5, - 6, -7, and -10 speed grades are compatible with the timing requirements o f th e pci s pecial interest group (pci sig) pci local bu s specification , revision 2.2 . see table 2 . notes: (1) contact altera applications for up-to-date information on available device speed grades. (2) timing parameters for these speed grades are preliminary. table 2. max 7000a s peed grades notes (1) , (2) device speed grade -4 -5 -6 -7 -10 -12 epm7032ae v v v epm7064ae v v v epm7128a v v v v epm7128ae v v v epm7256a v v v epm7256ae v v v EPM7512AE v v v
4 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation the max 7000a architecture supports 100 % ttl emulation and high- density integration of ssi, msi, and lsi logic functions. it easily integrates multiple devices ranging from pals, gals, and 22v10s to mach, and plsi devices. max 7000a devices are available in a wide range of packages, including plcc, bga , fineline bga, pqfp, and tqfp packages. see table 3 . notes: (1) contact altera for up-to-date information on available device package options. (2) when the ieee std. 1149.1 (jtag) interface is used for in-system programming or boundary-scan testing, four i/o pins become jtag pins. (3) all fineline bga packages are footprint-compatible via the sameframe feature. therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. device migration is fully supported by altera development tools. see sameframe pin-outs ?on page 14 for more details. max 7000a devices use cmos eeprom cells to implement logic functions. the user-configurable max 7000a architecture accommodates a variety of independent combinatorial and sequential logic functions. the devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. max 7000a devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register with independently programmable clock, clock enable, clear, and pres et functions. to build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms to provide up to 32 product terms per macrocell. table 3. max 7000a maxi mum user i/o pins notes (1) , (2) device 44-pin plcc 44-pin tqfp 84-pin plcc 100-pin tqfp 100-pin fineline bga (3) 144-pin tqfp 208-pin pqfp 256-pin bga 256-pin fineline bga (3) epm7032ae 36 36 epm7064ae 36 36 68 68 68 epm7128a 68 84 84 100 100 epm7128ae 68 84 84 100 100 epm7256a 84 120 164 164 epm7256ae 84 84 120 164 164 EPM7512AE 120 176 212 212
altera corporation 5 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation max 7000a devices provide programmabl e speed/power optimization. speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. this speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50 % or lower power while adding only a nominal timing delay. max 7000a devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. the output drivers of all max 7000a devices can be set for 2.5 v or 3.3 v and all input pins are 2.5-v, 3.3-v, and 5 .0- v tolerant, allowing max 7000a devices to be used in mixed-voltage systems. max 7000a devices are supported by the quartus and max+plus ii development systems, which are integrated packages that offer schematic, text?ncluding vhdl, verilog hdl, and the altera hardware description language (ahdl)?nd waveform design entry , c ompilation and logic synthesis , s imulation and timing analysis , a nd device programming. the quartus and max+plus ii software provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry- standard pc- and unix-workstation-based eda tools. the max+plus ii software runs on windows-based pcs, as well as s un sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations. the quartus software runs on windows-based pcs, as well as sun sparcstation and hp 9000 series 700 workstations . f for more information on development tools, see the max+plus ii programmable logic development system & software data sheet and the quartus programmable logic development system data sheet . funct ional description the max 7000a architecture includes the following elements: n logic array blocks (labs) n macrocells n expander product terms (shareable and parallel) n programmable interconnect array n i/o control blocks the max 7000a architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and i/o pin. figure 1 shows the architecture of max 7000a devices .
6 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 1. max 7000a device block diagram note: (1) epm7032ae, epm7064ae, epm7128a, epm7128ae, epm7256a, and epm7256ae devices have six output enables. EPM7512AE devices have 10 output enables. l ogic array blocks the max 7000a device architecture is based on the linking of high-performance labs. labs consist of 16-macrocell arrays, as shown in figure 1 . multiple labs are linked together via the pia, a global bus that is fed by all dedicated input pins, i/o pins, and macrocells. each lab is fed by the following signals: n 36 signals from the pia that are used for general logic inputs n global controls that are used for secondary register functions n direct input paths from i/o pins to the registers that are used for fast setup times 6 6 i n p u t / g c l r n 6 o r 1 0 o u t p u t e n a b l e s ( 1 ) 6 o r 1 0 o u t p u t e n a b l e s ( 1 ) 1 6 3 6 3 6 1 6 i / o c o n t r o l b l o c k l a b c l a b d i / o c o n t r o l b l o c k 6 1 6 3 6 3 6 1 6 i / o c o n t r o l b l o c k l a b a m a c r o c e l l s 1 t o 1 6 l a b b i / o c o n t r o l b l o c k 6 p i a i n p u t / g c l k 1 i n p u t / o e 2 / g c l k 2 i n p u t / o e 1 3 t o 1 6 i / o 3 t o 1 6 i / o 3 t o 1 6 i / o 3 t o 1 6 i / o 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 3 t o 1 6 m a c r o c e l l s 1 7 t o 3 2 m a c r o c e l l s 3 3 t o 4 8 m a c r o c e l l s 4 9 t o 6 4
altera corporation 7 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation ma crocells the max 7000a macrocell can be individually configured for either sequential or combinatorial logic operation. the macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. figure 2 shows the max 7000a macrocell. figure 2. max 7000a macrocell combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. the product-term select matrix allocates these product terms for use as either primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as secondary inputs to the macrocell? register preset, clock, and clock enable control functions. two kinds of expander product terms (?xpanders? are available to supplement macrocell logic resources: n shareable expanders, which are inverted product terms that are fed back into the logic array n parallel expanders, which are product terms borrowed from adjacent macrocells p r o d u c t - t e r m s e l e c t m a t r i x 3 6 s i g n a l s f r o m p i a 1 6 e x p a n d e r p r o d u c t t e r m s l a b l o c a l a r r a y p a r a l l e l l o g i c e x p a n d e r s ( f r o m o t h e r m a c r o c e l l s ) s h a r e d l o g i c e x p a n d e r s c l e a r s e l e c t g l o b a l c l e a r g l o b a l c l o c k s c l o c k / e n a b l e s e l e c t 2 p r n c l r n d / t q e n a r e g i s t e r b y p a s s t o i / o c o n t r o l b l o c k f r o m i / o p i n t o p i a p r o g r a m m a b l e r e g i s t e r f a s t i n p u t s e l e c t v c c
8 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation the max+plus ii development system automatically optimizes product-term allocation according to the logic requirements of the design. for registered functions, each macrocell flipflop can be individually programmed to implement d, t, jk, or sr operation with programmable clock control. the flipflop can be bypassed for combinatorial operation. during design entry, the designer specifies the desired flipflop type; the max+plus ii software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. each programmable register can be clocked in three different modes: n gl obal clo ck signal. this mode achieves the fastest clock-to-output performance. n gl obal clock signal e nabled by an active-high clock enable. a clock enable is generated by a product term. this mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. n ar ray clock implemented with a product term. in this mode, the flipflop can be clocked by signals from buried macrocells or i/o pins. two global clock signals are available in max 7000a devices. as shown in figure 1 , these global clock signals can be the true or the complement of either of the global clock pins, gclk1 or gclk2 . each register also supports asynchronous preset and clear functions. as shown in figure 2 , the product-term select matrix allocates product terms to control these operations. although the product-term-driven preset and clear from t he register are active high, active-low control can be obtained by inverting the signal within the logic array. in addition, each register clear function can be individually driven by the active-low dedicated global clear pin ( gclrn ). upon power-up, each register in a max 7000ae device may be set to either a high or low state. this power-up state is specified at design entry. all max 7000a i/o pins have a fast input path to a macrocell register. this dedicated path allows a signal to bypass the pia and combinatorial logic and be clocked to an input d flipflop with an extremely fast ( as low as 2 .5 ns) input setup time.
altera corporation 9 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation expander product t erms although most logic functions can be implemented with the five product terms available in each macrocell, more complex logic functions require additional product terms. another macrocell can be used to supply the required logic resources . ho wever, the max 7000a architecture also offers both shareable and parallel expander product terms (?xpanders? that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. shareable expanders each lab has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. each shareable expander can be used and shared by any or all macrocells in the lab to build complex logic functions. a small delay ( t sexp ) is incurred when shareable expanders are used. figure 3 shows how shareable expanders can feed multiple macrocells. figure 3. max 7000a shareable expanders shareable expanders can be shared by any or all macrocells in an lab. macrocell product-t erm logic product-t erm select matrix macrocell product-t erm logic 36 signals from pia 16 shared expanders
10 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. parallel expanders allow up to 20 product terms to directly feed the macrocell or logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the lab. the max+plus ii compiler can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms. each set of five parallel expanders incurs a small, incremental timing delay ( t pexp ). for example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 t pexp . two groups of eight macrocells within each lab (e.g., macrocells 1 through 8 and 9 through 1 6) form two chains to lend or borrow parallel expanders. a macrocell borrows parallel expanders from lower- numbered macrocells. for example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. within each group of eight, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell.
altera corporation 11 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 4. max 7000a parallel expanders unused product terms in a macrocell can be allocated to a neighboring macrocell. progr ammable interconnect array logic is routed between labs on the pia. this global bus is a programmable path that connects any signal source to any destination on the device. all max 7000a dedicated inputs, i/o pins, and macrocell outputs feed the pia, which makes the signals available throughout the entire device. only the signals required by each lab are actually routed from the pia into the lab. figure 5 shows how the pia signals are routed into the lab. an eeprom cell controls one input to a 2- input and gate, which selects a pia signal to drive into the lab. p r e s e t c l o c k c l e a r p r o d u c t - t e r m s e l e c t m a t r i x p r e s e t c l o c k c l e a r p r o d u c t - t e r m s e l e c t m a t r i x m a c r o c e l l p r o d u c t - t e r m l o g i c f r o m p r e v i o u s m a c r o c e l l t o n e x t m a c r o c e l l m a c r o c e l l p r o d u c t - t e r m l o g i c 3 6 s i g n a l s f r o m p i a 1 6 s h a r e d e x p a n d e r s
12 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 5. max 7000a pia routing while the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (fpgas) are cumulative, variable, and path-dependent, the max 7000a pia has a predictable delay. the pia makes a design? timing performance easy to predict. i/o cont rol blocks the i/o control block allows each i/o pin to be individually configured for input, output, or bidirectional operation. all i/o pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or v cc . figure 6 shows the i/o control block for max 7000a devices. the i/o control block has 6 or 10 g lobal output enable signals that are driven by the true or complement of two output enable signals, a subset of the i/o pins, or a subset of the i/o macrocells. t o l a b p i a s i g n a l s
altera corporation 13 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 6. i/o control blo ck of max 7000a devices when the tri-state buffer control is connected to ground , the output is tri- stated (high impedance) and the i/o pin can be used as a dedicated input. when the tri-state buffer control is connected to v cc , the output is enabled. the max 7000a architecture provides dual i/o feedback, in which macrocell and pin feedbacks are independent. when an i/o pin is configured as an input, the associated macrocell can be used for buried logic. f r o m m a c r o c e l l f a s t i n p u t t o m a c r o c e l l r e g i s t e r s l e w - r a t e c o n t r o l t o p i a t o o t h e r i / o p i n s 6 o r 1 0 g l o b a l o u t p u t e n a b l e s i g n a l s ( 1 ) p i a v c c o p e n - d r a i n o u t p u t o e s e l e c t m u l t i p l e x e r g n d note: (1) epm7032ae, epm7064ae, epm7128a, epm7128ae, e pm7256a , and epm7256ae d evices have six output enable signals. epm 7512 ae devices have 10 output enable signals.
14 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation sam eframe pin-outs max 7000a devices support the sameframe pin-out feature for fineline bga packages. the sameframe pin-out feature is the arrangement of balls on fineline bga packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. sameframe pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. a given printed circuit board (pcb) layout can support multiple device density/package combinations. for example, a single board layout can support a range of devices from an epm7128a device in a 100-pin fineline bga package to an EPM7512AE device in a 256-pin fineline bga package. the quartus and max+plus ii software provides support to design pcbs with sameframe pin-out devices. devices can be defined for present and future use. the quartus and max+plus ii software generates pin-outs describing how to lay out a board to take advantage of this migration (see figure 7 ). figure 7. sameframe pin-out example d e s i g n e d f o r 2 5 6 - p i n f i n e l i n e b g a p a c k a g e p r i n t e d c i r c u i t b o a r d 1 0 0 - p i n f i n e l i n e b g a p a c k a g e ( r e d u c e d i / o c o u n t o r l o g i c r e q u i r e m e n t s ) 2 5 6 - p i n f i n e l i n e b g a p a c k a g e ( i n c r e a s e d i / o c o u n t o r l o g i c r e q u i r e m e n t s ) 1 0 0 - p i n f i n e l i n e b g a 2 5 6 - p i n f i n e l i n e b g a
altera corporation 15 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation i n-system prog ramma- bility (isp) max 7000a devices can be programmed in-system via an industry- standard 4-pin ieee std. 1149.1- 1990 (jtag) interface. isp offers quick, efficient iterations during design development and debugging cycles. the max 7000a architecture internally generates the high programming voltages required to program eeprom cells, allowing in-system programming with only a single 3.3-v power supply. during in-system programming, the i/o pins are tri-stated and weakly pulled-up to eliminate board conflicts. the pull-up value is nominally 50 k w . m ax 7000ae devices have an enhanced isp algorithm for faster programming. these devices also offer an isp_done bit that provides safe operation when in-system programming is interrupted. this isp_done bit, which is the last bit programmed, prevents all i/o pins from driving until the bit is programmed. this feature is available in epm7032ae, epm7064ae, epm7128ae, epm7256ae, a nd e pm 7512ae devices only. isp simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board (pcb) with standard pick-and-place equipment before they are programmed. max 7000a devices can be programmed by downloading the information via in-circuit testers, embedded processors, the altera bitbla ster serial download cable, byteblaster parallel port download cable, by te bl aste rmv parallel port download cable , and masterblaster serial/usb communications cable. programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., qfp packages) due to device handling. max 7000a devices can be reprogrammed after a system has already shipped to the field. for example, product upgrades can be performed in the field via software or modem. in-system programming can be accomplished with either an adaptive or constant algorithm. an adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. a constant algorithm uses a pre- defined (non-adaptive) programming sequence that does not take advantage of adaptive algorithm programming time improvements. some automatic test equipment (ate) cannot program using an adaptive algorithm. therefore, a constant algorithm must be used. max 7000ae devices can be programmed with either an adaptive or constant (non- adaptive) algorithm. epm7218a and epm7256a device can only be programmed with an adaptive algorithm; users programming these two devices on platforms that cannot use an adaptive algorithm should use epm7128ae and epm7256ae devices. the jam p rogramming and test l anguage can be used to program max 7000a devices with in-circuit test ers , pc s , or embedded processor s. f for more information on using the jam language, see application note 88 (using the jam language for isp & icr via an embedded processor) .
16 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation program ming with external hardware max 7000a devices can be programmed on windows-based pcs with an altera logic programmer card, the mpu, and the appropriate device adapter. the mpu performs continuity checking to ensure adequate electrical contact between the adapter and the device. for more information, see the altera programming hardware data sheet . the max+plus ii software can use text- or waveform-format test vectors created with the max+plus ii text editor or waveform editor to test the programmed device. for added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. data i/o, bp microsystems, and other programming hardware manufacturers provide programming support for altera devices. for more information, see programming hardware manufacturers . iee e std. 1149.1 ( j t ag) b oundar y-scan support max 7000a devices include the jtag bst circuitry defined by ieee std. 1149.1-1990. table 4 describes the jtag instructions supported by max 7000a devices. the pin- out tables starting on page 41 of this data sheet show the location of the jtag control pins for each device. if the jtag interface is not required, the jtag pins are available as user i/o pins. table 4. max 7000a jtag instructions jtag instruction description sample/prelo ad allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. extest allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. byp ass places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a selected device to adjacent devices during normal device operation. idcode selects the idcode register and places it between the tdi and tdo pins , allowing the idcode to be serially shifted out of tdo . usercode selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode value to be shifted out of tdo . usercode instructions are available for max 7000ae devices only. uescode these instructions select the user electronic signature (uescode) and allow the uescode to be shifted out of tdo . uescode instructions are available for epm7128a and epm7256a devices only. isp instr uctions these instructions are used when programming max 7000a devices via the jtag ports with the bitblaster, byteblaster, b yteblastermv , or masterblaster d ownload cable, or using a jam file ( .jam ), jam byte-code file ( .jbc ), or serial vector format file ( .svf ) via an embedded processor or test equipment.
altera corporation 17 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation the instruction register length of max 7000a devices is 10 bits. the ues register length in max 7000a devices is 16 bits. the max 7000ae usercode register length is 32 bits. tables 5 and 6 show the boundary- scan register length and device idcode information for max 7000a devices. note s to tables : (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) for all jtag idcodes is 1 . f see application note 39 (ieee 1149.1 (jtag) boundary-scan testing in altera devices) for more information on jtag bst. table 5. max 7000a boundary-scan register length device boundary-scan register length epm7032ae 96 epm7064ae 192 epm7128a 288 epm7128ae 288 epm7256a 480 epm7256ae 480 EPM7512AE 624 table 6. 32-bit max 7000a device idcode note (1) device idcode (32 bits) version (4 b its) part number (16 b its) manufacturer? identity (11 b its) 1 (1 b it) (2) epm7032ae 0001 0111 0000 0011 0010 00001101110 1 epm7064ae 0001 0111 0000 0110 0100 00001101110 1 epm7128a 0000 0111 0001 0010 1000 00001101110 1 epm7128ae 0001 0111 0001 0010 1000 00001101110 1 epm7256a 0000 0111 0010 0101 0110 00001101110 1 epm7256ae 0001 0111 0010 0101 0110 00001101110 1 EPM7512AE 0001 0111 0101 0001 0010 00001101110 1
18 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 8 shows the timing information for the jtag signals. figure 8. max 7000a jt ag w aveforms table 7 shows the jtag timing parameters and values for max 7000a devices. table 7. jtag timing parameters & values for max 7000a devices symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns t d o t c k t j p z x t j p c o t j p h t j p x z t j c p t j p s u t j c l t j c h t d i t m s s i g n a l t o b e c a p t u r e d s i g n a l t o b e d r i v e n t j s z x t j s s u t j s h t j s c o t j s x z
altera corporation 19 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation programmable speed/power control max 7000a devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. this feature allows total power dissipation to be reduced by 50 % or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. the designer can program each individual macrocell in a max 7000a device for either high-speed or low-power operation. as a result, speed- critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. macrocells that run at low power incur a nominal timing delay adder ( t lpa ) for the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters. output con guration max 7000a device outputs can be programmed to meet a variety of system-level requirements. mult iv olt i/o interface the max 7000a device architecture supports the multivolt i/o interface feature, which allows max 7000a devices to connect to systems with differing supply voltages. max 7000a devices in all packages can be set for 2.5-v, 3.3-v, or 5.0-v i/o pin operation. these devices have one set of v cc pins for internal operation and input buffers ( v ccint ), and another set for i/o output drivers ( v ccio ). the v ccio pins can be connected to either a 3.3-v or 2.5-v power supply, depending on the output requirements. when the v ccio pins are connected to a 2.5-v power supply, the output levels are compatible with 2.5-v systems. when the v ccio pins are connected to a 3.3-v power supply, the output high is at 3.3 v and is therefore compatible with 3.3- v or 5.0-v systems. devices operating with v ccio levels lower than 3.0 v incur a nominally greater timing delay of t od2 instead of t od1 . inputs can always be driven by 2.5-v, 3.3-v, or 5.0-v signals. table 8 describes the max 7000a multivolt i/o support. table 8. max 7000a multivolt i/o support v ccio voltage input signal (v) output signal (v) 2.5 3.3 5.0 2.5 3.3 5.0 2.5 v v v v 3.3 v v v v v
20 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation open-dr ain output option max 7000a devices provide an optional open-drain (equivalent to open- collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. it can also provide an additional wired- or plane. open-drain output pins on max 7000a devices (with a pull-up resistor to the 5.0-v supply) can drive 5.0-v cmos input pins that require a v ih of 3.5 v. when the open-drain pin is active, it will drive low. when the pin is inactive, the trace will be pulled up to 5.0 v by the resistor. the open- drain pin will only drive low or tri-state; it will never drive high. the rise time is dependent on the value of the pull-up resistor and load impedance. the i ol current specification should be considered when selecting a pull-up resistor. programmable ground pins each unused i/o pin on max 7000a devices may be used as an additional ground pin. in epm7128a and epm7256a devices, utilizing unused i/o pins as additional ground pins requires using the associated macrocell. in max 7000ae devices, this programmable ground feature does not require the use of the associated macrocell; therefore, the buried macrocell is still available for user logic. slew-r ate control the output buffer for each max 7000a i/o pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. a faster slew rate provides high-speed transitions for high-performance systems. however, these fast transitions may introduce noise transients into the system. a slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. when the configuration cell is turned off, the slew rate is set for low-noise performance. each i/o pin has an individual eeprom bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. the slew rate control affects both the rising and falling edges of the output signal.
altera corporation 21 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation power sequencing & hot-socketing because max 7000a family devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. the v ccio and v ccint power planes can be powered in any order. signals can be driven into max 7000a devices before and during power up without damaging the device. additionally, max 7000a devices do not drive out during power up. once operating conditions are reached, max 7000a devices operate as specified by the user. design security all max 7000a devices contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security, because programmed data within eeprom cells is invisible. the security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. generic t esting max 7000a devices are fully functionally tested. complete testing of each programmable eeprom bit and all internal logic elements ensures 100 % programming yield. ac test measurements are taken under conditions equivalent to those shown in figure 9 . test patterns can be used and then erased during early stages of the production flow. figure 9. max 7000a ac t est conditions v c c t o t e s t s y s t e m c 1 ( i n c l u d e s j i g c a p a c i t a n c e ) d e v i c e i n p u t r i s e a n d f a l l t i m e s < 2 n s d e v i c e o u t p u t 7 0 3 w [ 5 2 1 w ] 8 , 0 6 0 w [ 4 8 1 w ] power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be per formed under ac conditions. large-amplitude, fast-ground- current transients normally occur as the device outputs discharge the load capacitances. when these transients ow through the parasitic inductance between the device ground pin and the test system ground, signi cant reductions in obser vable noise immunity can result. numbers in brackets are for 2.5-v outputs. numbers without brackets are for 3.3-v devices or outputs.
22 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation opera ting conditions tables 9 through 12 p rovide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for max 7000a devices . table 9. max 7000a device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) ?.5 4.6 v v i dc input voltage ?.0 5.75 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 ?c t a ambient temperature under bias ?5 135 ?c t j junction temperature bga, fineline bga, pqfp, and tqfp packages, under bias 135 ?c table 10. max 7000a device recomm ended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) 3.0 3.6 v v ccio supply voltage for output drivers, 3.3-v operation (3) 3.0 3.6 v supply voltage for output drivers, 2.5-v operation (3) 2.3 2.7 v v ccisp supply voltage during in- system programming 3.0 3.6 v v i input voltage (4) ?.5 5.75 v v o output voltage 0 v ccio v t a ambient temperature for commercial use 0 70 ?c for industrial use ?0 85 ?c t j junction temperature for commercial use 0 90 ?c for industrial use ?0 105 ?c t r input rise time 40 ns t f input fall time 40 ns
altera corporation 23 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 11. max 7000a device dc operating conditions note (5) symbol parameter conditions min max unit v ih high-level input voltage 1.7 5.75 v v il low-level input voltage ?.5 0.8 v v oh 3.3-v high-level ttl output voltage i oh = ? ma dc, v ccio = 3.00 v (6) 2.4 v 3.3-v high-level cmos output voltage i oh = ?.1 ma dc, v ccio = 3.00 v (6) v ccio ?0.2 v 2.5-v high-level output voltage i oh = ?00 ? dc, v ccio = 2.30 v (6) 2.1 v i oh = ? ma dc, v ccio = 2.30 v (6) 2.0 v i oh = ? ma dc, v ccio = 2.30 v (6) 1.7 v v ol 3.3-v low-level ttl output voltage i ol = 8 ma dc, v ccio = 3.00 v (7) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.00 v (7) 0.2 v 2.5-v low-level output voltage i ol = 100 ? dc, v ccio = 2.30 v (7) 0.2 v i ol = 1 ma dc, v ccio = 2.30 v (7) 0.4 v i ol = 2 ma dc, v ccio = 2.30 v (7) 0.7 v i i input leakage current v i = v ccint or ground ?0 10 ? i oz tri-state output off-state current v o = v ccint or ground ?0 10 ? r isp value of i/o pin pull-up resistor during programming in-system or during power-up v ccio = 3.0 to 3.6 v (8) 20 50 k w v ccio = 2.3 to 2.7 v (8) 30 80 k w v ccio = 2.3 to 3.6 v (9) 20 74 k w table 12. max 7000a device capacitance note (10) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 8 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 8 pf
24 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation n otes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input voltage is ?.5 v. during transitions, the inputs may undershoot to ?.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) v cc must rise monotonically. (4) in max 7000ae devices, all pins, including dedicated inputs, i/o pins, and jtag pins, may be driven before v ccint and v ccio are powered. (5) these values are specified in table 10 on page 22 . (6) the parameter is measured with 50 % of the outputs each sourcing the specified current. the i oh parameter refers to high-level ttl or cmos output current. (7) the parameter is measured with 50 % of the outputs each sinking the specified current. the i ol parameter refers to low-level ttl or cmos output current. (8) for epm7 128a and epm7256a devices, this pull-up exists while a device is programmed in-system. (9) f or max 7000ae devices, this pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. (10) c apacitance is measured at 25 c and is sample-tested only. the oe1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pf . figure 10 shows the typical output drive characteristics of max 7000a devices. figure 10. output drive characteristics of max 7000a devices t iming model max 7000a device timing can be analyzed with the quartus and max+plus ii software, with a variety of popular industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 11 . max 7000a devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. the max+plus ii software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. v o o u t p u t v o l t a g e ( v ) 1 2 3 4 1 0 2 0 3 0 4 0 i o l i o h v c c i n t = 3 . 3 v v c c i o = 3 . 3 v r o o m t e m p e r a t u r e 5 0 6 0 t y p i c a l i o u t p u t c u r r e n t ( m a ) o v o o u t p u t v o l t a g e ( v ) 1 2 3 4 1 0 2 0 3 0 4 0 v c c i n t = 3 . 3 v v c c i o = 2 . 5 v i o l i o h r o o m t e m p e r a t u r e 5 0 6 0 2 . 5 v 3 . 3 v t y p i c a l i o u t p u t c u r r e n t ( m a ) o
altera corporation 25 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 11. max 7000a t iming model t he timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. external timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. figure 12 shows the timing relationship between internal and external delay parameters. f see application note 94 (understanding max 7000 timing) for more information. l o g i c a r r a y d e l a y t l a d o u t p u t d e l a y t o d 3 t o d 2 t o d 1 t x z z t x 1 t z x 2 t z x 3 i n p u t d e l a y t i n r e g i s t e r d e l a y t s u t h t p r e t c l r t r d t c o m b t f s u t f h p i a d e l a y t p i a s h a r e d e x p a n d e r d e l a y t s e x p r e g i s t e r c o n t r o l d e l a y t l a c t i c t e n i / o d e l a y t i o g l o b a l c o n t r o l d e l a y t g l o b i n t e r n a l o u t p u t e n a b l e d e l a y t i o e p a r a l l e l e x p a n d e r d e l a y t p e x p f a s t i n p u t d e l a y t f i n
26 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 12. max 7000a switching w aveforms combinatorial mode input pin i/o pin pia delay shared expander delay logic array input parallel expander delay logic array output output pin t in t la c , t lad t pia t od t pexp t io t sexp t comb global clock mode global clock pin global clock at register data or enable (logic array output) t f t ch t cl t r t in t glob t su t h array clock mode input or i/o pin clock into pia clock into logic array clock at register data from logic array register to pia to logic array register output to pin t f t r t a ch t a cl t su t in t io t rd t pia t clr , t pre t h t pia t ic t pia t od t od t r & t f < 2 ns . i nputs are driven at 3 v f or a logic high and 0 v f or a logic low . all timing characteristics are measured at 1.5 v .
altera corporation 27 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation tables 13 through 20 show epm7128a, epm7256a, a nd max 7000a e a c operating conditions. table 13. epm7128a external timing parameters note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t su global clock setup time (2) 4.2 5.3 7.0 8.5 ns t h global clock hold time (2) 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.7 1.0 4.6 1.0 6.1 1.0 7.3 ns t ch global clock high time 3.0 3.0 4.0 5.0 ns t cl global clock low time 3.0 3.0 4.0 5.0 ns t asu array clock setup time (2) 1.9 2.4 3.1 3.8 ns t ah array clock hold time (2) 1.5 2.2 3.3 4.3 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 6.0 1.0 7.5 1.0 10.0 1.0 12.0 ns t ach array clock high time 3.0 3.0 4.0 5.0 ns t acl array clock low time 3.0 3.0 4.0 5.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 3.0 4.0 5.0 ns t cnt minimum global clock period (2) 6.9 8.6 11.5 13.8 ns f cnt maximum internal global clock frequency (2) , (4) 144.9 116.3 87.0 72.5 mhz t acnt minimum array clock period (2) 6.9 8.6 11.5 13.8 ns f acnt maximum internal array clock frequency (2) , (4) 144.9 116.3 87 72.5 mhz f max maximum clock frequency (5) 166.7 166.7 125.0 100.0 mhz
28 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 14. epm7128a interna l timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t in input pad and buffer delay 0.6 0.7 0.9 1.1 ns t io i/o input pad and buffer delay 0.6 0.7 0.9 1.1 ns t fin fast input delay 2.7 3.1 3.6 3.9 ns t sexp shared expander delay 2.5 3.2 4.3 5.1 ns t pexp parallel expander delay 0.7 0.8 1.1 1.3 ns t lad logic array delay 2.4 3.0 4.1 4.9 ns t lac logic control array delay 2.4 3.0 4.1 4.9 ns t ioe internal output enable delay 0.0 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.4 0.6 0.7 0.9 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 0.9 1.1 1.2 1.4 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.4 5.6 5.7 5.9 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 4.5 4.5 5.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 9.0 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 5.0 ns t su register setup time 1.9 2.4 3.1 3.8 ns t h register hold time 1.5 2.2 3.3 4.3 ns t fsu register setup time of fast input 0.8 1.1 1.1 1.1 ns t fh register hold time of fast input 1.7 1.9 1.9 1.9 ns
altera corporation 29 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation t rd register delay 1.7 2.1 2.8 3.3 ns t comb combinatorial delay 1.7 2.1 2.8 3.3 ns t ic array clock delay 2.4 3.0 4.1 4.9 ns t en register enable time 2.4 3.0 4.1 4.9 ns t glob global control delay 1.0 1.2 1.7 2.0 ns t pre register preset time 3.1 3.9 5.2 6.2 ns t clr register clear time 3.1 3.9 5.2 6.2 ns t pia pia delay (2) 0.9 1.1 1.5 1.8 ns t lpa low-power adder (7) 11.0 10.0 10.0 10.0 ns table 14. epm7128a interna l timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max
30 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 15. epm7256a exter nal timing parameters note (1) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 6.0 7.5 10.0 12.0 ns t su global clock setup time (2) 3.7 4.6 6.2 7.4 ns t h global clock hold time (2) 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.3 1.0 4.2 1.0 5.5 1.0 6.6 ns t ch global clock high time 3.0 3.0 4.0 4.0 ns t cl global clock low time 3.0 3.0 4.0 4.0 ns t asu array clock setup time (2) 0.8 1.0 1.4 1.6 ns t ah array clock hold time (2) 1.9 2.7 4.0 5.1 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 6.2 1.0 7.8 1.0 10.3 1.0 12.4 ns t ach array clock high time 3.0 3.0 4.0 4.0 ns t acl array clock low time 3.0 3.0 4.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 3.0 4.0 4.0 ns t cnt minimum global clock period (2) 6.4 8.0 10.7 12.8 ns f cnt maximum internal global clock frequency (2) , (4) 156.3 125.0 93.5 78.1 mhz t acnt minimum array clock period (2) 6.4 8.0 10.7 12.8 ns f acnt maximum internal array clock frequency (2) , (4) 156.3 125.0 93.5 78.1 mhz f max maximum clock frequency (2) , (5) 166.7 166.7 125.0 125.0 mhz
altera corporation 31 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 16. epm7256a internal timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max t in input pad and buffer delay 0.3 0.4 0.5 0.6 ns t io i/o input pad and buffer delay 0.3 0.4 0.5 0.6 ns t fin fast input delay 2.4 3.0 3.4 3.8 ns t sexp shared expander delay 2.8 3.5 4.7 5.6 ns t pexp parallel expander delay 0.5 0.6 0.8 1.0 ns t lad logic array delay 2.5 3.1 4.2 5.0 ns t lac logic control array delay 2.5 3.1 4.2 5.0 ns t ioe internal output enable delay 0.2 0.3 0.4 0.5 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.3 0.4 0.5 0.6 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 0.8 0.9 1.0 1.1 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.3 5.4 5.5 5.6 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 5.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 4.5 4.5 5.5 5.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 9.0 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 5.0 ns t su register setup time 1.0 1.3 1.7 2.0 ns t h register hold time 1.7 2.4 3.7 4.7 ns
32 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation t fsu register setup time of fast input 1.2 1.4 1.4 1.4 ns t fh register hold time of fast input 1.3 1.6 1.6 1.6 ns t rd register delay 1.6 2.0 2.7 3.2 ns t comb combinatorial delay 1.6 2.0 2.7 3.2 ns t ic array clock delay 2.7 3.4 4.5 5.4 ns t en register enable time 2.5 3.1 4.2 5.0 ns t glob global control delay 1.1 1.4 1.8 2.2 ns t pre register preset time 2.3 2.9 3.8 4.6 ns t clr register clear time 2.3 2.9 3.8 4.6 ns t pia pia delay (2) 1.3 1.6 2.1 2.6 ns t lpa low-power adder (7) 11.0 10.0 10.0 10.0 ns table 16. epm7256a internal timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -12 min max min max min max min max
altera corporation 33 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 17. max 7000ae exter nal timing parameters notes (1) , (8) symbol parameter conditions speed grade unit -4 -5 -6 epm7128ae epm7256ae min max min max min max min max t pd1 input to non-registered output c1 = 35 pf (2) 4.5 5.0 5.5 6.0 ns t pd2 i/o input to non- registered output c1 = 35 pf (2) 4.5 5.0 5.5 6.0 ns t su global clock setup time (2) 3.0 3.2 3.5 3.7 ns t h global clock hold time (2) 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 2.5 2.5 2.5 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 2.8 1.0 3.0 1.0 3.2 1.0 3.3 ns t ch global clock high time 2.0 2.0 2.5 3.0 ns t cl global clock low time 2.0 2.0 2.5 3.0 ns t asu array clock setup time (2) 1.4 1.0 0.9 0.8 ns t ah array clock hold time (2) 0.8 0.8 1.6 1.9 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 4.4 1.0 5.2 1.0 5.8 1.0 6.2 ns t ach array clock high time 2.0 2.0 2.5 3.0 ns t acl array clock low time 2.0 2.0 2.5 3.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 2.0 2.5 3.0 ns t cnt minimum global clock period (2) 5.2 5.5 6.1 6.4 ns f cnt maximum internal global clock frequency (2) , (4) 192.3 181.8 163.9 156.3 mhz t acnt minimum array clock period (2) 5.2 5.5 6.1 6.4 ns f acnt maximum internal array clock frequency (2) , (4) 192.3 181.8 163.9 156.3 mhz f max maximum clock frequency (5) 250.0 250.0 200.0 166.7 mhz
34 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 18. max 7000ae internal timing parameters (part 1 of 2) notes (1) , (8) symbol parameter conditions speed grade unit -4 -5 -6 epm7128ae epm7256ae min max min max min max min max t in input pad and buffer delay 0.3 0.3 0.3 0.3 ns t io i/o input pad and buffer delay 0.3 0.3 0.3 0.3 ns t fin fast input delay 2.6 2.6 2. 5 2.4 ns t sexp shared expander delay 1.9 2.4 2. 6 2.8 ns t pexp parallel expander delay 0.5 0.6 0.6 0.5 ns t lad logic array delay 1.9 2.5 2.5 2.5 ns t lac logic control array delay 1.8 2.3 2.4 2.5 ns t ioe internal output enable delay 0.0 0.0 0.1 0.2 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.3 0.4 0.3 0.3 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 0.8 0.9 0.8 0.8 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.3 5.4 5.3 5.3 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 4.0 4.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 4.5 4.5 4.5 4.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 9.0 9.0 9.0 ns
altera corporation 35 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation t xz output buffer disable delay c1 = 5 pf 4.0 4.0 4.0 4.0 ns t su register setup time 1.4 0.8 1.0 1.0 ns t h register hold time 0.8 1.0 1.5 1.7 ns t fsu register setup time of fast input 0.9 0.8 1.1 1.2 ns t fh register hold time of fast input 1.6 1.7 1.4 1.3 ns t rd register delay 1.2 1.4 1.5 1.6 ns t comb combinatorial delay 1.3 1.0 1.3 1.6 ns t ic array clock delay 1.9 2.3 2.6 2.7 ns t en register enable time 1.8 2.3 2.4 2.5 ns t glob global control delay 1.0 0.9 1.1 1.1 ns t pre register preset time 2.3 2.6 2.5 2.3 ns t clr register clear time 2.3 2.6 2.5 2.3 ns t pia pia delay (2) 0.7 0.8 1.1 1.3 ns t lpa low-power adder (7) 12.0 12.0 12.0 11.0 ns table 18. max 7000ae internal timing parameters (part 2 of 2) notes (1) , (8) symbol parameter conditions speed grade unit -4 -5 -6 epm7128ae epm7256ae min max min max min max min max
36 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 19. max 7000ae exter nal timing parameters notes (1) , (8) symbol parameter conditions speed grade unit -7 -10 -12 min max min max min max t pd1 input to non-registered output c1 = 35 pf (2) 7.5 10.0 12.0 ns t pd2 i/o input to non-registered output c1 = 35 pf (2) 7.5 10.0 12.0 ns t su global clock setup time (2) 4.9 6.6 7.8 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 4.5 1.0 5.9 1.0 7.1 ns t ch global clock high time 3.0 4.0 5.0 ns t cl global clock low time 3.0 4.0 5.0 ns t asu array clock setup time (2) 1.6 2.1 2.4 ns t ah array clock hold time (2) 2.1 3.4 4.4 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 7.8 1.0 10.4 1.0 12.5 ns t ach array clock high time 3.0 4.0 5.0 ns t acl array clock low time 3.0 4.0 5.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 4.0 5.0 ns t cnt minimum global clock period (2) 8.4 11.2 13.3 ns f cnt maximum internal global clock frequency (2) , (4) 119.0 89.3 75.2 mhz t acnt minimum array clock period (2) 8.4 11.2 13.3 ns f acnt maximum internal array clock frequency (2) , (4) 119.0 89.3 75.2 mhz f max maximum clock frequency (5) 166.7 125.0 100.0 mhz table 20. max 7000ae internal timing parameters (part 1 of 2) notes (1) , (8) symbol parameter conditions speed grade unit -7 -10 -12 min max min max min max t in input pad and buffer delay 0.4 0.6 0.7 ns t io i/o input pad and buffer delay 0.4 0.6 0.7 ns t fin fast input delay 3.3 3.7 4.1 ns
altera corporation 37 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation t sexp shared expander delay 3.6 4.9 5.9 ns t pexp parallel expander delay 0.8 1.1 1.3 ns t lad logic array delay 3.7 5.0 6.0 ns t lac logic control array delay 3.4 4.6 5.6 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.6 0.7 0.9 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 1.1 1.2 1.4 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.6 5.7 5.9 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 5.0 5.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 2.5 v c1 = 35 pf (6) 4.5 5.5 5.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 5.0 5.0 ns t su register setup time 1.3 1.7 2.0 ns t h register hold time 2.4 3.8 4.8 ns t fsu register setup time of fast input 1.1 1.1 1.1 ns t fh register hold time of fast input 1.9 1.9 1.9 ns t rd register delay 2.1 2.8 3.3 ns t comb combinatorial delay 1.5 2.0 2.4 ns t ic array clock delay 3.4 4.6 5.6 ns t en register enable time 3.4 4.6 5.6 ns t glob global control delay 1.4 1.8 2.2 ns t pre register preset time 3.9 5.2 6.2 ns t clr register clear time 3.9 5.2 6.2 ns t pia pia delay (2) 1.3 1.7 2.0 ns t lpa low-power adder (7) 10.0 10.0 10.0 ns table 20. max 7000ae internal timing parameters (part 2 of 2) notes (1) , (8) symbol parameter conditions speed grade unit -7 -10 -12 min max min max min max
38 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation notes to tables: (1) these values are specified in table 10 on page 22 . (2) these values are specified fo r a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (3) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (4) m easured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 2.5 0.2 v for commercial and industrial use. (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in low-power mode . (8) max 7000ae timing values are preliminary. p ower con sumption supply power (p) versus frequency ( f max , in mhz) for max 7000a devices is calculated with the following equation: p = p int + p io = i ccint v cc + p io the p io value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluating power for altera devices) . the i ccint value depends on the switching frequency and the application logic. the i ccint value is calculated with the following equation: i ccint = (a mc ton ) + [b (mc dev ?mc ton )] + (c mc used f max tog lc ) the parameters in this equation are: mc ton = number of macrocells with the turb o bit tm option turned on, as reported in the max+plus ii report file ( .rpt ) mc dev = number of macrocells in the device mc used = total number of macrocells in the design, as reported in the report file f max = highest clock frequency to the device tog lc = average percentage of logic cells toggling at each clock (typically 12.5 % ) a, b, c = constants, shown in table 21
altera corporation 39 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation note: (1) values for these devices are preliminary. t his calculation provides an i cc estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each lab with no output load. actual i cc should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. table 21. max 7000a i cc equation constants device a b c epm7032ae (1) 0.46 0.28 0.032 epm7064ae (1) 0.46 0.28 0.032 epm7128a (1) 0.46 0.28 0.032 epm7128ae (1) 0.46 0.28 0.032 epm7256a (1) 0.46 0.28 0.032 epm7256ae (1) 0.46 0.28 0.032 EPM7512AE (1) 0.46 0.28 0.032
40 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 13 shows the typical supply current versus frequency for max 7000a d evices. figure 13. i cc vs. frequency for max 7000a d evices (part 1 of 2) v c c = 3 . 3 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 5 0 1 0 0 1 5 0 2 0 0 1 8 1 . 8 m h z 5 6 . 1 7 m h z 2 5 0 e p m 7 1 2 8 a & e p m 7 1 2 8 a e e p m 7 0 3 2 a e v c c = 3 . 3 v r o o m t e m p e r a t u r e f r e q u e n c y ( m h z ) 3 0 4 0 6 0 7 0 8 0 9 0 v c c = 3 . 3 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 5 0 1 0 0 1 5 0 2 0 0 1 9 2 . 3 m h z 5 8 . 1 m h z 2 5 0 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 e p m 7 0 6 4 a e 1 0 5 0 2 0 1 5 2 0 3 0 3 5 4 0 4 5 h i g h s p e e d l o w p o w e r 1 9 2 . 3 m h z 5 8 . 1 m h z 5 2 5 1 0 t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c 6 0 8 0 1 2 0 1 4 0 1 6 0 1 8 0 2 0 1 0 0 4 0
altera corporation 41 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 13. i cc vs. frequency for max 7000a devices (part 2 of 2) device pin-outs tables 22 through 32 show the pin names and numbers for the pins in max 7000a and max7000ae d evice packages . e p m 7 2 5 6 a & e p m 7 2 5 6 a e v c c = 3 . 3 v r o o m t e m p e r a t u r e f r e q u e n c y ( m h z ) l o w p o w e r 1 6 3 . 9 m h z 5 5 . 2 m h z 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 h i g h s p e e d 0 5 0 1 0 0 1 5 0 2 0 0 t y p i c a l i a c t i v e ( m a ) c c e p m 7 5 1 2 a e v c c = 3 . 3 v r o o m t e m p e r a t u r e f r e q u e n c y ( m h z ) l o w p o w e r 1 1 9 m h z 5 3 . 8 m h z 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 0 2 0 4 0 8 0 1 0 0 t y p i c a l i a c t i v e ( m a ) c c h i g h s p e e d 6 0 1 2 0 1 4 0 table 22. epm7 032ae d edicated pin-outs dedicated pin 44-pin plcc 4 4-pin tqfp input / gclk1 43 37 input / gclrn 1 39 input / oe1 44 38 input / oe2 / gclk2 2 40 tdi (1) 7 1 tms (1) 13 7 tck (1) 32 26 tdo (1) 38 32 gnd int 2 2, 4 2 16 , 3 6 gndio 10, 30 4, 24 vcc int (3.3 v) 3, 2 3 1 7, 4 1 vccio (2.5 v or 3.3 v) 15, 35 9, 29 no connect (n.c.) total user i/o pins (2) 36 36
42 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 23. epm7032ae i/o pin-outs lab mc 44-pi n plcc 44-pin tqfp lab mc 44-pin plcc 44-pin tqfp a 1 4 42 b 17 41 35 2 5 43 18 40 34 3 6 44 19 39 33 4 7 (1) 1 (1) 20 38 (1) 32 (1) 5 8 2 21 37 31 6 9 3 22 36 30 7 11 5 23 34 28 8 12 6 24 33 27 9 13 (1) 7 (1) 25 32 (1) 26 (1) 10 14 8 26 31 25 11 16 10 27 29 23 12 17 11 28 28 22 13 18 12 29 27 21 14 19 13 30 26 20 15 20 14 31 25 19 16 21 15 32 24 18
altera corporation 43 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 24. epm7064ae dedicated pin-outs dedicated pin 44-pin plcc 44-pin tqfp 100-pin tqfp 100-pin fineline bga input / gclk1 43 37 87 a6 input / gclrn 1 39 89 b5 input / oe1 44 38 88 b6 input / oe2 / gclk2 2 40 90 a5 tdi (1) 7 1 4 a1 tms (1) 13 7 15 f3 tck (1) 32 26 62 f8 tdo (1) 38 32 73 a10 gndint 22, 42 16, 36 38, 86 c3, d6, d7, e5, f6, g4, g5, h8 gndio 10, 30 4, 24 11, 26, 43, 59, 74, 95 vccint (3.3 v only) 3, 23 17, 41 39, 91 d5, g6 vccio (2.5 v or 3.3 v) 15, 35 9, 29 3, 18, 34, 51, 66, 82 c8, d4, e6, f5, g7, h3 no connect (n.c.) 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 b1, b10, c1, c9, c10, d8, e3, e4, h1, h9, h10, j1, j2, j10, k1, k9 total user i/o pins (2) 36 36 68 68
44 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 25. epm7064ae i/o pin-outs (44-pin plcc & 44-pin tqfp packages) lab mc 44-pin plcc 44-pin tqfp lab mc 44-pin plcc 44-pin tqfp a 1 12 6 c 33 24 18 2 34 3 11 5 35 25 19 4 9 3 36 26 20 5 8 2 37 27 21 6 38 7 39 8 7 (1) 1 (1) 40 28 22 9 41 29 23 10 42 11 6 44 43 12 44 13 45 14 5 43 46 31 25 15 47 16 4 42 48 32 (1) 26 (1) b 17 21 15 d 49 33 27 18 50 19 20 14 51 34 28 20 19 13 52 36 30 21 18 12 53 37 31 22 54 23 55 24 17 11 56 38 (1) 32 (1) 25 16 10 57 39 33 26 48 27 59 28 60 29 61 30 14 8 62 40 34 31 63 32 13 (1) 7 (1) 64 41 35
altera corporation 45 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation notes to tables: (1) this pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for in-system programming, this pin is not available as a user i/o pin. (2) the user i/o pin count includes dedicated input pins and all i/o pins. table 26. epm7064ae i/o pin-outs (100-pin tqfp & 100-pin fineline bga packages) lab mc 100-pin tqfp 100-pin fineline bga lab mc 100-pin tqfp 100-pin fineline bga a 1 14 f4 c 33 40 k6 2 13 e2 34 41 j6 3 12 e1 35 42 h6 4 10 d2 36 44 k7 5 9 d1 37 45 j7 6 8 d3 38 46 h7 7 6 c2 39 47 j8 8 4 (1) a1 (1) 40 48 k8 9 100 b2 41 52 k10 10 99 a2 42 54 j9 11 98 a3 43 56 g9 12 97 b3 44 57 g10 13 96 a4 45 58 g8 14 94 b4 46 60 f9 15 93 c4 47 61 f10 16 92 c5 48 62 (1) f8 (1) b 17 37 k5 d 49 63 f7 18 36 j5 50 64 e9 19 35 h5 51 65 e10 20 33 k4 52 67 e8 21 32 j4 53 68 e7 22 31 h4 54 69 d9 23 30 j3 55 71 d10 24 29 k3 56 73 (1) a10 (1) 25 25 k2 57 75 b9 26 23 h2 48 76 a9 27 21 g2 59 79 a8 28 20 g1 60 80 b8 29 19 g3 61 81 a7 30 17 f2 62 83 b7 31 16 f1 63 84 c7 32 15 (1) f3 (1) 64 85 c6
46 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 27. epm7128a & epm7128ae dedicated pin-outs dedicated pin 84-pin plcc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 256-pin fineline bga input / gclk1 83 87 a6 125 d9 input / gclrn 1 89 b5 127 e8 input / oe1 84 88 b6 126 e9 input / oe2/gclk2 2 90 a5 128 d8 tdi (1) 14 4 a1 4 d4 tms (1) 23 15 f3 20 j6 tck (1) 62 62 f8 89 j11 tdo (1) 71 73 a10 104 d13 gndint 42, 82 38, 86 d6, g5 52, 57, 124, 129 a8, c9, g9, k8, p9 gndio 7, 19, 32, 47, 59, 72 11, 26, 43, 59, 74, 95 c3, d7, e5, f6, g4, h8 3, 13, 17, 33, 59, 64, 85, 105, 135 a3, b10, c2, d14, f6, g10, h8, j9, k7, l11, m3, p6, p10, r2, r3, t1, t15 vccint (3.3 v only) 3, 43 39, 91 d5, g6 51, 58, 123, 130 b9, c8, g8, k9, p8 vccio (2.5 v or 3.3 v) 13, 26, 38, 53, 66, 78 3, 18, 34, 51, 66, 82 c8, d4, e6, f5, g7, h3 24, 50, 73, 76, 95, 115, 144 b3, b5, c14, e15, f11, g3, g7, g15, h9, j8, k10, l3, l6, m15, p14, t2, t3 no connect (n.c.) 1, 2, 12, 19, 34, 35, 36, 43, 46, 47, 48, 49, 66, 75, 90, 103, 108, 120, 121, 122 a1, a2, a4, a5, a6, a7, a9, a10, a11, a12, a13, a14, a15, a16, b1, b2, b4, b6, b7, b8, b11, b12, b13, b14, b 15, b16, c1, c3, c4, c6, c11, c13, c15, c16, d1, d2, d3, d15, d16, e1, e2, e3, e14, e16, f1, f2, f15, f16, g1, g2, g14, g16, h1, h2, h15, h16, j1, j2, j15, j16, k1, k2, k3, k14, k15, k16, l1, l2, l15, l16, m1, m14, m16, n1, n2, n3, n14, n15, n16, p1, p2, p3, p4, p12, p13, p15, p16, r1, r4, r5, r6, r7, r8, r9, r11, r12, r13, r14, r15, r16, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t16 total user i/o pins (2) 68 84 84 100 100
altera corporation 47 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 28. epm7128a & epm7128ae i/o pin-outs (part 1 of 2) lab mc 84-pin plcc 100- pin tqfp 100-pin fineline bga 144-pin tqfp 256-pin fineline bga lab mc 84-pin plcc 100- pin tqfp 100-pin fineline bga 144- pin tqfp 256-pin fineline bga a 1 2 c1 143 f4 c 33 25 k1 32 n4 2 ? 34 3 12 1 b1 142 e4 35 31 24 j1 31 m4 4 141 c5 36 30 m2 5 11 100 b2 140 e5 37 30 23 h1 29 l4 6 10 99 a2 139 d5 38 29 22 h2 28 l5 7 39 8 9 98 a3 138 d6 40 28 21 g2 27 k5 9 97 b3 137 e6 41 20 g1 26 k4 10 42 11 8 96 a4 136 d7 43 27 19 g3 25 k6 12 134 c7 44 23 j3 13 6 94 b4 133 e7 45 25 17 f2 22 j5 14 5 93 c4 132 f7 46 24 16 f1 21 j4 15 47 16 4 92 c5 131 f8 48 23 (1) 15 (1) f3 (1) 20 (1) j6 (1) b 17 22 14 f4 18 j7 d 49 41 37 k5 56 n8 18 50 19 21 13 e2 16 h5 51 40 36 j5 55 m8 20 15 h3 52 54 p7 21 20 12 e1 14 h4 53 39 35 h5 53 l8 22 10 e3 11 h6 54 33 k4 45 n7 23 55 24 18 9 e4 10 h7 56 37 32 j4 44 m7 25 17 8 d2 9 g5 57 36 31 h4 42 l7 26 58 27 16 7 d1 8 g4 59 35 30 j3 41 m6 28 7 f3 60 40 p5 29 15 6 d3 6 g6 61 34 29 k3 39 n6 30 5 c2 5 f5 62 28 j2 38 m5 31 63 32 14 (1) 4 (1) a1 (1) 4 (1) d4 (1) 64 33 27 k2 37 n5
48 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation notes to tables: (1) this pin can function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for bst or in-system programming, this pin is not available as a user i/o pin. (2) the user i/o pin count includes dedicated input pins and all i/o pins. e 65 44 40 k6 60 n9 g 97 63 63 f7 91 j10 66 98 67 45 41 j6 61 m9 99 64 64 e9 92 h12 68 62 r10 100 93 h14 69 46 42 h6 63 l9 101 65 65 e10 94 h13 70 44 k7 65 n10 102 67 e8 96 h11 71 103 72 48 45 j7 67 m10 104 67 68 e7 97 h10 73 49 46 h7 68 l10 105 68 69 d9 98 g12 74 106 75 50 47 j8 69 m11 107 69 70 d10 99 g13 76 70 p11 108 100 f14 77 51 48 k8 71 n11 109 70 71 d8 101 g11 78 49 k9 72 n12 110 72 c9 102 f12 79 111 80 52 50 k10 74 n13 112 71 (1) 73 (1) a10 (1) 104 (1) d13 (1) f 81 52 j10 77 m13 h 113 75 c10 106 f13 82 114 83 54 53 h10 78 l13 115 73 76 b10 107 e13 84 79 l14 116 109 c12 85 55 54 h9 80 l12 117 74 77 b9 110 e12 86 56 55 j9 81 m12 118 75 78 a9 111 d12 87 119 88 57 56 g9 82 k12 120 76 79 a8 112 d11 89 57 g10 83 k13 121 80 b8 113 e11 90 122 91 58 58 g8 84 k11 123 77 81 a7 114 d10 92 86 j14 124 116 c10 93 60 60 f9 87 j12 125 79 83 b7 117 e10 94 61 61 f10 88 j13 126 80 84 c7 118 f10 95 127 96 62 (1) 62 (1) f8 (1) 89 (1) j11 (1) 128 81 85 c6 119 f9 table 28. epm7128a & epm7128ae i/o pin-outs (part 2 of 2) lab mc 84-pin plcc 100- pin tqfp 100-pin fineline bga 144-pin tqfp 256-pin fineline bga lab mc 84-pin plcc 100- pin tqfp 100-pin fineline bga 144- pin tqfp 256-pin fineline bga
altera corporation 49 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 29. epm7256a & epm7256ae dedicated pin-outs dedicated pin 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga input / gclk1 87 a6 125 184 d9 input / gclrn 89 b5 127 182 e8 input / oe1 88 b6 126 183 e9 input / oe2 / gclk2 90 a5 128 181 d8 tdi (1) 4 a1 4 176 d4 tms (1) 15 f3 20 127 j6 tck (1) 62 f8 89 30 j11 tdo (1) 73 a10 104 189 d13 gndint 38, 86 d6, g5 52, 57, 124, 129 75, 82, 180, 185 a8, c9, g9, k8, p9 gndio (2) 11, 26, 43, 59, 74, 95 c3, d7, e5, f6, g4, h8 3, 13, 17, 33, 59, 64, 85, 105, 135 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 a3, b10, c2, d14, f6, g10, h8, j9, k7, l11, m3, p6, p10, r2, r3, t1, t15 vccint (3.3 v only) 39, 91 d5, g6 51, 58, 123, 130 74, 83, 179, 186 b9, c8, g8, k9, p8 vccio (2.5 v or 3.3 v) (2) 3, 18, 34, 51, 66, 82 c8, d4, e6, f5, g7, h3 24, 50, 73, 76, 95, 115, 144 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 b3, b5, c14, e15, f11, g3, g7, g15, h9, j8, k10, l3, l6, m15, p14, t2, t3 no connect (n.c.) 1, 2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 a1, a2, a6, a12, a13, a14, a15, a16, b1, b2, b15, b16, c1, c15, c16, d1, d3, d15, d16, g1, g16, h15, h16, j1, k1, l1, l2, m1, m16, n1, n2, n14, n15, n16, p1, p2, p15, p16, r1, r14, r15, r16, t7, t8, t10, t11, t14, t16 total user i/o pins (3) 84 84 120 164 164
50 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 30. epm7256a & epm7256ae i/o pin-outs (part 1 of 4) lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga a 1 c1 153 c3 c 33 36 108 n4 2 34 3 2 154 c4 35 35 109 p3 4 36 5 b1 1 159 e5 37 34 110 n3 6 143 160 d5 38 111 m4 7 39 8 2 161 c5 40 25 k1 32 112 m2 9 1 162 b4 41 24 j1 31 113 l4 10 42 11 100 b2 142 163 a4 43 23 h1 30 114 l5 12 44 13 141 164 a5 45 22 h2 29 115 k6 14 99 a2 140 166 d6 46 117 k5 15 47 16 98 a3 139 167 c6 48 21 g2 28 118 k4 b 17 141 f5 d 49 31 h4 44 92 n6 18 50 19 10 142 f2 51 30 j3 43 93 t5 20 52 21 9 144 e1 53 29 k3 42 95 m6 22 145 f4 54 28 j2 41 96 r5 23 55 24 8 d2 8 146 f3 56 40 97 m5 25 7 d1 7 147 e2 57 98 p5 26 58 27 6 d3 6 148 d2 59 39 99 n5 28 60 29 5 c2 5 149 e3 61 38 100 t4 30 150 e4 62 101 r4 31 63 32 4 (1) a1 (1) 4 (1) 151 d4 (1) 64 27 k2 37 102 p4
altera corporation 51 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation e 65 168 b6 g 97 119 k3 66 98 67 169 e6 99 27 120 k2 68 100 69 138 170 f7 101 26 121 j7 70 171 e7 102 122 h7 71 103 72 97 b3 137 172 d7 104 20 g1 25 123 j5 73 96 a4 136 173 c7 105 19 g3 23 124 j2 74 106 75 94 b4 134 175 b7 107 17 f2 22 126 j3 76 108 77 93 c4 133 176 (1) a7 109 16 f1 21 127 (1) j4 78 132 177 f8 110 128 h6 79 111 80 92 c5 131 178 b8 112 15 (1) f3 (1) 20 (1) 129 j6 (1) f 81 130 h5 h 113 37 k5 79 m8 82 114 83 19 131 h1 115 36 j5 54 80 n8 84 116 85 18 132 h2 117 53 81 l8 86 133 h3 118 35 h5 84 r7 87 119 88 14 f4 16 135 h4 120 49 86 p7 89 13 e2 15 136 g6 121 48 87 n7 90 122 91 12 e1 14 137 g5 123 47 88 m7 92 124 93 10 e3 12 138 g2 125 33 k4 46 89 l7 94 139 g4 126 90 t6 95 127 96 9 e4 11 140 f1 128 32 j4 45 91 r6 table 30. epm7256a & epm7256ae i/o pin-outs (part 2 of 4) lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga
52 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation i 129 80 b8 114 197 c11 k 161 38 k11 130 162 131 81 a7 116 196 b11 163 57 g10 82 37 k12 132 164 133 117 195 a11 165 83 36 k14 134 194 f10 166 35 k13 135 167 136 118 193 e10 168 58 g8 84 34 k15 137 119 192 a10 169 86 33 k16 138 170 139 83 b7 120 190 c10 171 60 f9 87 31 j13 140 172 141 84 c7 121 189 (1) d10 173 61 f10 88 30 (1) j14 142 188 f9 174 29 j12 143 175 144 85 c6 122 187 a9 176 62 (1) f8 (1) 89 (1) 28 j11 (1) j 145 63 f7 27 j15 l 177 78 r8 146 178 147 64 e9 90 26 j16 179 55 77 t9 148 180 149 65 e10 91 25 j10 181 56 76 r9 150 24 h14 182 73 n9 151 183 152 92 22 h13 184 40 k6 60 71 m9 153 93 21 h12 185 41 j6 61 70 l9 154 186 155 67 e8 94 20 h11 187 42 h6 62 69 r10 156 188 157 96 19 h10 189 44 k7 63 68 n10 158 18 g11 190 67 m10 159 191 160 68 e7 97 17 g14 192 45 j7 65 66 l10 table 30. epm7256a & epm7256ae i/o pin-outs (part 3 of 4) lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga
altera corporation 53 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation m 193 106 4 b14 o 225 49 r13 194 226 195 75 c10 107 3 c13 227 74 48 p13 196 228 197 108 206 b13 229 75 47 n13 198 205 f12 230 46 m14 199 231 200 109 204 e12 232 52 j10 77 45 m13 201 76 b10 110 203 d12 233 53 h10 78 44 l13 202 234 203 77 b9 111 202 c12 235 54 h9 79 43 l14 204 236 205 201 b12 237 55 j9 80 42 l12 206 78 a9 112 199 e11 238 40 l15 207 239 208 79 a8 113 198 d11 240 56 g9 81 39 l16 n 209 16 g13 p 241 46 h7 66 65 r11 210 242 211 69 d9 98 15 g12 243 47 j8 67 64 p11 212 244 213 99 13 f16 245 48 k8 68 62 n11 214 12 f15 246 49 k9 69 61 m11 215 247 216 70 d10 100 11 f13 248 60 t12 217 101 10 f14 249 70 59 r12 218 250 219 71 d8 102 9 e16 251 58 m12 220 252 221 72 c9 103 8 e14 253 71 57 p12 222 7 e13 254 56 n12 223 255 224 73 (1) a10 (1) 104 (1) 6 d13 (1) 256 50 k10 72 55 t13 table 30. epm7256a & epm7256ae i/o pin-outs (part 4 of 4) lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga lab mc 100-pin tqfp 100-pin fineline bga 144-pin tqfp 208-pin pqfp 256-pin fineline bga
54 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation notes to tables: (1) this pin can function as either a jtag pin or a user i/o pin. if the device is programmed to use the jtag ports for bst or in-system programming, this pin is not available as a user i/o pin. (2) EPM7512AE devices in the 208-pin pqfp package support vertical migration fr om epm7256e, epm7256s, and epm7256a devices. EPM7512AE devices contain additional i/o pins which ar e no connects on the epm7256e, epm7256s, and epm7256a devices. t o support these additional i/o pins, EPM7512AE devices have two additional vccio (pins 105 and 207) and gndio (pins 51 and 158) pins that ar e no-connect pins on the epm7256e, epm7256s, and epm7256a devices. t o achieve vertical migration between the epm7256a and EPM7512AE devices, the no- connect pins 105 and 207 may be tied to vccio and pins 51 and 158 may be tied to gndio on the epm7256a devices. on the epm7256 e and epm7256s devices, these no-connect pins must not be tied to vccio or gndio . (3) the user i/o pin count includes dedicated input pins and all i/o pins. table 31. EPM7512AE dedicated pin-outs dedicated pin 144-pin tqfp 208-pin pqfp (1) 256-pin bga 256-pin fineline bga input / gclk1 125 184 l1 d9 input / gclrn 127 182 k2 e8 input / oe1 126 183 k1 e9 input / oe2 / gclk2 128 181 k3 d8 tdi (2) 4 176 a2 d4 tms (2) 20 127 b12 j6 tck (2) 89 30 v12 j11 tdo (2) 104 189 y2 d13 gndint 52, 57, 124, 129 75, 82, 180, 185 j20, k4, k18, l2, l17 a8, c9, g9, k8, p9 gndio 3, 13, 17, 33, 59, 64, 85, 105, 135 14, 32, 50, 51, 72, 94, 116, 134, 152, 158, 174, 200 a1, b2, b19, b20, c3, c18, d4, d17, u4, u17, v3, v18, v19, w2, w19, y1, y20 a3, b10, c2, d14, f6, g10, h8, j9, k7, l11, m3, p6, p10, r2, r3, t1, t15 vccint 51, 58, 123, 130 74, 83, 179, 186 j1, j19, l4, m19, m20 b9, c8, g8, k9, p8 vccio 24, 50, 73, 76, 95, 115, 144 5, 23, 41, 63, 85, 105, 107, 125, 143, 165, 191, 207 c4, c17, d3, d5, d16, d18, e4, e17, t4, t17, u3, u5, u16, u18, v2, v4, v17 b3, b5, c14, e15, f11, g3, g7, g15, h9, j8, k10,l3, l6, m15, p14, t2, t3 no connect (n.c.) total user i/o pins (3) 120 176 212 212
altera corporation 55 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation table 32. EPM7512AE i/o pin-outs (part 1 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga a 1 134 173 h3 d7 c 33 142 163 f4 e4 2 34 3 35 4 36 5 h2 c7 37 141 164 e3 c5 6 38 7 39 8 40 9 175 h1 b7 41 140 166 e2 a5 10 42 11 133 176 (2) j4 a7 43 167 f3 d5 12 44 13 45 14 132 177 j3 f8 46 139 168 e1 e5 15 47 16 131 178 j2 b8 48 f2 e6 b 17 169 g4 d6 d 49 2 b3 b2 18 50 19 51 20 52 21 138 170 f1 c6 53 1 c2 a2 22 54 23 55 24 56 25 137 171 g3 b6 57 159 b1 b4 26 58 27 136 172 g2 a6 59 160 c1 a4 28 60 29 61 30 g1 f7 62 161 d2 c4 31 63 32 h4 e7 64 143 162 d1 c3
56 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation e 65 b5 e3 g 97 c9 h6 66 98 67 7 153 c5 c1 99 15 141 d9 g5 68 100 69 d6 b1 101 14 142 a8 g4 70 102 71 103 72 104 73 154 a4 a1 105 144 b8 g2 74 106 75 6 155 b4 d2 107 145 c8 g1 76 108 77 109 78 5 156 a3 d3 110 12 146 d8 g6 79 111 80 4 (2) 157 a2 (2) d4 (2) 112 a7 f5 f 81 147 b7 f2 h 113 19 135 a11 j1 82 114 83 148 c7 f3 115 136 a10 h7 84 116 85 11 149 a6 f1 117 18 137 b10 h5 86 118 87 119 88 120 89 d7 f4 121 d10 h2 90 122 91 10 150 b6 e1 123 138 c10 h3 92 124 93 125 94 9 151 a5 d1 126 139 a9 h1 95 127 96 8 c6 e2 128 16 140 b9 h4 table 32. EPM7512AE i/o pin-outs (part 2 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
altera corporation 57 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation i 129 d12 k1 k 161 29 115 b16 n4 130 162 131 129 c12 j7 163 117 c15 m2 132 164 133 20 (2) 130 b12 (2) j6 (2) 165 118 a17 m1 134 166 135 167 136 168 137 131 a12 j5 169 28 119 b15 m4 138 170 139 d11 j4 171 d14 m5 140 172 141 173 142 132 c11 j3 174 120 a16 l5 143 175 144 133 b11 j2 176 27 121 a15 l4 j 145 122 c14 l2 l 177 34 109 a20 r1 146 178 147 b14 l1 179 148 180 149 26 123 a14 k6 181 32 110 a19 p2 150 182 151 183 152 184 153 25 124 d13 k5 185 111 b17 n3 154 186 155 23 126 c13 k4 187 112 a18 n2 156 188 157 189 158 22 127 (2) b13 k3 190 31 113 d15 p1 159 191 160 21 128 a13 k2 192 30 114 c16 n1 table 32. EPM7512AE i/o pin-outs (part 3 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
58 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation m 193 101 e18 p5 o 225 47 88 h19 r7 194 226 195 227 46 89 h18 p7 196 228 197 102 d20 n5 229 45 90 h17 t7 198 230 199 231 200 232 201 37 103 d19 t4 233 91 g20 l8 202 234 203 104 c20 r4 235 44 92 g19 n7 204 236 205 237 206 36 106 c19 p4 238 g18 m7 207 239 208 35 108 b18 p3 240 43 93 f20 l7 n 209 42 95 g17 r6 p 241 54 79 k20 m9 210 242 211 243 212 244 213 41 96 f19 t6 245 80 k19 l9 214 246 215 247 216 248 217 40 97 e20 n6 249 53 81 k17 r8 218 250 219 39 98 f18 m6 251 84 j18 t8 220 252 221 253 222 99 e19 r5 254 49 86 j17 n8 223 255 224 38 100 f17 t5 256 48 87 h20 m8 table 32. EPM7512AE i/o pin-outs (part 4 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
altera corporation 59 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation q 257 55 78 l20 n9 s 289 66 62 p17 k11 258 290 259 291 260 292 261 77 l19 t9 293 67 61 r19 m12 262 294 263 295 264 296 265 56 76 l18 r9 297 68 60 t20 n12 266 298 267 73 m18 l10 299 69 59 r18 t12 268 300 269 301 270 60 71 m17 m10 302 58 t19 r12 271 303 272 61 70 n20 n10 304 70 57 t18 t13 r 273 62 69 n19 r10 t 305 56 r17 p12 274 306 275 63 68 n18 t10 307 276 308 277 67 n17 m11 309 55 u20 t14 278 310 279 311 280 312 281 66 p20 n11 313 71 54 u19 p13 282 314 283 65 65 p19 p11 315 72 53 v20 r13 284 316 285 317 286 p18 r11 318 52 w20 r14 287 319 288 64 r20 t11 320 74 49 w18 r15 table 32. EPM7512AE i/o pin-outs (part 5 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
60 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation u 321 75 48 y19 p15 w 353 82 35 w14 l16 322 354 323 355 y14 l13 324 356 325 47 y18 n15 357 83 34 u13 l12 326 358 327 359 328 360 329 46 w17 t16 361 84 33 v13 k12 330 362 331 45 y17 r16 363 86 31 w13 k14 332 364 333 365 334 77 44 u15 p16 366 87 30 (2) y13 k15 335 367 336 78 43 v16 n14 368 88 29 u12 k16 v 337 79 42 w16 n16 x 369 89 (2) v12 (2) j11 (2) 338 370 339 80 40 v15 m14 371 28 w12 j12 340 372 341 39 y16 n13 373 27 y12 j13 342 374 343 375 344 376 345 81 38 w15 m16 377 26 v11 j14 346 378 347 u14 m13 379 u11 j15 348 380 349 381 350 37 y15 l14 382 25 w11 k13 351 383 352 36 v14 l15 384 90 24 y11 j16 table 32. EPM7512AE i/o pin-outs (part 6 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
altera corporation 61 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation y 385 91 22 y10 h10 aa 417 10 v7 f14 386 418 387 21 w10 h11 419 9 y6 f15 388 420 389 92 20 v10 h12 421 98 8 u7 f16 390 422 391 423 392 424 393 u10 h15 425 w6 e12 394 426 395 19 y9 h16 427 99 7 y5 e13 396 428 397 429 398 18 w9 h14 430 100 6 v6 e14 399 431 400 93 17 v9 h13 432 101 w5 e16 z 401 u9 g12 bb 433 v5 d16 402 434 403 16 y8 g13 435 102 4 u6 c16 404 436 405 94 15 w8 g14 437 y4 b16 406 438 407 439 408 440 409 96 13 v8 g16 441 3 w4 a16 410 442 411 12 u8 g11 443 103 2 y3 d15 412 444 413 445 414 97 11 y7 f12 446 104 (2) 1 y2 (2) d13 (2) 415 447 416 w7 f13 448 106 208 w3 c15 table 32. EPM7512AE i/o pin-outs (part 7 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
62 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation cc 449 w1 b15 ee 481 196 p3 d11 450 482 451 483 452 484 453 107 v1 a15 485 113 195 p2 c11 454 486 455 487 456 488 457 108 206 u2 b14 489 114 194 p1 a11 458 490 459 205 u1 a14 491 116 193 n4 b11 460 492 461 493 462 204 t3 b13 494 117 n3 f10 463 495 464 109 203 r4 a13 496 n2 e10 dd 465 202 t2 c13 ff 497 118 192 n1 d10 466 498 467 499 468 500 469 110 201 r3 d12 501 m4 c10 470 502 471 503 472 504 473 111 199 t1 c12 505 119 190 m3 a10 474 506 475 198 r2 b12 507 120 189 (2) m2 j10 476 508 477 509 478 112 197 p4 a12 510 121 188 m1 f9 479 511 480 r1 e11 512 122 187 l3 a9 table 32. EPM7512AE i/o pin-outs (part 8 of 8) lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga lab mc 144-pin tqfp 208-pin pqf p (1) 256-pin bga 256-pin fineline bga
altera corporation 63 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation notes to tables : (1) the EPM7512AE device in the 208-pin pqfp package supports vertical migration from the epm7256e, epm7256s, and epm7256a devices. the EPM7512AE device contains additional i/o pins which are no connects on the epm7256e, epm7256s, and epm7256a devices. to support these additional i/o pins, the EPM7512AE device has two additional vccio (pins 105 and 207) and gndio (pins 51 and 158) pins that are no-connect pins on the epm7256e, epm7256s, and epm7256a devices. to achieve vertical migration between the epm7256a and EPM7512AE devices, the no-connect pins 105 and 207 may be tied to vccio and pins 51 and 158 may be tied to gndio on the epm7256a devices. on the epm7256e and epm7256s devices, these no-connect pins must not be tied to vccio or gndio. EPM7512AE devices have identical pin-outs. (2) this pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for in-system programming, this pin is not available as a user i/o pin. (3) the user i/o pin count includes dedicated input pins and all i/o pins. figures 14 through 21 show the package pin-out diagrams for max 7000a devices. figure 14. 44-pin plcc/tqfp package pin-out diagram package outlines not drawn to scale. 4 4 - p i n p l c c i / o i / o i / o v c c i n p u t / o e 2 / ( g c l k 2 ) i n p u t / g c l r n i n p u t / o e 1 n i n p u t / g c l k 1 g n d i / o i / o i / o i / o / ( t d o ) i / o i / o v c c i / o i / o i / o / ( t c k ) i / o g n d i / o i / o i / o i / o i / o g n d v c c i / o i / o i / o i / o i / o 6 5 4 3 2 1 4 4 4 3 4 2 4 1 4 0 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 e p m 7 0 3 2 a e e p m 7 0 6 4 a e i / o / ( t d i ) i / o i / o g n d i / o i / o i / o / ( t m s ) i / o v c c i / o i / o 4 4 - p i n t q f p p i n 1 2 p i n 2 3 p i n 3 4 p i n 1 i / o i / o i / o v c c i n p u t / o e 2 / ( g c l k 2 ) i n p u t / g c l r n i n p u t / o e 1 n i n p u t / g c l k 1 g n d i / o i / o i / o i / o / ( t d o ) i / o i / o v c c i / o i / o i / o / ( t c k ) i / o g n d i / o i / o i / o i / o i / o g n d v c c i / o i / o i / o i / o i / o i / o / ( t d i ) i / o i / o g n d i / o i / o i / o / ( t m s ) i / o v c c i / o i / o e p m 7 0 3 2 a e e p m 7 0 6 4 a e
64 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 15. 8 4-pin plcc package pin-out diagram package outline not drawn to scale. figure 16. 100-pin tqfp package pin-out diagram package outline not drawn to scale. i / o v c c i o i / o / t d i i / o i / o i / o i / o g n d i / o i / o i / o i / o / t m s i / o v c c i o i / o i / o i / o i / o i / o g n d i / o i / o i / o i / o g n d i / o i / o i / o v c c i n t i n p u t / o e 2 / g c l k 2 i n p u t / g l c r n i n p u t / o e 1 i n p u t / g c l k 1 g n d i / o i / o i / o v c c i o i / o i / o i / o 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 1 1 0 9 8 7 6 5 4 3 2 1 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 i / o i / o g n d i / o / t d o i / o i / o i / o i / o v c c i o i / o i / o i / o i / o / t c k i / o i / o g n d i / o i / o i / o i / o i / o i / o i / o i / o i / o i / o v c c i o i / o i / o i / o g n d v c c i n t i / o i / o i / o g n d i / o i / o i / o i / o i / o v c c i o 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 e p m 7 1 2 8 a e p m 7 1 2 8 a e i / o p i n 1 p i n 2 6 p i n 7 6 p i n 5 1 e p m 7 0 6 4 a e e p m 7 1 2 8 a e p m 7 1 2 8 a e e p m 7 2 5 6 a e p m 7 2 5 6 a e
altera corporation 65 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 17. 100-pin fineline bga package pin-out diagram figure 18. 144- pin tqfp pack age pin-out diagram package outline not drawn to scale . i n d i c a t e s l o c a t i o n o f b a l l a 1 a 1 b a l l p a d c o r n e r a b c d e f g h j k 1 0 9 8 7 6 5 4 3 2 1 e p m 7 0 6 4 a e e p m 7 1 2 8 a e p m 7 1 2 8 a e e p m 7 2 5 6 a e package outline not drawn to scale. i n d i c a t e s l o c a t i o n o f p i n 1 p i n 1 p i n 1 0 9 p i n 7 3 p i n 3 7 e p m 7 1 2 8 a e p m 7 1 2 8 a e e p m 7 2 5 6 a e p m 7 2 5 6 a e e p m 7 5 1 2 a e
66 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 19. 208-pin p qfp pack age pin-out diagram package outline not drawn to scale . p i n 1 p i n 1 5 7 p i n 1 0 5 p i n 5 3 e p m 7 2 5 6 a e p m 7 2 5 6 a e e p m 7 5 1 2 a e
altera corporation 67 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 20. 256-pin bga package pin-out diagram package outline not drawn to scale. i n d i c a t e s l o c a t i o n o f b a l l a 1 a 1 b a l l p a d c o r n e r g f e d c b a h j k l m n p r t 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 e p m 7 5 1 2 a e u v w x y 1 7 1 8 1 9 2 0
68 altera corporation max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation figure 21. 256-pi n f ineline bga package pin-out diagram package outline not drawn to scale . revision histor y the information contained in the max 7000a programmable logic device family data sheet version 2.03 s upersedes information published in previous versions. v ersion 2.03 changes the max 7000a programmable logic device family data sheet version 2.03 contains the following change: 100-pin fineline bga package pin-out information added to tables 29 and 30 . i n d i c a t e s l o c a t i o n o f b a l l a 1 a 1 b a l l p a d c o r n e r g f e d c b a h j k l m n p r t 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 e p m 7 1 2 8 a e p m 7 1 2 8 a e e p m 7 2 5 6 a e p m 7 2 5 6 a e e p m 7 5 1 2 a e
altera corporation 69 max 7000a pr ogrammab le logic de vice f amil y data sheet preliminar y inf ormation v ersion 2.02 changes the max 7000a programmable logic device family data sheet version 2.02 contains the following changes: n epm7256ae-5 device information was added throughout the document. n masterblaster serial/usb communications cable was added throughout the document. n isp description was updated on page 15 . n t cppw timing parameter information was clarified in the timing model ?section. n 256-pin bga package diagram was corrected in figure 20 . v ersion 2.01 changes t he m ax 7000a programmable logic device family data sheet version 2.01 contain ed t he following changes: n note (2) on page 24 was updated. n minor stylistic changes were made throughout the data sheet.
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