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18mb: 1.8v v dd , hstl, qdriib2 sram mt54w1mh18b_h.fm ? rev. h, pub. 3/03 1 ?2003 micron technology, inc. 2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb qdr ? ii sram 2-word burst mt54w2mh8b mt54w1mh18b mt54w512h36b features ? dll circuitry for accurate output data placement separate independent read and write data ports with concurrent transactions 100 percent bus utilization ddr read and write operation fast clock to valid data times full data coherency, providing most current data two-tick burst counter for low ddr transaction size double data rate operation on read and write ports two input clocks (k and k#) for precise ddr timing at clock rising edges only two output clocks (c and c#) for precise flight time and clock skew matching?clock and data delivered together to receiving device optional-use echo clocks (cq and cq#) for flexible receive data synchronization single address bus simple control logic for easy depth expansion internally self-timed, registered writes core v dd = 1.8v (0.1v); i/o v dd q = 1.5v to v dd (0.1v) hstl clock-stop capability with s restart 13mm x 15mm, 1mm pitch, 11 x 15 grid fbga package user-programmable impedance output jtag boundary scan general description the micron ? qdr?ii (quad data rate?) synchro- nous, pipelined burst sram employs high-speed, low- power cmos designs using an advanced 6t cmos process. the qdr architecture consists of two separate ddr (double data rate) ports to access the memory array. the read port has dedicated data outputs to support read operations. the write port has dedicated data inputs to support write operations. this architecture eliminates the need for high-speed bus turnaround. access to each port is accomplished using a common address bus. addresses for reads and writes are latched on rising edges of the k and k# input clocks, respec- tively. each address location is associated with two words that burst sequentially into or out of the device. since data can be transferred into and out of the device on every rising edge of both clocks (k and k# and c and c#), memory bandwidth is maximized and system design is simplified by eliminating bus turnarounds. options marking 1 note : 1. a part marking guide for the fbga devices can be found on micron?s web site? http://www.micron.com/numberguide . clock cycle timing 4ns (250 mhz) -4 5ns (200 mhz) -5 6ns (167 mhz) -6 7.5ns (133 mhz) -7.5 configurations 2 meg x 8 mt54w2mh8b 1 meg x 18 mt54w1mh18b 512k x 36 mt54w512h36b package 165-ball, 13mm x 15mm fbga f operating temperature range commercial (0c t a +70c ) none table 1: valid part numbers part number description mt54w2mh8bf-xx 2 meg x 8, qdriib2 fbga mt54w1mh18bf-xx 1 meg x 18, qdriib2 fbga mt54w512h36bf-xx 512k x 36, qdriib2 fbga figure 1: 165-ball fbga
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 2 ?2003 micron technology, inc. depth expansion is accomplished with port selects for each port (read r#, write w#) which are received at k rising edge. port selects permit independent port operation. all synchronous inputs pass through registers con- trolled by the k or k# input clock rising edges. active low byte writes (bwx#) permit byte or nibble write selection. write data and byte writes are registered on the rising edges of both k and k#. the addressing within each burst of two is fixed and sequential, begin- ning with the lowest and ending with the highest address. all synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (c and c# if provided, otherwise k and k#). four balls are used to implement jtag test capabili- ties: test mode select (tms), test data-in (tdi), test clock (tck), and test data-out (tdo). jtag circuitry is used to serially shift data to and from the sram. jtag inputs use jedec-standard 1.8v i/o levels to shift data during this testing mode of operation. the sram operates from a 1.8v power supply, and all inputs and outputs are hstl-compatible. the device is ideally suited for applications that benefit from a high-speed, fully-utilized ddr data bus. please refer to micron?s web site ( www.micron.com/ sramds ) for the latest data sheet. read/write operations all bus transactions operate on an uninterruptable burst of two data, requiring one full clock cycle of bus utilization. the resulting benefit is that short data transactions can remain in operation on both buses provided that the address rate can be maintained by the system (2x the clock frequency). read cycles are pipelined. the request is initiated by asserting r# low at k rising edge. data is delivered after the next rising edge of the next k# (t + 1), using c and c# as the output timing references; or k and k#, if c and c# are tied high. if c and c# are tied high, they may not be toggled during device operation. out- put tri-stating is automatically controlled such that the bus is released if no data is being delivered. this per- mits banked sram systems with no complex output enable (oe) timing generation. back-to-back read cycles are initiated every k rising edge. write cycles are initiated by w# low at k rising edge. the addresses for the write cycle is provided at the following k# rising edge. data is expected at the rising edge of k and k#, beginning at the same k that initiated the cycle. write registers are incorporated to facilitate pipelined, self-timed write cycles and pro- vide fully coherent data for all combinations of reads and writes. a read can immediately follow a write, even if they are to the same address. although the write data has not been written to the memory array, the sram will deliver the data from the write register instead of using the older data from the memory array. the latest data is always utilized for all bus transactions. write cycles can be initiated on every k rising edge. partial write operations byte write operations are supported except for the x8 devices in which nibble write is supported. the active low byte write controls, bwx# (nw#), are regis- tered coincident with their corresponding data. this feature can eliminate the need for some read-mod- ify-write cycles, collapsing it to a single byte/nib- ble write operation in some instances.
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 3 ?2003 micron technology, inc. programmable impedance output buffer the qdr sram is equipped with programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an external precision resistor (rq) is con- nected between the zq ball and v ss . the value of the resistor must be five times the desired impedance. for example, a 350 resistor is required for an output impedance of 70 . to ensure that output impedance is one-fifth the value of rq (within 15 percent), the range of rq is 175 to 350 . alternately, the zq ball can be connected directly to v dd q, which will place the device in a minimum impedance mode. output impedance updates may be required because variations may occur in supply voltage and temperature over time. the device samples the value of rq. impedance updates are transparent to the sys- tem; they do not affect device operation, and all data sheet timing and current specifications are met during an update. the device will power up with an output impedance set at 50 . to guarantee optimum output driver impedance after power-up, the sram needs 1,024 cycles to update the impedance. the user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. clock considerations this device utilizes internal delay-locked loops for maximum output data valid window. it can be placed into a stopped-clock state to minimize power with a modest restart time of 1,024 clock cycles. circuitry automatically resets the dll when the absence of input clock is detected. see micron technical note tn- 54-02 for more information on clock dll start-up pro- cedures. single clock mode the sram can be used with the single k, k# clock pair by tying c and c# high. in this mode the sram will use k and k# in place of c and c#. this mode pro- vides the most rapid data output but does not com- pensate for system clock skew and flight times. the output echo clocks are precise references to output data. cq and cq# are both rising edge and fall- ing edge accurate and are 180 out of phase. either or both may be used for output data capture. k or c rising edge triggers cq rising and cq# falling edge. cq rising edge indicates first data response for qdri and ddri (version 1, non-dll) sram, while cq# rising edge indicates first data response for qdrii and ddrii (ver- sion 2, dll) sram. depth expansion port select inputs are provided for the read and write ports. this allows for easy depth expansion. both port selects are sampled on the rising edge of k only. each port can be independently selected and dese- lected and does not affect the operation of the oppo- site port. all pending transactions are completed prior to a port deselecting. depth expansion requires repli- cating r# and w# control signals for each bank if it is desired to have the bank independent of read and write operations.
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 4 ?2003 micron technology, inc. figure 2: functional block diagram 2 meg x 8; 1 meg x 18; 512k x 36 note : 1. figure 2 illustrates simplified device operation. see truth table, ball descriptions, and timing diagrams for detailed information. 2. for 2 meg x 8, n = 20, a = 8; nwx# = 2 separate nibble writes. for 1 meg x 18, n = 19, a = 18; bwx# = 2 separate byte writes. for 512k x 36, n = 18, a = 36; bwx# = 2 separate byte writes. address d (data in) n n r# w# k k# a 2a 2a 2a k# k r# w# nwx# or bwx# k 2 n x a memory array c address registry & logic data registry & logic c, c# or k, k# a q (data out) 2 cq, cq# (echo clock out) r e g 2 w r i t e mux d r i v e r w r i t e o u t p u t o u t p u t r e g a b u f f e r a m p s s e n s e o u t p u t s e l e c t
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 5 ?2003 micron technology, inc. figure 3: application example note : 1. in this approach, the second clock pair drives the c and c# clocks but is delayed such that return data meets data setup and hold times at the bus master. 2. consult micron technical notes for more thorough discussions of clocking schemes. 3. data capture is possible using only one of the two signals. cq and cq# clocks are optional use outputs. 4. for high frequency applications (200 mhz and faster) the cq and cq# clocks (for data capture) are recommended over the c and c# clocks (for data alignment). the c and c# clocks are optional use inputs. vt = v ref /2 cc# zq q k# d sa k cc# zq q k# d sa k bus master (cpu or asic) sram #1 sram #4 data in data out address read# write# bw# source k source k# delayed k delayed k# r = 50 ? r = 250 ? r = 250 ? r # w # b w # r # w # b w # vt vt vt r r r
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 6 ?2003 micron technology, inc. table 2: 2 meg x 8 ball layout (top view) 165-ball fbga 1234567891011 a cq# v ss / sa 1 sa w# nw1# 2 k# nc/ sa 3 r# sa v ss / sa 4 cq b nc nc nc sa nc/ sa 5 k nw0# 6 sa nc nc q3 c nc nc nc v ss sa sa sa v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v dd qv ss v ss v ss v dd qnc d2 q2 f nc nc nc v dd qv dd v ss v dd v dd qnc nc nc g nc d5 q5 v dd qv dd v ss v dd v dd qnc nc nc h dll# v ref v dd qv dd qv dd v ss v dd v dd qv dd qv ref zq j nc nc nc v dd qv dd v ss v dd v dd qnc q1 d1 k nc nc nc v dd qv dd v ss v dd v dd qnc nc nc l nc q6 d6 v dd qv ss v ss v ss v dd qnc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss sa sa sa v ss nc nc nc p nc nc q7 sa sa c sa sa nc nc nc r tdo tck sa sa sa c# sa sa sa tms tdi note : 1. expansion address: 2a for 72mb 2. nw1# controls writes to d4:d7 3. expansion address: 7a for 144mb 4. expansion address: 10a for 36mb 5. expansion address: 5b for 288mb 6. nw0# controls writes to d0:d3
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 7 ?2003 micron technology, inc. table 3: 1 meg x 18 ball layout (top view) 165-ball fbga 1234567891011 a cq# v ss / sa 1 nc/ sa 2 w# bw1# 3 k# nc/ sa 4 r# sa v ss / sa 5 cq b nc q9 d9 sa nc k bw0# 6 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v dd qv ss v ss v ss v dd qnc d6 q6 f nc q12 d12 v dd qv dd v ss v dd v dd qnc nc q5 g nc d13 q13 v dd qv dd v ss v dd v dd qnc nc d5 h dll# v ref v dd qv dd qv dd v ss v dd v dd qv dd qv ref zq j nc nc d14 v dd qv dd v ss v dd v dd qnc q4 d4 k nc nc q14 v dd qv dd v ss v dd v dd qnc d3 q3 l nc q15 d15 v dd qv ss v ss v ss v dd qnc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c# sa sa sa tms tdi note : 1. expansion address: 2a for 144mb 2. expansion address: 3a for 36mb 3. bw1# controls writes to d9:d17 4. expansion address: 7a for 288mb 5. expansion address: 10a for 72mb 6. bw0# controls writes to d0:d8
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 8 ?2003 micron technology, inc. table 4: 512k x 36 ball layout (top view) 165-ball fbga 1234567891011 a cq# v ss/ sa 1 nc/ sa 2 w# bw2# 3 k# bw1# 4 r# nc/ sa 5 v ss / sa 6 cq b q27 q18 d18 sa bw3# 7 kbw0# 8 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v dd qv ss v ss v ss v dd q q15 d6 q6 f q30 q21 d21 v dd qv dd v ss v dd v dd q d14 q14 q5 g d30 d22 q22 v dd qv dd v ss v dd v dd q q13 d13 d5 h dll# v ref v dd qv dd qv dd v ss v dd v dd qv dd qv ref zq j d31 q31 d23 v dd qv dd v ss v dd v dd q d12 q4 d4 k q32 d32 q23 v dd qv dd v ss v dd v dd q q12 d3 q3 l q33 q24 d24 v dd qv ss v ss v ss v dd q d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa c# sa sa sa tms tdi note : 1. expansion address is 2a for 288mb 2. expansion address is 3a for 72mb 3. bw2# controls writes to d18:d26 4. bw1# controls writes to d9:d17 5. expansion address is 9a for 36mb 6. expansion address is 10a for 144mb 7. bw3# controls writes to d27:d35 8. bw0# controls writes to d0:d8
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 9 ?2003 micron technology, inc. table 5: ball descriptions symbol type description bw_# nw_# input synchronous byte writes (or nibble writes on x8): when low, these inputs cause their respective bytes to be registered and written if w# had initiated a write cycle. these signals must meet setup and hold times around the risi ng edges of k and k# for each of the two rising edges comprising the write cycle. se e ball layout figures for signal to data relationships. c c# input output clock: this clock pair provides a user -controlled means of tuning device output data. the rising edge of c# is used as the output timing reference for first output data. the rising edge of c is used as the output reference for second output data. ideally, c# is 180 degrees out of phase with c. c and c# may be tied hi gh to force the use of k and k# as the output reference clocks instead of having to provide c and c# clocks. if tied high, these inputs may not be allowed to toggle during device operation. d_ input synchronous data inputs: input data must meet setup and hold times around the rising edges of k and k# during write oper ations. see ball layout figures for ball site location of individual signals. the x8 device uses d0:d7. remaining signals are nc. the x18 device uses d0:d17. remaining signals are nc. the x36 device uses d0:d35. remaining signals are nc. dll# input dll disable: when low, this input causes th e dll to be bypassed for stable, low-frequency operation. k k# input input clock: this input clock pair registers addr ess and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k#. k# is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. r# input synchronous read: when low, this input causes the address inputs to be registered and a read cycle to be initiated. this input must me et setup and hold times around the rising edge of k and is ignored on the s ubsequent rising edge of k. sa input synchronous address inputs: these inputs are re gistered and must meet the setup and hold times around the rising edge of k for read cycles and must meet the setup and hold times around the rising edge of k# for write cycles. see ball layout figures for address expansion inputs. all transactions operate on a burst of two words (one clock period of bus activity). these inputs are ignored when both ports are deselected. tck input ieee 1149.1 clock input: 1.8v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. tms tdi input ieee 1149.1 test inputs: 1.8v i/o levels. these balls may be left as no connects if the jtag function is not used in the circuit. v ref input hstl input reference voltage: nominally v dd q/2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffer trip point. w# input synchronous write: when low, this input causes the address inputs to be registered and a write cycle to be initiated. this input must meet setup and hold times around the rising edge of k. zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. dq output impedanc e is set to 0.2 x rq, where rq is a resistor from this ball to ground. alternately, this ball can be connected directly to v dd q to enable the minimum impedance mode. this ball cannot be connected directly to gnd or left unconnected. cq#, cq output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as data valid indication. these signals run freely and do not stop when q tri-states. q_ output synchronous data outputs: output data is sync hronized to the respective c and c# or to k and k# rising edges if c and c# are tied high. this bus operates in response to r# commands. see ball layout figures for ball site location of individual signals. the x8 device uses q0:q7. remaining signals are nc. the x18 device uses q0:q17. remaining signals are nc. the x36 device uses q0:q35. remaining signals are nc.
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 10 ?2003 micron technology, inc. tdo output ieee 1149.1 test output: 1.8v i/0 level. v dd supply power supply: 1.8v nominal. see dc electrical characteristics and operating conditions for range. v dd q supply power supply: isolated output buffer supply. nominally, 1.5v. 1.8v is also permissible. see dc electrical characteristics and operating conditions for range. v ss supply power supply: gnd. nc ? no connect: these balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. table 5: ball descriptions (continued) symbol type description
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 11 ?2003 micron technology, inc. figure 4: bus cycle state diagram note : 1. the address is concatenated with one additional internal lsb to facilitate burst operation. the address order is always fixed as: xxx...xxx+0, xxx...xxx+1. bus cycle is term inated at the end of this sequence (burst count = 2). 2. state transitions: rd = (r# = low); wt = (w# = low). 3. read and write state machines can be simultaneously active. 4. state machine, control timing sequence is controlled by k. load new read address read double power-up supply voltage provided read port nop r_init=0 rd rd always /rd /rd load new write address at k# write double at k# supply voltage provided write port nop wt wt always /wt /wt
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 12 ?2003 micron technology, inc. . note : 1. x means ?don?t care.? h means logic high. l means logic low. means rising edge; means falling edge. 2. data inputs are registered at k and k# rising edges. data outputs are delivered at c and c# rising edges, except if c and c# are high, then data outputs are delivered at k and k# rising edges. 3. r# and w# must meet setup and hold times around the rising edge (low to high) of k and are registered at the ris- ing edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. it is recommended that k = k# = c = c# when clock is st opped. this is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 7. assumes a write cycle was initiated. bw0# and bw1# can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. 8. this table illustrates operation for x18 devices. the x36 devi ce operation is similar, except for the addition of bw2# (controls d18:d26) and bw3# (controls d27:d35). the x8 operat ion is similar, except that nw0# controls d0:d3, and nw1# controls d4:d7. table 6: truth table notes 1?6 operation k r# w# d or q d or q write cycle: load address, input write data on consecutive k and k# rising edges l hx l d a (a0) at k(t) d a (a0 + 1) at k#(t + 1 ) read cycle: load address, output data on consecutive c and c# rising edges l hl x q a (a0) at c#(t) q a (a0 + 1) at c(t + 1) nop: no operation l h h h d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state table 7: byte write operation notes 7, 8 operation k k# bw0# bw1# write d0:17 at k rising edge l h00 write d0:17 at k# rising edge l h0 0 write d0:8 at k rising edge l h01 write d0:8 at k# rising edge l h0 1 write d9:17 at k rising edge l h10 write d9:17 at k# rising edge l h1 0 write nothing at k rising edge l h11 write nothing at k# rising edge l h1 1
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 13 ?2003 micron technology, inc. absolute maximum ratings voltage on v dd supply relative to v ss ..... -0.5v to +2.8v voltage on v dd q supply relative to v ss ....................................... -0.5v to +v dd v in ..................................................... -0.5v to v dd + 0.5v storage temperature ..............................-55oc to +125oc junction temperature .......................................... +125oc short circuit output current .............................. 70ma stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. maximum junction temperature depends upon package type, cycle time, loading, ambient tempera- ture, and airflow. table 8: dc electrical characteristics and operating conditions notes appear following parameter tables on page 16; 0c t a +70c; v dd = 1.8v 0.1v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih ( dc )v ref + 0.1 v dd q + 0.3 v 3, 4 input low (logic 0) voltage v il ( dc ) -0.3 v ref - 0.1 v 3, 4 clock input signal voltage v in -0.3 v dd q + 0.3 v 3, 4 input leakage current 0v v in v dd qil i -5 5 a output leakage current output(s) disabled, 0v v in v dd q (q) il o -5 5 a output high voltage | i oh | 0.1ma v oh ( low )v dd q - 0.2 v dd q v 3, 5, 6 note 1 v oh v dd q/2 - 0.12 v dd q/2 + 0.12 v 3, 5, 6 output low voltage i ol 0.1ma v ol ( low )v ss 0.2 v 3, 5, 6 note 2 v ol v dd q/2 - 0.12 v dd q/2 + 0.12 v 3, 5, 6 supply voltage v dd 1.7 1.9 v 3 isolated output buffer supply v dd q1.4 v dd v3, 7 reference voltage v ref 0.68 0.95 v 3 table 9: ac electrical characteristics and operating conditions notes appear following parameter tables on page 16; 0c t a +70c; v dd = 1.8v 0.1v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.2 ? v 3, 4, 8 input low (logic 0) voltage v il ( ac )?v ref - 0.2 v 3, 4, 8
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 14 ?2003 micron technology, inc. . table 11: capacitance note 13; notes appear following parameter tables on page 16 table 12: thermal resistance note 13; notes appear following parameter tables on page 16 ta bl e 1 0 : i dd operating conditions and maximum limits notes appear following parameter tables on page 16; 0c t a +70c; v dd = 1.8v 0.1v unless otherwise noted max description conditions sym typ -4 -5 -6 -7.5 units notes operating supply current: ddr all inputs v il or v ih ; cycle time t khkh (min ); outputs open; 100% bus utilization; 50% address and data bits toggling on each clock cycle i dd x8, x18 x36 tbd 600 800 330 445 280 380 235 310 ma 9, 10 standby supply current: nop t khkh = t khkh (min); device in nop state; all addresses/data static i sb1 x8, x18 x36 tbd 200 210 170 180 150 160 125 135 ma 10, 11 output supply current: ddr (information only) c l = 15pf i dd q x8 x18 x36 tbd 32 71 142 25 57 113 21 47 95 17 38 76 ma 12 description conditions symbol typ max units address/control input capacitance t a = 25oc; f = 1 mhz c i 4.5 5.5 pf output capacitance (q) c o 67pf clock capacitance c ck 5.5 6.5 pf description conditions symbol typ units notes junction to ambient (airflow of 1m/s) soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ja 19.4 oc/w 14 junction to case (top) jc 1.0 oc/w junction to balls (bottom) jb 9.6 oc/w 15
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 15 ?2003 micron technology, inc. table 13: ac electrical characteristics and recommended operating conditions notes 16?19, 22, notes appear following paramater tables on page 16; 0c t a +70c; t j +95c; v dd = 1.8v 0.1v description symbol -4 -5 -6 -7.5 units notes min max min max min max min max clock clock cycle time (k, k#, c, c#) t khkh 4.00 5.25 5.00 6.30 6.00 7.88 7.50 8.40 ns 20 clock phase jitter (k, k#, c, c#) t kc var 0.20 0.20 0.20 0.20 ns 21 clock high time (k, k#, c, c#) t khkl 1.60 2.00 2.40 3.00 ns clock low time (k, k#, c, c#) t klkh 1.60 2.00 2.40 3.00 ns clock to clock# (k k# , c c# ) at t khkh minimum t khk#h 1.80 2.20 2.70 3.38 ns clock# to clock (k# k, c# c) at t khkh minimum t k#hkh 1.80 2.20 2.70 3.38 ns clock to data clock (k c , k# c# ) t khch 0.00 1.80 0.00 2.30 0.00 2.80 0.00 3.55 ns dll lock time (k, c) t kc lock 1,024 1,024 1,024 1,024 cycles 22 k static to dll reset t kc reset 30 30 30 30 ns output times c, c# high to output valid t chqv 0.45 0.45 0.50 0.50 ns c, c# high to output hold t chqx -0.45 -0.45 -0.50 -0.50 ns c, c# high to echo clock valid t chcqv 0.45 0.45 0.50 0.50 ns c, c# high to echo clock hold t chcqx -0.45 -0.45 -0.50 -0.50 ns cq, cq# high to output valid t cqhqv 0.30 0.35 0.40 0.40 ns 23 cq, cq# high to output hold t cqhqx -0.30 -0.35 -0.40 -0.40 ns 23 c high to output high-z t chqz 0.45 0.45 0.50 0.50 ns c high to output low-z t chqx1 -0.45 -0.45 -0.50 -0.50 ns setup times address valid to k rising edge t avkh 0.35 0.40 0.50 0.50 ns 16 control inputs valid to k rising edge t ivkh 0.35 0.40 0.50 0.50 ns 16 data-in valid to k, k# rising edge t dvkh 0.35 0.40 0.50 0.50 ns 16 hold times k rising edge to address hold t khax 0.35 0.40 0.50 0.50 ns 16 k rising edge to control inputs hold t khix 0.35 0.40 0.50 0.50 ns 16 k, k# rising edge to data-in hold t khdx 0.35 0.40 0.50 0.50 ns 16
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 16 ?2003 micron technology, inc. notes 1. outputs are impedance-controlled. |i oh | = (v dd q/2)/(rq/5) for values of 175 rq 350 . 2. outputs are impedance-controlled. i ol = (v dd q/ 2)/(rq/5) for values of 175 rq 350 . 3. all voltages referenced to v ss (gnd). 4. overshoot: v ih ( ac ) v dd + 0.7v for t t khkh/2 undershoot: v il ( ac ) -0.5v for t t khkh/2 power-up: v ih v dd q + 0.3v and v dd 1.7v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . r# and w# signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 5. ac load current is higher than the shown dc val- ues. ac i/o curves are available upon request. 6. hstl outputs meet jedec hstl class i and class ii standards. 7. the nominal value of v dd q may be set within the range of 1.5v to 1.8v dc, and the variation of v dd q must be limited to 0.1v dc. 8. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through the target ac level, v il ( ac ) or v ih ( ac ). b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ). 9. i dd is specified with no output current. i dd is lin- ear with frequency. typical value is measured at 6ns cycle time. 10. typical values are measured at v dd = 1.8v, v dd q = 1.5v, and temperature = 25c. 11. nop currents are valid when entering nop after all pending read and write cycles are com- pleted. 12. average i/o current and power is provided for informational purposes only and is not tested. calculation assumes that all outputs are loaded with c l (in farads), f = input clock frequency, half of outputs toggle at each transition (n = 18 for the x36), c o = 6pf, v dd q = 1.5v and uses the equa- tions: average i/o power as dissipated by the sram is: p = 0.5 n f v dd q 2 x (c l + 2c o ). average iddq = n f v dd q x (c l + c o ). 13. this parameter is sampled. 14. average thermal resistance between the die and the case top surface per mil spec 883 method 1012.1. 15. junction temperature is a function of total device power dissipation and device mounting environ- ment. measured per semi g38-87. 16. this is a synchronous device. all addresses, data, and control lines must meet the specified setup and hold times for all latching clock edges. 17. test conditions as specified with the output load- ing as shown in figure 5 unless otherwise noted. 18. control input signals may not be operated with pulse widths less than t khkl (min). 19. if c and c# are tied high, then k and k# become the references for c and c# timing parameters. 20. the device will operate at clock frequencies slower than t khkh (max). see micron technical note tn-54-02 for more information. 21. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 22. v dd slew rate must be less than 0.1v dc per 50ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 23. echo clock is tightly controlled to data valid/data hold. by design, there is a 0.1ns variation from echo clock to data. the data sheet parameters reflect tester guardbands and test setup varia- tions.
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 17 ?2003 micron technology, inc. ac test conditions input pulse levels . . . . . . . . . . . . . . . . . . 0.25v to 1.25v input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns input timing reference levels . . . . . . . . . . . . . . . . 0.75v output reference levels . . . . . . . . . . . . . . . . . . .v dd q/2 zq for 50 impedance . . . . . . . . . . . . . . . . . . . . . 250 output load . . . . . . . . . . . . . . . . . . . . . . . . . see figure 5 figure 5: output load equivalent 50 ? v dd q/2 250 ? z = 50 ? o zq sram 0.75v v ref
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 18 ?2003 micron technology, inc. figure 6: read/write timing note : 1. q00 refers to output from address a0 + 1. q01 refers to output from the next internal burst address following a0, i.e., a0 + 1. 2. outputs are disabled (high-z) one clock cycle after a nop. 3. in this example, if address a0 = a1, then data q00 = d10 and q01 = d11. write data is forwarded immediately as read results. (this note applies to whole diagram.) k 12345 8 10 6 7 k# r# w# a q d c c# a0 read read write write write t khkl t khk#h t khch t chqv t klkh t khkh tt khix t avkh t khax t dvkh t khdx t khch nop don?t care undefined t chqx1 t chqz ivkh t khkl t klkh t t avkh t khax d30 d50 d51 d61 t dvkh t khdx read write (note 2) nop q00 q01 q20 t chqv t chqx t khk#h t khkh 9 a6 a5 a3 a4 a1 a2 q21 q40 q41 d31 d11 d10 d60 t cqhqv t chqx cq cq# t chcqv t chcqx t chcqv t chcqx (note 1) (note 3)
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 19 ?2003 micron technology, inc. ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully-compliant taps. the tap operates using jedec-standard 1.8v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. alternately, they may be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the opera- tion of the device. figure 7: tap controller state diagram note : the 0/1 next to each state represents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 7. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signifi- cant bit (msb) of any register, as illustrated in figure 8. test data-out (tdo) the tdo output ball is used to serially clock data- out from the registers. the output is active depending upon the current state of the tap state machine, as shown in figure 7. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register, as depicted in figure 8. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is seri- ally loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 20 ?2003 micron technology, inc. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls, as shown in figure 8. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two lsbs are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through reg- isters, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with mini- mal delay. the bypass register is set low (vss) when the bypass instruction is executed. figure 8: tap controller block diagram note : x = 106. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the sram has a 107-bit-long register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the balls on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction regis- ter. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift- dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully imple- mented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the i/o ring when these instructions are executed. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this sram tap controller; therefore, this device is not 1149.1-compliant. the tap controller does recognize an all-0 instruc- tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. extest does not place the sram outputs (including cq and cq#) in a high-z state. bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 21 ?2003 micron technology, inc. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc- tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. note that since the preload part of the command is not implemented, putting the tap into the update- dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruc- tion is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 22 ?2003 micron technology, inc. figure 9: tap timing note : timing for sram inputs and outputs is congruent with tdi and tdo, respectively, as shown in figure 9. note : 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 10. t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don?t care undefined table 14: tap dc electrical characteristics notes 1, 2; 0c t a +70c; v dd 1.8v 0.1v description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 23 ?2003 micron technology, inc. tap ac test conditions input pulse levels . . . . . . . . . . . . . . . . . . . . . v ss to 1.8v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . 1ns input timing reference levels . . . . . . . . . . . . . . . . . 0.9v output reference levels . . . . . . . . . . . . . . . . . . . . . . 0.9v test load termination supply voltage . . . . . . . . . . 0.9v figure 10: tap ac output load equivalent note : 1. all voltages referenced to v ss (gnd). 2. this table defines dc values for tap control and data balls only. the dq sram balls used in jtag operation will have the dc values as defined in table 8, ?dc electrical characteristics and operating conditions,? on page 13. tdo 0.9v 20pf z = 50 ? o 50 ? table 15: tap dc electrical characteristics and operating conditions note 2; 0c t a +70c; v dd 1.8v 0.1v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih 1.3 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.5 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a 2 output leakage current output(s) disabled, 0v v in v dd (dqx) il o -5.0 5.0 a 2 output low voltage i olc = 100a v ol 1 0.2 v 1, 2 output low voltage i olt = 2ma v ol 2 0.4 v 1, 2 output high voltage i ohc = -100a v oh 1 1.6 v 1, 2 output high voltage i oht = -2ma v oh 1 1.4 v 1, 2
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 24 ?2003 micron technology, inc. table 16: identification register definitions instruction field all devices description revision number (31:28) 000 revision number. device id (28:12) 00def0wx0t0q0b0s0 def = 010 for 36mb density def = 001 for 18mb density wx = 11 for x36 width wx = 10 for x18 width wx = 01 for x8 width t = 1 for dll version t = 0 for non-dll version q = 1 for qdr q = 0 for ddr b = 1 for 4-word burst b = 0 for 2-word burst s = 1 for separate i/o s = 0 for common i/o micron jedec id code (11:1) 00000101100 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. table 17: scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 table 18: instruction codes instruction code description extest 000 captures i/o ring contents. places the bounda ry scan register between tdi and tdo. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/ preload 100 captures i/o ring contents. places the bounda ry scan register between tdi and tdo. this instruction does not implement 1149.1 preload function and is therefore not 1149.1- compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 25 ?2003 micron technology, inc. table 19: boundary scan (exit) order bit# fbga ball bit# fbga ball bit# fbga ball 1 6r 37 10d 73 2c 26p389e743e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 57n 419c 771e 67r 429d 782f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 99r459b811f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1j 13 9p 49 9a 85 2j 14 10m 50 8b 86 3k 15 11n 51 7c 87 3j 16 9m 52 6c 88 2k 17 9n 53 8a 89 1k 18 11l 54 7a 90 2l 19 11m 55 7b 91 3l 20 9l 56 6b 92 1m 21 10l 57 6a 93 1l 22 11k 58 5b 94 3n 23 10k 59 5a 95 3m 24 9j 60 4a 96 1n 25 9k 61 5c 97 2m 26 10j 62 4b 98 3p 2711j 633a 992n 28 11h 64 2a 100 2p 29 10g 65 1a 101 1p 30 9g 66 2b 102 3r 31 11f 67 3b 103 4r 32 11g 68 1c 104 4p 33 9f 69 1b 105 5p 34 10f 70 3d 106 5n 35 11e 71 3c 107 5r 36 10e 72 1d
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of of micron technology, inc. 2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 26 ?2003 micron technology, inc. figure 11: 165-ball fbga note : all dimensions are in millimeters. data sheet designation no marking: this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are sub- ject to change, as further product development and data characterization sometimes occur. 10.00 14.00 15.00 0.10 1.00 typ 1.00 typ 5.00 0.05 13.00 0.10 pin a1 id pin a1 id ball a1 mold compound: epoxy novolac substrate: plastic laminate 6.50 0.05 7.00 0.05 7.50 0.05 1.20 max solder ball material: eutectic 63% sn, 37% pb solder ball pad: ? .33mm solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40 seating plane 0.85 0.075 0.12 c c 165x ? 0.45 ball a11
2 meg x 8, 1 meg x 18, 512k x 36 1.8v v dd , hstl, qdriib2 sram 18mb: 1.8v v dd , hstl, qdriib2 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54w1mh18b_h.fm ? rev. h, pub. 3/03 27 ?2003 micron technology, inc. document revision history rev. h, pub 3/03 ............................................................................................................... ...............................................3/03 updated jtag section removed preliminary status rev. g, pub 2/03............................................................................................................... ................................................2/03 added definitive notes to figure 3 added definitive note to table 9 added definitive note concerning bit# 64 to table 19 removed errata specifications updated ac timing values with new codevelopment values updated jtag description to reflect 1149.1 specification compliance with extest feature added definitive note concerning sram (dq) i/o balls used for jtag dc values and timing changed process information in header to die revision indicator updated thermal resistance values to table 12: c i = 4.5 typ; 5.5 max c o = 6 typ; 7 max c ck = 5.5 typ; 6.5 max updated thermal resistance values to table 12: j a = 19.4 typ j c = 1.0 typ j b = 9.6 typ added t j +95c to table 13 modified figure 2 regarding depth, configuration, and byte controls added definitive notes regarding i/o behavior during jtag operation added definitive notes regarding i dd test conditions for read to write ratio removed note regarding ac derating information for full i/o range remove references to jtag scan chain logic levels being at logic zero for nc pins in tables 5 and 19 revised ball description for nc balls: these balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. rev. 6, pub 9/02 ............................................................................................................... ................................................9/02 reverted data sheet to preliminary designation rev. 5, pub. 9/02, advance ..................................................................................................... ......................................9/02 added new output times values added errata to back of data sheet removed advance designation removed t j references rev. 4, pub. 8/02, advance ..................................................................................................... ......................................8/02 updated format rev. 3, pub. 12/01, advance .................................................................................................... ...................................12/01 changed ac timing rev. 2, pub. 11/01, advance .................................................................................................... ...................................11/01 new advance data sheet

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