? 2006 california micro devices corp. all rights reserved. 4/18/2006 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 1 cm20lt-c preliminary hdmi source/sink port protection and interface device features ? long hdmi cable support with integrated i 2 c accelerator ? low capacitance ddc for hdmi compliance ? improved cec signal quality and compatibility ? translates i 2 c level to cmos level on ddc line ? overcurrent output protection for source ? 5v diode bridge for eeprom for sink ? level shifting isolation circuitry, including 8 kv esd protection on all external i/o lines ? backdrive protection and isolation <5 m a on all pins applications ? pc and consumer electronics ? set top box, dvdrw players ? consumer electronics ? displays and digital television product description the cm20lt-c hdmi port protection and interface device is designed for next generation hdmi source and sink interface protection. an integrated package provides complete low capaci- tance esd, level shifting/isolation, slew rate limiting and terminations, overcurrent output protection, eeprom and backdrive protection to ensure hdmi compliance in a single 10-pin msop package. the cm20lt-c part is specifically designed to provide the designer with the most reliable path to hdmi 1.3 cts compliance. electrical schematic ddc_clk_out ddc_clk_in vin_1 vout 55ma overcurrent switch vin_2 vin_1 ddc_dat_out ddc_dat_in vin_1 vin_1 dynamic pullup dynamic pullup cmos/i2c level shift cmos/i2c level shift vin_1 cec_out cec_in vin_2 slew rate ctrl & termination backdrive control
? 2006 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 4/18/2006 cm20lt-c preliminary note 1: these 2 pins need to be connected together in-line on the pcb. see recommended layout diagram. note 2: this output can be connected to an external 0.1 m f ceramic capacitor/pads to mainatain backward compatibility with the cm2020. note 3: standard iec 61000-4-2, c discharge =150pf, r discharge =330 w , vin_2 and vin_1 within recommended operating con- ditions, gnd=0v, 5v_out (pin 38), and hotplug_det_out (pin 20) each bypassed with a 0.1 m f ceramic capacitor connected to gnd. note 4: human body model per mil-std-883, method 3015, c discharge =100pf, r discharge =1.5k w , vin_2and vin_1 within recommended operating conditions, gnd=0v, 5v_out (pin 38), and hotplug_det_out (pin 20) each bypassed with a 0.1 m f ceramic capacitor connected to gnd. note 5: these pins should be routed directly to the associated gnd pins on the hdmi connector with single point ground vias at the connector pin descriptions pins name esd level description 2 vin_1 2kv 4 system side voltage supply. this pin provides power to vout when vin_2 is "off". vin_1 also enables/disables backdrive isolation pro- tection on the ddc lines when vin_1 is "off." 5 vin_2 8kv 3 cable side voltage supply. this pin provides power to vout when vin_1 is "off". vin_2 also provides supply current for the cec slew- rate limiting and termination logic. 1 cec_in 2kv 4 bi-directional system side cec input from up. 10 cec_out 8kv 3 bi-directional cable side cec output (vin_2=3.3v referenced logic level ) plus 3.5pf esd. includes long cable accelerator/driver. con- nect to hdmi pin 13. 3 ddc_clk_in 2kv 4 bi-directional system side (vin_1 referenced logic level). includes cmos low-level shifter for guaranteed local v ol . 9 ddc_clk_out 8kv 3 bi-directional cable side (vin_2 referenced logic level ) plus 3.5pf esd. includes long cable accelerator/driver. connect to hdmi pin 15. 4 ddc_dat_in 2kv 4 bi-directional system side (vin_1 referenced logic level). includes cmos low-level shifter for guaranteed local v ol . 8 ddc_dat_out 8kv 3 bi-directional cable side (vin_2 referenced logic level ) plus 3.5pf esd. includes long cable accelerator/driver. connect to hdmi pin 16. 6 vout 8kv 3 55ma minimum overcurrent protected 5v output.this output must be bypassed with a 0.1 m f ceramic capacitor. for source, connect this to hdmi pin. for sink, use this to replace a diode bridge for local and external power to the e-edid eeprom. 7 gnd n/a gnd reference. package / pinout diagram note: this drawing is not to scale. 1 2 3 4 7 8 9 10 vin_1 vin_2 ddc_dat_out gnd vout ddc_clk_out top view ddc_clk_in ddc_dat_in 10-pin msop package 5 6 cec_in cec_out
? 2005, 2006california micro devices corp. all rights reserved. 4/3/2006 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 3 cm20lt-c preliminary backdrive protection and isolation backdrive current is defined as the undesirable current flow through an i/o pin when that i/o pin?s voltage exceeds the related local supply voltage for that cir- cuitry. this is a potentially common occurrence in mul- timedia entertainment systems with multiple components and several power plane domains in each system. for example, if a dvd player is switched off and an hdmi connected tv is powered on, there is a possibil- ity of reverse current flow back into the main power supply rail of the dvd player from pull-ups in the tv. as little as a few milliamps of backdrive current flowing back into the power rail can charge the dvd player?s bulk bypass capacitance on the power rail to some intermediate level. if this level rises above the power- on-reset (por) voltage level of some of the integrated circuits in the dvd player, then these devices may not reset properly when the dvd player is turned back on. if any soc devices are incorporated in the design which have built-in level shifter and/or esd protection structures, there can be a risk of permanent damage due to backdrive. in this case, backdrive current can forward bias the on-chip esd protection structure. if the current flow is high enough, even as little as a few milliamps, it could destroy one of the soc chip's inter- nal drc diodes, as they are not designed for passing dc. to avoid either of these situations, the cm20lt-c was designed to block backdrive current, guaranteeing less than 5 m a into any i/o pin when the i/o pin voltage exceeds its related operating cm20lt-c supply volt- age. figure 1. backdrive protection diagram. display data channel (ddc) lines the ddc interface is based on the i 2 c serial bus proto- col for edid configuration. dynamic pullups based on the hdmi specification, the maximum capac- itance of the ddc line can approach 800pf (50pf from source, 50pf from sink, and 700pf from cable). at the upper range of capacitance values (i.e. long cables), it becomes impossible for the ddc lines to meet the i 2 c timing specifications with the minimum pull-up resistor of 1.5k w . for this reason, the cm20lt-c was designed with an internal i 2 c accelerator to meet the ac timing specifi- cation even with very long and non-compliant cables. the internal accelerator increases the positive slew rate of the ddc_clk_out and ddc_dat_out lines whenever the sensed voltage level exceeds 0.3*vin_2 (approximately 1.5v). this provides faster overall rise- time in heavily loaded situations without overloading the mutli-drop open drain i 2 c outputs elsewhere. low voltage hdmi asic lv_supply =off +5v asic hdmi source hdmi sink
? 2006 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 4/18/2006 cm20lt-c preliminary dynamic pullups (cont?d) figure 2. dynamic ddc pullups (discrete - left. cm20lt-c - right.) figure 2 demonstrates the "worst case" operation of the dynamic cm20lt-c ddc level shifting circuitry (right) against a discrete nfet common-gate level shifter circuit with a typical 1.5k pullup (left.) both are shown driving an off-spec, but unfortunately readily available 31m hdmi cable which exceeds the 700pf hdmi specification. when the standard i/od cell releases the nfet dis- crete shifter, the risetime is limited by the pullup and the parasitics of the cable, source and sink. for long cables, this can extend the risetime and reduce the margin for reading a valid "high" level on the data line. in this case, an hdmi source may not be able to read uncorrupted data and will not be able to initiate a link. with the cm20lt-c?s dynamic pullups, when the asic driver releases its ddc line and the "out" line reaches at least 0.3*vdd (of vin_2), then the "out" active pullups are enabled and the cm20lt-c takes over driving the cable until the "out" voltage approaches the vin_2 rail. the internal pass element and the dynamic pullups also work together to damp reflections on the longer cables and keep them from glitching the local asic. i 2 c/cmos level shifting using a standard cmos input buffer for the ddc inter- face on the local hdmi asic can create a failure to communicate at the specified i 2 c levels. with an i 2 c vil of approximately 1.5v (0.3*vdd), and typical cmos/ttl vil input levels of 0.8v or less, an incom- patibility can arise where valid hdmi specified logic lows on the cable are not recognized within the asic. the cm20lt-c incorporates automatic cmos/i 2 c logic low translation on the ddc_clk_in and ddc_dat_in lines. as highlighted in figure 2 above, when the cable-side level ("out" side) of each ddc line is below 0.3*vdd, the asic-side ("in" side) of the ddc line is forced to a cmos low-level while the "out" side is allowed to slew normally. the cm20lt-c dynamic pullups, low level shifters, and pass element shifters are all matched to allow transparent operation. this bi-directional circuit can be used as easily as any discrete common-gate nfet level shifter, but with the added functionality. multiport ddc multiplexing additionally, by switching vin_1, the ddc/hpd blocks can be independently disabled by engaging their inher- ent "backdrive" protection. this allows n:1 multiplexing of the low-speed hdmi signals without any additional fet switches.
? 2005, 2006california micro devices corp. all rights reserved. 4/3/2006 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 5 cm20lt-c preliminary consumer electronics control (cec) the consumer electronics control (cec) line is a high level command and control protocol, based on a single wire multidrop open drain communication bus running at approximately 1khz (see figure 3). while the hdmi link provides only a single point-to-point connection, up to ten (10) cec devices may reside on the bus, and they may be daisy chained out through other physical connectors including other hdmi ports or other dedi- cated cec links. the high level protocol of cec can be implemented in a simple microcontroller or other inter- face with any i/od (input/open-drain) gpio. figure 3. typical m c i/od driver to limit possible emi and ringing in this potentially complex connection topology, the rise- and fall-time of this line are limited by the specification. however, meeting the slew-rate limiting requirements with addi- tional discrete circuitry in this bi-directional block is not trivial without an additional rx/tx control line to limit the output slew-rate without affecting the input sensing (see figure 4). figure 4. three-pin external buffer control simple cmos buffers cannot be used in this applica- tion since the load can vary so much (total pullup of 27k w to less than 2k w , and up to 7.3nf total capaci- tance. ) the cm20lt-c targets an output drive slew- rate of less than 100mv/ m s regardless of static load for the cec line. additionally, the same internal circuitry will perform active termination, thus reducing ringing and overshoot in entertainment systems connected to legacy or poorly designed cec nodes. the cm20lt-c?s bi-directional slew rate limiting is integrated into the cec level-shifter functionality thus allowing the designer to directly interface a simple low voltage cmos gpio directly to the cec bus and simultaneously guarantee meeting all cec output logic levels and hdmi slew-rate and isolation specifications (see figure 5). figure 5. integrated cm20lt-c solution the cm20lt-c also includes an internal backdrive protected static pullup 120 m a current source from the ce_supply rail in addition to the dynamic slew rate control circuitry. figure 6 shows a typical shaped cm20lt-c cec out- put. figure 6. cm20lt-c cec output rx tx i/od gpio cec rx tx tx_en cec slew rate limited 3-state buffer x cec cm20lt-c cec i/f m p
? 2006 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 4/18/2006 cm20lt-c preliminary ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. specifications part numbering information pins package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 10 msop-10 CM20LT-C-00TS CM20LT-C-00TS cm20lt-c-00tr cm20lt-c-00tr absolute maximum ratings parameter rating units v cc2 , v cc1 6.0 v dc voltage at any channel input [gnd - 0.5] to [vcc + 0.5] v storage temperature range -65 to +150 c standard (recommended) operating conditions symbol parameter min typ max units vin_2 operating supply voltage 5 5.5 v vin_1 bias supply voltage 1 3.3 5.5 v operating temperature range -40 85 c
? 2005, 2006california micro devices corp. all rights reserved. 4/3/2006 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 7 cm20lt-c preliminary specifications (cont?d) note 1: operating characteristics are over standard operating conditions unless otherwise specified. note 2: this parameter is guaranteed by design and verified by device characterization. note 3: standard iec61000-4-2, c discharge =150pf, r discharge =330 w , vin_2=5v, 3.3v_supply=3.3v, vin_1=3.3v, gnd=0v. note 4: human body model per mil-std-883, method 3015, c discharge =100pf, r discharge =1.5k w, vin_2=5v, 3.3v_supply=3.3v, vin_1=3.3v, gnd=0v. note 5: intra-pair matching, each tmds pair (i.e. d+, d-) note 6: these measurements performed with no external capacitor on v p (v p floating) electrical operating characteristics (see note 1) symbol parameter conditions min typ max units i cc2 operating supply current vin_2= 5.0v, vin_1= 3.3v, ddc=5v 250 m a i cc1 bias supply current vin_1 = 3.3v 10 m a v drop 5v_out overcurrent output drop vin_@= 5.0v, i out =55ma 65 100 mv i sc 5v_out short circuit current limit vin_2= 5.0v, vout = gnd 90 135 175 ma i off off state leakage current, level shifting nfet vin_1 = 0v 0.1 5 m a i backdrive current conducted from output pins to v_supply rails when powered down vin_2 < v ch_out ; signal pins: tmds_[2:0]+/-, tmds_ck+/-, ce_remote_out, ddc_dat_out, ddc_clk_out, hotplug_det_out, 5v_out only 0.1 m a v acc turn on of i 2 c accelerator voltage is 0.3*vin2 1.5 v v f diode forward voltage top diode bottom diode i f = 8ma, t a = 25c, note 2 0.6 0.6 0.85 0.85 0.95 0.95 v v v esd esd withstand voltage (iec) pins 4, 7, 10, 13, 20, 21, 22, 23, 24, 27, 30, 33; notes 2 and 3 8 kv v esd esd withstand voltage (hbm) pins 1, 2, 16, 17, 18, 19, 37, 38; notes 2 and 4 2 kv v cl channel clamp voltage @ 8kv hbm esd positive transients negative transients t a =25c, i pp = 1a, t p = 8/20us; notes 2, & 6 9.0 -9.0 v v r dyn dynamic resistance positive transients negative transients t a =25c, i pp = 1a, t p = 8/20us any i/o pin to ground; note 6 1.4 0.9 w w i leak channel leakage current t a = 25c, note 2 0.01 1 m a c in, ddc level shifting input capaci- tance, capacitance to gnd vin_2= 0v, measured at 100khz, v bias =2.5v, note 2 3.5 pf
? 2006 california micro devices corp. all rights reserved. 8 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 4/18/2006 cm20lt-c preliminary application information (source) figure 7. typical source application for cm20lt-c layout notes 1 differential tmds pairs should be designed as normal 100w hdmi microstrip, with cmd picoguard cm1213-04ms/mresd protection or equivalent. 2 level shifter signals should be biased with a weak pullup to the desired local vin_1. if the local asic includes sufficient pullups to register a logic high, then external pullups may not be needed. tmds_d2+ tmds_gnd tmds_d2- tmds_d1+ tmds_gnd tmds_d1- tmds_d0+ tmds_gnd tmds_d0- tmds_ck+ tmds_gnd tmds_ck- ce_remote n/c ddc_clk ddc_dat gnd +5v hotplug_det hdmi source cm20lt-c 2 3 4 5 9 8 7 6 tmds_d2+ tmds_d2- tmds_d1+ tmds_d1- tmds_d0+ tmds_d0- tmds_ck+ tmds_ck- d d c _ d a t asic_scl 2 asic_sda 2 c hp 100nf r pd1 5k w c vout 100nf note 1 { r dat 2k w r scl 2k w d d c _ c l k asic_supply/ vin_2 10k w h o t p l u g _ d e t enable connector r pd2 1 10 cec_gpio 2
? 2005, 2006california micro devices corp. all rights reserved. 4/3/2006 430 n. mccarthy blvd., milpitas, ca 95035-5112 - tel: 408.263.3214 - fax: 408.263.7846 - www.calmicro.com 9 cm20lt-c preliminary application information (sink) figure 8. typical sink application for cm20lt-c layout notes 1 differential tmds pairs should be designed as normal 100w hdmi microstrip, with cmd picoguard cm1213-04ms/mresd protection or equivalent. 2 level shifter signals should be biased with a weak pullup to the desired local vin_1. if the local asic includes sufficient pullups to register a logic high, then external pullups may not be needed. tmds_d2+ tmds_gnd tmds_d2- tmds_d1+ tmds_gnd tmds_d1- tmds_d0+ tmds_gnd tmds_d0- tmds_ck+ tmds_gnd tmds_ck- ce_remote n/c ddc_clk ddc_dat gnd +5v hotplug_det hdmi sink 2 3 4 5 9 8 7 6 tmds_d2+ tmds_d2- tmds_d1+ tmds_d1- tmds_d0+ tmds_d0- tmds_ck+ tmds_ck- e e p r o m _ d a t asic_scl 2 asic_sda 2 c hp 100nf r pu 1k w c vout 100nf note 1 { r dat n/a r scl 47k e e p r o m _ c l k asic_supply/ 5v_hdmi h o t p l u g _ d e t enable connector e e p r o m _ s u p p l y 1 10 cec_gpio 2 cm20lt-c
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