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524,288 bit flash eeprom features ? 4 megabit flash memory. fast access times of 55/70/90/120 ns. operating power 248 mw (max), low power standby (cmos) 633w (max). automatic write/erase by embedded algorithm - end of write/erase indicated by data polling and toggle bit. flexible sector erase architecture - 64k byte sector size, with hardware protection of any number of sectors. byte program of 16s (typ), sector program of 2s (typ) erase/write cycle endurance, standard 10,000 (min) extended 100,000 (min) ? 10 year data retention. may be screened in accordance with mil-std-883. pin definitions 512k x 8 flash mfm8516 - 55/70/90/12 issue 5.0 : april 2001 description the mfm8516 is a 4m bit cmos 5v only flash monolithic device organised : 512k x 8. the device offers fast access times of 55/70/90 and 120ns and 5v program/erase. the device has a 64 kbyte sector size. the program and erase procedure is simplified via automatic program and erase algorithms. the mfm8516 has a 10k cycle write erase cycle endurance (100k cycle e-part) and a 10 year data retention time. we erase volta g e generator input/output buffers state control command re g ister pgm volta g e generator chip enable output enable lo g ic data latch y-gatin g y-decoder a d d r l a t c h x-decoder cell matrix vcc detector timer vcc vss ce oe a0-a18 dq0-dq7 stb package details pin count description package type 32 dual in-line s 32 jlcc (j leaded chip carrier) j pin functions a0-a18 address inputs d0-d7 data inputs/outputs cs chip enable we write enable oe output enable vcc power (+5v) gnd ground block diagram s,v package top view 31 we 30 a17 29 a14 28 a13 27 a8 26 a9 25 a11 24 oe 23 a10 22 cs 21 d7 20 d6 19 d5 32 v cc a18 1 a16 2 a15 3 a12 4 a7 5 a6 6 a5 7 a4 8 a3 9 a2 10 a1 11 a0 12 d0 13 d1 14 d2 15 gnd 16 18 d4 17 d3 31 we 32 vcc 15 d2 16 gnd 4 a12 1 a18 2 a16 3 a15 30 a17 a7 5 a6 6 a5 7 a4 8 a3 9 a2 10 a1 11 a0 12 d0 13 27 a8 26 a9 25 a11 24 oe 23 a10 22 cs 21 d7 28 a13 29 a14 20 d6 17 d3 18 d4 19 d5 14 d1
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 2 unit voltage on any pin w.r.t. gnd -2.0 to +7 v supply voltage (2) -2.0 to +7 v voltage on a9 w.r.t. gnd (3) -2.0 to +14 v storage temperature -65 to +150 c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. (2) minimum dc voltage on any input or i/o pin is -0.5v. maximum dc voltage on output and i/o pins is vcc+0.5v during transitions voltage may overshoot by +/-1v for up to 10ns (3) minimum dc input voltage on a9 is -0.5v during voltage transitions, a9 may overshoot vss to -1v for periods of up to 10ns, maximum dc input voltage in a9 is 13.5v which may overshoot to 14.0v for periods up to 10ns dc operating conditions parameter symbol test condition min typ max unit i/p leakage current address, oe i li1 v cc = v cc max, v in = 0v or v cc --1a a9 input leakage current i li2 v cc = v cc max, a9 = 12.5v --50a other pins i li3 v cc = v cc max, v in = 0v or v cc --1a output leakage current i lo v cc = v cc max, v out = 0v or v cc --1a v cc operating current i cco cs = v il , os = v ih , i out = 0ma, f = 6mhz --45ma v cc program/erase current i ccp programming in progress --65ma standby supply current ttl i sb v cc = v cc max, cs = v ih oe = v ih - - 1.5 ma cmos i sb1 v cc = v cc max, cs = v cc +0.5, oe = v il - - 115 a autoselect / sector protect voltage v id v cc = 5.0v 11.5 - 12.5 v output low voltage v ol i ol = 5.8ma. v cc = v cc min. - - 0.45 v output high voltage v oh1 i oh = -2.5ma. v cc = v cc min. 2.4 - - v low v cc lock-out voltage v lko 3.2 - 4.2 v absolute maximum ratings (1) parameter min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage (ttl) v ih 2.0 - v cc +0.5 v input low voltage (ttl) v il -0.5 - 0.8 v input high voltage (cmos) v ih 0.7v cc - v cc +0.3 v input low voltage (cmos) v il -0.5 - 0.8 v operating temperature t a 0- 70 c t ai -40 - 85 o c (-i suffix) t am -55 - 125 o c (-m\mb suffix) recommended operating conditions dc electrical characteristic (t a =-55 c to + 125 c,v cc =5v 10%)
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 3 * input pulse levels : 0.0v to 3.0v * input rise and fall times : 5 ns * input and output timing reference levels : 1.5v * v cc = 5v + 10% i/o pin 166 30pf 1.76v ? capacitance (t a =25 c,f=1mhz) parameter symbol test condition typ max unit input capacitance c in1 v in = 0v - 10 pf control pin capacitance c in2 v pp = 0v - 12 pf output capacitance c out v out = 0v - 12 pf note: these parameters are calculated, not measured. ac test conditions
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 4 123456789012345678901234567890121234 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 1 2345678901234567890123456789012123 4 123456789012345678901234567890121234 parameter symbol 55 70 min typ max min typ max unit read cycle time t rc 55 - - 70 - - ns address to output delay t acc - - 55 - - 70 ns chip enable to output t ce - - 55 - - 70 ns output enable to output t oe - - 30 - - 30 ns output enable to output high z t df - - 18 - - 20 ns output hold time from address t oh 0- -0- -ns cs or oe whichever occurs first parameter symbol 90 120 min typ max min typ max unit read cycle time t rc 90 - - 120 - - ns address to output delay t acc - - 90 - - 120 ns chip enable to output t ce - - 90 - - 120 ns output enable to output t oe - - 35 - - 50 ns output enable to output high z t df - - 20 - - 30 ns output hold time from address t oh 0--0- -ns cs or oe whichever occurs first ac operating conditions read cycle 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 consult factory
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 5 123456789012345678901234567890121 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 123456789012345678901234567890121 parameter symbol 55 70 min typ max min typ max unit write cycle time (2) t wc 55 - - 70 - - ns address setup time t as 0-- 0- - ns address hold time t ah 40 - - 45 - - ns data setup time t ds 25 - - 30 - - ns data hold time t dh 0-- 0- - ns output enable setup time t oes 0-- 0- - ns read recover before write t ghwl 0-- 0- - ns cs setup time t ce 0-- 0- - ns cs hold time t ch 0-- 0- - ns we pulse width t wp 40 - - 35 - - ns we pulse width high t wph 20 - - 20 - - ns byte programming operation t whwh1 -16- -16- s sector erase operation (1) t whwh2 - 2 30 - 2 30 sec chip erase operation (1) t whwh3 - 14 120 - 14 120 sec vcc setup time (2) t vcs 50 - - 50 - - s parameter symbol 90 120 min typ max min typ max unit write cycle time (2) t wc 90 - - 120 - - ns address setup time t as 0-- 0- - ns address hold time t ah 45 - - 50 - - ns data setup time t ds 45 - - 50 - - ns data hold time t dh 0-- 0- - ns output enable setup time t oes 0-- 0- - ns read recover before write t ghwl 0-- 0- - ns cs setup time t ce 0-- 0- - ns cs hold time t ch 0-- 0- - ns we pulse width t wp 45 - - 50 - - ns we pulse width high t wph 20 - - 20 - - ns byte programming operation t whwh1 -16- -16- s sector erase operation (1) t whwh2 - 2 30 - 2 30 sec chip erase operation (1) t whwh3 - 14 120 - 14 120 sec vcc setup time (2) t vcs 50 - - 50 - - s notes: (1) this does not include the preprogramming time. (2) not 100% tested. write/erase/program 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 consult factory
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 6 123456789012345678901234567890121 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 1 2345678901234567890123456789012 1 123456789012345678901234567890121 parameter symbol 55 70 min typ max min typ max unit write cycle time (2) t wc 55 - - 70 - - ns address setup time t as 0-- 0- - ns address hold time t ah 40 - - 45 - - ns data setup time t ds 25 - - 30 - - ns data hold time t dh 0-- 0- - ns output enable setup time t oes 0-- 0- - ns read recover before write t ghel 0-- 0- - ns we setup time t ws 0-- 0- - ns we hold time t wh 0-- 0- - ns cs pulse width t cp 30 - - 35 - - ns cs pulse width high t cph 20 - - 20 - - ns programming operation t whwh1 -16- -16- us sector erase operation (1) t whwh2 - 2 30 - 2 30 sec chip erase operation (1) t whwh3 - 14 120 - 14 120 sec vcc setup time (2) t vcs -50- -50- us parameter symbol 90 120 min typ max min typ max unit write cycle time (2) t wc 90 - - 120 - - ns address setup time t as 0-- 0- - ns address hold time t ah 45 - - 50 - - ns data setup time t ds 45 - - 50 - - ns data hold time t dh 0-- 0- - ns output enable setup time t oes 0-- 0- - ns read recover before write t ghel 0-- 0- - ns we setup time t ws 0-- 0- - ns we hold time t wh 0-- 0- - ns cs pulse width t cp 45 - - 50 - - ns cs pulse width high t cph 20 - - 20 - - ns programming operation t whwh1 -16- -16- us sector erase operation (1) t whwh2 - 2 30 - 2 30 sec chip erase operation (1) t whwh3 - 14 120 - 14 120 sec vcc setup time (2) t vcs -50- -50- us note: (1) does not include pre-programming time. (2) not 100% tested. write/erase/program alternate cs controlled writes 1234567890123 1 23456789012 3 1 23456789012 3 1 23456789012 3 1 23456789012 3 1 23456789012 3 1234567890123 consult factory
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 7 output valid oe t oe t acc t df t oh t ce address address stable rc cs outputs we high z high z t notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. d7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t wp t cs t whp t whwh1 t rc t as t ah t wc t ghwl t dh t df t oe t ce address v cc oe data cs we 5555h pa pa a0h pd d out d7 data pollin g t oh t ds ac waveforms for read operation ac waveforms program
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 8 ac waveforms for data polling during embedded algorithm operations notes : 1. pa is address of memory location to be programmed. 2. pd is data to be programmed at byte address. 3. d7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. oh t ce t wc t as t ah t rc t df t oe t ws t address v cc oe data we cs 5555h pa pa a0h pd d out d7 data pollin g ds t dh t cp t chp t ghel t wh wh1 t whwh1 or 2 t df t oh t oe t ce t oe t oeh t oe cs we d7 = valid data d7 high z d0-d6 high z d0-d6 = invalid d0-d6= vaild data d7 * ch t a.c waveforms - alternate cs controlled program operation timings
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 9 valid oe cs we data (d0-d7) * d6 = to gg le d6 = to gg le d6 = stop to gg lin g d0-d7 oe t oeh t * d6 stops toggling ( the device has completed the embedded operations) t wph address we cs data vcc 5555h 2aaah 5555h 5555h 2aaah sa t as t ah oe t ghwl t wp t cs t dh aah 55h 80h aah 55h 10h/30h t ds t vcs notes: 1. sa is the address for sector erase. addresses = don't care for chip erase. ac waveforms for toggle bit during embedded algorithm operations ac waveforms chip / sector erase
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 10 data poll device write pro g ram command sequence (see below) last address ? pro g rammin g completed increment address 5555h/aah 2aaah/55h 5555h/a0h pro g ram address/pro g ram data no yes start pro g ram command sequence (address /command) embedded programming algorithm
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 11 start write erase command sequence see below data poll or to gg le bit successfully completed erasure completed chip erase command sequence (address/command): 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h 5555h/10h 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h sector address/30h sector address/30h sector address/30h } additional sector erase commands are optional individual sector/mulitiple sector erase command sequence (address/command): embedded erase algorithm
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 12 data polling algorithm start read d7~d0 addr=va d7=data? d5=1? read d7~d0 addr = va no yes yes note : 1. va = valid address for programming. during a sector erase operartion, a valid adddress is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. d7 should be rechecked even if d5 = '1' beceause d7 may change simultaneously with d5. d7=data? fail pass yes no
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 13 start read byte addr=va (d0 - d7) d6 = to gg le? d5=1? d6 = to gg le? pass fail read byte addr=va (d0 - d7) yes yes yes no no no va = byte address for pro g rammin g = any of the sector addresses within the sector bein g erased durin g sector erase operation. = xxxxh durin g chip erase note : d6 is rechecked even if d5 = "1" beceause d6 may stop to gg lin g at the same time as d5 chan g in g to "1" toggle bit algorithm
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 14 device operation to activate this mode the programming equipment must force v id on address a9 . all addresses are don't care apart from a0, a1 & a6. device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the register is a latch used to store the commands along with the address and data information required to execute the command. the command register is written by bringing we to v il while cs is at v il and oe is at v ih . addresses are latched on the falling edge of we or cs, whichever happens later; while data is latched on the rising edge of we or cs, whichever happens first. this mode is intended for use by programming equipment. this mode is functional over the full military temperature range. the autoselect codes as follows : * outputs 01h at protected sector address with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. read mode standby mode write type a18 a17 a16 a6 a1 a0 code d7 d6 d5 d4 d3 d2 d1 d0 sector sector address v il v ih v il 01h* 0 0 0 0 0 0 0 1 protection (hex) autoselect output disable two standby modes are available : cmos standby : cs held at vcc +/- 0.5v ttl standby : cs held at v ih in the standby mode the outputs are in a high impedance state independent of the oe input. if the device is deselected during erasure or programming the device will draw active current until the operation is completed. the mfm8516 has two control functions which must be satisfied in order to obtain data at the outputs cs is the power control and should be used for device selection. oe is the output control and should be used to gate data to the output pins if the device is selected.
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 15 device operations are selected by writing specific address and data sequences into the command register. the following table defines these register command sequences. notes: 1. address bit a 15 ,a 16 ,a 17 , a 18 =x=don't care. write sequences may be initiated with a 15 in either state. command sequence read/reset bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle read/reset read/reset autoselect byte program chip erase sector erase sector erase suspend sector erase resume 1 4 3 4 6 6 addr data addr addr addr addr addr data data data data data xxxh 5555h f0h aah 2aaah 55h 90h 80h 5555h 5555h 5555h 5555h aah aah aah 55h 55h 55h 55h 2aaah 2aaah 2aaah 2aaah 5555h 5555h 5555h 5555h 5555h f0h a0h 80h aah ra pa 5555h 5555h rd data aah aah 2aaah 2aaah 55h 55h 5555h sa 10h 30h erase can be suspended during sector erase with addr (don't care) data (b0h) erase can be resumed after suspend with addr (don't care), data (30h) the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of memory content occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. 2. address bit a 15 ,a 16 ,a 17 , a 18 =x=don't care for all address commands except for program address (pa) and sector address (sa). 3. ra=address of the memory location to be read. pa=address of memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa=address of the sector to be erased. the combination of a 18 , a 17 and a 16 will uniquely select any sector. 4. rd=data read from location ra during read operation. pd=data to be programmed at location pa. data is latched on the rising edge of we 5. read and byte program functions to non-erasing sectors are allowed in the erase suspend mode. command definitions read / reset command
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 16 the mfm8516 features hardware sector protection. this feature will disable both program and erase opera- tions in any number of sectors (0 through 8). the sector protect feature is enabled using programming equip- ment at the users site. the device is shipped with all sectors unprotected. it is also possible to determine if a sector is protected in the system by writing the autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a16, a17, a18) are the sector addresses will produce a logical "1" at d0 for a protected sector. the mfm8516 also features a sector unprotect mode so that a potected sector may be unprotected to incorporate any changes in the code. the sector unprotect is enabled using programming equipment at the user's site. it is also possible to determine if a sector is unprotected in the system by writing the autoselect command and a6 is set at v ih . performing a read operation at address location xxx2h, where the higher order addresses (a18, a17, and a16) define a particular sector address, will produce 00h at data outputs (d0 - d7) for an unprotected sector. sector address table a18 a17 a16 address range sa0 0 0 0 00000h-0ffffh sa1 0 0 1 10000h-1ffffh sa2 0 1 0 20000h-2ffffh sa3 0 1 1 30000h-3ffffh sa4 1 0 0 40000h-4ffffh sa5 1 0 1 50000h-5ffffh sa6 1 1 0 60000h-6ffffh sa7 1 1 1 70000h-7ffffh flash memories are intended for use in applications where the local cpu alters memory contents. prom programmers typically access the signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desired system design practice. to terminate the operation, it is necessary to write the read/reset command sequence into the register. the device contains an autoselect operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following command write, scanning the sector addresses on a16, a17, & a18 while a6, a1 & a0 = 0, 1, 0 will produce a logical "1" at device output d0 for a protected sector. sector protection sector unprotect autoselect command
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 17 the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two "unlock" write cycle. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of we or cs, whichever happens later, while the data are latched on the rising edge of we or cs whichever happens first. the rising edge of we or cs begins programming. upon executing the embedded program algorithm command sequence the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on d7 is equiva- lent to data written to this bit (see write operations status) at which time the device returns to the read mode and addresses are no longer latched. data polling must be performed at the memory location which is being programmed. programming is allowed in any address sequence and across sector boundaries. sector erase is a six bus cycle operation. there are two "unlock"write cycles. these are followed by writing the "set-up" command. two more "unlock" write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we, while the command (data) is latched on the rising edge of we. a time-out of 80 s from the rising edge of the last sector erase command will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 80 s, otherwise the command will not be accepted. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be-enabled after the last sector erase command is written. a time-out of 80 s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 80us time-out window the timer is reset. any command other than sector erase or erase suspend during this period and afterwards will reset the device to read mode, ignoring the previous command string. resetting the device after it has begun execution will result in the data of the operated sectors being undefined. in that case, restart the erase on those sectors and allow them to complete. loading the sector erase buffer may be done in any sequence and with any number of sectors. sector erase doesn't require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 100 s time-out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on d7 is "1" ( see written operation status section) at which time the device returns to read mode. data polling must be preformed at an address within any of the sectors being erased. chip erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command. two more "unlock" write cycles are then followed by the chip erase command. chip erase doesn't require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the systems is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on d7 is "1" (see written operation section) at which time the device returns to read the mode. byte programming sector erase chip erase
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 18 erase suspend allows the user to interrupt a sector erase operation and then perform data reads or programs to a sector not being erased. this command is only applicable during the sector erase operation which in- cludes the time-out period for sector erase. the erase suspend command will be ignored if written during chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume command. writing the erase resume command resumes the erase operation. the addresses are "don't- cares" when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 15 s to suspend the erase operation. when the device has entered the erase-suspend mode, d7 bit will be a logic '1', and d6 will stop toggling. the user must use the address of the erasing sector for reading d6 and d7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. read- ing data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspend sector while the device is in the erase-suspend-read mode will cause d2 to toggle. after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for byte program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular byte program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase- suspended sector while the device is in the erase-suspend-program mode will cause d2 to toggle. the end of the erase-suspend-program operation is detected by data polling of d7, or by the toggle bit (d6) which is the same as the regular byte program operation. note that d7 must be read from the byte program address while d6 can be read from any address. to resume the operation of sector erase, the resume command should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. status d7 d6 d5 d3 in progress byte programming in embedded algorithm d7 toggle 0 0 embedded erase algorithm 0 toggle 0 1 erase erase suspended sector 1 no tog 0 1 suspended mode non-erase suspended sector data data data data exceeded byte-programming in embedded algorithm d7 toggle 1 0 time limits embedded erase algorithm 0 toggle 1 1 program in erase suspended mode d7 toggle 1 1 erase suspend write operations status
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 19 the following modes are used to control the device. operation cs oe we a0 a1 a6 a9 i /o read (1) llha0a1a6a9d out standby h x x x x x x high z output disable l h h x x x x high z write l h l a0 a1 a6 a9 din verify sector protect l l h l h l v id code auto-select device unprotected code l l h h h l v id code the mfm8516 features data polling as a method to indicate to the host system that the embedded algo- rithms are in progress or completed. during the embedded programming algorithm, an attempt to read the device will produce complement data of the data last written to d7. upon completion of the embedded pro- gramming algorithm an attempt to read the device will produce the true data last written to d7. during the embedded erase algorithm, during the embedded erase algorithm, an attempt to read the device will pro- duce a "0" at the d7 output. for chip erase, the data polling is valid after the rising edge of the six we pulse in the six write pulse se- quence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector address within any of the sectors being erased or not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the device data pins (d7) may change asynchronously while oe is asserted low. this means that the device is driving status information on d7 at one instant of time and then that byte's valid data at the next instant of time. depending on when the system samples the d7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and d7 has a valid data, the data outputs on d0-d6 may still be invalid. the valid data on d0-d7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out. 1) l=v il , h=v ih, x=don't care note: 1) we can be v il if oe is v il , oe at v ih initiates write operation. operating modes d7 data polling
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 20 d5 will indicate if the program or erase time has exceeded the specified limits. under these conditions d5 will produce "1", indicating the program or erase cycle was not successfully completed . data polling is the only operating function of the device under this condition. the cs circuit will partially power down the device under these conditions (to approximately 2ma). the oe and we pins will control the output disable functions . if this failure occurs during sector erase operations, it specifies that a particular sector is bad and may not be re-used. the device must be reset to use other sectors. write the reset command sequence and execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this failure occurs during chip erase operation , it specifies that the device chip or combination of sectors are bad. if this failure occurs during the byte programming operation, it specifies that the entire sectors containing that byte is bad and may not be re-used. the d5 failure condition may also appear if the user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence the system never reads a valid data on d7 and d6 never stops toggling. once the device has exceeded timing limits, the d5 bit will indicate '1' during an embedded program or erase algorithm cycle, successive attempts to read data from the device will result in d6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, d6 will stop toggling and valid data will be read on the next successive attempts. during program- ming, the toggle bit is valid after the rising edge of the forth we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erare we pulse. the toggle bit is active during the sector time-out. the mfm8516 also features the "toggle bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. after the completion of the initial sector erase command sequence the sector erase time-out will begin. d3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, d3 may be used to determine if the sector erase timer window is still open. if d3 is high the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera- tion is completed as indicated by data polling or toggle bit. if d3 is low , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of d3 prior to and following each subsequent sector erase command. if d3 were high on the second status check, the command may not have been accepted. d6 toggle bit d5 exceeding time limits d3 sector erase timer
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 21 the mfm8516 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the internal state machine in the read mode. also, with its controls register architecture , alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power up and power down transitions or system noise. to avoid initiation of a write cycle during v cc power up and power down, a write cycle is locked out for v cc v lko . noise pulses of less than 5ns (typical) on oe, cs, we will not initiate a write cycle writing is inhibited by holding any one of oe=v il , cs=v ih or we=v ih . to initiate a write cycle cs and we must be logical zero while oe is a logical one. power-up of the device with we = cs = v il and oe = v ih will not accept commands on the rising edge of we. the internal state machine is automatically reset to the read mode on power-up. sectors of the mfm8516 may be hardware protected at the users factory. the protection circuitry will disable both program and erase functions for the protected sector(s). requests to program or erase a protected sector will be ignored by the device. notes: (1) 25 o c, 5v v cc , 10,000 cycles. (2) the embedded algorithms allow for 2.5ms byte program time. data protection low v cc write inhibit write pulse "glitch" protection logical inhibit power up write inhibit sector protect erase and programming performance limits parameter min typ max unit comments sector erase time 1 15 sec excludes 00h programming (note 1) prior to erasure. chip erase time 8 120 sec excludes 00h programming prior to erasure. byte programming time 7 1000 s excludes system-level overhead. (note 1) chip programming time 3.6 25 sec excludes system-level overhead. (note 1) (note 2)
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 22 package details 4.00 (0.157) 3.00 (0.117) 1.52 (0.060) 1.02 (0.040) 2.67 (0.105) 0.51 (0.020) 0.41 (0.016) 2.41 (0.095) 4.30 (0.170) 3.30 (0.130) 15.56 (0.610) 15.05 (0.590) 41.05 (1.615) 40.26 (1.585) 32 pin 0.6" dual-in-line (dil) - 's' package 32 pin j-leaded chip carrier (jlcc) - 'j' package 1.90 (0.075) no. 1 index 1.27 (0.050) typ 0.71 (0.028) typ 4.32 (0.170) 13.45 (0.530) 0.43 (0.017) typ 3.80 (0.150) 10.41 (0.410) 7.87 (0.310) 1.65 (0.065) 11.70 (0.460) 11.30 (0.445) 14.22 (0.560) 13.84 (0.545) 9.91 (0.390) 7.37 (0.290) 13.95 (0.510)
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 23 military screening procedure component screening flow for high reliability product using methods from 5004. screening mechanical temperature cycle 1010 condition c (10 cycles,-65 c to +150 c) 100% constant acceleration 2001 condition e (y, only) (30,000g) 100% pre-burn-in electrical per applicable device specifications at t a =+25 c 100% burn-in method 1015,condition d,t a =+125 c,160hrs min 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post-burn-in at t a =+25 c 5% hermeticity 1014 fine condition a 100% gross condition c 100% external visual 2009 per vendor or customer specification 100% screen test method level mb component screening flow endurance as per internal specification write cycle endurance and data retention performance
mfm8516 - 55/70/90/12 issue 5.0 : april 2001 24 ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express approval of a company director. mfm8516smb - 55e write cycle endurance e = 100,000 cycles (min) blank = 10,000 cycles (min) speed 55 = 55 ns - consult factory 70 = 70 ns 90 = 90 ns 12 = 120 ns temp. range/screening blank = commercial temperature i = industrial temperature m = military temperature mb = processed in accordance with mil-std-883 packages s = 32 pin ceramic dual in-line j = 32 pad ceramic jlcc organisation 8516 = 512kx 8 flash memory technology f = fl ash memory

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