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512 k x 32 static ram elm road, west chirton industrial estate, north shields, ne29 8se, england. tel +44 (0191) 2930500. fax +44 (0191) 2590997 e-mail: hmpsales@mosaicsemi.com /we /cs1 d16~23 d0~7 d8~15 d24~31 /cs2 /cs3 /cs4 a0~a18 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram /oe description signal address input a0~a18 data input/output d0~d31 chip select /cs1~4 write enable /we output enable /oe no connect nc power v cc ground v ss pin functions block diagram pin definition see page 2. package details puma 68 - plastic 68 ?j? leaded package max. dimensions (mm) - 25.27 x 25.27 x 5.08 features access times of 12/15/17 ns. 3.3v + 10%. commercial and industrial temperature grades jedec standard 68 j lead footprint. industry standard pinout. may be organised as 512k x 32, 1m x 16, 2m x 8 operating power (32 bit) 2.74w (max) low power standby. (ttl) 0.87w (max) (cmos) 145mw (max) completely static operation. puma 68sv16000xb - 012/015/017 issue 5.2 april 2001 description the puma68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including sram, eeprom and flash. the devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide. the puma68sv16000xb is a 512kx32 sram mod- ule housed in a 68 jleaded package which complies with the jedec 68 plcc standard. access times of 12, 15 or 17ns are available. the 3.3v low voltage device is available to commercial and industrial temperature grade.
issue 5.2 april 2001 page 2 pin definition - puma68sv16000x pin si g nal pin si g nal 1 v cc 35 v cc 2 nc 36 a13 3 /cs1 37 a12 4 /cs2 38 a11 5 /cs3 39 a10 6 /cs4 40 a9 7 a17 41 a8 8 a18 42 a7 9 d16 43 d0 10 d17 44 d1 11 d18 45 d2 12 d19 46 d3 13 v ss 47 v ss 14 d20 48 d4 15 d21 49 d5 16 d22 50 d6 17 d23 51 d7 18 v cc 52 v cc 19 d24 53 d8 20 d25 54 d9 21 d26 55 d10 22 d27 56 d11 23 v ss 57 v ss 24 d28 58 d12 25 d29 59 d13 26 d30 60 d14 27 d31 61 d15 28 a6 62 a14 29 a5 63 a15 30 a4 64 a16 31 a3 65 /we 32 a2 66 /oe 33 a1 67 nc 34 a0 68 nc
dc operating conditions issue 5.2 april 2001 page 3 parameter s y mbol min t y p max unit suppl y volta g e v cc 3.0 3.3 3.6 v input hi g h volta g e v ih 2.0 - v cc +0.3 v input low volta g e v il ( 1 ) -0.3 - 0.8 v operatin g temperature t a 0 - 70 o c t ai -40 - 85 o c ( i suffix ) absolute maximum ratings (1) recommended operating conditions dc electrical characteristics (v cc =3.3v +10%, t a =-40 o c to +85 o c) parameter s y mbol min max unit volta g e on an y pin relative to v ss v t -0.3 to +4.6 v power dissipation p t 4.0 w stora g e temperature t stg -55 to +125 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability notes : (1) pulse width : -2.0v for less than 10ns. notes (1) /cs1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) at f=f max address and data inputs are cycling at max frequency. parameter symbol test condition min typ max unit input leakage current i li v in =0v to v cc -8 - 8 a output leakage current i lo v i/o =0v to v cc -8 - 8 a average supply current (2) 32 bit i cc32 /cs (1) =v il , i i/o =0ma,f=f max - - 760 ma 16 bit i cc16 as above. - - 490 ma 8 bit i cc8 as above. - - 370 ma standby supply current ttl i sb /cs (1) =v ih ,min cycle - - 240 ma cmos i sb1 /cs > v cc -0.2v, 0.2v > v in > v cc -0.2v, f=0 - - 40 ma output voltage low v ol i ol =8.0ma, v cc =min - - 0.4 v output voltage high v oh i oh =-4.0ma, v cc =min 2.4 - - v
issue 5.2 april 2001 page 4 166? 30pf i/o pin 1.76v capacitance (v cc = 3.3v, t a = 25 o c, f=1mhz.) parameter symbol test condition min typ max unit input capacitance, address, /oe, /we c in1 v in =0v - - 30 pf output capacitance, 8 bit mode (worst case) c i/o v i/o =0v - - 34 pf test conditions output load input pulse levels : 0v to 3.0v input rise and fall times : 3ns input and output timing reference levels : 1.5v output load : see load diagram. v cc = 3.3v +10% puma module tested in 32 bit mode. note : these parameters are calculated not measured. /cs1 /cs2 /cs3 /cs4 /oe /we suppl y current mode l h h h x l i cc8 write d0~d7 h l h h x l i cc8 write d8~d15 h h l h x l i cc8 write d16~d23 h h h l x l i cc8 write d24~d31 l l h h x l i cc16 write d0~d15 h h l l x l i cc16 write d16~d31 l l l l x l i cc32 write d0~d31 l h h h l h i cc8 read d0~d7 h l h h l h i cc8 read d8~d15 h h l h l h i cc8 read d16~d23 h h h l l h i cc8 read d24~d31 l l h h l h i cc16 read d0~d15 h h l l l h i cc16 read d16~d31 l l l l l h i cc3 2 read d0~d31 x x x x h h i cc32 /i cc16 /i cc8 d0~d31 hi g h-z h h h h x x i sb , i sb1 d0~d31 standb y operation truth table notes : h=v ih : l=vi l : x=v ih or v il
ac operating conditions issue 5.2 april 2001 page 5 read cycle write cycle 12 15 17 parameter s y mbol min max min max min max units read c y cle time t rc 12 - 15 - 17 - ns address access time t aa - 12 - 15 - 17 ns chip select access time t a cs - 12 - 15 - 17 ns output enable to output valid t o e - 6 - 7 - 8 ns output hold from address chan g e t o h 3 - 3 - 3 - ns chip selection to output in low z t c lz 3 - 3 - 3 - ns output enable to output in low z t o lz 0 - 0 - 0 - ns chip deselection to output in hi g h z t c hz 0 6 0 7 0 8 ns output disable to output in hi g h z t o hz 0 6 0 7 0 8 ns 12 15 17 parameter s y mbol min max min max min max units write c y cle time t wc 12 - 15 - 17 - ns chip selection to end of write t c w 8 - 10 - 12 - ns address valid to end of write t aw 8 - 10 - 12 - ns address setup time t a s 0 - 0 - 0 - ns write pulse width ( /oe hi g h ) t wp1 8 - 10 - 12 - ns write pulse width ( /oe low ) t wp2 12 - 12 - 13 - ns write recover y time t wr 0 - 0 - 0 - ns write to output in hi g h z t whz 0 6 0 7 0 8 ns data to write time overlap t dw 6 - 7 - 8 - ns data hold time from write time t dh 0 - 0 - 0 - ns output active from end of write t ow 3 - 3 - 3 - ns
timing waveforms issue 5.2 april 2001 page 6 address data out valid data t rc t aa t acs t olz t clz(4,5) t chz(3,4,5) t ohz t oh /cs /oe notes (read cycle) 1. /we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t chz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t chz (max.) is less than t clz (min.) both for a given device and from device to device. 5. transition is measured ? 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with /cs=v il . 7. address valid prior to coincident with /cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 9. /cs=/cs1~4 t oe previous data valid data valid address data out t rc t aa t oh read cycle 1 (address controlled, /cs=/oe=v il , /we=v ih ) read cycle 2 (/we = v ih )
issue 5.2 april 2001 page 7 valid data address /oe /cs data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t dw t dh t ohz(6) high z high z(8) /we notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite p hase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 ./cs=/cs1~4 write cycle 1 (/oe = clock)
issue 5.2 april 2001 page 8 write cycle 2 (/oe = low fixed) /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t ow (10) (9) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite p hase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 ./cs=/cs1~4
issue 5.2 april 2001 page 9 write cycle 3 (/cs = controlled) /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t lz high z high z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 /cs=/cs1~4
package details page 10 issue 5.2 april 2001 puma 68 pin jedec surface mount plcc notes: 1. all dimensions in mm (inches). 25.02 (0.985) 0.90 (0.035) typ 23.11 (0.910) 5.08 (0.200) max 24.13 (0.950) 25.27 (0.995) xxxxxx-x 0.46 (0.018) 1.27 (0.050) pin 68 pin 1
ordering information page 11 issue 5.2 april 2001 ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. puma 68sv16000xbi-015 speed 012 = 12ns 015 = 15ns 017 = 17ns temp. range/screening blank = commercial i = industrial pinout configuration xb = csp based industry standard pinout memory organisation 16000 = 512k x 32 configurable as 1m x 16 and 2m x 8 technology sv = sram 3.3v +10% v cc package puma 68 = 68 pin ? j ? leaded plcc
customer guidelines page 12 issue 5.2 april 2001 visual inspection standard all devices inspected to ansi/j-std-001b class 2 standard moisture sensitivity devices are moisture sensitive. shelf life in sealed bag 12 months at <40 o c and <90% relative humidity (rh). after this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220 o c) must be : a : mounted within 72 hours at factory conditions of <30 o c/60% rh or b : stored at <20% rh if these conditions are not met or indicator card is >20% when read at 23 o c +/-5% devices require baking as specified below. if baking is required, devices may be baked for :- a : 24 hours at 125 o c +/-5% for high temperature device containers or b : 192 hours at 40 o c +5 o c/-0 o c and <5% rh for low temperature device containers . packaging standard devices packaged in dry nitrogen, jed-std-020. packaged in trays as standard. tape and reel available for shipment quantities exceeding 200pcs upon request. soldering recomendations ir/convection - ramp rate 6 o c/sec max. temp. exceeding 183 o c 150 secs. max. peak temperature 225 o c time within 5 o c of peak 20 secs max. ramp down 6 o c/sec max. vapour phase - ramp up rate 6 o c/sec max. peak temperature 215 - 219 o c time within 5 o c of peak 60 secs max. ramp down 6 o c/sec max. the above conditions must not be exceeded note : the above recomendations are based on standard industry practice. failiure to comply with the above recomendations invalidates product warranty.

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