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mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 3 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change features 1.0 description the m3024 group is a 16-bit microcomputer based on the m16c family core technology. they are single-chip usb peripheral microcontrollers based on the universal serial bus (usb) version 1.1 specification. they are packaged in an 80-pin, molded plastic qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency, making them capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. 1.1 features ? cpu .................................................... 16-bit (including a hardware multiplier) ? number of instructions ........................ 91 ? shortest instruction execution time ..... 83ns(f(xin)=12mhz ? usb features:..................................... five endpoint pairs (in/out) fifo sizes (endpoints 0-4):32,128, 32, 32, 32 conforms to usb v1.1 speci?cation ? usb transceiver ................................. conforms to usb v1.1 speci?cation-internal vref ? frequency multiplier............................ pll for 48mhz clock ? memory capacity (mask device):......... rom (40k) / ram (3.0 k) ? memory capacity (otp device):.......... eprom (128k) / ram (5k) ? supply voltage .................................... 4.1 to 5.5v (f(xin)=12mhz) ? interrupts............................................. 21 internal and 4 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt x 16) ? multifunction timer ............................... 5 x 16-bit, w/integrated 20ma pwm outputs ? general purpose timer ........................ 3 x 16-bit, internal interrupt only ? uart................................................... 3 x 7/8/9 bits; con?gurable for synchronous or asynchronous mode ? dmac.................................................. 2 channels (trigger: 16 sources) ? a-d converter ..................................... 10 bits x 8 channels ? crc calculation circuit ........................ industry standard polynomial ? watchdog timer ................................... 15-bit ? programmable i/o............................... 63 lines ? high current and led drivers ............. 5 high current and 8 led drivers ? clock-generating circuit....................... 1 built-in circuit including feedback resistor ? package: ............................................. 80p6n (0.8 mm pitch) 1.2 applications usb peripherals, such as telephones, audio systems, scanners, and digital cameras.
confidential 4 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change pin configuration 1.3 pin con?guration figure 1 shows the pin configuration (top view). figure 1: pin con?guration (top view) 41 40 24 65 p100/an0 66 avss 67 lpf 68 vref 69 avcc 70 p87/ ad trg 71 p86/sof 72 extcap 73 74 75 76 77 78 79 80 23 22 21 20 19 18 17 16 15 p84/int1 14 p85/ nmi 13 vcc 12 11 10 x in 9 vss 8 x out 7 6 d- 5 d+ 4 3 2 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p107/an7 p106/an6 p105/an5 m30240mx/ec reset 61 p104/an4 62 p103/an3 63 p102/an2 64 p101/an1 p83/attach p82/int0 p81/ta4in p80/ta4out p77/ta3in p75/ta2in p72/clk2/t a1out p73/ cts2/rts2 /ta1in p74/ta2out p76/ta3out p32 p33 p34 p35 p36 p37/clkout p60/cts0/rts0 p61/clk0 p62/rxd0 p63/txd0 p64/ cts1/rts1/cts0/clks1 p65/clk1 p66/rxd1 p67/txd1 p70/txd2/ta0out p71/rxd2/ta0in p03/ ki3 p02/ ki2 p01/ ki1 p00/ ki0 p04/ ki4 p05/ ki5 p06/ ki6 p07/ ki7 p10/ ki8 p11 /ki9 p12/ ki10 p13/ ki11 p14/ ki12 p15/ ki13 p16/ ki14 vss p17/ ki15 vcc p20/led0 p21/led1 p22/led2 p23/led3 p24/led4 p25/led5 p26/led6 p27/led7 p30 p31 byte cnvss
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 5 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change block diagram 1.4 block diagram figure 2 is a block diagram of the m16c/24 group. figure 2: block diagram of m16c/24 group timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) internal peripheral functions watchdog timer (15 bits) dmac (2 channels) a-d converter 10 bits x 8 channels system clock generator x in -x out i/o ports crc arithmetic circuit (ccitt) (polynomial : x 16 +x 12 +x 5 +1) note 1: one of serial i/o can be used for sim interface. memory m16c/24 series16-bit cpu core r0l r0h r1h r1l r2 r3 a0 a1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers isp usp stack pointer vector table intb multiplier sb flg pc program counter port p0 8 port p1 8 port p2 8 port p3 8 port p6 8 port p7 8 port p8 7 port p8 5 port p10 8 usb function frequency synthesizer rom ram uart/clock synchronous si/o (8bits x 3 channels) (note 1)
confidential 6 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change performance outline 1.5 performance outline table 1 is a performance outline of the m16c/24 group. table 1: performance outline of m16c/24 group item performance number of basic instructions 91 instructions shortest instruction execution time 83ns (f(xin)=12mhz) memory capacity rom (see figure 3: rom capacity ?eld) ram i/o port p0 to p3, p6,p7, p8 (except p85), p10 8 bits x 7, 7 bits x 1 input port p85 1 bit x 1 multifunction timer ta0, ta1, ta2, ta3, ta4 16 bits x 5 general purpose timer tb0, tb1, tb2 16 bits x 3 serial i/o uart0, uart1, uart2 (uart or clock synchronous) x 3 a-d converter 10 bits x 8 channels dmac 2 channels (trigger: 24 sources) crc calculation circuit crc-ccitt watchdog timer 15 bits x 1 (with prescaler) interrupt 21 internal and 4 external sources, 4 software sources, 7 levels clock-generating circuit built-in clock generation circuit (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage 4.1 to 5.5v (f(xin)=12mhz, without software wait) power consumption 83 ma @ 12mhz i/o characteristics i/o withstand voltage 5v output current 20 ma available on ports p20 through p27; also ports p70, p72, p74, p76, and p80 are available. operating temperature C40 to 85 o c device con?guration cmos high performance silicon gate package 80-pin plastic molded qfp
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 7 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change performance outline mitsubishi plans to release the following products in the m16c/24 group: (1) support for mask rom version, one-time prom version, and eprom version (2) rom capacity (3) package ? 80p6n: plastic molded qfp (mask rom version and one-time prom version) figure 3 shows the type number, memory size and package for the m16c/24 group. figure 3: type number, memory size, and package package type: fp : package 80p6n rom no. omitted for blank one-time prom version and eprom version rom capacity: 1 : 8k bytes 7 : 56k bytes 2 : 16k bytes 8 : 64k bytes 3 : 24k bytes 9 : 80k bytes 4 : 32k bytes a : 96k bytes 5 : 40k bytes c : 128k bytes 6 : 48k bytes memory type: m : mask rom version e : eprom or one-time prom version s : external rom version f : flash rom version m 3 0 2 4 0 m 5 ? x x x f p m16c/24 group m16c family part type: specifies part variations within m16c/24 group type no.
confidential 8 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change pin description 1.6 pin description table 2: figure pin description pin # name i/o description 1 p8 7 i/o cmos i/o port. this pin also functions as an external trigger for a-d conversion. 2 p8 6 i/o cmos i/o port. this pin also functions as the start of frame (sof) pulse for the usb module. 3 p8 5 / (nmi) i cmos input port. this pin also functions as a non-maskable external interrupt. 4,5 p8 4 ~ p8 3 i/o cmos i/o port. these pins also functions as external interrupt 1 and are used to enable the stealth detach function for the usb transceiver. 6 extcap i an external capacitor (ext. cap) pin. if v dd (av dd ) =5v is used for the entire chip, a 2 m f or larger capacitor connects between this pin and v ss to ensure proper operation of the usb line driver. this option is enabled by setting bit 4 of the usb control register (0013 16 ) to a 1. 7 byte i connect this pin to vss 8 cnv ss i connect this pin to vss 9 usb d + i/o usb d+ voltage line interface, a series resistor of 33 w is connected to this pin. 10 usb d - i/o usb d- voltage line interface, a series resistor of 33 w is connected to this pin. 11 reset i a l on this input resets the microcomputer. 12 x out o see xin 13 v ss i ground: v ss = 0v 14 x in i input and output signals to and from the internal clock generation circuit. connect a ceramic resonator or quartz crystal between x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 15 v cc i power: v cc = 4.1~ 5.5v 16 p8 2 i/o cmos i/o port. this pin also functions as external interrupt 0. 17-18 p8 1 ~ p8 0 i/o cmos i/o port . pins in this port also function as timera4 input and output as selected by software. 19-22 p7 7 ~ p7 4 i/o cmos i/o port . pins in this port also function as timer pins. p7 7 and p7 6 can function as timera3 input and output as selected by software. p7 5 and p7 4 can function as timera2 input and output as selected by software. 23-26 p7 3 ~ p7 0 i/o cmos i/o port . pins in this port also function as uart2 cts, rts, clk, rxd, and txd as selected by software. p7 3 and p7 2 can function as timera1 input and output as selected by software. p7 1 and p7 0 can function as timera0 input and output as selected by software. 27-30 p6 7 ~ p6 4 i/o cmos i/o port . pins in this port also function as uart1 cts, rts, clk, serial clock, rxd, and txd as selected by software. txd(oe~) and rts(suspend) in addition to d+ and d- can be used to run the device in usb bypass mode. 31-34 p6 3 ~ p6 0 i/o cmos i/o port . pins in this port also function as uart0 cts, rts, clk, rxd, and txd as selected by software. 35-42 p3 7 ~ p3 0 i/o cmos i/o port. 43-50 p2 7 /led7 ~ p2 0 /led0 i/o cmos i/o port. these pins are capable of driving up to 20ma for leds.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 9 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change pin description 51 v cc i power: v cc = 4.1~ 5.5v 52 p1 7 / ki 15 i/o cmos i/o port. this port can also function as the key-on wakeup interrupt ki15. 53 v ss i ground: v ss = 0v 54-60 p1 6 / ki 14 ~ p1 0 / ki 8 i/o cmos i/o port. this port can also function as the key-on wakeup interrupts ( ki8 ~ ki14). 61-68 p0 7 / ki 7 ~ p0 0 / ki 0 i/o cmos i/o port. this port can also function as the key-on wakeup interrupts ( ki0 ~ ki7). 69-76 p10 7 ~ p10 0 i/o cmos i/o port. these pins also function as analog inputs 7-0 for a-d conversion 77 av ss i analog ground: av ss = 0v 78 lpf o loop ?lter for the frequency synthesizer. 79 v ref i this pin is the reference voltage input for the a-d converter. 80 av cc i analog power: av cc = 4.75~ 5.25v table 2: figure pin description pin # name i/o description
confidential 10 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change overview 1.7 overview the m30240 device is a single chip pc peripheral microcontroller based on the universal serial bus (usb) version 1.1 specification. this device provides interface between a usb- equipped host computer and pc peripherals such as telephones, audio systems, and digital cameras. the m30240 block diagram is shown in figure 4. the usb function control unit of the m30240 device can support all four data transfer types listed in the usb specification: isochronous, interrupt, bulk, and control. each transfer type is used for controlling a different set of pc peripherals. isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (cti) and audio systems. interrupt transfers are designed to support human input devices (hid) that communicate small amounts of data infrequently. bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the pc as bus bandwidth becomes free. finally, control transfers are supported and are useful for bursty, host-initiated type communication where bus management is the primary concern. figure 4: m30240 block diagram frequency ram eprom dmac x 2 m16c cpu uart x 3 timers x 8 watchdog crc circuit i/o ports (p0~p3, p6 ~ p8, p10) fifos usb function control unit transceiver d+ d- (normal mcu or dma transfer) 4 - 12mhz 48 mhz f synthesizer led drivers ( x 8 ) a-d converter timer (3.0k) 128k rom 40k
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 11 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change central processing unit (cpu) 2.0 operation of functional blocks the m16c/24 group accommodates certain units in a single chip. these units include rom and ram to store instructions and data, and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as usb, timers, serial i/o, dmac, crc calculation circuit, a-d converter, and i/o ports. the following explains each unit. 2.1 central processing unit (cpu) the cpu has a total of 13 registers shown in figure 5. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. figure 5: central processing unit register (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa b15 b0 r3 (note) aaaaaaa aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa b15 b0 fb (note) aaaaaaa aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. aa aa aa aa a a aa aa aaaaaa aaaaaa aa aa aa aa a a aa aa aa aa c d z s b o i u ipl
confidential 12 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change central processing unit (cpu) registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1, can be used as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be execut- ed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vec- tor table. intb can be used as separate registers of four high-order bits and 16 low-order bits. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each con- figured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 6 shows the flag reg- ister (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 13 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change central processing unit (cpu) ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software inter- rupts 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is en- abled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the m16c software manual for details. figure 6: flag register (flg) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa aa aa aa aa a a aaaaaaa aaaaaaa aa aa a a aa aa aa aa aa aa c d z s b o i u ipl b0 b15
confidential 14 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change processor mode 2.2 processor mode figure 7 shows the processor mode registers 0 and 1. figure 7: processor mode registers 0 and 1 processor mode register 0 (note 1) symbol address when reset pm0 0004 16 00 16 (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bit note : set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. processor mode register 1 (note) symbol address when reset pm1 0005 16 00xxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. reserved bit must always be set to ? 0 note : set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. pm17 wait bit 0 : no wait state 1 : wait state inserted 0 must always be set to "0" pm03 software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. 0 0 0 0 0 0
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 15 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change memory 2.3 memory figure 8: memory map figure 8 is a memory map of the m16c/24 group. the address space extends the 1m bytes from address 00000 16 to fffff 16 . addresses above xxxxx 16 are rom. for example, in the m30240ec- xxxfp, there is 128k bytes of internal rom from e0000 16 to fffff 16 . the special page vector table is mapped from ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as two-byte instructions, reducing the number of program steps. the vector table for fixed interrupts such as the reset and nmi are mapped from fffdc 16 to fffff 16 . the starting addresses of the interrupt routines are stored here. the address of the vector table for software interrupts can be set as desired using the internal register (intb). see section 2.12 on interrupts for further details. addresses below yyyyy 16 are ram. for example, in m30240ec-xxxfp, 5k bytes of internal ram are mapped to the space from 00400 16 to 017ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated.the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates control registers for peripheral devices such as i/o ports, a-d converter, serial i/o, and timers. section 2.4 describes the sfr area for peripheral unit control registers. any part of the sfr area that is unoccupied is reserved and cannot be used for other purposes. masked rom version eprom version yyyyy 16 overflow brk instruction address match single step watchdog timer reset 00000 16 00400 16 01800 16 e0000 16 eprom 128k unused sfr ram 5k ffe00 16 fffdc 16 fffff 16 undefined instruction special page vector table dbc nmi xxxxx 16 00000 16 00400 16 0fff 16 rom 40k unused sfr ram 3k ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi yyyyy 16 xxxxx 16 f6000 16
confidential 16 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change sfr map 2.4 sfr map the table below shows the peripheral control registers, their addresses, names, acronyms, and values after reset. address register name acronym value after reset 0000 16 0001 16 0002 16 0003 16 0004 16 processor mode register 0 pm0 00 16 0005 16 processor mode register 1 pm1 0 0 0 0006 16 system clock control register 0 cm0 00 16 0007 16 system clock control register 1 cm1 20 16 0008 16 0009 16 address match interrupt enable register aier 00 000a 16 protect register prcr 000 000b 16 000c 16 usb control register usbc 00 16 000d 16 000e 16 watchdog timer start register wdts 000f 16 watchdog timer control register wdc 0 0 0 ? ? ? ? ? 0010 16 address match interrupt register 0 rmad0 00 16 0011 16 00 16 0012 16 0000 0013 16 0014 16 address match interrupt register 1 rmad1 00 16 0015 16 00 16 0016 16 0000 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 reserved 001f 16 usb attach / detach register 00 16 0020 16 dma0 source pointer sar0 0021 16 0022 16 0023 16 0024 16 dma0 destination pointer dar0 0025 16 0026 16 0027 16 0028 16 dma0 transfer counter tcr0 0029 16 002a 16 002b 16 002c 16 dma0 control register dm0con 0 0 0 0 0 ? 0 0 002d 16 002e 16 002f 16 0030 16 dma1 source pointer sar1 0031 16 0032 16 0033 16 0034 16 dma1 destination pointer dar1 0035 16 0036 16 0037 16 0038 16 dma1 transfer counter tcr1 0039 16 003a 16 003b 16 003c 16 dma1 control register dm1con 0 0 0 0 0 ? 0 0 003d 16 003e 16 003f 16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 17 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change sfr map 0040 16 0041 16 0042 16 0043 16 0044 16 suspend interrupt control register suspic ?000 0045 16 0046 16 resume interrupt control register rsmic ?000 0047 16 usb sof interrupt control register sofic ?000 0048 16 0049 16 004a 16 bus collision detection interrupt control register bcnic ?000 004b 16 dma0 interrupt control register dm0ic ?000 004c 16 dma1 interrupt conrol register dm1ic ?000 004d 16 key input interrupt control register kupic ?000 004e 16 a-d conversion interrupt control register adic ?000 004f 16 uart2 transmit interrupt control register s2tic ?000 0050 16 uart2 receive interrupt control register s2ric ?000 0051 16 uart0 transmit interrupt control register s0tic ?000 0052 16 uart0 receive interrupt control register s0ric ?000 0053 16 uart1 transmit interrupt control register s1tic ?000 0054 16 uart1 receive interrupt control register s1ric ?000 0055 16 timer a0 interrupt control register ta0ic ?000 0056 16 timer a1 interrupt control register ta1ic ?000 0057 16 timer a2 interrupt control register ta2ic ?000 0058 16 timer a3 interrupt control register ta3ic ?000 0059 16 timer a4 interrupt control register ta4ic ?000 005a 16 timer b0 interrupt control register tb0ic ?000 005b 16 timer b1 interrupt control register tb1ic ?000 005c 16 reset interrupt control register rstic ?000 005d 16 int0 interrupt control register int0ic 00?000 005e 16 int1 interrupt control register int1ic 00?000 005f 16 usb function interrupt control register usbfic ?000 - - - 0300 16 usb address register usba 00 16 0301 16 usb power management register usbpm 00 16 0302 16 usb interrupt status register 1 usbis1 00 16 0303 16 usb interrupt status register 2 usbis2 00 16 0304 16 usb interrupt enable register 1 usber1 ff 16 0305 16 usb interrupt enable register 2 usber2 33 16 0306 16 usb frame number register low usbsofl 00 16 0307 16 usb frame number register high usbsofh 00 16 0308 16 usb iso control register usbisoc 0 0 0309 16 usb dma0 source register usbsar0 00 16 030a 16 usb dma1 source register usbsar1 00 16 030b 16 usb endpoint enable usbepen ? 0 0 0 030c 16 030d 16 030e 16 030f 16 0310 16 usb reserved 0311 16 usb ep 0 control/status register 00 16 0312 16 usb reserved 0313 16 usb ep 0 max packet size register 08 16 0314 16 usb reserved 0315 16 usb ep 0 out write count 00 16 0316 16 usb reserved 0317 16 usb reserved 0318 16 usb reserved 0319 16 usb ep 1 in control/status register 00 16 031a 16 usb ep 1 out control/status register 00 16 031b 16 usb ep 1 in max packet size register 00 16 031c 16 usb ep 1 out max packet size register 00 16 031d 16 usb ep 1 out write count 00 16 031e 16 usb reserved 031f 16 usb reserved address register name acronym value after reset
confidential 18 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change sfr map 0320 16 usb reserved 0321 16 usb ep 2 in control/status register 00 16 0322 16 usb ep 2 out control/status register 00 16 0323 16 usb ep 2 in max packet size register 00 16 0324 16 usb ep 2 out max packet size register 00 16 0325 16 usb ep 2 out write count 00 16 0326 16 usb reserved 0327 16 usb reserved 0328 16 usb reserved 0329 16 usb ep 3 in control/status register 00 16 032a 16 usb ep 3 out control/status register 00 16 032b 16 usb ep 3 in max packet size register 00 16 032c 16 usb ep 3 out max packet size register 00 16 032d 16 usb ep 3 out write count 00 16 032e 16 usb reserved 00 16 032f 16 usb reserved 0330 16 usb reserved 0331 16 usb ep 4 in control/status register 00 16 0332 16 usb ep 4 out control/status register 00 16 0333 16 usb ep 4 in max packet size register 00 16 0334 16 usb ep 4 out max packet size register 00 16 0335 16 usb ep 4 out write count 00 16 0336 16 usb reserved 0337 16 usb reserved 0338 16 usb ep 0 fifo 0339 16 usb ep 1 fifo 033a 16 usb ep 2 fifo 033b 16 usb ep 3 fifo 033c 16 usb ep 4 fifo 033d 16 reserved 033e 16 reserved 033f 16 reserved 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 address register name acronym value after reset
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 19 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change sfr map 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 reserved 0378 16 uart2 transmit / receive mode register u2mr 00 16 0379 16 uart2 bit rate generator u2brg 037a 16 uart2 transmit buffer register u2tb 037b 16 037c 16 uart2 transmit /receive control register 0 u2c0 08 16 037d 16 uart2 transmit / receive control register 1 u2c1 02 16 037e 16 uart2 receive buffer register u2rb 037f 16 0380 16 count start ?ag tabsr 00 16 0381 16 clock prescaler reset ?ag cpsrf 0 0382 16 one-shot start ?ag onsf 0 0 00000 0383 16 trigger select register trgsr 00 16 0384 16 up-down ?ag udf 00 16 0385 16 0386 16 timer a0 ta0 0387 16 0388 16 timer a1 ta1 0389 16 038a 16 timer a2 ta2 038b 16 038c 16 timer a3 ta3 038d 16 038e 16 timer a4 ta4 038f 16 0390 16 timer b0 tb0 0391 16 0392 16 timer b1 tb1 0393 16 0394 16 timer b2 tb2 0395 16 0396 16 timer a0 mode register ta0mr 00 16 0397 16 timer a1 mode register ta1mr 00 16 0398 16 timer a2 mode register ta2mr 00 16 0399 16 timer a3 mode register ta3mr 00 16 039a 16 timer a4 mode register ta4mr 00 16 039b 16 timer b0 mode register tb0mr 0 0 ? 0000 039c 16 timer b1 mode register tb1mr 0 0 ? 0000 039d 16 timer b2 mode register tb2mr 0 0 ? 0000 039e 16 039f 16 03a0 16 uart0 transmit / receive mode register u0mr 00 16 03a1 16 uart0 bit rate generator u0brg 03a2 16 uart0 transmit buffer register u0tb 03a3 16 03a4 16 uart0 transmit / receive control register 0 u0c0 08 16 03a5 16 uart0 transmit / receive control register 1 u0c1 02 16 03a6 16 uart0 receive buffer register u0rb 03a7 16 03a8 16 uart1 transmit / receive mode register u1mr 00 16 03a9 16 uart1 bit rate generator u1brg 03aa 16 uart1 transmit buffer register u1tb 03ab 16 03ac 16 uart1 transmit / receive control register 0 u1c0 08 16 03ad 16 uart1 transmit / receive control register 1 u1c1 02 16 03ae 16 uart1 receive buffer register u1rb 03af 16 address register name acronym value after reset
confidential 20 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change sfr map 03b0 16 uart transmit / receive control register 2 ucon 0000000 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 dma0 cause select register dm0sl 00 16 03b9 16 03ba 16 dma1 cause select register dm1sl 00 16 03bb 16 03bc 16 crc data register crcd 03bd 16 03be 16 crc input register crcin 03bf 16 03c0 16 a-d register 0 ad0 03c1 16 03c2 16 a-d register 1 ad1 03c3 16 03c4 16 a-d register 2 ad2 03c5 16 03c6 16 a-d register 3 ad3 03c7 16 03c8 16 a-d register 4 ad4 03c9 16 03ca 16 a-d register 5 ad5 03cb 16 03cc 16 a-d register 6 ad6 03cd 16 03ce 16 a-d register 7 ad7 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 a-d control register 2 adcon2 0 03d5 16 03d6 16 a-d control register 0 adcon0 0 0 0 0 0 ? ? ? 03d7 16 a-d conrol register 1 adcon1 00 16 03d8 16 03d9 16 03da 16 03db 16 frequency synthesizer clock control fsccr 00 16 03dc 16 frequency synthesizer control fsc 60 16 03dd 16 frequency synthesizer multiplier control fsm ff 16 03de 16 frequency synthesizer prescaler control fsp ff 16 03df 16 frequency synthesizer divider fsd ff 16 03e0 16 port p0 p0 03e1 16 port p1 p1 03e2 16 port p0 direction register pd0 00 16 03e3 16 port p1 direction register pd1 00 16 03e4 16 port p2 p2 03e5 16 port p3 p3 03e6 16 port p2 direction register pd2 00 16 03e7 16 port p3 direction register pd3 00 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 port p6 p6 03ed 16 port p7 p7 03ee 16 port p6 direction register pd6 00 16 03ef 16 port p7 direction register pd7 00 16 address register name acronym value after reset
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 21 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change sfr map 03f0 16 port p8 p8 03f1 16 03f2 16 port p8 direction register pd8 00 16 03f3 16 03f4 16 port p10 p10 03f5 16 03f6 16 port p10 direction register pd10 00 16 03f7 16 03f8 16 03f9 16 03fa 16 p2 drive capacity p2dr 03fb 16 pwm drive capacity pwmdr 03fc 16 pull-up control register 0 pur0 00 16 03fd 16 pull-up control register 1 pur1 00 16 03fe 16 03ff 16 address register name acronym value after reset
confidential 22 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change reset 2.5 reset there are two types of resets: hardware and software. in both cases, operation is the same after the reset. (see software reset for further details regarding software resets.) this section explains on hardware resets. note: the usb peripheral is only reset during a hardware reset; software resets do not affect the usb peripheral. when the supply voltage is within the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2vcc max.) for at least 20 xin cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 9 shows an example of a reset circuit. figure 10 shows the reset sequence. . figure 9: reset circuit figure 10: reset sequence reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v example when f(x in ) = 10mhz and v cc = 5v . bclk address microprocessor mode byte = ? content of reset vector single chip mode bclk 24cycles ffffe 16 x in reset ffffc 16 at least 20 cycles are needed
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 23 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change software reset when the reset pin level = l, all ports change to input mode (floating.) table 3 shows the status of the other pins while the reset pin level is l. 2.6 software reset writing "1" to bit 3 of processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. 2.7 clock-generating circuit the clock-generating circuit contains one oscillator circuit that supplies the operating clock sources to the cpu and internal peripheral units.example of oscillator circuit figure 11 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figure 11 vary with each oscillator used. use circuit constant values recommended by the oscillator manfacturer. figure 11: examples of clock source table 3: main clock-generating circuits functions main clock-generating circuit use of clock ? cpus operating clock source ? internal peripheral units operating clock source usable oscillator ceramic or crystal oscillator pins to connect oscillator xin, xout oscillation stop/restart function available oscillator status immediately after reset oscillating microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable.
confidential 24 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change clock control 2.8 clock control figure 12 shows the block diagram of the clock-generating circuit. figure 12: clock-generating circuit the following paragraphs describes the clocks generated by the clock-generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the internal clock f . the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the xout pin can be reduced using the xin-xout drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the xout pin reduces the power dissipation. this bit defaults to 1 when shifting to stop mode and after a reset. (2) internal clock f the internal clock f is the clock that drives the cpu, and is either the main clock or is derived by di- viding the main clock by 2, 4, 8, or 16. the internal clock f is derived by dividing the main clock by 8 after a reset. cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wait instruction cm02 q s r nmi interrupt request level judgment output reset software reset f ad divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider c b b 1/2 c f 1 f 32 sio2 f 8 sio2 f 1 sio2 f 8 f 32 f x out main clock cm10 ?? write signal q s r x in frequency multiplier f usb (48mhz) fsccr0=1 fsccr0=0 internal clock f
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 25 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change clock control when shifting to stop mode, the main clock division select bit (bit 6 at 0006 16 ) is set to 1. (3) peripheral function clock ? f1, f8, f32 the clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral func- tion clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. ? fad this clock has the same frequency as the main clock and is used for a-d conversion. (4) clock output in single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 16 ) enable f8 or f32 to be output from the p37/clkout pin. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1, the output of f8 and f32 stops when a wait instruction is executed. figure 13 shows the system clock control registers 0 and 1.
confidential 26 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change clock control figure 13: system clock control registers 0 and 1 system clock control register 0 (note 1) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shiffing to stop mode. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? when main clock oscillation is operating by itself, set system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shiffing to stop mode. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is ?? if ?? division mode is fixed at 8. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit 0 : clock on 1 : all clocks off (stop mode) cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r cm16 cm17 reserved bit always set to ? reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to ? reserved bit always set to ? 0 0 symbol address when reset cm0 0006 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p3 7 0 1 : not used 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm01 cm02 cm00 clock output function select bit wait peripheral function clock stop bit 0 : do not stop f 1 , f 8 , f 32 in wait mode 1 : stop f 1 , f 8 , f 32 in wait mode w r cm05 cm06 main clock (x in -x out ) stop bit (note 3) (note 4) 0 : on 1 : off main clock division select bit 0 (note 2) 0 : cm16 and cm17 valid 1 : division by 8 mode reserved bit always set to "0" reserved bit always set to "0" reserved bit always set to "0"
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 27 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change stop mode 2.9 stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcomputer enters stop mode. in stop mode, the content of the internal ram is retained provided that vcc remains above 2v. because the oscillation of internal clock f , f1 to f32, and fad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a operates, provided that the event counter mode is set to an external pulse, and uarti(i = 0 to 2) functions provided an external clock is selected. table 4 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. when shifting to stop mode, the main clock division select bit 0 (bit 6 at 0006 16 ) is set to 1. table 4: port status during stop mode pin single-chip mode port retains status before stop mode clkout when f8, f32 selected retains status before stop mode
confidential 28 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change wait mode 2.10 wait mode when a wait instruction is executed, the internal clock f stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the internal clock f and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 5 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts using as internal clock f the clock that had been selected when the wait instruction was executed. status transition of internal clock f power dissipation can be reduced and low-voltage operation achieved by changing the count source for internal clock f . table 6 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. after a reset, operation defaults to division by 8 mode. when shifting to stop mode, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. the following shows the operational modes of internal clock (1) division by 2 mode the main clock is divided by 2 to obtain the internal clock f . (2) division by 4 mode the main clock is divided by 4 to obtain the internal clock f . (3) division by 8 mode the main clock is divided by 8 to obtain the internal clock f . note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. (4) division by 16 mode the main clock is divided by 16 to obtain the internal clock f . (5) no-division mode the main clock is used as internal clock table 5: port status during wait mode pin single-chip mode port retains status before stop mode clkout when f8, f32 selected does not stop when the wait peripheral function clock stop bit is 0 when the wait peripheral function clock stop bit is 0, the status immediately prior to entering wait mode is maintained.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 29 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change protection table 6: operating modes dictated by settings of system clock control registers 0 and 1 2.11 protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. .figure 14 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control register 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ) and frequency synthesizer registers can only be changed when the respective bit in the protect register is set to 1. the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. figure 14: protect register cm17 cm16 cm06 cm05 cm04 operating mode of internal clock 0100inv alid division by 2 mode 1000inv alid division by 4 mode invalid invalid 1 0 invalid division by 8 mode 1100inv alid division by 16 mode 0000inv alid no-division mode protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) and frequency synthesizer registers (addresses 03db 16 and 03df 16 ) w r nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. reserved bit must always be set to "0"
confidential 30 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change interrupts 2.12 interrupts table 7 and table 8 show the interrupt sources and vector table addresses. when an interrupt is received, the program is executed from the address shown by the respective interrupt vector. the vector table addresses for the interrupts in table 7 are fixed (interrupt vector addresses). these interrupts are not affected by the interrupt enable flag (i flag) (non-maskable interrupts). the vector table addresses for the interrupts in table 8 are variable, being determined as relative to the fixed address in the interrupt table register (intb). these interrupts can be enabled or disabled using the interrupt enable flag (i flag) (maskable interrupts). 64 vectors can be set in the interrupt table register (intb). any of software interrupts 0 to 63 can be assigned to each vector. by using the int instruction to specify a software interrupt number, the program can be executed starting at the address indicated by the respective vector. the brk instruction interrupt has interrupt vectors in both the fixed vector address and variable vector address. when the contents of fffe4 16 through fffe7 16 are all ff 16 , the program is executed from the address shown in the brk instruction interrupt vector in the variable vector address. specify the starting address of the interrupt program in the interrupt vector. figure 15 shows the format for specifying the address. note: interrupts used for debugging purposes only figure 15: format for specifying interrupt vector addresses table 7: interrupt vectors (?xed interrupt vector addresses) interrupt source vector table addresses address(l) to address(h) remarks unde?ned instruction fffdc 16 to fffdf 16 interrupt on und instruction over?ow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector is ?lled with ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to fff3 16 dbc (note) ffff4 16 to ffff7 16 do not use nmi ffff8 16 to ffffb 16 external interrupt by nmi pin reset ffffc 16 to fffff 16 aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa 0 0 0 0 high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 31 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change interrupts note 1:address relative to address in interrupt table base address register (intb) table 8: interrupt vectors (variable interrupt vector addresses) software interrupt number vector table addresses address(l) to address(h) interrupt source remarks software interrupt number 0 +0 to +3 (note 1) brk instruction cannot be masked by i ?ag software interrupt number 4 +16 to +19 usb suspend software inturrupt number 6 +24 to +27 resume software inturrupt nubmer 7 +28 to +31 usb start of frame software interrupt number 10 +40 to +43 bus collision detection software interrupt number 11 +44 to +47 dma0 software interrupt number 12 +48 to +51 dma1 software interrupt number 13 +52 to +55 key input interrupt software interrupt number 14 +56 to +59 a-d software interrupt number 15 +60 to +63 uart2 transmit software interrupt number 16 +64 to +67 uart2 receive software interrupt number 17 +68 to +71 uart0 transmit software interrupt number 18 +72 to +75 uart0 receive software interrupt number 19 +76 to +79 uart1 transmit software interrupt number 20 +80 to +83 uart1 receive software interrupt number 21 +84 to +87 timer a0 software interrupt number 22 +88 to +91 timer a1 software interrupt number 23 +92 to +95 timer a2 software interrupt number 24 +96 to +99 timer a3 software interrupt number 25 +100 to +103 timer a4 software interrupt number 26 +104 to +107 timer b0 software interrupt number 27 +108 to +111 timer b1 software interrupt number 28 +112 to +115 usb reset software interrupt number 29 +116 to +119 int0 software interrupt number 30 +120 to +123 int1 software interrupt number 31 +124 to +127 usb function software interrupt number 32 to software interrupt number 63 +252 to +255 software interrupt cannot be masked by i ?ag
confidential 32 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change interrupts (1) interrupt control registers peripheral i/o interrupts have their own interrupt control registers. table 9 shows the addresses of the interrupt control registers. figure 16 shows the interrupt control registers. the interrupt request bit is set by hardware to 0 when an interrupt request is received. the interrupt request bit can also be set by software to 0. (do not set to 1.) int0 and int1 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. (other interrupts are described elsewhere.) an interrupt must first be enabled before it can be used to cancel stop mode. table 9: addresses in interrupt control register interrupt control register symbol name address interrupt control register symbol name address suspend-interrupt suspic 0044 16 uart1 receive s1ric 0054 16 resume interrupt rsmic 0046 16 timer a0 ta0ic 0055 16 usb start of frame sofic 0047 16 timer a1 ta1ic 0056 16 bus collision detection bcnic 004a 16 timer a2 ta2ic 0057 16 dma0 dm0ic 004b 16 timer a3 ta3ic 0058 16 dma1 dm1ic 004c 16 timer a4 ta4ic 0059 16 key input interrupt kupic 004d 16 timer b0 tb0ic 005a 16 a-d adic 004e 16 timer b1 tb1ic 005b 16 uart2 transmit s2tic 004f 16 reset interrupt rstic 005c 16 uart2 receive s2ric 0050 16 int0 int0ic 005d 16 uart0 transmit s0tic 0051 16 int1 int1ic 005e 16 uart0 receive s0ric 0052 16 usb function usbfic 005f 16 uart1 transmit s1tic 0053 16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 33 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change interrupts figure 16: interrupt control registers symbol address when reset intiic(i=3) 005d 16, 005e 16 xx00x000 2 sofic 0047 16 xx00x000 2 interrupt control register symbol address when reset suspic 0044 16 xx00x000 2 rsmic 0046 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dmiic(i=0, 1) 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0 to 2) 0051 16 , 0053 16 , 004f 16 xxxxx000 2 siric(i=0 to 2) 0052 16 , 0054 16 , 0050 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005b 16 xxxxx000 2 rstic 005c 16 xxxxx000 2 usbfic 005f 16 xxxxx000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name function bit symbol w r ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. (note) note: this bit can only be reset (= 0), but cannot be set ( = 1). 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ilvl0 ir pol nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to ? ilvl1 ilvl2 note 1: this bit can only be reset (= 0), but cannot be set (= 1). note 2: for sofic, (address 0047 16 ) , a "0" should always be written. (note 1) 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 (note 2)
confidential 34 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change interrupts (2) interrupt priority the order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. the interrupt priority levels determined by hardware are reset > nmi > dbc > wacthdog timer > pe- ripheral i/o interrupts > single-step > address matching interrupt. the interrupt priority levels determined by software are set in the interrupt control registers. figure 17 shows the circuit that judges the interrupt hardware priority level. when two or more inter- rupts are generated simultaneously, the interrupt with the higher software priority is selected. howev- er, if the interrupts have the same software priority level, the interrupt is selected according to the hardware priority set in the circuit. the selected interrupt is accepted only when the priority level is higher than the processor interrupt priority level (ipl) in the flag register (flg) and the interrupt enable flag (i flag) is 1. note that the reset, nmi, dbc, watchdog timer, single-step, address-match, brk instruction, overflow, and unde- fined instruction interrupts are accepted regardless of the interrupt enable flag (i flag).
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 35 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change interrupts figure 17: interrupt resolution circuit usb function timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception uart2 reception a-d conversion dma1 bus collision detection timer a0 uart1 transmission uart0 transmission uart2 transmission key input interrupt dma0 processor interrupt priority level (ipl) interrupt enable flag (i flag) usb sof watchdog timer reset dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) address match int1 int0
confidential 36 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change nmi interrupt (3) flag changes when an interrupt request is received, the stack pointer select flag (u flag) changes to 0 and the flag register (flg) and program counter (pc) are saved to the stack area indicated by the interrupt stack pointer (isp). thereafter, the interrupt enable flag (i flag) and debug flag (d flag) change to 0 and the processor interrupt priority level (ipl) at the flag register (flg) is replaced by the priority level of the received interrupt. however, when interrupt requests are received for software interrupts 32 to 63, the flag register (flg) and program counter (pc) are saved to the stack shown by the stack pointer select flag (u flag) at the time the interrupt was received. the stack pointer select flag (u flag) does not change. the value of the processor interrupt priority level (ipl) in the flag register (flg) differs in the case of reset, nmi, dbc, watchdog timer, single-step, address-match, brk instruction, overflow, and undefined instruction interrupts. table 10 shows how the ipl changes when interrupt requests are received. 2.13 nmi interrupt an n m i interrupt is generated when the input to the p85/ n m i pin changes from h to l. the n m i interrupt is a non-maskable external interrupt. the pin level can be checked in the port p85 register (bit 5 at address 03f0 16 ). this pin cannot be used as a normal port input. notes: (1) when not intending to use the nmi function, be sure to connect the nmi pin to vcc. because the nmi interrupt is non-maskable, it cannot be disabled. (2) when the nmi pin input is l, do not set the microcomputer in stop mode or wait mode. the nmi interrupt is triggered by the falling edge, so the l level does not need to be maintained longer than necessary. table 10: change of ipl state when interrupt request are accepted interrupt change of ipl reset level 0 ( 000 2 ) is set nmi level 7 ( 111 2 ) is set dbc does not change watchdog timer level 7 ( 111 2 ) is set single step does not change address match does not change software interrupt does not change
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 37 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change key-input interrupt 2.14 key-input interrupt if the direction register of any of pin of port0 or port1 is set for input and a falling edge is input to that port, a key-input interrupt is generated. a key-input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. figure 18 shows the block diagram of the key-input interrupt. figure 18: block diagram of key input interrupt (1) enabling/disabling the key-input interrupt the key-input interrupt can be enabled and disabled using the key-input interrupt register (004d 16 ). the key-input interrupt is affected by the interrupt priority level (ipl) and the interrupt enable ?ag (i ?ag). (2) occurrence timing of the key-input interrupt with key-input interrupt acceptance enabled, ports p0 and p1, which are set to input, become key-input interrupt pins ( ki0 through ki15). a key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. at this moment, the level of other key-input interrupt pins must be h. no interrupt occurs when the level of any other key- input interrupt pins is l. (3) how to determine a key-input interrupt a key-input interrupt occurs when a falling edge is input to one of 16 pins, but each pin has the same vector address. therefore, read the input level of ports p0 and p1 in the key-input interrupt routine to determine the interrupted pin. (4) registers related to the key-input interrupt figure 19 shows the memory map of key-input interrupt-related registers. figure 19: memory map of key-input interrupt-related registers p1 i /ki j port px i pull-up select bit port p1 i direction register pull-up transistor interrupt control circuit key input interrupt control register (address 004d 16 ) key input interrupt request p0 i /ki j port p0 i pull-up select bit port p0 i direction register pull-up transistor i=0~7; j=0~7 i=0~7; j=8~15 kio 0 kio 15 key-input interrupt control register (kupic) port 0 (p0) port 1 (p1) port 0 direction register port 1 direction register pull-up control register 0 pull- up control register 1 04d 16 3e0 16 3e1 16 3e2 16 3e3 16 3fc 16 3fd 16
confidential 38 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change address match interrupt 2.15 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). figure 20 shows the address match interrupt-related registers. figure 20: address match interrupt-related registers bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaaa a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) a a a a a a a a a a
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 39 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change watchdog timer 2.16 watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter that decrements using the clock derived by dividing the internal clock f using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or 128). table 11 shows the periodic table for the watchdog timer . note: error is generated by the prescaler the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 21 shows the block diagram of the watchdog timer. figure 22 shows the watchdog timer-related registers. figure 21: block diagram of watchdog timer table 11: watchdog timer periodic table (xin = 10mhz) cm06 cm17 cm16 internal clock f wdc7 period 0 0 0 10mhz 0 approx. 52.4ms (note) 1 approx. 419.2ms (note) 0 0 1 5mhz 0 approx. 104.9ms (note) 1 approx. 838.8ms (note) 0 1 0 2.5mhz 0 approx. 209.7ms (note) 1 approx. 1.68s (note) 0 1 1 0.625mhz 0 approx. 838.8ms (note) 1 approx. 6.71s (note) 1 invalid invalid 1.25mhz 0 approx. 419.2ms (note) 1 approx. 3.35s (note) 1/16 1/128 watchdog timer watchdog timer interrupt request set to 7fff 16 wdc7 = 0 wdc7 = 1 reset write to the watchdog timer start register (address 000e 16 ) hold internal clock f
confidential 40 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change watchdog timer figure 22: watchdog timer control and start registers watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to 0 must always be set to 0 0 0 a a a a a a a a
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 41 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change frequency synthesizer circuit 2.17 frequency synthesizer circuit the frequency synthesizer circuit generates a 48mhz clock needed by the usb block and a clock f syn that are both a multiple of the external input reference clock f in . a block diagram of the circuit is shown in figure 23. figure 23: frequency synthesizer circuit the frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro, and five registers, namely fsp, fsm, fsc, fsd, and fsccr. clock f in is prescaled down using fsp to generate f pin .f pin is multiplied using fsm to generate an f vco clock which is then divided using fsd to produce the clock f syn . the f vco clock is optimized for 48 mhz operation and is buffered and sent out of the frequency synthesizer block as signal f usb . this signal is used by the usb block. (1) prescaler clock f pin is a divided down version of clock f in (see figure 24). the relationship between f pin and the clock input to the prescaler (f in ) is as follows: ?f pin = f in / 2(n+1) where n is a decimal number between 0 and 254. setting fsp to 255 disables the prescaler and f pin = f in . figure 24: frequency synthesizer prescaler register (fsp) fsp data bus fsm fsc fsd 03de 03dd 03dc 03df frequency multiplier frequency divider 8 bit ls 8 bit f in f vco f syn f usb prescaler 8 bit f pin fsccr fsccr0 03db f in /2( n +1)=f pin f pin fsp f in dec(n) hex(n) 12 mhz 255 ff 12.00 mhz 1 mhz 5 05 12.00 mhz 2 mhz 2 02 12.00 mhz 3 mhz 1 01 12.00 mhz 6 mhz 0 00 12.00 mhz msb 7 lsb 0 bit 6 bit 1 bit 0 bit 2 bit 5 bit 4 bit 3 bit 7 access: r/w address: 03de 16 reset: ff 16
confidential 42 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change frequency synthesizer circuit (2) multiplier clock f vco is a multiplied up version of clock f pin (see figure 25). the relationship between f vco and the clock input to the multiplier (f pin ) from the prescaler is as follows: ?f vco = f pin x 2( n +1) where n is the decimal equivalent of the value loaded in fsm. setting fsm to 255 disables the multiplier and f vco = f pin . note: n must be chosen such that f vco equals 48 mhz. figure 25: frequency synthesizer multiply register (fsm) (3) divider clock f syn is a divided down version of clock f vco (see figure 26). the relationship between f syn and the clock input to the divider (f vco ) from the multiplier is as follows: ?f syn = f vco / 2(m+1) where m is the decimal equivalent of the value loaded in fsd. setting fsd to 255 disables the divider and f syn = f vco . figure 26: frequency synthesizer divide register (fsd) f pin x2( n +1)=f vco f pin fsm f vco dec(n) hex(n) 320 khz 74 4a 48.00 mhz 2 mhz 11 0b 48.00 mhz 4 mhz 5 05 48.00 mhz 6 mhz 3 03 48.00 mhz 12 mhz 1 01 48.00 mhz msb 7 lsb 0 bit 6 bit 1 bit 0 bit 2 bit 5 bit 4 bit 3 bit 7 address: 03dd 16 access: r/w reset: ff 16 f vco /2(m+1) = f syn f vco fsd f syn dec(m) hex(m) 48.00 mhz 1 01 12.00 mhz 48.00 mhz 127 7f 187.50 khz msb 7 lsb 0 bit 6 bit 1 bit 0 address: 03df 16 access: r/w reset: ff 16 bit 2 bit 5 bit 4 bit 3 bit 7
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 43 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change frequency synthesizer circuit the fsc0 bit in the fsc control register enables the frequency synthesizer block. when disabled (fsc0 = "0"), f vco is held at either a high or low state. when the frequency synthesizer control bit is active (fsc0 = "1"), a lock status (ls = "1") indicates that f syn and f vco are the correct frequency. the ls and fsco control bits in the fsc control register are shown in figure 27. when using the frequency synthesizer, a low-pass filter must be connected to the lpf pin. once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. this is done to allow the output to stabilize. it is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. the cpu and usb clock sources are selecxted via the frequency synthesizer clock control register (fsccr). see figure 28 figure 27: frequency synthesizer control register (fsc) figure 28: frequency synthesizer clock control register (fsccr) fse frequency synthesizer enable - bit 0 0: disabled 1: enabled vco1,0 vco gain control - bits 2,1 bit 2 bit 1 0 0: lowest gain (recommended) 0 1: low gain 1 0: high gain 1 1: highest gain bits 4,3 reserved (read/write 0) chg1,0 lpf current control - bits 6,5 bit 6 bit 5 0 0: disabled 0 1: low current 1 0: intermediate current (recommended) 1 1: high current ls frequency synthesizer lock status (read only; write 0) - bit 7 0: unlocked 1: locked msb 7 lsb 0 chg0 vco0 fse address: 03dc 16 access: r/w reset: 60 16 vco1 ls chg1 reserved reserved fsccr0 clock source selection- bit 0 0: xin 1: f syn fsccr1 usb clock source selection- bit 1 0: f usb = f vco 1: f usb = f xin bits 7-2 reserved (read/write 0) msb 7 lsb 0 fsccr1 fsccr0 address: 03db 16 access: r/w reset: 00 16 reserved reserved reserved reserved reserved reserved
confidential 44 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus 2.18 universal serial bus the universal serial bus (usb) has the following features: ? complete usb speci?cation (version 1.0) compatibility ? error-handling capabilities ? fifos: ? endpoint 0: in 32-byte out 32-byte ? endpoint 1: in 128-byte out 128-byte ? endpoint 2: in 32-byte out 32-byte ? endpoint 3: in 32-byte out 32-byte ? endpoint 4: in 32-byte out 32-byte ? nine endpoints - control endpoint (endpoin t 0 - bidirectional) plus four in and four out endpoints ? complete device con?guration ? supports all device commands ? supports full-speed functions ? support of all usb transfer types: ? isochronous ? bulk ? control ? interrupt ? suspend/resume operation ? on-chip usb transceiver with voltage converter ? start-of-frame interrupt and output pin usb function control unit (usb fcu) the implementation of the usb by this device is accomplished chiefly through the devices usb function control unit (see figure 29). the function control units overall purpose is to handle the usb packet protocol layer. the function control unit notifies the mcu that a valid token has been received. when this occurs, the data portion of the token is routed to the appropriate fifo. the mcu transfers the data to, or from, the host by interacting with that endpoints fifo and csr register. the usb function control unit is composed of five sections: ? serial interface engine (sie) ? generic function interface (gfi) ? serial engine interface unit (siu) ? microcontroller interface (mci) ? usb transceiver serial interface engine the sie interfaces to the usb serial data and handles deserialization/serialization of data, nrzi encoding decoding, clock extraction, crc generation and checking, bit stuffing, and other specifications pertaining to the usb protocol such as handling inter-packet time-outs and packet id (pid) decoding.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 45 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus generic function interface the gfi handles the all usb standard requests from the host through the control endpoint (endpoint zero), handles bulk, isochronous and interrupt transfers through endpoints 1-4. the gfi handles read pointer rever- sal for re-transmit the current data set; write pointer reversal for reception of the last data set; data toggle syn- chronization. serial engine interface unit the siu block decodes the address and endpoint fields from the usb host. microcontroller interface the mci block handles the microcontroller interface and performs address decoding and synchronization of control signals. usb transceiver the usb transceiver, designed to interface with the physical layer of the usb, is compliant with the usb specification (version 1.0) for high speed devices. it consists of two 6-ohm drivers, a receiver, and schmitt triggers for single-ended receive signals. the transceiver also includes a voltage converter. the voltage converter can supply 3.0 - 3.6v to the trans- mitter when the rest of the chip (cpu, usb fcu) operates at 4.15 - 5.25v. to enable the voltage converter, set bit 4 of the usb control register (usbc) to a 1. to disable the voltage converter, set bit 4 of the usbc to a 0. refer to section 5.5 usb transceiver for more detailed information. figure 29: usb function control unit block diagram usb interrupts there are two types of usb interrupts in this device: the first type is the usb function (including overrun/un- derrun usb, reset, suspend and resume) interrupt, used to control the flow of data and usb power control; the second type is start-of-frame (sof) interrupt, used to monitor the transfer of isochronous (iso) data. usb function interrupt endpoints 1-4 each have two interrupt status bits associated with them to control the data transfer or to report a stall/under_run/over_run condition. the epx_out_int bit is set when the usb fcu successfully receives a packet of data, or sets the force_stall bit, or the over_run bit of the endpoint x out csr. the epx_in_int bit is set when the usb fcu successfully sends a packet of data, or sets the under_run bit of the endpoint x in csr. endpoint 0 - the control endpoint - has one interrupt status bit associated with it to control the data transfer or report a stall condition. the ep0_int is set when the usb fcu successfully receives/sends a packet of data, or sets the setup_end bit, the force_stall bit, or clears the data_end bit in the endpoint 0 in csr. each endpoint interrupt is enabled by setting the corresponding bit in the usb interrupt enable register 1 and 2. the usb interrupt status register 1 and 2 are used to indicate cpu mci siu gfi fifos sie transceiver d + d -
confidential 46 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus pending interrupts for a given endpoint. the usb fcu sets the interrupt status bits. the cpu writes a 1 to clear the corresponding status bit. by writing back the same value it read, the cpu will clear all the existing interrupts. the cpu must read then write both status registers, writing status register 1 first and status register 2 second to guarantee proper operation. the suspend interrupt status bit is set if a usb suspend signal is received. if the device is in suspend mode, the resume interrupt status bit is set when a usb resume signal is received. there is a single interrupt enable bit for both of suspend and resume interrupts (bit 7 of the interrupt enable register 2). the usb reset interrupt status bit is set if a usb reset signal is received. when this bit is set, all usb internal registers is reset to their default values except this bit itself. this bit is cleared by the cpu writing a 0 to it. when the cpu detects a usb reset interrupt, it needs to re-initialize the usb block in order to accept packets from the host. the over/underrun status bit is set (applicable to endpoints used for isochronous data transfer), when an overrun condition occurs in an endpoint (cpu is too slow to unload the data from the fifo), or when an un- derrun condition occurs in an endpoint (cpu is too slow to load the data to the fifo). the usb function interrupt (sum of all individual function interrupts) is enabled by setting the corresponding bit in the interrupt control register of the interrupt control unit. usb sof interrupt the usb sof (start-of-frame) interrupt is used to control the transfer of isochronous data. the usb fcu generates a start-of-frame interrupt when a start-of-frame packet is received. the usb sof interrupt is en- abled by setting the corresponding bit in the interrupt control register of the interrupt control unit. usb endpoint fifos the usb fcu has an in (transmit) fifo and an out (receive) fifo for each endpoint. both fifos support up to two separate data sets of variable size (except endpoint 0), and provide the ability of back-to-back trans- mission and reception. throughout this specification, the terms in fifo and out fifo refer these fifos associated with the current endpoint. in the event of a bad transmission/reception, the usb fcu handles all the read/write pointer reversal and data set management tasks when it is applicable. in (transmit) fifos the cpu/dma writes data to the endpoints in fifo location specified by the fifo write pointer, which auto- matically increments by "1" after a write. endpoint 0 in fifo operation: the cpu writes a 1 to the in_pkt_rdy bit after it finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit after the packet is successfully transmitted to the host (ack is received from the host) or the setup_end bit of the in csr is set to a 1. endpoint 1-4 in fifo operation when auto_set (bit 7 of in csr) = 0: maxp > half of the in fifo size: the cpu writes a 1 to in_pkt_rdy bit after the cpu/dmac finishes writ- ing a packet of data to the in fifo. the usb fcu clears tx_not_empty bit after the packet is successfully transmitted to the host (ack is received from the host). the cpu should only write data to the in fifo if the tx_not_empty bit of the in csr is a 0. maxp <= half of the in fifo size: the cpu writes a 1 to the in_pkt_rdy bit after the cpu/dmac finishes writing a packet of data to the in fifo. if only one packet of data is the fifo tx_not_empty bit gets set to a 1 and the in_pkt_rdy bit gets clear to a 0. if two packets of data in the fifo, then the tx_not_empty bit gets set to a 1 and the in_pkt_rdy bit stays as a 1 (the fifo can hold up to two data packets at the same time in this configuration, for back-to-back transmission). the cpu should only write data to the in fifo if the in_pkt_rdy bit of the in csr is a 0. endpoint 1-4 in fifo operation when auto_set (bit 7 of in csr) = 1: maxp > half of the in fifo size: when the number of bytes of data equal to the maxp (maximum packet size) is written to the in fifo by the cpu/dmac, the usb fcu sets the tx_not_empty bit to a 1 auto- matically. the usb fcu clears the tx_not_empty bit after the packet is successfully transmitted to the host (ack is received from the host). the cpu should only write data to the in fifo if the tx_not_empty bit of the in csr is a 0.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 47 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus maxp <= half of the in fifo size: when the number of bytes of data equal to the maxp (maximum packet size) is written to the in fifo by the cpu/dmac, the usb fcu sets the tx_not_empty/in_pkt_rdy bits to a 1 automatically depends on fifo status. if only one packet of data is the fifo tx_not_empty bit gets set to a 1 and the in_pkt_rdy bit get clear to a 0. if two packets of data in the fifo then both the tx_not_empty bit gets set to a 1 and the in_pkt_rdy bit gets set to a 1 (the fifo can hold up to two data packets at the same time in this configuration, for back-to-back transmission). the cpu should only write data to the in fifo if the in_pkt_rdy bit of the in csr is a 0. a software or a hardware flush acts as if a packet is being successfully transmitted out to the host. if there is one packet in the in fifo, a flush causes the in fifo to be empty, if there are two packets in the in fifo, a flush causes the older packet to be flushed out from the in fifo. flush updates the in fifo status (in_pkt_rdy and tx_not_empty bits). the status of the endpoint 1-4 in fifo for both of the above cases, could be obtained from the in csr as shown in table 12 . interrupt endpoints: any endpoint can be used for interrupt transfers. for normal interrupt transfers, the interrupt transactions be- have the same as bulk transactions, i.e., no special setting is required. the in endpoints may also be used to communicate rate feedback information for certain types of isochronous functions. this is done by setting the intpt bit in the in csr register of the corresponding endpoint. when the intpt bit is set, the data toggle bits is changed after each packet is sent to the host without regard to the presence or type of handshakepack- et. the following outlines the operation sequence for an in endpoint used to communicate rate feedback infor- mation: 1. set maxp > 1/2 of the endpoints fifo size; 2. set intpt bit of the in csr; 3. flush the old data in the fifo; 4. load interrupt status information and set in_pkt_rdy bit in the in csr; 5. repeat steps 3 & 4 for all subsequent interrupt status updates. out (receive) fifos the usb fcu writes data to the endpoints out fifo location specified by the fifo write pointer, which au- tomatically increments by one after a write. when the usb fcu has successfully received a data packet, it sets the out_pkt_rdy bit to a 1 in the out csr. the cpu/dmac only reads data from the out fifo if the out_pkt_rdy bit of the out csr is a 1. endpoint 0 out fifo operation: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the cpu writes a 0 to the out_pkt_rdy bit after the packet of data is unloaded from the out fifo by the cpu. endpoint 1-4 out fifo operation when auto_clr (bit 7 of out csr) = 0: maxp > half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the cpu writes a 0 to the out_pkt_rdy bit after the packet of data is unloaded from the out fifo by the cpu/dmac. table 12: ta fifo status in_pkt_rdy tx_not_empty tx fifo status 00 no data packet in tx fifo 01 one data packet in tx fifo if maxp <= half of the fifo size. x1 one data packet in tx fifo if maxp >= half of the fifo size. 10 invalid 11 two data packets in tx fifo if maxp <= half of the fifo size
confidential 48 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus maxp <= half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has success- fully received a packet of data from the host. the cpu writes a 0 to the out_pkt_rdy bit after the packet of data is unloaded from the out fifo by the cpu/dmac. in this configuration, the fifo can store up to two data packets at the same time, for back-to-back reception. therefore, the out_pkt_rdy bit may remain set after the cpu writes a 0 to it if there is another packet in the out fifo. endpoint 1-4 out fifo operation when auto_clr (bit 7 of out csr) = 1: maxp > half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the usb fcu clears the out_pkt_rdy bit to a 0 automatically when the number of bytes of data equal to the maxp (maximum packet size) is unloaded from the out fifo by the cpu/dmac. maxp <= half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has success- fully received a packet of data from the host. the usb fcu clears the out_pkt_rdy bit to a 0 automati- cally when the number of bytes of data equal to the maxp (maximum packet size) is unloaded from the out fifo by the cpu/dmac. in this configuration, the fifo can hold up to two data packets at the same time, for back-to-back reception. therefore, the out_pkt_rdy bit may remain set after one packet (size equal to maxp) of data is unloaded if there is another packet in the out fifo. a software flush acts as if a packet is being unloaded from the out fifo. if there is one packet in the out fifo, a flush causes the out fifo to be empty, if there are two packets in the out fifo, a flush causes the older packet to be flushed out from the out fifo. usb special function registers the mcu controls usb operation through the use of special function registers (sfr). this section de- scribes in detail each usb related sfr. some usb special function registers have a mix of read/write, read only, and write only register bits. additionally, the bits may be configured to allow the user to write only a 0 or a 1 to individual bits. when accessing these registers, writing a 0 to a register that can only be set to a 1 by the cpu has no effect on that register bit. each figure and description of the special function registers details this operation. usb attach / detach register the usb attach / detach register is shown in figure 30. the register is used to detach the usb func- tion from a usb host without physically disconnecting the usb cable. the register is enabled in this special mode by setting port83_second high, this forces port 8_3 to operate as a pull-up for d+(it tri-states the port output driver and forces a 1 if port 8_3 is read).when the attach/detach bit is high, an attach is detected by the host; when set low, a detach is registered by the host. a 1.5k ohm pull- up resistor must be added externally from port 8 3 to d+ to enable this mode. this mode is bypassed when extcap is used to pull up d+ via a 1.5 k ohm resistor. figure 30: usb attach / detach register port83_second: 0 normal mode for port 8_3 1 forces port 8_3 to operate as pull-up for d+ enable special register. attach / detach (enabled when bit 0 is set to 1): 0 will cause the host to eventually detect a detach. 1 will cause host to detect attach. bit 7:2 reserved msb 7 lsb 0 address: 001f 16 access: r/w reset: 00 16 attach p83_2nd reserved reserved reserved reserved reserved reserved
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 49 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus the usb control register , shown in figure 31 , is used to control the usb fcu (for microsoft legacy application, please see addendum). this register is not reset by a usb reset signaling. after the usb is enabled (usbc7 set to 1), a minimum delay of 250ns (three 12 mhz clock periods) is needed be- fore performing any other usb register read/write operations. figure 31: usb control register (for microsoft legacy application, see addendum) the usb function address register, shown in figure 32, maintains the 7-bit usb address assigned by the host. the usb fcu uses this register value to decode usb token packet addresses. at reset, when the device is not yet configured, the value is 00 16 . figure 32: usb function address register the usb power management registe r , shown in figure 33, is used for power management in the usb fcu. figure 33: usb power management register bit 2:0 reserved usbc3 transceiver voltage converter high/low current mode selection bit (bit 3) 0: high current mode, for usb normal operation 1: low current mode, for usb suspend operation usbc4 usb transceiver voltage converter enable bit (bit 4) 0: usb transceiver voltage converter disabled 1: usb transceiver voltage converter enabled usbc5 usb clock enable bit (bit 5) 0: 48 mhz clock to the usb block is disabled. 1: 48 mhz clock to the usb block is enabled. usbc6 usb sof port select bit (bit 6) 0: usb sof output is disabled. p8 6 is used as gpio pin. 1: usb sof output is enabled usbc7 usb enable bit (bit 7) 0: usb block is disabled, all usb internal registers are held at their default values. 1: usb block is enabled msb 7 lsb 0 usbc7 usbc6 usbc5 usbc4 usbc3 reserved reserved access: r/w reset: 00 16 address: 000c 16 reserved funad6:0 7-bit programmable function address (bits 6-0) bit 7 reserved (read/write 0) msb 7 lsb 0 reserved funad6 funad5 funad4 funad3 funad1 funad0 access: r/w reset: 00 16 funad2 address: 0300 16 suspend usb suspend detection flag (bit 0) (write 0 only or read) 0: no usb suspend signal detected 1: usb suspend signal detected resume usb resume detection flag (bit 1) (write 0 only or read) 0: no usb resume signal detected 1: usb resume signal detected wakeup usb remote wake-up bit (bit 2) 0: end remote resume signaling 1: remote resume signaling (if suspend = 1) bit7:3 reserved (read/write 0) msb 7 lsb 0 reserved reserved reserved reserved reserved resume suspend access: r/w reset: 00 16 wakeup address: 0301 16
confidential 50 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus usb suspend detection flag when the usb fcu receives a usb suspend signaling, it sets the suspend bit and generates an interrupt. the cpu writes a 0 to clear this bit when the device is resumed by the host (resume inter- rupt is generated and resume detection flag is set) or remote wake-up by itself (the cpu writes a 1 to remote wake-up bit). usb resume detection flag when the usb fcu is in suspend mode and receives a usb resume signaling, it sets the resume bit, and generates an interrupt. the cpu writes a 0 to clear this bit. usb remote wake-up bit the cpu writes a 1 to the wakeup bit for remote wake-up. while this bit is set, and the usb fcu is in suspend mode, it generates a resume signaling to the host. the cpu must keep this bit set for a minimum of 10ms and a maximum of 15ms before writing a 0 to this bit. the usb fcu is able to generate a usb function interrupt as discussed in usb interrupt section . usb interrupt status registers , shown in figures 34 and 35, are used to indicate the condition that caused a usb function interrupt to the cpu. a 1 indicates the corresponding condition caused a usb function interrupt. the usb interrupt status registers can be cleared by writing back to the reg- ister the same value that was read. to ensure proper operation, the cpu reads both usb interrupt status registers, then write back the same values it read to these two registers for clearing the status bits. the cpu must write the usb interrupt status register 1 first, then the usb interrupt status register 2. the registers cannot be cleared by writing a 0 to the bits that are a 1. figure 34: usb interrupt status register 1 intst0 is set to a 1 by the usb fcu if (in endpoint 0 csr): ? successfully receives a packet of data ? successfully sends a packet of data ? ep0csr3 (data_end) bit is cleared ? ep0csr4 (force_stall) bit is set ? ep0csr5 (setup_end) bit is set intst2, intst4, intst6 or intst8 is set to a 1 by the usb fcu if (in endpoint x in csr): ? successfully sends a packet of data ? inxcsr1 (under_run) bit is set intst0 usb endpoint 0 interrupt status flag (bit 0) bit 1 reserved (read/write 0) intst2 usb endpoint 1 in interrupt status flag (bit 2) intst3 usb endpoint 1 out interrupt status flag (bit 3) intst4 usb endpoint 2 in interrupt status flag (bit 4) intst5 usb endpoint 2 out interrupt status flag (bit 5) intst6 usb endpoint 3 in interrupt status flag (bit 6) intst7 usb endpoint 3 out interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 intst7 intst6 intst5 intst4 intst3 reserved intst0 access: r/w reset: 00 16 intst2 address: 0302 16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 51 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus intst3, intst5, intst7 or intst9 is set to a 1 by the usb fcu if (in endpoint xout csr): ? successfully receives a packet of data ? outxcsr1 (over_run) bit is set ? outxcsr4 (force_stall) bit is set figure 35: usb interrupt status register 2 intst12 is set to a 1 by the usb fcu if an overrun or underrun condition occurs in any of the end- points. intst13 is set to a 1 by the usb fcu if a usb reset signaling from the host is received. all other usb internal registers is reset to their default values. intst14 is set to a 1 by the usb fcu if a usb resume signaling is received from the host. intst15 is set to a 1 by the usb fcu if a usb suspend signaling is received from the host. the usb interrupt enable register s, shown in figure 36 and figure 37, are used to enable the cor- responding interrupt status conditions, which can generate a usb function interrupt. if the bit to a cor- responding interrupt condition is 0, that condition does not generate a usb function interrupt. if the bit is a 1, that condition can generate a usb function interrupt. upon reset, all usb interrupt status conditions are enabled except bit 7 of usb interrupt enable register 2 (that is, suspend and resume interrupt is disabled). figure 36: usb interrupt enable register 1 intst8 usb endpoint 4 in interrupt status flag (bit 0) intst9 usb endpoint 4 out interrupt status flag (bit 1) bit 3:2 reserved (read/write 0) intst12 usb overrun/underrun interrupt status flag (bit 4) intst13 usb reset interrupt status flag (bit 5) intst14 usb resume signaling interrupt status flag (bit 6) intst15 usb suspend signaling interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 intst15 intst14 intst13 intst12 reserved intst9 intst8 access: r/w reset: 00 16 address: 0303 16 reserved inten0 usb endpoint 0 in interrupt enable bit (bit 0) bit 1 reserved (read/write 0) inten2 usb endpoint 1 in interrupt enable bit (bit 2) inten3 usb endpoint 1 out interrupt enable bit (bit 3) inten4 usb endpoint 2 in interrupt enable bit (bit 4) inten5 usb endpoint 2 out interrupt enable bit (bit 5) inten6 usb endpoint 3 in interrupt enable bit (bit 6) inten7 usb endpoint 3 out interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled msb 7 lsb 0 inten7 inten6 inten5 inten4 inten3 reserved inten0 access: r/w reset: ff 16 inten2 address: 0304 16
confidential 52 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus figure 37: usb interrupt enable register 2 the usb frame number low register, shown in figure 38, contains the lower 8 bits of the 11-bit frame number received from the host. the usb frame number high register, shown in figure 39 contains the upper 3 bits of the 11-bit frame number received from the host. figure 38: usb frame number low register figure 39: usb frame number high register the usb iso control register, shown in figure 40, contains two global bits, iso_upd and auto_fl for endpoints 1-4 regarding the isochronous data transfer. if iso_upd = 0, a data packet in an endpoints in fifo is always ready to transmit upon receiving the next in_token from the host (with matched address & endpoint number). if iso_upd = 1 and the iso bit of the corresponding endpoints in csr is set, then the internal ready to transmit signal to the transmit control logic is delayed until the next sof. in this way, the data loaded in frame n is transmitted out in frame n+1. the iso_upd bit is a global bit for endpoints 1 to 4, and works with iso- chronous pipes only. if auto_fl = 1, iso_upd = "1", and a particular in endpoints iso bit is set, then at the time the usb fcu detects a sof packet, if the corresponding in endpoints in_pkt_rdy = 1, the usb fcu automatically flushes the oldest packet from the in fifo. in this case, in_pkt_rdy = 1 indicates that two data packets are in the in fifo. since, for iso transfer, double buffering is a requirement, maxp must be set to less than or equal to 1/2 of the fifo size. inten8 usb endpoint 4 in interrupt enable bit (bit 0) inten9 usb endpoint 4 out interrupt enable bit (bit 1) bit 3:2 reserved (read/write 0) inten12 usb overrun/underrun interrupt enable bit (bit 4) bit 5 reserved bit 6 reserved bit 7 reserved 0: interrupt disabled 1: interrupt enabled msb 7 lsb 0 reserved reserved reserved inten12 reserved inten9 inten8 access: r/w reset: 33 16 address: 0305 16 reserved fn7:0 lower 8 bits of the 11-bit frame number issued with a sof token msb 7 lsb 0 fn7 fn6 fn5 fn4 fn3 fn1 fn0 access: r reset: 00 16 fn2 address: 0306 16 fn10:8 upper 3 bits of the 11-bit frame number issued with a sof token bits 7:3 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved fn9 fn8 access: r reset: 00 16 fn10 address: 0307 16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 53 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus figure 40: usb iso control register the usb dmax request registers, shown in figures 41 and 42, are used to select the usb endpoint x fifo read/write request as dmac channel 0 or channel 1 request source. figure 43 shows the usb enpoint enable register. the usb dma0 (dma1) request register has only one bit set at any given time. if multiple bits are set, then no request is selected . figure 41: usb dma0 request register figure 42: usb dma1 request register figure 43: usb endpoint enable register bits 5:0 reserved (read/write 0) auto_fl auto_flush bit (bit 6) 0: hardware auto fifo ?ush disabled 1: hardware auto fifo ?ush enabled iso_upd iso_update bit (bit 7) 0: iso_update disabled 1: iso_update enabled msb 7 lsb 0 iso_upd auto_fl reserved reserved reserved reserved reserved access: r/w reset: 00 16 address: 0308 16 reserved dma0r0 endpoint 1 in fifo write request selection bit (bit 0) dma0r1 endpoint 2 in fifo write request selection bit (bit 1) dma0r2 endpoint 3 in fifo write request selection bit (bit 2) dma0r3 endpoint 4 in fifo write request selection bit (bit 3) dma0r4 endpoint 1 out fifo read request selection bit (bit 4) dma0r5 endpoint 2 out fifo read request selection bit (bit 5) dma0r6 endpoint 3 out fifo read request selection bit (bit 6) dma0r7 endpoint 4 out fifo read request selection bit (bit 7) 0: not selected 1: selected msb 7 lsb 0 dma0r7 dma0r6 dma0r5 dma0r4 dma0r3 dma0r1 dma0r0 access: r/w reset: 00 16 dma0r2 address: 0309 16 dma1r0 endpoint 1 in fifo write request selection bit (bit 0) dma1r1 endpoint 2 in fifo write request selection bit (bit 1) dma1r2 endpoint 3 in fifo write request selection bit (bit 2) dma1r3 endpoint 4 in fifo write request selection bit (bit 3) dma1r4 endpoint 1 out fifo read request selection bit (bit 4) dma1r5 endpoint 2 out fifo read request selection bit (bit 5) dma1r6 endpoint 3 out fifo read request selection bit (bit 6) dma1r7 endpoint 4 out fifo read request selection bit (bit 7) 0: not selected 1: selected msb 7 lsb 0 dma1r7 dma1r6 dma1r5 dma1r4 dma1r3 dma1r1 dma1r0 access: r/w reset: 00 16 dma1r2 address: 030a 16 msb 7 ep4_in ep4_out ep3_in ep3_out ep2_in ep1_in ep1_out access: r/w reset: ff 16 ep2_out address: 030b 16 lsb 0 0: not selected 1: selected ep1_out endpoint 1 in fifo write request selection bit (bit 0) ep1_in endpoint 2 in fifo write request selection bit (bit 1) ep2_out endpoint 3 in fifo write request selection bit (bit 2) ep2_in endpoint 4 in fifo write request selection bit (bit 3) ep3_out endpoint 1 out fifo read request selection bit (bit 4) ep3_in endpoint 2 out fifo read request selection bit (bit 5) ep4_out endpoint 3 out fifo read request selection bit (bit 6) ep4-in endpoint 4 out fifo read request selection bit (bit 7)
confidential 54 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus the endpoint 0 csr (control & status register), shown in figure 44, contains the control and status infor- mation of endpoint 0. figure 44: usb endpoint 0 csr ep0csr0 (out_pkt_rdy): the usb fcu sets this bit to a 1 upon receiving a valid setup/out token from the host. the cpu clears this bit after unloading the fifo, by way of writing a 1 to ep0csr6. the cpu does not clear the out_pkt_rdy bit before finishes decoding the host request. if ep0csr2 (send_stall) needs to be set - the cpu decodes an invalid or unsupported request - the setting ep0csr6 = 1 & ep0csr2 = 1 is done in a same cpu write. ep0csr1 (in_pkt_rdy): the cpu writes a 1 to this bit after it finishes writing a packet of data to the endpoint 0 fifo. the usb fcu clears this bit after the packet is successfully transmitted to the host, or the ep0csr5 (setup_end) bit is set. ep0csr2 (send_stall): the cpu writes a 1 to this bit if it decodes an invalid or unsupported standard device request from the host. the usb fcu returns a stall handshake for all subsequent in/out transactions (during control transfer data or status stages) while this bit is set. the cpu writes a 0 to clear this bit. ep0csr3 (data_end): for control transfers, the cpu writes a 1 to this bit when it writes (in data phase) or reads (out data phase) the last packet of data to or from the fifo. this bit indicates to the usb fcu that the specific amount of data in the setup phase is transferred. the usb fcu advances to the status phase once this bit is set. when the status phase completes, the usb fcu clears this bit. when this bit is set to a 1, and the host again requests or sends more data, the usb fcu returns a stall handshake. ep0csr4 (force_stall): the usb fcu sets this bit to a 1 if the host sends out a larger data packet than the maxp size, or if during a data stage a command pipe is sent more data or is requested to return more data than was indicated in the setup stage (see description for ep0csr3). the usb fcu returns a stall handshake for all subsequent in/out transactions (during data or status stages) while this bit is set. the cpu writes a 0 to clear this bit. ep0csr0 out_pkt_rdy flag (bit 0) (read only - write ?0? 0: out packet is not ready 1: out packet is ready ep0csr1 in_pkt_rdy bit (bit 1) (write ?1?only or read) 0: in packet is not ready 1: in packet is ready ep0csr2 send_stall bit (bit 2) (write ?1?only or read) 0: no action 1: stall endpoint 0 by the cpu ep0csr3 data_end bit (bit 3) (write ?1?only or read) 0: no action 1: last packet of data transferred from/to the fifo ep0csr4 force_stall flag (bit 4) (write ?0?only or read) 0: no action 1: stall endpoint 0 by the usb fcu ep0csr5 setup_end flag (bit 5) (read only - write ?0? 0: no action 1: control transfer ended before the specific length of data is transferred during the data phase ep0csr6 serviced_out_pkt_rdy bit (bit 6) (write only - read ?0? 0: no change 1: clear the out_pkt_rdy bit (ep0csr0) ep0csr7 serviced_setup_end bit (bit 7) (write only - read ?0? 0: no change 1: clear the stup_end bit (ep0csr5) ep0csr7 ep0csr1 ep0csr6 ep0csr0 ep0csr2 ep0csr3 ep0csr4 ep0csr5 address: 0311 16 access: r/w reset 00 16 lsb 0 msb 7
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 55 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus ep0csr5 (setup_end): the usb fcu sets this bit to a 1 if a control transfer has ended before the specific length of data is trans- ferred during the data phase. the cpu clears this bit by writing a 1 to ep0csr7. once the cpu sees the setup_end bit set, it stops accessing the fifo to service the previous setup transaction. if out_pkt_rdy is set at the same time setup_end is set, it indicates the previous setup transaction ended, and a new set- up token is in the fifo. ep0csr6 and ep0csr7: these bits are used to clear ep0csr0 and ep0csr5 respectively. writing a 1 to these bits clears the corre- sponding register bit. the usb endpoint 0 maxp, shown in figure 45, indicates the maximum packet size (maxp) of end- point 0 in/out packet. the default value for endpoint 0 maxp is 8 bytes. the cpu can change this value, as negotiated with the host controller through the set_descriptor command. figure 45: usb endpoint 0 maxp the usb endpoint 0 out wrt cnt register, shown in figure 46, contains the number of bytes of the current data set in the out fifo. the usb fcu sets the value in the write count register after having successfully received a packet of data from the host. the cpu reads the register to determine the number of bytes to be read from the fifo. figure 46: usb endpoint 0 out wrt cnt the usb endpoint x in csr (control & status register), shown in figure 47, contains control and status information of the respective in endpoint 1-4. inxcsr0 (in_pkt_rdy) and inxcsr5 (tx_fifo_not_empty): these two bits are read together to determine in fifo status. a 1 can be written to the inxcsr0 bit by the cpu to indicate a packet of data is written to the fifo (see in (transmit) fifo operation for details). inxcsr1 (under_run): this bit is used in iso mode only to indicate to the cpu that a fifo underrun has occurred. the usb fcu sets this bit to a 1 at the beginning of an in token if no data packet is in the fifo. setting this bit causes the inst12 bit of the interrupt status register 2 to set. the cpu writes a 0 to clear this bit. inxcsr2 (send_stall): the cpu writes a 1 to this bit when the endpoint is stalled (transmitter halt). the usb fcu returns a stall handshake while this bit is set. the cpu writes a 0 to clear this bit. inxcsr3 (iso): the cpu writes a 1 to this bit to initialize the respective endpoint as an isochronous endpoint for in trans- actions. inxcsr4 (intpt): the cpu writes a 1 to this bit to initialize this endpoint as a status change endpoint for in transactions. this bit is set only if the corresponding endpoint is to be used to communicate rate feedback information (see chapter . in (transmit) fifos for details). ep0mxp4:0 maximum packet size (maxp) of endpoint 0 in/out packet. msb 7 lsb 0 reserved reserved ep0mxp5 ep0mxp4 ep0mxp3 ep0mxp1 ep0mxp0 ep0mxp2 access: r/w reset: 08 16 address: 0313 16 w_cnt4:0 receive byte count. msb 7 lsb 0 reserved reserved reserved w_cnt4 w_cnt3 w_cnt1 w_cnt0 w_cnt2 access: r reset: 00 16 address: 0315 16
confidential 56 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus inxcsr5 (tx_fifo_not_empty): the usb fcu sets this bit to a 1 when there is data in the in fifo. this bit in conjunction with in_pkt_rdy bit provides the transmit fifo status information (see in (transmit) fifo operation for details). inxcsr6 (flush): the cpu writes a 1 to this bit to flush the in fifo. if there is one packet in the in fifo, a flush causes the in fifo to be empty, if there are two packets in the in fifo, a flush causes the older packet to be flushed out from the in fifo. setting the inxcsr6 (flush) bit during transmission could produce unpredictable results. inxcsr7 (auto_set): if the cpu sets this bit to a 1, the in_pkt_rdy bit is set automatically by the usb fcu after the number of bytes of data equal to the maximum packet size (maxp) is written into the in fifo (see in (transmit) fifo operation for details). figure 47: usb endpoint x in csr the usb endpoint x out csr (control & status register), shown in figure 48, contains control and status information of the respective out endpoint 1-4. outxcsr0 (out _pkt_rdy): the usb fcu sets the this bit to a 1 after it successfully receives a packet of data from the host. this bit is cleared by the cpu or by the usb fcu after a packet of data is unloaded from the fifo (see out (receive) fifo operation for details). outxcsr1 (over_run): this bit is used in iso mode only to indicate to the cpu that a fifo overrun has occurred. the usb fcu sets this bit to a 1 at the beginning of an out token if the outxcsr0 (out_pkt_rdy) bit is not cleared. setting this bit causes the inst12 bit of the interrupt status register 2 to set. the cpu writes a 0 to clear this bit. outxcsr2 (send_stall): the cpu writes a 1 to this bit when the endpoint is stalled (receiver halt). the usb fcu returns a stall handshake while this bit is set. the cpu writes a 0 to clear this bit. outxcsr3 (iso): the cpu sets this bit to a 1 to initialize the respective endpoint as an isochronous endpoint for out trans- actions. inxcsr0 in_pkt_rdy bit (bit 0) (write 1 only or read) 0: in packet is not ready 1: in packet is ready inxcsr1 under_run flag (bit 1) (write 0 only or read) 0: no fifo underrun 1: fifo underrun has occurred inxcsr2 send_stall bit (bit 2) 0: no action 1: stall in endpoint x by the cpu inxcsr3 iso bit (bit 3) 0: select non-isochronous transfer 1: select isochronous transfer inxcsr4 intpt bit (bit 4) 0: select non-rate feedback interrupt transfer 1: select rate feedback interrupt transfer inxcsr5 tx_not_ept flag (bit 5) (read only - write 0) 0: transmit fifo is empty 1: transmit fifo is not empty inxcsr6 flush bit (bit 6) (write only - read 0) 0: no action 1: flush the fifo inxcsr7 auto_set bit (bit 7) 0: auto_set disabled 1: auto_set enabled msb 7 lsb 0 inxcsr7 inxcsr6 inxcsr5 inxcsr4 inxcsr3 inxcsr1 inxcsr0 inxcsr2 address: 0319 16 access: r/w reset: 00 16 address: 0321 16 address: 0329 16 address: 0331 16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 57 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus outxcsr4 (force_stall): the usb fcu sets this bit to a 1 if the host sends out a larger data packet than the maxp size. the usb fcu returns a stall handshake while this bit is set. the cpu writes a 0 to clear this bit. outxcsr5 (data_err): the usb fcu sets this bit to a 1 to indicate a crc error or a bit stuffing error received in an iso packet. the cpu writes a 0 to clear this bit. outxcsr6 (flush): the cpu writes a 1 to this to flush the out fifo. if there is one packet in the out fifo, a flush causes the out fifo to be empty, if there are two packets in the out fifo, a flush causes the older packet to be flushed out from the out fifo. setting the outxcsr6 (flush) bit during reception could produce unpre- dictable results. outxcsr7 (auto_clr): if the cpu sets this bit to a 1, the out_pkt_rdy bit is cleared automatically by the usb fcu after the number of bytes of data equal to the maximum packet size (maxp) is unloaded from the out fifo (see out (receive) fifo operation for details). figure 48: usb endpoint x out csr the usb endpoint x in maxp, shown in figure 49, indicates the maximum packet size (maxp) of an endpoint x in packet. the default values for endpoints 1-4 are 0 bytes. the cpu can change this val- ue, as negotiated with the host controller through the set_descriptor command. figure 49: usb endpoint x in maxp outxcsr0 out_pkt_rdy flag (bit 0) (write 0 only or read) 0: out packet is not ready 1: out packet is ready outxcsr1 over_run flag (bit 1) (write 0 only or read) 0: no fifo overrun 1: fifo overrun occurred outxcsr2 send_stall bit (bit 2) 0: no action 1: stall out endpoint x by the cpu outxcsr3 iso bit (bit 3) 0: select non-isochronous transfer 1: select isochronous transfer outxcsr4 force_stall flag (bit 4) (write 0 only or read) 0: no action 1: stall endpoint x by the usb fcu outxcsr5 data_err flag (bit 5) (write 0 only or read) 0: no error 1: crc or bit stuf?ng error received in an iso packet outxcsr6 flush bit (bit 6) (write only - read 0) 0: no action 1: flush the fifo outxcsr7 auto_clr bit (bit 7) 0: auto_clr disabled 1: auto_clr enabled msb 7 lsb 0 outxcsr7 outxcsr6 outxcsr5 outxcsr4 outxcsr3 outxcsr1 outxcsr0 outxcsr2 address: 031a 16 access: r/w reset: 00 16 address: 0322 16 address: 032a 16 address: 0332 16 imaxp7:0 maximum packet size (maxp) of endpoint x in packet. for endpoints that support smaller fifo size, unused bits are not implemented (always write 0 to those bits) msb 7 lsb 0 imaxp7 imaxp6 imaxp5 imaxp4 imaxp3 imaxp1 imaxp0 imaxp2 address: 031b 16 access: r/w reset: 00 16 address: 0323 16 address: 032b 16 address: 0333 16
confidential 58 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change universal serial bus the usb endpoint x out maxp, shown infigure 50, indicates the maximum packet size (maxp) of an endpoint x out packet. the default values for endpoints 1-4 are 0 bytes. the cpu can change this value, as negotiated with the host controller through the set_descriptor command. figure 50: usb endpoint x out maxp the u sb endpoint x out wrt cnt register, shown in figure 51, contains the number of bytes of the current data set in the out fifo. the usb fcu sets the value in the write count register after having successfully received a packet of data from the host. the cpu reads the register to determine the num- ber of bytes to be read from the fifo. figure 51: usb endpoint x out wrt cnt the usb endpoint x fifo register, shown in figure 52, is the usb in (transmit) and out (receive) fifo data register. the cpu writes data to these registers for the corresponding endpoint in fifo and reads data from these registers for the corresponding endpoint out fifo. figure 52: usb endpoint x fifo register omaxp7:0 maximum packet size (maxp) of endpoint x out packet. for endpoints that support smaller fifo size, unused bits are not implemented (always write 0 to those bits) msb 7 lsb 0 omaxp7 omaxp6 omaxp5 omaxp4 omaxp3 omaxp1 omaxp0 omaxp2 address: 031c 16 access: r/w reset: 00 16 address: 0324 16 address: 032c 16 address: 0334 16 w_cnt7:0 receive byte count. msb 7 lsb 0 w_cnt7 w_cnt6 w_cnt5 w_cnt4 w_cnt3 w_cnt1 w_cnt0 w_cnt2 address: 031d 16 access: r reset: 00 16 address: 0325 16 address: 032d 16 address: 0335 16 data_7:0 endpoint x in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 data_2 address: 0338 16 access: r reset: n/a address: 0339 16 address: 033a 16 address: 033b 16 address: 033c 16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 59 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change dmac 2.19 dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu.table 13 shows the dmac specifications. figure 53 shows the block diagram of the dmac. figure 54, figure 55 and figure 56 show the registers used by the dmac. note: dma transfer is not affected by any interrupt. table 13: dmac speci?cations item speci?cation number of channels 2 (cycle steal method) transfer memory space ?from any sfr, ram, or rom address to a ?xed address ?from a ?xed address to any sfr or ram address ?from a ?xed address to a ?xed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum number of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) falling edge of int0 or int1 (int0 can be selected by dma0, int1 by dma1) timer a0 to timer a4 interrupt requests timer b0 to timer b1 interrupt requests uart0 transmission and reception interrupt requests uart1 transmission and reception interrupt requests uart2 transmission and reception interrupt requests a-d conversion interrupt requests usb function interrupt requests usb sof interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward/?xed (forward direction cannot be speci?ed for both source and destination simultaneously) transfer mode single transfer the dma enable bit is cleared and transfer ends when an under?ow occurs in the transfer counter repeat transfer when an under?ow occurs in the transfer counter, the value in the transfer counter reload register is reloaded into the transfer counter and the dma transfer is repeated dma interrupt request generation timing when an under?ow occurs in the transfer counter dma startup single transfer transfer starts when the dma is requested after 1 is written to the dma enable bit repeat transfer transfer starts when the dma is requested after 1 is written to the dma enable bit or after an under?ow occurs in the transfer counter dma shutdown when 0 is written to the dma enable bit when, in single transfer mode, an under?ow occurs in the transfer counter forward address pointer and reload timing for transfer counter when dma transfer starts, the value of whichever of the source or destination pointer that is set up as the forward pointer is reloaded into the forward address pointer. the value in the transfer counter reload register is reloaded into the transfer counter. writing to register registers speci?ed for forward direction transfer are always write-enabled. registers speci?ed for ?xed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register sets up as the forward register is the same as reading the value of the forward address pointer.
confidential 60 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change dmac figure 53: block diagram of dmac figure 54: dmac register (1) a a a a a a aa aa aa aa aa a a aa aa aa aa aa aa aa aa aa data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits aa aa aa aa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaa aaaaaaaa address bus a a a a a a a a dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) a a a dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) aa aa aa aa aa aa a a a a a a a a aa aa aa aa a a a a a a a a dmai request cause select register symbol address when reset dmisl (i=0,1) 03b8 16, 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is ?? software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int0 / int1 pin (note1) 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 0 1 1 1 : timer b0 1 0 0 0 : timer b1 1 0 0 1 : usb0/usb1 (note 3) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit / uart1 receive (note 2) bit name note 1: address 03b8 16 is for int0, 03ba 16 is for int1. note 2: address 03b8 16 is for uart1 transmit, 03ba 16 is for uart1 receive. note 3: address 03b8 16 is for usb0, 03ba 16 is for usb1.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 61 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change dmac figure 55: dmac register (2) figure 56: dmac register (3) dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit rw dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is ?? note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to ?? note 3: source address direction select bit and destination address direction select bit cannot be set to ??simultaneously. (note 2) b7 b0 b7 b0 (b8) (b15) function rw transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is ?? symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is ??
confidential 62 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change dmac (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses and the software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd address- es, there is one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 14 show the num- ber of dmac transfer cycles. table 15 shows the corresponding coefficient values. figure 57 shows an example of the transfer cycle for a source read. the number of dmac transfer cycles can be calculated as follows: number of transfer cycles per transfer unit = number of read cycles x j + number of write cycles x k table 14: number of dmac transfer cycles transfer unit access address single-chip mode number of read cycles number of write cycles 8-bit transfers (dmbit=1) even 1 1 odd 1 1 16-bit transfers (dmbit=0) even 1 1 odd 2 2 table 15: coef?cients j,k internal memory internal rom/ ram no wait internal rom/ ram with wait sfr area 122
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 63 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change dmac figure 57: example of the transfer cycle for a source read clkout address bus data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. clkout address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) one wait is inserted into the source read under the conditions in (1) clkout address bus data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd transferring 16-bit data on an 8-bit data bus (in this case, there are two destination write cycles). clkout address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) (when 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). note: the same timing changes occur with the respective conditions at the destination as at the source.
confidential 64 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timers 2.20 timers there are eight 16-bit timers. these timers can be classified by function into timers a (five) and timers b (three). all these timers function independently. figure 58 shows the block diagram of timers a and b. figure 58: timer a andtimer b block diagram timer a3 interrupt timer a4 interrupt timer a1 interrupt timer a2 interrupt timer a0 interrupt timer b1 interrupt ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 noise filter noise filter noise filter noise filter noise filter 1/8 1/4 f 1 f 8 f 32 x in timer b0 interrupt ?timer mode ?timer mode ?timer mode timer b0 timer b1 timer b2 timer b2 interrupt
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 65 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a 2.21 timer a figure 59, figure 60, figure 61, and figure 62 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 000016. ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure 59: block diagram of timer a figure 60: timer a related registers (1) tai addresses taj tak timer a0 0387 16 0386 16 timer a4 timer a1 timer a1 0389 16 0388 16 timer a0 timer a2 timer a2 038b 16 038a 16 timer a1 timer a3 timer a3 038d 16 038c 16 timer a2 timer a4 timer a4 038f 16 038e 16 timer a3 timer a0 count start flag (address 0380 16 ) up count/down count always down count except in event counter mode reload register (16) counter (16) low-order 8 bits high-order 8 bits clock source selection ?timer (gate function) ?timer ?one shot ?pwm f 1 f 8 f 32 external trigger tai in (i = 0 to 4) tb2 overflow ?event counter f c32 clock selection taj overflow (j = i ?1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits up/down flag down count (address 0384 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit
confidential 66 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a figure 61: timer a-related registers (2) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to ? symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow one-shot timer mode 0000 16 to ffff 16 counts a one shot width pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 67 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a figure 62: timer a-related registers (3) symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0 ) cpsr w r nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to 0 . ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to 0 . w r 1 : timer start when read, the value is 0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
confidential 68 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a (1) timer mode in this mode, the timer counts an internally generated count source. see table 16 below. figure 63 shows the timer ai mode register in timer mode. figure 63: timer ai mode register in timer mode table 16: speci?cations of timer mode item speci?cation count source f1, f8, f32 count operation ? down count ? when the timer under?ows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start ?ag is set (= 1) count stop condition count start ?ag is reset (= 0) interrupt request generation timing when the timer under?ows taiin pin function programmable i/o port or gate input taiout pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written only to reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by taiin pins input signal ? pulse output funtion each time the timer under?ows, the taiout pins polarity is reversed. note 1: the settings of the corresponding port register and port direction register are invalid. note 2: the bit can be ??or ?? note 3: set the corresponding port direction register to ?? timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held ??(note 3) 1 1 : timer counts only when ta iin pin is held ??(note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 69 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 17 lists the timer specifications when counting a single-phase external signal. figure 64 shows timer ai mode register in event counter mode, single-phase signal. table 17: timer speci?cation in event counter mode (when not processing two-phase pulse signal) item speci?cation count source ?external signals input to taiin pin (effective edge can be selected by software ?tb2 over?ow, taj over?ow count operation ?up count or down count can be selected by external signal or software ?when the timer over?ows or under?ows, it reloads the reload register contents before continuing counting. (however, this does not apply when the free-run function is selected.) divide ration 1/ (fff 16 - n+1) for up count 1/ (n + 1) for down count n: set value count start condition count start ?ag is set (=1) count stop condition count start ?ag is reset (=0) interrupt request generation timing timer over?ows or under?ows taiin pin function programmable i/o port or count source input taiout pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register writer to timer ?when counting stopped when a value is written to timer ai register, it si written to both reload register and counter ?when counting in progress when a value is writtento timer ai register, it si written to only reload register select function ?free-run count function even when the timer over?ows or under?ows, the reload register content is not reloaded to it ?pulse output function
confidential 70 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a figure 64: timer ai mode register in event counter mode, single signal table 18 shows the timer specification in event counter mode when processing two-phase signal with timers a2, a3, and a4. figure 65 shows timer ai mode register in event counter mode when processing two-phase signal. timer ai mode register note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 0383 16 ). note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an l signal is input to the tai out pin, the downcount is activated. when h , the upcount is activated. set the corresponding port direction register to 0 . symbol address when reset taimr(i = 0, 1) 0396 16 , 0397 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to 0 in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 invalid in event counter mode can be 0 or 1 tmod1 a a a a a a a a a a a a a a a a a a
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 71 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a table 18: timer speci?cation in even counter mode (when processing two-phase pulse signal with timers a2, a3, and a4) item speci?cation count source ?two-phase pulse signals input to taiin or taiout pin count operation ?up count or down count can be selected by two-phase pulse signal ?when the timer over?ow or under?ows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (fff16 - n + 1) for up count 1/ (n+1) for down count n : set value count start condition count start ?ag is set (=1) count stop condition count start ?ag is reset (=0) interrupt request generation timing timer over?ow or under?ows ta i in pin function two-phase pulse input ta i out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register writer to timer ?when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ?when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register (transferred to counter at next reload time.) select function ?normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ?multiply-by-4 processing operation if the phase relationship is such that the ta i in pin goes h when the input signal on the ta i out pin is h, the timer counts up rising and falling edges on the ta i out a nd t ai in pins. if the phase relationship is such that the t ai in pin goes l when the input signal on the ta i out pin is h, the timer counts rising and falling edges on the ta i out and t ai in pins. note this does not apply when the free-run function is selected. ta i out ta i in (i=2,3) up count up count up count down count down count down count count up all edges count down all edges count down all edges count up all edges ta i out t ai in (i=3,4)
confidential 72 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a figure 65: timer ai mode register in event counter mode, two-phase signal note 1: the settings of the corresponding port register and port direction register are invalid. note 2: this bit is valid when only counting an external signal. note 3: set the corresponding port direction register to 0 . note 4: this bit is valid for the timer a3 mode register. for timer a2 and a4 mode registers, this bit can be 0 or 1 . note 5: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to 1 . also, always be sure to set the event/trigger select bit (addresses 0382 16 and 0383 16 ) to 00 . timer ai mode register (when not using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (tai out pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 0 : (must always be 0 in event counter mode) tck1 tck0 01 0 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) bit symbol bit name function w r count operation type select bit two-phase pulse signal processing operation select bit (note 4)(note 5) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation note 1: this bit is valid for timer a3 mode register. for timer a2 and a4 mode registers, this bit can be 0 or 1 . note 2: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to 1 . also, always be sure to set the event/trigger select bit (addresses 0382 16 and 0383 16 ) to 00 . timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be 0 when using two-phase pulse signal processing) 0 (must always be 0 when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be 0 when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be 1 when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 aa aa a a aa a aa a aa a aa a aa a aa aa a a aa a aa a aa aa a a aa a aa a aa a aa a aa a aa aa a a
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 73 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a (3) one-shot timer mode in this mode, the timer operates only once. (see table 19 .) when a trigger occurs, the timer starts up and continues operating for a given period. figure 66 shows the timer ai mode register in one-shot mode. figure 66: timer ai mode register in one-shot mode table 19: timer speci?cations in one-shot timer mode item speci?cation count source f1, f8, f32 count operation ?the timer counts down ?when the count reaches000016, the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer over?ows ? the one-shot start ?ag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 000016 ? the count start ?ag is reset (= 0) interrupt request generation tim ing the count reaches 000016 taiin pin function programmable i/o port or trigger input taiout pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ?when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : invalid b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ??or ?? note 3: set the corresponding port direction register to ?? w r
confidential 74 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a (4) pulse-width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 20 .) in this mode, the counter functions as either a 16-bit pulse-width modulator or an 8-bit pulse-width modulator. fig- ure 67 shows the timer ai mode register in pulse-width modulation mode. figure 68 shows the exam- ple of how a 16-bit pulse-width modulator operates. figure 69 shows the example of how an 8-bit pulsewidth modulator operates. table 20: timer speci?cations in pulse-width modulation mode item speci?cation count source f1, f8, f32 count operation ?the timer counts down (operating as an 8-bit or a 16-bit pulse-width modulator) ?the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ?high level width n / ?n n : set value ?cycle time(216-1) / ? ?xed 8-bit pwm ?high level width n (m+1) / ? n : values set to timer ai registers high-order address ?cycle time (28-1) (m+1) / ? m : values set to timer ai registers low-order address count start condition ?external trigger is input ?the timer over?ows ?the count start ?ag is set (= 1) count stop condition ?the count start ?ag is reset (= 0) interrupt request generation timing pwm pulse goes l taiin pin function programmable i/o port or trigger input taiout pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ?when counting in progress when a value is written to timer a register, it is written to only reload register (transferred to counter at next reload timer).
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 75 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a figure 67: timer ai mode register in pulse-width modulation mode figure 68: example of how a 16-bit pulse-width modulator operates bit name timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ??in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ??or ?? note 2: set the corresponding port direction register to ?? 1 / f i x (2 ?1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal ? ? ? ? timer ai interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 ) note: n = 0000 16 to fffe 16 . 1 / f i x n
confidential 76 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer a figure 69: example of how an 8-bit pulse-width modulator operates count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin ? ? ? ? ? ? ? ? timer ai interrupt request bit cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to fe 16 ; n = 00 16 to fe 16 . condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 ?1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1)
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 77 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer b 2.22 timer b figure 70 shows the block diagram of timer b. figure 71 and figure 72 show the timer b-related registers. use the timer bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. timer b works in timer mode only (i.e., the timer counts an in internal count source). figure 70: block diagram of timer b figure 71: timer b-related registers clock source selection (address 0380 16 ) reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 count start flag counter reset circuit counter (16) address 0391 16 0390 16 0393 16 0392 16 0395 16 0394 16 tbi timer b0 timer b1 timer b2 tbj timer b2 timer b0 timer b1 tbj overflow (j=i - 1. note, however, j = 2 when i = 0) note 1: timer b0. note 2: timer b1, timer b2. timer bi mode register symbol address when reset tbimr(i=0 to 2) 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be ??or ? mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : invalid tck1 tck0 count source select bit 0 invalid in timer mode. this bit can neither be set nor reset. when read in timer mode, its content is indeterminate. 0 0 (fixed to ??in timer mode ; i = 0) nothing is assiigned (i = 1, 2). this bit can neither be set nor reset. when read, its content is indeterminate. (note 1) (note 2) b7 b6
confidential 78 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timer b figure 72: timer b-related registers symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r ?pulse period / pulse width measurement mode measures a pulse period or width ?timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set ?event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 79 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timer b (1) timer mode in this mode, the timer counts an internally generated count source. (see table 21 ) figure 73 shows the timer bi mode register in timer mode. note: timer b2 does not generate an interrupt; it is used only as a prescaler. figure 73: timer bi mode register in timer mode table 21: timer speci?cations in timer mode item speci?cation count source f1, f8, f32 count operation ?counts down ?when the timer under?ows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start ?ag is set (= 1) count stop condition count start ?ag is reset (= 0) interrupt request generation timing the timer under?ows (see note) note 1: timer b0. note 2: timer b1, timer b2. timer bi mode register symbol address when reset tbimr(i=0 to 2) 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be ??or ? mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : invalid tck1 tck0 count source select bit 0 invalid in timer mode. this bit can neither be set nor reset. when read in timer mode, its content is indeterminate. 0 0 (fixed to ??in timer mode ; i = 0) nothing is assiigned (i = 1, 2). this bit can neither be set nor reset. when read, its content is indeterminate. (note 1) (note 2) b7 b6
confidential 80 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 2.23 uart0 through uart2 serial i/o is configured as three channels: uart0, uart1, and uart2. uart0, uart1, and uart2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 74 shows the block diagram of uart0, uart1, and uart2. figure 74: block diagram of uarti (i=0 to 2) n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1 / (n 2 +1) 1/16 1/16 1/2 bit rate generator (address 0379 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 cts 2 / rts 2 f 1 f 8 f 32 vcc rts 2 cts 2 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd 0 1 / (n 0 +1) 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 / rts 0 f 1 f 8 f 32 reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd 0 transmit/ receive unit rxd 1 1 / (n 1 +1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external rts 1 cts 1 txd 1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled cts/rts separated clock output pin select switch cts 1 / rts 1 / cts 0 / clks 1 cts/rts disabled cts0 from uart1 cts/rts selected cts/rts disabled v cc cts0 to uart0 cts 0 cts/rts disabled cts/rts separated cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 81 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 75 and figure 76 show the block diagram of the transmit/receive unit. figure 75: block diagram of uar2 (i=0,1) transmit/receive circuit figure 76: block diagram of uart2 transmit/receive circuit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit
confidential 82 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 uarti (i = 0 to 2) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 , 03a8 16 and 0378 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0 and uart1 have almost the same functions. uart0 through uart2 are almost equal in their functions with minor exceptions.table 22 shows the comparison of functions of uart0 through uart2, and figure 77, figure 78, figure 79, figure 80, and figure 81 show the registers related to uarti. note 1: only during clock synchronous serial i/o mode. note 2: only during clock synchronous serial i/o mode and 8-bit uart mode. note 3: only during uart mode. note 4: used for sim interface. table 22: comparison of functions of uart0 throught uart2 function uart0 uart1 uart2 clk polarity selection possible (note 1) possible (note 1) possible (note 1) lsb ?rst / msb ?rst selection possible (note 1) possible (note 1) possible (note 2) continuous receive mode selection possible (note 1) possible (note 1) possible (note 1) transfer clock output from multiple pins selection impossible possible (note 1) impossible separate cts/rts pins possible impossible impossible serial data logic switch impossible impossible possible (note 4) sleep mode selection possible (note 3) possible (note 3) impossible txd, rxd i/o polarity switch impossible impossible possible txd, rxd port output format cmos output cmos output cmos output parity error signal output impossible impossible possible (note 4) bus collision detection impossible impossible possible
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 83 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 77: serial i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data (note) nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate u2tb 037b 16 , 037a 16 indeterminate w r note: bit 8 is set to ??when i 2 c mode is used. (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate u2rb 037f 16 , 037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: bits 15 through 12 are set to ??when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 , 03a8 16 and 0378 16 ) are set to ?00 2 ?or the receive enable bit is set to ?? (bit 15 is set to ??when bits 14 to 12 all are set to ??) bits 14 and 13 are also set to ??when the lower byte of the uarti receive buffer register (addresses 03a6 16 , 03ae 16 and 037e 16 ) is read out. invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is ?? receive data w r receive data
confidential 84 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 78: serial i/o-related registers (2) uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid must always be ? function (during uart mode) function (during clock synchronous serial i/o mode) uart2 transmit/receive mode register symbol address when reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : (note) 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to ? 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to ? function (during uart mode) function (during clock synchronous serial i/o mode) aa a aa aa a a aa aa a a aa a aa a aa a aa a aa a aa aa a a aa a aa a aa a aa a aa a aa aa a a aa a note: bit 2 to bit 0 are set to 010 2 when i 2 c mode is used.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 85 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 79: serial i/o-related registers (3) uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be ? bit name bit symbol must always be ? note 1: set the corresponding port direction register to ?? note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) a a a a a a a a a a a a a a a a a uart2 transmit/receive control register 0 symbol address when reset u2c0 037c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit (note 3) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol note 1: set the corresponding port direction register to 0. note 2: the settings of the corresponding port register and port direction register are invalid. note 3: only clock synchronous serial i/o mode and 8-bit uart mode are valid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) nothing is assigned. this bit can neither be set nor reset. when read, the value of this bit is 0. 0 : lsb first 1 : msb first a a a a a a a a a a a a a a a a a
confidential 86 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 80: serial i/o-related registers (4) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is ?? uart2 transmit/receive control register 1 symbol address when reset u2c1 037d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must be fixed to ? 0 : output disabled 1 : output enabled a a a a a a a a a a a a a a a a a a a a a a
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 87 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 81: serial i/o-related registers (5) note: when using multiple pins to output the transfer clock, the following requirements must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 rcsp uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm 0 : cts/rts shared pin 1 : cts/rts separated 0 : cts/rts shared pin 1 : cts/rts separated separate cts/rts bit invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 a a a a a a a a a a a a a a a a
confidential 88 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 23 and table 24 list the specifications of the clock synchronous serial i/o mode. figure 82 shows the uarti transmit/receive mode register. note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: maximum 5 mbps. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. table 23: speci?cations of clock synchronous serial i/o mode (1) item speci?cation transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0) : ?=2(n+1) (note 1) ? = f1, f8, f32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 1) : input from clki pin (note 2) transmission/reception control ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty ?ag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 _ when cts function selected, cts input level = l ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1: clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16) = 1 _ transmit buffer empty ?ag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 1: interrupts requested when data transmission from error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 89 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 82: uarti transmit/receive mode register in clock synchronous serial i/o mode table 24: speci?cations of clock synchronous serial i/o mode (2) item speci?cation select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb ?rst/msb ?rst selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection (uart1) (note) uart1 transfer clock can be chosen by software to be output from one of the two pins set ? separate cts/rts pins (uart0) (note) uart0 cts and rts pins each can be assigned to separate pins ? switching serial data logic (uart2) whether to reverse data in writing to th etransmission buffer register or readin g the reception buffer register can be sele ? switching serial data logic (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed. symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be ??in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note) 0 : no reverse 1 : reverse note: usually set to ?? a aa a aa a a aa aa a a aa aa a aa a aa a aa a aa a aa a aa a a aa aa a aa a aa a a aa aa a aa a aa
confidential 90 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 table 25 lists the functions of the input/output pins during clock synchronous serial i/o mode. this table shows the pin functions when the transfer clock output from multiple pins and the separate cts/ rts pins functions are not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. the typical clock synchronous timing dia- grams are shown in figure 83. table 25: input/output pin functions in clock synchronous serial i/o mode pin name function method of selection txdi (p63, p67, p70) serial data output (outputs dummy data when performing reception only) rxdi (p62, p66, p71) serial data input port p62, p66, and p71 direction register (bits 2 and 6 at address 03ee 16 bit 1 at address 03ef 16 )= 0 (can be used as an input port when performing transmission only.) clki (p61, p65, p72) transfer clock output internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 0 transfer clock input internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 1 port p61, p65, and p72 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = 0 ctsi/ rtsi (p60,p64,p73) cts input cts/ rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 cts/ rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 port p60, p64 and p73 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = 0 rts output cts/ rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 cts/ rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1 programmable i/o port cts/ rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 91 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 83: typical transmit/receive timings in clock synchronous serial i/o mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because transfer enable bit = ? data is set in uarti transmit buffer register tc = tclk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) ? ? ? ? ? ? ? ? ctsi the above timing applies to the following settings: ?internal clock is selected. ?cts function is selected. ?clk polarity select bit = ?? ?transmit interrupt cause select bit = ?? transmit interrupt request bit (ir) ? ? stopped pulsing because cts = ? 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi ? ? ? ? ? ? ? ? receive enable bit (re) ? ? receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ?external clock is selected. ?rts function is selected. ?clk polarity select bit = ?? f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. transferred from uarti transmit buffer register to uarti transmit register meet the following conditions are met when the clk input before data reception = ? ?transmit enable bit ? ?receive enable bit ? ?dummy data write to uarti transmit buffer register shown in ( ) are bit symbols. cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software example of receive timing (when external clock is selected)
confidential 92 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (a) polarity select function as shown in figure 84, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) allows selec- tion of the polarity of the transfer clock. figure 84: polarity of transfer clock (b) lsb first/msb first select function as shown in figure 85, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 85: transfer format ?when clk polarity select bit = ? note 2: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ?when clk polarity select bit = ? note 1: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first ?when transfer format select bit = ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = ??
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 93 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (seefigure 86.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when this function is selected, uart1 cts/rts function cannot be used. figure 86: the transfer clock output from the multiple pins function usage (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 , bit 5 at address 037d 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) separate cts/rts pins function (uart0) this function works the same way as in the clock asynchronous serial i/o (uart) mode. the method of set- ting and the input/output pin functions are both the same, so refer to select function in the next section, (2) clock asynchronous serial i/o (uart) mode. note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) serial data logic switch function (uart2) when the data logic select bit (bit6 at address 037d 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 87 shows the example of serial data logic switch timing. figure 87: serial data logic switch timing microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) ? ? ? ? ? ? ?hen lsb first
confidential 94 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. table 26 and table 27 list the specifications of the uart mode. figure 88 shows the uarti transmit/receive mode register. note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: fext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1 table 26: speci?cations of uart mode (1) item speci?cation transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0) : ?/ 16(n+1) (note 1) ? = f1, f8, f32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a816, 0378 16 =1) : fext/ 16(n+1)(note 1) (note 2) transmission/reception control ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - transmit buffer empty ?ag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 - when cts function selected, cts input level = l reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - start bit detection interrupt reques t generation timing ? when transmitting - transmit interrupt cause select bits (bits 0,1 at address 03b0 16 , bit4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 , bit4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum ?ag this ?ag is set (= 1) when any of the overrun, framing, and parity errors is encountered
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 95 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 88: uarti transmit/receive mode register in uart mode table 27: speci?cations of uart mode (2) item speci?cation select function ? separate cts/rts pins (uart0) uart0 cts and rts pins each can be assigned to separate pins ? sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro-computers ?serial data logic switch (uart2) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ?txd, rxd i/o polarity switch this function is reversing txd port output and rxd port input. all i/o data level is reversed. symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit / receive mode register internal / external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note: usually set to 0.
confidential 96 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 table 28 lists the functions of the input/output pins during uart mode. this table shows the pin func- tions when the separate cts/rts pins function is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. figure 89 and figure 90 show the typical uart mode transmit and receive timing diagrams. table 28: input/output pin functions in uart mode pin name function method of selection txdi (p63, p67, p70) serial data output rxdi (p62, p66, p71) serial data input port p62, p66, and p71 direction register (bits 2 and 6 at address 03ee 16 bit 1 at address 03ef 16 )= 0 (can be used as an input port when performing transmission only.) clki (p61, p65, p72) programmable i/o port internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 0 transfer clock input internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 1 port p61, p65, and p72 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = 0 ctsi/ rtsi (p60,p64,p73) cts input cts/ rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 cts/ rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 port p60, p64 and p73 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = 0 rts output cts/ rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 cts/ rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1 programmable i/o port cts/ rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 97 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 89: typical transmit timings in uart mode transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?cts function is selected. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings : ?parity is disabled. ?two stop bits. ?cts function is disabled. ?transmit interrupt cause select bit = ?? transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = ? stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is ??when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to ?? data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. ? sp cleared to ??when interrupt request is accepted, or cleared by software ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of receive timing when transfer data is 8 bits long (parity enabled, one stop bit)
confidential 98 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 90: typical receive timing in uart mode (a) separate cts/rts pins function (uart0) with the separate cts/rts bit (bit 6 at address 03b0 16 ) is set to 1, the unit outputs/inputs the cts and rts signals on different pins. (see figure 91.) this function is valid only for uart0. note that if this function is selected, the cts/rts function for uart1 cannot be used. figure 91: the separate cts/rts pins function usage (b) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers con- nected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. d 0 start bit sampled ? receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit ? ? ? ? ? ? the above timing applies to the following settings : ?arity is disabled. ?ne stop bit. ?ts function is selected. receive interrupt request bit ? ? transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to ??when interrupt request is accepted, or cleared by software example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts0 (p6 4 ) rts0 (p6 0 ) ic
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 99 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (c) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 037d 16 ) is assigned 1, data is inverted in writing to the trans- mission buffer register or reading the reception buffer register. figure 92 shows the example of timing for switching serial data logic. figure 92: timing for switching serial data logic (d) txd, rxd i/o polarity reverse function (uart2) this function is to reverse txd pin output and rxd pin input. the level of any data to be input or output (in- cluding the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. (e) bus collision detection function (uart2) this function is to sample the output level of the txd pin and the input level of the rxd pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 93 shows the exam- ple of detection timing of a buss collision (in uart mode). figure 93: detection timing of a bus collision (in uart mode) st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) txd 2 (reverse) ? ? ? ? ? ? ?when lsb first, parity enabled, one stop bit st : start bit sp : stop bit st st sp sp transfer clock txd 2 rxd 2 bus collision detection interrupt request signal ? ? ? ? ? ? ? ? bus collision detection interrupt request bit ? ?
confidential 100 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (3) clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card i/c or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this func- tion. table 29 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). figure 94 shows the typical transmit/receive timing in uart mode. note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: fext is input from the clk2 pin. note 3: if an overrun error occurs, the uart2 receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. table 29: specifications of clock-asynchronous serial i/o mode (compliant with the sim interface) item speci?cation transfer data format ? transfer data 8-bit uart mode (bit 2 through bit 0 of address 0378 16 = 1012) ? one stop bit (bit 4 of address 0378 16 = 0) ? with the direct format chosen set parity to even (bit 5 and bit 6 of address 0378 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 037d 16 = 0). set transfer format to lsb (bit 7 of address 037c 16 = 0). ? with the inverse format chosen set parity to odd (bit 5 and bit 6 of address 0378 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 037d 16 = 1) set transfer format to msb (bit 7 of address 037c 16 = 1) transfer clock ? with the internal clock chosen (bit 3 of address 0378 16 = 0) : ? / 16 (n + 1) (note 1) : ?=f1, f8, f32 ? with an external clock chosen (bit 3 of address 0378 16 = 1) : fext / 16 (n+1) (note 1) (note 2) transmission / reception control ? disable the cts and rts function (bit 4 of address 037c 16 = 1) other settings ? the sleep mode select function is not available for uart2 ? set transmission interrupt factor to transmission completed (bit 4 of address 037d 16 = 1) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 037d 16 ) = 1 - transmit buffer empty ?ag (bit 1 of address 037d 16 ) = 0 reception start condition ? to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 037d 16 ) = 1 - detection of a start bit ? when transmitting when data transmission from the uart2 transfer register is completed (bit 4 of address 037d 16 = 1) ? when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed error detection ? overrun error (see the speci?cations of clock-asynchronous serial i/o) (note 3) ? framing error (see the speci?cations of clock-asynchronous serial i/o) ? parity error (see the speci?cations of clock-asynchronous serial i/o) - on the reception side, an l level is output from the txd2 pin by use of the parity error signal output function (bit 7 of address 037d 16 = 1) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the rxd2 pin when a transmission interrupt occurs ? the error sum ?ag (see the speci?cations of clock-asynchronous serial i/o)
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 101 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 figure 94: typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uarti transmit buffer register sp a ??level returns from txd 2 due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit txd 2 the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a ??level returns from txd 2 due to the occurrence of a parity error. rxd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 1) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 1) note: equal in waveform because txd 2 and rxd 2 are connected. transferred from uarti transmit buffer register to uarti transmit register cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software
confidential 102 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change uart0 through uart2 (a) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 037d 16 ) assigned 1, you can output an l level from the txd2 pin when a parity error is detected. in step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. figure 95 shows the output timing of the parity error signal. figure 95: output timing of the parity error signal (b) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d0 data is output from txd2. if you choose the inverse format, d7 data is inverted and output from txd2. figure 96 shows the sim interface format. figure 96: sim interface format figure 97 shows the example of connecting the sim interface with txd2 and rxd2 pulled up. figure 97: connecting the sim interface st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag ? ? ? ? ? ? ? ?lsb first ? p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p microcomputer sim card txd 2 rxd 2
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 103 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter 2.24 a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p100 to p107 function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (vref) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from vref, reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect vref. the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 30 shows the performance of the a-d converter. figure 98 shows the block diagram of the a-d converter, and figure 99 and figure 100 show the a-d converter-related registers. r table 30: performance of a-d converter item performance method of a-d conversion successive approximation (capacitive coupling ampli?er) analog input voltage (note 1) 0v to avcc (vcc) operating clock fad (note 2) vcc = 5v fad/divide-by-2 or fad/divide-by-4 or fad, fad=f(xin) resolution 8-bit or 10-bit (selectable) absolute precision vcc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? with sample and hold function (10-bit resolution)an0 to an7 input 3lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8pins (an0 to an7) a-d conversion start condition ?software trigger a-d conversion starts when the a-d conversion start ?ag changes to 1 ?external trigger (can be retriggered) a-d conversion starts when the a-d conversion start ?ag is 1 and the ad trg /p87 input changes from h to l conversion speed per pin ?without sample and hold function 8-bit resolution: 49 f ad cycles, 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles, 10-bit resolution: 33 f ad cycles note 1 does not depend on use of sample and hold function. note 2 without sample and hold function, set the 0ad frequency to 250 khz minimum; with sample and hold function, set the 0ad frequency to 1 mhz minimum.
confidential 104 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter figure 98: block diagram of a-d converter 1/2 f ad 1/2 f ad a-d conversion rate selection (03c1 16 , 03c0 16 ) (03c3 16 , 03c2 16 ) (03c5 16 , 03c4 16 ) (03c7 16 , 03c6 16 ) (03c9 16 , 03c8 16 ) (03cb 16 , 03ca 16 ) (03cd 16 , 03cc 16 ) (03cf 16 , 03ce 16 ) cks1=1 cks0=0 a-d register 0(16) a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) resistor ladder successive conversion register an 0 an 1 an 2 an 3 an 5 an 6 an 7 a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) v ref v in data bus high-order data bus low-order v ref an 4 vcut=0 av ss vcut=1 cks0=1 cks1=0 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 decoder comparator addresses
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 105 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter figure 99: a-d converter-related registers (1) a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 (note 2) md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. reserved bit always set to ? reserved bit always set to ?
confidential 106 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter figure 100: a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 xxxxxxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. nothing is assigned. these bits can neither be set nor reset. when read, their content is ?? (ja 03 um60) a-d register i symbol address when reset adi(i=0 to 7) 03c0 16 to 03cf 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) ?during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. these bits can neither be set nor reset. when read, their content is ?? ?during 8-bit mode when read, the content is indeterminate smp reserved bit always set to ? 000
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 107 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d con- version.table 31 shows the specifications of one-shot mode. figure 101 shows the a-d control reg- ister in one-shot mode. figure 101: a-d conversion register in one-shot mode table 31: one-shot mode speci?cation item speci?cation function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start ?ag stop condition ?end of a-d conversion (a-d conversion start ?ag changes to 0, except when external trigger is selected) ?writing 0 to a-d conversion start ?ag interrupt request generation timing end of a-d conversion input pin one of an0 to an7, as selected reading of result of a-d converter read a-d register corresponding to selected pin a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w r 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 0 : one-shot mode (note 2) b4 b3 ch0 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. reserved bit always set to ? reserved bit always set to ?
confidential 108 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conver- sion. table 32 shows the specifications of repeat mode. figure 102 shows the a-d control register in repeat mode. figure 102: a-d conversion register in repeat mode table 32: repeat sweep mode 0 speci?cations item speci?cation function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start ?ag stop condition writing 0 to a-d conversion start ?ag interrupt request generation timing none generated input pin one of an0 to an7, as selected reading of result of a-d converter read a-d register corresponding to selected pin a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 1 : vref connected w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 1 : repeat mode (note 2) b4 b3 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. reserved bit always set to ? reserved bit always set to ?
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 109 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 33 shows the specifications of single sweep mode. figure 103 shows the a-d control register in single sweep mode. figure 103: a-d conversion register in single sweep mode table 33: single sweep mode speci?cation item speci?cation function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start ?ag stop condition ?end of a-d conversion (a-d conversion start ?ag changes to 0, except when external trigger is selected) ?writing 0 to a-d conversion start ?ag interrupt request generation timing end of a-d conversion input pin an0 and an1 (2 pins), an0 to an3 (4 pins), an0 to an5 (6 pins), or an0 to an7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 0 invalid in single sweep mode 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 reserved bit always set to ? reserved bit always set to ?
confidential 110 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 34 shows the specifications of repeat sweep mode 0. figure 104 shows the a-d control register in repeat sweep mode 0. figure 104: a-d conversion register in repeat sweep mode 0 table 34: repeat sweep mode 0 speci?cations item speci?cation function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start ?ag stop condition writing 0 to a-d conversion start ?ag interrupt request generation timing none generated input pin an0 and an1 (2 pins), an0 to an3 (4 pins), an0 to an5 (6 pins), or an0 to an7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 0 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 reserved bit always set to ? reserved bit always set to ?
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 111 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins select- ed using the a-d sweep pin select bit. table 35 shows the specifications of repeat sweep mode 1. figure 105 show the a-d control in repeat sweep mode 1. table 35: repeat sweep mode 1 speci?cation figure 105: a-d conversion register in repeat sweep mode 1 item speci?cation function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an0 selected an0 an1 an0 an2 an0 an3, etc start condition writing 1 to a-d conversion start ?ag stop condition writing 0 to a-d conversion start ?ag interrupt request generation timing none generated input pin an0 (1 pin), an0 and an1 (2 pins), an0 to an2 (3 pins), an0 to an3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 1 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ?1?nor ?0?can be selected with the external op-amp connection mode bit. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 reserved bit always set to ? reserved bit always set to ?
confidential 112 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change a-d converter sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved with 8-bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 113 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change crc calculation circuit 2.25 crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcomputer uses a generator polynomial of crc_ccitt (x16 + x12 + x5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is completed in two machine cycles. figure 106 shows the block diagram of the crc circuit. figure 107 shows the crc-related registers. figure 106: block diagram of crc circuit figure 107: crc-related registers aaaaaa eight low-order bits aaaaaa eight high-order bits data bus high-order bits data bus low-order bits aaaaaaaaaa aaaaaaaaaa aaaaaa aaaaaa crc data register (16) crc input register (8) aaaaaaaaaa aaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 03bd 16 , 03bc 16 ) (address 03be 16 ) symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16 aa a aa aa a a
confidential 114 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change programmable i/o ports 2.26 programmable i/o ports there are 63 programmable i/o ports: p0 to p3, p6 to p8 (excluding p85), and p10. each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p85 is an input-only port and has no built-in pull-up resistance. figure 108 and figure 109 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices, they function as outputs regardless of the contents of the direction registers. unused i/o pins can be terminated as shown in figure 114 and table 36 . (1) direction registers figure 110 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these registers corresponds one for one to each i/o pin. note: there is no direction register bit for p85. (2) port registers figure 111 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 112 shows the pull-up control registers.the pull-up control register can be set to apply a pull- up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. (4) high drive capacity registers figure 113 shows the port 2 and pwm drive capacity registers. port 2 can be configured to drive an led by increasing the drive strength of the corresponding bits n-channel transistor. each pwm out- put (ta0out~ta4out) can be configured for high-drive capability by increasing the drive strength of the corresponding bits.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 115 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change programmable i/o ports figure 108: programmable i/o ports (1) p3 0 to p3 6 data bus direction register pull-up selection port latch input to respective peripheral functions p0 0 to p0 7 p1 0 to p1 7 p62, p66, p71, p73,p75, p77, p81, p82, p84, p87 data bus pull-up selection port latch direction register data bus pull-up selection output ? input to respective peripheral functions direction register port latch drive capacity control register p70, p72, p74, p76, p80 p2 0 to p2 7 data bus direction register pull-up selection port latch drive capacity control register
confidential 116 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change programmable i/o ports figure 109: programmable i/o ports (2) p10 0 to p10 7 data bus pull-up selection analog input direction register port latch p3 7 p6 3 , p6 7 p8 6 data bus pull-up selection ? output direction register port latch data bus pull-up selection output ? input to respective peripheral functions direction register port latch p6 0, p6 1, p6 4 , p6 5 p8 5 data bus nmi interrupt input
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 117 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change programmable i/o ports figure 110: direction register figure 111: port register port pi direction register (note) symbol address when reset pdi (i = 0 to 10, except 8) 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 , 03ea 16 00 16 03eb 16 , 03ee 16 , 03ef 16 , 03f3 16 , 03f6 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 10 except 8) port p8 direction register symbol address when reset pd8 03f2 16 00x00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 direction register pd8_1 port p8 1 direction register pd8_2 port p8 2 direction register pd8_3 port p8 3 direction register pd8_4 port p8 4 direction register nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. pd8_6 port p8 6 direction register pd8_7 port p8 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note: set bit 2 of protect register (address 000a 16 ) to 1 before rewriting to the port p9 direction register. a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a port pi register symbol address when reset pi (i = 0 to 10, except 8) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 register pdi_1 port pi 1 register pdi_2 port pi 2 register pdi_3 port pi 3 register pdi_4 port pi 4 register pdi_5 port pi 5 register pdi_6 port pi 6 register pdi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : l level data 1 : h level data (i = 0 to 10 except 8) port p8 register symbol address when reset p8 03f0 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 register pd8_1 port p8 1 register pd8_2 port p8 2 register pd8_3 port p8 3 register pd8_4 port p8 4 register pd8_5 port p8 5 register pd8_6 port p8 6 register pd8_7 port p8 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for p8 5 ) 0 : l level data 1 : h level data a aa a aa a a aa aa a aa a aa a a aa aa a a aa aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a
confidential 118 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change programmable i/o ports figure 112: pull-up control register figure 113: port 2 and pwm drive capacity registers pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p6 0 to p6 3 pull-up pu11 p6 4 to p6 7 pull-up pu12 p7 0 to p7 3 pull-up pu13 p7 4 to p7 7 pull-up pu14 p8 0 to p8 3 pull-up pu15 p8 4, p8 6, p8 7 pull-up pu16 p10 0 to p10 3 pull-up pu17 p10 4 to p10 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high port 2 drive capacity register symbol address when reset p2dr 03fa 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 p2dr0 p2 0 led drive capacity p2dr1 p2 1 led drive capacity p2dr2 p2 2 led drive capacity p2dr3 p2 3 led drive capacity p2dr4 p2 4 led drive capacity p2dr5 p2 5 led drive capacity p2dr6 p2 6 led drive capacity p2dr7 p2 7 led drive capacity the n-channel high-drive capacity is activated for the corresponding bit. 0 : normal drive 1 : n-channel high drive pwm drive capacity register symbol address when reset pwmdr 03fb 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pwmdr0 ta0out drive capacity pwmdr1 ta1out drive capacity pwmdr2 ta2out drive capacity pwmdr3 ta3out drive capacity pwmdr4 ta4out drive capacity high-drive capacity is activated for the corresponding taiout pin. 0 : normal drive 1 : high drive nothing is assigned. these bits can neither be set nor reset. when read, their content is 0.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 119 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change programmable i/o ports figure 114: example connection unused pins table 36: example connection of unused pins in single-chip mode pin name connection ports p0 to p3, p6 to p8, p10 (excluding p85) after setting for input mode, connect every pin to vss or vcc via a resistor; or after setting for output mode, leave these pins open xout open nmi connect via resistor to vcc (pull-up) avcc connect to vcc avss, vref, byte connect to vss port p0 to p10 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc byte av ss v ref microcomputer v cc v ss in single chip mode port p6 to p10 (except for p (input m o (input m o (output m o n x a v a v v microcomputer in memory expansion h o r a b c b h l open open
confidential 120 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change usage precautions 3.0 usage 3.1 usage precautions timer a (timer mode) ? reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff16. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. timer a (event counter mode) ? reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff16 by underflow or 000016 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. ? when stop counting in free run type, set timer again. timer a (pulse width modulation mode) ? the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. ? setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the taiout pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the taiout pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1. timer b (timer mode) ? reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff16. reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. a-d converter ? write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 s or longer. ? when changing a-d operation mode, select analog input pin again. ? using one-shot mode or single sweep mode ? read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a- d conversion interrupt request bit.) ? using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 ? use the undivided main clock as the internal cpu clock.
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 121 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change usage precautions stop mode and wait mode ? when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. interrupts ? reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and inter- rupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 is then set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. ? setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 000016. accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. ? when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning the first instruction immediately after reset, generating any interrupts including the nmi interrupt is prohibited. ? the nmi interrupt ? as for the nmi interrupt pin, an interrupt cannot be prohibited. connect it to the vcc pin if unused. ? do not get either into stop mode or into wait mode with the nmi pin set to l. built-in prom version ? all built-in prom versions high voltage is required to program to the built-in prom. be careful not to apply excessive voltage. be es- pecially careful during power-on. ? one time prom version one time prom versions shipped in blank, of which built-in proms are programmed by users, are also pro- vided. for these microcomputers, a programming test and screening are not performed in the assembly pro- cess and the following processes. to improve their reliability after programming, we recommend to program and test as flow shown in figure 115 before use.
confidential 122 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change usage precautions figure 115: programming and test ?ow for one-time prom (otp) version ? eprom version ? cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the information. ? a shield to cover the transparent window is available from mitsubishi electric corp. be careful that the shield does not touch the eprom lead pins. ? clean the transparent glass before erasing. fingers flat and paste disturb the passage of ultraviolet rays and may affect badly the erasure capability. ? the eprom version is a tool only for program development (for evaluation), and do not use it for the mass product run programming with prom programmer verify test prom programmer function check in target device note: never expose to 150 degrees celsius exceeding 100 hours. screening (note) leave at 150 degrees celsius for 40 hours
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 123 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change electrical 4.0 speci?cations 4.1 electrical note 1: when writing to eprom, cnvss rated value is -0.3 to 13 volts note 2: extended temperature version (-40 to 85 c) must be speci?ed. table 38: recommended operatingconditions (note 1) note: the total output current is the sum of all the currents ?owing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. table 37: absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage v cc =av cc -0.3 to 7.0 v av cc analog supply voltage v cc =av cc -0.3 to 7.0 v v i input voltage port0, port1, port2, port3, port6, port7, port8, port10, r eset ,v ref , x in -0.3 to vcc+0.3 v v i input voltage cnv ss -0.3 to 7.0 (note 1) v v o output voltage port0, port1, port2, port3, port6, port7, port8 (except p85), port10, r eset ,v ref ,x in v p d power dissipation ta=25 c 300 mw t opr operating ambient temperature -20 to 85 / -40 to 85 (note 2) c t stg storage temperature -65 to 150 c symbol parameter standard unit min typ max v cc supply voltage 4.1 5.0 5.5 v av cc analog supply voltage vcc v v ih high input voltage port 0, port1, port2, port3, port6, port7, port8, port10, reset, v ref ,x in , cnv ss 0.8vcc vcc v v il low input voltage port0, port1, port2, port3, port6, port7, port8, port10, reset, v ref ,x in , cnv ss 0 0.2vcc v ioh (peak) high peak output current port0, port1, port3, port6, p71, p73, p75, p77, p81 to p87, port10 -10 ma p20 to p27, p70, p72, p74, p76, p80 -20 ma ioh (avg.) high avg output current port0, port1, port3, port6, p71, p73, p75, p77, p81 to p87, port10 -5 ma p20 to p27, p70, p72, p74, p76, p80 -10 ma s ioh(peak) high peak output current p2, p3, p6, p7, p8 0 ~p8 2 -80 ma p0, p1, p8 3 ~p8 7 , p10 -80 ma s ioh (avg.) high avg output current p2, p3, p6, p7, p8 0 ~p8 2 -40 ma p0, p1, p8 3 ~p8 7 , p10 -40 ma iol (peak) low peak output current port0, port1, port3, port6, p71, p73, p75, p77, p81 to p87, port10 10 ma p20 to p27, p70, p72, p74, p76, p80 20 ma iol (avg.) low avg output current port0, port1, port3, port6, p71, p73, p75, p77, p81 to p87, port10 5ma p20 to p27, p70, p72, p74, p76, p80 10 ma s iol (peak) low peak output current p2, p3, p6, p7, p8 0 ~p8 2 80 ma p0, p1, p8 3 ~p8 7 , p10 80 ma s iol (avg. low avg output current p2, p3, p6, p7, p8 0 ~p8 2 40 ma p0, p1, p8 3 ~p8 7 , p10 40 ma f(xin) main clock input oscillation frequency 0 12 mhz
confidential 124 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change electrical table 39: electrical characteristics (vcc=5v, vss=0v, ta=25 c , f(xin) = 12mhz) symbol parameter measuring condition standard unit min typ max v oh high output voltage port0, port1, port2, port3, port6, port71, ,p73,p75,p77,port8 (except p85), port10 i oh = -5ma 3.0 v v oh high output voltage port 70,p72,p74,p76,p80 i oh = -10ma 3.0 v v oh high output voltage port0, port1, port2, port3, port6, port71, ,p73,p75,p77,port8 (except p85), port10 i oh = -5ma 3.0 v v oh high output voltage xout high power i oh = -1ma 3.0 v low power i oh = -0.5ma 3.0 v v ol low output voltage port0, port1, port2, port3, port6, port71, ,p73,p75,p77,port8 (except p85), port10 i ol = 5ma 2.0 v v ol low output voltage high-drive mode port 2 i ol = 10ma 2.0 v v ol low output voltage port 70,p72,p74,p76,p80 i ol = 10ma 2.0 v v ol low output voltage port0, port1, port2, port3, port6, port71, ,p73,p75,p77,port8 (except p85), port10 i ol = 200ua 0.45 v v ol low output voltage xout high power i oh = 1ma 2.0 v low power i oh = 0.5ma 2.0 v v t +-v t - hysteresis hold , rdy , ta 0in to ta 4in, int 0to int 2, ad trg , cts 0, cts 1, clk 0, clk 1, ta 2out to ta 4out, nmi , ki 0 to ki 15 0.2 0.8 v v t +-v t - hysteresis reset 0.2 0.8 v iih high input current port0, port1, port2, port3, port6, port7,port8, port10, xin, reset , cnvss, byte v i = 5v 5.0 ua iil low input current port0, port1, port2, port3, port6, port7, port8, port10, xin, reset , cnvss, byte v i = 0v -5.0 ua r pullup pull-up resistance port0, port1, port2, port3, port6, port7, port8, port10, xin, reset , cnvss, byte v i = 0v 30 50 167 k w r xin feedback resistance, xin 1.0 m w v ram ram retention voltage when clock is stopped 2.0 v icc power supply current(vcc = 5.5v) 1.estimated output pins open, other pins tied to vss f( xin )=12mhz square wave 83 1 ma ta=25 c clock stopped 1ua ta=85 c clock stopped 20 ua
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 125 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timing 4.2 timing timing requirements referenced to vcc = 5v, vss = 0v, ta = 25 c unless otherwise speci?ed. table 40: a-d conversion characteristics (vcc,avcc=5v, vs,avss=0v, ta=25 c , f(xin) = 12mhz) symbol parameter measuring condition standard unit min typ max - resolution v ref = vcc 10 bits - absolute accuracy sample and hold function not available v ref = vcc = 5v 3 lsb sample and hold function available (10bit) v ref = vcc = 5v 3 lsb sample and hold function available (8bit) v ref = vcc = 5v 2 lsb r ladder ladder resistance v ref = vcc 10 40 k w t conv conversion time (10bit) 2.75 m s t conv conversion time (8bit) 2.34 m s t samp sampling time 0.25 m s v ref reference voltage 2 v v ia analog input voltage 0 v ref v table 41: external clock input symbol parameter standard unit min max tc external clock input cycle time 83.3 ns tw(h) external clock input high pulse width 33 ns tw(l) external clock input low pulse width 33 ns tr external clock rise time 15 ns tf external clock fall time 15 ns table 42: timer a input (counter input in event counter mode) symbol parameter standard unit min max tc( ta )tai in input cycle time 83 ns tw( ta h )tai in input high pulse width 33 ns tw( ta l )tai in input low pulse width 33 ns table 43: timer a input (gating input in timer mode) symbol parameter standard unit min max tc( ta )tai in input cycle time 333 ns tw( ta h )tai in input high pulse width 167 ns tw( ta l )tai in input low pulse width 167 ns
confidential 126 mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer preliminary specifications rev.b specifications in this manual are tentative and subject to change timing table 49: external interrupt inti inputs table 44: timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min max tc( ta )tai in input cycle time 167 ns tw( ta h )tai in input high pulse width 83 ns tw( ta l )tai in input low pulse width 83 ns table 45: timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min max tw( ta h )tai in input high pulse width 83 ns tw( ta l )tai in input low pulse width 83 ns table 46: timer a input (up/down input in event counter mode) symbol parameter standard unit min max tc( up )tai out input cycle time 1667 ns tw( uph )tai out input high pulse width 833 ns tw( upl )tai out input low pulse width 833 ns tsu( up - tin )tai out input setup time 333 ns th( tin - up )tai out input hold time 333 ns table 47: a-d trigger input symbol parameter standard unit min max tc(ad) ad trg input cycle time (triggerable minimum) 833 ns tw(adl) ad trg input low pulse width 105 ns table 48: serial i/o symbol parameter standard unit min max tc( ck ) clki input cycle time 167 ns tw( ckh ) clki input high pulse width 83 ns tw( ckl ) clki input low pulse width 83 ns td( c - q ) txdi output delay time 80 ns th( c - q ) txdi hold time 0 ns tsu( d - c ) rxdi input setup time 30 ns th( c - d ) rxdi input hold time 90 ns symbol parameter standard unit min max tw( inh ) int i input high pulse width 208 ns tw( inl ) int i input low pulse width 208 ns
mitsubishi microcomputers m16c / 24 group single-chip 16-bit cmos microcomputer 127 confidential preliminary specifications rev.b specifications in this manual are tentative and subject to change timing diagrams- peripheral/interrupt 4.3 timing diagrams- peripheral/interrupt figure 116: peripheral / interrupt timing diagram tai in input tai out input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) t su(d?) clki txdi rxdi t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) inti input ad trg input

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