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? 2001 microchip technology inc. advance information ds41139a pic16c433 data sheet 8-bit cmos microcontroller with lin bus transceiver
ds41139a - page ii advance information ? 2001 microchip technology inc. ?all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no rep- resentation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accu- racy or use of such information, or infringement of patents or other intellectual property rights arising from such use or oth- erwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.? trademarks the microchip name, logo, pic, picmicro, picmaster, pic- start, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trade- marks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filter- lab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picdem, icepic, migratable memory, fansense, economonitor and selectmode are trade- marks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
? 2001 microchip technology inc. advance information ds41139a-page 1 pic16c433 devices included in this data sheet: pic16c433 high-performance risc cpu: only 35 single word instructions to learn all instructions are single cycle (400 ns) except for program branches which are two-cycle operating speed: dc - 10 mhz clock input dc - 400 ns instruction cycle 14-bit wide instructions 8-bit wide data path interrupt capability special function hardware registers 8-level deep hardware stack direct, indirect and relative addressing modes for data and instructions peripheral features: integrated lin bus transceiver wake-up on bus activity 12v battery operation for transceiver thermal shut-down for transceiver ground loss protection four-channel, 8-bit a/d converter 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler pin diagram special microcontroller features: in-circuit serial programming (icsp ? ) internal 4 mhz oscillator with programmable cali- bration selectable clockout power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode interrupt-on-pin change (gp0, gp1, gp3) internal pull-ups on i/o pins (gp0, gp1, gp3) internal pull-up on mclr pin selectable oscillator options: - intrc: precision internal 4 mhz oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - hs: high speed crystal/resonator - lp: power saving, low frequency crystal cmos technology: low power, high speed cmos eprom/ hv-cmos technology fully static design operating voltage range 4.5v to 5.5v industrial and extended temperature ranges low power consumption < 2 ma @ 5v, 4 mhz < 1 a typical standby current device memory program data ram pic16c433 2048 x 14 128 x 8 pdip, soic, windowed cerdip lin bus v ss v ss v dd av dd gp5/osc1/clkin gp4/osc2/an3/clkout gp3/mclr /v pp nc v bat bact v ss av ss v ss gp0/an0 gp1/an1/v ref gp2/t0cki/an2/int nc pic16c433 1 2 3 4 5 6 7 18 17 16 15 14 13 12 8 9 11 10 8-bit cmos microcontroller with lin bus transceiver
pic16c433 ds41139a-page 2 advance information ? 2001 microchip technology inc. table of contents 1.0 general description......................................................................................................... .................................... 3 2.0 pic16c433 device varieties .................................................................................................. ............................. 5 3.0 architectural overview ...................................................................................................... .................................. 7 4.0 memory organization ......................................................................................................... ............................... 11 5.0 i/o port .................................................................................................................... .......................................... 25 6.0 lin bus transceiver ......................................................................................................... ................................. 33 7.0 timer0 module............................................................................................................... .................................... 35 8.0 analog-to-digital converter (a/d) module .................................................................................... ..................... 41 9.0 special features of the cpu ................................................................................................. ............................ 49 10.0 instruction set summary .................................................................................................... ............................... 65 11.0 development support........................................................................................................ ................................ 79 12.0 electrical specifications for pic16c433 .................................................................................... ........................ 85 13.0 dc and ac characteristics - pic16c433...................................................................................... .................. 103 14.0 packaging information...................................................................................................... ............................... 107 appendix a: compatibility ...................................................................................................... ...................................111 index .......................................................................................................................... ................................................. 113 on-line support ................................................................................................................ .......................................... 117 reader response ................................................................................................................ ....................................... 118 product identification system.................................................................................................. .................................... 119 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? 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? 2001 microchip technology inc. advance information ds41139a-page 3 pic16c433 1.0 general description the pic16c433 device is a low cost, high perfor- mance, cmos, fully static, 8-bit microcontroller with integrated analog-to-digital (a/d) converter and an integrated lin bus transceiver. the lin physical layer is implemented in hardware with a voltage range from 0v to 18v, with a 40v transient capability. the lin protocol is to be implemented in firmware, which enables flexibility with future revisions of the lin protocol. all picmicro ? microcontrollers employ an advanced risc architecture. the pic16c433 microcontroller has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. a total of 35 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16c433 microcontroller typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. the pic16c433 device has 128 bytes of ram, 5 i/o pins and 1 input pin. in addition, a timer/counter is available. also a 4-channel, high-speed, 8-bit a/d is provided. the 8-bit resolution is ideally suited for appli- cations requiring low cost analog interface (i.e., thermostat control, pressure sensing, etc.) the pic16c433 device has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. the power-on reset (por), power-up timer (pwrt), and oscillator start-up timer (ost) eliminate the need for external reset circuitry. there are five oscillator configurations to choose from, including intrc preci- sion internal oscillator mode and the power saving lp (low power) oscillator mode. power saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the sleep (power-down) feature provides a power saving mode. the user can wake-up the chip from sleep through several external and internal interrupts and resets. a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software lock-up. a uv erasable windowed package version is ideal for code development, while the cost-effective one-time- programmable (otp) version is suitable for production in any volume. the customer can take full advantage of microchip ? s price leadership in otp microcontrollers, while benefiting from the otp ? s flexibility. 1.1 applications the pic16c433 microcontroller fits well in applications ranging from personal care appliances and security systems to low power remote transmitters/receivers. the eprom technology makes customizing applica- tion programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast. the small footprint packages, for through hole or surface mount- ing, make this microcontroller series perfect for applica- tions with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the pic16c433 series very versatile even in areas where no microcontroller use has been considered before (i.e., timer functions, replacement of "glue" logic and pld ? s in larger systems, coprocessor applications). 1.2 family and upward compatibility the pic16c433 product is code compatible with other members of the 14-bit pic16cxxx families. 1.3 development support the pic16c433 device is supported by a full featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full featured programmer. a ? c ? compiler and fuzzy logic support tools are also available.
pic16c433 ds41139a-page 4 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 5 pic16c433 2.0 pic16c433 device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c433 product identi- fication system section at the end of this data sheet. when placing orders, please use that page of the data sheet to specify the correct part number. for example, the pic16c433 device ? type ? is indicated in the device number: 1. c , as in pic16 c 433. these devices have eprom type memory and operate over the standard voltage range. 2. lc , as in pic16 lc 433. these devices have eprom type memory and operate over an extended voltage range. 2.1 uv erasable devices the uv erasable version, offered in windowed pack- age, is optimal for prototype development and pilot pro- grams. the uv erasable version can be erased and repro- grammed to any of the configuration modes. microchip's pro mate ? ii device programmer sup- ports the pic16c433. third party programmers also are available; refer to the microchip third party guide for a list of sources. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must also be programmed. 2.3 quick-turn-programming (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices, but with all eprom locations and configuration options already programmed by the factory. certain code and prototype verification procedures apply before produc- tion shipments are available. please contact your local microchip technology sales office for more details. 2.4 serialized quick-turn programming (sqtp sm ) devices microchip offers a unique programming service where a few user defined locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random, or sequential. serial programming allows each device to have a unique number which can serve as an entry code, password, or id number. note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be saved prior to erasing the part.
pic16c433 ds41139a-page 6 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 7 pic16c433 3.0 architectural overview the high performance of the pic16c433 family can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16c433 uses a harvard architecture, in which program and data are accessed from separate memo- ries using separate buses. this improves bandwidth over traditional von neumann architecture in which pro- gram and data are fetched from the same memory using the same bus. separating program and data buses also allow instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 14-bits wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single instruction cycle. a two-stage pipeline overlaps fetch and execu- tion of instructions (example 3-1). consequently, all instructions (35) execute in a single cycle (400 ns @ 10 mhz) except for program branches. the pic16c433 can directly or indirectly address its register files or data memory. all special function regis- ters, including the program counter, are mapped in the data memory. the pic16c433 has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ? special optimal situations ? make programming with the pic16c433 simple, yet efficient. in addition, the learn- ing curve is reduced significantly. pic16c433 devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between the data in the working register and any register file. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a file register, or an immediate con- stant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples.
pic16c433 ds41139a-page 8 advance information ? 2001 microchip technology inc. figure 3-1: pic16c433 block diagram power-up timer oscillator start-up timer eprom program memory 13 data bus 8 14 program bus instruction reg program counter ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 gpio 8 8 gp4/osc2/an3/clkout gp3/mclr/v pp gp2/t0cki/an2/int gp1/an1/v ref gp0/an0 8 3 gp5/osc1/clkin 8 level stack (13-bit) 128 bytes note 1: higher order bits are from the status register. a/d watchdog timer power-on reset 4 mhz clock internal lintx linrx device program memory data memory (ram) pic16c433 2k x 14 128 x 8 lin bus v bat bact lin bus transceiver 2k x 14
? 2001 microchip technology inc. advance information ds41139a-page 9 pic16c433 table 3-1: pic16c433 pinout description name dip pin # i/o/p type buffer type description gp0/an0 13 i/o ttl/st bi-directional i/o port/serial programming data/analog input 0. can be software programmed for internal weak pull-up and interrupt-on-pin change. this buffer is a schmitt trigger input when used in serial programming mode. gp1/an1/v ref 12 i/o ttl/st bi-directional i/o port/serial programming clock/analog input 1/ voltage reference. can be software programmed for internal weak pull-up and interrupt-on-pin change. this buffer is a schmitt trigger input when used in serial programming mode. gp2/t0cki/an2/int 11 i/o st bi-directional i/o port/analog input 2. can be configured as t0cki or external interrupt. gp3/mclr /v pp 8 i ttl/st input port/master clear (reset) input/programming voltage input. when configured as mclr , this pin is an active low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation. can be software pro- grammed for internal weak pull-up and interrupt-on-pin change. weak pull-up always on if configured as mclr . this buffer is schmitt trigger when in mclr mode. gp4/osc2/an3/clkout 7 i/o ttl bi-directional i/o port/oscillator crystal output/analog input 3. connections to crystal or resonator in crystal oscillator mode (hs, xt and lp modes only, gpio in other modes). in extrc and intrc modes, the pin output can be configured to clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. gp5/osc1/clkin 6 i/o ttl/st bi-directional io port/oscillator crystal input/external clock source input (gpio in intrc mode only, osc1 in all other oscillator modes). schmitt trigger input for extrc oscillator mode. lin bus 1 i/o hv/od high voltage bi-directional bus interface. v bat 18 p ? battery input voltage. bact 17 o ? bus activity output pin. v dd 4p ? positive supply for logic and i/o pins. v ss 2,3,14, 16 p ? ground reference for logic and i/o pins. av dd 5p ? analog positive supply. av ss 15 p ? analog ground. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, od = open drain
pic16c433 ds41139a-page 10 advance information ? 2001 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, and the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2. 3.2 instruction flow/pipelining an ? instruction cycle ? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (i.e., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ? instruction register" (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (extrc and pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock intrc modes) all instructions are single cycle, except for any program branches. these take two cycles since the fetched instruction is ? flushed ? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf gpio fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf gpio, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
? 2001 microchip technology inc. advance information ds41139a-page 11 pic16c433 4.0 memory organization 4.1 program memory organization the pic16c433 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. for the pic16c433 the first 2k x 14 (0000h-07ffh) is implemented. accessing a location above the physi- cally implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 4-1: pic16c433 program memory map and stack 4.2 data memory organization the data memory is partitioned into two banks, which contain the general purpose registers and the special function registers. bit rp0 is the bank select bit. rp0 (status<5>) = 1 bank 1 rp0 (status<5>) = 0 bank 0 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers implemented as static ram. both bank 0 and bank 1 contain special function registers. some "high use" special function registers from bank 0 are mirrored in bank 1 for code reduction and quicker access. also note that f0h through ffh on the pic16c433 is mapped into bank 0 registers 70h-7fh as common ram. 4.2.1 general purpose register file the register file can be accessed either directly or indi- rectly through the file select register fsr (section 4.5). pc<12:0> 13 0000h 0004h 0005h 07ffh 1fffh stack level 1 stack level 8 reset vector on-chip program memory call, return retfie, retlw 0800h 0400h 03ffh peripheral interrupt vector
pic16c433 ds41139a-page 12 advance information ? 2001 microchip technology inc. figure 4-2: pic16c433 register file map 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the special function registers can be classified into two sets (core and peripheral). those registers associ- ated with the ? core ? functions are described in this sec- tion, and those related to the operation of the peripheral features are described in the section of that peripheral feature. indf (1) tmr0 pcl status fsr gpio pclath intcon pir1 adres adcon0 indf (1) option pcl status fsr tris pclath intcon pie1 pcon adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address osccal f0h efh mapped in bank 0 70h
? 2001 microchip technology inc. advance information ds41139a-page 13 pic16c433 table 4-1: pic16c433 special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h (1) status irp (4) rp1 (4) rp0 to pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h gpio lintx linrx gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu 06h ? unimplemented ? ? 07h ? unimplemented ? ? 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte gpie t0if intf gpif 0000 000x 0000 000u 0ch pir1 ? adif ? ? ? ? ? ? -0-- ---- -0-- ---- 0dh ? unimplemented ? ? 0eh ? unimplemented ? ? 0fh ? unimplemented ? ? 10h ? unimplemented ? ? 11h ? unimplemented ? ? 12h ? unimplemented ? ? 13h ? unimplemented ? ? 14h ? unimplemented ? ? 15h ? unimplemented ? ? 16h ? unimplemented ? ? 17h ? unimplemented ? ? 18h ? unimplemented ? ? 19h ? unimplemented ? ? 1ah ? unimplemented ? ? 1bh ? unimplemented ? ? 1ch ? unimplemented ? ? 1dh ? unimplemented ? ? 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 reserved chs1 chs0 go/done reserved adon 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: other (non power-up) resets include external reset through mclr and watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c433; always maintain these bits clear.
pic16c433 ds41139a-page 14 advance information ? 2001 microchip technology inc. bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter ? s (pc) least significant byte 0000 0000 0000 0000 83h (1) status irp (4) rp1 (4) rp0 to pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h tris ? ? gpio data direction register --11 1111 --11 1111 86h ? unimplemented ? ? 87h ? unimplemented ? ? 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah (1,2) pclath ? ? ? write buffer for the upper 5 bits of the pc ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte gpie t0if intf gpif 0000 000x 0000 000u 8ch pie1 ? adie ? ? ? ? ? ? -0-- ---- -0-- ---- 8dh ? unimplemented ? ? 8eh pcon ? ? ? ? ? ? por ? ---- --0- ---- --u- 8fh osccal cal3 cal2 cal1 cal0 calfst calslw ? ? 0111 00-- uuuu uu-- 90h ? unimplemented ? ? 91h ? unimplemented ? ? 92h ? unimplemented ? ? 93h ? unimplemented ? ? 94h ? unimplemented ? ? 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h ? unimplemented ? ? 99h ? unimplemented ? ? 9ah ? unimplemented ? ? 9bh ? unimplemented ? ? 9ch ? unimplemented ? ? 9dh ? unimplemented ? ? 9eh ? unimplemented ? ? 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 table 4-1: pic16c433 special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ? 0 ? . note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: other (non power-up) resets include external reset through mclr and watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c433; always maintain these bits clear.
? 2001 microchip technology inc. advance information ds41139a-page 15 pic16c433 4.2.2.1 status register the status register, shown in register 4-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status reg- ister is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status regis- ter as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the "instruction set summary." register 4-1: status register (address 03h, 83h) note 1: bits irp and rp1 (status<7:6>) are not used by the pic16c433 and should be maintained clear. use of these bits as general purpose r/w bits is not recom- mended, since this may affect upward compatibility with future products. 2: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. reserved reserved r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit7 bit0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) the irp bit is reserved, always maintain this bit clear. bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. the rp1 bit is reserved, always maintain this bit clear. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf , addlw, sublw, subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf, addlw, sublw, subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c433 ds41139a-page 16 advance information ? 2001 microchip technology inc. 4.2.2.2 option register the option register is a readable and writable regis- ter, which contains various control bits to configure the tmr0/wdt prescaler, the external int interrupt, tmr0 and the weak pull-ups on gpio. register 4-2: option register (address 81h)) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer by setting bit psa (option<3>). r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 gppu intedg t0cs t0se psa ps2 ps1 ps0 bit7 bit0 bit 7 gppu : weak pull-up enable bit 1 = weak pull-ups disabled 0 = weak pull-ups enabled (gp0, gp1, gp3) bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of gp2/t0cki/an2/int pin 0 = interrupt on falling edge of gp2/t0cki/an2/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on gp2/t0cki/an2/int pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on gp2/t0cki/an2/int pin 0 = increment on low-to-high transition on gp2/t0cki/an2/int pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0> : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 2001 microchip technology inc. advance information ds41139a-page 17 pic16c433 4.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, gpio port change and exter- nal gp2/int pin interrupts. register 4-3: intcon register (address 0bh, 8bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte gpie t0if intf gpif bit7 bit0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : int external interrupt enable bit 1 = enables the external interrupt on gp2/int/t0cki/an2 pin 0 = disables the external interrupt on gp2/int/t0cki/an2 pin bit 3 gpie : gpio interrupt-on-change enable bit 1 = enables the gpio interrupt-on-change 0 = disables the gpio interrupt-on-change bit 2 t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the external interrupt on gp2/int/t0cki/an2 pin occurred (must be cleared in software) 0 = the external interrupt on gp2/int/t0cki/an2 pin did not occur bit 0 gpif : gpio interrupt-on-change flag bit 1 = gp0, gp1 or gp3 pins changed state (must be cleared in software) 0 = neither gp0, gp1 nor gp3 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c433 ds41139a-page 18 advance information ? 2001 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 4-4: pie1 register (address 8ch)) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ? adie ? ? ? ? ? ? bit7 bit0 bit 7 unimplemented: read as ? 0 ? bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds41139a-page 19 pic16c433 4.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 4-5: pir1 register (address 0ch)) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ? adif ? ? ? ? ? ? bit7 bit0 bit 7 unimplemented: read as ? 0 ? bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c433 ds41139a-page 20 advance information ? 2001 microchip technology inc. 4.2.2.6 pcon register the power control (pcon) register contains a flag bit to allow differentiation between a power-on reset (por), an external mclr reset and a wdt reset. register 4-6: pcon register (address 8eh)) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ? por ? bit7 bit0 bit 7-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2001 microchip technology inc. advance information ds41139a-page 21 pic16c433 4.2.2.7 osccal register the oscillator calibration (osccal) register is used to calibrate the internal 4 mhz oscillator. it contains four bits for fine calibration and two other bits to either increase or decrease frequency. register 4-7: osccal register (address 8fh) r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 u-0 u-0 cal3 cal2 cal1 cal0 calfst calslw ? ? bit7 bit0 bit 7-4 cal<3:0>: fine calibration ? bit 3 calfst : calibration fast 1 = increase frequency 0 = no change bit 2 calslw : calibration slow 1 = decrease frequency 0 = no change bit 1-0 unimplemented: read as ? 0 ? note: if calfst = 1 and calslw = 1, calfst has precedence. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c433 ds41139a-page 22 advance information ? 2001 microchip technology inc. 4.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 4-3 shows the two situations for the loading of the pc. the upper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower exam- ple in the figure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 4-3: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note ? implementing a table read" (an556). 4.3.2 stack the pic16c433 family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an inter- rupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execu- tion. pclath is not affected by a push or pop oper- ation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 4.4 program memory paging the pic16c433 ignores both paging bits pclath<4:3>, which are used to access program memory when more than one page is available. the use of pclath<4:3> as general purpose read/write bits for the pic16c433 is not recommended, since this may affect upward compatibility with future products. pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instructions, or the vectoring to an inter- rupt address.
? 2001 microchip technology inc. advance information ds41139a-page 23 pic16c433 4.5 indirect addressing, indf and fsr registers the indf register is not a physical register. address- ing the indf register will cause indirect addressing. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself, indirectly (fsr = ? 0 ? ) will read 00h. writing to the indf register, indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-4. however, irp is not used in the pic16c433. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 4-1. example 4-1: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue figure 4-4: direct/indirect addressing for register file map detail see figure 4-2. note 1: the rp1 and irp bits are reserved; always maintain these bits clear. data memory indirect addressing direct addressing bank select location select rp1 rp0 (1) 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used
pic16c433 ds41139a-page 24 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 25 pic16c433 5.0 i/o port as with any other register, the i/o register can be writ- ten and read under program control. however, read instructions (i.e., movf gpio,w ) always read the i/o pins independent of the pin ? s input/output modes. on reset, all i/o ports are defined as input (inputs are at hi-impedance), since the i/o control registers are all set. 5.1 gpio gpio is an 8-bit i/o register. only the low order 6 bits are used (gp<5:0>). bits 6 and 7 (lintx and linrx, respectively) are used by the lin bus transceiver peripheral. please note that gp3 is an input only pin. the configuration word can set several i/o ? s to alter- nate functions. when acting as alternate functions, the pins will read as ? 0 ? during port read. pins gp0, gp1 and gp3 can be configured with weak pull-ups and also with interrupt-on-change. the interrupt-on-change and weak pull-up functions are not pin selectable. if pin 4 (gp3), is configured as mclr , a weak pull-up is always on. interrupt-on-change for this pin is not set and gp3 will read as '0'. interrupt-on-change is enabled by setting bit gpie, intcon<3>. note that external oscillator use overrides the gpio functions on gp4 and gp5. 5.2 tris register this register controls the data direction for gpio. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the exceptions are gp3, which is input only and its tris bit will always read as '1', while gp6 and gp7 tris bits will read as ? 0 ? . upon reset, the tris register is all '1's, making all pins inputs. tris for pins gp4 and gp5 is forced to a ? 1 ? , where appropriate. writes to tris <5:4> will have an effect in extrc and intrc oscillator modes only. when gp4 is configured as clkout, changes to tris<4> will have no effect. 5.3 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1 through figure 5-5. all port pins, except gp3, which is input only, may be used for both input and output operations. for input operations, these ports are non-latching. any input must be present until read by an input instruction (i.e., movf gpio,w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit in tris must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin (except gp3) can be programmed individually as input or output. port pins lintx and linrx are used for the lin bus transceiver. these port pins are not available exter- nally on the package. users should avoid writing to pins gp6 (sda) and gp7 (scl), when not communi- cating with the lin bus transceiver. 5.4 the bact pin the bact pin can be used to wake-up the device from sleep upon bus activity. in order to wake the bus up, the bact pin has to be tied to either gp0, gp1 or gp2. these pins can be configured to wake the pic16c433 upon a change. the bact pin reflects the communica- tion on the lin bus. this pin is not latched. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. note: on a power-on reset, gp0, gp1, gp2 and gp4 are configured as analog inputs and read as '0'.
pic16c433 ds41139a-page 26 advance information ? 2001 microchip technology inc. figure 5-1: block diagram of gp0/an0 and gp1/an1/v ref pin data bus p n wr port wr tris rd tris v dd data latch dq ck q tris latch v dd p v dd d q en rd port to a/d converter analog input mode ttl input buffer i/o pin gppu v ss dq ck q v ss gp0/int (1) and gp1/int (1) note 1: wake-up on pin change interrupts for gp0 and gp1.
? 2001 microchip technology inc. advance information ds41139a-page 27 pic16c433 figure 5-2: block diagram of gp2/t0cki/an2/int pin data bus p n wr port wr tris rd tris v dd dq ck q data latch dq ck q tris latch d q en rd port to a/d converter analog input mode schmitt trigger input buffer i/o pin tmr0 clock input gp2/int v ss v dd v ss
pic16c433 ds41139a-page 28 advance information ? 2001 microchip technology inc. figure 5-3: block diagram of gp3/mclr /v pp pin p gppu v dd d q en rd port schmitt trigger input buffer input pin v ss mclren rd tris data bus program mode hv detect mclr gp3/int (1) note 1: wake-up on pin change interrupt for gp3. ttl input buffer v ss
? 2001 microchip technology inc. advance information ds41139a-page 29 pic16c433 figure 5-4: block diagram of gp4/osc2/an3/clkout pin data bus p n wr port wr tris rd tris v dd dq ck q data latch dq ck q tris latch d q en rd port to a/d converter analog input mode ttl input buffer i/o pin v ss 0 1 from osc1 oscillator circuit intrc or extrc w/o clkout intrc or extrc w/ clkout clkout (f osc /4) v dd v ss intrc/ extrc
pic16c433 ds41139a-page 30 advance information ? 2001 microchip technology inc. figure 5-5: block diagram of gp5/osc1/clkin pin table 5-1: summary of port registers data bus p n wr port wr tris rd tris v dd dq en q data latch dq en q tris latch d q en rd port intrc ttl input buffer i/o pin v ss v ss v dd to o s c 2 oscillator circuit intrc address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 85h tris ? ? gpio data direction register --11 1111 --11 1111 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 03h status irp (1) rp1 (1) rp0 to pd zdcc 0001 1xxx 000q quuu 05h gpio lintx linrx gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu legend: shaded cells not used by port registers, read as ? 0 ? , ? = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in section 9.4 for possible values. note 1: the irp and rp1 bits are reserved on the pic16c433; always maintain these bits clear.
? 2001 microchip technology inc. advance information ds41139a-page 31 pic16c433 5.5 i/o programming considerations 5.5.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs defined. for example, a bsf operation on bit5 of gpio will cause all eight bits of gpio to be read into the cpu. then, the bsf operation takes place on bit5 and gpio is written to the output latches. if another bit of gpio is used as a bi-directional i/o pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwrit- ing the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched to an output, the content of the data latch may now be unknown. reading the port register reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (i.e., bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. example 5-1 shows the effect of two sequential read- modify-write instructions on an i/o port. example 5-1: read-modify-write instructions on an i/o port ;initial gpio settings ; gpio<5:3> inputs ; gpio<2:0> outputs ; ; gpio latch gpio pins ; ---------- ---------- bcf gpio, 5 ;--01 -ppp --11 pppp bcf gpio, 4 ;--10 -ppp --11 pppp movlw 007h ; tris gpio ;--10 -ppp --10 pppp ; ;note that the user may have expected the pin ;values to be --00 pppp. the 2nd bcf caused ;gp5 to be latched as the pin value (high). a pin actively outputting a low or high should not be driven from external devices at the same time, in order to change the level on this pin ( ? wired-or ? , ? wired-and ? ). the resulting high output currents may damage the chip.
pic16c433 ds41139a-page 32 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 33 pic16c433 6.0 lin bus transceiver the pic16c433 has an integrated lin bus transceiver, which allows the microcontroller to communicate via a lin bus. the lin bus protocol is handled by the micro- controller. the conversion from 5v signal to lin bus signals is handled by the transceiver 6.1 the lin bus protocol the lin bus protocol is not described within this docu- ment. for further information regarding the lin bus protocol, please refer to www.lin-subbus.de. 6.2 lin bus interfacing the lin bus will be transmitted by toggling the lintx bit in the linintf register. data transmitted on the lin bus is read by checking the linrx bit in the porta register. for a lin bus slave software implementation, please refer to an729. 6.3 lin bus hardware interface figure 6-1shows how to implement a hardware lin bus interface for the pic16c433. an external 45v zener diode between v bb and ground, with a 500 ? resistor in series with the battery supply and the v bb pin, protects the pic16c433 from power transients. an external reverse battery blocking diode is used to provide polarity protection. 6.4 thermal shut-down in thermal shut-down, the lin bus output is disabled instantaneously. the output transistor is turned off, regardless of the input level at pin lintx bit and only a limited current can flow into the receiver connected to the lin bus pin. 6.5 wake-up from sleep upon bus activity the pic16c433 can wake-up from sleep upon bus activity in the following way: 1. connect bact to gp2/t0cki/an2/int. the bact signal is a mirror of the lin bus. this signal can be routed to gp2/t0cki/an2/int pin. the gp2/ t0cki/an2/int interrupt wakes up the device from sleep. figure 6-1: typical lin bus application note: tlinrx must be set to ? 1 ? at all times. rmaster = 900 ? to 1.1k ? lin bus 10nf 5.0nf 27v 500 ? 45v v bb v dd v ss v bat lin bus +5 +12 pic16c433 rslave = 20k ? to 42k ?
pic16c433 ds41139a-page 34 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 35 pic16c433 7.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock figure 7-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing bit t0cs (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles (figure 7-2 and figure 7-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the bit t0se (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are dis- cussed in detail in section 7.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the prescaler assignment is controlled in software by con- trol bit psa (option<3>). clearing bit psa will assign the prescaler to the timer0 module. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. section 7.3 details the operation of the prescaler. 7.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. see figure 7-4 for timer0 interrupt timing. figure 7-1: timer0 block diagram figure 7-2: timer0 timing: internal clock/no prescale note 1: tocs, tose, psa, ps<2:0> (option<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 7-6 for detailed block diagram). gp2/tocki/ tose 0 1 1 0 an2/int tocs f osc /4 programmable prescaler sync with internal clocks tmr0 (2 t cy delay) data bus 8 psa ps<2:0> set interrupt flag bit t0if on overflow 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t0 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed
pic16c433 ds41139a-page 36 advance information ? 2001 microchip technology inc. figure 7-3: timer0 timing: internal clock/prescale 1:2 figure 7-4: timer0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout (3) timer0 t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h flow interrupt latency (2) note 1: interrupt flag bit t0if is sampled here (every q1). 2: interrupt latency = 3t cy where t cy = instruction cycle time. 3: clkout is available only in the intrc and extrc oscillator modes.
? 2001 microchip technology inc. advance information ds41139a-page 37 pic16c433 7.2 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 7.2.1 external clock synchronization when no prescaler is used, the external clock input is used as the clock source. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 7-5). there- fore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler, so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns), divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41 and 42 in the electrical specification of the desired device. 7.2.2 tmr0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 7-5 shows the delay from the external clock edge to the timer incrementing. figure 7-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling (3) (1) note 1: delay from clock input change to timer0 increment is 3t osc to 7t osc (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4t osc max. 2: external clock if no prescaler selected; prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs.
pic16c433 ds41139a-page 38 advance information ? 2001 microchip technology inc. 7.3 pre scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 7-6). for simplicity, this counter is being referred to as ? prescaler ? throughout this data sheet. note that there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the psa and ps<2:0> bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (i.e., clrf 1, movwf 1, bsf 1,x ...., etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the pres- caler is not readable or writable. figure 7-6: block diagram of the timer0/wdt prescaler gp2/t0cki/ t0se an2/int m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are (option<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs
? 2001 microchip technology inc. advance information ds41139a-page 39 pic16c433 7.3.1 switching prescaler assignment the prescaler assignment is fully under software con- trol (i.e., it can be changed ? on-the-fly ? during program execution). example 7-1: changing prescaler (timer0 wdt) bcf status, rp0 ;bank 0 clrf tmr0 ;clear tmr0 & prescaler bsf status, rp0 ;bank 1 clrwdt ;clears wdt movlw b?xxxx1xxx? ;select new prescale movwf option_reg ;value & wdt bcf status, rp0 ;bank 0 to change prescaler from the wdt to the timer0 mod- ule, use the sequence shown in example 7-2. example 7-2: changing prescaler (wdt timer0) clrwdt ;clear wdt and ;prescaler bsf status, rp0 ;bank 1 movlw b?xxxx0xxx? ;select tmr0, new ;prescale value and movwf option_reg ;clock source bcf status, rp0 ;bank 0 table 7-1: registers associated with timer0 note: to avoid an unintended device reset, the following instruction sequence (shown in example 7-1) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 01h tmr0 timer0 module ? s register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte gpie t0if intf gpif 0000 000x 0000 000u 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h tris ? ? tris5 tris4 tris3 tris2 tris1 tris0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic16c433 ds41139a-page 40 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 41 pic16c433 8.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has four analog inputs. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to applica- tion note an546 for use of a/d converter). the output of the sample and hold is the input into the converter, which generates the result via successive approxima- tion. the analog reference voltage is software select- able to either the device ? s positive supply voltage (v dd ), or the voltage level on the gp1/an1/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. the a/d module has three registers. these registers are: a/d result register (adres) a/d control register 0 (adcon0) a/d control register 1 (adcon1) the adcon0 register, shown in figure 8-1, controls the operation of the a/d module. the adcon1 regis- ter, shown in figure 8-2, configures the functions of the port pins. the port pins can be configured as analog inputs (gp1 can also be a voltage reference) or as digital i/o. register 8-1: adcon0 register (address 1fh) note 1: if the port pins are configured as analog inputs (reset condition), reading the port ( movf gpio,w ) results in reading '0's. 2: changing adcon1 register can cause the gpif and intf flags to be set in the intcon register. these interrupts should be disabled prior to modifying adcon1. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 reserved chs1 chs0 go/done reserved adon bit7 bit0 bit 7-6 adcs<1:0>: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from an rc oscillation) bit 5 reserved bit 4-3 chs<1:0>: analog channel select bits 00 = channel 0, (gp0/an0) 01 = channel 1, (gp1/an1) 10 = channel 2, (gp2/an2) 11 = channel 3, (gp4/an3) bit 2 go/done : a/d conversion status bit if adon = 1: 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 reserved bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
pic16c433 ds41139a-page 42 advance information ? 2001 microchip technology inc. register 8-2: adcon1 register (address 9fh u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pcfg2 pcfg1 pcfg0 bit7 bit0 bit 7-2 unimplemented: read as ? 0 ? bit 1-0 pcfg<2:0>: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por reset ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown a = analog input d = digital i/o note 1: value on reset. 2: any instruction that reads a pin configured as an analog input will read a '0'. pcfg<2:0> gp4 gp2 gp1 gp0 v ref 000 (1) a aaav dd 001 aav ref agp1 010 d aaav dd 011 dav ref agp1 100 ddaav dd 101 ddv ref agp1 110 dddav dd 111 ddddv dd
? 2001 microchip technology inc. advance information ds41139a-page 43 pic16c433 the adres register contains the result of the a/d conversion. when the a/d conversion is complete, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared and a/d interrupt flag bit adif (pie1<6>) is set. the block diagrams of the a/d module are shown in figure 8-1. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine sample time, see section 8.1. after this acquisition time has elapsed, the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: configure analog pins/voltage reference/ and digital i/o (adcon1 and tris) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for the next conversion, go to step 1, step 2, or step 3, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 8-1: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg<2:0> chs<1:0> gp4/an3 gp0/an0 gp2/an2 gp1/an1/v ref 11 10 01 00 a/d converter
pic16c433 ds41139a-page 44 advance information ? 2001 microchip technology inc. 8.1 a/d sampling requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 8-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 8-2. the maximum recommended imped- ance for analog sources is 10 k ? . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 8-1 may be used. this equation assumes that 1/2 lsb error is used (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 8-1: a/d minimum charging time v hold = (v ref - (v ref /512)) (1 - e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(51.2 pf)(1 k ? + r ss + r s ) ln(1/511) example 8-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following system assumptions. rs = 10 k ? 1/2 lsb error v dd = 5v rss = 7 k ? temperature (system max.) = 50 c v hold = 0 @ t = 0 example 8-1: calculating the minimum required sample time t acq = internal amplifier settling time + holding capacitor charging time + temperature coefficient t acq =5 s + tc + [(temp - 25 c)(0.05 s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/512) -51.2 pf (1 k ? + 7 k ? + 10 k ? ) ln(0.0020) -51.2 pf (18 k ? ) ln(0.0020) -0.921 s (-6.2146) 5.724 s t acq =5 s + 5.724 s + [(50 c - 25 c)(0.05 s/ c)] 10.724 s + 1.25 s 11.974 s figure 8-2: analog input model note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specifi- cation. 4: after a conversion has completed, a 2.0 t ad delay must complete before acquisition can begin again. during this time, the holding capacitor is not con- nected to the selected a/d input channel. c pin va r s ra x 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 ( k ? ) v dd = 51.2 pf 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
? 2001 microchip technology inc. advance information ds41139a-page 45 pic16c433 8.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.5 t ad per 8-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: 2t osc 8t osc 32t osc internal adc rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. if the minimum t ad time of 1.6 s can not be obtained, t ad should be 8 s for preferred operation. table 8-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 8.3 configuring analog port pins the adcon1 and tris registers control the opera- tion of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<2:0> bits and the tris bits. table 8-1: t ad vs. device operating frequencies note 1: when reading the port register, all pins configured as analog input channel will read as cleared (a low level). pins config- ured as digital inputs, will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin that is defined as a digital input (including the an<3:0> pins) may cause the input buffer to consume cur- rent that is out of the devices specification. ad clock source (t ad ) device frequency operation adcs<1:0> 4 mhz 1.25 mhz 333.33 khz 2t osc 00 500 ns (2) 1.6 s6 s 8t osc 01 2.0 s6.4 s 24 s (3) 32t osc 10 8.0 s 25.6 s (3) 96 s (3) internal adc rc oscillator (5) 11 2 - 6 s (1,4) 2 - 6 s (1,4) 2 - 6 s (1) note 1: the rc source has a typical t ad time of 4 s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: while in rc mode, with device frequency above 1 mhz, conversion accuracy is out of specification. 5: for extended voltage devices (lc), please refer to electrical specifications section.
pic16c433 ds41139a-page 46 advance information ? 2001 microchip technology inc. 8.4 a/d conversions example 8-2 shows how to perform an a/d conversion. the gpio pins are configured as analog inputs. the analog reference (v ref ) is the device v dd . the a/d interrupt is enabled and the a/d conversion clock is f rc . the conversion is performed on the gp0 channel. clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d con- version sample. that is, the adres register will con- tinue to contain the value of the last completed conversion (or the last value written to the adres reg- ister). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, an acquisition is automatically started on the selected channel. example 8-2: doing an a/d conversion bsf status, rp0 ; select page 1 clrf adcon1 ; configure a/d inputs bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select page 0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input channel has elapsed. ; then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the a/d conversion. note: the go/done bit should not be set in the same instruction that turns on the a/d.
? 2001 microchip technology inc. advance information ds41139a-page 47 pic16c433 8.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs<1:0> = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared, and the result loaded into the adres register. if the a/ d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 8.6 a/d accuracy/error the overall accuracy of the a/d is less than 1 lsb for v dd = 5v 10% and the analog v ref = v dd . this over- all accuracy includes offset error, full scale error, and integral error. the a/d converter is monotonic over the full v dd range. the resolution and accuracy may be less when either the analog reference (v dd ) is less than 5.0v, or when the analog reference (v ref ) is less than v dd . the maximum pin leakage current is specified in the device data sheet electrical specification, parameter #d060. in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high fre- quencies, t ad should be derived from the device oscil- lator. t ad must not violate the minimum and should be 8 s for preferred operation. this is because t ad , when derived from t osc , is kept away from on-chip phase clock transitions. this reduces, to a large extent, the effects of digital switching noise. this is not possi- ble with the rc derived clock. the loss of accuracy due to digital switching noise can be significant if many i/o pins are active. in systems where the device will enter sleep mode after the start of the a/d conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep is stopped. this method gives high accuracy. 8.7 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adres register is not modified for a reset. the adres register will contain unknown data after a power-on reset. 8.8 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.2v, then the accuracy of the conver- sion is out of specification. an external rc filter is sometimes added for anti- aliasing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 10 k ? recommended specification. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 8.9 transfer function the ideal transfer function of the a/d converter is as follows: the first transition occurs when the analog input voltage (v ain ) is 1 lsb (or analog v ref /256) (figure 8- 3). figure 8-3: a/d transfer function note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs<1:0> = 11 ). to perform an a/d conversion in sleep, the go/done bit must be set, followed by the sleep instruction. note: for the pic16c433, care must be taken when using the gp4 pin in a/d conver- sions due to its proximity to the osc1 pin. digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb (full scale) analog input voltage
pic16c433 ds41139a-page 48 advance information ? 2001 microchip technology inc. figure 8-4: flow chart of a/d operation table 8-2: summary of a/d registers acquire adon = 0 adon = 0? go = 0? a/d clock go = 0 adif = 0 abort conversion wait 2 t ad wake-up yes no yes no no yes finish conversion go = 0 adif = 1 device in no yes finish conversion go = 0 adif = 1 wait 2 t ad stay in sleep selected channel = rc? sleep no yes instruction? start of a/d conversion delayed 1 instruction cycle from power-down a/d yes no wait 2 t ad finish conversion go = 0 adif = 1 sleep? sleep? sleep power-down a/d address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 0bh/8bh intcon (1) gie peie t0ie inte gpie t0if intf gpif 0000 000x 0000 000u 0ch pir1 ? adif ? ? ? ? ? ? -0-- ---- -0-- ---- 8ch pie1 ? adie ? ? ? ? ? ? -0-- ---- -0-- ---- 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 reserved chs1 chs0 go/done reserved adon 0000 0000 0000 0000 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h gpio lintx linrx gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu 85h tris ? ? tris5 tris4 tris3 tris2 tris1 tris0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for a/d conversion. note 1: these registers can be addressed from either bank.
? 2001 microchip technology inc. advance information ds41139a-page 49 pic16c433 9.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real- time applications. the pic16c433 device has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offer code protection. these are: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming the pic16c433 has a watchdog timer, which can be shut-off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which pro- vides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the intrc/extrc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits is used to select various options. 9.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h- 3fffh), which can be accessed only during programming. register 9-1: configuration word cp1 cp0 cp1 cp0 cp1 cp0 mclre cp1 cp0 pwrte wdte fosc2 fosc1 fosc0 register: config address 2007h bit13 bit0 bit 13-8, cp<1:0>: code protection bit pairs (1) 6-5: 11 = code protection off 10 = locations 400h through 7feh code protected 01 = locations 200h through 7feh code protected 00 = all memory is code protected bit 7: mclre: master clear reset enable bit 1 = master clear enabled 0 = master clear disabled bit 4: pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 3: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0: fosc<2:0>: oscillator selection bits 111 = extrc, clockout on osc2 110 = extrc, osc2 is i/o 101 = intrc, clockout on osc2 100 = intrc, osc2 is i/o 011 = invalid selection 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator note 1: all of the cp<1:0> pairs have to be given the same value to enable the code protection scheme listed.
pic16c433 ds41139a-page 50 advance information ? 2001 microchip technology inc. 9.2 oscillator configurations 9.2.1 oscillator types the pic16c433 can be operated in seven different oscillator modes. the user can program three configu- ration bits (f osc <2:0>) to select one of these seven modes: lp: low power crystal hs: high speed crystal/resonator xt: crystal/resonator intrc*: internal 4 mhz oscillator extrc*: external resistor/capacitor *can be configured to support clkout 9.2.2 crystal oscillator/ceramic resonators in xt, hs or lp modes, a crystal or ceramic resonator is connected to the gp5/osc1/clkin and gp4/osc2 pins to establish oscillation (figure 9-1). the pic16c433 oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in xt, hs or lp modes, the device can have an external clock source drive the gp5/osc1/ clkin pin (figure 9-2). figure 9-1: crystal operation or ceramic resonator (xt, hs or lp osc configuration) figure 9-2: external clock input operation (xt, hs or lp osc configuration) table 9-1: capacitor selection for ceramic resonators - pic16c433 table 9-2: capacitor selection for crystal oscillator - pic16c433 note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: rf varies with the oscillator mode selected (approx. value = 10 m ? ). c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic r s (2) pic16c433 clock from ext. system osc1 osc2 pic16c433 open osc type resonator freq cap. range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 22-100 pf 15-68 pf 15-68 pf 22-100 pf 15-68 pf 15-68 pf hs 4.0 mhz 8.0 mhz 10.0 mhz 15-68 pf 10-68 pf 10-22 pf 15-68 pf 10-68 pf 10-22 pf these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. osc type resonator freq cap. range c1 cap. range c2 lp 32 khz (1) 100 khz 200 khz 15 pf 15-30 pf 15-30 pf 15 pf 30-47 pf 15-82 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-47 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15-30 pf 15-47 pf hs 4 mhz 8 mhz 10 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf note 1: for v dd > 4.5v, c1 = c2 30 pf is recommended. these values are for design guidance only. r s may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specifi- cation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
? 2001 microchip technology inc. advance information ds41139a-page 51 pic16c433 9.2.3 external crystal oscillator circuit either a pre-packaged oscillator, or a simple oscillator circuit with ttl gates, can be used as an external crys- tal oscillator circuit. pre-packaged oscillators provide a wide operating range and better stability. a well designed crystal oscillator will provide good perfor- mance with ttl gates. two types of crystal oscillator circuits can be used; one with parallel resonance, or one with series resonance. figure 9-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiome- ters bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 9-3: external parallel resonant crystal oscillator circuit figure 9-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator cir- cuit. the 330 ? resistors provide the negative feedback to bias the inverters in their linear region. figure 9-4: external series resonant crystal oscillator circuit 9.2.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit, due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 9-5 shows how the r/c combination is con- nected to the pic16c433. for r ext values below 2.2 k ? , the oscillator operation may become unstable or stop completely. for very high r ext values (i.e., 1 m ? ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. the variation is greater for larger r (since leakage cur- rent variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). figure 9-5: external rc oscillator mode 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c433 clkin to other devices 330 74as04 74as04 pic16c433 clkin to other devices xtal 330 74as04 0.1 f v dd r ext c ext v ss osc1 internal clock pic16c433 n osc2/clkout f osc /4
pic16c433 ds41139a-page 52 advance information ? 2001 microchip technology inc. 9.2.5 internal 4 mhz rc oscillator the internal rc oscillator provides a fixed 4 mhz (nom- inal) system clock at v dd = 5v and 25 c. see section 13.0 for information on variation over voltage and temperature. in addition, a calibration instruction is programmed into the last address of the program memory, which con- tains the calibration value for the internal rc oscillator. this value is programmed as a retlw xx instruction, where xx is the calibration value. in order to retrieve the calibration value, issue a call yy instruction, where yy is the last location in program memory. con- trol will be returned to the user ? s program with the cali- bration value loaded into the w register. the program should then perform a movwf osccal instruction to load the value into the internal rc oscillator trim register. osccal, when written to with the calibration value, will ? trim ? the internal oscillator to remove process variation from the oscillator frequency. bits <7:4>, cal<3:0> are used for fine calibration, while bit3, calfst, and bit2, calslw, are used for more coarse adjustment. adjusting cal<3:0> from 0000 to 1111 yields a higher clock speed. set calfst = 1 for greater increase in frequency, or set calslw = 1 for greater decrease in frequency. note that bits 1 and 0 of osccal are unim- plemented and should be written as 0, when modifying osccal for compatibility with future devices. 9.2.6 clkout the pic16c433 can be configured to provide a clock out signal (clkout) on pin 3, when the configuration word address (2007h) is programmed with f osc 2, f osc 1, and f osc 0, equal to 101 for intrc or 111 for extrc. the oscillator frequency, divided by 4, can be used for test purposes or to synchronize other logic. 9.3 reset the pic16c433 differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (normal operation) some registers are not affected in any reset condi- tion; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ? reset state ? on power-on reset (por), mclr reset, wdt reset, and mclr reset during sleep. they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differently in different reset situations, as indicated in table 9-5. these bits are used in software to determine the nature of the reset. see table 9-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 9-6. the pic16c433 has a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. when mclr is asserted, the state of the osc1/clkin and clkout/osc2 pins are as follows: note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be saved prior to erasing the part. table 9-3: clkin/clkout pin states when mclr asserted oscillator mode osc1/clkin pin osc2/clkout pin extrc, clkout on osc2 osc1 pin is tri-stated and driven by external circuit osc2 pin is driven low extrc, osc2 is i/o osc1 pin is tri-stated and driven by external circuit osc2 pin is tri-state input intrc, clkout on osc2 osc1 pin is tri-state input osc2 pin is driven low intrc, osc2 is i/o osc1 pin is tri-state input osc2 pin is tri-state input
? 2001 microchip technology inc. advance information ds41139a-page 53 pic16c433 figure 9-6: simplified block diagram of on-chip reset circuit s r q weak pull-up gp3/mclr /v pp v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt time-out power-on reset ost pwrt chip_reset 10-bit ripple-counter enable ost enable pwrt sleep see table 9-4 for time-out situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin. clkin pin 10-bit ripple-counter mclre internal mclr pin
pic16c433 ds41139a-page 54 advance information ? 2001 microchip technology inc. 9.4 power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) 9.4.1 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. to take advantage of the por, just tie the mclr pin through a resistor to v dd . this will eliminate exter- nal rc components usually needed to create a power- on reset. a maximum rise time for v dd is specified. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, ...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, " power-up trouble shooting ." 9.4.2 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up only, from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt ? s time delay allows v dd to rise to an accept- able level. a configuration bit is provided to enable/dis- able the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. 9.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscil- lator, or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 9.4.4 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired; then, ost is activated. the total time-out will vary, based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 9-7, figure 9-8, and figure 9-9 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (figure 9-9). this is useful for testing purposes, or to synchronize more than one pic16c433 device operat- ing in parallel. 9.4.5 power control/status register (pcon) the power control/status register, pcon (address 8eh), has one bit. bit1 is por (power-on reset). it is cleared on a power- on reset and is unaffected otherwise. the user sets this bit following a power-on reset. on subsequent resets, if por is ? 0 ? , it will indicate that a power-on reset must have occurred. table 9-4: time-out in various situations table 9-5: status/pcon bits and their significance legend: u = unchanged, x = unknown oscillator configuration power-up wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 1024t osc intrc, extrc 72 ms ?? por to pd 011 power-on reset 00x illegal, to is set on por 0x0 illegal, pd is set on por 10u wdt reset 100 wdt wake-up 1uu mclr reset during normal operation 110 mclr reset during sleep or interrupt wake-up from sleep
? 2001 microchip technology inc. advance information ds41139a-page 55 pic16c433 table 9-6: reset condition for special registers table 9-7: initialization conditions for all registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0- mclr reset during normal operation 000h 000u uuuu ---- --u- mclr reset during sleep 000h 0001 0uuu ---- --u- wdt reset during normal operation 000h 0000 uuuu ---- --u- wdt wake-up from sleep pc + 1 uuu0 0uuu ---- --u- interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --u- legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). register power-on reset mclr reset wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf 0000 0000 0000 0000 0000 0000 tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu gpio 11xx xxxx 11uu uuuu 11uu uuuu pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uqqq (1) pir1 -0-- ---- -0-- ---- -q-- ---- (4) adcon0 0000 0000 0000 0000 uuuu uquu (5) option 1111 1111 1111 1111 uuuu uuuu tris --11 1111 --11 1111 --uu uuuu pie1 -0-- ---- -0-- ---- -u-- ---- pcon ---- --0- ---- --u- ---- --u- osccal 0111 00-- uuuu uu-- uuuu uu-- adcon1 ---- -000 ---- -000 ---- -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in intcon and pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 9-5 for reset value for specific condition. 4: if wake-up was due to a/d completing then bit 6 = 1 , all other interrupts generating a wake-up will cause bit 6 = u . 5: if wake-up was due to a/d completing then bit 3 = 0 , all other interrupts generating a wake-up will cause bit 3 = u .
pic16c433 ds41139a-page 56 advance information ? 2001 microchip technology inc. figure 9-7: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 9-8: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 9-9: time-out sequence on power-up (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset pwrt time-out v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
? 2001 microchip technology inc. advance information ds41139a-page 57 pic16c433 figure 9-10: external power-on reset circuit (for slow v dd power-up) figure 9-11: external brown-out protection circuit 3 figure 9-12: external brown-out protection circuit 1 figure 9-13: external brown-out protection circuit 2 note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that voltage drop across r does not violate the device ? s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown due to electrostatic discharge (esd), or electrical overstress (eos). c r1 r d v dd mclr pic16c433 this brown-out protection circuit employs microchip technology ? s mcp809 microcontroller supervisor. the mcp8xx and mcp1xx families of supervisors provide push-pull and open collector outputs, with both high and low active reset pins. there are 7 different trip point selections to accommodate 5v and 3v systems. mclr pic16c433 v dd v ss rst mcp809 v dd v dd bypass capacitor note 1: this circuit will activate reset when v dd goes below (vz + 0.7v), where vz = zener voltage. 2: resistors should be adjusted for the character- istics of the transistor. v dd 33k 10k 4.3k v dd mclr pic16c433 note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level, such that: 2: resistors should be adjusted for the charac- teristics of the transistor. v dd r1 r1 + r2 = 0.7v v dd r2 4.3k pic16c433 r1 q1 v dd mclr
pic16c433 ds41139a-page 58 advance information ? 2001 microchip technology inc. 9.5 interrupts there are four sources of interrupt: the interrupt control register (intcon) records indi- vidual interrupt requests in flag bits. it also has individ- ual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. when bit gie is enabled and an interrupt ? s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. the gie bit is cleared on reset. the ? return-from-interrupt ? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the gp2/int, gpio port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flag adif, is contained in the special function register pir1. the corresponding interrupt enable bit is contained in special function register pie1, and the peripheral interrupt enable bit is contained in special function register intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid repeated interrupts. for external interrupt events, such as gpio change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends on when the interrupt event occurs (figure 9-15). the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. figure 9-14: interrupt logic interrupt sources tmr0 overflow interrupt external interrupt gp2/int pin gpio port change interrupts (pins gp0, gp1, gp3) a/d interrupt note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit, or the gie bit. gpif gpie t0if t0ie gie wake-up (if in sleep mode) interrupt to cpu peie adif adie intf inte
? 2001 microchip technology inc. advance information ds41139a-page 59 pic16c433 figure 9-15: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? 1 4 5 1 note 1: intf flag is sampled here (every q1). 2: interrupt latency = 3-4 t cy where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle, or a 2-cycle instruction. 3: clkout is available only in intrc and extrc oscillator modes. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set any time during the q4-q1 cycles. 2 3
pic16c433 ds41139a-page 60 advance information ? 2001 microchip technology inc. 9.5.1 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>) (see section 7.0). the flag bit t0if (intcon<2>) will be set, regardless of the state of the enable bits. if used, this flag must be cleared in software. 9.5.2 int interrupt external interrupt on gp2/int pin is edge triggered; either rising if bit intedg (option<6>) is set, or fall- ing, if the intedg bit is clear. when a valid edge appears on the gp2/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the pro- cessor branches to the interrupt vector following wake- up. see section 9.8 for details on sleep mode. 9.5.3 gpio intcon change an input change on gp3, gp1 or gp0 sets flag bit gpif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit gpie (intcon<3>) (section 5.1) . this flag bit gpif (intcon<0>) will be set, regardless of the state of the enable bits. if used, this flag must be cleared in software. 9.6 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w register and status register). this will have to be implemented in software. example 9-1 shows the storing and restoring of the status and w registers. the register, w_temp, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1). example 9-2 shows the saving and restoring of status and w using ram locations 0x70 - 0x7f. w_temp is defined at 0x70 and status_temp is defined at 0x71. the example: a) stores the w register. b) stores the status register in bank 0. c) executes the isr code. d) restores the status register (and bank select bit). e) restores the w register. f) returns from interrupt. example 9-1: saving status and w registers using general purpose ram (0x20 - 0x6f) movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w bcf status,rp0 ;change to bank zero, regardless of current bank movwf status_temp ;save status to bank zero status_temp register : :(isr) : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w retfie ;return from interrupt example 9-2: saving status and w registers using shared ram (0x70 - 0x7f) movwf w_temp ;copy w to temp register (bank independent) movf status,w ;move status register into w movwf status_temp ;save contents of status register : :(isr) : movf status_temp,w ;retrieve copy of status register movwf status ;restore pre-isr status register contents swapf w_temp,f ; swapf w_temp,w ;restore pre-isr w register contents retfie ;return from interrupt
? 2001 microchip technology inc. advance information ds41139a-page 61 pic16c433 9.7 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscil- lator, which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clk- out pins of the device has been stopped, for example, by execution of a sleep instruction. during normal oper- ation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watchdog timer wake-up). the wdt can be permanently disabled by clearing configuration bit wdte (section 9.1). 9.7.1 wdt period the wdt has a nominal time-out period of 18 ms (with no prescaler). the time-out periods vary with tempera- ture, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control, by writing to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out early and generating a premature device reset condition. the to bit in the status register will be cleared upon a watchdog timer time-out. 9.7.2 wdt programming considerations it should also be taken into account that under worst case conditions (v dd = min., temperature = max., and max. wdt prescaler), it may take several seconds before a wdt time-out occurs. see example 7-1 and example 7-2 for changing pres- caler between wdt and timer0. figure 9-16: watchdog timer block diagram table 9-8: summary of watchdog timer registers note: when the prescaler is assigned to the wdt, always execute a clrwdt instruc- tion before changing the prescale value, otherwise a wdt reset may occur. from tmr0 clock source (figure 7-5) to tmr0 (figure 7-5) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps<2:0> 0 1 mux psa wdt time-out note: psa and ps<2:0> are bits in the option register. 8 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) mclre cp1 cp0 pwrte wdte fosc2 fosc1 fosc0 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 9-1 for operation of these bits. not all cp0 and cp1 bits are shown.
pic16c433 ds41139a-page 62 advance information ? 2001 microchip technology inc. 9.8 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input, if enabled, should also be at v dd or v ss , for lowest current consumption. the contribution from on-chip pull-ups on gpio should be considered. the mclr pin, if enabled, must be at a logic high level (v ihmc ). 9.8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. gp2/int interrupt, interrupt gpio port change or some peripheral interrupts. 4. lin bus activity (connect bact to gp2/t0cki/ an2/int pin). external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupt can wake the device from sleep: 1. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts since dur- ing sleep, no on-chip q clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 9.8.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake-up from sleep . the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction. 9.8.3 wake-up from sleep upon bus activity the pic16c433 can be woken up upon bus activity on the lin bus. this is done by connecting the bact pin with either gp0, gp1 or gp2. the pin which will be connected to the bact pin has to be configured to wake the microcontroller up from sleep.
? 2001 microchip technology inc. advance information ds41139a-page 63 pic16c433 figure 9-17: wake-up from sleep through interrupt 9.9 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 9.10 id locations four memory locations (2000h - 2003h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. 9.11 in-circuit serial programming pic16c433 microcontrollers can be serially pro- grammed, while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. the device is placed into a program/verify mode by hold- ing the gp1 and gp0 pins low, while raising the mclr (v pp ) pin from v il to v ihh (see programming specifica- tion). gp1 (clock) becomes the programming clock and gp0 (data) becomes the programming data. both gp0 and gp1 are schmitt trigger inputs in this mode. after reset, and if the device is placed into program- ming/verify mode, the program counter (pc) is at loca- tion 00h. a 6-bit command is then supplied to the device. depending on the command, 14-bits of pro- gram data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c433 programming specifications. figure 9-18: typical in-circuit serial programming connection q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) gpio pin gpif flag (intcon<0>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc)=sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 3) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay will not be there for intrc and extrc osc mode. 3: gie = ? 1 ? assumed. in this case, after wake-up, the processor jumps to the interrupt routine. if gie = ? 0 ? , execution will continue in-line. 4: clkout is not available in xt, hs or lp osc modes, but shown here for timing reference. note: microchip does not recommend code pro- tecting windowed devices. external connector signals to n o r m a l connections to n o r m a l connections pic16c433 v dd v ss mclr /v pp gp1 gp0 +5v 0v v pp clk data i/o v dd
pic16c433 ds41139a-page 64 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 65 pic16c433 10.0 instruction set summary each pic16c433 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16c433 instruction set summary in table 10-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 10-1 shows the opcode field descriptions. for byte-oriented instructions, ? f ? represents a file reg- ister designator and ? d ? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator which selects the number of the bit affected by the operation, while ? f ? represents the address of the file in which the bit is located. for literal and control operations, ? k ? represents an eight or eleven bit constant or literal value. table 10-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 s. table 10-2 lists the instructions recognized by the mpasm assembler. figure 10-1 shows the three general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 10-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don ? t care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1. label label name tos top-of-stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of i talics user defined term (font is courier) note: to maintain upward compatibility with future pic16c433 products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c433 ds41139a-page 66 advance information ? 2001 microchip technology inc. 10.1 special function registers as source/destination the pic16c433 ? s orthogonal instruction set allows read and write of all file registers, including special function registers. there are some special situations specified in the following sections the user should be aware of. 10.1.1 status as destination if an instruction writes to status, the z, c and dc bits may be set or cleared as a result of the instruction and overwrite the original data bits written. for example, executing clrf status will clear register status, and then set the z bit leaving 0000 0100b in the register. 10.1.2 tris as destination bit 3 of the tris register always reads as a '1' since gp3 is an input only pin. this fact can affect some read-modify-write operations on the tris register. 10.1.3 pcl as source or destination read, write or read-modify-write on pcl may have the following results: read pc: pcl dest write pcl: pclath pch; 8-bit destination value pcl read-modify-write: pcl alu operand pclath pch; 8-bit result pcl where pch = program counter high byte (not an addressable register), pclath = program counter high holding latch, dest = destination, wreg or f. 10.1.4 bit manipulation all bit manipulation instructions are done by first read- ing the entire register, operating on the selected bit and writing the result back (read-modify-write). the user should keep this in mind when operating on special function registers, such as ports.
? 2001 microchip technology inc. advance information ds41139a-page 67 pic16c433 table 10-2: instruction set summary mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( i.e., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop .
pic16c433 ds41139a-page 68 advance information ? 2001 microchip technology inc. 10.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal ? k ? and the result is placed in the w register. words: 1 cycles: 1 example addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (dest) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register ? f ? . if ? d ? is 0, the result is stored in the w register. if ? d ? is 1, the result is stored back in register ? f ? . words: 1 cycles: 1 example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w= 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and ? ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (dest) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02
? 2001 microchip technology inc. advance information ds41139a-page 69 pic16c433 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none encoding: 01 00bb bfff ffff description: bit ? b ? in register ? f ? is cleared. words: 1 cycles: 1 example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none encoding: 01 01bb bfff ffff description: bit ? b ? in register ? f ? is set. words: 1 cycles: 1 example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit ? b ? in register ? f ? is ? 0 ? , then the next instruction is skipped. if bit ? b ? is ? 0 ? , then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address true if flag<1>=1, pc = address false
pic16c433 ds41139a-page 70 advance information ? 2001 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit ? b ? in register ? f ? is ? 1 ? , then the next instruction is skipped. if bit ? b ? is ? 1 ? , then the next instruc- tion fetched during the current instruction execution is discarded and a nop is executed instead, making this a 2-cycle instruction. words: 1 cycles: 1(2) example here false true btfss goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address false if flag<1> = 1, pc = address true call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. words: 1 cycles: 2 example here call there before instruction pc = address here after instruction pc = address there tos = address here+1 clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z encoding: 00 0001 1fff ffff description: the contents of register ? f ? are cleared and the z bit is set. words: 1 cycles: 1 example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z encoding: 00 0001 0000 0011 description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example clrw before instruction w = 0x5a after instruction w = 0x00 z=1
? 2001 microchip technology inc. advance information ds41139a-page 71 pic16c433 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler= 0 to =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (dest) status affected: z encoding: 00 1001 dfff ffff description: the contents of register ? f ? are complemented. if ? d ? is 0, the result is stored in w. if ? d ? is 1, the result is stored back in register ? f ? . words: 1 cycles: 1 example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (dest) status affected: z encoding: 00 0011 dfff ffff description: decrement register ? f ? . if ? d ? is 0, the result is stored in the w regis- ter. if ? d ? is 1, the result is stored back in register ? f ? . words: 1 cycles: 1 example decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (dest); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register ? f ? are decre- mented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in register ? f ? . if the result is 0, the next instruc- tion, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt ? 0, pc = address here+1
pic16c433 ds41139a-page 72 advance information ? 2001 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. words: 1 cycles: 2 example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (dest) status affected: z encoding: 00 1010 dfff ffff description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in register ? f ? . words: 1 cycles: 1 example incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in register ? f ? . if the result is 0, the next instruc- tion, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register are or ? ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=1
? 2001 microchip technology inc. advance information ds41139a-page 73 pic16c433 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (dest) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with register ? f ? . if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in register ? f ? . words: 1 cycles: 1 example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=1 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight-bit literal ? k ? is loaded into w register. the don ? t cares will assemble as 0 ? s. words: 1 cycles: 1 example movlw 0x5a after instruction w = 0x5a movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z= 1 movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f'. words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f
pic16c433 ds41139a-page 74 advance information ? 2001 microchip technology inc. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code compatibility with pic16c5x products. since option is a read- able/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibility with future pic16c433 products, do not use this instruction. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global inter- rupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight-bit literal ? k ? . the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example table call table;w contains table ;offset value ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w= value of k8
? 2001 microchip technology inc. advance information ds41139a-page 75 pic16c433 return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. words: 1 cycles: 2 example return after interrupt pc = tos rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register ? f ? are rotated one bit to the left through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is stored back in register ? f ? . words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register ? f ? are rotated one bit to the right through the carry flag. if ? d ? is 0, the result is placed in the w register. if ? d ? is 1, the result is placed back in register ? f ? . words: 1 cycles: 1 example rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 example: sleep register f c
pic16c433 ds41139a-page 76 advance information ? 2001 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2 ? s complement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w= 1 c= ? after instruction w= 1 c = 1; result is positive example 2: before instruction w= 2 c= ? after instruction w= 0 c = 1; result is zero example 3: before instruction w= 3 c= ? after instruction w= 0xff c = 0; result is negative subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2 ? s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example 1: subwf reg1,1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1; result is positive example 2: before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1; result is zero example 3: before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0; result is negative
? 2001 microchip technology inc. advance information ds41139a-page 77 pic16c433 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register ? f ? are exchanged. if ? d ? is 0, the result is placed in w regis- ter. if ? d ? is 1, the result is placed in register ? f ? . words: 1 cycles: 1 example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 f 7 operation: (w) tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x products. since tris registers are readable and writ- able, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic16c433 products, do not use this instruction. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor ? ed with the eight bit lit- eral 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg 1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
pic16c433 ds41139a-page 78 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 79 pic16c433 11.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian simulators - mplab sim software simulator emulators - mplab ice 2000 in-circuit emulator - icepic ? in-circuit emulator in-circuit debugger - mplab icd for pic16f87x device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 11.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor a project manager customizable toolbar and key mapping a status bar on-line help the mplab ide allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro emulator and simulator tools (auto- matically updates all project information) debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 11.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all picmicro mcu ? s. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: integration into mplab ide projects. user-defined macros to streamline assembly code. conditional assembly for multi-purpose source files. directives that allow complete control over the assembly process. 11.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ? c ? compilers for microchip ? s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c433 ds41139a-page 80 advance information ? 2001 microchip technology inc. 11.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: integration with mpasm assembler and mplab c17 and mplab c18 c compilers. allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: easier linking because single libraries can be included instead of many smaller files. helps keep code maintainable by grouping related modules together. allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 11.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execution can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 11.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 11.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 2001 microchip technology inc. advance information ds41139a-page 81 pic16c433 11.8 mplab icd in-circuit debugger microchip ? s in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic16f87x and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. the mplab icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-circuit serial programming tm protocol, offers cost- effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single- stepping and setting break points. running at full speed enables testing hardware in real-time. 11.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program picmicro devices. it can also set code protection in this mode. 11.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all picmicro devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 11.11 picdem 1 low cost picmicro demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip ? s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 11.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic16c433 ds41139a-page 82 advance information ? 2001 microchip technology inc. 11.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 11.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 11.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip ? s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 2001 microchip technology inc. advance information ds41139a-page 83 pic16c433 table 11-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 c compiler mplab ? c18 c compiler mpasm tm assembler/ mplink tm object linker emulators mplab ? ice in-circuit emulator ** icepic tm in-circuit emulator debugger mplab ? icd in-circuit debugger * * programmers picstart ? plus entry level development programmer ** pro mate ? ii universal device programmer ** demo boards and eval kits picdem tm 1 demonstration board ? picdem tm 2 demonstration board ? ? picdem tm 3 demonstration board picdem tm 14a demonstration board picdem tm 17 demonstration board k ee l oq ? evaluation kit k ee l oq ? transponder kit microid tm programmer? s kit 125 khz microid tm developer ? s kit 125 khz anticollision microid tm developer ? s kit 13.56 mhz anticollision microid tm developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c433 ds41139a-page 84 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 85 pic16c433 12.0 electrical specifications for pic16c433 absolute maximum ratings ? ambient temperature under bias................................................................................................. .............. ? 40 to +125 c storage temperature ............................................................................................................ ................. ? 65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr , lin and bact) ............................... ? 0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.0v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1) ..........................................................................................................................700 m w maximum current out of v ss pin ........................................................................................................................... 200 ma maximum current into v dd pin ........................................................................................................................... ...150 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin (except lin and bact) ............................................................... ....25 ma maximum output current sunk by lin and bact.................................................................................... ..............200 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by gpio pins combined...................................................................................................100 ma maximum current sourced by gpio pins combined.................................................................................. ............100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ). ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c433 ds41139a-page 86 advance information ? 2001 microchip technology inc. figure 12-1: pic16c433 voltage-frequency graph, -40 c t a < 0 c, +85 c < t a +125 c figure 12-2: pic16c433 voltage-frequency graph, 0 c t a +85 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts.
? 2001 microchip technology inc. advance information ds41139a-page 87 pic16c433 12.1 dc characteristics pic16c433 (industrial, extended) standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +85 c for industrial ? 40 c t a +125 c for extended parm no. sym characteristic min typ ? max units conditions d001 v dd supply voltage 3.0 5.5 v d001a v bat operating battery voltage 8.0 13.8 18 v d002 v dr ram data retention voltage (note 1) 1.5* v device in sleep mode d003 v por v dd start voltage to ensure power-on reset v ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* v/ms see section on power-on reset for details d010 d010c d010a i dd supply current (note 2) ? ? ? ? ? ? 1.2 1.2 2.2 19 19 32 2.5 2.5 8 29 37 60 ma ma ma a a a f osc = 4mhz, v dd = 3.0v xt and extrc mode (note 3) f osc = 4mhz, v dd = 3.0v intrc mode (note 5) f osc = 10mhz, v dd = 5.5v hs mode f osc = 32khz, v dd = 3.0v, wdt disabled lp mode, commercial temperature f osc = 32khz, v dd = 3.0v, wdt disabled lp mode, industrial temperature f osc = 32khz, v dd = 3.0v, wdt disabled lp mode, extended temperature d020 d021 d021b i pd power-down current (note 4) ? ? ? ? ? ? 0.25 0.25 2 0.5 0.8 3 6 7 14 8 9 16 a a a a a a v dd = 3.0v, commercial, wdt disabled v dd = 3.0v, industrial, wdt disabled v dd = 3.0v, extended, wdt disabled v dd = 5.5v, commercial, wdt disabled v dd = 5.5v, industrial, wdt disabled v dd = 5.5v, extended, wdt disabled d022 ? i wdt watchdog timer current ? ? ? 2.2 2.2 4 5 6 11 a a a v dd = 3.0v, commercial v dd = 3.0v, industrial v dd = 3.0v, extended d028 ? i ee supply current (note 2) during read/write to eeprom peripheral ? 0.1 0.2 ma f osc = 4mhz, v dd = 5.5v, scl = 400khz f osc lp oscillator operating frequency intrc/extrc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency 0 ? 0 0 200 4 (5) 4 10 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. ? data in typical ( ? typ ? ) column is based on characterization results at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature, also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt disabled. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 3: for extrc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula: ir = v dd /2r ext (ma) with r ext in kohm. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 5: intrc calibration value is for 4mhz nominal at 5v, 25 c.
pic16c433 ds41139a-page 88 advance information ? 2001 microchip technology inc. 12.2 dc characteristics: pic16c433 (industrial, extended) and pic16lc433 (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range as described in dc spec section 12.1. param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss ? 0.8v v for 4.5v v dd 5.5v v ss ? 0.15v dd v otherwise d031 with schmitt trigger buffer v ss ? 0.2v dd v d032 mclr , gp2/t0cki/an2/int (in extrc mode) v ss ? 0.2v dd v d033 osc1 (in extrc mode) v ss ? 0.2v dd (note 1) d033 osc1 (in xt, hs, and lp) v ss ? 0.3v dd v (note 1) input high voltage i/o ports v ih ? d040 with ttl buffer 2.0v ? v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v ? v dd v otherwise d041 with schmitt trigger buffer 0.8v dd ? v dd v for entire v dd range d042 mclr , gp2/t0cki/an2/int 0.8v dd ? v dd v d042a osc1 (xt, hs, and lp) 0.7v dd ? v dd v (note 1) d043 osc1 (in extrc mode) 0.9v dd ? v dd v input leakage current (notes 2, 3) d060 i/o ports i il ?? + 1 av ss v pin v dd , pin at hi-impedance d061 gp3/mclr (note 5) + 30 av ss v pin v dd d061a gp3 (note 6) + 5 av ss v pin v dd d062 gp2/t0cki ?? + 5 av ss v pin v dd d063 osc1 ?? + 5 av ss v pin v dd , xt, hs, and lp osc configuration d070 gpio weak pull-up current (note 4) i pur 50 250 400 av dd = 5v, v pin = v ss mclr pull-up current ??? 30 av dd = 5v, v pin = v ss output low voltage d080 i/o ports v ol ?? 0.6 v i ol = 8.5 ma, v dd = 4.5v, ? 40 c to +85 c d080a ?? 0.6 v i ol = 7.0 ma, v dd = 4.5v, ? 40 c to +125 c d083 osc2/clkout ?? 0.6 v i ol = 1.6 ma, v dd = 4.5v, ? 40 c to +85 c d083a ?? 0.6 v i ol = 1.2 ma, v dd = 4.5v, ? 40 c to +125 c ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c433 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: does not include gp3. for gp3 see parameters d061 and d061a. 5: this spec. applies to gp3/mclr configured as external mclr and gp3/mclr configured as input with internal pull- up enabled. 6: this spec. applies when gp3/mclr is configured as an input with pull-up disabled. the leakage current of the mclr circuit is higher than the standard i/o logic.
? 2001 microchip technology inc. advance information ds41139a-page 89 pic16c433 output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 ?? vi oh = -3.0 ma, v dd = 4.5v, ? 40 c to +85 c d090a v dd - 0.7 ?? vi oh = -2.5 ma, v dd = 4.5v, ? 40 c to +125 c d092 osc2/clkout v dd - 0.7 ?? vi oh = 1.3 ma, v dd = 4.5v, ? 40 c to +85 c d092a v dd - 0.7 ?? vi oh = 1.0 ma, v dd = 4.5v, ? 40 c to +125 c capacitive loading specs on output pins d100 osc2 pin c osc 2 ?? 15 pf in xt and lp modes when external clock is used to drive osc1 d101 all i/o pins c io ?? 50 pf dc characteristics standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range as described in dc spec section 12.1. param no. characteristic sym min typ ? max units conditions ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c433 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: does not include gp3. for gp3 see parameters d061 and d061a. 5: this spec. applies to gp3/mclr configured as external mclr and gp3/mclr configured as input with internal pull- up enabled. 6: this spec. applies when gp3/mclr is configured as an input with pull-up disabled. the leakage current of the mclr circuit is higher than the standard i/o logic.
pic16c433 ds41139a-page 90 advance information ? 2001 microchip technology inc. table 12-1: lin bus transceiver operating specifications operating conditions: v dd range as described in table 12-1, -40 c < t a < +125 c. table 12-2: lin bus transceiver interface specifications operating conditions: v dd range as described in table 12-1, -40 c < t a < +125 c. param no. characteristics sym min typ max units comments d313 v dd quiescent operating current i dd _ lin --1ma d314 v bat low power current i bat 50 a * these parameters are characterized but not tested. param no. characteristics sym min typ max units comments d315 low level output current i ol _ lin _ dominant 40 - 200 ma v bus = 12v d316 high level output leakage current i oh _ lin -20 20 av bus v bat ; v bus < 40v d317 low level output current, open ground i oh _ lin _ revers -1 1 ma d318 low level input voltage v il _ lin -8 0.4v bat v dominant state d319 high level input voltage v ih _ lin 0.6v bat 18 v recessive state d320 input hysteresis v hys _ lin 0.05v bat 0.1v bat vv ih _ lin - v il _ lin d321 short circuit current limit i sc _ lin 0.05 200 ma d322 high level output voltage v oh _ lin 0.8v bat v d323 low level output voltage v ol _ lin 0.2v bat v * these parameters are characterized but not tested.
? 2001 microchip technology inc. advance information ds41139a-page 91 pic16c433 12.3 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 12-3: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c433 ds41139a-page 92 advance information ? 2001 microchip technology inc. 12.4 timing diagrams and specifications figure 12-4: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 12-3: clock timing requirements parameter no. sym characteristic min typ ? max units conditions f osc external clkin frequency (note 1) dc ? 4 mhz xt and extrc osc mode dc ? 4 mhz hs osc mode dc ? 10 mhz hs osc mode dc ? 200 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz extrc osc mode .455 ? 4 mhz xt osc mode 4 ? 4 mhz hs osc mode 4 ? 10 mhz hs osc mode 5 ? 200 khz lp osc mode 1t osc external clkin period (note 1) 250 ?? ns xt and extrc osc mode 250 ?? ns hs osc mode 100 ?? ns hs osc mode 5 ?? s lp osc mode oscillator period (note 1) 250 ?? ns extrc osc mode 250 ? 10,000 ns xt osc mode 250 ? 250 ns hs osc mode 100 ? 250 ns hs osc mode 5 ?? slp osc mode 2t cy instruction cycle time (note 1) 400 ? dc ns t cy = 4/f osc 3 tosl, to s h external clock in (osc1) high or low time 50 ?? ns xt oscillator 2.5 ?? s lp oscillator 10 ?? ns hs oscillator 4tosr, to s f external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ?? 15 ns hs oscillator ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device exe- cuting code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc2 is discon- nected (has no loading) for the pic16c433.
? 2001 microchip technology inc. advance information ds41139a-page 93 pic16c433 table 12-4: calibrated internal rc frequencies - pic16c433 ac characteristics standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min* typ (1) max* units conditions internal calibrated rc frequency 3.65 4.00 4.28 mhz v dd = 5.0v * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c433 ds41139a-page 94 advance information ? 2001 microchip technology inc. figure 12-5: clkout and i/o timing table 12-5: clkout and i/o timing requirements param no. sym characteristic min typ ? max units conditions 10* tosh2ckl osc1 to clkout ? 75 200 ns (note 1) 11* tosh2ckh osc1 to clkout ? 75 200 ns (note 1) 12* tckr clkout rise time ? 35 100 ns (note 1) 13* tckf clkout fall time ? 35 100 ns (note 1) 14* tckl2iov clkout to port out valid ?? 0.5t cy + 20 ns (note 1) 15* tiov2ckh port in valid before clkout t osc + 200 ?? ns (note 1) 16* tckh2ioi port in hold after clkout 0 ?? ns (note 1) 17* tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 ns 18* tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) pic16 c 433 100 ?? ns 18a* pic16 lc 433 200 ?? ns 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ?? ns 20* tior port output rise time pic16 c 433 ? 10 40 ns 20a* pic16 lc 433 ?? 80 ns 21* tiof port output fall time pic16 c 433 ? 10 40 ns 21a* pic16 lc 433 ?? 80 ns 22 ?? * tinp gp2/int pin high or low time t cy ?? ns 23 ?? * trbp gp0/gp1/gp3 change int high or low time t cy ?? ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in extrc and intrc modes where clkout output is 4 x t osc . note: refer to figure 12-3 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
? 2001 microchip technology inc. advance information ds41139a-page 95 pic16c433 figure 12-6: reset, watchdog timer, oscillator start-up timer, and power-up timer timing table 12-6: reset, watchdog timer, oscillator start-up timer, power-up timer v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 36 parameter no. sym characteristic min typ ? max units conditions 30 tmcl mclr pulse width (low) 2 ?? sv dd = 5v, ? 40 c to +125 c 31* twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, ? 40 c to +125 c 32 tost oscillation start-up timer period ? 1024t osc ?? t osc = osc1 period 33* tpwrt power up timer period 28 72 132 ms v dd = 5v, ? 40 c to +125 c 34 tioz i/o hi-impedance from mclr low or watchdog timer reset ?? 2.1 s * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c433 ds41139a-page 96 advance information ? 2001 microchip technology inc. figure 12-7: timer0 clock timings table 12-7: timer0 and timer1 external clock requirements param no. sym characteristic min typ ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ?? ns must also meet parameter 42 with prescaler 10 ?? ns 42* tt0p t0cki period no prescaler t cy + 40 ?? ns with prescaler greater of: 20 or t cy + 40 n ?? ns n = prescale value (2, 4,..., 256) 48 tcke2tmr1 delay from external clock edge to timer increment 2t osc ? 7t osc ? * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 12-3 for load conditions. 41 42 40 gp2/t0cki tmr0
? 2001 microchip technology inc. advance information ds41139a-page 97 pic16c433 table 12-8: gpio pull-up resistor ranges v dd (volts) temperature ( c) min typ max units gp0/gp1 2.5 ? 40 38k 42k 63k ? 25 42k 48k 63k ? 85 42k 49k 63k ? 125 50k 55k 63k ? 5.5 ? 40 15k 17k 20k ? 25 18k 20k 23k ? 85 19k 22k 25k ? 125 22k 24k 28k ? gp3 2.5 ? 40 285k 346k 417k ? 25 343k 414k 532k ? 85 368k 457k 532k ? 125 431k 504k 593k ? 5.5 ? 40 247k 292k 360k ? 25 288k 341k 437k ? 85 306k 371k 448k ? 125 351k 407k 500k ? * these parameters are characterized but not tested.
pic16c433 ds41139a-page 98 advance information ? 2001 microchip technology inc. table 12-9: lin bus ac characteristics table 12-10: lin thermal characteristics symbol parameter min. typ. max. unit note ? dv/dt ? slope rising and falling edges 12 v/ s t trans_pd propagation delay of transmitter 4 st trans_pd = max(t trans_pdr or t trans_pdf ) t rec_pd propagation delay of receiver 6 st rec_pd = max(t rec_pdr or t rec_pdf ) t rec_sym symmetry of receiver propagation delay rising edge w.r.t. falling edge -2 2 st rec_sym = t rec_pdf - t rec_pdr) t trans_sym symmetry of transmitter propagation delay rising edge w.r.t. falling edge -2 2 st trans_sym = t trans_pdf - t rans_pdr ) symbol parameter typ. max. unit note recovery recovery temperature +135 c information parameter shutdown shut-down temperature +155 c information parameter t therm short circuit recovery time 1.5 ms information parameter
? 2001 microchip technology inc. advance information ds41139a-page 99 pic16c433 figure 12-8: timing diagram txd (input of physical layer) t trans_pdf t trans_pdr bus signal rec. threshold rec. threshold t rec_pdf t rec_pdr rxd (physical layer output)
pic16c433 ds41139a-page 100 advance information ? 2001 microchip technology inc. table 12-11: a/d converter characteristics: pic16c433 param no. sym characteristic min typ ? max units conditions a01 n r resolution ?? 8-bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs total absolute error ?? < 1lsbv ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ?? < 1lsbv ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ?? < 1lsbv ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error ?? < 1lsbv ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ?? < 1lsbv ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity ? guaranteed (note 3) ?? v ss v ain v ref a20 v ref reference voltage 2.5v ? v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 ? v ref + 0.3 v a30 z ain recommended impedance of analog voltage source ?? 10.0 k ? a40 i ad a/d conversion current (v dd ) pic16 c 433 ? 180 ? a average current consumption when a/d is on (note 1) pic16 lc 433 ? 90 ? a a50 i ref v ref input current (note 2) 10 ? ? ? 1000 10 a a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 8.1 during a/d conversion cycle * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from gp1 pin or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage, and has no missing codes.
? 2001 microchip technology inc. advance information ds41139a-page 101 pic16c433 figure 12-9: a/d conversion timing table 12-12: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134 param no. sym characteristic min typ ? max units conditions 130 t ad a/d clock period pic16 c 433 1.6 ?? st osc based, v ref 3.0v pic16 lc 433 2.0 ?? st osc based, v ref full range pic16 c 433 2.0 4.0 6.0 s a/d rc mode pic16 c 433 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 ? 11 tad 132 t acq acquisition time (note 2) 5* 20 ? ? ? s s the minimum time is the amplifier setting time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert sample time 1.5 ? ? tad * these parameters are characterized but not tested. ? data in ? typ ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this specification ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see section 8.1 for minimum conditions.
pic16c433 ds41139a-page 102 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 103 pic16c433 13.0 dc and ac characteristics - pic16c433 the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ? typical ? represents the mean of the distribution while ? max ? or ? min ? represents (mean + 3 ) and (mean ? 3 ) respectively, where is standard deviation. figure 13-1: calibrated internal rc frequency range vs. temperature (v dd = 5.0v) (internal rc is calibrated to 25 c, 5.0v) figure 13-2: calibrated internal rc frequency range vs. temperature (v dd = 2.5v) (internal rc is calibrated to 25 c, 5.0v) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 0 max. min. frequency (mhz) temperature (degree c) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 0 max. min . frequency (mhz) temperature (degree c)
pic16c433 ds41139a-page 104 advance information ? 2001 microchip technology inc. table 13-1: dynamic i dd (typical) - wdt enabled, 25 c figure 13-3: wdt timer time-out period vs. v dd figure 13-4: i oh vs. v oh , v dd = 2.5v oscillator frequency v dd = 2.5v v dd = 5.5v external rc 4 mhz 400 a* 900 a* internal rc 4 mhz 400 a900 a xt 4 mhz 400 a900 a lp 32 khz 15 a 60 a *does not include current through external r&c. min ? 40 c typ +25 c max +85 c max +125 c 55 50 45 40 35 30 25 20 15 10 0 2.5 3.5 4.5 5.5 6.5 v dd (volts) wdt period (ms) max -40 c typ +25 c min +85 c min +125 c v oh (volts) i oh (ma) .5 1.0 1.5 2.0 2.5 -0 -1 -2 -3 -4 -5 -10 2.25 1.75 1.25 .75 -6 -7 -8 -9
? 2001 microchip technology inc. advance information ds41139a-page 105 pic16c433 figure 13-5: i oh vs. v oh , v dd = 3.5v figure 13-6: i oh vs. v oh , v dd = 5.5v figure 13-7: i ol vs. v ol , v dd = 2.5v figure 13-8: i ol vs. v ol , v dd = 3.5v v oh (volts) i oh (ma) 1.5 2.0 2.5 3.0 3.5 0 -5 -10 -15 -20 -25 min +125 c min +85 c typ +25 c max -40 c 3.5 4.0 4.5 v oh (volts) i oh (ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 m i n + 1 2 5 c m a x ? 4 0 c t y p + 2 5 c m i n + 8 5 c -35 -40 min +125 c min +85 c typ +25 c max -40 c 25 20 15 10 5 0 0.5 0.75 1.0 v ol (volts) i ol (ma) 0 30 35 0.25 min +125 c min +85 c typ +25 c max -40 c 30 25 20 15 10 0 0.5 0.75 1.0 v ol (volts) i ol (ma) 0 35 40 0.25 45
pic16c433 ds41139a-page 106 advance information ? 2001 microchip technology inc. figure 13-9: i ol vs. v ol , v dd = 5.5v figure 13-10: v th (input threshold voltage) of gpio pins vs. v dd figure 13-11: v il , v ih of nmclr and t0cki vs. v dd min +125 c min +85 c typ +25 c max -40 c 30 25 20 15 10 0 0.5 0.75 1.0 v ol (volts) i ol (ma) 0 35 40 0.25 45 50 55 typ +25 max -40 to +125 min -40 to +125 1.6 1.4 1.2 1.0 0.8 0.6 0 2.5 3.5 4.5 5.5 v dd (volts) v th (volts) 1.8 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.5 3.5 4.5 5.5 v dd (volts) v il , v ih (volts) v ih max (-40 to +125 ) v ih typ (+25 ) v ih min (-40 to +125 ) v ih max (-40 to +125 ) v ih typ (+25 ) v ih min (-40 to +125 )
? 2001 microchip technology inc. advance information ds41139a-page 107 pic16c433 14.0 packaging information 14.1 package marking information xxxxxxxx xxxxxxxx yywwnnn 18-lead cerdip windowed 18-lead soic (.300") xxxxxxxxxxxx yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn 18-lead pdip example example example pic16c433 -i/p423 0007cdk -i/so218 0007cdk pic16c433 18-lead cerdip windowed 16c433 /jw 0007cba * standard marking consists of microchip part number, year code, week code, and traceability code. for marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information.
pic16c433 ds41139a-page 108 advance information ? 2001 microchip technology inc. 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic
? 2001 microchip technology inc. advance information ds41139a-page 109 pic16c433 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle f 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic
pic16c433 ds41139a-page 110 advance information ? 2001 microchip technology inc. 18-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 * controlling parameter significant characteristic jedec equivalent: mo-036 drawing no. c04-010
? 2001 microchip technology inc. advance information ds41139a-page 111 pic16c433 appendix a: compatibility to convert code written for pic16c5x to pic16c433, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h.
pic16c433 ds41139a-page 112 advance information ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. advance information ds41139a-page 113 pic16c433 index a a/d accuracy/error ........................................................... 47 adcon0 register ...................................................... 41 adif bit ...................................................................... 43 analog input model block diagram ............................ 44 analog-to-digital converter ........................................ 41 configuring analog port pins ..................................... 45 configuring the interrupt ............................................ 43 configuring the module .............................................. 43 connection considerations ........................................ 47 conversion clock ....................................................... 45 conversions ............................................................... 46 converter characteristics ........................................ 100 delays ........................................................................ 44 effects of a reset .................................................... 47 equations ................................................................... 44 flow chart of a/d operation ...................................... 48 go/done bit ............................................................. 43 internal sampling switch (rss) impedence ............... 44 operation during sleep ........................................... 47 sampling requirements ............................................. 44 sampling time ........................................................... 44 source impedence ..................................................... 44 time delays ............................................................... 44 transfer function ....................................................... 47 absolute maximum ratings ............................................... 85 addlw instruction ............................................................ 68 addwf instruction ............................................................ 68 adie bit .............................................................................. 18 adif bit .............................................................................. 19 adres register .................................................... 13, 41, 43 alu ...................................................................................... 7 andlw instruction ............................................................ 68 andwf instruction ............................................................ 68 application notes an546 ........................................................................ 41 an556 ........................................................................ 22 architecture harvard ........................................................................ 7 overview ...................................................................... 7 von neumann ............................................................... 7 assembler mpasm tm assembler ................................................. 79 b bcf instruction .................................................................. 69 bit manipulation ................................................................. 66 block diagrams analog input model .................................................... 44 on-chip reset circuit ................................................ 53 timer0 ........................................................................ 35 timer0/wdt prescaler .............................................. 38 watchdog timer ......................................................... 61 bsf instruction .................................................................. 69 btfsc instruction .............................................................. 69 btfss instruction .............................................................. 70 c c bit ................................................................................... 15 cal0 bit ............................................................................. 21 cal1 bit ............................................................................. 21 cal2 bit ............................................................................. 21 cal3 bit ............................................................................. 21 calfst bit ........................................................................ 21 call instruction ................................................................ 70 calslw bit ....................................................................... 21 carry bit ............................................................................... 7 clocking scheme ............................................................... 10 clrf instruction ................................................................ 70 clrw instruction ............................................................... 70 clrwdt instruction .......................................................... 71 code examples changing prescaler (timer0 to wdt) ....................... 39 changing prescaler (wdt to timer0) ....................... 39 indirect addressing .................................................... 23 code protection ........................................................... 49, 63 comf instruction ............................................................... 71 computed goto ............................................................... 22 configuration bits .............................................................. 49 d dc and ac characteristics .............................................. 103 dc bit ................................................................................. 15 dc characteristics pic16c433 ................................................................ 87 decf instruction ............................................................... 71 decfsz instruction ........................................................... 71 development support .......................................................... 3 diagrams - see block diagrams digit carry bit ....................................................................... 7 direct addressing .............................................................. 23 e eeprom peripheral operation ......................................... 33 electrical characteristics pic16c433 ................................................................ 85 errata ................................................................................... 2 external brown-out protection circuit ................................ 57 external power-on reset circuit ........................................ 57 f features .............................................................................. 1 fsr register ......................................................... 13, 14, 23 g general description ............................................................. 3 gie bit ................................................................................ 58 goto instruction ............................................................... 72 gpif bit ............................................................................. 60 gpio ............................................................................ 25, 55 gpio register ................................................................... 13 gppu bit ............................................................................ 16
pic16c433 ds41139a-page 114 advance information ? 2001 microchip technology inc. i i/o interfacing ..................................................................... 25 i/o ports ............................................................................. 25 i/o programming considerations ....................................... 31 id locations ....................................................................... 49 incf instruction ................................................................. 72 incfsz instruction ............................................................. 72 in-circuit serial programming ...................................... 49, 63 indf register .............................................................. 14, 23 indirect addressing ............................................................ 23 initialization conditions for all registers ............................ 55 instruction cycle ................................................................. 10 instruction flow/pipelining ................................................. 10 instruction format .............................................................. 65 instruction set addlw ...................................................................... 68 addwf ...................................................................... 68 andlw ...................................................................... 68 andwf ...................................................................... 68 bcf ............................................................................ 69 bsf ............................................................................ 69 btfsc ....................................................................... 69 btfss ....................................................................... 70 call .......................................................................... 70 clrf .......................................................................... 70 clrw ........................................................................ 70 clrwdt .................................................................... 71 comf ........................................................................ 71 decf ......................................................................... 71 decfsz ..................................................................... 71 goto ........................................................................ 72 incf ........................................................................... 72 incfsz ...................................................................... 72 iorlw ....................................................................... 72 iorwf ....................................................................... 73 movf ......................................................................... 73 movlw ..................................................................... 73 movwf ..................................................................... 73 nop ........................................................................... 74 option ..................................................................... 74 retfie ...................................................................... 74 retlw ...................................................................... 74 return .................................................................... 75 rlf ............................................................................ 75 rrf ............................................................................ 75 sleep ....................................................................... 75 sublw ...................................................................... 76 subwf ...................................................................... 76 swapf ...................................................................... 77 tris ........................................................................... 77 xorlw ...................................................................... 77 xorwf ...................................................................... 77 section ....................................................................... 65 intcon register ............................................................... 17 intedg bit ......................................................................... 16 internal sampling switch (rss) impedence ....................... 44 interrupts ............................................................................ 49 a/d ............................................................................. 58 gp2/int ..................................................................... 58 gpio port .................................................................. 58 section ....................................................................... 58 tmr0 ......................................................................... 60 tmr0 overflow .......................................................... 58 iorlw instruction .............................................................. 72 iorwf instruction .............................................................. 73 irp bit ................................................................................ 15 k k ee l oq ? evaluation and programming tools ................... 82 l lin bus hardware interface ............................................... 33 lin bus interfacing ............................................................. 33 lin bus protocol ................................................................ 33 loading of pc .................................................................... 22 m mclr ........................................................................... 52, 55 memory data memory ............................................................. 11 program memory ....................................................... 11 register file map pic16c433 ........................................................ 12 movf instruction ............................................................... 73 movlw instruction ............................................................ 73 movwf instruction ........................................................... 73 mplab ? integrated development environment software ....................................................... 79 n nop instruction ................................................................. 74 o opcode .............................................................................. 65 option instruction ........................................................... 74 option register ............................................................... 16 orthogonal ........................................................................... 7 osc selection ................................................................... 49 osccal register .............................................................. 21 oscillator extrc ...................................................................... 54 hs .............................................................................. 54 intrc ........................................................................ 54 lp .............................................................................. 54 xt .............................................................................. 54 oscillator configurations .................................................... 50 oscillator types extrc ...................................................................... 50 hs .............................................................................. 50 intrc ........................................................................ 50 lp .............................................................................. 50 xt .............................................................................. 50
? 2001 microchip technology inc. advance information ds41139a-page 115 pic16c433 p package marking information .......................................... 107 packaging information ..................................................... 107 paging, program memory .................................................. 22 pcl .................................................................................... 66 pcl register .......................................................... 13, 14, 22 pclath ............................................................................. 55 pclath register .................................................. 13, 14, 22 pcon register ............................................................ 20, 54 pd bit ........................................................................... 15, 52 picdem tm 1 low cost picmicro demonstration board ......................................................... 81 picdem tm 2 low cost pic16cxx demonstration board ......................................................... 81 picdem tm 3 low cost pic16cxxx demonstration board ......................................................... 82 picstart ? plus entry level development system ......... 81 pie1 register ..................................................................... 18 pinout description pic16c433 .................................................................. 9 pir1 register ..................................................................... 19 pop ................................................................................... 22 por ................................................................................... 54 oscillator start-up timer (ost) ........................... 49, 54 power control register (pcon) ................................ 54 power-on reset (por) .................................. 49, 54, 55 power-up timer (pwrt) ..................................... 49, 54 power-up-timer (pwrt) ........................................... 54 time-out sequence .................................................... 54 time-out sequence on power-up .............................. 56 to .............................................................................. 52 power ................................................................................. 52 power-down mode (sleep) .............................................. 62 power-on reset (por) time-out (to bit) ....................................................... 15 prescaler, switching between timer0 and wdt ............... 39 pro mate ? ii universal programmer .............................. 81 program branches ............................................................... 7 program memory paging ........................................................................ 22 program verification .......................................................... 63 ps0 bit ............................................................................... 16 ps1 bit ............................................................................... 16 ps2 bit ............................................................................... 16 psa bit ............................................................................... 16 push ................................................................................. 22 r rc oscillator ...................................................................... 51 read-modify-write ............................................................. 31 read-modify-write ............................................................. 31 register file ....................................................................... 11 registers map pic16c433 ........................................................ 12 reset conditions ..................................................... 55 reset ......................................................................... 49, 52 reset conditions for special registers ........................... 55 retfie instruction ............................................................. 74 retlw instruction ............................................................. 74 return instruction .......................................................... 75 rlf instruction ................................................................... 75 rp0 bit ......................................................................... 11, 15 rp1 bit ............................................................................... 15 rrf instruction .................................................................. 75 s services one-time-programmable (otp) ................................. 5 quick-turnaround-production (qtp) .......................... 5 serialized quick-turnaround production (sqtp) ....... 5 sfr ................................................................................... 66 sfr as source/destination ............................................... 66 sleep ......................................................................... 49, 52 sleep instruction ............................................................. 75 software simulator (mplab sim) ..................................... 80 special features of the cpu ............................................. 49 special function register pic16c433 ................................................................ 13 special function registers ................................................ 66 special function registers, section .................................. 12 stack .................................................................................. 22 overflows ................................................................... 22 underflow .................................................................. 22 status register .............................................................. 15 dc bit .................................................................. 15, 41 irp bit ........................................................... 15, 41, 42 to bit ........................................................................ 15 z bit ..................................................................... 15, 41 sublw instruction ............................................................ 76 subwf instruction ............................................................ 76 swapf instruction ............................................................ 77 t t0cs bit ............................................................................. 16 t ad .................................................................................... 45 thermal shut-down ........................................................... 33 timer0 rtcc ......................................................................... 55 timers timer0 block diagram ................................................... 35 external clock ................................................... 37 external clock timing ........................................ 37 increment delay ................................................ 37 interrupt ............................................................. 35 interrupt timing ................................................. 36 prescaler ........................................................... 38 prescaler block diagram ................................... 38 section .............................................................. 35 switching prescaler assignment ....................... 39 synchronization ................................................. 37 t0cki ................................................................ 37 t0if ................................................................... 60 timing ................................................................ 35 tmr0 interrupt .................................................. 60 timing diagrams a/d conversion ....................................................... 101 clkout and i/o ....................................................... 94 external clock timing ................................................ 92 time-out sequence ................................................... 56 timer0 ....................................................................... 35 timer0 interrupt timing ............................................. 36 timer0 with external clock ........................................ 37 wake-up from sleep via interrupt ........................... 63 to bit ................................................................................. 15 tose bit ............................................................................ 16 tris instruction ................................................................. 77 tris register ........................................................ 14, 25, 30 two ? s complement .............................................................. 7
pic16c433 ds41139a-page 116 advance information ? 2001 microchip technology inc. u uv erasable devices ........................................................... 5 w w register alu .............................................................................. 7 wake-up from sleep ........................................................ 62 watchdog timer (wdt) ................................... 49, 52, 55, 61 wdt ................................................................................... 55 block diagram ............................................................ 61 period ......................................................................... 61 programming considerations .................................... 61 timeout ...................................................................... 55 www, on-line support ....................................................... 2 x xorlw instruction ............................................................ 77 xorwf instruction ............................................................ 77 z z bit .................................................................................... 15 zero bit ................................................................................. 7
? 2001 microchip technology inc. advance information ds41139a-page117 pic16c433 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip ? s development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development sys- tems, technical information and more listing of seminars and events 013001
pic16c433 ds41139a-page118 advance information ? 2001 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41139a pic16c433
? 2001 microchip technology inc. advance information ds41139a-page 119 pic16c433 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type. sales and support part no. x /xx xxx pattern package temperature range device device pic16c433 pic16lc433 pic16c433t (tape & reel for soic only) pic16lc433t (tape & reel for soic only) temperature range i = -40 c to +85 c e= -40 c to +125 c package p = pdip jw* = windowed cerdip sm = soic pattern special requirements examples: a) pic16c433-i/p = industrial temp., pdip, 4 mhz - 10 mhz, normal v dd limits b) pic16c433-e/p = extended temp., pdip, 4 mhz - 10 mhz, normal v dd limits data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds41139a-page 120 advance information ? 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shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 asia/pacific (continued) korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d ? activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 germany analog product sales lochhamer strasse 13 d-82152 martinsried, germany tel: 49-89-895650-0 fax: 49-89-895650-22 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/30/01 w orldwide s ales and s ervice

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