dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
msm6648 ? semiconductor 1/9 general description the msm6648 is a dot matrix lcd common driver. fabricated in cmos technology, the device consists of two 50-bit bidirectional shift registers, two 50-bit level shifters, and two 50-bit 4-level drivers. the msm6648 is equipped with 100 lcd output pins. by connecting more than two msm6648s in cascade, this lsi is applicable to a wide lcd panel. features ? logic supply voltage : 2.7 to 5.5 v ? lcd drive voltage : 18 to 28 v ? applicable lcd duty : 1/64 to 1/240 ? suitable for bath panel sizes of 400 (200 2) and 480 (240 2) in common numbers by the use of intermediate data input and 10-bit bypass function. ? structure: tape carrier package (tcp) mounting with 35 mm wide film (product name : MSM6648AV-Z-01) sn-plated ? semiconductor msm6648 100-dot common driver e2b0029-27-y2 this version: nov. 1997 previous version: mar. 1996
msm6648 ? semiconductor 2/9 block diagram o 49 v ss v ee v 1r v 2r v 5r v eer df v dd v dd o 2 o 50 o 1 50-bit bidirectional shift register shl mode1 v dd v ss disp off io 51 io 1 cp io 50 o 99 o 52 o 100 o 51 50-bit bidirectional shift register 50-bit level shifter 50-bit 4-level driver v dd v dd v ss v ee io 100 50-bit 4-level driver 50-bit level shifter mode2 v 1l v 2l v 5l v eel
msm6648 ? semiconductor 3/9 pin configuration (top view) 1 surface of chip o 100 o 99 234567891011121314151617181920 o 2 o 1 (input pin side) (lcd output side) pin symbol pin symbol 111 212 313 414 515 616 717 818 919 10 20 v 1l io 50 v 2l v ss v 5l df v eel cp mode1 io 1 io 100 mode2 disp off v eer v dd v 5r shl v 2r io 51 v 1r
msm6648 ? semiconductor 4/9 absolute maximum ratings parameter symbol condition rating unit power supply voltage (1) v dd ta = 25c C0.3 to +6.5 v power supply voltage (2) v dd Cv ee *1 ta = 25c 0 to 30 v input voltage v i ta = 25c C0.3 to v dd + 0.3 v storage temperature t stg C30 to +85 c *1 v 1 > v 2 > v 5 > v ee , v dd 3 v 1 > v 2 3 v dd C 10v, v ee + 10v 3 v 5 > v ee v 1 = v 1l = v 1r , v 2 = v 2l = v 2r , v 5 = v 5l = v 5r , v ee = v eel = v eer recommended operating conditions *1 v 1 > v 2 > v 5 > v ee , v dd 3 v 1 > v 2 3 v dd C 7v, v ee + 7v 3 v 5 > v ee v 1 = v 1l = v 1r , v 2 = v 2l = v 2r , v 5 = v 5l = v 5r , v ee = v eel = v eer parameter symbol condition range unit power supply voltage (1) v dd 2.7 to 5.5 v power supply voltage (2) v dd C v ee *1 no load 14 to 28 v during lcd drive 18 to 28 v operating temperature top C20 to +75 c
msm6648 ? semiconductor 5/9 note 1 : when display is controlled by dispoff pin, cp rise and fall time must be 1 m s. electrical characteristics dc characteristics *1 applicable to cp, io 1 , io 50 , io 100 , shl, df, disp off , mode1, mode2. *2 applicable to io 1 , io 50 , io 51 , io 100 *3 v n = v dd to v ee , v 2 = 1/16 (v dd C v ee ), v 5 = 15/16 (v dd C v ee ), v dd = v1, v dd = 4.5v *4 applicable to o 1 to o 100 switching characteristics cp io 1 (io 50 ) io 51 (io 100 ) t setup 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.8v dd 0.2v dd io 50 (io 1 ) io 100 (io 51 ) t f(cp) t r(cp) t plh (t phl ) t hold t wcp 0.8v dd 0.2v dd (v dd = 2.7 to 5.5v, ta = C20 to +75c) parameter symbol condition min. typ. max. unit "h" input voltage v ih *1 0.8v dd v dd v "l" input voltage v il *1 v ss 0.2v dd v "h" input current i ih *1 v i = v dd , v dd = 5.5v 1 m a "l" input current i il *1 v i = 0v, v dd = 5.5v C1 m a "h" output voltage v oh *2 i o = C0.2ma, v dd = 2.7v v dd C 0.4 v "l" output voltage v ol *2 i o = 0.2ma, v dd = 2.7v 0.4 v on resistance r on *4 v dd C v ee = 25v, | v n C v o | = 0.25v *3 2k w supply current i ss f cp = 28khz, v dd = 3.0v v dd C v ee = 25v, no load 50 m a i ee 300 input capacitance c i f = 1mhz 5 pf (v dd = 2.7 to 5.5v, ta = C20 to +75c, c l = 15pf) parameter symbol condition min. typ. max. unit "h", "l" propagation delay time t plh , t phl clock frequency f cp cp pulse width t wcp data setup time t setup data hold time t hold rise/fall time of cp t r (cp) , t f (cp) 3 m s 1 mhz 63ns 100 ns 100 ns 20ns
msm6648 ? semiconductor 6/9 functional description pin functional description ? io, io 50 , io 51 , io 100 these are i/o pins for the two 50-bit bidirectional shift registers. ? shl this is an input pin to select the shift direction of the two 50-bit bidirectional shift registers. set this pin to "h" or "l" level during power-on. ? mode1, mode2 these are input pins to select whether the two 50-bit shift registers are used as a two 50-bit application or a 40-bit and 50-bit application. functions of the shl, mode1 and mode2 pins are shown below. the scan data input into the io 1 , and io 51 pins are shifted at the falling edge of cp and are output from the io 50 and io 100 pins after the lapse of 50 clock pulses. the scan data input into the io 100 and io 50 pins are shifted at the falling edge of cp and are output from the io 51 and io 1 pins after 50 clock pulses. this condition means a mode of bypassing between the o 1 and o 10 pins. the scan data input into the io 1 pin is stored in the o 11 pin and is output from the io 50 pin after 40 clock pulses. the operation in the o 51 to o 100 pins is the same as that in setting shl to "l" and mode2 to "l". this condition means a mode of bypassing between the o 91 and o 100 pins. the scan data input into the io 100 pin is stored in o 90 and is output from the io 51 pin after 40 clock pulses. the operation in the o 1 to o 50 pins is the same as that in setting shl to "h" and mode1 to "l". function mode2 mode1 shl scan direction data input pin scan output pin l l hl l h hh o 1 ? o 50 io 1 io 50 o 51 ? o 100 io 51 io 100 o 50 ? o 1 io 50 io 1 o 100 ? o 51 io 100 io 51 o 11 ? o 50 io 1 io 50 o 51 ? o 100 io 51 io 100 o 50 ? o 1 io 50 io 1 o 90 ? o 51 io 100 io 51
msm6648 ? semiconductor 7/9 ? cp this is a clock pulse input pin for two 50-bit bi-directional shift registers. scan data is shifted at the falling edge of a clock pulse. ? df this is an input pin for an lcd drive waveform ac synchronization signal, which generally inputs a frame inversion signal. see the truth table. ? disp off this is an input pin used to control the output pins o 1 to o 100 . signals on the v 1 level are output from the output pins o 1 to o 100 , independent of the shift register data during low signal input. see the truth table. ? o 1 to o 100 these are 4-level driver output pins, directly corresponding to each bit of the shift register. df signals combined to shift register data select and output any of four levels v 1 , v 2 , v 5 , and v ee . ? v dd , v ss these are power supply pins. v dd is normally 2.7 to 5.5 v. v ss is a grounding pin, which is normally set to 0 v. ? v 1l , v 2l , v 5l , v eel , v 1r , v 1r , v 5r , v eer these are lcd drive bias voltage pins. the v 1 pin may be separated from the v dd pin. bias supply voltages are supplied from an external source. truth table df shift register data disp off driver output (o 1 to o 100 ) llh v 2 lhh v ee hlh v 5 hhh v 1 lv 1 : don't care notes on use note the following when turning power on and off: the lcd drivers of this ic requires a high voltage. if a high voltage is applied to them with the logic power supply floating, excess current flows. this may damage the ic. be sure to carry out the following power-on and power-off sequences. when turning power on: first turn on the logic circuits, then the lcd drivers, or turn on both of them at the same time. when turning power off: first turn off the lcd drivers, then the logic circuits, or turn off both of them at the same time.
msm6648 ? semiconductor 8/9 application circuits example of connecting to lcd panel in the case of 400 (200 2) lines data data o 1 o 100 o 100 o 1 o 1 o 100 o 100 o 1 upper screen lower screen data data o 1 o 100 o 100 o 1 o 1 o 100 o 100 o 1 1st line 100th line 101st line 200th line 1st line 100th line 101st line 200th line
msm6648 ? semiconductor 9/9 in the case of 480 (240 2) lines data data o 1 o 100 o 1 o 100 o 100 o 1 upper screen lower screen 1st line 90th line 91st line 190th line 191st line 240th line 1st line 50th line 51st line 150th line 151st line 240th line o 10 o 11 o 100 o 1 o 91 o 90 data data o 1 o 100 o 1 o 100 o 100 o 1 o 50 o 51 o 100 o 1 o 51 o 50 o 1 o 100 o 90 o 91 o 100 o 1 o 11 o 10 10 pins not used 10 pins not used 10 pins not used 10 pins not used
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