1/9 preliminary data november 2004 this is preliminary information on a new product now in devel opment or undergoing evaluation. de tails are subject to change wit hout notice. m58bw032bt, m58bw032bb m58bw032dt, m58bw032db 32 mbit (1mb x32, boot block, burst) 3.3v supply flash memory features summary supply voltage ?v dd = 3.0v to 3.6v for program, erase and read ?v ddq = v ddqin = 1.6v to 3.6v for i/o buffers high performance ? access time: 45, 55 and 60ns ? 75mhz effective zero wait-state burst read ? synchronous burst reads ? asynchronous page reads memory organization ? eight 64 kbit small parameter blocks ? four 128kbit large parameter blocks (of which one is otp) ? sixty-two 512kbit main blocks hardware block protection ?wp pin lock program and erase ?v pen signal for program/erase enable software block protection ? tuning protection to lock program and erase with 64-bit user programmable password (m58bw032b version only) security ? 64-bit unique device identifier (uid) fast programming ? write to buffer and program capability optimized for fdi drivers ? common flash interface (cfi) ? fast program/erase suspend feature in each block low power consumption ? 100a typical standby figure 1. packages electronic signature ? manufacturer code: 20h ? top device code m58bw032xt: 8838h ? bottom device code m58bw032xb: 8837h operating temperature range ? automotive (grade 3): ? 40 to 125c ? industrial (grade 6): ? 40 to 90c bga lbga80 (za) 10 x 8 ball array pqfp80 (t)
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 2/9 summary description the m58bw032b/d is a 32mbit non-volatile flash memory that can be erased electrically at the block level and programmed in-system on a double- word basis using a 3.0v to 3.6v v dd supply for the circuit and a v ddq supply down to 1.6v for the in- put and output buffers. the devices support asynchronous (latch con- trolled and page read) and synchronous bus op- erations. the synchronous burst read interface allows a high data transfer rate controlled by the burst clock, k, signal. it is capable of bursting fixed or unlimited lengths of data. the burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. all writes are asynchronous. on power-up the memory defaults to read mode with an asynchronous bus. the device features an asymmetrical block archi- tecture. the m58bw032b/d has an array of 62 main blocks of 512 kbits each, plus 4 large param- eter blocks of 128kbits each and 8 small parame- ter blocks of 64 kbits each. the large and small parameter blocks are located either at the top (m58bw032bt, m58bw032dt) or at the bottom (m58bw032bb, m58bw032db) of the address space. the first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. all blocks are protected during power-up. the m58bw032b features four different levels of hard- ware and software block protection to avoid un- wanted program/erase operations: write/protect enable input, wp, provides a hardware protection of a combination of blocks from program or erase operations. the block protection configuration can be defined individually by issuing a set block protection configuration register or clear block protection configuration register commands. all program or erase operations are blocked when reset, rp, is held low. a program/erase enable input, v pen , is used to protect all blocks, preventing program and erase operations from affecting their data. the program and erase commands can be password protected by the tuning protection command. the m58bw032d offers the same protection fea- tures with the exception of the tuning block pro- tection which is disabled in the factory. a reset/power-down mode is entered when the rp input is low. in this mode the power consump- tion is reduced to the standby level, the device is write protected and both the status and burst con- figuration registers are cleared. a recovery time is required when the rp input goes high. a manufacturer and device code are available. they can be read from the memory allowing pro- gramming equipment or applications to automati- cally match their interface to the characteristics of the memory. finally, the m58bw032b/d features a unique de- vice identifier (uid) which is programmed by st. it is unique for each die and can be used to imple- ment cryptographic algorithms to improve securi- ty. the memory is offered in pqfp80 (14 x 20mm) and lbga80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to ?1?).
3/9 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 2. logic diagram table 1. signal names ai08918b a0-a19 l dq0-dq31 v dd m58bw032dt m58bw032db e v ss rp g gd v ddq w wp r k v pen b v ssq v ddqin m58bw032bt m58bw032bb a0-a19 address inputs dq0-dq7 data input/output, command input dq8-dq15 data input/output, burst configuration register dq16-dq31 data input/output b burst address advance e chip enable g output enable kburst clock l latch enable r valid data ready rp reset /power-down w write enable gd output disable wp write protect v dd supply voltage v ddq power supply for output buffers v ddqin power supply for input buffers only v pen program/erase enable v ss ground v ssq input/output ground nc not connected internally du don?t use as internally connected
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 4/9 figure 3. lbga connections (top view through package) ai08920b b dq24 dq7 v ssq f v ddq dq26 dq4 v ddq e dq29 v ss dq0 dq3 d a0 du a7 a11 a18 a17 c a1 a4 a5 a8 rp e a13 a16 b a2 a3 a6 v dd v pen v dd a14 a 8 7 6 5 4 3 2 1 dq20 dq18 dq19 dq17 dq11 dq12 dq13 v ddq dq23 dq8 v ddq h g du gd w v ddqin dq16 r g l dq14 dq15 k j a15 v ss a12 a9 a10 nc a19 nc dq31 dq30 dq2 dq28 dq6 dq25 v ssq dq10 dq9 dq21 wp k du dq1 dq27 dq5 nc dq22
5/9 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db figure 4. pqfp connections (top view through package) ai08919c 12 1 73 m58bw032bt m58bw032bb 53 v ddq dq24 dq25 dq18 dq17 dq16 dq19 dq20 dq21 dq22 dq23 v ddq dq29 dq26 dq30 du dq31 dq28 dq27 a2 a5 a3 a4 a0 a1 a11 v ss a12 a13 a14 a10 gd wp w du g v ss e k l nc b rp v ddq dq7 dq6 dq13 dq14 dq15 dq12 dq11 dq10 dq9 v ssq dq8 dq2 dq5 dq0 a19 a18 a16 a17 dq3 dq4 v ssq v ssq a8 a6 a7 v pen v dd a9 a15 dq1 v ddq v ssq r v dd nc v ddqin 24 25 32 40 41 64 65 80 m58bw032dt m58bw032db
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 6/9 block protection the m58bw032b features four different levels of block protection. the m58bw032d has the same block protection with the exception of the tuning block protection, which is disabled in the factory. write protect pin, wp , - when wp is low, v il , the protection status that has been configured in the block protection configuration register is activated. the block protection configuration register is volatile. any combination of blocks is possible. any attempt to program or erase a protected block will be ignored and will return an error in the status register. reset/power-down pin, rp , - if the device is held in reset mode (rp at v il ), no program or erase operations can be performed on any block. program/erase enable, v pen , - v pen protects all blocks preventing program and erase operations from affecting their data. program/erase enable must be kept high (v ih ) during all program/erase controller operations, otherwise the operations is not guaranteed to succeed and data may become corrupt. tuning block protection - m58bw032b features a 64 bit password protection for program and erase operations for a fixed number of blocks after power-up or reset the device is tuning protected. an unlock command is provided to allow program or erase operations in all the blocks. after a device reset the first two kinds of block pro- tection (wp , rp ) can be combined to give a flexi- ble block protection. they do not affect the tuning block protection. when the two protections are disabled, wp and rp at v ih , the blocks locked by the tuning block protection cannot be modified. all blocks are protected at power-up. tuning block protection the tuning block protection is a software feature to protect blocks from program or erase opera- tions. it allows the user to lock program and erase operations with a user definable 64 bit code. it is only available on the m58bw032b version. the code is written once in the tuning protection register and cannot be erased. when shipped the flash memory will have the tuning protection code bits set to ?1'. the user can program a ?0? in any of the 64 positions. once programmed it is not possible to reset a bit to ?1? as the cells cannot be erased. the tuning protection register can be programmed at any moment (after providing the correct code), however once all bits are set to ?0? the tuning protection code can no longer be al- tered. the tuning protection code locks the program and erase operations of all the blocks except for blocks 12 and 13 for the bottom configuration, and blocks 60 and 61 for the top configuration. the tuning blocks are "locked" if the tuning protec- tion code has not been provided, and ?unlocked" once the correct code has been provided. the tun- ing blocks are locked after reset or power-up. the tuning protection status can be monitored in the status register. refer to the status register sec- tion. refer to the command interface section for the tuning protection block unlock and tuning pro- tection program commands.
7/9 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db part numbering table 2. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m58bw032b t 45 t 3 t device type m58 architecture b = burst mode operating voltage w = v dd = 3.0v to 3.6v; v ddq = v ddqin =1.6 to v dd device function 032b = 32 mbit (x32), boot block, burst tuning protection 032d = 32 mbit (x32), boot block, burst no tuning protection array matrix t = top boot b = bottom boot speed 45 = 45ns 55 = 55ns 60 = 60ns package t = pqfp80 za = lbga80: 1.0mm pitch temperature range 3 = ?40 to 125 c 6 = ?40 to 85 c option t = tape & reel packing
m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db 8/9 revision history table 3. document revision history date version revision details 05-nov-2004 1.0 first issue.
9/9 m58bw032bt, m58bw032bb, m58bw032dt, m58bw032db information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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