k6t0808c1d family cmos sram revision 1.01 november 1997 document title 32kx8 bit low power cmos static ram revision history revision no 0.0 0.1 1.0 remark design target preliminily final history initial draft first revision - k m62256dl/dli i sb1 = 100 ? 50 m a km62256dl-l i sb1 = 20 ? 10 m a km62256dli-l i sb1 = 50 ? 15 m a - c in = 6 ? 8pf, c io = 8 ? 10pf - km62256d-4/5/7 family toh = 5 ? 10ns - km62256dl/dli i dr = 50 ? 30 m a km62256dl-l/dli-l i dr = 30 ? 15 m a finalize - remove i cc write value - improved operating current i cc2 = 70 ? 60ma - improved standby current km62256dl/dli i sb1 = 50 ? 30 m a km62256dl-l i sb1 = 10 ? 5 m a km62256dli-l i sb1 = 15 ? 5 m a - improved data retention current km62256dl/dli i dr = 30 ? 5 m a km62256dl-l/dli-l i dr = 15 ? 3 m a - remove 45ns part from commercial product and 100ns part from industrial product. replace test load 100pf to 50pf for 55ns part draft data may 18, 1997 april 1, 1997 november 11, 1997 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserves the right to change the spe cifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices.
k6t0808c1d family cmos sram revision 1.01 november 1997 32kx8 bit low power cmos static ram general description the k6t0808c1d families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and have various package types for user flexibility of system design. the fami- lies also support low data retention voltage for battery back- up operation with low data retention current. features process technology: tft organization: 32kx8 power supply voltage: 4.5~5.5v low data retention voltage: 2v(min) three state output and ttl compatible package type: 28-dip-600b, 28-sop-450 28-tsop1-0813.4 f/r pin description pin name function pin name function cs chip select input i/o 1 ~i/o 8 data inputs/outputs oe output enable input vcc power we write enable input vss ground a 0 ~a 14 address inputs nc no connect product family 1. the parameter is tested with 50pf test load. product family operating temperature v cc range speed power dissipation pkg type standby (i sb1 , max) operating (icc 2, max) k6t0808c1d-l commercial (0~70 c) 4.5 to 5.5v 55 1) /70ns 30 m a 60ma 28-dip-600b, 28-sop-450 28-tsop1-0813.4 f/r k6t0808c1d-b 5 m a k6t0808c1d-p industrial (-40~85 c) 70ns 30 m a 28-sop-450 28-tsop1-0813.4 f/r k6t0808c1d-f 5 m a functional block diagram a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 28-dip 28-sop 15 16 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a11 a9 a8 a13 we vcc a3 a14 a12 a7 a6 a5 a4 a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 28-tsop type1 - forward 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 28 25 24 23 22 21 20 19 18 17 16 15 oe 28-tsop a11 a9 a8 a13 we vcc a3 a14 a12 a7 a6 a5 a4 a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 28 25 24 23 22 21 20 19 18 17 16 15 oe type1 - reverse samsung electronics co., ltd. reserves the right to change products and specifications without notice. precharge circuit. memory array 256 rows 128 8 columns i/o circuit column select clk gen. row select a10 a3 a0 a1 a2 a11 a9 a13 a8 a12 a14 a4 a5 a7 cs we i/o 1 data cont data cont oe i/o 8 a6 control logic
k6t0808c1d family cmos sram revision 1.01 november 1997 product list commercial temperature products(0~70 c) industrial temperature products(-40~85 c) part name function part name function k6t0808c1d-dl55 k6t0808c1d-db55 k6t0808c1d-dl70 k6t0808c1d-db70 k6t0808c1d-gl55 k6t0808c1d-gb55 k6t0808c1d-gl70 k6t0808c1d-gb70 k6t0808c1d-tl55 k6t0808c1d-tb55 k6t0808c1d-tl70 k6t0808c1d-tb70 k6t0808c1d-rl55 k6t0808c1d-rb55 k6t0808c1d-rl70 k6t0808c1d-rb70 28-dip, 55ns, l-pwr 28-dip, 55ns, ll-pwr 28-dip, 70ns, l-pwr 28-dip, 70ns, ll-pwr 28-sop, 55ns, l-pwr 28-sop, 55ns, ll-pwr 28-sop, 70ns, l-pwr 28-sop, 70ns, ll-pwr 28-tsop1-f, 55ns, l-pwr 28-tsop1-f, 55ns, ll-pwr 28-tsop1-f, 70ns, l-pwr 28-tsop1-f, 70ns, ll-pwr 28-tsop1-r, 55ns, l-pwr 28-tsop1-r, 55ns, ll-pwr 28-tsop1-r, 70ns, l-pwr 28-tsop1-r, 70ns, ll-pwr k6t0808c1d-gp70 k6t0808c1d-gf70 k6t0808c1d-tp70 k6t0808c1d-tf70 k6t0808c1d-rp70 k6t0808c1d-rf70 28-sop, 70ns, l-pwr 28-sop, 70ns, ll-pwr 28-tsop1-f, 70ns, l-pwr 28-tsop1-f, 70ns, ll-pwr 28-tsop1-r, 70ns, l-pwr 28-tsop1-r, 70ns, ll-pwr functional description 1. x means don t care (must be in high or low states) cs oe we i/o mode power h x 1) x 1) high-z deselected standby l h h high-z output disabled active l l h dout read active l x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to 7.0 v - voltage on vcc supply relative to vss v cc -0.5 to 7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t0808c1d-l/-b -40 to 85 c k6t0808c1d-p/-f soldering temperature and time t solder 260 c, 10sec (lead only) - -
k6t0808c1d family cmos sram revision 1.01 november 1997 recommended dc operating conditions 1) note: 1. commercial product: t a =0 to 70 c, otherwise specified industrial product: t a =-40 to 85 c, otherwise specified 2. overshoot: v cc +3.0v in case of pulse width 30ns 3. undershoot: -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested item symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.5v 2) v input low voltage v il -0.5 3) - 0.8 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled not, 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il , v io =v ss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs =v il, v in =v ih or v il , read - 5 10 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma cs 0.2v, v in 0.2v, v in 3 vcc -0.2v read - 2 5 ma write - 20 i cc2 cycle time=min,100% duty, i io =0ma, cs =v il, v in =v ih or v il - 45 60 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs =v ih , other inputs=v ih or v il - - 1 ma standby current (cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc low power - 1 30 m a low low power - 0.2 5 m a
k6t0808c1d family cmos sram revision 1.01 november 1997 c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.8 to 2.4v input rising and falling time: 5ns input and output reference voltage: 1.5v output load (see right): c l =100pf+1ttl c l =50pf+1ttl ac characteristics (vcc=4.5~5.5v, commercial product: t a =0 to 70 c, industrial product: t a =-40 to 85 c) 1. the parameter is tested with 50pf test load. parameter list symbol speed bins units 55 1) ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co - 55 - 70 ns output enable to valid output t oe - 25 - 35 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 20 0 30 ns output disable to high-z output t ohz 0 20 0 30 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 40 - 50 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns data retention characteristics item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 2.0 - 5.5 v data retention current i dr vcc=3.0v, cs 3 vcc-0.2v l-ver - 1 15 m a ll-ver - 0.2 3 data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
k6t0808c1d family cmos sram revision 1.01 november 1997 address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs address oe data ou t notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oh t aa t olz t lz t ohz t hz t rc t oe t co
k6t0808c1d family cmos sram revision 1.01 november 1997 timing waveform of write cycle(2) ( cs controlled) address cs t wc t wr(4) t as(3) t dw t dh data valid we data in data out high-z high-z t cw(2) t wp(1) t aw notes (write cycle) 1. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low : a write end at the earliest transition among cs going high and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs or we going high. data retention wave form cs controlled v cc 4.5v 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(1) ( we controlled) address cs t cw(2) t wr(4) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t wc t aw t as(3)
k6t0808c1d family cmos sram revision 1.01 november 1997 package dimensions units: millimeter(inch) 1.65 #1 28 pin dual inline package(600mil) #28 13.60 0.20 0.535 0.008 36.32 0.20 1.430 0.008 ( ) 0.065 1.52 0.10 0.060 0.004 0.46 0.10 0.018 0.004 1 5 . 2 4 0 . 6 0 0 + 0.10 max 36.72 1.446 0.25 - 0.05 + 0.004 0.010 - 0.002 #14 #15 2.54 0.100 max 3.81 0.20 0.150 0.008 5.08 0.200 min 0.015 0.38 0.130 0.012 3.30 0.30 0~15 28 pin plastic small outline package(450mil) 0~8 #28 11.81 0.30 0.465 0.012 18.29 0.20 0.720 0.008 max 18.69 0.736 max 2.59 0.20 0.102 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #15 0.41 0.10 0.016 0.004 #1 #14 0.89 ( ) 0.035 1 1 . 4 3 0 . 4 5 0 8.38 0.20 0.330 0.008 1.02 0.20 0.040 0.008 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 1.27 0.050
k6t0808c1d family cmos sram revision 1.01 november 1997 package dimensions 28 pin thin small outline package type1 (0813.4f) #28 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 m a x 0 . 1 0 m a x #1 13.40 0.20 0.528 0.008 #15 #14 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.55 0.0217 0.425 ( ) 0.017 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 #28 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 m a x 0 . 1 0 m a x #1 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 13.40 0.20 0.528 0.008 #15 #14 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 0.425 ( ) 0.017 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 0.55 0.0217 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 28 pin thin small outline package type1 (0813.4r) 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 typ 0.25 0.010 units: millimeter(inch)
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