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femtoclock? crystal-to-lvcmos/lvttl clock generator ics840021 idt? / ics? lvcmos clock generator 1 ics840021ag rev. b april 28, 2009 general description the ics840021 is a gigabit ethernet clock generator and a member of the hiperclocks tm family of high performance devices from idt. the ics840021 uses a 25mhz crystal to synthesize 125mhz. the ics840021 has excellent phase jitter performance, over the 1.875mhz ? 20mhz integration range. the ics840021 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. features ? one lvcmos/lvttl output, 7 ? output impedance ? crystal oscillator interface designed for 25mhz, 18pf parallel resonant crystal ? output frequency: 125mhz ? vco range: 560mhz to 680mhz ? rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.34ps (typical) 3.3v ? rms phase noise at 125mhz (typical) ? phase noise: offset noise power 100hz ................-96.9 dbc/hz 1khz ..............-122.2 dbc/hz 10khz ..............-131.1 dbc/hz 100hz ..............-129.5 dbc/hz ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 1 2 3 4 8 7 6 5 v dda oe xtal_out xtal_in v dd q0 gnd reserved pin assignment ics840021 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view block diagram osc phase detector vco 5 25 (fixed) q0 pullup oe xtal_in xtal_out 25mhz
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 2 ics840021ag rev. b april 28, 2009 table 1. pin descriptions note: pullup refers to internal input resistors. see table 1, pin characteristics, for typical values. table 2. pin characteristics function table table 3. control function table number name type description 1v dda power analog supply pin. 2 oe input pullup output enable pin. when high, q0 output is enabled. when low, forces q0 to high-impedance state. lvcmos/lvttl interface levels. 3, 4 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 5 reserved reserved reserve pin. 6 gnd power power supply ground. 7 q0 output single-ended clock output. lvcmos/lvttl interface levels. 7 ? output impedance. 8v dd power core supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf c pd power dissipation capacitance v dd = 3.465v 24 pf r pullup input pullup resistor 51 k ? r out output impedance 5 7 12 ? control input output oe q0 0 high-impedance 1active
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 3 ics840021ag rev. b april 28, 2009 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c note 1: outputs terminated with 50 ? to v dd /2. see parameter measurement information se ction, "3.3v output load test circuit" diagram. item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 101.7 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v i dd power supply current 75 ma i dda analog supply current 15 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd +0.3 v v il input low voltage -0.3 0.8 v i ih input high current v dd = v in = 3.465v 5a i il input low current v dd =3.465v, v in = 0v -150 a v oh output high voltage; note 1 2.6 v v ol output high voltage; note 1 0.5 v
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 4 ics840021ag rev. b april 28, 2009 table 5. crystal characteristics ac electrical characteristics table 6. ac characteristics, v dd = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 1: please refer to phase noise plots. parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf drive level 1mw symbol parameter test conditio ns minimum typical maximum units f out output frequency 125 mhz t jit(?) rms phase jitter, random; note 1 integration range: 1.875mhz ? 20mhz 0.34 ps t r / t f output rise/fall time 20% to 80% 250 550 ps odc output duty cycle 48 52 %
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 5 ics840021ag rev. b april 28, 2009 typical phase noise at 125mhz 10 gb ethernet filter phase noise result by adding a 10 gb ethernet filter to raw data raw phase noise data 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.34ps (typical) noise power dbc hz offset frequency (hz)
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 6 ics840021ag rev. b april 28, 2009 parameter measureme nt information 3.3v output load ac test circuit output duty cycle/pulse width/period rms phase jitter output rise/fall time scope qx lvcmos gnd v dd, 1.65v ? 5 -1.65v ? 5 v dda t period t pw t period odc = v dd 2 x 100% t pw q0 phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power q0 20% 80% 80% 20% t r t f
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 7 ics840021ag rev. b april 28, 2009 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform- ance, power supply isolation is required. the ics840021provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individ- ually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering crystal input interface the ics840021 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 2. crystal input interface v dd v dda 3.3v 10 ? 10f .01f .01f xtal_in xtal_out x1 18pf parallel crystal c1 33p c2 22p
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 8 ics840021ag rev. b april 28, 2009 lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v dd v dd
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 9 ics840021ag rev. b april 28, 2009 application schematic figure 4a shows a schematic example of the ics840021. an example of lvcmos termination is shown in this schematic. additional lvcmos termination approaches are shown in the lvcmos termination application note. in this example, an 18pf parallel resonant 25mhz crystal is used for generating 125mhz output frequency. the c1 = 27pf and c2 = 33pf are recommended for frequency accuracy. for different board layout, the c1 and c2 values may be slightly adjusted for optimizing frequency accuracy. figure 4a. ics840021 schematic example pc b oard l ayout e xample figure 4b shows an example of ics840021 p.c. board layout. the crystal x1 footprint shown in this example allows installation of either surface mount hc49s or through-hole hc49 package. the footprints of other components in this example are listed in the table 7. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. figure 4b. ics840021 pc board layout example table 7. footprint table note: table 7, lists component sizes shown in this layout example. vdd oe vdda vdd c1 22pf r2 10 r3 43 c5 0.1u c4 0.1u c2 33pf x1 zo = 50 ohm c3 10uf q lvcmos u1 ics840021i vdda 1 oe 2 xtal_out 3 xtal_in 4 vdd 8 q0 7 gnd 6 reserv ed 5 vdd=3.3v reference size c1, c2 0402 c3 0805 c4, c5 0603 r2, r3 0603
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 10 ics840021ag rev. b april 28, 2009 reliability information table 8. ja vs. air flow table for a 8 lead tssop transistor count the transistor count for ics840021 is: 1961 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 11 ics840021ag rev. b april 28, 2009 package outline and package dimensions package outline - g suffix for 8 lead tssop table 9. package dimensions reference document: jede c publication 95, mo-153 all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 12 ics840021ag rev. b april 28, 2009 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 840021ag 021ag 8 lead tssop tube 0 c to 70 c 840021agt 021ag 8 lead tssop 2500 tape & reel 0 c to 70 c 840021aglf 021al ?lead-free? 8 lead tssop tube 0 c to 70 c 840021AGLFT 021al ?lead-free? 8 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserv es the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics840021 femtoclock?crystal-to-lvcmos /lvttl clock generator idt? / ics? lvcmos clock generator 13 ics840021ag rev. b april 28, 2009 revision history sheet rev table page description of change date a t10 10 ordering information table - correct count from 154 to 100. 10/14/04 a t8 3 8 absolute maximum ratings - corrected package thermal impedance air flow. corrected air flow in table. 11/30/04 a t10 1 10 features section - added lead-free bullet. ordering information table - added lead-free part number and marking. 10/7/05 a 8 added lvcmos to xtal interface section. changed formatting throughout data sheet. 1/10/09 b t1 1 2 pin assignment - changed pin 5 from nc to reserved. pin description table - changed pin 5 from nc to reserved. 4/15/09
ics840021 femtoclock?crystal-to-lvcmos/lvttl clock generator www.idt.com ? 2009 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contact idt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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