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obsolete product ? xicor, inc. 2000 patents pending 9900-2002.1 11/4/03 ep characteristics subject to change without notice. 1 of 14 1k x24c01 128 x 8 bit serial e 2 prom features 2.7v to 5.5v power supply ? ow power cmos active current less than 1 ma standby current less than 50 ? internally organized 128 x 8 ? wire serial interface bidirectional data transfer protocol four byte page write mode self timed write cycle ? ypical write cycle time of 5 ms high reliability endurance: 1 million cycles data retention: 100 years 8-pin mini-dip, 8-pin msop, and 8-pin soic packages description the x24c01 is a cmos 1024 bit serial e 2 prom, internally organized as 128 x 8. the x24c01 features a serial interface and software protocol allowing opera- tion on a simple two wire bus. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data retention is greater than 100 years. functional diagram start stop logic control logic h.v. generation timing & control word address counter xdec ydec d out ack e 2 prom 32 x 32 data register start cycle (8) v cc r/w pin (4) v ss (5) sda (6) scl d out load inc ck 8
obsolete product x24c01 characteristics subject to change without notice. 2 of 14 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output, and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guide- lines for calculating typical values of bus pull-up resistors graph. pin names a.c. conditions of test pin configuration equivalent a.c. load circuit symbol description nc no connect v ss ground v cc supply voltage sda serial data scl serial clock input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input and output timing levels v cc x 0.5 nc nc nc v ss v cc nc scl x24c01 plastic nc nc nc v ss v cc nc scl x24c01 soic/msop sdl sdl 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 2190 ? 100pf output 5v
obsolete product x24c01 characteristics subject to change without notice. 3 of 14 device operation the x24c01 supports a bidirectional bus oriented pro- tocol. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and pro- vide the clock for both transmit and receive operations. therefore, the x24c01 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24c01 continuously monitors the sda and scl lines for the start condition, and will not respond to any command until this condition has been met. figure 1. data validity scl sda data stable data change
obsolete product x24c01 characteristics subject to change without notice. 4 of 14 stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used by the x24c01 to place the device in the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24c01 will respond with an acknowledge after recognition of a start condition, a seven bit word address and a r/w bit. if a write operation has been selected, the x24c01 will respond with an acknowl- edge after each byte of data is received. in the read mode, the x24c01 will transmit eight bits of data, release the sda line, and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24c01 will continue to transmit data. if an acknowledge is not detected, the x24c01 will terminate further data trans- missions. the master must then issue a stop condition to return the x24c01 to the standby power mode and place the device into a known state. figure 2. definition of start and stop figure 3. acknowledge response from receiver scl sda start condition stop condition scl from master data output from transmitter data output from receiver start acknowledge 189
obsolete product x24c01 characteristics subject to change without notice. 5 of 14 write operations byte write to initiate a write operation, the master sends a start condition followed by a seven bit word address and a write bit. the x24c01 responds with an acknowledge, then waits for eight bits of data and then responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the x24c01 begins the internal write cycle to the non- v olatile memory. while the internal write cycle is in progress, the x24c01 inputs are disabled, and the device will not respond to any requests from the mas- ter. refer to figure 4 for the address, acknowledge and data transfer sequence. page write the most signi?ant ?e bits of the word address de?e the page address. the x24c01 is capable of a f our byte page write operation. it is initiated in the same manner as the byte write operation, but instead of terminating the transfer of data after the ?st data b yte, the master can transmit up to three more bytes. after the receipt of each data byte, the x24c01 will respond with an acknowledge. after the receipt of each data byte, the two low order address bits are internally incremented by one. the high order ?e bits of the address remain constant. if the master should transmit more than four data bytes prior to generating the stop condition, the address counter will ?oll over and the previously transmitted data will be overwritten. as with the byte write opera- tion, all inputs are disabled until completion of the inter- nal write cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. figure 4. byte write figure 5. page write bus activity: sda line bus activity: x24c01 s t a word address (n) s t p a data n r / l s b s a o p r t m s b w c k c k bus activity: sda line bus activity: x24c01 s t a s s t p a a a word address (n) data n data n+1 data n+3 a r l s b o p c k c k c k c k / w r t
obsolete product x24c01 characteristics subject to change without notice. 6 of 14 acknowledge polling the disabling of the inputs can be used to take advan- tage of the typical 5 ms write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the x24c01 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the w ord address for a write operation. if the x24c01 is still busy with the write operation, no ack will be returned. if the x24c01 has completed the write oper- ation an ack will be returned, and the controller can then proceed with the next read or write operation. read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the word address is set to a one. there are two basic read operations: byte read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. byte read to initiate a read operation, the master sends a start condition followed by a seven bit word address and a read bit. the x24c01 responds with an acknowledge and then transmits the eight bits of data. the read operation is terminated by the master by not respond- ing with an acknowledge and issuing a stop condition. refer to figure 7 for the start, word address, read bit, acknowledge and data transfer sequence. figure 6. ack polling sequence figure 7. byte read write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? proceed issue stop no yes yes proceed issue stop no bus activity: master sda line bus activity: x24c01 s t a word address n s t p a data n r l s b s r t o p / w c k m s b
obsolete product x24c01 characteristics subject to change without notice. 7 of 14 sequential read sequential read is initiated in the same manner as the b yte read. the ?st data byte is transmitted as with the b yte read mode, however, the master now responds with an acknowledge, indicating it requires additional data. the x24c01 continues to output data for each acknowledge received. the read operation is termi- nated by the master by not responding with an acknowledge, and issuing a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 127) the counter ?olls over to zero and the x24c01 continues to output data for each acknowl- edge received. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 8. sequential read figure 9. typical system configuration bus activity: sda line bus activity: x24c01 address a a data n+x s t p data n a data n+1 a data n+2 r / w c k c k c k c k o p master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl vcc
obsolete product x24c01 characteristics subject to change without notice. 8 of 14 absolute maximum ratings t emperature under bias ....................?5? to +135? storage temperature .........................?5? to +150? v oltage on any pin with respect to vss ................................. ?.0v to +7.0v d. c. output current .............................................. 5 ma lead temperature......................................................... (soldering, 10 seconds) ..................................300? recommended operating conditions comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. d.c. operating characteristics (over recommended operating conditions, unless otherwise specified) capacitance t a = 25?, f = 1.0 mhz, v cc = 5v notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. temperature min. max. commercial 0? 70? industrial ?0? +85? military ?5? +125? supply voltage limits x24c01 4.5v to 5.5v x24c01-3.5 3.5v to 5.5v x24c01-3 3.0v to 5.5v x24c01-2.7 2.7v to 5.5v symbol parameter limits units test conditions min. max. i cc (1) v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100 khz, sda = open i cc (2) v cc supply current (write) 2 i sb1 (1) v cc standby current 100 ? scl = sda = v cc , v cc = 5v ?10% i sb2 (1) v cc standby current 50 ? scl = sda = v cc , v cc = 2.7v i li input leakage current 10 ? v in = gnd to v cc i lo output leakage current 10 ? v out = gnd to v cc v ll (2) input low voltage ?.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1 ma symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (scl) 6 pf v in = 0v
obsolete product x24c01 characteristics subject to change without notice. 9 of 14 a.c. characteristics (over recommended operating conditions, unless otherwise specified) read & write cycle limits power-up timing bus timing notes: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 ? t buf time the bus must be free before a new transmission can start 4.7 ? t hd:sta start condition hold time 4.0 ? t low clock low period 4.7 ? t high clock high period 4.0 ? t su:sta start condition setup time 4.7 ? t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 ? t dh data out hold time 300 ns symbol parameter max. units t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high
obsolete product x24c01 characteristics subject to change without notice. 10 of 14 write cycle limits the write cycle time is the time from a valid stop condi- tion of a write sequence to the end of the internal erase/program cycle. during the write cycle, the x24c01 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its word address. write cycle timing notes: (5) typical values are for t a = 25? and nominal supply voltage (5v). (6) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. guidelines for calculating typical values of bus pull-up resistors symbol table symbol parameter min. typ.(5) max. units t wr (6) write cycle time 5 10 ms sda 8th bit word n ack t wr stop condition start condition x24c01 address scl 120 100 80 40 60 20 20 40 60 80 100 120 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max = 2.6k 0 0 resistance (k ? ) wa veform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
obsolete product x24c01 characteristics subject to change without notice. 11 of 14 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic, pdip, package code p8 half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62)
obsolete product x24c01 characteristics subject to change without notice. 12 of 14 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint 8-lead plastic, soic, package code s8
obsolete product x24c01 characteristics subject to change without notice. 13 of 14 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) ref. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ note: 1. all dimensions in inches and (millimeters) 0.220" 0.0256" typical 0.025" typical 0.020" typical 8 places footprint 8-lead plastic, msop, package code m8
obsolete product x24c01 characteristics subject to change without notice. 14 of 14 ?icor, inc. 2001 patents pending limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, e xpress, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. copyrights and trademarks xicor, inc., the xicor logo, e 2 pot, xdcp, xbga, autostore, direct write cell, concurrent read-write, pass, mps, pushpot, block lock, identiprom, e 2 key, x24c16, secureflash, and serialflash are all trademarks or registered trademarks of xicor, inc. all other brand and produc t names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. u .s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information device v cc limits blank = 4.5v to 5.5v 3.5 = 3.5v to 5.5v 3 = 3.0v to 5.5v 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? m = military = ?5? to +125? package p = 8-lead plastic dip s = 8-lead soic m = 8-lead msop x24c01 x -x x24c01 x x blank = 8-lead soic p = 8-lead plastic dip m = 8-lead msop blank = 4.5v to 5.5v, 0? to +70? f = 2.7v to 5.5v, 0? to +70? g = 2.7v to 5.5v, ?0? to +85? i = 4.5v to 5.5v, ?0? to +85? b = 3.5v to 5.5v, 0? to +70? c = 3.5v to 5.5v, ?0? to +85? d = 3.0v to 5.5v, 0? to +70? e = 3.0v to 5.5v, ?0? to +85? m = 4.5v to 5.5v, ?5? to +125? part mark convention x

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