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power management 1 www.semtech.com sc1172 & sc1173 programmable synchronous dc/dc converter with ldo controller features applications revision 1, january 2001 description the sc1172/3 combines a synchronous voltage mode con- troller with a low-dropout linear regulator providing most of the circuitry necessary to implement two dc/dc con- verters for powering advanced microprocessors such as pentium ? ii . the sc1172/3 switching section features an integrated 5 bit d/a converter, pulse by pulse current limiting, inte- grated power good signaling, and logic compatible shut- down. the sc1172/3 switching section operates at a fixed frequency of 200khz, providing an optimum compromise between size, efficiency and cost in the intended applica- tion areas. the integrated d/a converter provides pro- grammability of output voltage from 2.0v to 3.5v in 100mv increments and 1.30v to 2.05v in 50mv increments with no external components. the sc1172/3 linear section is a low dropout regulator. the sc1172 supplies 1.5v for gtl bus , the sc1173 fea- tures an adjustable ldo voltage. u synchronous design, enables no heatsink solution. u 95% efficiency (switching section). u 5 bit dac for output programmability. u on chip power good function. u designed for intel pentium ? ll vrm8.1 requirements. u 1.5v or adjustable @ 1% for linear section. u pentium ? ll microprocessor supplies u flexible motherboards u 1.3v to 3.5v microprocessor supplies u programmable triple power supplies typical application circuit ovp + 4.7uf u4 sc1172/3csw 1 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 13 12 14 24 2 23 3 4 agnd vcc ovp pwrgood cs- cs+ pgndh dh bsth en vosense vid4 vid3 vid2 vid1 vid0 dl pgndl bstl gate nc ldov nc ldos 10 + 330uf 5mohm x4 irlr3103n 0.1uf vid3 1.5v irlr3103n vid1 0.1uf + 1500uf 12v 0.1uf vcc_core 2.32k vid0 + 330uf 2r2 5v 3.3v 2r2 vid4 pwrgood vid2 1.9uh irlr024n en + 1500uf 0.1uf 1.00k x2
2 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 electrical characteristics absolute maximum ratings r e t e m a r a pl o b m y sm u m i x a ms t i n u d n g a o t c c vv n i 7 + o t 3 . 0 -v d n g o t h d n g p , l d n g p 1 v l d n g p o t l t s b , h d n g p o t h t s bv t s o o b 5 1 + o t 3 . 0 -v e g n a r e r u t a r e p m e t g n i t a r e p ot a 0 7 + o t 0c e g n a r e r u t a r e p m e t n o i t c n u jt j 5 2 1 + o t 0c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt l 0 0 3c t n e i b m a o t n o i t c n u j e c n a d e p m i l a m r e h t q a j 0 8w / c e s a c o t n o i t c n u j e c n a d e p m i l a m r e h t q c j 5 2w / c r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u n o i t c e s g n i h c t i w s e g a t l o v t u p t u oi o t i u c r i c n o i t a c i l p p a n i a 2 =e l b a t e g a t l o v t u p t u o e e s e g a t l o v y l p p u s 5 . 47v t n e r r u c y l p p u sv n i v 0 . 5 =85 1a m n o i t a l u g e r d a o li o a 5 1 o t a 8 . 0 =1% n o i t a l u g e r e n i l 5 . 0% e g a t l o v g n i t a r e p o m u m i n i m 2 . 4v e g a t l o v t i m i l t n e r r u c 0 60 70 8v m y c n e u q e r f r o t a l l i c s o 0 8 10 0 20 2 2z h k e l c y c y t u d x a m r o t a l l i c s o 0 95 9% t n e r r u c e c r u o s / k n i s h d k a e p, v 5 . 4 = h d - h t s bv 2 = h d n g p - h d1 a t n e r r u c e c r u o s / k n i s l d k a e p, v 5 . 4 = l d - l t s bv 2 = l d n g p - l d1 a o c p m e t e g a t l o v t u p t u o 0 30 0 1/ m p p o c a ( n i a g l o )v e s n e s o v o t o 5 3b d e g a t l o v d l o h s e r h t p v o 0 2 1% t n e r r u c e c r u o s p v ov p v o v 0 . 3 =0 1a m e g a t l o v d l o h s e r h t d o o g r e w o p 8 82 1 1% e m i t d a e d 0 50 0 1s n unless specified: v in =4.75v to 5.25v; agnd=pgndh=pgndl=0v; vosense=v o ; 0mv< (cs+-cs-)< 60mv; ldov= v boost = 11.4v to 12.6v; t a = 25c
3 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 electrical characteristics (cont.) r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u s n o i t c e s r a e n i l t n e r r u c t n e c s e i u qi q v 2 1 = v o d l5a m ) 2 7 1 1 c s ( e g a t l o v t u p t u o 5 8 4 . 10 0 5 . 15 1 5 . 1v ) 3 7 1 1 c s ( e g a t l o v e c n e r e f e rv f e r 2 5 2 . 15 6 2 . 18 7 2 . 1v ) 3 7 1 1 c s ( t n e r r u c s a i b n i p k c a b d e e fi b f 0 1 m a a ( n i a g l o )e t a g o t s o d l0 9b d n o i t a l u g e r d a o li o a 8 o t 0 =3 . 0% n o i t a l u g e r e n i l 3 . 0% e c n a d e p m i t u p t u ov 5 . 6 = e t a g v0 0 2 w note: (1) this device is esd sensitive. use of standard esd handling precautions is required.
4 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 note: (1) all logic level inputs and outputs are open collector ttl compatible. pin configuration ordering information pin descriptions r e b m u n t r a p ) 1 ( e g a k c a pr a e n i l e g a t l o v p m e t t ( e g n a r j ) r t . w s c 2 7 1 1 c s4 2 - o sv 5 . 1c 5 2 1 o t 0 r t . w s c 3 7 1 1 c s4 2 - o se l b a t s u j d ac 5 2 1 o t 0 note: (1) only available in tape and reel packaging. a reel contains 1000 devices. # n i pe m a n n i pn o i t c n u f n i p 1d n g ad n u o r g l a t i g i d d n a g o l a n a l a n g i s l l a m s 2c nn o i t c e n n o c o n 3c nn o i t c e n n o c o n 4s o d lo d l r o f t u p n i e s n e s 5c c ve g a t l o v t u p n i 6p v ov f i t u o l a n g i s h g i h o % 0 2 + t n i o p t e s > 7d o o g r w p ) 1 ( v f i h g i h , t u p t u o c i g o l r o t c e l l o c n e p o o t n i o p t e s f o % 0 1 n i h t i w 8- s c) e v i t a g e n ( t u p n i e s n e s t n e r r u c 9+ s c) e v i t i s o p ( t u p n i e s n e s t n e r r u c 0 1h d n g ph c t i w s e d i s h g i h r o f d n u o r g r e w o p 1 1h dt u p t u o r e v i r d e d i s h g i h 2 1l d n g ph c t w s e d i s w o l r o f d n u o r g r e w o p 3 1l dt u p t u o r e v i r d e d i s w o l 4 1l t s br e v i r d e d i s w o l r o f y l p p u s 5 1h t s br e v i r d e d i s h g i h r o f y l p p u s 6 1n e ) 1 ( . n o i t a r e p o l a m r o n r o f n e p o r o h g i h . r e t r e v n o c e h t n w o d s t u h s w o l c i g o l 7 1e s n e s o vn i a h c k c a b d e e f l a n r e t n i f o d n e p o t 8 14 d i v ) 1 ( ) b s m ( t u p n i g n i m m a r g o r p 9 13 d i v ) 1 ( t u p n i g n i m m a r g o r p 0 22 d i v ) 1 ( t u p n i g n i m m a r g o r p 1 21 d i v ) 1 ( t u p n i g n i m m a r g o r p 2 20 d i v ) 1 ( ) b s l ( t u p n i g n i m m a r g o r p 3 2v o d ln o i t c e s o d l r o f v 2 1 + 4 2e t a go d l t u p t u o e v i r d e t a g 1 2 3 4 5 6 7 8 gate agnd top view (24 pin soic) 13 14 15 16 ldov nc vid0 nc vid1 ldos vid2 vcc vid3 ovp vid4 pwrgood vosense cs- 9 10 22 en cs+ bsth pgndh 21 18 17 19 20 11 12 24 bstl dh dl pgndl 23
5 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 block diagram synchronous drive vcc r s q + - 70mv 1.265v ref vid0 ldos d/a pwrgood ref en ovp agnd + - ldov oscillator level shift and high side drive dl pgndl + - + - dh open collectors vid3 gate bsth shoot thru control + - current limit vosense + - agnd vid1 agnd error amp fet controller 1.5v/adj. cs+ bstl vcc pgndh vid4 vid2 cs- setting ldo output voltage. r b r a v t u o o d l v 5 4 . 35 0 1 w 2 8 1 w v 0 3 . 35 0 1 w 9 6 1 w v 0 1 . 32 0 1 w 7 4 1 w v 0 9 . 20 0 1 w 0 3 1 w v 0 8 . 20 0 1 w 1 2 1 w v 0 5 . 20 0 1 w 6 . 7 9 w v 0 5 . 10 0 1 w 7 . 8 1 w for the sc1173, the ldo output voltage must be set by selecting appropriate resistor values. these values may be determined from the equation below, or from the table at right. error t significan cause not does term ) r (i the that so enough low be must r ion clarificat for diagram layout see resistor feedback bottom r resistor feedback top r current bias pin feedback i : where ) r i ( r ) r r ( 265 . 1 v a fb a b a fb a fb b b a out = = = + + =
6 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 output voltage table unless specified: 4.75v < vcc < 5.25v; gnd = pgnd = 0v; vosense = v o ; 0mv < (cs+-cs-) < 60mv; t a = 25c r e t e m a r a ps n o i t i d n o cd i v 0 1 2 3 4 n i mp y tx a ms t i n u e g a t l o v t u p t u oi o t i u c r i c n o i t a c i l p p a n i a 2 =1 1 1 1 07 8 2 . 10 0 3 . 13 1 3 . 1v 0 1 1 1 06 3 3 . 10 5 3 . 14 6 3 . 1 1 0 1 1 06 8 3 . 10 0 4 . 14 1 4 . 1 0 0 1 1 05 3 4 . 10 5 4 . 15 6 4 . 1 1 1 0 1 05 8 4 . 10 0 5 . 15 1 5 . 1 0 1 0 1 04 3 5 . 10 5 5 . 16 6 5 . 1 1 0 0 1 04 8 5 . 10 0 6 . 16 1 6 . 1 0 0 0 1 03 3 6 . 10 5 6 . 17 6 6 . 1 1 1 1 0 03 8 6 . 10 0 7 . 17 1 7 . 1 0 1 1 0 02 3 7 . 10 5 7 . 18 6 7 . 1 1 0 1 0 02 8 7 . 10 0 8 . 18 1 8 . 1 0 0 1 0 01 3 8 . 10 5 8 . 19 6 8 . 1 1 1 0 0 01 8 8 . 10 0 9 . 19 1 9 . 1 0 1 0 0 00 3 9 . 10 5 9 . 10 7 9 . 1 1 0 0 0 00 8 9 . 10 0 0 . 20 2 0 . 2 0 0 0 0 09 2 0 . 20 5 0 . 21 7 0 . 2 1 1 1 1 10 8 9 . 10 0 0 . 20 2 0 . 2 0 1 1 1 19 7 0 . 20 0 1 . 21 2 1 . 2 1 0 1 1 18 7 1 . 20 0 2 . 22 2 2 . 2 0 0 1 1 17 7 2 . 20 0 3 . 23 2 3 . 2 1 1 0 1 16 7 3 . 20 0 4 . 24 2 4 . 2 0 1 0 1 15 7 4 . 20 0 5 . 25 2 5 . 2 1 0 0 1 14 7 5 . 20 0 6 . 26 2 6 . 2 0 0 0 1 13 7 6 . 20 0 7 . 27 2 7 . 2 1 1 1 0 12 7 7 . 20 0 8 . 28 2 8 . 2 0 1 1 0 11 7 8 . 20 0 9 . 29 2 9 . 2 1 0 1 0 10 7 9 . 20 0 0 . 30 3 0 . 3 0 0 1 0 19 6 0 . 30 0 1 . 31 3 1 . 3 1 1 0 0 18 6 1 . 30 0 2 . 32 3 2 . 3 0 1 0 0 17 6 2 . 30 0 3 . 33 3 3 . 3 1 0 0 0 16 6 3 . 30 0 4 . 34 3 4 . 3 0 0 0 0 15 6 4 . 30 0 5 . 35 3 5 . 3
7 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 layout guidelines careful attention to layout requirements are necessary for successful implementation of the sc1172/3 pwm con- troller. high currents switching at 200khz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). the high power parts of the circuit should be laid out first. a ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bot- tom fet ground. 2). the loop formed by the input capacitor(s) (cin), the top fet (q1) and the bottom fet (q2) must be kept as small as possible. this loop contains all the high current, fast transition switching. connections should be as wide and as short as possible to minimize loop inductance. mini- mizing this loop area will a) reduce emi, b) lower ground injection currents, resulting in electrically ?cleaner? grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). the connection between the junction of q1, q2 and the output inductor should be a wide trace or copper re- gion. it should be as short as practical. since this connec- tion has fast voltage transitions, keeping this connection short will minimize emi. the connection between the out- put inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transi- tions in this connection and length is not so important, however adding unnecessary impedance will reduce effi- ciency. vout 12v in 3.3v 5v l 5mohm + cout + cin 10 q2 0.1uf 2.32k 1.00k + cin lin sc1172/3 agnd 1 vcc 5 ovp 6 pwrgood 7 cs- 8 cs+ 9 pgndh 10 dh 11 bsth 15 en 16 vosense 17 vid4 18 vid3 19 vid2 20 vid1 21 vid0 22 dl 13 pgndl 12 bstl 14 gate 24 nc 2 ldov 23 nc 3 ldos 4 q1 0.1uf heav y lines indicate hi g h current paths. la y out dia g ram sc1172/3 for sc1172, ra and rb are not required. ldos connects to vo lin vo lin2 q4 + cout lin2 ra rb
8 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 layout guidelines 4) the output capacitor(s) (cout) should be located as close to the load as possible, fast transient load cur- rents are supplied by cout only, and connections between cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) the sc1172/3 is best placed over a quiet ground plane area, avoid pulse currents in the cin, q1, q2 loop flowing in this area. pgndh and pgndl should be returned to the ground plane close to the package. the agnd pin should be connected to the ground side of (one of) the output capacitor(s). if this is not possible, the agnd pin may be connected to the ground path between the output capacitor(s) and the cin, q1, q2 loop. under no circum- stances should agnd be returned to a ground inside the cin, q1, q2 loop. 6) vcc for the sc1172/3 should be supplied from the 5v currents in various parts of the power section supply through a 10 w resistor, the vcc pin should be decoupled directly to agnd by a 0.1 m f ceramic capacitor, trace lengths should be as short as possible. 7) the current sense resistor and the divider across it should form as small a loop as possible, the traces run- ning back to cs+ and cs- on the sc1172/3 should run parallel and close to each other. the 0.1 m f capacitor should be mounted as close to the cs+ and cs- pins as possible. 8) ideally, the grounds for the two ldo sections should be returned to the ground side of (one of) the output capacitor(s). vout 5v + +
9 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 layout guidelines component selection switching section output capacitors - selection begins with the most critical component. because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. output capacitor esr is therefore one of the most important criteria. the maximum esr can be simply calculated from: step current transient i excursion voltage transient maximum v where i v r t t t t esr = = for example, to meet a 100mv transient limit with a 10a load step, the output capacitor esr must be less than 10m w . to meet this kind of esr level, there are three available capacitor technologies. y g o l o n h c e t . p a c h c a e . y t q . d q r l a t o t c ( m ) f r s e m ( w ) c ( m ) f r s e m ( w ) m u l a t n a t r s e w o l0 3 30 660 0 0 20 1 n o c - s o0 3 35 230 9 93 . 8 m u n i m u l a r s e w o l0 0 5 14 450 0 5 73 . 8 the choice of which to use is simply a cost/performance issue, with low esr aluminum being the cheapest, but taking up the most space. inductor - having decided on a suitable type and value of output capacitor, the maximum allowable value of in- ductor can be calculated. too large an inductor will pro- duce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the esr excursion calculated above. the maximum inductor value may be calculated from: () o in o a a t esr v v or v of lesser the is v where v i c r l - the calculated maximum inductor value assumes 100% and 0% duty cycle, so some allowance must be made. choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the esr at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. we must also be concerned with ripple current in the out- put inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor esr. ripple current can be calculated from: osc in l f l 4 v i ripple = ripple current allowance will define the minimum permit- ted inductor value. power fets - the fets are chosen based on several criteria with probably the most important being power dis- sipation and power handling capability. top fet - the power dissipation in the top fet is a combi- nation of conduction losses, switching losses and bottom fet body diode recovery losses. a) conduction losses are simply calculated as: in o ) on ( ds 2 o cond v v c y cle dut y = where r i p ? d d = b) switching losses can be estimated by assuming a switch- ing time, if we assume 100ns then: 2 in o sw 10 v i p - = or more generally, 4 f ) t t ( v i p osc f r in o sw + = c) body diode recovery losses are more difficult to esti- mate, but to a first approximation, it is reasonable to as- sume that the stored charge on the bottom fet body di- ode will be moved through the top fet as it starts to turn on. the resulting power dissipation in the top fet will be: osc in rr rr f v q p = to a first order approximation, it is convenient to only con-
10 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 layout guidelines sider conduction losses to determine fet suitability. for a 5v in; 2.8v out at 14.2a requirement, typical fet losses would be: using 1.5x room temp r ds(on) to allow for temperature rise. e p y t t e fr ) n o ( s d m ( w )p d ) w (e g a k c a p 5 2 0 4 3 l r i5 19 6 . 1d 2 k a p 3 0 2 2 l r i5 . 0 19 1 . 1d 2 k a p 0 1 4 4 i s0 26 2 . 28 - 0 s bottom fet - bottom fet losses are almost entirely due to conduction. the body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the fet turns on and off, there is very little voltage across it, resulting in low switching losses. conduction losses for the fet can be determined by: ) 1 ( r i p ) on ( ds 2 o cond d - = for the example above: e p y t t e fr ) n o ( s d m ( w )p d ) w (e g a k c a p 5 2 0 4 3 l r i5 13 3 . 1d 2 k a p 3 0 2 2 l r i5 . 0 13 9 . 0d 2 k a p 0 1 4 4 i s0 27 7 . 18 - 0 s each of the package types has a characteristic thermal impedance, for the to-220 package, thermal impedance is mostly determined by the heatsink used. for the sur- face mount packages on double sided fr4, 2 oz printed circuit board material, thermal impedances of 40 o c/w for the d 2 pak and 80 o c/w for the so-8 are readily achiev- able. the corresponding temperature rise is detailed be- low: ( e s i r e r u t a r e p m e t o ) c e p y t t e ft e f p o tt e f m o t t o b 5 2 0 4 3 l r i6 . 7 62 . 3 5 3 0 2 2 l r i6 . 7 42 . 7 3 0 1 4 4 i s8 . 0 8 16 . 1 4 1 it is apparent that single so-8 si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. input capacitors - since the rms ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. also, during fast load transients, there may be restrictions on input di/dt. these restrictions require useable energy storage within the converter circuitry, either as extra out- put capacitance or, more usually, additional input capaci- tors. choosing low esr input capacitors will help maximize ripple rating for a given size.
11 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 typical characteristics typical efficiency at vo=2.8v 70% 75% 80% 85% 90% 95% 0246810121416 io (am ps) efficiency 2.8v std 2.8v sync 2.8v sync lo rds typical efficiency at vo=2.0v 70% 75% 80% 85% 90% 95% 0246810121416 io (amps) efficiency 2.0v std 2.0v sync 2.0v sync lo rds typical efficiency at vo=2.5v 70% 75% 80% 85% 90% 95% 0 2 4 6 8 10 12 14 16 io (am ps) efficiency 2.5v std 2.5v sync 2.5v sync lo rds typical efficiency at vo=3.5v 70% 75% 80% 85% 90% 95% 0 2 4 6 8 10 12 14 16 io (am ps) efficiency 3.5v std 3.5v sync 3.5v sync lo rds transient response vo=2.8v, io=300ma to 10a typical ripple, vo=2.8v, io=10a
12 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 typical application circuit vid3 schematic is for sc1172 (fixed ldo output voltage) for sc1173, ldo output voltage setting is by resistor. see the layout diagram and "setting ldo output voltage" section for details + c15 330uf + c7 1500uf r6 2r2 j13 vid2 + c6 1500uf vid0 + c26 4.7uf vid 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 vout no cpu 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 vcc_core pwrgood r3 empty en vid1 + c3 1500uf 12v j23 c4 0.1uf j1 j18 scop 1.5v j17 1 2 3 4 j26 5v j15 q1 irlr3103n + c9 1500uf u4 sc1172cs 1 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 13 12 14 24 2 23 3 4 agnd vcc ovp pwrgood cs- cs+ pgndh dh bsth en vo sense vid4 vid3 vid2 vid1 vid0 dl pgndl bstl gate nc ldov nc ldos + c12 330uf + c8 1500uf + c14 330uf r4 1.00k vid4 3.3v vout 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 j22 + c11 330uf c1 0.1uf l1 1.9uh q3 irlr3103n r8 5mohm j12 j16 1 2 3 4 + c2 1500uf r1 10 c10 0.1uf vid 43210 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 r9 2r2 r11 0 j21 c5 0.1uf q5 irlr024n s1 1 2 3 4 5 6 r5 2.32k
13 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 materials list m e t i. y t qf e re u l a vs e t o n 14 0 1 c , 5 c , 4 c , 1 cf u 1 . 0 26 9 c , 8 c , 7 c , 6 c , 3 c , 2 cf u 0 0 5 1r s e w o l . v i u q e r o x g - v m o y n a s 34 5 1 c , 4 1 c , 2 1 c , 1 1 cf u 0 3 3 41 6 2 cf u 7 . 4 51 1 lh u 9 . 1 s l a t e m o r c i m n o g w a 6 1 s n r u t 6 e r o c d 2 5 - 0 5 t 62 3 q , 1 qn 3 0 1 3 r l r i 71 5 qn 4 2 0 r l r i 81 1 r0 1 91 3 ry t p m e 0 11 4 rk 0 0 . 1 1 11 5 rk 2 3 . 2 2 12 9 r , 6 r2 r 2 3 11 8 rm h o m 5s e i r e s 1 - r a o c r i 4 11 1 1 r0 5 11 1 s6 - p i d w s 6 11 4 us c 2 7 1 1 c s
14 ? 2001 semtech corp. www.semtech.com power management sc1172 & sc1173 semtech corporation power management products division 652 mitchell rd., newbury park, ca 91320 phone: (805)498-2111 fax (805)498-3804 outline drawing contact information

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