mk3732-15 low phase noise vcxo+multiplier preliminary information mds 3732-15 a 1 revision 082800 printed 11/16/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?5126?408) 295-9800tel?www.icst.com block diagram description features the mk3732-15 is a low cost, low phase noise, high performance vcxo and pll clock synthesizer designed to replace expensive discrete vcxos and oscillators. the on-chip voltage controlled crystal oscillator (vcxo) accepts a 0 to 3.3 v input voltage to cause the output clocks to vary by ?00 ppm. using ics? patented vcxo and analog phase-locked loop (pll) techniques, the device uses an inexpensive 10 mhz to 18 mhz pullable crystal input to produce one or two output clocks. to achieve lowest phase noise, the refclk can be turned off. ics manufactures the largest variety of clocks for set-top boxes and communications. consult ics to eliminate vcxos, crystals, oscillators and buffers from your board. ?packaged in 16 pin tssop ?ideal for adi? adsl chipsets ?for mpeg 2 decoders ?can replace a vcxo and crystal/oscillator ?uses an inexpensive pullable crystal ?on-chip patented vcxo with pull range of 200 ppm (?00 ppm) minimum ?vcxo tuning voltage of 0 to 3.3 v ?zero ppm synthesis error in all clocks ?full cmos output swings with 12 ma output drive capability at ttl levels ?advanced, low power, sub-micron cmos process ?3.3v only operating voltage voltage controlled crystal oscillator pll/clock synthesis circuitry 10-18 mhz pullable crystal x1 x2 vin clk output buffer oe (both outputs) s1, s0 2 refclk output buffer refen
mk3732-15 low phase noise vcxo+multiplier preliminary information mds 3732-15 a 2 revision 082800 printed 11/16/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?5126?408) 295-9800tel?www.icst.com pin descriptions key: i = input with internal pull-up resistor; ti = tri-level input; o = output; p = power supply connection; vi = analog voltage input; xi, xo = crystal pins. pin assignment number name type description 1 x1 xi crystal connection. connect to a pullable crystal of 10-18 mhz. 2, 3, 11 vdd p vdd. connect to +3.3v. 4 vin vi voltage input to vcxo. zero to 3.3 v signal which controls the frequency of the vcxo. 5, 6, 13 gnd p connect to ground. 7 s2 i select input #2. selects clk output per table above. 8 oe i output enable. tri-states outputs when low. 9 s0 ti select input #0. selects clk output per table above. 10 refen i reference enable (active low). when pin is connected to ground, the refclk is running. 12 clk o vcxo clock output per table above. 14 refclk o buffered crystal vcxo clock 15 s1 i select input #1. selects clk output per table above. 16 x2 xo crystal connection. connect to a pullable crystal of 10-18 mhz. mk3732-15 external components the mk3732-15 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01? should be connected between vdd and gnd on pins 3 and 5, and vdd and gnd on pins 11 and 13, as close to the mk3732-15 as possible. a series termination resistor of 33 w may be used for each clock output. the input crystal must be connected as close to the chip as possible. the input crystal should be a fundamental mode, parallel resonant, pullable, at cut. a crystal with 14 pf load capacitance is recommended. consult ics/microclock for recommended suppliers. important - consult the application note man05 for layout guidelines. 16 15 14 13 16 pin (173 mil) tssop 12 11 10 9 1 2 3 4 5 6 7 8 vdd gnd x2 x1 vin oe gnd s2 gnd clk refen s0 vdd vdd s1 refclk s2 s1 s0 clk 0 0 0 ref/2 0 0 m x0.666 0 0 1 x2.6666 0 1 0 x4 0 1 m x1.5 0 1 1 x1.3333 1 0 0 test 1 0 m x4 1 0 1 x2 1 1 0 x3 1 1 m x5 1 1 1 x6 0 = connect directly to gnd, m = leave unconnected (floating), 1 = connect directly to vdd. clock select table for analog devices? adsl chipset, use a 17.664 mhz crystal, and the 101 setting for a 35.328 mhz output clock. pin 10 should be grounded to get the 17.664 mhz clock output on pin 14.
mk3732-15 low phase noise vcxo+multiplier preliminary information mds 3732-15 a 3 revision 082800 printed 11/16/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?5126?408) 295-9800tel?www.icst.com parameter conditions minimum typical maximum units absolute maximum ratings (note 1) absolute maximum ratings (note 1) supply voltage, vdd referenced to gnd 7 v inputs and clock outputs referenced to gnd -0.5 vdd+0.5 v ambient operating temperature 0 70 ? soldering temperature max of 10 seconds 260 ? storage temperature -65 150 ? dc characteristics (vdd = 3.3v unless noted) dc characteristics (vdd = 3.3v unless noted) core operating voltage, vdd 3.15 3.30 3.45 v input high voltage, vih, x1 pin only 3.5 2.5 v input low voltage, vil, x1 pin only 2.5 1.5 v input high voltage, vih, binary input oe 2 v input low voltage, vil, binary input oe 0.8 v input high voltage, vih, trinary inputs s1, s0 vdd-0.5 v input low voltage, vil, trinary inputs s1, s0 0.5 v output high voltage, voh ioh=-12ma 2.4 v output low voltage, vol iol=12ma 0.4 v output high voltage, voh, cmos level ioh=-8ma vdd-0.4 v operating supply current, idd no load 9 ma short circuit current each output ?0 ma input capacitance s1, s0, oe 5 pf frequency synthesis error all clocks 0 ppm vin, vcxo control voltage 0 3.3 v ac characteristics (vdd = 3.3v unless noted) ac characteristics (vdd = 3.3v unless noted) input crystal frequency 10 18 mhz output clock rise time 0.8 to 2.0v 1.5 ns output clock fall time 2.0 to 0.8v 1.5 ns output clock duty cycle at vdd/2 40 60 % maximum absolute jitter, short term ?50 ps phase noise, relative to carrier, note 3 10 khz offset -115 dbc/hz output pullability, note 2 0v vin 3.3v ?00 ppm electrical specifications notes: 1. stresses beyond those listed under absolute maximum ratings could cause permanent damage to the device. prolonged exposure to levels above the operating limits but below the absolute maximums may affect device reliability. 2. with an ics/microclock approved pullable crystal. 3. to achieve this level of phase noise (lowest), refclk must be turned off by connecting refen to vdd.
mk3732-15 low phase noise vcxo+multiplier preliminary information mds 3732-15 a 4 revision 082800 printed 11/16/00 integrated circuit systems, inc. ?525 race street ?san jose ?ca ?5126?408) 295-9800tel?www.icst.com while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorporated (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. ordering information part/order number shipping packaging marking (both) package temperature mk3732-15g tubes ics (top line) 16 pin tssop 0-70 ? MK3732-15GTR tape and reel 3732-15g (2nd line) 16 pin tssop 0-70 ? revision history: version revision comments - 12139 original a 8280 preliminary 16 pin tssop millimeters millimeters symbol min max a - 1.20 a1 0.05 0.15 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 bsc 6.40 bsc e1 4.30 4.50 e 0.65 bsc 0.65 bsc l 0.45 0.75 package outline and package dimensions ( for current dimensional specifications, see jedec publication no. 95.) b d e1 e e a1 c a l index area 1 2
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