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single-chip 8-bit cmos microcomputer description the 7542 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7542 group has a serial i/o, 8-bit timers, a 16-bit timer, and an a-d converter, and is useful for control of home electric appli- ances and office automation equipment. features basic machine-language instructions ...................................... 71 the minimum instruction execution time .. 0.25 s (target spec.) (at 8 mhz oscillation frequency, double-speed mode for the shortest instruction) memory size rom ............................................ 8 k to 32 k bytes ram ........................................... 384 to 1024 bytes programmable i/o ports ....................... 29 (25 in 32-pin version) interrupts ................................................. 18 sources, 16 vectors timers ............................................................................. 8-bit ? 2 ...................................................................................... 16-bit ? 2 output compare ............................................................ 4-channel input capture ................................................................ 2-channel serial i/o ...................... 8-bit ? 2 (uart or clock-synchronized) a-d converter ............................................... 10-bit ? 8 channels .................................................... (6 channels for 32-pin version) clock generating circuit ............................................. built-in type (low-power dissipation by a ring oscillator) (connected to external ceramic resonator or quartz-crystal oscillator permitting rc oscillation) watchdog timer ............................................................ 16-bit ? 1 power source voltage x in oscillation frequency at ceramic oscillation, in double-speed mode at 8 mhz ................................................................................ tbd x in oscillation frequency at ceramic oscillation, in high-speed mode at 8 mhz .................................................................... 4.0 to 5.5 v at 4 mhz .................................................................... 2.4 to 5.5 v at 2 mhz .................................................................... 2.2 to 5.5 v x in oscillation frequency at rc oscillation in high-speed mode or middle-speed mode at 4 mhz .................................................................... 4.0 to 5.5 v at 2 mhz .................................................................... 2.4 to 5.5 v at 1 mhz .................................................................... 2.2 to 5.5 v power dissipation .................................................................. tbd operating temperature range ................................... ?0 to 85 ? (?0 to 85 ? for extended operating temperature version) (?0 to 125 ? for extended operating temperature 125 ? ver- sion ( note )) note: in this version, the operating temperature range and total time are limited as follows; 55 ? to 85 ?: within total 6000 hours, 85 ? to 125 ?: within total 1000 hours. mitsubishi microcomputers 7542 group application office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. preliminar y notice: this is not a final specification. some parametric limits are subject to change.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 2 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 2 pin configuration (36p2r-a type) pin configuration (top view) fig. 1 pin configuration (32p6u-a type) package type: 32p6u-a p0 7 (led 07 )/s rdy2 p1 0 /r x d 1 /cap 0 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 p3 0 (led 10 )/cap 1 v ss x out x in 9 10 11 12 13 14 15 16 8 7 6 5 3 14 v cc cnv ss reset p2 2 /an 2 p0 5 (led 05 )/txd 2 20 17 18 19 21 24 p0 2 (led 02 )/cmp 1 p0 4 (led 04 )/rxd 2 p0 3 (led 03 )/tx out p0 6 (led 06 )/sclk 2 23 22 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 m37542m4-xxxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref 2 packa g e t yp e: 36p2r-a 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 cnv ss x out x in v ss p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 vcc v ref p0 5 (led 05 )/txd 2 p1 0 /r x d 1 /cap 0 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 11 )/cmp 2 p3 6 (led 16 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 (led 06 )/sclk 2 p0 7 (led 07 )/s rdy2 reset m37542m4-xxxfp p1 4 /cntr 0 p3 5 (led 15 ) p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 7 (led 17 )/int 0 p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 3 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 4 pin configuration (42s1m type) fig. 3 pin configuration (32p4b-a type) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 /cap 0 p0 7 (led 07 )/s rdy2 p0 6 (led 06 )/sclk 2 p0 5 (led 05 )/txd 2 p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 p2 5 /an 5 v ref reset p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 m37542m4-xxxsp 32 14 15 16 p3 4 (led 14 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 package type: 32p4b p0 3 (led 03 )/tx out p0 2 (led 02 )/cmp 1 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 outline 42s1m 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 32 27 29 28 19 20 21 42 41 40 39 37 38 cnv ss x out x in v ss p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 vcc v ref p0 5 (led 05 )/txd 2 p1 2 /s clk1 p2 5 /an 5 p2 6 /an 6 p1 3 /s rdy1 p1 4 /cntr 0 nc p2 2 /an 2 nc p2 1 /an 1 p2 0 /an 0 p3 1 (led 11 )/cmp 2 p3 6 (led 16 )/int 1 p2 3 /an 3 p2 4 /an 4 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 reset m37542rss nc p3 5 (led 15 ) p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 nc p1 0 /r x d 1 /cap 0 p1 1 /t x d 1 nc nc p2 7 /an 7 p3 7 (led 17 )/int 0 p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 4 preliminar y notice: this is not a final specification. some parametric limits are subject to change. functional block fig. 5 functional block diagram (32p6u package) functional block diagram (package: 32p6u) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 11 reset 6 v cc 8 7 cnv ss p1(5) 30 28 26 29 27 32 31 p2(6) p3(6) 12 15 13 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 9 10 4 2 3 1 a-d converter (10) v ref watchdog timer reset 0 14 int 0 16 17 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 25 23 21 19 24 22 20 18 timer 1 (8) prescaler 1 (8) timer a (16) input capture output compare int 1
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 5 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 6 functional block diagram (36p2r package) functional block diagram (package: 36p2r) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 18 reset 13 v cc 15 14 cnv ss p1(5) 31 35 2 36 76 p2(8) p3(8) 21 24 22 12 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 16 17 11 9 10 8 a-d converter (10) v ref watchdog timer reset 0 23 int 0 25 26 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 34 32 30 28 33 31 29 27 timer 1 (8) prescaler 1 (8) timer a (16) int 1 19 20 5 4 input capture output compare
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 6 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 7 functional block diagram (32p4b package) functional block diagram (package: 32p4b) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 16 reset 11 v cc 13 12 cnv ss p1(5) 31 31 2 32 p2(6) p3(6) 17 20 18 10 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 14 15 a-d converter (10) v ref watchdog timer reset 0 19 int 0 21 22 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 25 23 24 timer 1 (8) prescaler 1 (8) timer a (16) int 1 28 26 27 30 29 4 75 6 8 9 input capture output compare
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 7 preliminar y notice: this is not a final specification. some parametric limits are subject to change. pin description table 1 pin description function apply voltage of 2.2 to 5.5 v to vcc, and 0 v to vss. reference voltage input pin for a-d converter. chip operating mode control pin, which is always connected to vss. reset input pin for active l input and output pins for main clock generating circuit. connect a ceramic resonator or quartz crystal oscillator between the x in and x out pins. for using rc oscillator, short between the x in and x out pins, and connect the capacitor and resistor. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. when the ring oscillator is selected as the main clock, connect x in pin to v cc and leave x out open. function expect a port function name power source (note 1) analog refer- ence voltage cnvss reset input clock input i/o port p0 i/o port p1 i/o port p2 (note 2) i/o port p3 (note 3) pin vcc, vss v ref cnvss reset x in p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out p0 4 (led 04 )/rxd 2 p0 5 (led 05 )/txd 2 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 p1 0 /rxd 1 /cap 0 p1 1 /txd 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 p2 7 /an 7 p3 0 (led 10 )/cap 1 p3 1 (led 11 )/cmp 2 p3 2 (led 12 )/cmp 3 p3 3 (led 13 )/int 1 p3 4 (led 14 ) p3 5 (led 15 ) p3 6 (led 16 )/int 1 p3 7 (led 17 )/int 0 notes 1: v cc = 2.4 to 5.5 v for the extended operating temperature version and the extended operating temperature 125 c version. 2: p2 6 /an 6 and p2 7 /an 7 do not exist for the 32-pin version, so that port p2 is a 6-bit i/o port. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version, so that port p3 is a 6-bit i/o port. capture function pin compare function pin timer x function pin serial i/o2 function pin serial i/o1 function pin capture function pin serial i/o1 function pin timer x function pin input pins for a-d converter capture function pin compare function pin interrupt input pin interrupt input pin 8-bit i/o port. i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level cmos 3-state output structure whether a built-in pull-up resistor is to be used or not can be determined by program. high drive capacity for led drive port can be selected by program. 5-bit i/o port i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level cmos 3-state output structure cmos/ttl level can be switched for p1 0 , p1 2 and p1 3 8-bit i/o port having almost the same function as p0 cmos compatible input level cmos 3-state output structure 8-bit i/o port i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level (cmos/ttl level can be switched for p3 6 and p3 7 ). cmos 3-state output structure whether a built-in pull-up resistor is to be used or not can be determined by program. high drive capacity for led drive port can be selected by program. x out clock output key-input (key-on wake up interrupt input) pin
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 8 preliminar y notice: this is not a final specification. some parametric limits are subject to change. group expansion mitsubishi plans to expand the 7542 group as follow: memory type support for mask rom version, flash memory version, and emu- lator mcu . memory size flash memory size ......................................................... 32 k bytes mask rom size ................................................... 8 k to 16 k bytes ram size ............................................................ 384 to 1024 bytes package 32p4b .................................................. 32-pin plastic molded sdip 32p6u-a ...................... 0.8 mm-pitch 32-pin plastic molded lqfp 36p2r-a ...................... 0.8 mm-pitch 36-pin plastic molded ssop 42s1m .................................... 42-pin shrink ceramic piggy back fig. 8 memory expansion plan 384 32k rom size (bytes) ram size (bytes) 512 1024 16k 0 m37542f8 m37542m4 m37542m4t note: products under development the development schedule and s p ecification ma y be revised without notice. 8k m37542f8t m37542f8v m37542m2t m37542m2 ** : under development m37542m2v m37542m4v ** ** ** ** ** ** ** ** **
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 9 preliminar y notice: this is not a final specification. some parametric limits are subject to change. currently supported products are listed below. table 2 list of supported products product rom size (bytes) rom size for user () 8192 (8062) 16384 (16254) 32768 (32638) ram size (bytes) 384 512 1024 1024 package 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 42s1m remarks mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) flash memory version flash memory version flash memory version (extended operating temperature version) flash memory version (extended operating temperature 125 c version) flash memory version flash memory version (extended operating temperature version) flash memory version (extended operating temperature 125 c version) emulator mcu m37542m2-xxxsp m37542m2-xxxfp m37542m2t-xxxfp M37542M2V-XXXFP m37542m2-xxxgp m37542m2t-xxxgp m37542m2v-xxxgp m37542m4-xxxsp m37542m4-xxxfp m37542m4t-xxxfp m37542m4v-xxxfp m37542m4-xxxgp m37542m4t-xxxgp m37542m4v-xxxgp m37542f8sp m37542f8fp m37542f8tfp m37542f8vfp m37542f8gp m37542f8tgp m37542f8vgp m37542rss
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 10 preliminar y notice: this is not a final specification. some parametric limits are subject to change. b7 b0 x b7 b0 s b7 b0 y b7 b0 pc l processor status register (ps) carry flag b7 b0 b7 b0 a b15 pc h zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag program counter stack pointer index register y index register x accumulator c z i d b t v n functional description central processing unit (cpu) the mcu uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine-language instructions or the series 740 user s manual for details on each instruction set. machine-resident 740 family instructions are as follows: 1. the fst and slw instructions cannot be used. 2. the mul and div instructions can be used. 3. the wit instruction can be used. 4. the stp instruction can be used. this instruction cannot be used while cpu operates by a ring os- cillator. accumulator (a) the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. index register x (x), index register y (y) both index register x and index register y are 8-bit registers. in the index addressing modes, the value of the operand is added to the contents of register x or register y and specifies the real address. when the t flag in the processor status register is set to 1 , the value contained in index register x becomes the address for the second operand. stack pointer (s) the stack pointer is an 8-bit register used during subroutine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. the lower eight bits of the stack address are determined by the contents of the stack pointer. the upper eight bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , then the ram in the zero page is used as the stack area. if the stack page selection bit is 1 , then ram in page 1 is used as the stack area. the stack page selection bit is located in the sfr area in the zero page. note that the initial value of the stack page selection bit varies with each microcomputer type. also some microcom- puter types have no stack page selection bit and the upper eight bits of the stack address are fixed. the operations of pushing reg- ister contents onto the stack and popping them from the stack are shown in fig. 9. program counter (pc) the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 9 740 family cpu register structure
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 11 preliminar y notice: this is not a final specification. some parametric limits are subject to change. execute jsr on-going routine m (s) (pc h ) (s) (s 1) m (s) (pc l ) execute rts (pc l ) m (s) (s) (s 1) (s) (s + 1) (s) (s + 1) (pc h ) m (s) subroutine restore return address store return address on stack m (s) (ps) execute rti (ps) m (s) (s) (s 1) (s) (s + 1) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s 1) m (s) (pc l ) (s) (s 1) (pc l ) m (s) (s) (s + 1) (s) (s + 1) (pc h ) m (s) restore return address i flag 0 to 1 fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is 1 interrupt disable flag is 0 table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 10 register push and pop at interrupt generation and subroutine call
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 12 preliminar y notice: this is not a final specification. some parametric limits are subject to change. processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to 1 , but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . when an interrupt occurs, this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are ex- ecuted in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. (5) break flag (b) the b flag is used to indicate that the current interrupt was gener- ated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is 0 , arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. when the t flag is 1 , direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal ad- dressing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location oper- ated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 13 preliminar y notice: this is not a final specification. some parametric limits are subject to change. [cpu mode register] cpum the cpu mode register contains the stack page selection bit, etc.. this register is allocated at address 003b 16 . switching method of cpu mode register switch the cpu mode register (cpum) at the head of program af- ter releasing reset in the following method. fig. 12 switching method of cpu mode register fig. 11 structure of cpu mode register after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with a built-in ring oscillator an initial value is set as a ceramic oscillation mode. when it is switched to an rc oscillation, its oscillation starts. select 1/1, 1/2, 1/8 or ring oscillator. wait by ring oscillator operation until establishment of oscillator clock when using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. when using an rc oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement). oscillation mode selection bit (note 1) 0 : ceramic oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( ) = f(x in )/2 (high-speed mode) 0 1 : f( ) = f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f( ) = f(x in ) (double-speed mode)(note 2) ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37542rss .) do not use these when an rc oscillation is selected.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 14 preliminar y notice: this is not a final specification. some parametric limits are subject to change. memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for a stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 13 memory map diagram 0100 16 0 0 0 0 1 6 0 0 4 0 1 6 0440 1 6 ff00 16 ffdc 1 6 fffe 16 ffff 16 384 512 1024 x x x x 1 6 01bf 16 023f 16 043f 16 8 1 9 2 1 6 3 8 4 3 2 7 6 8 e000 16 c000 16 8000 16 e 0 8 0 1 6 c 0 8 0 1 6 8 0 8 0 1 6 yyyy 16 zzzz 16 ram rom r e s e r v e d a r e a sfr area not used interrupt vector are a r o m a r e a reserved rom area (128 bytes) z e r o p a g e special page r a m a r e a ram capacity (bytes) address xxxx 16 r o m c a p a c i t y ( b y t e s ) address yyyy 16 r e s e r v e d r o m a r e a a d d r e s s z z z z 1 6
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 15 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 14 memory map of special function register (sfr) note : do not access to the sfr area including nothing. 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit 1 /receive 1 buffer register (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator 1 (brg1) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) a-d conversion register (low-order) (adl) prescaler 1 (pre1) timer 1 (t1) timer x mode register (txm) prescaler x (prex) timer x (tx) serial i/o2 control register (sio2con) uart2 control register (uart2con) a-d control register (adcon) a-d conversion register (high-order) (adh) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a, b mode register (tabm) capture/compare port register (ccpr) timer source selection register (tmsr) capture mode register (capm) compare output mode register (cmom) capture/compare status register (ccsr) compare interrupt source set register (cisr) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) ring oscillation division ratio selection register (rodr) baud rate generator 2 (brg2) timer a (low-order) (tal) timer a (high-order) (tah) timer b (low-order) (tbl) timer b (high-order) (tbh) transmit 2 / receive 2 buffer register (tb2/rb2) serial i/o2 status register (sio2sts) port p0p3 drive capacity control register (dccr) compare register re-load register (cmpr) capture software trigger register (cstr) capture/compare register r/w pointer (ccrp) compare register (high-order) (cmph) compare register (low-order) (cmpl) capture register 1 (high-order) (cap1h) capture register 1 (low-order) (cap1l) capture register 0 (high-order) (cap0h) capture register 0 (low-order) (cap0l) interrupt source set register (intset) interrupt source discrimination register (intdis) reserved reserved reserved
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 16 preliminar y notice: this is not a final specification. some parametric limits are subject to change. i/o ports [direction registers] pid the i/o ports have direction registers which determine the input/ output direction of each pin. each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. when 1 is set to the bit corresponding to a pin, this pin becomes an output port. when 0 is set to the bit, the pin becomes an in- put port. when data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. pins set to input are float- ing, and permit reading pin values. if a pin set to input is written to, only the port latch is written to and the pin remains floating. note: p2 6 /an 6 , p2 7 /an 7 , p3 5 and p3 6 do not exist for the 32-pin version. accordingly, the following settings are required; select p3 3 for the int 1 function. set direction registers of ports p2 6 and p2 7 to output. set direction registers of ports p3 5 and p3 6 to output. [port p0p3 drive capacity control register] dccr by setting the port p0p3 drive capacity control register (address 0015 16 ), the drive capacity of the n-channel output transistor for the port p0 and port p3 can be selected. [pull-up control register] pull by setting the pull-up control register (address 0016 16 ), ports p0 and p3 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull-up control. [port p1p3 control register] p1p3c by setting the port p1p3 control register (address 0017 16 ), a cmos input level or a ttl input level can be selected for ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 by program. fig. 17 structure of port p1p3 control register fig. 16 structure of pull-up control register port p1p3 control register (p1p3c: address 0017 16 , initial value: 00 16 ) b7 b0 p3 7 /int 0 input level selection bit 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit 0 : cmos level 1 : ttl level p1 0 ,p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level not used note: keep setting the p3 6 /int 1 input level selection bit to 0 (initial value) for 32-pin version. p u l l - u p c o n t r o l r e g i s t e r ( p u l l : a d d r e s s 0 0 1 6 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) p 0 0 pu ll -up contro l bi t p0 1 , p0 2 pull-up control bit p0 3 p0 7 pull-up control bit p3 0 pull-up control bit p3 1 , p3 2 pull-up control bit p3 3 pull-up control bit p3 4 , p3 5 pull-up control bit p3 6 , p3 7 pull-up control bit b 7 b 0 0 : p u l l - u p o f f 1 : p u l l - u p o n n o t e : p i n s s e t t o o u t p u t p o r t s a r e d i s c o n n e c t e d f r o m p u l l - u p c o n t r o l . p o r t p 0 p 3 d r i v e c a p a c i t y c o n t r o l r e g i s t e r ( d c c r : a d d r e s s 0 0 1 5 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) p o r t p 0 0 d r i v e c a p a c i t y b i t p o r t s p 0 1 , p 0 2 d r i v e c a p a c i t y b i t p o r t s p 0 3 p 0 7 d r i v e c a p a c i t y b i t p o r t p 3 0 d r i v e c a p a c i t y b i t p o r t s p 3 1, p 3 2 d r i v e c a p a c i t y b i t p o r t p 3 3 d r i v e c a p a c i t y b i t p o r t s p 3 4 , p 3 5 d r i v e c a p a c i t y b i t p o r t s p 3 6 , p 3 7 d r i v e c a p a c i t y b i t b 7 b 0 0 : l o w 1 : h i g h n o t e : n u m b e r o f l e d d r i v e p o r t ( d r i v e c a p a c i t y i s h i g h ) i s 8 - p o r t . fig. 15 structure of port p0p3 drive capacity control register
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 17 preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 5 i/o port function table pin p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out p0 4 (led 04 )/rxd 2 p0 5 (led 05 )/txd 2 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 p1 0 /rxd 1 /cap 0 p1 1 /txd 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 ?2 7 /an 7 p3 0 (led 10 )/cap 1 p3 1 (led 11 )/cmp 2 p3 2 (led 12 )/cmp 3 p3 3 (led 13 )/int 1 p3 4 (led 14 ) p3 5 (led 15 ) p3 6 (led 16 )/int 1 p3 7 (led 17 )/int 0 i/o format ?mos compatible input level ( note 1 ) ?mos 3-state output non-port function ?capture function input ?key input interrupt ?compare function output ?key input interrupt ?timer x function output ?key input interrupt ?serial i/o2 function input/output ?key input interrupt ?serial i/o1 function input ?capture function input ?serial i/o1 function input/output ?timer x function input/output ?external interrupt input ?a-d conversion input ?capture function input ?compare function output ?external interrupt input ?external interrupt input sfrs related each pin capture/compare port register interrupt edge selection register pull-up control register port p0p3 drive capacity control register capture/compare port register pull-up control register port p0p3 drive capacity control register timer x mode register pull-up control register port p0p3 drive capacity control register serial i/o2 control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register serial i/o2 control register pull-up control register port p0p3 drive capacity control register serial i/o2 control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register serial i/o2 control register pull-up control register port p0p3 drive capacity control register serial i/o1 control register capture/compare port register port p1p3 control register serial i/o1 control register serial i/o1 control register port p1p3 control register serial i/o1 control register port p1p3 control register timer x mode register a-d control register capture/compare port register pull-up control register port p0p3 drive capacity control register capture/compare port register pull-up control register port p0p3 drive capacity control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register pull-up control register port p0p3 drive capacity control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register port p1p3 control register diagram no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) notes 1: ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 are cmos/ttl level. 2: p2 6/ an 6 and p2 7 /an 7 do not exist for the 32-pin version. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version. name i/o port p0 i/o port p1 i/o port p2 ( note 2 ) i/o port p3 ( note 3 )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 18 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 18 block diagram of ports (1) (1) port p0 0 direction register data bus port latch pull-up control to key input interrupt generating circuit capture 0 input p0 0 key-on wakeup selection bit drive capacity control capture 0 input control (2) ports p0 1, p0 2 compare output direction register data bus port latch pull-up control to key input interrupt generating circuit compare output control drive capacity control (3) port p0 3 timer output direction register data bus port latch pull-up control to key input interrupt generating circuit p0 3 /t xout output valid drive capacity control (4) port p0 4 serial i/o2 input direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 enable bit drive capacity control p0 4 key-on wakeup selection bit receive enable bit (5) port p0 5 serial i/o2 output direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 enable bit drive capacity control transmit enable bit p0 5 /txd 2 p-channel output disable bit (6) port p0 6 serial i/o2 clock output direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 mode selection bit drive capacity control serial i/o2 enable bit serial i/o2 synchronous clock selection bit serial i/o2 clock input p0 6 key-on wakeup selection bit serial i/o2 enable bit (7) port p0 7 serial i/o2 ready output direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 mode selection bit serial i/o2 enable bit s rdy2 output enable bit drive capacity control
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 19 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 19 block diagram of ports (2) (8) port p1 0 direction register data bus port latch serial i/o1 enable bit receive enable bit serial i/o1 input capture 0 input control p1 0 , p1 2 , p1 3 input level selection bit capture 0 input p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. when the ttl level is selected , there is no h y steresis characteristics. (9) port p1 1 data bus port latch serial i/o1 output p1 1 /t x d 1 p-channel output disable bit direction register serial i/o1 enable bit transmit enable bit (10) port p1 2 serial i/o1 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit direction register data bus port latch serial i/o1 clock input p1 0 , p1 2 , p1 3 input level selection bit * (12) port p1 4 data bus serial i/o1 ready output port latch direction register cntr 0 interrupt input timer output p1 0 , p1 2 , p1 3 input level selection bit serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit data bus port latch direction register * (11) port p1 3 data bus port latch direction register a-d converter input analog input pin selection bit (13) ports p2 0 p2 7 * * pulse output mode
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 20 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 20 block diagram of ports (3) (14) port p3 0 direction register data bus port latch pull-up control capture 1 input drive capacity control capture 1 input control (15) ports p3 1, p3 2 compare output direction register data bus port latch pull-up control compare output control drive capacity control (16) port p3 3 direction register data bus port latch pull-up control int1 input control drive capacity control int1 input (17) ports p3 4, p3 5 direction register data bus port latch pull-up control drive capacity control (19) port p3 7 direction register data bus port latch pull-up control drive capacity control int0 input p3 input level selection bit * p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. * when the ttl level is selected , there is no h y steresis characteristics. (18) port p3 6 direction register data bus port latch pull-up control drive capacity control int1 input p3 input level selection bit * int1 input control
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 21 preliminar y notice: this is not a final specification. some parametric limits are subject to change. interrupts interrupts occur by 18 different sources : 6 external sources, 11 in- ternal sources and 1 software source. interrupt control all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. when the interrupt enable bit and the in- terrupt request bit are set to ??and the interrupt disable flag is set to ?? an interrupt is accepted. the interrupt request bit can be cleared by program but not be set. the interrupt enable bit can be set and cleared by program. the reset and brk instruction interrupt can never be disabled with any flag or bit. all interrupts except these are disabled when the interrupt disable flag is set. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. [interrupt source set register] intset when two interrupt sources are assigned to the same interrupt vector, the valid/invalid of each interrupt is set by this register. when both two interrupt sources are set to be valid, which inter- rupt request occurs is confirmed by the next interrupt source discrimination bit. [interrupt source discrimination register] intdis when two interrupt sources are assigned to the same interrupt vector, which interrupt source occurs is confirmed by this register. if an interrupt request of a key-on wakeup, uart1 bus collision detection, a-d conversion or timer 1 occurs, an interrupt discrimi- nation bit is set to ??regardless of valid/invalid state by the interrupt source set register. however, when the interrupt valid bit of an interrupt source set register is ??(invalid), the interrupt request bit of an interrupt con- trol register is not set to ?. moreover, since an interrupt discrimination bit is not automatically cleared to ??by interrupt, please clear it by program. an interrupt discrimination bit can be cleared to ??by program but not be set to ?. [interrupt edge selection register] intedge the valid edge of external interrupt int 0 and int 1 can be selected by the interrupt edge selection bit, respectively. for the external interrupt int 1 , the external input pin p3 3 /int 1 or p3 6 /int 1 can be selected by the int 1 input port selection bit. however, since there is no p3 6 /int 1 pin in the 32-pin version, se- lect p3 3 /int 1 pin. by the key-on wakeup selection bit, enable/ disable of a key-on wakeup of p0 0 , p0 4 , and p0 6 pins can be se- lected, respectively. notes on use (1) when setting the followings, the interrupt request bit may be set to ?? ?hen setting external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 002b 16 ) capture mode register (address 0020 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit, trigger mode bit). ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). (2) use a ldm instruction to clear an interrupt discrimination bit. ldm #$0n, $0bn set the following values to ? ?? an interrupt discrimination bit to clear ?? other interrupt discrimination bits ex.) when a key-on wakeup interrupt discrimination bit is cleared; ldm #00001110b and $0b.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 22 preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 6 interrupt vector address and priority vector addresses (note 1) high-order priority low-order interrupt request generating conditions remarks interrupt source fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 note 1: vector addressed contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: key-on wakeup interrupt and uart1 bus collision detection interrupt can be enabled by setting of interrupt source set register. the occurrence of these interrupts are discriminated by interrupt source discrimination register. 4: a-d conversion interrupt and timer 1 interrupt can be enabled by setting of interrupt source set register. the occurrence of t hese interrupts are dis- criminated by interrupt source discrimination register. non-maskable valid only when serial i/o1 is selected valid only when serial i/o1 is selected valid only when serial i/o2 is selected valid only when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling, when key-on wakeup interrupt is enabled) when uart1 bus collision detection interrupt is enabled. external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) compare interrupt source is selected. when a-d conversion interrupt is enabled. stp release timer underflow (when timer 1 interrupt is enabled) non-maskable software interrupt at reset input at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or when transmit buffer is empty at completion of serial i/o2 data receive at completion of serial i/o2 transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of uart1 bus collision detection at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of capture 0 input at detection of either rising or falling edge of capture 1 input at compare matched at timer x underflow at timer a underflow at timer b underflow at completion of a-d conversion at timer 1 underflow at brk instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 reset (note 2) serial i/o1 receive serial i/o1 transmit serial i/o2 receive serial i/o2 transmit int 0 int 1 key-on wake-up/ uart1 bus collision detection (note 3) cntr 0 capture 0 capture 1 compare timer x timer a timer b a-d conversion/ timer 1 (note 4) brk instruction
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 23 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 21 interrupt control interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset timer 1 interrupt request timer 1 interrupt valid bit a-d conversion interrupt request a-d conversion interrupt valid bit a-d conversion interrupt discrimination bit timer 1 interrupt discrimination bit a-d conversion/ timer 1 interrupt request bit uart1 bus collision detection interrupt request uart1 bus collision detection interrupt valid bit key-on wakeup interrupt request key-on wakeup interrupt valid bit key-on wakeup interrupt discrimination bit uart1 bus collision detection interrupt discrimination bit key-on wakeup/ uart1 bus collision detection interrupt request bit note: for key-on wakeup, uart1 bus collision detection, a-d conversion and timer 1 interrupt, even if interrupt valid bit (000a 16 ) is set 0: invalid , interrupt discrimination bit (000b 16 ) is set to 1: interrupt occurs when corresponding interrupt request occurs. but corresponding interrupt request bit (003c 16 , 003d 16 ) is not set to 1 .
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 24 preliminar y notice: this is not a final specification. some parametric limits are subject to change. b7 b0 i n t e r r u p t c o n t r o l r e g i s t e r 1 s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 t r a n s m i t i n t e r r u p t e n a b l e b i t i n t 0 i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t k e y - o n w a k e u p / u a r t 1 b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t e n a b l e b i t c n t r 0 i n t e r r u p t e n a b l e b i t 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b7 b0 interrupt control register 2 capture 0 interrupt enable bit capture 1 interrupt enable bit compare interrupt enable bit timer x interrupt enable bit timer a interrupt enable bit timer b interrupt enable bit a-d conversion/timer 1 interrupt enable bit not used (returns ??when read) (do not write ??to this bit) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d (icon2 : address 003f 16 , initial value : 00 16 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b7 b0 c a p t u r e 0 i n t e r r u p t r e q u e s t b i t c a p t u r e 1 i n t e r r u p t r e q u e s t b i t c o m p a r e i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r a i n t e r r u p t r e q u e s t b i t t i m e r b i n t e r r u p t r e q u e s t b i t a - d c o n v e r s i o n / t i m e r 1 i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) i n t e r r u p t r e q u e s t r e g i s t e r 1 s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 t r a n s m i t i n t e r r u p t r e q u e s t b i t i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t k e y - o n w a k e u p / u a r t 1 b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t r e q u e s t b i t c n t r 0 i n t e r r u p t r e q u e s t b i t 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 interrupt source set register (intset: address 000a 16 , initial value: 00 16 ) key-on wakeup interrupt valid bit b7 b0 interrupt source discrimination register (intdis: address 000b 16 , initial value: 00 16 ) key-on wakeup interrupt discrimination bit b7 b0 interrupt edge selection register (intedge : address 003a 16 , initial value: 00 16 ) b7 b0 not used (returns 0 when read) timer 1 interrupt valid bit a-d conversion interrupt valid bit uart1 bus collision detection interrupt valid bit 1: interrupt valid 0: interrupt invalid 1: interrupt occurs 0: interrupt does not occur not used (returns 0 when read) timer 1 interrupt discrimination bit a-d conversion interrupt discrimination bit uart1 bus collision detection interrupt discrimination bit int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 input port selection bit 0 : p3 6 1 : p3 3 not used (returns 0 when read) p0 0 key-on wakeup enable bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled p0 4 key-on wakeup enable bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled p0 6 key-on wakeup enable bit 0 : key-on wakeup enabled 1 : ke y -on wakeu p disabled fig. 22 structure of interrupt-related registers note: p3 6 does not exist for the 32-pin version. accordingly, select p3 3 for the int 1 function.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 25 preliminar y notice: this is not a final specification. some parametric limits are subject to change. key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying l level to any pin of port p0 that has been set to input mode. in other words, it is generated when the and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 23 connection example when using key input interrupt and port p0 block diagram port pxx l level output pull register bit 3 = 0 port p0 7 latch port p0 7 direction register = 1 ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos out p ut buffer pull register bit 3 = 0 port p0 6 latch port p0 6 direction register = 1 ** * p0 6 output pull register bit 3 = 0 port p0 5 latch port p0 5 direction register = 1 ** * p0 5 output pull register bit 3 = 0 port p0 4 latch port p0 4 direction register = 1 ** * p0 4 output pull register bit 2 = 1 port p0 3 latch port p0 3 direction register = 0 ** * p0 3 input pull register bit 2 = 1 port p0 2 latch port p0 2 direction register = 0 ** * p0 2 input pull register bit 1 = 1 port p0 1 latch port p0 1 direction register = 0 ** * p0 1 input pull register bit 0 = 1 port p0 0 latch port p0 0 direction register = 0 ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection port p0 0 key-on wakeup selection bit port p0 6 key-on wakeup selection bit port p0 4 key-on wakeup selection bit
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 26 preliminar y notice: this is not a final specification. some parametric limits are subject to change. timers the 7542 group has 4 timers: timer 1, timer x, timer a and timer b. the division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches ?? an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to each timer is set to ?? ?frequency divider for timer according to the clock division selection bits (b7 and b6) of cpu mode register (003b 16 ), the count source of frequency divider is set as follows; b7b6 = ?0?high-speed), ?1?middle-speed), ?1?double-speed): x in b7b6 = ?0?ring oscillator): ring oscillator timer 1 timer 1 is an 8-bit timer and counts the prescaler output. when timer 1 underflows, the timer 1 interrupt request bit is set to ?? prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. prescaler 1 and timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. the value of prescaler 1 latch is set to prescaler 1 when prescaler 1 underflows.the value of timer 1 latch is set to timer 1 when timer 1 underflows. when writing to prescaler 1 (pre1) is executed, the value is writ- ten to both the prescaler 1 latch and prescaler 1. when writing to timer 1 (t1) is executed, the value is written to both the timer 1 latch and timer 1. when reading from prescaler 1 (pre1) and timer 1 (t1) is ex- ecuted, each count value is read out. timer 1 always operates in the timer mode. prescaler 1 counts the signal which is the oscillation frequency di- vided by 16. each time the count clock is input, the contents of prescaler 1 is decremented by 1. when the contents of prescaler 1 reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count contin- ues. the division ratio of prescaler 1 is 1/(n+1) provided that the value of prescaler 1 is n. the contents of timer 1 is decremented by 1 each time the under- flow signal of prescaler 1 is input. when the contents of timer 1 reach ?0 16 ? an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the di- vision ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. accordingly, the division ratio of prescaler 1 and timer 1 is 1/((n+1) ? (m+1)) provided that the value of prescaler 1 is n and the value of timer 1 is m. timer 1 cannot stop counting by software. timer x timer x is an 8-bit timer and counts the prescaler x output. when timer x underflows, the timer x interrupt request bit is set to ?? prescaler x is an 8-bit prescaler and counts the signal selected by the timer x count source selection bit. prescaler x and timer x have the prescaler x latch and the timer x latch to retain the reload value, respectively. the value of prescaler x latch is set to prescaler x when prescaler x underflows.the value of timer x latch is set to timer x when timer x underflows. when writing to prescaler x (prex) is executed, the value is writ- ten to both the prescaler x latch and prescaler x. when writing to timer x (tx) is executed, the value is written to both the timer x latch and timer x. when reading from prescaler x (prex) and timer x (tx) is ex- ecuted, each count value is read out. timer x can can be selected in one of 4 operating modes by set- ting the timer x operating mode bits of the timer x mode register. (1) timer mode prescaler x counts the count source selected by the timer x count source selection bits. each time the count clock is input, the con- tents of prescaler x is decremented by 1. when the contents of prescaler x reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler x latch is reloaded into prescaler x and count continues. the division ratio of prescaler x is 1/(n+1) pro- vided that the value of prescaler x is n. the contents of timer x is decremented by 1 each time the under- flow signal of prescaler x is input. when the contents of timer x reach ?0 16 ? an underflow occurs at the next count clock, and the timer x latch is reloaded into timer x and count continues. the di- vision ratio of timer x is 1/(m+1) provided that the value of timer x is m. accordingly, the division ratio of prescaler x and timer x is 1/((n+1) ? (m+1)) provided that the value of prescaler x is n and the value of timer x is m. (2) pulse output mode in the pulse output mode, the waveform whose polarity is inverted each time timer x underflows is output from the cntr 0 pin. the output level of cntr 0 pin can be selected by the cntr 0 ac- tive edge switch bit. when the cntr 0 active edge switch bit is ?? the output of cntr 0 pin is started at ??level. when this bit is ?? the output is started at ??level. also, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting ??to the p0 3 /tx out output valid bit. when using a timer in this mode, set the port p1 4 and p0 3 direc- tion registers to output mode. (3) event counter mode the timer a counts signals input from the p1 4 /cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 0 pin input signal can be selected from rising or falling by the cntr 0 active edge switch bit .
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 27 preliminar y notice: this is not a final specification. some parametric limits are subject to change. (4) pulse width measurement mode in the pulse width measurement mode, the pulse width of the sig- nal input to p1 4 /cntr 0 pin is measured. the operation of timer x can be controlled by the level of the sig- nal input from the cntr 0 pin. when the cntr 0 active edge switch bit is ?? the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is ?? the count is stopped while the pin is ?? also, when the cntr 0 active edge switch bit is ?? the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is ?? the count is stopped while the pin is ?? timer x can stop counting by setting ??to the timer x count stop bit in any mode. also, when timer x underflows, the timer x interrupt request bit is set to ?? note on timer x is described below; note on timer x (1) cntr 0 interrupt active edge selection-1 cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. (2) cntr 0 interrupt active edge selection-2 according to the setting value of cntr 0 active edge switch bit, the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the active edge switch bit. ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). fig. 24 structure of timer x mode register fig. 25 timer count source set register t i m e r x m o d e r e g i s t e r ( t x m : a d d r e s s 0 0 2 b 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e ( i n e v e n t c o u n t e r m o d e ) 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e ( i n e v e n t c o u n t e r m o d e ) t i m e r x o p e r a t i n g m o d e b i t s b 1 b 0 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e n o t u s e d ( r e t u r n 0 w h e n r e a d ) t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0 p 0 3 / t x o u t o u t p u t v a l i d b i t 0 : o u t p u t i n v a l i d ( i / o p o r t ) 1 : o u t p u t v a l i d ( i n v e r t e d c n t r 0 o u t p u t ) b 7 b 0 t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 1 b 0 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : f ( x i n ) ( n o t e 1 ) 1 1 : n o t a v a i l a b l e t i m e r a c o u n t s o u r c e s e l e c t i o n b i t s b 4 b 3 b 2 000 : f ( x i n ) / 1 6 001 : f ( x i n ) / 2 010 : f ( x i n ) / 3 2 011 : f ( x i n ) / 6 4 100 : f ( x i n ) / 1 2 8 101 : f ( x i n ) / 2 5 6 110 : r i n g o s c i l l a t o r o u t p u t ( n o t e 2 ) 111 : n o t a v a i l a b l e t i m e r b c o u n t s o u r c e s e l e c t i o n b i t s b 7 b 6 b 5 000 : f ( x i n ) / 1 6 001 : f ( x i n ) / 2 010 : f ( x i n ) / 3 2 011 : f ( x i n ) / 6 4 100 : f ( x i n ) / 1 2 8 101 : f ( x i n ) / 2 5 6 110 : t i m e r a u n d e r f l o w 111 : n o t a v a i l a b l e n o t e s 1 : f ( x i n ) c a n b e u s e d a s t i m e r x c o u n t s o u r c e w h e n u s i n g a c e r a m i c r e s o n a t o r o r r i n g o s c i l l a t o r . d o n o t u s e i t a t r c o s c i l l a t i o n . 2 : r i n g o s c i l l a t o r c a n b e u s e d w h e n t h e r i n g o s c i l l a t o r i s e n a b l e d b y b i t 3 o f c p u m . timer count source set register (tcss : address 002a 16 , initial value: 00 16 )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 28 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 26 block diagram of timer 1 and timer x q q p1 4 /cntr 0 r t 1/16 1/2 timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode cntr 0 interrupt request bit pulse output mode port p1 4 latch port p1 4 direction register cntr 0 active edge switch bit timer mode pulse output mode cntr 0 active edge switch bit timer x count source selection bits 1/1 p0 3 /tx out prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) data bus 0 1 0 1 writing to timer x latch pulse output mode p0 3 /tx out output valid port p0 3 latch port p0 3 direction register prescaler 1 latch (8) prescaler 1 (8) timer 1 latch (8) timer 1 (8) 1/16 data bus timer 1 interrupt request bit frequency divider x in ring oscillator 00 01 11 0 10 clock division ratio selection bits
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 29 preliminar y notice: this is not a final specification. some parametric limits are subject to change. timer a,b timer a and timer b are 16-bit timers and counts the signal which is the oscillation frequency selected by setting of the timer count source set register (tcss). timer a and timer b have the same function except of the count source clock selection. the count source clock of timer a is selected from among 1/2,1/ 16, 1/32, 1/64, 1/128, 1/256 of f(x in ) clock and ring oscillator clock. the count source clock of timer b is selected from among 1/2, 1/ 16, 1/32, 1/64, 1/128, 1/256 of f(x in ) clock and timer a underflow. timer a (b) consists of the low-order of timer a: tal (timer b: tbl) and the high-order of timer a: tah (timer b: tbh). timer a (b) is decremented by 1 when each time of the count clock is in- put. when the contents of timer a (b) reach 0000 16 , an underflow occurs at the next count clock, and the timer latch is re- loaded into timer. when timer a (b) underflows, the timer a (b) interrupt request bit is set to 1 . timer a (b) has the timer a (b) latch to retain the load value. the value of timer a (b) latch is set to timer a (b) at the timing of timer a (b) underflow. the division ratio of timer a (b) is 1/(n+1) pro- vided that the value of timer a (b) is n. when writing to both the low-order of timer a (b) and the high or- der of timer a (b) is executed, writing to latch only or latch and timer can be selected by the setting value of the timer a (b) write control bit. when reading from timer a (b) register is executed, the count value of timer a (b) is read out. be sure to write to/read out the low-order of timer a (b) and the high-order of timer a (b) in the following order; read read the high-order of timer a (b) first, and the low-order of timer a (b) next and be sure to read both high-order and low-order. write write to the low-order of timer a (b) first, and the high-order of timer a (b) next and be sure to write both low-order and high or- der. timer a and timer b can be used for the timing timer of input cap- ture and output compare function. notes on timer a, b (1) setting of timer value when 1: write to only latch is set to the timer a (b) write control bit, written data to timer register is set to only latch even if timer is stopped. accordingly, in order to set the initial value for timer when it is stopped, set 0: write to latch and timer simultaneously to timer a (b) write control bit. (2) read/write of timer a stop timer a to read/write its data when the system is in the follow- ing state; cpu operation clock source: x in oscillation timer a count source: ring oscillator output (3) read/write of timer b stop timer b to read/write its data when the system is in the fol- lowing state; cpu operation clock source: x in oscillation timer b count source: timer a underflow timer a count source: ring oscillator output
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 30 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 29 block diagram of timer a and timer b timer a (low-order) latch (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (high-order) (8) data bus timer a interrupt request compare capture timer b (low-order) latch (8) timer b (low-order) (8) timer b (high-order) latch (8) timer b (high-order) (8) data bus timer b interrupt request compare capture 1/2 1/16 1/32 1/64 1/128 1/256 timer a count stop bit timer a count source selection bits ring oscillator timer a write control bit timer b write control bit 1/2 1/16 1/32 1/64 1/128 1/256 timer b count stop bit timer b count source selection bits frequency divider ring oscillator x in ?0 ?1 ?1 clock division ratio selection bits ?0 frequency divider fig. 27 structure of timer a, b mode register fig. 28 timer count source set register t i m e r a , b m o d e r e g i s t e r ( t a b m : a d d r e s s 0 0 1 d 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 t i m e r a w r i t e c o n t r o l b i t 0 : w r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t e t o o n l y l a t c h t i m e r a c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r b w r i t e c o n t r o l b i t 0 : w r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t e t o o n l y l a t c h t i m e r b c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p n o t u s e d ( r e t u r n 0 w h e n r e a d ) c o m p a r e 0 , 1 m o d u l a t i o n m o d e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 2 , 3 m o d u l a t i o n m o d e b i t 0 : d i s a b l e d 1 : e n a b l e d b 7 b 0 t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 1 b 0 0 0 : f ( x i n ) / 1 6 0 1 : f ( x i n ) / 2 1 0 : f ( x i n ) ( n o t e 1 ) 1 1 : n o t a v a i l a b l e t i m e r a c o u n t s o u r c e s e l e c t i o n b i t s b 4 b 3 b 2 000 : f ( x i n ) / 1 6 001 : f ( x i n ) / 2 010 : f ( x i n ) / 3 2 011 : f ( x i n ) / 6 4 100 : f ( x i n ) / 1 2 8 101 : f ( x i n ) / 2 5 6 110 : r i n g o s c i l l a t o r o u t p u t ( n o t e 2 ) 111 : n o t a v a i l a b l e t i m e r b c o u n t s o u r c e s e l e c t i o n b i t s b 7 b 6 b 5 000 : f ( x i n ) / 1 6 001 : f ( x i n ) / 2 010 : f ( x i n ) / 3 2 011 : f ( x i n ) / 6 4 100 : f ( x i n ) / 1 2 8 101 : f ( x i n ) / 2 5 6 110 : t i m e r a u n d e r f l o w 111 : n o t a v a i l a b l e n o t e s 1 : f ( x i n ) c a n b e u s e d a s t i m e r x c o u n t s o u r c e w h e n u s i n g a c e r a m i c r e s o n a t o r o r r i n g o s c i l l a t o r . d o n o t u s e i t a t r c o s c i l l a t i o n . 2 : r i n g o s c i l l a t o r c a n b e u s e d w h e n t h e r i n g o s c i l l a t o r i s e n a b l e d b y b i t 3 o f c p u m . t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s : a d d r e s s 0 0 2 a 1 6 , i n i t i a l v a l u e : 0 0 1 6 )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 31 preliminar y notice: this is not a final specification. some parametric limits are subject to change. output compare 7542 group has 4-output compare channels. each channel (0 to 3) has the same function and can be used to output waveform by us- ing count value of either timer a or timer b. the source timer for each channel is selected by setting value of the compare x (x = 0, 1, 2, 3) timer source bit. timer a and timer b can be selected for the source timer to each channel, respectively. to use each compare channel, set ??to the compare x output port bit and set the port direction register corresponding to com- pare channel to output mode. the compare value for each channel is set to the compare regis- ter (low-order) and compare register (high-order). writing to the register for each channel is controlled by setting value of compare register write pointer. writing to each register is in the following order; 1.set the value of corresponded output compare channel to the compare register write pointer. 2.write a value to the compare register (low-order) and compare register (high-order). 3.set ??to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31) re-load bit. when ??is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. when count value of timer and setting value of compare latch is matched, compare output trigger occurs. when ?: enabled?is set to the compare trigger x enable bit, the output waveform from port is inverted by compare trigger. when ?: disabled?is set to the compare trigger x enable bit, the out- put waveform is not inverted, so port output can be fixed to ??or ?? when ?: positive?is set to the compare x output level latch, the compare output waveform is turned to ? level?at compare latch x0s match and turned to ? level?at compare latch x1s match. when ? :negative?is set to the compare x output level latch, the compare output waveform is turned to ? level?at compare latch x0s match and turned to ? level?at compare latch x1s match. the compare output level of each channel can be confirmed by reading the compare x output status bit. compare output interrupt is available when match of each com- pare channel and timer count value. the interrupt request from each channel can be disabled or enabled by setting value of com- pare latch y interrupt source bit. compare 0,1 (2,3) modulation mode in compare modulation mode, modulation waveform can be gener- ated by using compare channel 0 and 1, or compare channel 2 and 3. to use this mode, ?set ?: enabled?to the compare 0,1 (2, 3) modulation mode bit. ?set timer a underflow for timer b count source. ?set timer a for the timer source of compare channel 0 (2). ?set timer b for the timer source of compare channel 1 (3). in this mode, and waveform of compare 0 (1) and compare 2 (3) is generated from port p0 1 and p3 1 , respectively. accordingly, in order to use this mode, set ??to the compare 0 output port bit or compare 2 output port bit. fig. 30 structure of capture/compare register r/w pointer fig. 31 structure of compare register re-load register b 7 b 0 c o m p a r e r e g i s t e r r / w p o i n t e r b 2 b 1 b 0 000 : c o m p a r e l a t c h 0 0 001 : c o m p a r e l a t c h 0 1 010 : c o m p a r e l a t c h 1 0 011 : c o m p a r e l a t c h 1 1 100 : c o m p a r e l a t c h 2 0 101 : c o m p a r e l a t c h 2 1 110 : c o m p a r e l a t c h 3 0 111 : c o m p a r e l a t c h 3 1 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e r e g i s t e r 0 r / w p o i n t e r 0 : c a p t u r e l a t c h 0 0 1 : c a p t u r e l a t c h 0 1 c a p t u r e r e g i s t e r 1 r / w p o i n t e r 0 : c a p t u r e l a t c h 1 0 1 : c a p t u r e l a t c h 1 1 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e / c o m p a r e r e g i s t e r r / w p o i n t e r ( c c r p : a d d r e s s 0 0 1 2 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e l a t c h 0 0 , 0 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w c o m p a r e l a t c h 1 0 , 1 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w c o m p a r e l a t c h 2 0 , 2 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w c o m p a r e l a t c h 3 0 , 3 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w n o t u s e d ( r e t u r n s 0 w h e n r e a d ) compare register re-load register (cmpr : address 0014 16 , initial value: 00 16 ) notes on output compare ?when the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously. ?do not write the same data to both of compare latch x0 and x1. ?when setting value of the compare latch is larger than timer set- ting value, compare match signal is not generated. accordingly, the output waveform is fixed to ??or ??level. however, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. accordingly, compare match interrupt occurs. ?when the compare x trigger enable bit is cleared to ??(dis- abled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to ??or ? level. however, in this case, the compare match signal is generated. accordingly, compare match interrupt occurs.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 32 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 33 structure of timer source selection register fig. 34 structure of compare output mode register fig. 35 structure of capture/compare status register fig. 36 structure of compare interrupt source register b 7 b 0 c o m p a r e 0 t i m e r s o u r c e b i t c o m p a r e 1 t i m e r s o u r c e b i t c o m p a r e 2 t i m e r s o u r c e b i t c o m p a r e 3 t i m e r s o u r c e b i t c a p t u r e 0 t i m e r s o u r c e b i t c a p t u r e 1 t i m e r s o u r c e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) 0 : t i m e r a 1 : t i m e r b t i m e r s o u r c e s e l e c t i o n r e g i s t e r ( t m s r : a d d r e s s 0 0 1 f 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e 0 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 1 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 2 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 3 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 0 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 1 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 2 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 3 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e o u t p u t m o d e r e g i s t e r ( c m o m : a d d r e s s 0 0 2 1 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e 0 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c o m p a r e 1 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c o m p a r e 2 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c o m p a r e 3 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c a p t u r e 0 s t a t u s b i t 0 : l a t c h 0 0 c a p t u r e d 1 : l a t c h 0 1 c a p t u r e d c a p t u r e 1 s t a t u s b i t 0 : l a t c h 1 0 c a p t u r e d 1 : l a t c h 1 1 c a p t u r e d n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e / c o m p a r e s t a t u s r e g i s t e r ( c c s r : a d d r e s s 0 0 2 2 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 compare latch 00 interrupt source bit compare latch 01 interrupt source bit compare latch 10 interrupt source bit compare latch 11 interrupt source bit compare latch 20 interrupt source bit compare latch 21 interrupt source bit compare latch 30 interrupt source bit compare latch 31 interrupt source bit 0: disabled 1: enabled c o m p a r e i n t e r r u p t s o u r c e r e g i s t e r ( c i s r : a d d r e s s 0 0 2 3 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) fig. 32 structure of capture/compare port register b 7 b 0 c a p t u r e 0 i n p u t p o r t b i t s b 1 b 0 00 : c a p t u r e f r o m p 0 0 01 : c a p t u r e f r o m p 1 0 10 : r i n g / 5 1 2 11 : n o t a v a i l a b l e c o m p a r e 0 o u t p u t p o r t b i t 0 : p 0 1 i s i / o p o r t 1 : p 0 1 i s c o m p a r e 0 c o m p a r e 1 o u t p u t p o r t b i t 0 : p 0 2 i s i / o p o r t 1 : p 0 2 i s c o m p a r e 1 c a p t u r e 1 i n p u t p o r t b i t 0 : c a p t u r e f r o m p 3 0 1 : r i n g / 5 1 2 c o m p a r e 2 o u t p u t p o r t b i t 0 : p 3 1 i s i / o p o r t 1 : p 3 1 i s c o m p a r e 2 c o m p a r e 3 o u t p u t p o r t b i t 0 : p 3 2 i s i / o p o r t 1 : p 3 2 i s c o m p a r e 3 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e / c o m p a r e p o r t r e g i s t e r ( c c p r : a d d r e s s 0 0 1 e 1 6 , i n i t i a l v a l u e : 0 0 1 6 )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 33 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 37 block diagram of output compare fig. 38 block diagram of compare channel 0 timer a latch timer a counter timer b counter timer b latch compare latch 00 compare latch 01 wave latch channel 0 compare 0 timer source bit compare channel 0 compare channel 1 compare channel 2 compare channel 3 p0 1 p0 2 p3 1 p3 2 compare buffer 00 (16) compare latch 00 (16) compare buffer 01 (16) compare latch 01 (16) data bus compare interrupt compare register write pointer (0012 16 , bits 0 to 2) compare latch 00, 01 re-load bit (0014 16 , bit 0) timer a counter (16) compare 0 timer source bit (001f 16 , bit 0) compare 0 trigger enable bit (0021 16 , bit 4) output latch compare 0 output level latch (0021 16 , bit 0) compare 0 output status bit (0022 16 , bit 0) compare 0 output port bit (001e 16 , bit 2) p0 1 timer b counter (16) i/o port compare latch 00 interrupt source bit (0023 16 , bit 0) compare latch 01 interrupt source bit (0023 16 , bit 1) compare register
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 34 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 39 block diagram of compare channel 0, 1 compare buffer 00 (16) compare latch 00 (16) compare buffer 01 (16) compare latch 01 (16) data bus compare register compare register write pointer (0012 16 , bits 0 to 2) compare latch 00, 01 re-load bit (0014 16 , bit 0) timer a counter (16) compare 0 (1) timer source bits (001f 16 , bit 0 (bit 1) compare 0 trigger enable bit (0021 16 , bit 4) output latch compare 0 output level latch (0021 16 , bit 0) compare 0 output status bit (0022 16 , bit 0) compare 0 output port bit (001e 16 , bit 2) p0 1 timer b counter (16) compare 1 trigger enable bit (0021 16 , bit 5) output latch compare 1 output level latch (0021 16 , bit 1) compare 1 output status bit (0022 16 , bit 1) underflow compare latch 10 (16) compare buffer 10 (16) compare latch 11 (16) compare buffer 11 (16) data bus compare register compare latch 10, 11 re-load bit (0014 16 , bit 1) compare register write pointer (0012 16 , bits 0 to 2) i/o port
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 35 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 40 output compare mode (general waveform) fig. 41 output compare mode (compare register write timing) 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 000b 0005 0 1 0 timer underflow timer count value compare latch 00 compare latch 01 compare 00 match compare 01 match compare output compare interrupt compare status bit timer count clock note: compare interrupt occurs only for the interrupt source selected by compare interrupt source register. re-load the count value 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 000b 0005 0 1 1 0 000e 000c 0 timer underflow timer count value compare latch 00 compare latch 01 compare latch 00 write compare latch 01 write compare latch 00, 01 re-load bit compare latch 00, 01 re-load signal compare 00 match compare 01 match compare output compare interrupt compare status bit timer count clock re-load the count value
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 36 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 42 output compare mode (compare 0, 1 modulation mode) 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 0003 0000 0006 0002 0 1 1 0 1 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 0003 0000 0004 0001 0 1 1 0 1 0 timer a underflow timer a count value compare latch 00 compare latch 01 compare 00 match compare 01 match compare 0 output compare 0 output status bit timer a count clock carrier wave generated by compare 0 compare 0 output timer b count value compare latch 10 compare latch 11 compare 10 match compare 11 match compare 1 output compare interrupt compare 1 output status bit timer a underflow modulation of output waveform generated by compare 1 modulation output note: compare interrupt occurs only for the interrupt source selected by compare interrupt source register. port outptu wavefowm
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 37 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 43 output compare mode (compare 0, 1 modulation mode: effect of output level latch) modulation output compare 1 output compare 0 output 1. when compare 0 output level latch is ?ositive? compare 1 output level latch is ?ositive? modulation output compare 1 output compare 0 output 2. when compare 0 output level latch is ?egative? compare 1 output level latch is ?ositive? modulation output compare 1 output compare 0 output 3. when compare 0 output level latch is ?ositive? compare 1 output level latch is ?egative? modulation output compare 1 output compare 0 output 4. when compare 0 output level latch is ?egative? compare 1 output level latch is ?egative?
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 38 preliminar y notice: this is not a final specification. some parametric limits are subject to change. input capture 7542 group has 2-input capture channels. each channel (0 and 1) has the same function and can be used to capture count value of either timer a or timer b. the source timer for each channel is selected by setting value of the capture x (x = 0, 1) timer source bit. timer a and timer b can be selected for the source timer to each channel, respectively. to use each capture channel, set the capture x input port bits and set the port direction register corresponding to capture channel to input mode. the input capture circuit retains the count value of selected timer when external trigger is input. the timer count value is retained to the capture latch x0 when rising edge is input and is retained to the capture latch x1 when falling edge is input. the count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. when ??is set to this bit, count value of timer is retained to the corresponded capture latch. when reading from the capture y software trigger bit is executed, ??is read out. the latest status of capture latch can be confirmed by reading of the capture x status bit. this bit indicates the capture latch which latest data is in. the valid trigger edge for capture interrupt is set by the capture x interrupt edge selection bits. (regardless of the setting value of capture x interrupt edge selection bits, timer count values for both edges are retained to the capture latch.) each capture input has the noise filter circuit that judges continu- ous 4-time same level with sampling clock to be valid. the sampling clock of noise filter is set by the capture x noise filter clock selection bits. reading from the register for each channel is controlled by setting value of the capture register read pointer. reading from each reg- ister is in the following order; 1.set the value of the corresponded input capture channel to the capture register read pointer. 2.read from the capture register (low-order) and capture register (high-order). notes on input capture ?if the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. accordingly, some countermeasure by software is recommended, for example comparing the values that twice of read. ?when the ring-oscillator is selected for timer a count source, timer a cannot be used for the capture source timer. timer b cannot be used for the capture source timer when the system is in the following state; ?cpu operation clock source: x in oscillation ?timer b count source: timer a underflow ?timer a count source: ring oscillator output ?when writing ??to capture latch x0 (x1) software trigger bit of capture latch x0 and x1 at the same time, or external trigger and software trigger occur simultaneously, the set value of capture x status bit is undefined. ?when setting the interrupt active edge selection bit and noise fil- ter clock selection bit of external interrupt cap 0 , cap 1 , the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge selection bit or noise filter clock selection bit. ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). ?the capture interrupt cannot be used as the interrupt for return from stop mode. even when the valid edge of the capture inter- rupt is input at stop mode, system retains the stop mode. then, system returns from stop mode by other external interrupts, the capture interrupt is accepted. in this case, after system returns from stop mode, the interrupt request bit of the corresponding capture interrupt is set to ??
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 39 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 44 structure of capture software trigger register b 7 b 0 c a p t u r e r e g i s t e r 0 ( l o w - o r d e r ) ( c a p 0 l : a d d r e s s 0 0 0 c 1 6 ) b 7 b 0 c a p t u r e r e g i s t e r 0 ( h i g h - o r d e r ) ( c a p 0 h : a d d r e s s 0 0 0 d 1 6 ) b 7 b 0 c a p t u r e r e g i s t e r 1 ( l o w - o r d e r ) ( c a p 1 l : a d d r e s s 0 0 0 e 1 6 ) b 7 b 0 c a p t u r e r e g i s t e r 1 ( h i g h - o r d e r ) ( c a p 1 h : a d d r e s s 0 0 0 f 1 6 ) b 7 b 0 c a p t u r e 0 i n t e r r u p t e d g e s e l e c t i o n b i t s b 1 b 0 00 : r i s i n g a n d f a l l i n g e d g e 01 : r i s i n g e d g e 10 : f a l l i n g e d g e 11 : n o t a v a i l a b l e c a p t u r e 1 i n t e r r u p t e d g e s e l e c t i o n b i t s b 3 b 2 00 : r i s i n g a n d f a l l i n g e d g e 01 : r i s i n g e d g e 10 : f a l l i n g e d g e 11 : n o t a v a i l a b l e c a p t u r e 0 n o i s e f i l t e r c l o c k s e l e c t i o n b i t s b 5 b 4 00 : f i l t e r s t o p 01 : f ( x i n ) 10 : f ( x i n ) / 8 11 : f ( x i n ) / 3 2 c a p t u r e 1 n o i s e f i l t e r c l o c k s e l e c t i o n b i t s b 7 b 6 00 : f i l t e r s t o p 01 : f ( x i n ) 10 : f ( x i n ) / 8 11 : f ( x i n ) / 3 2 c a p t u r e m o d e r e g i s t e r ( c a p m : a d d r e s s 0 0 2 0 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c a p t u r e l a t c h 0 0 s o f t w a r e t r i g g e r b i t c a p t u r e l a t c h 0 1 s o f t w a r e t r i g g e r b i t c a p t u r e l a t c h 1 0 s o f t w a r e t r i g g e r b i t c a p t u r e l a t c h 1 1 s o f t w a r e t r i g g e r b i t e a c h so f t w a r e t r i g g e r o c c u r s b y s e t t i n g 1 t o c o r r e s p o n d i n g b i t . ( r e t u r n s 0 w h e n r e a d ) n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e s o f t w a r e t r i g g e r r e g i s t e r ( c s t r : a d d r e s s 0 0 1 3 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) fig. 45 structure of capture software trigger register/capture mode register
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 40 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 46 block diagram of input capture fig. 47 block diagram of capture channel 0 timer a latch timer a counter timer b counter timer b latch capture latch 00 capture latch 01 trigger input channel 0 capture 0 timer source bit capture channel 0 capture channel 1 p1 0 ring /512 ring /512 p3 0 p0 0 capture pointer (0013 16 , bits 4, 5) capture latch 00 (16) capture latch 01 (16) data bus capture interrupt capture register 0 read pointer (0012 16 , bit 4) timer a counter (16) capture 0 timer source bit (001f 16 , bit 4) capture trigger capture 0 status bit (0022 16 , bit 4) digital filter ring/512 capture latch 00 software trigger bit (0013 16 , bit 0) capture 0 input port bits (001e 16 , bits 0, 1) timer b counter (16) capture 0 interrupt edge selection bits (0020 16 , bits 0, 1) p1 0 capture register capture latch 0 (16) capture 0 noise filter clock selection bits (0020 16 , bits 4, 5) p0 0 rising falling
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 41 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 48 capture interrupt edge selection = rising edge fig. 49 capture interrupt edge selection = rising and falling edge 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 xxxx 000a 000c xxxx 0005 0001 000f 1 0 1 010 timer underflow capture input wave timer count value capture latch 00 capture latch 01 capture interrupt capture x (x=0, 1) status bit re-load the timer count value overwrite 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 1 0 1 010 xxxx 000a 000c xxxx 0005 0001 000f timer underflow capture input wave timer count value capture latch 00 capture latch 01 capture interrupt capture x (x=0, 1) status bit re-load the timer count value overwrite
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 42 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 50 block diagram of clock synchronous serial i/o1 fig. 51 operation of clock synchronous serial i/o1 function serial i/o the 7542 group has serial i/o1 and serial i/o2. except that se- rial i/o1 has the bus collision detection function, they have the same function. serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6) to ?? for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. 1/4 1/4 f/f p 1 2 / s c l k 1 serial i/o1 status register serial i/o1 control register p1 3 /s rdy1 p 1 0 / r x d 1 / c a p 0 p1 1 /t x d 1 x i n r e c e i v e b u f f e r r e g i s t e r 1 a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r 1 receive buffer full flag (rbf) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator 1 address 001c 16 b r g c o u n t s o u r c e s e l e c t i o n b i t clock control circui t f a l l i n g - e d g e d e t e c t o r transmit buffer register 1 data bus address 0018 16 shift cloc k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t address 0019 16 d a t a b u s a d d r e s s 0 0 1 a 1 6 transmit shift register 1 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 t b e = 1 t s c = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) serial output txd 1 s e r i a l i n p u t r x d 1 w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 1
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 43 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 52 block diagram of uart serial i/o1 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 53 operation of uart serial i/o1 function x i n 1/4 oe pe fe 1 / 1 6 1/16 data bus r e c e i v e b u f f e r r e g i s t e r 1 a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r 1 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) baud rate generator 1 f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) address 001c 16 st/sp/pa generator transmit buffer register 1 data bus t r a n s m i t s h i f t r e g i s t e r 1 address 0018 16 t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) address 0019 16 s t d e t e c t o r sp detector u a r t 1 c o n t r o l r e g i s t e r a d d r e s s 0 0 1 b 1 6 character length selection bit a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s serial i/o1 control register p 1 2 / s c l k 1 serial i/o1 status register p 1 0 / r x d 1 / c a p 0 p1 1 /t x d 1 t s c = 0 t b e = 1 r b f = 0 t b e = 0t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 s t d 0 d 1 s p d 0 d 1 s t s p t r a n s m i t o r r e c e i v e c l o c k t r a n s m i t b u f f e r w r i t e s i g n a l g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , c a n b e s e l e c t e d t o o c c u r d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s ? ? s e r i a l o u t p u t t x d 1 s e r i a l i n p u t r x d 1 r e c e i v e b u f f e r r e a d s i g n a l
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 44 preliminar y notice: this is not a final specification. some parametric limits are subject to change. [transmit buffer register 1/receive buffer register 1 (tb1/ rb1)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit of the serial i/o1 control regis- ter has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart1 control register (uart1con)] 001b 16 the uart1 control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the p1 1 /txd 1 pin. [baud rate generator 1 (brg1)] 001c 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o1 serial i/o interrupt when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled). i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit 1 : clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin turns into an output pin of a synchronous clock. 1 : p1 2 pin turns into an input pin of a synchronous clock. setup of a s rdy1 output enable bit (srdy) 0 : p1 3 pin can be used as a normal i/o pin. 1 : p1 3 pin turns into a s rdy1 output pin. (2) serial i/o1 mode selection bit 0 : clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin can be used as a normal i/o pin. 1 : p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 45 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 54 structure of serial i/o1-related registers t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) b 7 b 7 s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) 1 : f ( x i n ) / 4 s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 1 3 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 1 3 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 1 d i s a b l e d ( p i n s p 1 0 t o p 1 3 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 1 e n a b l e d ( p i n s p 1 0 t o p 1 3 o p e r a t e a s s e r i a l i / o p i n s ) b 7 u a r t 1 c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 1 1 / t x d 1 p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 , i n i t i a l v a l u e : 8 0 1 6 ) ( s i o 1 c o n : a d d r e s s 0 0 1 a 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) ( u a r t 1 c o n : a d d r e s s 0 0 1 b 1 6 , i n i t i a l v a l u e : e 0 1 6 )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 46 preliminar y notice: this is not a final specification. some parametric limits are subject to change. bus collision detection (sio1) sio1 can detect a bus collision by setting uart1 bus collision de- tection interrupt enable bit. when transmission is started in the clock synchronous or asyn- chronous (uart) serial i/o mode, the transmit pin txd 1 is compared with the receive pin rxd 1 in synchronization with rising edge of transmit shift clock. if they do not coincide with each other, a bus collision detection interrupt request occurs. when a transmit data collision is detected between lsb and msb of transmit data in the clock synchronous serial i/o mode or be- tween the start bit and stop bit of transmit data in uart mode, a bus collision detection can be performed by both the internal clock and the external clock. a block diagram is shown in fig. 56. a timing diagram is shown in fig. 57. note: bus collision detection can be used when sio1 is operating at full-duplex communication. when sio1 is operating at half-duplex communication, set bus collision detection inter- rupt to be disabled. fig. 56 block diagram of bus collision detection interrupt circuit fig. 57 timing diagram of bus collision detection interrupt bus collision detection interrupt generation data collision transmit shift clock transmit pin txd 1 receive pin rxd 1 d txd rxd shift clock uart1 bus collision detection interrupt valid bit (address 000a 16 , bit 1) uart1 bus collision detection interrupt discrimination bit (address 000b 16 , bit 1) key-on wakeup/ uart1 bus collision detection interrupt request bit (address 003c 16 , bit 6) key-on wakeup interrupt request q 0 : no interrupt request issued interrupt source set register (intset: address 000a 16 , initial value: 00 16 ) key-on wakeup interrupt valid bit b7 b0 0: interrupt invalid interrupt source discrimination register (intdis: address 000b 16 , initial value: 00 16 ) key-on wakeup interrupt discrimination bit b7 b0 interrupt request register 1 (ireq1 : address 003c 16 , initial value : 00 16 ) serial i/o1 receive interrupt request bit b7 b0 serial i/o1 receive interrupt enable bit 0 : interrupts disabled interrupt control register 1 (icon1 : address 003e 16 , initial value : 00 16 ) b7 b0 1 : interrupts enabled cntr 0 interrupt enable bit key-on wake up/uart1 bus collision int 1 interrupt enable bit int 0 interrupt enable bit serial i/o2 transmit interrupt enable bit serial i/o2 receive interrupt enable bit serial i/o1 transmit interrupt enable bit detection interrupt enable bit 1 : interrupt request issued cntr 0 interrupt request bit detection interrupt request bit key-on wake up/uart1 bus collision int 1 interrupt request bit int 0 interrupt request bit serial i/o2 transmit interrupt request bit serial i/o2 receive interrupt request bit serial i/o1 transmit interrupt request bit 1: interrupt occurs 0: interrupt does not occur not used (returns ??when read) timer 1 interrupt discrimination bit a-d conversion interrupt discrimination bit discrimination bit uart1 bus collision detection interrupt 1: interrupt valid not used (returns ??when read) timer 1 interrupt valid bit a-d conversion interrupt valid bit uart1 bus collision detection interrupt valid bit fig. 55 bus collision detection circuit related registers
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 47 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 58 block diagram of clock synchronous serial i/o2 fig. 59 operation of clock synchronous serial i/o2 function serial i/o2 serial i/o2 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o2 mode can be selected by setting the serial i/o2 mode selection bit of the serial i/o2 control register (bit 6) to 1 . for clock synchronous serial i/o2, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 tbe = 1 tsc = 0 t r a n s f e r s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) serial output txd 2 s e r i a l i n p u t r x d 2 w r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 2 e 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n notes 1 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 2 1 / 4 1 / 4 f / f p 0 6 / s c l k 2 s e r i a l i / o 2 s t a t u s r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r p 0 7 / s r d y 2 p 0 4 / r x d 2 p 0 5 / t x d 2 x i n r e c e i v e b u f f e r r e g i s t e r 2 a d d r e s s 0 0 2 e 1 6 r e c e i v e s h i f t r e g i s t e r 2 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r 2 a d d r e s s 0 0 3 2 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g - e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r 2 d a t a b u s a d d r e s s 0 0 2 e 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 2 f 1 6 d a t a b u s a d d r e s s 0 0 3 0 1 6 t r a n s m i t s h i f t r e g i s t e r 2
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 48 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 60 block diagram of uart serial i/o2 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o2 mode selection bit of the serial i/o2 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 61 operation of uart serial i/o2 function x i n 1/4 oe pe fe 1 / 1 6 1/16 d a t a b u s r e c e i v e b u f f e r r e g i s t e r 2 address 002e 16 r e c e i v e s h i f t r e g i s t e r 2 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) baud rate generator 2 frequency division ratio 1/(n+1) address 0032 16 st/sp/pa generator transmit buffer register 2 data bus transmit shift register 2 address 002e 16 t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) transmit buffer empty flag (tbe) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) address 002f 16 st detector sp detector u a r t 2 c o n t r o l r e g i s t e r address 0031 16 character length selection bit a d d r e s s 0 0 3 0 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t transmit interrupt source selection bit s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 bits s e r i a l i / o 2 c o n t r o l r e g i s t e r p 0 6 / s c l k 2 s e r i a l i / o 2 s t a t u s r e g i s t e r p 0 4 / r x d 2 p0 5 /t x d 2 t s c = 0 t b e = 1 r b f = 0 t b e = 0t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 s t d 0 d 1 s p d 0 d 1 s t s p t r a n s m i t o r r e c e i v e c l o c k t r a n s m i t b u f f e r w r i t e s i g n a l g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : a s t h e t r a n s m i t i n t e r r u p t ( t i ) , w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , c a n b e s e l e c t e d t o o c c u r d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s ? ? s e r i a l o u t p u t t x d 2 s e r i a l i n p u t r x d 2 r e c e i v e b u f f e r r e a d s i g n a l
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 49 preliminar y notice: this is not a final specification. some parametric limits are subject to change. [transmit buffer register 2/receive buffer register 2 (tb2/ rb2)] 002e 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o2 status register (sio2sts)] 002f 16 the read-only serial i/o2 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o2 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o2 enable bit sioe (bit 7 of the serial i/o2 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o2 status register are initialized to 0 at reset, but if the transmit enable bit of the serial i/o2 control regis- ter has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o2 control register (sio2con)] 0030 16 the serial i/o2 control register consists of eight control bits for the serial i/o2 function. [uart2 control register (uart2con)] 0031 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p0 5 /txd 2 pin. [baud rate generator 2 (brg2)] 0032 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o2 serial i/o interrupt when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled). i/o pin function when serial i/o2 is enabled. the functions of p0 6 and p0 7 are switched with the setting values of a serial i/o2 mode selection bit and a serial i/o2 synchronous clock selection bit as follows. (1) serial i/o2 mode selection bit 1 : clock synchronous type serial i/o is selected. setup of a serial i/o2 synchronous clock selection bit 0 : p0 6 pin turns into an output pin of a synchronous clock. 1 : p0 6 pin turns into an input pin of a synchronous clock. setup of a s rdy2 output enable bit (srdy) 0 : p0 7 pin can be used as a normal i/o pin. 1 : p0 7 pin turns into a s rdy2 output pin. (2) serial i/o2 mode selection bit 0 : clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o2 synchronous clock selection bit 0 : p0 6 pin can be used as a normal i/o pin. 1 : p0 6 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p0 7 pin. it can be used as a normal i/o pin.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 50 preliminar y notice: this is not a final specification. some parametric limits are subject to change. t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) b 7 b 7 s e r i a l i / o 2 s t a t u s r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) 1 : f ( x i n ) / 4 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 2 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 0 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 0 7 p i n o p e r a t e s a s s r d y 2 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 2 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 2 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 2 d i s a b l e d ( p i n s p 0 4 t o p 0 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 2 e n a b l e d ( p i n s p 0 4 t o p 0 7 o p e r a t e a s s e r i a l i / o p i n s ) b 7 u a r t 2 c o n t r o l r e g i s t e r character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p0 5 /t x d 2 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b 0 ( s i o 2 s t s : a d d r e s s 0 0 2 f 1 6 , i n i t i a l v a l u e : 8 0 1 6 ) ( s i o 2 c o n : a d d r e s s 0 0 3 0 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) ( u a r t 2 c o n : a d d r e s s 0 0 3 1 1 6 , i n i t i a l v a l u e : e 0 1 6 ) fig. 62 structure of serial i/o2-related registers
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 51 preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register] ad the a-d conversion register is a read-only register that stores the result of a-d conversion. do not read out this register during an a- d conversion. [a-d control register] adcon the a-d control register controls the a-d converter. bit 2 to 0 are analog input pin selection bits. bit 4 is the ad conversion comple- tion bit. the value of this bit remains at 0 during a-d conversion, and changes to 1 at completion of a-d conversion. a-d conversion is started by setting this bit to 0 . [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 1024, and outputs the divided voltages. [channel selector] the channel selector selects one of ports p2 7 /an 7 to p2 0 /an 0 , and inputs the voltage to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the a-d conversion register. when a-d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . because the comparator is constructed linked to a capacitor, set f(x in ) to 500 khz or more during a-d con- version. fig. 63 structure of a-d control register fig. 64 structure of a-d conversion register fig. 65 block diagram of a-d converter a-d control register (address 0034 16 ) channel selector a-d control circuit resistor ladder v ref comparator a-d interrupt request b7 b0 data bus 3 10 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 p2 6 /an 6 p2 7 /an 7 a-d conversion register (low-order) (address 0036 16 ) (address 0035 16 ) a-d conversion register (high-order) v ss read 8-bit (read only address 0035 16 ) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 (address 0035 16 ) read 10-bit (read in order address 0036 16 , 0035 16 ) b7 b0 b9 b8 (address 0036 16 ) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 (address 0035 16 ) note: high-order 6-bit of address 0036 16 returns 0 when read. n o t u s e d ( r e t u r n s 0 w h e n r e a d ) a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d b 7 b 0 a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 2 0 / a n 0 0 0 1 : p 2 1 / a n 1 0 1 0 : p 2 2 / a n 2 0 1 1 : p 2 3 / a n 3 1 0 0 : p 2 4 / a n 4 1 0 1 : p 2 5 / a n 5 1 1 0 : p 2 6 / a n 6 ( n o t e ) 1 1 1 : p 2 7 / a n 7 ( n o t e ) n o t e : t h e s e c a n b e u s e d o n l y f o r 3 6 p i n v e r s i o n . a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 , i n i t i a l v a l u e : 1 0 1 6 ) n o t u s e d ( d o n o t w r i t e 1 t o t h i s b i t . )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 52 preliminar y notice: this is not a final specification. some parametric limits are subject to change. watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8-bit watchdog timer l, being a 16-bit counter. standard operation of watchdog timer the watchdog timer stops when the watchdog timer control regis- ter (address 0039 16 ) is not set after reset. writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. when the watchdog timer h underflows, an internal reset occurs. accord- ingly, it is programmed that the watchdog timer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h, stp instruction disable bit and watchdog timer h count source se- lection bit are read. initial value of watchdog timer by a reset or writing to the watchdog timer control register (ad- dress 0039 16 ), the watchdog timer h is set to ff 16 and the watchdog timer l is set to ff 16 . operation of watchdog timer h count source selection bit a watchdog timer h count source can be selected by bit 7 of the watchdog timer control register (address 0039 16 ). when this bit is 0 , the count source becomes a watchdog timer l underflow sig- nal. the detection time is 131.072 ms at f(x in )=8 mhz. when this bit is 1 , the count source becomes f(x in )/16. in this case, the detection time is 512 s at f(x in )=8 mhz. this bit is cleared to 0 after reset. operation of stp instruction disable bit when the watchdog timer is in operation, the stp instruction can be disabled by bit 6 of the watchdog timer control register (ad- dress 0039 16 ). when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled, and an inter- nal reset occurs if the stp instruction is executed. once this bit is set to 1 , it cannot be changed to 0 by program. this bit is cleared to 0 after reset. fig. 66 block diagram of watchdog timer fig. 67 structure of watchdog timer control register watchdog timer control register (wdtcon: address 0039 16 , initial value: 3f 16 ) watchdog timer h (read only for high-order 6-bit) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 b7 b0 x in data bus 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) write "ff 16 " to the watchdog timer control register internal reset reset watchdog timer l (8) stp instruction write ff 16 to the watchdog timer control register
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 53 preliminar y notice: this is not a final specification. some parametric limits are subject to change. reset circuit the microcomputer is put into a reset status by holding the re- set pin at the l level for 2 s or more when the power source voltage is 2.2 to 5.5 v and x in is in stable oscillation. after that, this reset status is released by returning the reset pin to the h level. the program starts from the address having the contents of address fffd 16 as high-order address and the con- tents of address fffc 16 as low-order address. in the case of f( ) 6 mhz, the reset input voltage must be 0.9 v or less when the power source voltage passes 4.5 v. in the case of f( ) 4 mhz, the reset input voltage must be 0.8 v or less when the power source voltage passes 4.0 v. in the case of f( ) 2 mhz, the reset input voltage must be 0.48 v or less when the power source voltage passes 2.4 v. in the case of f( ) 1 mhz, the reset input voltage must be 0.44 v or less when the power source voltage passes 2.2 v. fig. 68 example of reset circuit fig. 69 timing diagram at reset data address 8-13 clock cycles reset address from the vector table 1 : a built-in ring oscillator applies about ring 2 mhz, 250 khz frequency clock at average of vcc = 5 v. 2 : the mark ? means that the address is changeable depending on the previous state. 3 : these are all internal signals except reset. notes ?? fffc fffd ad h ,ad l ??? ?? ad l ad h ??? clock from built-in ring oscillator ring reset reset out sync (note) 0.2 v cc 0 v 0 v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage vcc = 2.2 v
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 54 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 70 internal status of microcomputer at reset prescaler 1 (pre1) t i m e r 1 ( t 1 ) t i m e r x m o d e r e g i s t e r ( t x m ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r c o u n t s o u r c e s e t r e g i s t e r ( t c s s ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 s t s ) a - d c o n t r o l r e g i s t e r ( a d c o n ) m i s r g watchdog timer control register (wdtcon) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) processor status register p r o g r a m c o u n t e r ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) (22) (23) (29) (30) (31) ( 3 2 ) ( 3 3 ) ( 3 4 ) contents of address fffc 16 ( p c h ) (pc l ) ff 16 01 16 0 0 1 6 0 0 1 6 f f 1 6 f f 1 6 00 16 0028 16 0029 16 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 f 1 6 0030 16 0 0 3 4 1 6 0037 16 0039 16 0 0 3 a 1 6 003b 16 0 0 3 c 1 6 0 0 3 e 1 6 (ps) n o t e x : u n d e f i n e d c o n t e n t s o f a d d r e s s f f f d 1 6 0011 1111 0 0 1 6 0 0 1 6 0 0 1 6 1000 0000 x x x x x1xx p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p u l l - u p c o n t r o l r e g i s t e r ( p u l l ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 1 3 ) register contents 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 1 1 6 0 0 0 3 1 6 0 0 0 5 1 6 0 0 0 7 1 6 0 0 1 6 1 6 s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o 1 c o n ) u a r t 1 c o n t r o l r e g i s t e r ( u a r t 1 c o n ) (16) ( 1 7 ) serial i/o1 status register (sio1sts) ( 1 5 ) 001a 16 0 0 1 b 1 6 00 16 1110 0000 0 0 1 9 1 6 1000 0000 x x x 0 0000 a d d r e s s p o r t p 1 p 3 c o n t r o l r e g i s t e r ( p 1 p 3 c ) ( 1 4 ) 0 0 1 7 1 6 0 0 1 6 t i m e r a , b m o d e r e g i s t e r ( t a b m ) c a p t u r e / c o m p a r e p o r t r e g i s t e r ( c c p r ) t i m e r s o u r c e s e l e c t i o n r e g i s t e r ( t m s r ) 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0 0 1 6 00 16 00 16 0 0 2 0 1 6 0021 16 0022 16 0 0 1 6 0023 16 (35) (36) ( 3 7 ) ( 3 8 ) (39) (41) ( 4 2 ) (43) ( 4 4 ) ( 4 5 ) s e r i a l i / o 2 r e g i s t e r ( s i o 2 c o n ) 0031 16 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) 0 0 3 d 1 6 0 0 1 6 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) 0 0 3 f 1 6 0 0 1 6 ( 4 6 ) ( 4 7 ) (48) ( 4 9 ) u a r t 2 c o n t r o l r e g i s t e r ( u a r t 2 c o n ) ring oscillation division ratio selection register (rodr) 0 0 1 6 0 0 3 8 1 6 ( 4 0 ) 0000 0010 0001 0000 1110 0000 1000 0000 capture mode register (capm) compare output mode register (cmom) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ff 16 0024 16 f f 1 6 f f 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 ff 16 t i m e r a ( l o w - o r d e r ) ( t a l ) t i m e r a ( h i g h - o r d e r ) ( t a h ) t i m e r b ( l o w - o r d e r ) ( t b l ) timer b (high-order) (tbh) (24) capture/compare status register (ccsr) c o m p a r e i n t e r r u p t s o u r c e r e g i s t e r ( c i s r ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) i n t e r r u p t s o u r c e d i s c r i m i n a t i o n r e g i s t e r ( i n t d i s ) c o m p a r e r e g i s t e r ( l o w - o r d e r ) ( c m p l ) ( 6 ) ( 7 ) i n t e r r u p t s o u r c e s e t r e g i s t e r ( i n t s e t ) ( 5 ) 0 0 0 b 1 6 0 0 1 0 1 6 0 0 1 6 0 0 0 a 1 6 c o m p a r e r e g i s t e r ( h i g h - o r d e r ) ( c m p h ) c a p t u r e / c o m p a r e r e g i s t e r r / w p o i n t e r ( c c r p ) c a p t u r e s o f t w a r e t r i g g e r r e g i s t e r ( c s t r ) 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 6 0 0 1 6 0 0 1 4 1 6 0 0 1 5 1 6 c o m p a r e r e g i s t e r r e - l o a d r e g i s t e r ( c m p r ) p o r t p 0 p 3 d r i v e c a p a c i t y c o n t r o l r e g i s t e r ( d c c r ) 0 0 1 6 0 0 1 6
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 55 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 72 external circuit of ceramic resonator fig. 73 external circuit of rc oscillation fig. 74 external clock input circuit fig. 71 processing of x in and x out pins at ring oscillator op- eration clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out , and an rc oscillation circuit can be formed by connecting a resistor and a capacitor. use the circuit constants in accordance with the resonator manufacturer's recommended values. (1) ring oscillator operation when the mcu operates by the ring oscillator for the main clock, connect x in pin to v cc through a resistor and leave x out pin open. the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (2) ceramic resonator when the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in be- tween pins x in and x out . (3) rc oscillation when the rc oscillation is used for the main clock, connect the x in pin to the external circuit of resistor r and the capacitor c at the shortest distance and leave x out pin open. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. (4) external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. externally connect a damping resistor rd de- pending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manufacturer s recom- mended value because constants such as ca- pacitance depend on the resonator. note: connect the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is af- fected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. note: the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies and obtain the sufficient margin. note: x i n x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v c c v s s o p e n m 3 7 5 4 2 x i n x o u t c r m 3 7 5 4 2 x i n c out c i n x o u t m 3 7 5 4 2 r d x in x o u t m 3 7 5 4 2 o p e n r
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 56 preliminar y notice: this is not a final specification. some parametric limits are subject to change. (1) oscillation control ?stop mode when the stp instruction is executed, the internal clock stops at an h level and the x in oscillator stops. at this time, timer 1 is set to 01 16 and prescaler 1 is set to ff 16 when the oscillation sta- bilization time set bit after release of the stp instruction is 0 . on the other hand, timer 1 and prescaler 1 are not set when the above bit is 1 . accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(x in )/16 is forcibly connected to the input of prescaler 1. when an external interrupt is accepted, oscillation is restarted but the internal clock remains at h until timer 1 underflows. as soon as timer 1 underflows, the internal clock is supplied. this is because when a ceramic oscil- lator is used, some time is required until a start of oscillation. in case oscillation is restarted by reset, no wait time is generated. so apply an l level to the reset pin while oscillation becomes stable. ?wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to 1 before the stp or wit instruction is executed. notes on clock generating circuit for use with the oscillation stabilization set bit after release of the stp instruction set to 1 , set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is se- lected by setting bit 5 of the cpu mode register. double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu m37542rss is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. clock division ratio, x in oscillation control, ring oscillator control the state transition shown in fig. 79 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 79. ring oscillation division ratio at ring oscillator mode, division ratio of ring oscillator for cpu clock is selected by setting value of ring oscillation division ratio selection register. the division ratio of ring oscillation for cpu clock is selected from among 1/1, 1/2, 1/8, 1/128. the operation clock for the peripheral function block is not changed by setting value of this register. notes on ring oscillation division ratio when system is released from reset, r osc /8 (ring middle-speed mode) is selected for cpu clock. ? when state transition from the ceramic or rc oscillation to ring oscillator, r osc /8 (ring middle-speed mode) is selected for cpu clock. ? when the mcu operates by ring-oscillator for the main clock without external oscillation circuit, connect x in pin to v cc through a resistor and leave x out pin open. set 10010x00 2 (x = 0 or 1) to cpum. fig. 76 structure of ring oscillation division ratio selection register fig. 75 structure of cpu mode register r i n g o s c i l l a t i o n d i v i s i o n r a t i o s e l e c t i o n r e g i s t e r ( r o d r : a d d r e s s 0 0 3 7 1 6 , i n i t i a l v a l u e : 0 2 1 6 ) r i n g o s c i l l a t o r d i v i s i o n r a t i o b 1 b 0 00 : r i n g d o u b l e - s p e e d m o d e ( r o s c / 1 ) 01 : r i n g h i g h - s p e e d m o d e ( r o s c / 2 ) 10 : r i n g m i d d l e - s p e e d m o d e ( r o s c / 8 ) 11 : r i n g l o w - s p e e d m o d e ( r o s c / 1 2 8 ) n o t u s e d ( r e t u r n s 0 w h e n r e a d ) b 7 b 0 oscillation mode selection bit (note 1) 0 : ceramic oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( ) = f(x in )/2 (high-speed mode) 0 1 : f( ) = f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f( ) = f(x in ) (double-speed mode)(note 2) ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37542rss .) do not use these when an rc oscillation is selected.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 57 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 77 block diagram of internal clock generating circuit (for ceramic resonator) fig. 78 block diagram of internal clock generating circuit (for rc oscillation) s r q s r q 1/2 r s q rf 1/4 1/2 wit instruction stp instruction timing (internal clock) stp instruction interru p t re q uest reset interrupt disable flag l high-speed mode middle-speed mode prescaler 1 timer 1 main clock division ratio selection bits double-speed mode ring oscillator mode ring oscillator x out x in 1/16 main clock division ratio selection bit middle-, high-, low-speed mode ring oscillator mode 1/4 1/2 ring oscillator division ratio selection bits r osc /128 r osc /8 r osc /2 r osc /1 s r q s r q 1/2 r s q 1/4 1/2 wit instruction stp instruction timing (internal clock) stp instruction interru p t re q uest reset interrupt disable flag l high-speed mode middle-speed mode prescaler 1 timer 1 main clock division ratio selection bits double-speed mode ring x out x in delay main clock division ratio selection bit middle-, high-, low-speed mode ring oscillator mode reset ring oscillator mode ring oscillator division ratio selection bits ring oscillator 1/16 1/4 1/2 r osc /128 r osc /8 r osc /2 r osc /1
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 58 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 79 state transition stp mode f(x in ) oscillation: stop ring oscillator: stop wait mode 1 wait mode 2 wait mode 3 wait mode 3 operation clock source: ring oscillator (note 2) operation clock source: f(x in ) (note 1) notes on switch of clock (1) in operation clock = f(x in ), the following can be selected for the cpu clock division ratio. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode, only at a ceramic oscillation) (2) in operation clock = ring oscillator, the following can be selected for the cpu clock division ratio. r osc /1 (ring double-speed mode) r osc /2 (ring high-speed mode) r osc /8 (ring middle-speed mode) r osc /128 (ring low-speed mode) (3) after system is released from reset, and state transition of state 2 state 3 and state transition of state 2 state 3 , r osc /8 (ring middle-speed mode) is selected for cpu clock. (4) executing the state transition state 3 to 2 or state 3 to 3 after stabilizing x in oscillation. (5) when the state 2 state 3 state 4 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. 1. cpum 76 = 10 2 (state 2 state 3) 2. nop instruction double-speed mode: nop ? 3 high-speed mode: nop ? 1 middle-speed mode: nop ? 0 3. cpu 4 = 1 2 (state 3 state 4) (6) when the state 3 state 2 state 1 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. 1. cpum 76 = 00 2 or 01 2 or 11 2 (state 3 state 2) 2. nop instruction tbd 3. cpu 3 = 1 2 (state 2 state 1) wait mode 4 state 4 reset state f(x in ) oscillation: enabled ring oscillator: enabled state 3 state 3 wait mode 2 state 2 state 2 state 1 interrupt stp instruction interrupt wit instruction interrupt cpum 3 =0 2 cpum 3 =1 2 cpum 76 =10 2 ( note 3 ) cpum 76 =00 2 01 2 11 2 ( note 4 ) cpum 76 =10 2 ( note 3 ) cpum 76 =00 2 01 2 11 2 misrg 1 =1 2 misrg 1 =0 2 misrg 1 =1 2 ( note 4 ) misrg 1 =0 2 reset released ( note 3 ) cpum 4 =0 2 cpum 4 =1 2 interrupt wit instruction wit instruction interrupt wit instruction interrupt wit instruction interrupt wit instruction stp instruction stp instruction stp instruction interrupt interrupt interrupt f(x in ) oscillation: enabled ring oscillator: stop f(x in ) oscillation: enabled ring oscillator: enabled f(x in ) oscillation: enabled ring oscillator: enabled f(x in ) oscillation: enabled ring oscillator: enabled f(x in ) oscillation: enabled ring oscillator: enabled oscillation stop detection circuit valid f(x in ) oscillation: stop ring oscillator: enabled
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 59 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 80 structure of misrg the oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or rc oscillation circuit stops by dis- connection. to use this circuit, set a built-in ring oscillator to be in active. the oscillation stop detection circuit is in active to set 1 to the ceramic or rc oscillation stop detection function active bit. when the oscillation stop detection circuit is in active, ceramic or rc os- cillation is watched by the built-in ring oscillator. when stop of ceramic or rc oscillation is detected, the oscillation stop detection status bit is set to 1 . while 1 is set to the oscillation stop reset bit, internal reset occurs when oscillation stop is detected. the external reset and the oscillation stop reset can be discrimi- nated by reading the oscillation stop detection status bit. the oscillation stop detection status bit retains 1 , not initialized, when the oscillation stop reset occurs. the oscillation stop detec- tion status bit is initialized to 0 when the external reset occurs. accordingly, reset by oscillation stop can be confirmed by using this bit. when the oscillation stop reset bit is set to 0 , internal reset does not occur. if the ceramic or rc oscillation is selected for the cpu clock, mcu will be locked when the ceramic or rc os- cillation is stopped. so when the ceramic or rc oscillation is selected for the main clock, set the oscillation stop reset bit to 1 . (state 2 a of fig. 81) ceramic or rc oscillation stop detection function active bit is not cleared by the oscillation stop internal reset. accordingly, the oscillation stop detection circuit is in active when system is re- leased from internal reset cause of oscillation stop detection. oscillation stop detection status bit is initialized by the following operation. (1) external reset (2) write 0 data to the ceramic or rc oscillation stop detection function active bit. the oscillation stop detection circuit is not included in the emu- lator mcu m37542rss . misrg(address 0038 16 , initial value: 00 16 ) b 7 b 0 o s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e s t p i n s t r u c t i o n 0 : s e t 0 1 1 6 i n t i m e r 1 , a n d f f 1 6 i n p r e s c a l e r 1 a u t o m a t i c a l l y 1 : n o t s e t a u t o m a t i c a l l y c e r a m i c o r r c o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n a c t i v e b i t 0 : d e t e c t i o n f u n c t i o n i n a c t i v e 1 : d e t e c t i o n f u n c t i o n a c t i v e o s c i l l a t i o n s t o p r e s e t b i t 0 : o s c i l l a t i o n s t o p r e s e t d i s a b l e d 1 : o s c i l l a t i o n s t o p r e s e t e n a b l e d o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t 0 : o s c i l l a t i o n s t o p n o t d e t e c t e d 1 : o s c i l l a t i o n s t o p d e t e c t e d n o t u s e d ( r e t u r n 0 w h e n r e a d ) r e s e r v e d b i t s ( d o n o t w r i t e 1 t o t h e s e b i t s )
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 60 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 81 state transition operation clock source: ring oscillator (note 2) operation clock source: f(x in ) (note 1) notes on switch of clock (1) in operation clock = f(x in ), the following can be selected for the cpu clock division ratio. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode, only at a ceramic oscillation) (2) in operation clock = ring oscillator, the following can be selected for the cpu clock division ratio. r osc /1 (ring double-speed mode) r osc /2 (ring high-speed mode) r osc /8 (ring middle-speed mode) r osc /128 (ring low-speed mode) (3) executing the state transition state 3 to 2 or state 3 to 3 after stabilizing x in oscillation. (4) after system is released from reset, and state transition of state 2 state 3 and state transition of state 2 b state 3 b, r osc /8 (ring middle-speed mode) is selected for cpu clock. (5) state 2 a is prohibitive state. because when oscillation stop reset bit is set to 0 , internal reset does not occur. so if clock stop is detected at state 2 a , mcu will be locked. (6) stp instruction cannot be used when oscillation stop detection circuit is in active. reset state 2 f(x in ) oscillation: enabled ring oscillator: enabled reset state 1 f(x in ) oscillation: enabled ring oscillator: enabled oscillation stop detection circuit is in active. (note 6) hardware reset (external reset ) misrg 3 is cleared to 0 . misrg 2 =1 2 misrg 2 =0 2 misrg 2 =1 2 misrg 2 =0 2 misrg 1 =1 2 misrg 1 =0 2 (misrg 3 is cleared to 0 .) misrg 1 =1 2 ( note 3 ) misrg 1 =0 2 (misrg 3 is cleared to 0 .) state 3 state 2 f(x in ) oscillation: enabled ring oscillator: enabled f(x in ) oscillation: enabled ring oscillator: enabled state 3 state 2 f(x in ) oscillation: enabled ring oscillator: enabled state 2 a (note 5) oscillation stop reset disabled when oscillation stop is detected; misrg 3 is set to 1 . internal reset does not occur. prohibitive state muc will be locked when ceramic or rc oscillation is stopped. state 3 a oscillation stop reset disabled when oscillation stop is detected; misrg 3 is set to 1 . internal reset does not occur. oscillation stop reset enabled when oscillation stop is detected; misrg 3 is set to 1 . internal reset occurs. oscillation stop reset enabled when oscillation stop is detected; misrg 3 is set to 1 . internal reset occurs. state 3 c release from internal reset misrg 3 is set to 1 . oscillation status can be confirmed by reading misrg 3 . f(x in ) oscillation: enabled ring oscillator: enabled state 3 b state 2 b cpum 76 =10 2 ( note 4 ) cpum 76 =00 2 01 2 11 2 ( note 3 ) cpum 76 =10 2 cpum 76 =00 2 01 2 11 2 cpum 76 =10 2 ( note 4 ) cpum 76 =00 2 01 2 11 2 reset released ( note 4 ) reset released ( note 4 ) oscillation stop is detected (internal reset)
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 61 preliminar y notice: this is not a final specification. some parametric limits are subject to change. notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is ?? after reset, initialize flags which affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effect on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruction before executing the bbc or bbs instruction. decimal calculations ?for calculations in decimal notation, set the decimal mode flag d to ?? then execute the adc instruction or sbc instruction. in this case, execute sec instruction, clc instruction or cld in- struction after executing one instruction before the adc instruction or sbc instruction. ?in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. ports ?the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is ?? addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta in- struction, etc. a-d conversion do not execute the stp instruction during a-d conversion. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles men- tioned in the machine-language instruction table. the frequency of the internal clock is the same as that of the x in in double-speed mode, twice the x in cycle in high-speed mode and 8 times the x in cycle in middle-speed mode. cpu mode register the oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is ex- cluded.) when a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. do not use it when an rc oscillation is selected. state transition do not stop the clock selected as the operation clock because of setting of cm3, 4. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 f to 0.1 f is recommended. notes on peripheral functions interrupt (1) when setting the followings, the interrupt request bit may be set to ?? ?hen setting external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 002b 16 ) capture mode register (address 0020 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit, trigger mode bit). ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). (2) use a ldm instruction to cleare an interrupt discrimination bit. ldm #$0n, $0bn set the following values to ? ?? an interrupt discrimination bit to clear ?? other interrupt discrimination bits ex.) when a key-on wakeup interrupt discrimination bit is cleared; ldm #00001110b and $0b.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 62 preliminar y notice: this is not a final specification. some parametric limits are subject to change. timers ?when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). ?when a count source of timer x, timer y or timer z is switched, stop a count of timer x. timer x (1) cntr 0 interrupt active edge selection-1 cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. (2) cntr 0 interrupt active edge selection-2 according to the setting value of cntr 0 active edge switch bit, the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the active edge switch bit. ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). notes on timer a, b (1) setting of timer value when ?: write to only latch?is set to the timer a (b) write control bit, written data to timer register is set to only latch even if timer is stopped. accordingly, in order to set the initial value for timer when it is stopped, set ?: write to latch and timer simultaneously?to timer a (b) write control bit. (2) read/write of timer a stop timer a to read/write its data when the system is in the follow- ing state; ?cpu operation clock source: x in oscillation ?timer a count source: ring oscillator output (3) read/write of timer b stop timer b to read/write its data when the system is in the fol- lowing state; ?cpu operation clock source: x in oscillation ?timer b count source: timer a underflow ?timer a count source: ring oscillator output notes on output compare ?when the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously. ?do not write the same data to both of compare latch x0 and x1. ?when setting value of the compare latch is larger than timer set- ting value, compare match signal is not generated. accordingly, the output waveform is fixed to ??or ??level. however, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. accordingly, compare match interrupt occurs. ?when the compare x trigger enable bit is cleared to ??(dis- abled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to ??or ? level. however, in this case, the compare match signal is generated. accordingly, compare match interrupt occurs. notes on input capture ?if the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. accordingly, some countermeasure by software is recommended, for example comparing the values that twice of read. ?when the ring-oscillator is selected for timer a count source, timer a cannot be used for the capture source timer. timer b cannot be used for the capture source timer when the system is in the following state; ?cpu operation clock source: x in oscillation ?timer b count source: timer a underflow ?timer a count source: ring oscillator output ?when writing ??to capture latch x0 (x1) software trigger bit of capture latch x0 and x1 at the same time, or external trigger and software trigger occur simultaneously, the set value of capture x status bit is undefined. ?when setting the interrupt active edge selection bit and noise fil- ter clock selection bit of external interrupt cap 0 , cap 1 , the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge selection bit or noise filter clock selection bit. ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). ?the capture interrupt cannot be used as the interrupt for return from stop mode. even when the valid edge of the capture inter- rupt is input at stop mode, system retains the stop mode. then, system returns from stop mode by other external interrupts, the capture interrupt is accepted. in this case, after system returns from stop mode, the interrupt request bit of the corresponding capture interrupt is set to ??
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 63 preliminar y notice: this is not a final specification. some parametric limits are subject to change. notes on serial i/o1 ?serial i/o interrupt when setting the transmit enable bit to ?? the serial i/o transmit interrupt request bit is automatically set to ?? when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to ??(disabled). ? set the transmit enable bit to ?? ? set the serial i/o transmit interrupt request bit to ??after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to ??(enabled). ?i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit ??: clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit ??: p1 2 pin turns into an output pin of a synchronous clock. ??: p1 2 pin turns into an input pin of a synchronous clock. setup of a s rdy1 output enable bit (srdy) ??: p1 3 pin can be used as a normal i/o pin. ??: p1 3 pin turns into a s rdy1 output pin. (2) serial i/o1 mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit ?? p1 2 pin can be used as a normal i/o pin. ?? p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. ?bus collision detection bus collision detection can be used when sio1 is operating at full- duplex communication. when sio1 is operating at half-duplex communication, set bus collision detection interrupt to be dis- abled. notes on serial i/o2 ?serial i/o interrupt when setting the transmit enable bit to ?? the serial i/o transmit interrupt request bit is automatically set to ?? when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to ??(disabled). ? set the transmit enable bit to ?? ? set the serial i/o transmit interrupt request bit to ??after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to ??(enabled). ?i/o pin function when serial i/o2 is enabled. the functions of p0 6 and p0 7 are switched with the setting values of a serial i/o2 mode selection bit and a serial i/o2 synchronous clock selection bit as follows. (1) serial i/o2 mode selection bit ??: clock synchronous type serial i/o is selected. setup of a serial i/o2 synchronous clock selection bit ??: p0 6 pin turns into an output pin of a synchronous clock. ??: p0 6 pin turns into an input pin of a synchronous clock. setup of a s rdy2 output enable bit (srdy) ??: p0 7 pin can be used as a normal i/o pin. ??: p0 7 pin turns into a s rdy2 output pin. (2) serial i/o2 mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o2 synchronous clock selection bit ?? p0 6 pin can be used as a normal i/o pin. ?? p0 6 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p0 7 pin. it can be used as a normal i/o pin. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is 500khz or more during a-d conversion.
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 64 preliminar y notice: this is not a final specification. some parametric limits are subject to change. notes on clock generating circuit for use with the oscillation stabilization set bit after release of the stp instruction set to ?? set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. ?switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is se- lected by setting bit 5 of the cpu mode register. ?double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. ?cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu ?37542rss?is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. ?clock division ratio, x in oscillation control, ring oscillator control the state transition shown in fig. 79 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 79. notes on ring oscillation division ratio ?when system is released from reset, r osc /8 (ring middle-speed mode) is selected for cpu clock. ? when state transition from the ceramic or rc oscillation to ring oscil- lator, r osc /8 (ring middle-speed mode) is selected for cpu clock. ? when the mcu operates by ring-oscillator for the main clock without external oscillation circuit, connect x in pin to v cc through a resistor and leave x out pin open. set ?0010x00 2 ?(x = 0 or 1) to cpum. notes on oscillation stop detection circuit ?when the oscillation stop reset bit is set to ?? internal reset does not occur. if the ceramic or rc oscillation is selected for the cpu clock, mcu will be locked when the ceramic or rc os- cillation is stopped. so when the ceramic or rc oscillation is selected for the main clock, set the oscillation stop reset bit to ?? (state 2? of fig. 81) ? ceramic or rc oscillation stop detection function active bit is not cleared by the oscillation stop internal reset. accordingly, the oscillation stop detection circuit is in active when system is re- leased from internal reset cause of oscillation stop detection. ? oscillation stop detection status bit is initialized by the following operation. (1) external reset (2) write ??data to the ceramic or rc oscillation stop detection function active bit. ? the oscillation stop detection circuit is not included in the emu- lator mcu ?37542rss? data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form * 2.mark specification form * 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. * for the mask rom confirmation, rom programming order con- firmation and the mark specifications, refer to the ?itsubishi mcu technical information?homepage (http://www.infomicom.maec.co.jp/indexe.htm).
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 65 preliminar y notice: this is not a final specification. some parametric limits are subject to change. package outline ssop36-p-450-0.80 weight(g) e jedec code 0.53 eiaj package code lead material alloy 42 36p2r-a plastic 36pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 e e .35 0 .05 0 .13 0 .8 14 .2 8 e .63 11 .3 0 e e e .27 1 e e .0 2 .4 0 .15 0 .0 15 .4 8 .8 0 .93 11 .5 0 .765 1 e .43 11 e e .4 2 e .5 0 .2 0 .2 15 .6 8 e .23 12 .7 0 e .15 0 e b 2 e.5 0e e 0
single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers 66 preliminar y notice: this is not a final specification. some parametric limits are subject to change. sdip32-p-400-1.78 weight(g) e 2.2 jedec code eiaj package code lead material alloy 42/cu alloy 32p4b plastic 32pin 400mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ee e 3.8 e 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 e 1.778 e e 10.16 e 3.0 ee 0
? 2002mitsubishi electric corp. new publication, effective nov. 2002. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan single-chip 8-bit cmos microcomputer 7542 group mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change.
revision history 7542 group data sheet rev. date description page summary (1/1) 1.0 11/27/02 first edition

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