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| september 1997 1-9 ? 1997 actel corporation integrator series fpgas C 1200xl and 3200dx familes features high capacity ? 2,500 to 40,000 logic gates ? up to 4 kbits configurable dual-port sram ? fast wide-decode circuitry ? up to 288 user-programmable i/o pins high performance ? 225 mhz performance ? 5 ns dual-port sram access ? 100 mhz fifos ? 7.5 ns 35-bit address decode ease-of-integration ? synthesis-friendly architecture supports asic design methodologies ? 95C100% device utilization using automatic place and route tools ? deterministic, user-controllable timing via directtime software tools ? supported by actel designer series development system with interfaces to popular design environments such as cadence, escalade, exemplar, ist, mentor graphics, synopsys and viewlogic ? jtag 1149.1 boundary scan testing general description actels integrator series fpgas are the first programmable logic devices optimized for high-speed system logic integration. based on actel's proprietary plice antifuse technology and state-of-the-art 0.6-micron double metal cmos process, the integrator series devices offer a fine-grained, register-rich architecture with the industrys fastest embedded dual-port sram and wide decode circuitry. 3200dx and 1200xl fpgas were designed to integrate system logic which is typically implemented in multiple cplds, pals and fpgas. these devices provide the features and performance required for todays complex, high-speed digital logic systems. the 3200dx family offers the industrys fastest dual-port sram for implementing fast fifos, lifos and temporary data storage. the large number of storage elements can efficiently address applications requiring wide datapath manipulation and transformation functions such as telecommunications, networking and dsp. integrator series product profile device a1225xl a1240xl a3265dx a1280xl a32100dx a32140dx a32200dx a32300dx a32400dx capacity logic gates 1 sram bits 2,500 n/a 4,000 n/a 6,500 n/a 8,000 n/a 10,000 2,048 14,000 n/a 20,000 2,560 30,000 3,072 40,000 4,096 logic modules sequential combinatorial decode 231 220 n/a 348 336 n/a 510 475 20 624 608 n/a 700 662 20 954 912 24 1,230 1,184 24 1,888 1,833 28 2,526 2,466 28 sram modules (64x4 or 32x8) na na na na 8 na 10 12 16 dedicated flip-flops 231 348 510 624 700 954 1,230 1,888 2,526 clocks 222262666 user i/o (maximum) 83 104 126 140 152 176 202 250 288 jtag no no no no yes yes yes yes yes packages pl84 pq100 vq100 pg100 pl84 pq100 pq144 tq176 pg132 pl84 pq100 pq160 tq176 pl84 pq160 pq208 tq176 pg176 cq172 pl84 pq160 pq208 tq176 cq84 pl84 pq160 pq208 tq176 cq256 pq208 rq208 rq240 cq208 cq256 rq208 rq240 cq256 rq240 note 1: logic gate capacity does not include sram bits as logic.
1- 10 ordering information application (t emper ature range) c = commercial (0 to +70 c) i = industr ial (C40 to +85 c) m = militar y (C55 to +125 c) b = mil-std-883 p ac kage t ype cq = cer amic quad flatpac k pg = cer amic pin gr id arr a y pl = plastic leaded chip carr ier pq = plastic quad flatpac k rq = plastic p o w er quad flatpac k tq = thin (1.4 mm) quad flatpac k vq = v er y thin (1.0 mm) quad flatpac k speed gr ade blank = standard speed 1 = appro ximately 15% f aster than standard 2 = appro ximately 25% f aster than standard 3 = appro ximately 35% f aster than standard f = appro ximately 30% slo w er than standard p ar t number a1225 = 2500 gates a1240 = 4000 gates a3265 = 6500 gates a1280 = 8000 gates a32100 = 10000 gates a32140 = 14000 gates a32200 = 20000 gates a32300 = 30000 gates a32400 = 40000 gates die re vision xl = 1200xl f amily dx = 3200dx f amily p ac kage lead count a1225 C pq 100 c xl oper ating v oltage v = 3.3 v olt blank = 5.0 v olt v 1- 11 integrator series fpgas C 1200xl and 3200dx familes product plan speed grade application Cf std C1* C2* C3 c i m b a1225xl de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 4 4 100-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 100-pin v er y thin plastic quad flatpac k (vqfp) 4 4 4 4 4 100-pin cer amic pin gr id arr a y (cpga) 4 4 4 4 a1225xl v de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 100-pin v er y thin plastic quad flatpac k (vqfp) 4 4 4 a1240xl de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 4 4 100-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 132-pin cer amic pin gr id arr a y (cpga) 4 4 4 4 144-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 a1240xl v de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 a3265dx de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 4 4 100-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 160-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 a3265dxv de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 a1280xl de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 4 4 160-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 172-pin cer amic quad flatpac k (cqfp) 4 4 4 4 p p 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 176-pin cer amic pin gr id arr a y (cpga) 4 4 4 4 p p 208-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 a1280xl v de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 applications: c = commercial availability: 4 = available * speed grade: C1 = approx. 15% faster than standard i = industrial p = planned C2 = approx. 25% faster than standard m = military = not planned C3 = approx. 35% faster than standard b = mil-std-883 Cf = approx. 30% slower than standard 1- 12 a32100dx de vice 84-pin cer amic quad flatpac k (cqfp) p p p p p 84-pin plastic leaded chip carr ier (plcc) 4 4 4 4 4 4 4 160-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 208-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 a32100dxv de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 a32140dx de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 4 4 4 4 160-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 208-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 256-pin cer amic quad flatpac k (cqfp) p p p p p a32140dxv de vice 84-pin plastic leaded chip carr ier (plcc) 4 4 4 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 a32200dx de vice 208-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 208-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 4 4 4 4 240-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 4 4 4 4 208-pin cer amic quad flatpac k (cqfp) p p p p p 256-pin cer amic quad flatpac k (cqfp) p p p p p a32200dxv de vice 208-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 240-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 4 4 4 4 a32300dx de vice 208-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 4 4 4 4 240-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 4 4 4 4 256-pin cer amic quad flatpac k (cqfp) p p p p p a32300dxv de vice 208-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 240-pin plastic p o w er quad flatpac k (rqfp) 4 4 4 a32400dx de vice 240-pin plastic p o w er quad flatpac k (rqfp) p p p p p p p product plan (continued) speed grade application Cf std C1* C2* C3 c i m b applications: c = commercial availability: 4 = available * speed grade: C1 = approx. 15% faster than standard i = industrial p = planned C2 = approx. 25% faster than standard m = military = not planned C3 = approx. 35% faster than standard b = mil-std-883 Cf = approx. 30% slower than standard 1- 13 integrator series fpgas C 1200xl and 3200dx familes integrator series devices are supported by actels designer series development software which provides a seamless integration into any asic design flow. the designer series development tools offer automatic placement and routing (even with pre-assigned pins), static timing analysis, user programming, and debug and diagnostic probe capabilities. in addition, the directtime tool provides deterministic as well as controllable timing. directtime allows the designer to specify the performance requirements of individual paths and system clock(s). using these specifications, the software will automatically optimize the placement and routing of the logic to meet these constraints. included with the designer series tools is actels actgen? macro builder. actgen allows the designer to quickly build fast, efficient logic functions such as counters, adders, fifos, and ram. the designer series tools provide designers the capability to move up to high-level description languages, such as vhdl and verilog, or use schematic design entry with interfaces to most eda tools. designer series is supported on the following development platforms: 486 and pentium pc, sun? and hp? workstations. the software provides cae interfaces to cadence, mentor graphics?, escalade, orcad? and viewlogic? design environments. additional development tools are supported through actel's industry alliance program, including data i/o (abel fpga) and minc. actels fpgas are an ideal solution for shortening the system design and development cycle and offers a cost-effective alternative for low volume production runs. the 3200dx and 1200xl devices are an excellent choice for integrating logic that is currently implemented in multiple pals, cplds and fpgas. some example applications include high-speed controllers and address decoding, peripheral bus interfaces, dsp, and co-processor functions. plastic device resources user i/os de vice plcc 84-pin vqfp 100-pin pqfp 100-pin pqfp 144-pin pqfp 160-pin pqfp 208-pin rqfp 240-pin tqfp 176-pin a1225xl 72 83 83 a1240xl 72 83 104 103 a3265dx 72 83 125 126 a1280xl 72 125 140 140 a32100dx 72 125 152 142 a32140dx 72 125 176 150 a32200dx 176* 202 a32300dx 176 202 a32400dx 202 package definitions (consult your local actel sales representative for product availability.) plcc = plastic leaded chip carrier, pqfp = plastic quad flat pack, tqfp = thin quad flat pack, bga = ball grid array, vqfp = ve ry thin quad flat pack, rqfp = plastic power quad flat pack ? also available in rqfp 208-pin. hermetic device resources user i/os de vice cpga 176-pin cqfp 84-pin cqfp 172-pin cqfp 208-pin cqfp 256-pin a1280xl 140 140 a32100dx 60 a32140dx 176 a32200dx 176 202 a32300dx 212 package definitions (consult your local actel sales representative for product availability.) cpga = ceramic pin grid array, cqfp = ceramic quad flat pack 1- 14 pin description clka, clkb clock a and clock b (input) ttl clock inputs for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd gr ound (input) input low supply voltage. i/o input/output (input, output) i/o pin functions as an input, output, three-state or bi-directional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are automatically driven low by the designer series software. mode mode (input) the mode pin controls the use of multi-function pins (dclk, pra, prb, sdi, tdo). when the mode pin is high, the special functions are active. to provide actionprobe capability, the mode pin should be terminated to gnd through a 10k resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra/i/o pr obe a (output) the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb/i/o pr obe b (output) the probe b pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. the pins probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. qclka/b,c,d quadrant clock (input/output) these four pins are the quadrant clock inputs. when not used as a register control signal, these pins can function as general purpose i/o. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. tck t est clock clock signal to shift the jtag data into the device. this pin functions as an i/o when the jtag fuse is not programmed. tdi t est data in serial data input for jtag instructions and data. data is shifted in on the rising edge of tclk. this pin functions as an i/o when the jtag fuse is not programmed. tdo t est data out serial data output for jtag instructions and test data. this pin functions as an i/o when the jtag fuse is not programmed. tms t est mode select serial data input for jtag test mode. data is shifted in on the rising edge of tclk. this pin functions as an i/o when the jtag fuse is not programmed. v cc supply v oltage (input) input high supply voltage. note: tck, tdi, tdo, tms are only available on devices containing jtag circuitry. integrator series architectural overview the 1200xl and 3200dx architecture is composed of fine-grained building blocks which produce fast, efficient logic designs. all devices within the integrator series are composed of logic modules, routing resources, clock networks, and i/o modules which are the building blocks to design fast logic designs. in addition, a subset of devices contain embedded dual-port sram and wide decode modules. the dual-port sram modules are optimized for high-speed data path functions such as fifos, lifos, and scratchpad memory. integrator series product profile on page 1-9 lists the specific logic resources contained within each device. 1- 15 integrator series fpgas C 1200xl and 3200dx familes logic modules 3200dx and 1200xl devices contain three types of logic modules: combinatorial (c-modules), sequential (s-modules), and decode (d-modules). 1200xl devices contain only the c-module and s-module, while the 3200dx devices contain d-modules and dual-port sram modules; in addition to the s-module and c-module. the c-module is shown in figure 1 and implements the following function: y=!s1*!s0*d00+!s1*s0*d01+s1*!s0*d01+s1*s0*d11 where: s0=a0*b0 s1=a1+b1 the s-module shown in figure 2 is designed to implement high-speed sequential functions within a single logic module. the s-module implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d flip-flop or a transparent latch. to increase flexibility, the s-module register can be by-passed so that it implements purely combinatorial logic. figure 1 ? c-module implementation d00 d01 d10 d11 s0 s1 y a0 b0 a1 b1 figure 2 ? s-module implementation d11 d01 d00 d10 y out s1 s0 up to 7-input function plus d-type ? ip-? op with clear d11 d01 d00 d10 y s1 s0 up to 7-input function plus latch y up to 4-input function plus latch with clear d11 d01 d00 d10 y out s1 s0 up to 8-input function (same as c-module) s d1 d0 clr d q out clr d q out ga te d q ga te 1- 16 3200dx devices contain a third type of logic module, d-modules, which are arranged around the periphery of device. d-modules contain wide decode circuitry which provides a fast, wide-input and function similar to that found in product term architectures ( figure 3 ). the d-module allows 3200dx devices to perform wide decode functions at speeds comparable cplds and pal devices. the output of the d-module has a programmable inverter for active high or low assertion. the d-module output is hardwired to an output pin or can be fed back into the array to be incorporated into other logic. dual-port sram modules several 3200dx devices contain dual-port sram modules that have been optimized for synchronous or asynchronous applications. the sram modules are arranged in 256 bit blocks which can be configured as 32 x 8 or 64 x 4 (refer to integrator series product profile on page 1-9 for the number of sram blocks within a particular device). sram modules can be cascaded together to form memory spaces of user-definable width and depth. a block diagram of the 3200dx dual-port sram block is shown in figure 4 . the 3200dx sram modules are true dual-port structures containing independent read and write ports. each sram module contains six bits of read and write addressing (rdad[5:0] and wrad[5:0] respectively) for 64x4 bit blocks. when configured in byte mode, the highest order address bits (rdad5 and wrad5) are not used. the read and write ports of the sram block contain independent clocks (rclk and wclk) with programmable polarities offering active high or low implementation. the sram block contains eight data inputs (wd[7:0]) and eight outputs (rd[7:0]) which are connected to segmented vertical routing tracks. the 3200dx dual-port sram blocks are ideal for high-speed buffered applications requiring fast fifo and lifo queues. actels actgen macro builder provides the capability to quickly design memory functions, such as fifos, lifos, and figure 3 ? d-module implementation 7 inputs hardwire to i/o f eedbac k to arr a y prog r ammab le in v er ter figure 4 ? 3200dx dual-port sram block sram module 32 x 8 or 64 x 4 (256 bits) read p or t logic wr ite p or t logic rd[7:0] routing t r ac ks latches read logic [5:0] rd ad[5:0] ren rclk latches wd[7:0] latches wrad[5:0] wr ite logic mode blken wen wclk [5:0] [7:0] 1- 17 integrator series fpgas C 1200xl and 3200dx familes ram arrays. additionally, unused sram blocks need not be wasted since they can be used to implement registers for other logic within the design. i/o modules the i/o modules provide the interface between the device pins and the logic array. figure 5 is a block diagram of the i/o module. a variety of user functions, determined by a library macro selection, can be implemented in the module (refer to the macro library guide for more information). i/o modules contain a tri-state buffer, input and output latches which can be configured for input, output, or bi-directional pins ( figure 5 ). the integrator series devices contain flexible i/o structures in that each output pin has a dedicated output enable control. the i/o module can be used to latch input and/or output data, providing a fast setup time. in addition, the actel designer software tools can build a d flip-flop, using a c-module, to register input and/or output signals. actels designer series development tools provide a design library of i/o macros. the i/o macro library provides macrofunctions which can implement all i/o configurations supported by the integrator series fpgas. routing structure the integrator series architecture uses vertical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are metal interconnects that may either be of continuous length or broken into pieces called segments. varying segment lengths allows the interconnect of over 90% of design tracks to occur with only two antifuse connections. segments can be joined together at the ends, using antifuses, to increase their lengths up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal channels are located between the rows of modules and are composed of several routing tracks. the horizontal routing tracks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. any segment that spans more than one-third the row length is considered a long horizontal segment. a typical channel is shown in figure 6 . non-dedicated horizontal routing tracks are used to route signal nets. dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. vertical routing another set of routing tracks run vertically through the module. vertical tracks are of three types: input, output, and long. vertical tracks are also divided into one or more segments. each segment in an input track is dedicated to the input of a particular module. each segment in an output track is dedicated to the output of a particular module. long segments are uncommitted and can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. lvts contain either one or two segments. an example of vertical routing tracks and segments is shown in figure 6 . antifuse structures an antifuse is a normally open structure as opposed to the normally closed fuse structure used in proms or pals. the use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. the structure is highly testable figure 5 ? i/o module g/clk* q d en p ad * can be con? gured as a latch or d flip-flop f rom arr a y t o arr a y (using c-module) g/clk* q d figure 6 ? routing structure v er tical routing tr ac ks antifuses logic segmented hor iz ontal routing tr ac ks modules 1- 18 because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed as well as isolate individual circuit structures to be tested. this can be done both before and after programming. for example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. clock networks two low-skew, high fanout clock distribution networks are provided in each 3200dx device. these networks are referred to as clk0 and clk1. each network has a clock module (clkmod) that selects the source of the clock signal and may be driven as follows: 1. externally from the clka pad 2. externally from the clkb pad 3. internally from the clkina input 4. internally from the clkinb input the clock modules are located in the top row of i/o modules. clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. the user controls the clock module by selecting one of two clock macros from the macro library. the macro clkbuf is used to connect one of the two external clock pins to a clock network, and the macro clkint is used to connect an internally generated clock signal to a clock network. since both clock networks are identical, the user does not care whether clk0 or clk1 is being used. the clock input pads may also be used as normal i/os, bypassing the clock networks (see figure 7 ). the 3200dx devices which contain sram modules (all except a3265dx and a32140dx) have four additional register control resources, called quadrant clock networks ( figure 8 ). each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. quadrant clock signals can originate from specific i/o pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. test circuitry both 3200dx and 1200xl devices provide the means to test and debug a design once it is programmed into a device. 3200dx and 1200xl devices contain actels actionprobe? test facility. once a device has been programmed, the actionprobe test facility allows the designer to probe any internal node during device operation to aid in debugging a design. in addition, 3200dx devices contain jtag 1149.1 boundary scan test. jtag boundary scan testing (bst) device pin spacing is decreasing with the advent of fine-pitch packages such as tqfp and bga packages and manufacturers are routinely implementing surface-mount technology with multi-layer pc boards. boundary scan is becoming an attractive tool to help systems manufacturers test their pc boards. the joint test action group (jtag) developed the ieee boundary scan standard 1149.1 to facilitate board-level testing during manufacturing. ieee standard 1149.1 defines a 4-pin test access port (tap) interface for testing integrated circuits in a system. the 3200dx family provides four jtag bst pins: test data in (tdi), test data out (tdo), test clock (tclk) and test mode select (tms). devices are configured in a jtag chain where bst data can be transmitted serially between devices via tdo to tdi interconnections. the tms and tclk signals are shared between all devices in the jtag chain so that all components operate in the same state. the 3200dx family implements a subset of the ieee 1149.1 boundary scan test (bst) instruction in addition to a private instruction to allow the use of actels actionprobe facility with jtag bst. refer to the ieee 1149.1 specification for detailed information regarding jtag testing. jtag architecture the 3200dx jtag bst circuitry consist of a test access port (tap) controller, jtag instruction register, jprobe register, bypass register and boundary scan register. figure 9 is a block diagram of the 3200dx jtag circuitry. figure 7 ? clock networks clkb clka fr om p ads clock drivers clkmod clkinb clkina s0 s1 internal signal clk o(17) clk o(16) clk o(15) clk o(2) clk o(1) clock tra cks 1- 19 integrator series fpgas C 1200xl and 3200dx familes figure 8 ? quadrant clock network figure 9 ? jtag bst circuitry quad cloc k module qclka qclkb *qclk1in s0 s1 qclk1 quad cloc k module *qclk2in s0 s1 qclk2 quad cloc k module qclkc qclkd *qclk3in s0 s1 qclk3 quad cloc k module *qclk4in s0 s1 qclk4 *qclk1in, qclk2in, qclk3in, and qckl4in are internally generated signals. jpr obe register boundar y scan register instr uction decode control logic t ap controller instr uction register bypass register tms tclk tdi output mux tdo 1- 20 when a device is operating in jtag bst mode, four i/o pins are used for the tdi, tdo, tms, and tclk signals. an active reset (ntrst) pin is not supported, however the 3200dx contains power-on reset circuitry which resets the jtag bst circuitry upon power-up. during normal device operation, the jtag pins should be held low to disable the jtag circuitry. the following table summarizes the functions of the jtag bst signals. jtag bst instructions jtag bst testing within the 3200dx devices is controlled by a test access port (tap) state machine. the tap controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. the tap controller uses the tms signal to control the jtag testing of the device. the jtag test mode is determined by the bit stream entered on the tms pin. the table in the next column describes the jtag instructions supported by the 3200dx. actionprobe if a device has been successfully programmed and the security fuse has not been programmed, any internal logic or i/o module output can be observed using the actionprobe circuitry and the pra and/or prb pins. the actionprobe diagnostic system provides the software and hardware required to perform real-time debugging. refer to using the actionprobe for system-level debug application note on page 4-123 for further information. jt a g signal name function tdi t est data in ser ial data input f or jt a g instr uctions and data. data is shifted in on the r ising edge of tclk. tdo t est data out ser ial data output f or jt a g instr uctions and test data. tms t est mode select ser ial data input f or jt a g test mode . data is shifted in on the r ising edge of tclk. tclk t est cloc k cloc k signal to shift the jt a g data into the de vice . t est mode code description extest 000 allo ws the e xter nal circuitr y and board-le v el interconnections to be tested b y f orcing a test patter n at the output pins and captur ing test results at the input pins . sample/ prelo ad 001 allo ws a snapshot of the signals at the de vice pins to be captured and e xamined dur ing de vice oper ation. intest 010 ref er to ieee 1149.1 speci? cation jpr obe 011 a pr iv ate instr uction allo wing the user to connect actel s micro probe registers to the jt a g chain. user instr uction 100 allo ws the user to b uild application-speci? c instr uctions such as ram read and ram write. high z 101 ref er to ieee 1149.1 speci? cation clamp 110 ref er to ieee 1149.1 speci? cation byp ass 111 enab les the b y b ypass register betw een the tdi and tdo pins . the test data passes through the selected de vice to adjacent de vices in the jt a g chain. 1- 21 integrator series fpgas C 1200xl and 3200dx familes 5.0v operating conditions absolute maximum ratings 1 fr ee air temperatur e range symbol p arameter limits units v cc dc supply v oltage C0.5 to +7.0 v v i input v oltage C0.5 to v cc +0.5 v v o output v oltage C0.5 to v cc +0.5 v i io i/o source/sink current 2 20 ma t stg stor age t emper ature C65 to +150 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedence and draw extremely low current. however, when input voltage is greater than v cc + 0.5 v or less than gnd C 0.5 v, the internal protection diode will be forward biased and can draw excessive current. recommended operating conditions p arameter commer cial industrial militar y units t emper ature range 1 0 to +70 C40 to +85 C55 to +125 c p o w er supply t oler ance 5 10 10 %v cc note: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. electrical specifications symbol p arameter commer cial commer cial Cf industrial militar y units min. max. min. max. min. max. min. max. v oh 1 (i oh = C10 ma) 2 2.4 2.4 v (i oh = C6 ma) 3.84 3.84 v (i oh = C4 ma) 3.7 3.7 v v ol 1 (i ol = 10 ma) 2 0.5 0.5 v (i ol = 6 ma) 0.33 0.33 0.40 0.40 v v il C0.3 0.8 C0.3 0.8 C0.3 0.8 C0.3 0.8 v v ih 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v input t r ansition time t r , t f 2 500 500 500 500 ns c io i/o capacitance 2, 3 10 10 10 10 pf standb y current, i cc 4 (typical = 1 ma) 1.5 20 10 20 ma i cc(d) dynamic v cc supply current see p o w er dissipation on page 1-21 notes: 1. only one output tested at a time. v cc = min. 2. not tested, for information only. 3. includes worst-case 176 cpga package capacitance. v out = 0 v, f = 1 mhz. 4. all outputs unloaded. all inputs = v cc or gnd, typical i cc = 1 ma. i cc limit includes i pp and i sv during normal operation. 1- 22 3.3v operating conditions absolute maximum ratings 1 free air temperature range recommended operating conditions symbol p arameter limits units v cc dc supply v oltage C0.5 to +7.0 v v i input v oltage C0.5 to v cc +0.5 v v o output v oltage C0.5 to v cc +0.5 v i io i/o source sink current 2 20 ma t stg stor age t emper ature C65 to +150 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5 v or less than gnd C 0.5 v, the internal protection diodes will forward bias and can draw excessive current. p arameter commer cial units t emper ature range 1 0 to +70 c p o w er supply t oler ance 5 %v note: 1. ambient temperature (t a ) is used for commercial. electrical specifications p arameter commer cial units min. max. v oh 1 (i oh = C4 ma) 2.15 v (i oh = C3.2 ma) 2.4 v v ol 1 (i ol = 6 ma) 0.4 v v il C0.3 0.8 v v ih 2.0 v cc + 0.3 v input t r ansition time t r , t f 2 500 ns c io i/o capacitance 2, 3 10 pf standb y current, i cc 4 (typical = 0.3 ma) 0.75 ma i cc(d) dynamic v cc supply current see p o w er dissipation on page 1-21 notes: 1. only one output tested at a time. v cc = min. 2. not tested, for information only. 3. includes worst-case 84-pin plcc package capacitance. v out = 0 v, f = 1 mhz. 4. typical standby current = 0.3 ma. all outputs unloaded. all inputs = v cc or gnd. 1- 23 integrator series fpgas C 1200xl and 3200dx familes package thermal characteristics the device junction to case thermal characteristic is q jc, and the junction to ambient air characteristic is q ja. the thermal characteristics for q ja are shown with two different air flow rates. maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a pqfp 160-pin package at commercial temperature is as follows: power dissipation general power equation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc C v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . an accurate determination of n and m is problematic because their values depend on the family type, design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in lower power dissipation than pals or plds. by integrating multiple pals/plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated below for commercial, worst case conditions. i cc v cc power 2 ma 5.25 v 10.5 mw the static power dissipation by ttl loads depends on the number of outputs driving high or low and the dc load current. again, this number is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33 v will generate 42 mw with all outputs driving low and 140 mw with all outputs driving high. the actual dissipation will average somewhere between as i/os switch states with time. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totem-pole current in the cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. p ac ka g e t ype pin count q ja maxim um p o wer dissipation still air 300 ft/min still air 300 ft/min plastic quad flatpac k 100 42 c/w 33 c/w 1.9 w 2.4 w plastic quad flatpac k 144 36 c/w 29 c/w 2.2 w 2.8 w plastic quad flatpac k 160 34 c/w 27 c/w 2.4 w 3.0 w plastic quad flatpac k 208 25 c/w 16.2 c/w 3.2 w 4.9 w plastic leaded chip carr ier 84 37 c/w 28 c/w 2.2 w 2.9 w thin quad flatpac k 176 32 c/w 25 c/w 2.5 w 3.2 w p o w er quad flatpac k 208 16.8 c/w 11.4 c/w 4.8 w 7.0 w p o w er quad flatpac k 240 16.1 c/w 10.6 c/w 5.0 w 7.5 w max. junction temp. ( c) C max. commercial temp. q j a ( c/w) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 c C 70 c 30 c/w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2.6 w = = 1- 24 equivalent capacitance the power dissipated by a cmos circuit can be expressed by equation 1. power ( m w) = c eq * v cc 2 * f (1) where: c eq is the equi v alent capacitance e xpressed in picof arads (pf). v cc is po wer supply in v olts (v). f is the switching frequenc y in me g ahertz (mhz). equivalent capacitance is calculated by measuring i ccactive at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. equivalent capacitance values are shown below. c eq v alues for actel fpgas modules (c eqm ) 5.2 input buffers (c eqi ) 11.6 output buffers (c eqo ) 23.8 routed array clock buffer loads (c eqcr ) 3.5 to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. equation 2 shows a piece-wise linear summation over all components. power = v cc 2 * [(m x c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * ( c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 (2) where: m = number of logic modules switching at frequency f m n = number of input buffers switching at frequency f n p = number of output buffers switching at frequency f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output load capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz fixed capacitance values for actel fpgas (pf) deter mining a verage switching fr equency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. these guidelines are as follows: device type r 1 routed_clk1 r 2 routed_clk2 a1225xl 106 106 a1240xl 134 134 a3265dx 158 158 a1280xl 168 168 a32100dx 178 178 a32140dx 190 190 a32200dx 230 230 a32300dx 285 285 logic modules (m) = 80% of combinatorial modules inputs switching (n) = # of inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 ) = 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l ) = 35 pf average logic module switching rate (f m ) = f/10 average input switching rate (f n ) = f/5 average output switching rate (f p ) = f/10 average first routed array clock rate (f q1 ) = f average second routed array clock rate (f q2 ) = f/2 1- 25 integrator series fpgas C 1200xl and 3200dx familes 1200xl timing model* *values shown for a1225xl-2 at worst-case commercial conditions. ? input module predicted routing delay output dela ys internal dela ys input dela ys t inh = 0.0 ns t insu = 0.3 ns i/o module d q t ingl = 2.6 ns t inyl = 1.3 ns t ird2 = 3.2 ns ? combinator ial logic module t pd = 2.6 ns sequential logic module i/o module t rd1 = 0.8 ns t dlh = 3.8 ns i/o module arra y clocks f max = 225 mhz combin- ator ial logic included in t sud d q d q t outh = 0.0 ns t outsu = 0.3 ns t glh = 4.2 ns t dlh = 3.8 ns t enhz = 5.4 ns t rd1 = 0.8 ns t co = 2.6 ns t sud = 0.4 ns t hd = 0.0 ns t rd4 = 2.0 ns t rd8 = 3.2 ns predicted routing dela ys t ckh = 5.1 ns g g fo = 256 t rd2 = 1.3 ns t lco = 10.7 ns (64 loads , pad-pad) 1- 26 3200dx timing model (logic functions using array clocks)* *values shown for a3265dx-2 at worst-case commercial conditions. output dela ys internal dela ys input dela ys t inh = 0.0 ns t insu = 0.3 ns i/o module d q t ingo = 2.6 ns t inpy = 1.3 ns t ird1 = 3.2 ns combinator ial module t pd = 2.5 ns sequential logic module i/o module t rd1 = 1.3 ns t dlh = 3.7 ns i/o module arra y clocks f max = 200 mhz combin- ator ial logic included in t sud d q d q t lh = 0.0 ns t lsu = 0.3 ns t ghl = 4.6 ns t dlh = 3.7 ns t enhz = 3.7 ns t rd1 = 1.3 ns t co = 2.5 ns t sud = 0.3 ns t hd = 0.0 ns predicted routing dela ys g g decode module t pdd = 2.9 ns t rdd = 0.3 ns t rd2 = 1.8 ns t rd4 = 2.6 ns t ckh = 5.1 ns 1- 27 integrator series fpgas C 1200xl and 3200dx familes 3200dx timing model (logic functions using quadrant clocks)* * preliminary values shown for a32200dx-2 at worst-case commercial conditions. ** load dependent. output dela ys internal dela ys input dela ys t inh = 0.0 ns t insu = 0.3 ns i/o module d q t ingo = 2.6 ns t inpy = 1.3 ns t ird1 = 3.2 ns combinator ial module t pd = 2.5 ns sequential logic module i/o module t rd1 = 1.3 ns t dlh = 3.7 ns i/o module q u adrant clocks f max = 100 mhz combin- ator ial logic included in t sud d q d q t lh = 0.0 ns t lsu = 0.3 ns t ghl = 4.6 ns t dlh = 3.7 ns t enhz = 3.7 ns t rd1 = 1.3 ns t co = 2.5 ns t sud = 0.3 ns t hd = 0.0 ns predicted routing dela ys g g decode module t pdd = 2.9 ns t rdd = 0.3 ns t rd2 = 1.8 ns t rd4 = 2.6 ns t ckh = 12 ns** 1- 28 3200dx timing model (sram functions)* *values shown for a32200dx-2 at worst-case commercial conditions. t inh = 0.0 ns t insu = 0.3 ns input dela ys i/o module d q t ingo = 2.6 ns t inpy = 1.3 ns t ird1 = 3.2 ns arra y clocks f max = 100 mhz g t ghl = 4.6 ns t lsu = 0.3 ns i/o module d q t lh = 0.0 ns t dlh = 3.7 ns g wd [7:0] wrad [5:0] blken wen wclk t adsu = 1.8 ns t adh = 0.0 ns t wensu = 2.9 ns t bens = 2.9 ns rd [7:0] rd ad [5:0] ren rclk t adsu = 1.8 ns t adh = 0.0 ns t rensu = 0.8 ns ? ? ? t rd1 = 2.0 ns predicted routing dela ys t rco = 3.8 ns 1- 29 integrator series fpgas C 1200xl and 3200dx familes parameter measurement output buf fer delays ac t est loads input buf fer delays module delays t o a c test loads (sho wn belo w) p ad d e trib uff in 50% p ad v ol v oh 1.5 v t dlh 50% 1.5 v t dhl e 50% p ad v ol 1.5 v t enzl 50% 10% t enlz e 50% p ad gnd v oh 1.5 v t enzh 50% 90% t enhz v cc load 1 (used to measure pr opa gation dela y) load 2 (used to measure rising/falling edg es) 35 pf t o the output under test v cc gnd 35 pf t o the output under test r to v cc f or t plz /t pzl r to gnd f or t phz /t pzh r = 1 k w p ad y inb uf p ad 3 v 0 v 1.5 v y gnd v cc 50% t inyh 1.5 v 50% t inyl s a b y s , a or b y 50% t plh y 50% 50% 50% 50% 50% t phl t phl t plh 1- 30 sequential module timing characteristics flip-flops and latches note: d represents all data functions involving a, b, and s for multiplexed flip-flops. (p ositiv e edge tr iggered) d e clk clr pre y d 1 g, clk e q pre, clr t wclka t w asyn t hd t suena t sud t rs t a t wclki t co t hena 1- 31 integrator series fpgas C 1200xl and 3200dx familes sequential timing characteristics (continued) input buf fer latches output buffer latches g p ad p ad clk d a t a g clk t inh clkb uf t insu t suext t hext ibdl d a t a d g t outsu t outh p ad obdlhs d g 1- 32 decode module timing sram timing characteristics aCg, h y t plh 50% v cc v cc t phl y a b c d e f g h wrad [5:0] blken wen wclk rd ad [5:0] lew ren rclk rd [7:0] wd [7:0] wr ite p or t read p or t ram arr a y 32x8 or 64x4 (256 bits) 1- 33 integrator series fpgas C 1200xl and 3200dx familes dual-port sram timing waveforms 3200dx sram w rite operation 3200dx sram synchr onous read operation note: identical timing for falling-edge clock. wclk wd[7:0] wrad[5:0] wen blken v alid v alid t rckhl t rckhl t wensu t bensu t wenh t benh t adsu t adh note: identical timing for falling-edge clock. rclk ren rd ad[5:0] rd[7:0] old data v alid t rckhl t ckhl t renh t rco t adh t doh t adsu ne w data t rensu 1- 34 3200dx sram asynchr onous read operationt ype 1 3200dx sram asynchr onous read operationt ype 2 (read ad dress contr olled) (write ad dress contr olled) rd ad[5:0] rd[7:0] data 1 t rd ad v t doh addr2 addr1 data 2 t rpd wen wd[7:0] wclk rd[7:0] old data v alid t wenh t rpd t wensu ne w data t doh t adsu wrad[5:0] blken t adh 1- 35 integrator series fpgas C 1200xl and 3200dx familes predictable performance: tight delay distributions propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. from a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. higher fanout usually requires some paths to have longer routing tracks. the integrator series delivers a very tight fanout delay distribution. this tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. actels patented plice antifuse offers a very low resistive/capacitive interconnect. the antifuses, fabricated in 0.6 micron lithography, offer nominal levels of 100 ohms resistance and 7.0 femtofarad (ff) capacitance per antifuse. the integrator series fanout distribution is also tight due to the low number of antifuses required for each interconnect path. the proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. timing characteristics timing characteristics for devices fall into three categories: family dependent, device dependent, and design dependent. the input and output buffer characteristics are common to all integrator series members. internal routing delays are device dependent. design dependency means actual delays are not determined until after placement and routing of the users design is complete. delay values may then be determined by using the designer series utility or performing simulation with post-layout delays. critical nets and t ypical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. since the architecture provides deterministic timing and abundant routing resources, actels designer series development tools offers directtime; a timing-driven place and route tool. using directtime, the designer may specify timing-critical nets and system clock frequency. using these timing specifications, the place and route software optimized the layout of the design to meet the users specifications. long t racks some nets in the design use long tracks. long tracks are special routing resources that span multiple rows, columns, or modules. long tracks employ three and sometimes four antifuse connections. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6% of nets in a fully utilized device require long tracks. long tracks contribute approximately 3 ns to 6 ns delay. this additional delay is represented statistically in higher fanout (fo=8) routing delays in the data sheet specifications section. timing derating a best case timing derating factor of 0.45 is used to reflect best case processing. note that this factor is relative to the standard speed timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. timing derating factor (temperature and voltage) timing derating factor for designs at typical temperature (t j = 25 c) and voltage (5.0 v) note: this derating factor applies to all routing and propagation delays. industrial militar y min. max. min. max. (commercial speci? cation) x 0.69 1.11 0.67 1.23 (maxim um speci? cation, w orst-case condition) x 0.85 1- 36 temperature and voltage derating factors (normalized to worst-case commercial, t j = 4.75 v, 70 c) C55 C40 0 25 70 85 125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 note: this derating factor applies to all routing and propagation delays. 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 1 . 3 4 . 5 0 4 . 7 5 5 . 0 0 5 . 2 5 5 . 5 0 d e r a t i n g f a c t o r v o l t a g e ( v ) 1 2 5 c 8 5 c 7 0 c 2 5 c 0 c 4 0 c 5 5 c j unction t emperature and v olta g e derating cur ves (normaliz ed to w or st-case commer cial, t j = 4.75 v , 70 c) 1- 37 integrator series fpgas C 1200xl and 3200dx familes a1225xl timing characteristics (w orst-case commer cial conditions, v cc = 4.75 v , t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtaine d from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup /hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. v cc = 3.0 v for 3.3v specifications. logic module pr opa gation dela ys 1 C2 speed C1 speed std speed Cf speed 3.3v speed 5 p arameter description min. max. min. max. min. max. min. max. min. max. units t pd1 single module 2.6 3.0 3.5 5.0 4.2 ns t co sequential clk to q 2.6 3.0 3.5 5.0 4.2 ns t go latch g to q 2.6 3.0 3.5 5.0 4.2 ns t rs flip-flop (latch) reset to q 2.6 3.0 3.5 5.0 4.2 ns predicted routing dela ys 2 t rd1 fo=1 routing dela y 0.8 0.9 1.1 1.57 1.3 ns t rd2 fo=2 routing dela y 1.3 1.4 1.7 2.43 2.0 ns t rd3 fo=3 routing dela y 1.7 1.8 2.2 3.15 2.6 ns t rd4 fo=4 routing dela y 2.0 2.3 2.7 3.86 3.2 ns t rd8 fo=8 routing dela y 3.2 3.5 4.2 6.00 5.0 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 0.7 0.6 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enab le setup 0.8 0.9 1.0 1.4 1.2 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.2 3.6 4.3 6.1 5.2 ns t w asyn flip-flop (latch) asynchronous pulse width 3.2 3.6 4.3 6.1 5.2 ns t a flip-flop cloc k input p er iod 6.5 7.4 8.7 12.4 10.4 ns t inh input buff er latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buff er latch setup 0.3 0.4 0.4 0.6 0.5 ns t outh output buff er latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buff er latch setup 0.3 0.4 0.4 0.6 0.5 ns f max flip-flop (latch) cloc k f requency 225.0 200.0 170.0 120.0 115.0 mhz 1- 38 a1225xl timing characteristics (continued) (w orst-case commer cial conditions) note: 1. these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 3 ns. routing delays are for typical designs across worst-case operating conditions. post- route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units t inyh p ad to y high 1.1 1.2 1.4 2.0 1.7 ns t inyl p ad to y lo w 1.3 1.4 1.7 2.4 2.0 ns t ingh g to y high 2.0 2.3 2.7 3.9 3.2 ns t ingl g to y lo w 2.6 3.0 3.5 5.0 4.2 ns input module predicted routing dela ys 1 t ird1 fo=1 routing dela y 2.9 3.3 3.9 5.6 4.7 ns t ird2 fo=2 routing dela y 3.2 3.6 4.3 6.1 5.2 ns t ird3 fo=3 routing dela y 3.8 4.2 5.0 7.2 6.0 ns t ird4 fo=4 routing dela y 4.1 4.6 5.4 7.7 6.5 ns t ird8 fo=8 routing dela y 5.2 5.9 6.9 9.9 8.3 ns global cloc k netw ork t ckh input lo w to high fo = 32 fo = 256 5.1 5.7 5.8 6.5 6.8 7.6 9.7 10.9 8.2 9.1 ns t ckl input high to lo w fo = 32 fo = 256 5.0 5.7 5.7 6.5 6.7 7.6 9.6 10.9 8.0 9.1 ns t pwh minim um pulse width high fo = 32 fo = 256 2.6 2.7 3.0 3.1 3.5 3.6 5.0 5.1 4.2 4.3 ns t pwl minim um pulse width lo w fo = 32 fo = 256 2.6 2.7 3.0 3.1 3.5 3.6 5.0 5.1 4.2 4.3 ns t cksw maxim um sk e w fo = 32 fo = 256 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 1.2 1.2 ns t suext input latch exter nal setup fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t hext input latch exter nal hold fo = 32 fo = 256 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.1 5.2 ns t p minim um p er iod fo = 32 fo = 256 5.4 5.6 6.1 6.3 7.2 7.4 10.3 10.6 8.6 8.9 ns f max maxim um f requency fo = 32 fo = 256 225.0 200.0 200.0 180.0 170.0 155.0 120.0 105.0 115.0 105.0 mhz 1- 39 integrator series fpgas C 1200xl and 3200dx familes a1225xl timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.8 4.3 5.0 7.1 6.0 ns t dhl data to p ad lo w 4.1 4.6 5.4 7.7 6.5 ns t enzh enab le p ad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enab le p ad z to lo w 4.1 4.7 5.5 7.9 6.5 ns t enhz enab le p ad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enab le p ad lo w to z 5.4 6.1 7.2 10.3 8.6 ns t glh g to p ad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g to p ad lo w 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch cloc k-out (pad-to-pad), 64 cloc k loading 9.0 10.0 12.0 17.2 14.4 ns t a co arr a y cloc k-out (pad-to-pad), 64 cloc k loading 12.8 14.4 17.0 24.3 20.4 ns d tlh capacitiv e loading, lo w to high 0.04 0.04 0.05 0.06 0.06 ns/pf d thl capacitiv e loading, high to lo w 0.05 0.06 0.07 0.08 0.08 ns/pf cmos output module timing 1 t dlh data to p ad high 4.8 5.4 6.4 9.1 7.7 ns t dhl data to p ad lo w 3.4 3.8 4.5 6.4 5.4 ns t enzh enab le p ad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enab le p ad z to lo w 4.1 4.7 5.5 7.9 6.6 ns t enhz enab le p ad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enab le p ad lo w to z 5.4 6.1 7.2 10.3 8.6 ns t glh g to p ad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g to p ad lo w 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch cloc k-out (pad-to-pad), 64 cloc k loading 10.7 11.8 14.2 20.3 17.0 ns t a co arr a y cloc k-out (pad-to-pad), 64 cloc k loading 15.0 17.0 20.0 28.6 24.0 ns d tlh capacitiv e loading, lo w to high 0.05 0.06 0.07 0.08 0.08 ns/pf d thl capacitiv e loading, high to lo w 0.05 0.05 0.06 0.07 0.07 ns/pf 1- 40 a1240xl timing characteristics (w orst-case commer cial conditions, v cc = 4.75 v , t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtaine d from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup /hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. v cc = 3.0 v for 3.3v specifications. logic module pr opa gation dela ys 1 C2 speed C1 speed std speed Cf speed 3.3v speed 5 p arameter description min. max. min. max. min. max. min. max. min. max. units t pd1 single module 2.6 3.0 3.5 5.0 4.2 ns t co sequential clk to q 2.6 3.0 3.5 5.0 4.2 ns t go latch g to q 2.6 3.0 3.5 5.0 4.2 ns t rs flip-flop (latch) reset to q 2.6 3.0 3.5 5.0 4.2 ns predicted routing dela ys 2 t rd1 fo=1 routing dela y 1.1 1.2 1.4 2.0 1.7 ns t rd2 fo=2 routing dela y 1.3 1.4 1.7 2.4 2.0 ns t rd3 fo=3 routing dela y 1.7 1.9 2.2 3.1 2.6 ns t rd4 fo=4 routing dela y 2.3 2.6 3.0 4.3 3.6 ns t rd8 fo=8 routing dela y 3.4 3.8 4.5 6.4 5.4 ns sequential timing characteristics 3, 4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 0.7 0.6 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enab le setup 0.8 0.9 1.0 1.4 1.2 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.4 3.8 4.5 6.4 5.4 ns t w asyn flip-flop (latch) asynchronous pulse width 3.4 3.8 4.5 6.4 5.4 ns t a flip-flop cloc k input p er iod 6.8 7.7 9.1 13.0 10.9 ns t inh input buff er latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buff er latch setup 0.3 0.4 0.4 0.6 0.5 ns t outh output buff er latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buff er latch setup 0.3 0.4 0.4 0.6 0.5 ns f max flip-flop (latch) cloc k f requency 215.0 190.0 160.0 110.0 105.0 mhz 1- 41 integrator series fpgas C 1200xl and 3200dx familes a1240xl timing characteristics (continued) (w orst-case commer cial conditions) note: 1. these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 3 ns. routing delays are for typical designs across worst-case operating conditions. post- route timing analysis or simulation is required to determine actual worst-case input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units t inyh p ad to y high 1.1 1.2 1.4 2.0 1.7 ns t inyl p ad to y lo w 1.3 1.4 1.7 2.4 2.0 ns t ingh g to y high 2.0 2.3 2.7 3.9 3.2 ns t ingl g to y lo w 2.6 3.0 3.5 5.0 4.2 ns input module predicted routing dela ys 1 t ird1 fo=1 routing dela y 2.9 3.3 3.9 5.6 4.7 ns t ird2 fo=2 routing dela y 3.4 3.8 4.5 6.4 5.4 ns t ird3 fo=3 routing dela y 3.8 4.3 5.1 7.3 6.1 ns t ird4 fo=4 routing dela y 4.1 4.7 5.5 7.9 6.6 ns t ird8 fo=8 routing dela y 5.6 6.3 7.4 10.6 8.9 ns global cloc k netw ork t ckh input lo w to high fo = 32 fo = 256 5.1 5.7 5.8 6.5 6.8 7.6 9.7 10.9 8.2 9.1 ns ns t ckl input high to lo w fo = 32 fo = 256 5.0 5.7 5.7 6.5 6.7 7.6 9.6 10.9 8.0 9.1 ns ns t pwh minim um pulse width high fo = 32 fo = 256 2.7 2.9 3.1 3.3 3.6 3.9 5.1 5.6 4.3 4.7 ns ns t pwl minim um pulse width lo w fo = 32 fo = 256 2.7 2.9 3.1 3.3 3.6 3.9 5.1 5.6 4.3 4.7 ns ns t cksw maxim um sk e w fo = 32 fo = 256 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 1.2 1.2 ns ns t suext input latch exter nal setup fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo = 32 fo = 256 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.1 5.2 ns ns t p minim um p er iod fo = 32 fo = 256 5.6 6.0 6.3 6.8 7.4 8.0 10.6 11.4 8.9 9.6 ns ns f max maxim um f requency fo = 32 fo = 256 215.0 195.0 190.0 170.0 160.0 144.0 110.0 100.0 105.0 95.0 mhz mhz 1- 42 a1240xl timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.8 4.3 5.0 7.1 6.0 ns t dhl data to p ad lo w 4.1 4.6 5.4 7.7 6.5 ns t enzh enab le p ad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enab le p ad z to lo w 4.1 4.7 5.5 7.9 6.6 ns t enhz enab le p ad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enab le p ad lo w to z 5.4 6.1 7.2 10.3 8.6 ns t glh g to p ad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g to p ad lo w 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch cloc k-out (pad-to-pad), 64 cloc k loading 9.2 10.5 12.3 17.6 14.8 ns t a co arr a y cloc k-out (pad-to-pad), 64 cloc k loading 12.9 14.6 17.2 24.6 20.6 ns d tlh capacity loading, lo w to high 0.04 0.04 0.05 0.06 0.06 ns/pf d thl capacity loading, high to lo w 0.05 0.06 0.07 0.08 0.08 ns/pf cmos output module timing 1 t dlh data to p ad high 4.8 5.4 6.4 9.1 7.7 ns t dhl data to p ad lo w 3.4 3.8 4.5 6.4 5.4 ns t enzh enab le p ad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enab le p ad z to lo w 4.1 4.7 5.5 7.9 6.6 ns t enhz enab le p ad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enab le p ad lo w to z 5.4 6.1 7.2 10.3 8.6 ns t glh g to p ad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g to p ad lo w 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch cloc k-out (pad-to-pad), 64 cloc k loading 10.9 12.4 14.5 20.7 17.4 ns t a co arr a y cloc k-out (pad-to-pad), 64 cloc k loading 15.2 17.2 20.3 29.0 24.4 ns d tlh capacity loading, lo w to high 0.05 0.06 0.07 0.08 0.08 ns/pf d thl capacity loading, high to lo w 0.05 0.05 0.06 0.07 0.07 ns/pf 1- 43 integrator series fpgas C 1200xl and 3200dx familes a3265dx timing characteristics (w orst-case commer cial conditions) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtaine d from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup /hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. v cc = 3.0 v for 3.3v specifications. logic module pr opa gation dela ys 1 C2 speed C1 speed std speed Cf speed 3.3v speed 5 p arameter description min. max. min. max. min. max. min. max. min. max. units combinatorial functions t pd inter nal arr a y module dela y 1.8 2.4 2.9 3.7 3.2 ns t pdd inter nal decode module dela y 2.1 2.8 3.4 4.4 3.7 ns predicted routing dela ys 2 t rd1 fo=1 routing dela y 0.3 0.4 .05 0.6 0.5 ns t rd2 fo=2 routing dela y 0.6 0.8 .09 1.2 1.0 ns t rd3 fo=3 routing dela y 0.9 1.2 1.4 1.8 1.6 ns t rd4 fo=4 routing dela y 1.2 1.6 1.9 2.4 2.1 ns t rd5 fo=8 routing dela y 2.4 3.2 3.7 4.9 4.1 ns t rdd decode-to-output routing dela y 0.4 0.5 0.62 0.8 0.7 ns sequential timing chatacteristics 3, 4 t co flip-flop cloc k-to-output 2.0 2.7 3.1 4.1 3.5 ns t go latch gate-to-output 1.8 2.4 2.9 3.7 3.2 ns t su flip-flop (latch) setup time 0.3 0.4 0.47 0.6 0.5 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t r o flip-flop (latch) reset to output 2.0 2.7 3.1 4.1 3.5 ns t suena flip-flop (latch) enab le setup 0.6 0.9 1.0 1.3 1.1 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.1 4.2 4.9 6.4 5.5 ns t w asyn flip-flop (latch) asynchronous pulse width 4.1 5.5 6.5 8.4 7.1 ns 1- 44 a3265dx timing characteristics (continued) (w orst-case commer cial conditions) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units t inpy input data p ad to y 1.2 1.6 1.9 2.4 2.1 ns t ingo input latch gate-to-output 2.8 3.7 4.4 5.7 4.8 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch setup 0.4 0.6 0.7 0.9 0.8 ns t ila latch activ e pulse width 4.4 5.9 6.9 9.0 7.7 ns input module predicted routing dela ys 1 t ird1 fo=1 routing dela y 2.7 3.7 4.3 5.6 4.8 ns t ird2 fo=2 routing dela y 3.1 4.2 4.9 6.4 5.4 ns t ird3 fo=3 routing dela y 3.4 4.5 5.3 6.9 5.9 ns t ird4 fo=4 routing dela y 3.9 5.2 6.1 7.9 6.7 ns t ird5 fo=8 routing dela y 5.6 7.5 8.8 11.4 9.7 ns t irdd decode-to-output routing dela y 0.3 0.4 0.5 0.7 0.6 ns global cloc k netw ork t ckh input lo w to high fo=32 fo=256 6.3 5.3 8.4 7.1 9.9 8.4 12.8 10.9 10.9 9.2 ns ns t ckl input high to lo w fo=32 fo=256 4.95 5.5 6.6 7.3 7.8 8.6 10.1 11.2 8.6 9.5 ns ns t pw minim um pulse width fo=32 fo=256 2.7 2.9 3.7 3.9 4.3 4.6 5.6 6.0 4.8 5.1 ns ns t cksw maxim um sk e w fo=32 fo=256 0.6 0.6 0.9 0.9 1.0 1.0 1.3 1.3 1.1 1.1 ns ns t suext input latch exter nal setup fo=32 fo=256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo=32 fo=256 2.2 2.2 2.9 2.9 3.4 3.4 4.4 4.4 3.8 3.8 ns ns t p minim um p er iod (1/fmax) fo=32 fo=256 12.5 13.8 10.0 11.0 8.7 9.6 6.1 6.7 9.6 10.6 ns ns f max maxim um datapath f requency fo=32 fo=256 172.5 150.9 138.0 120.8 120.0 105.0 84.0 73.5 108.0 94.5 mhz mhz 1- 45 integrator series fpgas C 1200xl and 3200dx familes a3265dx timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. delays based on 35pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.2 4.3 5.0 6.5 5.5 ns t dhl data to p ad lo w 3.9 5.2 6.1 7.9 6.7 ns t enzh enab le p ad z to high 4.1 5.4 6.4 8.3 7.1 ns t enzl enab le p ad z to lo w 4.4 5.9 6.9 9.0 7.6 ns t enhz enab le p ad high to z 7.1 9.5 11.1 14.5 12.3 ns t enlz enab le p ad lo w to z 7.1 9.5 11.1 14.5 12.3 ns t glh g to p ad high 7.1 9.4 11.1 14.4 12.3 ns t ghl g to p ad lo w 6.5 8.7 10.2 13.3 11.3 ns t lsu i/o latch output setup 0.4 0.6 0.7 0.9 0.8 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 8.4 11.1 13.1 17.0 14.5 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 11.8 15.7 18.5 24.1 20.5 ns d tlh capacitiv e loading, lo w to high 0.03 0.04 0.05 0.1 0.1 ns/pf d tll capacitiv e loading, high to lo w 0.02 0.03 0.07 0.1 0.1 ns/pf t wdo hard-wired wide decode output 0.3 0.4 0.5 0.7 0.6 ns/pf cmos output module timing 1 t dlh data to p ad high 3.9 5.2 6.1 7.9 6.7 ns t dhl data to p ad lo w 3.2 4.3 5.0 6.5 5.5 ns t enzh enab le p ad z to high 4.1 5.5 6.4 8.4 7.1 ns t enzl enab le p ad z to lo w 4.4 5.9 6.9 9.0 7.6 ns t enhz enab le p ad high to z 7.1 9.5 11.1 14.5 12.3 ns t enlz enab le p ad lo w to z 7.1 9.5 11.1 14.5 12.3 ns t glh g to p ad high 7.1 9.4 11.1 14.4 12.3 ns t ghl g to p ad lo w 7.7 10.2 12.0 15.6 13.3 ns t lsu i/o latch setup 0.4 0.6 0.7 0.9 0.8 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 9.9 13.3 15.6 20.3 17.3 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 13.9 18.5 21.8 28.3 24.1 ns d tlh capacitiv e loading, lo w to high 0.04 0.06 0.07 0.1 0.1 ns/pf d tll capacitiv e loading, high to lo w 0.04 0.05 0.06 0.1 0.1 ns/pf t wdo hard-wired wide decode output 0.3 0.4 0.5 0.7 0.6 ns/pf 1- 46 a1280xl timing characteristics (w orst-case commer cial conditions, v cc = 4.75 v , t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtaine d from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup /hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. v cc = 3.0 v for 3.3v specifications. logic module pr opa gation dela ys 1 C2 speed C1 speed std speed Cf speed 3.3v speed 5 p arameter description min. max. min. max. min. max. min. max. min. max. units t pd1 single module 2.6 3.0 3.5 5.0 4.2 ns t co sequential clk to q 2.6 3.0 3.5 5.0 4.2 ns t go latch g to q 2.6 3.0 3.5 5.0 4.2 ns t rs flip-flop (latch) reset to q 2.6 3.0 3.5 5.0 4.2 ns predicted routing dela ys 2 t rd1 fo=1 routing dela y 1.3 1.4 1.7 2.4 2.0 ns t rd2 fo=2 routing dela y 1.8 2.0 2.4 3.4 2.9 ns t rd3 fo=3 routing dela y 2.2 2.5 2.9 4.1 3.5 ns t rd4 fo=4 routing dela y 2.6 3.0 3.5 5.0 4.2 ns t rd8 fo=8 routing dela y 5.0 5.7 6.7 9.6 8.0 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 0.7 0.6 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enab le setup 0.8 0.9 1.0 1.4 1.2 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.7 4.3 4.9 7.0 5.9 ns t w asyn flip-flop (latch) asynchronous pulse width 3.7 4.3 4.9 7.0 5.9 ns t a flip-flop cloc k input p er iod 8.0 8.7 10 14 12 ns t inh input buff er latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buff er latch setup 0.3 0.4 0.4 0.6 0.5 ns t outh output buff er latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buff er latch setup 0.3 0.4 0.4 0.6 0.5 ns f max flip-flop (latch) cloc k f requency 200.0 167.0 130.0 90.0 110.0 mhz 1- 47 integrator series fpgas C 1200xl and 3200dx familes a1280xl timing characteristics (continued) (w orst-case commer cial conditions) note: 1. these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typical designs across worst-case operating conditions. post- route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units t inyh p ad to y high 1.1 1.2 1.4 2.0 1.7 ns t inyl p ad to y lo w 1.3 1.4 1.7 2.4 2.0 ns t ingh g to y high 2.0 2.3 2.7 3.9 3.2 ns t ingl g to y lo w 2.6 3.0 3.5 5.0 4.2 ns input module predicted routing dela ys 1 t ird1 fo=1 routing dela y 3.2 3.7 4.3 6.1 5.2 ns t ird2 fo=2 routing dela y 3.7 4.2 4.9 7.0 5.9 ns t ird3 fo=3 routing dela y 4.0 4.5 5.3 7.6 6.4 ns t ird4 fo=4 routing dela y 4.6 5.2 6.1 8.7 7.3 ns t ird8 fo=8 routing dela y 6.6 7.5 8.8 12.6 10.6 ns global cloc k netw ork t ckh input lo w to high fo = 32 fo = 384 5.1 5.7 5.8 6.5 6.8 7.6 9.7 10.9 8.2 9.1 ns ns t ckl input high to lo w fo = 32 fo = 384 5.0 5.7 5.7 6.5 6.7 7.6 9.6 10.9 8.0 9.1 ns ns t pwh minim um pulse width high fo = 32 fo = 384 3.2 3.5 3.5 3.9 4.3 4.6 6.1 6.6 5.2 5.5 ns ns t pwl minim um pulse width lo w fo = 32 fo = 384 3.2 3.5 3.5 3.9 4.3 4.6 6.1 6.6 5.2 5.5 ns ns t cksw maxim um sk e w fo = 32 fo = 384 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 1.2 1.2 ns ns t suext input latch exter nal setup fo = 32 fo = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo = 32 fo = 384 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.1 5.2 ns ns t p minim um p er iod fo = 32 fo = 384 6.5 7.2 7.4 8.0 8.7 9.6 12.4 13.7 10.4 11.5 ns ns f max maxim um f requency fo = 32 fo = 384 200.0 180.0 167.0 150.0 143.0 130.0 100.0 90.0 120.0 110.0 mhz mhz 1- 48 a1280xl timing characteristics (continued) (worst-case commercial conditions) notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed 3.3v speed p arameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.8 4.3 5.0 7.1 6.0 ns t dhl data to p ad lo w 4.1 4.6 5.4 7.7 6.5 ns t enzh enab le p ad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enab le p ad z to lo w 4.1 4.7 5.5 7.7 6.6 ns t enhz enab le p ad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enab le p ad lo w to z 5.4 6.1 7.2 10.3 8.6 ns t glh g to p ad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g to p ad lo w 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch cloc k-out (pad-to-pad), 64 cloc k loading 9.8 11.0 13.1 18.7 15.7 ns t a co arr a y cloc k-out (pad-to-pad), 64 cloc k loading 13.9 15.7 18.5 26.4 22.2 ns d tlh capacitiv e loading, lo w to high 0.04 0.04 0.05 0.06 0.06 ns/pf d thl capacitiv e loading, high to lo w 0.05 0.06 0.07 0.08 0.08 ns/pf cmos output module timing 1 t dlh data to p ad high 4.8 5.4 6.4 9.1 7.7 ns t dhl data to p ad lo w 3.4 3.8 4.5 6.4 5.4 ns t enzh enab le p ad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enab le p ad z to lo w 4.1 4.7 5.5 7.9 6.6 ns t enhz enab le p ad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enab le p ad lo w to z 5.4 6.1 7.2 10.3 8.6 ns t glh g to p ad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g to p ad lo w 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch cloc k-out (pad-to-pad), 64 cloc k loading 11.6 13.0 15.5 22.2 18.6 ns t a co arr a y cloc k-out (pad-to-pad), 64 cloc k loading 16.4 18.5 21.8 31.2 26.2 ns d tlh capacitiv e loading, lo w to high 0.05 0.06 0.07 0.08 0.08 ns/pf d thl capacitiv e loading, high to lo w 0.05 0.05 0.06 0.07 0.07 ns/pf 1- 49 integrator series fpgas C 1200xl and 3200dx familes a32100dx timing characteristics (w orst-case commer cial conditions) logic module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units combinatorial functions t pd inter nal arr a y module dela y 2.2 3.0 3.5 5.2 ns t pdd inter nal decode module dela y 2.4 3.1 3.7 5.7 ns predicted module routing dela ys t rd1 fo=1 routing dela y 1.0 1.3 1.5 3.3 ns t rd2 fo=2 routing dela y 1.4 1.9 2.2 4.3 ns t rd3 fo=3 routing dela y 1.8 2.5 2.9 5.2 ns t rd4 fo=4 routing dela y 2.4 3.1 3.7 6.5 ns t rd5 fo=8 routing dela y 4.2 5.6 6.6 10.0 ns t rdd decode-to-output routing dela y 0.3 0.4 0.5 0.4 ns sequential timing characteristics t co flip-flop cloc k-to-output 2.2 3.0 3.5 5.0 ns t go latch gate-to-output 2.2 3.0 3.5 5.0 ns t su flip-flop (latch) setup time 0.3 0.4 0.5 0.7 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 ns t r o flip-flop (latch) reset to output 2.2 3.0 3.5 5.0 ns t suena flip-flop (latch) enab le setup 0.6 0.9 1.0 1.4 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.1 4.2 4.9 7.0 ns t w asyn flip-flop (latch) asynchronous pulse width 4.1 5.4 6.4 7.0 ns 1- 50 a32100dx timing characteristics (continued) (w orst-case commer cial conditions) logic module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units sync hr onous sram operations t rc read cycle time 6.4 8.5 10.0 14.3 ns t wc wr ite cycle time 6.4 8.5 10.0 14.3 ns t rckhl cloc k high/lo w time 3.2 4.3 5.0 7.1 ns t rco data v alid after cloc k high/lo w 3.2 4.3 5.0 7.1 ns t adsu address/data setup time 1.5 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 ns t rensu read enab le setup 0.6 0.8 0.9 1.4 ns t renh read enab le hold 3.2 4.3 5.0 0.7 ns t wensu wr ite enab le setup 2.6 3.4 4.0 5.4 ns t wenh wr ite enab le hold 0.0 0.0 0.0 0.0 ns t bens bloc k enab le setup 2.6 3.5 4.1 5.6 ns t benh bloc k enab le hold 0.0 0.0 0.0 0.0 ns async hr onous sram operations t rpd asynchronous access time 7.7 10.2 12.0 17.2 ns t rd ad v read address v alid 8.3 11.1 13.0 18.6 ns t adsu address/data setup time 1.5 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 ns t rensu a read enab le setup to address v alid 0.57 0.8 0.9 1.4 ns t renha read enab le hold 3.2 4.3 5.0 7.1 ns t wensu wr ite enab le setup 2.6 3.4 4.0 5.4 ns t wenh wr ite enab le hold 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.1 1.5 1.8 2.6 ns 1- 51 integrator series fpgas C 1200xl and 3200dx familes a32100dx timing characteristics (continued) (w orst-case commer cial conditions) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units t inpy input data p ad to y 1.4 1.9 2.2 2.9 ns t ingo input latch gate-to-output 1 2.9 3.8 4.5 5.0 ns t inh input latch hold 1 0.0 0.0 0.0 0.0 ns t insu input latch setup 1 0.45 0.6 0.7 0.6 ns t ila latch activ e pulse width 1 4.4 5.9 6.9 7.0 ns input module predicted routing dela ys t ird1 fo=1 routing dela y 1.6 2.1 2.5 6.1 ns t ird2 fo=2 routing dela y 2.0 2.7 3.2 7.0 ns t ird3 fo=3 routing dela y 2.6 3.4 4.0 7.6 ns t ird4 fo=4 routing dela y 2.6 3.4 4.0 8.7 ns t ird8 fo=8 routing dela y 4.1 5.4 6.4 12.6 ns global cloc k netw ork t ckh input lo w to high fo=32 fo=635 4.7 5.7 6.3 7.7 7.4 9.0 8.4 9.9 ns ns t ckl input high to lo w fo=32 fo=635 4.8 6.4 6.4 8.5 7.5 10.0 8.4 11.3 ns ns t pwh minim um pulse width high fo=32 fo=635 2.5 2.7 3.3 3.7 3.9 4.3 5.07 5.59 ns ns t pwl minim um pulse width lo w fo=32 fo=635 2.5 2.7 3.3 3.7 3.9 4.3 5.07 5.59 ns ns t cksw maxim um sk e w fo=32 fo=635 0.6 0.6 0.9 0.9 1.0 1.0 1.4 1.4 ns ns t suext input latch exter nal setup fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo=32 fo=635 2.2 2.7 2.9 3.7 3.4 4.3 4.9 6.1 ns ns t p minim um p er iod (1/fmax) fo=32 fo=635 5.0 5.5 7.4 8.2 7.9 8.6 12.4 13.7 ns ns f hmax maxim um datapath f requency fo=32 fo=635 182.6 166.8 146 133 127 116 88.9 81.2 mhz mhz 1- 52 a32100dx timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.7 4.9 5.8 4.8 ns t dhl data to p ad lo w 4.5 6.0 7.1 6.2 ns t enzh enab le p ad z to high 4.8 6.4 7.5 7.2 ns t enzl enab le p ad z to lo w 5.1 6.8 8.0 7.9 ns t enhz enab le p ad high to z 8.3 11.1 13.0 14.0 ns t enlz enab le p ad lo w to z 8.3 11.1 13.0 14.0 ns t glh g to p ad high 8.3 11.1 13.0 8.0 ns t ghl g to p ad lo w 9.0 12.0 14.1 9.0 ns t lsu i/o latch output setup 0.26 0.3 0.4 0.6 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 8.4 11.1 13.1 18.7 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 11.8 15.7 18.5 26.5 ns d tlh capacitiv e loading, lo w to high 0.03 0.0 0.05 0.07 ns/pf d thl capacitiv e loading, high to lo w 0.04 0.1 0.07 0.10 ns/pf t wdo hard-wired wide decode output 0.04 0.1 0.06 0.09 ns cmos output module timing 1 t dlh data to p ad high 4.5 6.0 7.1 9.1 ns t dhl data to p ad lo w 3.7 4.9 5.8 6.4 ns t enzh enab le p ad z to high 4.8 6.4 7.5 7.2 ns t enzl enab le p ad z to lo w 5.1 6.8 8.0 7.9 ns t enhz enab le p ad high to z 8.3 11.1 13.0 14.0 ns t enlz enab le p ad lo w to z 8.3 11.1 13.0 14.0 ns t glh g to p ad high 8.3 11.1 13.0 8.0 ns t ghl g to p ad lo w 9.0 12.0 14.1 9.0 ns t lsu i/o latch setup 0.26 0.3 0.4 0.6 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 9.9 13.2 15.5 22.3 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 13.9 18.5 21.8 31.2 ns d tlh capacitiv e loading, lo w to high 0.04 0.1 0.07 0.10 ns/pf d thl capacitiv e loading, high to lo w 0.04 0.1 0.06 0.09 ns/pf t wdo hard-wired wide decode output 0.04 0.1 0.06 0.09 ns 1- 53 integrator series fpgas C 1200xl and 3200dx familes a32140dx timing characteristics (w orst-case commer cial conditions) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtaine d from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup /hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. logic module pr opa gation dela ys 1 C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units combinatorial functions t pd inter nal arr a y module dela y 1.8 2.3 2.8 3.6 ns t pdd inter nal decode module dela y 1.9 2.5 3.0 3.8 ns predicted routing dela ys 2 t rd1 fo=1 routing dela y 1.0 1.3 1.6 2.0 ns t rd2 fo=2 routing dela y 1.4 1.9 2.2 2.8 ns t rd3 fo=3 routing dela y 1.8 2.4 2.8 3.7 ns t rd4 fo=4 routing dela y 2.2 2.9 3.4 4.5 ns t rd5 fo=8 routing dela y 3.8 5.0 5.9 7.7 ns t rdd decode-to-output routing dela y 0.5 0.7 0.78 1.0 ns sequential timing characteristics 3, 4 t co flip-flop cloc k-to-output 2.1 2.8 3.3 4.3 ns t go latch gate-to-output 1.8 2.3 2.8 3.6 ns t su flip-flop (latch) setup time 0.3 0.4 0.47 0.6 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 ns t r o flip-flop (latch) reset to output 2.1 2.8 3.3 4.3 ns t suena flip-flop (latch) enab le setup 0.6 0.9 1.0 1.3 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 2.6 3.5 4.1 5.4 ns t w asyn flip-flop (latch) asynchronous pulse width 4.1 5.5 6.5 8.4 ns 1- 54 a32140dx timing characteristics (continued) (w orst-case commer cial conditions) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units t inpy input data p ad to y 1.2 1.6 1.9 2.4 ns t ingo input latch gate-to-output 2.3 3.1 3.7 4.7 ns t inh input latch hold 0.0 0.0 0.0 0.0 ns t insu input latch setup 0.3 0.4 0.47 0.6 ns t ila latch activ e pulse width 3.1 4.2 4.9 6.4 ns input module predicted routing dela ys 1 t ird1 fo=1 routing dela y 2.7 3.7 4.3 5.6 ns t ird2 fo=2 routing dela y 3.1 4.2 4.9 6.4 ns t ird3 fo=3 routing dela y 3.4 4.5 5.3 6.9 ns t ird4 fo=4 routing dela y 3.9 5.2 6.1 7.9 ns t ird5 fo=8 routing dela y 5.6 7.5 8.8 11.4 ns t irdd decode-to-output routing dela y 0.3 0.4 0.5 0.7 ns global cloc k netw ork t ckh input lo w to high fo=32 fo=486 6.2 6.8 8.3 9.1 9.7 10.7 12.7 13.9 ns ns t ckl input high to lo w fo=32 fo=486 6.12 6.7 8.2 8.9 9.6 10.5 12.5 13.6 ns ns t pw minim um pulse width fo=32 fo=486 2.7 2.9 3.7 3.9 4.3 4.6 5.6 6.0 ns ns t cksw maxim um sk e w fo=32 fo=486 0.6 0.6 0.9 0.9 1.0 1.0 1.3 1.3 ns ns t suext input latch exter nal setup fo=32 fo=486 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo=32 fo=486 2.2 2.2 2.9 2.9 3.4 3.4 4.4 4.4 ns ns t p minim um p er iod (1/fmax) fo=32 fo=486 12.5 13.8 10.0 11.0 8.7 9.6 6.1 6.7 ns ns f max maxim um datapath f requency fo=32 fo=486 172.5 150.9 138.0 120.8 120.0 105.0 84.0 73.5 mhz mhz 1- 55 integrator series fpgas C 1200xl and 3200dx familes a32140dx timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.3 4.4 5.1 6.7 ns t dhl data to p ad lo w 3.5 4.6 5.4 7.1 ns t enzh enab le p ad z to high 4.1 5.5 6.4 8.4 ns t enzl enab le p ad z to lo w 4.4 5.9 6.9 9.0 ns t enhz enab le p ad high to z 7.1 9.5 11.1 14.5 ns t enlz enab le p ad lo w to z 7.1 9.5 11.1 14.5 ns t glh g to p ad high 6.5 8.7 10.2 13.3 ns t ghl g to p ad lo w 6.5 8.7 10.2 13.3 ns t lsu i/o latch output setup 0.4 0.6 0.7 0.9 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 8.4 11.1 13.1 17.0 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 11.8 15.7 18.5 24.1 ns d tlh capacitiv e loading, lo w to high 0.03 0.04 0.05 0.1 ns/pf d thl capacitiv e loading, high to lo w 0.02 0.03 0.07 0.1 ns/pf t wdo hard-wired wide decode output 0.3 0.4 0.5 0.7 ns/pf cmos output module timing 1 t dlh data to p ad high 3.5 4.6 5.4 7.1 ns t dhl data to p ad lo w 3.3 4.4 5.1 6.7 ns t enzh enab le p ad z to high 4.1 5.5 6.4 8.4 ns t enzl enab le p ad z to lo w 4.4 5.9 6.9 9.0 ns t enhz enab le p ad high to z 7.1 9.5 11.1 14.5 ns t enlz enab le p ad lo w to z 7.1 9.5 11.1 14.5 ns t glh g to p ad high 6.5 8.7 10.2 13.3 ns t ghl g to p ad lo w 6.5 8.7 10.2 13.3 ns t lsu i/o latch setup 0.4 0.6 0.7 0.9 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 9.9 13.3 15.6 20.3 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 13.9 18.5 21.8 28.3 ns d tlh capacitiv e loading, lo w to high 0.04 0.06 0.07 0.1 ns/pf d thl capacitiv e loading, high to lo w 0.04 0.05 0.06 0.1 ns/pf t wdo hard-wired wide decode output 0.3 0.4 0.5 0.7 ns/pf 1- 56 a32200dx timing characteristics (w orst-case commer cial conditions) logic module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units combinatorial functions t pd inter nal arr a y module dela y 2.0 2.7 3.2 5.2 ns t pdd inter nal decode module dela y 2.5 3.3 3.9 5.7 ns predicted module routing dela ys t rd1 fo=1 routing dela y 1.1 1.5 1.8 3.3 ns t rd2 fo=2 routing dela y 1.7 2.2 2.6 4.3 ns t rd3 fo=3 routing dela y 2.1 2.8 3.3 5.2 ns t rd4 fo=4 routing dela y 2.6 3.4 4.0 6.5 ns t rd5 fo=8 routing dela y 4.5 6.0 7.0 10.0 ns t rdd decode-to-output routing dela y 0.6 0.8 0.9 0.4 ns sequential timing characteristics t co flip-flop cloc k-to-output 2.3 3.1 3.6 5.0 ns t go latch gate-to-output 2.0 2.7 3.2 5.0 ns t su flip-flop (latch) setup time 0.3 0.4 0.47 0.7 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 ns t r o flip-flop (latch) reset to output 2.3 3.1 3.6 5.0 ns t suena flip-flop (latch) enab le setup 0.6 0.9 1.0 1.4 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.1 4.2 4.9 7.0 ns t w asyn flip-flop (latch) asynchronous pulse width 4.1 5.5 6.5 7.0 ns 1- 57 integrator series fpgas C 1200xl and 3200dx familes a32200dx timing characteristics (continued) (w orst-case commer cial conditions) logic module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units sync hr onous sram operations t rc read cycle time 6.4 8.5 10.0 14.3 ns t wc wr ite cycle time 6.4 8.5 10.0 14.3 ns t rckhl cloc k high/lo w time 3.2 4.3 5.0 7.1 ns t rco data v alid after cloc k high/lo w 3.2 4.3 5.0 7.1 ns t adsu address/data setup time 1.5 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 ns t rensu read enab le setup 0.6 0.8 0.9 1.4 ns t renh read enab le hold 3.2 4.3 5.0 0.7 ns t wensu wr ite enab le setup 2.6 3.4 4.0 5.4 ns t wenh wr ite enab le hold 0.0 0.0 0.0 0.0 ns t bens bloc k enab le setup 2.6 3.5 4.1 5.6 ns t benh bloc k enab le hold 0.0 0.0 0.0 0.0 ns async hr onous sram operations t rpd asynchronous access time 7.7 10.2 12.0 17.2 ns t rd ad v read address v alid 8.3 11.1 13.0 18.6 ns t adsu address/data setup time 1.5 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 ns t rensu a read enab le setup to address v alid 0.57 0.8 0.9 1.4 ns t renha read enab le hold 3.2 4.3 5.0 7.1 ns t wensu wr ite enab le setup 2.6 3.4 4.0 5.4 ns t wenh wr ite enab le hold 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.1 1.5 1.8 2.6 ns 1- 58 a32200dx timing characteristics (continued) (w orst-case commer cial conditions) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units t inpy input data p ad to y 1.4 1.9 2.2 2.9 ns t ingo input latch gate-to-output 1 3.3 4.3 5.1 5.0 ns t inh input latch hold 1 0.0 0.0 0.0 0.0 ns t insu input latch setup 1 0.45 0.6 0.7 0.6 ns t ila latch activ e pulse width 1 4.4 5.9 6.9 7.0 ns input module predicted routing dela ys t ird1 fo=1 routing dela y 1.9 2.6 3.0 6.1 ns t ird2 fo=2 routing dela y 2.5 3.3 3.9 7.0 ns t ird3 fo=3 routing dela y 3.3 4.4 5.2 7.6 ns t ird4 fo=4 routing dela y 3.9 5.2 6.1 8.7 ns t ird5 fo=8 routing dela y 5.0 6.7 7.9 8.7 ns t irdd decode-to-output dela y 0.3 0.4 0.5 12.6 ns global cloc k netw ork t ckh input lo w to high fo=32 fo=635 5.3 6.1 7.1 8.2 8.3 9.6 8.4 9.9 ns ns t ckl input high to lo w fo=32 fo=635 5.2 6.8 7.0 9.0 8.2 10.6 8.4 11.3 ns ns t pwh minim um pulse width high fo=32 fo=635 2.7 2.9 3.7 3.9 4.3 4.6 6.1 6.6 ns ns t pwl minim um pulse width lo w fo=32 fo=635 2.7 2.9 3.7 3.9 4.3 4.6 6.1 6.6 ns ns t cksw maxim um sk e w fo=32 fo=635 0.6 0.6 0.9 0.9 1.0 1.0 1.4 1.4 ns ns t suext input latch exter nal setup fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo=32 fo=635 2.2 2.7 2.9 3.7 3.4 4.3 4.9 6.1 ns ns t p minim um p er iod (1/fmax) fo=32 fo=635 5.5 6.1 7.4 8.2 8.7 9.6 12.4 13.7 ns ns f hmax maxim um datapath f requency fo=32 fo=635 165.3 150.9 132.3 120.8 115.0 105.0 80.0 73.0 mhz mhz 1- 59 integrator series fpgas C 1200xl and 3200dx familes a32200dx timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.7 4.9 5.8 4.8 ns t dhl data to p ad lo w 4.5 6.0 7.1 6.2 ns t enzh enab le p ad z to high 4.8 6.4 7.5 7.2 ns t enzl enab le p ad z to lo w 5.2 6.9 8.1 7.9 ns t enhz enab le p ad high to z 8.3 11.1 13.0 14.0 ns t enlz enab le p ad lo w to z 8.3 11.1 13.0 14.0 ns t glh g to p ad high 8.3 11.1 13.0 8.0 ns t ghl g to p ad lo w 8.9 11.9 14.0 9.0 ns t lsu i/o latch output setup 0.26 0.3 0.4 0.6 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 8.4 11.1 13.1 18.7 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 11.8 15.7 18.5 26.5 ns d tlh capacitiv e loading, lo w to high 0.03 0.0 0.05 0.07 ns/pf d thl capacitiv e loading, high to lo w 0.04 0.1 0.07 0.10 ns/pf t wdo hard-wired wide decode output 0.04 0.1 0.06 0.09 ns cmos output module timing 1 t dlh data to p ad high 3.7 4.9 7.1 9.1 ns t dhl data to p ad lo w 4.5 6.0 5.8 6.4 ns t enzh enab le p ad z to high 4.8 6.4 7.5 7.2 ns t enzl enab le p ad z to lo w 5.2 6.9 8.1 7.9 ns t enhz enab le p ad high to z 8.3 11.1 13.0 14.0 ns t enlz enab le p ad lo w to z 8.3 11.1 13.0 14.0 ns t glh g to p ad high 8.3 11.1 13.0 8.0 ns t ghl g to p ad lo w 8.9 11.9 14.0 9.0 ns t lsu i/o latch setup 0.26 0.3 0.4 0.6 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 9.9 13.2 15.5 22.3 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 13.9 18.5 21.8 31.2 ns d tlh capacitiv e loading, lo w to high 0.04 0.1 0.07 0.10 ns/pf d thl capacitiv e loading, high to lo w 0.04 0.1 0.06 0.09 ns/pf t wdo hard-wired wide decode output 0.04 0.1 0.06 0.09 ns 1- 60 a32300dx timing characteristics (w orst-case commer cial conditions) logic module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units combinatorial functions t pd inter nal arr a y module dela y 2.2 2.9 3.4 5.2 ns t pdd inter nal decode module dela y 2.5 3.3 3.9 5.7 ns predicted module routing dela ys t rd1 fo=1 routing dela y 1.1 1.5 1.8 3.3 ns t rd2 fo=2 routing dela y 1.7 2.3 2.7 4.3 ns t rd3 fo=3 routing dela y 2.4 3.1 3.7 5.2 ns t rd4 fo=4 routing dela y 2.9 3.9 4.6 6.5 ns t rd5 fo=8 routing dela y 5.2 7.0 8.2 10.0 ns t rdd decode-to-output routing dela y 0.6 0.8 0.9 0.4 ns sequential timing characteristics t co flip-flop cloc k-to-output 2.3 3.1 3.6 5.0 ns t go latch gate-to-output 2.2 2.9 3.4 5.0 ns t su flip-flop (latch) setup time 0.3 0.3 0.5 0.7 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 ns t r o flip-flop (latch) reset to output 2.2 3.0 3.5 5.0 ns t suena flip-flop (latch) enab le setup 0.6 0.9 1.0 1.4 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 3.1 4.2 4.9 7.0 ns t w asyn flip-flop (latch) asynchronous pulse width 3.5 4.7 5.5 7.0 ns 1- 61 integrator series fpgas C 1200xl and 3200dx familes a32300dx timing characteristics (continued) (w orst-case commer cial conditions) logic module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units sync hr onous sram operations t rc read cycle time 6.4 8.5 10.0 14.3 ns t wc wr ite cycle time 6.4 8.5 10.0 14.3 ns t rckhl cloc k high/lo w time 3.2 4.3 5.0 7.1 ns t rco data v alid after cloc k high/lo w 3.2 4.3 5.0 7.1 ns t adsu address/data setup time 1.5 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 ns t rensu read enab le setup 0.6 0.8 0.9 1.4 ns t renh read enab le hold 3.2 4.3 5.0 0.7 ns t wensu wr ite enab le setup 2.6 3.4 4.0 5.4 ns t wenh wr ite enab le hold 0.0 0.0 0.0 0.0 ns t bens bloc k enab le setup 2.6 3.5 4.1 5.6 ns t benh bloc k enab le hold 0.0 0.0 0.0 0.0 ns async hr onous sram operations t rpd asynchronous access time 7.7 10.2 12.0 17.2 ns t rd ad v read address v alid 8.3 11.1 13.0 18.6 ns t adsu address/data setup time 1.5 2.0 2.4 3.4 ns t adh address/data hold time 0.0 0.0 0.0 0.0 ns t rensu a read enab le setup to address v alid 0.57 0.8 0.9 1.4 ns t renha read enab le hold 3.2 4.3 5.0 7.1 ns t wensu wr ite enab le setup 2.6 3.4 4.0 5.4 ns t wenh wr ite enab le hold 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.1 1.5 1.8 2.6 ns 1- 62 a32300dx timing characteristics (continued) (w orst-case commer cial conditions) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. input module pr opa gation dela ys C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units t inpy input data p ad to y 1.4 1.9 2.2 2.9 ns t ingo input latch gate-to-output 1 2.9 3.8 4.5 5.0 ns t inh input latch hold 1 0.0 0.0 0.0 0.0 ns t insu input latch setup 1 0.45 0.6 0.7 0.6 ns t ila latch activ e pulse width 1 4.4 5.9 6.9 7.0 ns input module predicted routing dela ys t ird1 fo=1 routing dela y 1.9 2.6 3.0 6.1 ns t ird2 fo=2 routing dela y 2.5 3.3 3.9 7.0 ns t ird3 fo=3 routing dela y 3.3 4.4 5.2 7.6 ns t ird4 fo=4 routing dela y 3.9 5.2 6.1 8.7 ns t ird5 fo=8 routing dela y 5.0 6.7 7.9 8.7 ns t rdd decode-to-output routing dela y 0.6 0.8 0.9 ns global cloc k netw ork t ckh input lo w to high fo=32 fo=635 6.4 7.3 8.6 9.7 10.1 11.4 8.4 9.9 ns ns t ckl input high to lo w fo=32 fo=635 6.6 7.1 8.8 9.5 10.3 11.2 8.4 11.3 ns ns t pwh minim um pulse width high fo=32 fo=635 3.0 3.3 4.0 4.3 4.7 5.1 6.1 6.6 ns ns t pwl minim um pulse width lo w fo=32 fo=635 3.0 3.3 4.0 4.3 4.7 5.1 6.1 6.6 ns ns t cksw maxim um sk e w fo=32 fo=635 0.6 0.6 0.9 0.9 1.0 1.0 1.4 1.4 ns ns t suext input latch exter nal setup fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch exter nal hold fo=32 fo=635 2.2 2.7 2.9 3.7 3.4 4.3 4.9 6.1 ns ns t p minim um p er iod (1/fmax) fo=32 fo=635 5.5 6.1 7.4 8.2 9.3 10.2 12.4 13.7 ns ns f hmax maxim um datapath f requency fo=32 fo=635 153.8 140.9 123.1 112.7 107 98 74.9 68.6 mhz mhz 1- 63 integrator series fpgas C 1200xl and 3200dx familes a32300dx timing characteristics (continued) (w orst-case commer cial conditions) notes: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note on page 4-125. output module timing C2 speed C1 speed std speed Cf speed p arameter description min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 3.7 4.9 5.8 4.8 ns t dhl data to p ad lo w 4.4 5.9 6.9 6.2 ns t enzh enab le p ad z to high 4.8 6.4 7.5 7.2 ns t enzl enab le p ad z to lo w 5.1 6.8 8.0 7.9 ns t enhz enab le p ad high to z 8.3 11.1 13.0 14.0 ns t enlz enab le p ad lo w to z 8.3 11.1 13.0 14.0 ns t glh g to p ad high 4.3 5.7 6.7 8.0 ns t ghl g to p ad lo w 5.4 7.1 8.4 9.0 ns t lsu i/o latch output setup 0.26 0.3 0.4 0.6 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 8.4 11.1 13.1 18.7 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 11.8 15.7 18.5 26.5 ns d tlh capacitiv e loading, lo w to high 0.26 0.3 0.4 0.07 ns/pf d thl capacitiv e loading, high to lo w 0.32 0.4 0.5 0.10 ns/pf t wdo hard-wired wide decode output 0.03 0.04 0.05 0.09 ns cmos output module timing 1 t dlh data to p ad high 4.4 5.9 6.9 9.1 ns t dhl data to p ad lo w 3.7 4.9 5.8 6.4 ns t enzh enab le p ad z to high 4.8 6.4 7.5 7.2 ns t enzl enab le p ad z to lo w 5.1 6.8 8.0 7.9 ns t enhz enab le p ad high to z 8.3 11.1 13.0 14.0 ns t enlz enab le p ad lo w to z 8.3 11.1 13.0 14.0 ns t glh g to p ad high 4.3 5.7 6.7 8.0 ns t ghl g to p ad lo w 5.4 7.1 8.4 9.0 ns t lsu i/o latch setup 0.26 0.34 0.4 0.6 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 ns t lco i/o latch cloc k-out (p ad-to-p ad) 32 i/o 9.9 13.2 15.5 22.3 ns t a co arr a y latch cloc k-out (p ad-to-p ad) 32 i/o 13.9 18.5 21.8 31.2 ns d tlh capacitiv e loading, lo w to high 0.32 0.4 0.5 0.10 ns/pf d thl capacitiv e loading, high to lo w 0.26 0.3 0.4 0.09 ns/pf t wdo hard-wired wide decode output 0.03 0.04 0.05 0.09 ns 1- 64 package pin assignments 84-pin plcc package (top view) 1 84 84-pin plcc 1- 65 integrator series fpgas C 1200xl and 3200dx familes notes: 1. i/o (wd) : denotes i/o pin with an associated wide decode module 2. wide decode i/o (wd) can also be general purpose user i/o 3. nc : denotes no connection 4. all unlisted pin numbers are user i/os 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 84-pin plcc package pin number a1225xl function a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function 2 clkb ,i/o clkb ,i/o clkb ,i/o clkb ,i/o clkb , i/o clkb , i/o 4 prb ,i/o prb ,i/o prb ,i/o prb ,i/o prb , i/o prb , i/o 5 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 6 gnd gnd gnd gnd gnd gnd 7 i/o i/o i/o i/o qclkc , i/o i/o 8 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 9 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 10 dclk,i/o dclk,i/o dclk,i/o dclk,i/o dclk, i/o dclk, i/o 12 mode (gnd) mode (gnd) mode (gnd) mode (gnd) mode (gnd) mode (gnd) 22 vcc vcc vcc vcc vcc vcc 23 vcc vcc vcc vcc vcc vcc 28 gnd gnd gnd gnd gnd gnd 34 i/o i/o i/o i/o tms , i/o tms , i/o 35 i/o i/o i/o i/o tdi, i/o tdi, i/o 36 i/o i/o i/o i/o i/o (wd) i/o (wd) 37 i/o i/o i/o i/o qclka, i/o i/o 38 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 39 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 43 vcc vcc vcc vcc vcc vcc 44 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 45 i/o i/o i/o i/o qclkb , i/o i/o (wd) 46 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 47 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 49 gnd gnd gnd gnd gnd gnd 50 i/o i/o i/o i/o i/o (wd) i/o (wd) 51 i/o i/o i/o i/o i/o (wd) i/o (wd) 52 i/o i/o i/o i/o tdo , i/o tdo , i/o 53 i/o i/o i/o i/o i/o i/o 62 i/o i/o i/o i/o tck, i/o tck, i/o 63 gnd gnd gnd gnd gnd gnd 64 vcc vcc vcc vcc vcc vcc 65 vcc vcc vcc vcc vcc vcc 70 gnd gnd gnd gnd gnd gnd 76 sdi,i/o sdi,i/o sdi,i/o sdi,i/o sdi, i/o sdi, i/o 78 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 79 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 80 i/o i/o i/o (wd) i/o qclkd , i/o i/o (wd) 81 pra,i/o pra,i/o pra,i/o pra,i/o pra, i/o pra, i/o 83 clka,i/o clka,i/o clka,i/o clka,i/o clka, i/o clka, i/o 84 vcc vcc vcc vcc vcc vcc 1- 66 package pin assignments (continued) 100-pin pqfp package, 100-pin vqfp package (top view) 100-pin pqfp 1 100 1 100-pin vqfp 100 1- 67 integrator series fpgas C 1200xl and 3200dx familes 100-pin pqfp package, 100-pin vqfp package pin number a1225xl- pq100 function a1225xl- vq100 function a1240xl- pq100 function a3256dx pq100 function 2 dclk, i/o mode (gnd) dclk, i/o dclk, i/o 4 mode (gnd) i/o mode (gnd) mode (gnd) 7 i/o gnd i/o i/o 9 gnd i/o gnd gnd 14 i/o vcc i/o i/o 15 i/o vcc i/o i/o 16 vcc i/o vcc vcc 17 vcc i/o vcc vcc 20 i/o gnd i/o i/o 22 gnd i/o gnd gnd 32 i/o gnd i/o i/o 34 gnd i/o gnd gnd 35 i/o i/o i/o i/o (wd) 36 i/o i/o i/o i/o (wd) 37 i/o i/o i/o i/o (wd) 38 i/o vcc i/o i/o (wd) 40 vcc i/o vcc vcc 41 i/o i/o i/o i/o (wd) 42 i/o i/o i/o i/o (wd) 44 i/o gnd i/o i/o (wd) 45 i/o i/o i/o i/o (wd) 46 gnd i/o gnd gnd 47 i/o i/o i/o i/o (wd) 48 i/o i/o i/o i/o (wd) 55 i/o gnd i/o i/o 57 gnd i/o gnd gnd 62 i/o gnd i/o i/o 63 i/o vcc i/o i/o 64 gnd vcc gnd gnd 65 vcc vcc vcc vcc 66 vcc i/o vcc vcc 67 vcc i/o vcc vcc 70 i/o gnd i/o i/o 72 gnd i/o gnd gnd 77 i/o sdi, i/o i/o i/o 79 sdi, i/o i/o sdi, i/o sdi, i/o 81 i/o i/o i/o i/o (wd) 82 i/o gnd i/o i/o (wd) 83 i/o i/o i/o i/o (wd) 84 gnd i/o gnd gnd 85 i/o pra, i/o i/o i/o (wd) 86 i/o i/o i/o i/o (wd) 1- 68 notes: 1. nc : denotes no connection 2. all unlisted pin numbers are user i/os 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 4. i/o (wd): denotes i/o pin with an associated wide decode module 87 pra, i/o clka, i/o pra, i/o pra, i/o 88 i/o vcc i/o i/o 89 clka, i/o i/o clka, i/o clka, i/o 90 vcc clkb , i/o vcc vcc 92 clkb , i/o prb , i/o clkb , i/o clkb , i/o 94 prb , i/o gnd prb , i/o prb , i/o 95 i/o i/o i/o i/o (wd) 96 gnd i/o gnd gnd 99 i/o i/o i/o i/o (wd) 100 i/o dclk, i/o i/o i/o (wd) 100-pin pqfp package, 100-pin vqfp package (continued) pin number a1225xl- pq100 function a1225xl- vq100 function a1240xl- pq100 function a3256dx pq100 function 1- 69 integrator series fpgas C 1200xl and 3200dx familes package pin assignments (continued) 144-pin pqfp package (top view) 144 1 144 -pin pqfp 1- 70 notes: 1. nc : denotes no connection 2. all unlisted pin numbers are user i/os 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 144-pin pqfp package pin number a1240xl function pin number a1240xl function 2 mode (gnd) 89 vcc 9 gnd 90 vcc 10 gnd 91 vcc 11 gnd 92 vcc 18 vcc 93 vcc 19 vcc 100 gnd 20 vcc 101 gnd 21 vcc 102 gnd 28 gnd 110 sdi, i/o 29 gnd 116 gnd 30 gnd 117 gnd 44 gnd 118 gnd 45 gnd 123 pra, i/o 46 gnd 125 clka, i/o 54 vcc 126 vcc 55 vcc 127 vcc 56 vcc 128 vcc 64 gnd 130 clkb , i/o 65 gnd 132 prb , i/o 79 gnd 136 gnd 80 gnd 137 gnd 81 gnd 138 gnd 88 gnd 144 dclk, i/o 1- 71 integrator series fpgas C 1200xl and 3200dx familes package pin assignments (continued) 160-pin pqfp package (top view) notes: 1. i/o (wd) : denotes i/o pin with an associated wide decode module 2. wide decode i/o (wd) can also be general purpose user i/o 3. nc : denotes no connection 4. all unlisted pin numbers are user i/os 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 160 1 160 -pin pqfp 1- 72 160-pin pqfp package pin number a3265dx function a1280xl function a32100dx function a32140dx function 2 dclk,i/o dclk,i/o dclk dclk,i/o 4 i/o i/o i/o (wd) i/o (wd) 5 i/o (wd) i/o i/o (wd) i/o (wd) 6 vcc vcc vcc vcc 7 i/o (wd) i/o i/o i/o 11 gnd gnd gnd gnd 12 i/o i/o qclkc , i/o i/o 13 i/o (wd) i/o i/o (wd) i/o (wd) 14 i/o (wd) i/o i/o (wd) i/o (wd) 16 prb ,i/o prb ,i/o prb , i/o prb ,i/o 18 clkb ,i/o clkb ,i/o clkb , i/o clkb ,i/o 20 vcc vcc vcc vcc 21 clka,i/o clka,i/o clka, i/o clka,i/o 23 pra,i/o pra,i/o pra, i/o pra,i/o 24 i/o i/o i/o (wd) i/o (wd) 25 i/o (wd) i/o i/o (wd) i/o (wd) 26 i/o (wd) i/o i/o i/o 28 i/o i/o qclkd i/o 29 i/o (wd) i/o i/o (wd) i/o (wd) 30 gnd gnd gnd gnd 31 i/o (wd) i/o i/o (wd) i/o (wd) 33 i/o i/o nc i/o 34 i/o (wd) i/o nc i/o 35 vcc vcc vcc vcc 36 i/o (wd) i/o i/o (wd) i/o (wd) 37 i/o i/o i/o (wd) i/o (wd) 38 sdi,i/o sdi,i/o sdi, i/o sdi,i/o 40 gnd gnd gnd gnd 44 gnd gnd gnd gnd 49 gnd gnd gnd gnd 54 vcc vcc vcc vcc 57 vcc vcc vcc vcc 58 vcc vcc vcc vcc 59 gnd gnd gnd gnd 60 vcc vcc vcc vcc 61 gnd gnd gnd gnd 62 i/o i/o tck, i/o tck, i/o 64 gnd gnd gnd gnd 69 gnd gnd gnd gnd 80 gnd gnd gnd gnd 82 i/o i/o sdo , i/o tdo , i/o 83 i/o i/o i/o (wd) i/o (wd) 1- 73 integrator series fpgas C 1200xl and 3200dx familes 84 i/o i/o i/o (wd) i/o (wd) 86 vcc vcc vcc vcc 87 i/o (wd) i/o i/o i/o 88 i/o (wd) i/o i/o (wd) i/o (wd) 89 gnd gnd gnd gnd 90 i/o i/o i/o (wd) i/o 91 i/o i/o qclkb , i/o i/o 92 i/o (wd) i/o i/o i/o 93 i/o (wd) i/o i/o i/o 95 i/o i/o i/o (wd) i/o 96 i/o (wd) i/o i/o (wd) i/o (wd) 97 i/o (wd) i/o i/o i/o 98 vcc vcc vcc vcc 99 gnd gnd gnd gnd 106 i/o (wd) i/o i/o (wd) i/o (wd) 107 i/o (wd) i/o i/o (wd) i/o (wd) 109 gnd gnd gnd gnd 110 i/o i/o qclka, i/o i/o 111 i/o (wd) i/o i/o i/o (wd) 112 i/o (wd) i/o i/o i/o (wd) 114 vcc vcc vcc vcc 115 i/o i/o i/o (wd) i/o (wd) 116 i/o i/o i/o (wd) i/o (wd) 118 i/o i/o tdi, i/o tdi, i/o 119 i/o i/o tms , i/o tms , i/o 120 gnd gnd gnd gnd 125 gnd gnd gnd gnd 130 gnd gnd gnd gnd 135 vcc vcc vcc vcc 138 vcc vcc vcc vcc 139 vcc vcc vcc vcc 140 gnd gnd gnd gnd 145 gnd gnd gnd gnd 150 vcc vcc vcc vcc 155 gnd gnd gnd gnd 159 mode (gnd) mode (gnd) mode (gnd) mode (gnd) 160 gnd gnd gnd gnd 160-pin pqfp package (continued) pin number a3265dx function a1280xl function a32100dx function a32140dx function 1- 74 package pin assignments (continued) 208-pin pqfp package, 208-pin rqfp package (top view) notes: 1. i/o (wd) : denotes i/o pin with an associated wide decode module 2. wide decode i/o (wd) can also be general purpose user i/o 3. nc : denotes no connection 4. all unlisted pin numbers are user i/os 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 6. rqfp has an exposed circular metal heatsink on the top surface. 208 -pin pqfp 208-pin rqfp 1 208 1- 75 integrator series fpgas C 1200xl and 3200dx familes 208-pin pqfp package, 208-pin rqfp package pin number a1280xl function a32100dx function a32140dx function a32200dx- pq208 function a32200dx- rq208 function a32300dx function 1 gnd gnd gnd gnd i/o i/o 2 nc vcc vcc vcc dclk, i/o dclk, i/o 3 mode (gnd) mode (gnd) mode (gnd) mode (gnd) i/o i/o 5 i/o i/o i/o i/o i/o (wd) i/o (wd) 6 i/o i /o i/o i/o i/o (wd) i/o (wd) 7 i/o i/o i/o i/o vcc vcc 9 nc nc i/o i/o i/o i/o 10 nc nc i/o i/o i/o i/o 11 nc nc i/o i/o i/o i/o 13 i/o i/o i/o i/o qclkc , i/o qclkc , i/o 15 i/o i/o i/o i/o i/o (wd) i/o (wd) 16 nc nc i/o i/o i/o (wd) i/o (wd) 17 vcc vcc vcc vcc i/o i/o 19 i/o i/o i/o i/o i/o (wd) i/o (wd) 20 i/o i/o i/o i/o i/o (wd) i/o (wd) 22 gnd gnd gnd gnd prb , i/o prb , i/o 24 i/o i/o i/o i/o clkb , i/o clkb , i/o 26 i/o i /o i/o i/o gnd gnd 27 gnd gnd gnd gnd vcc vcc 28 vcc vcc vcc vcc i/o i/o 29 vcc vcc vcc vcc clka, i/o clka, i/o 30 i/o i/o i/o i/o pra, i/o pra, i/o 32 vcc vcc vcc vcc i/o (wd) i/o (wd) 33 i/o i/o i/o i/o i/o (wd) i/o (wd) 38 i/o i/o i/o i/o qclkd , i/o qclkd , i/o 40 i/o i /o i/o i/o i/o (wd) i/o (wd) 41 nc nc i/o i/o i/o (wd) i/o (wd) 42 nc nc i/o i/o i/o i/o 43 nc nc i/o i/o i/o i/o 45 i/o i/o i/o i/o vcc vcc 47 i/o i/o i/o i/o i/o (wd) i/o (wd) 48 i/o i/o i/o i/o i/o (wd) i/o (wd) 50 nc nc i/o i/o sdi, i/o sdi, i/o 51 nc nc i/o i/o i/o i/o 52 gnd gnd gnd gnd gnd gnd 53 gnd gnd gnd gnd i/o i/o 54 i/o tms , i/o tms , i/o tms , i/o i/o i/o 55 i/o tdi, i/o tdi, i/o tdi, i/o i/o i/o 57 i/o i/o i/o (wd) i/o (wd) i/o i/o 58 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 59 i/o i/o (wd) i/o i/o gnd gnd 60 vcc vcc vcc vcc i/o i/o 61 nc i/o i/o i/o i/o i/o 62 nc i/o i/o i/o i/o i/o 65 i/o qclka, i/o i/o qclka, i/o i/o i/o 66 i/o i/o i/o (wd) i/o (wd) i/o i/o 67 nc nc i/o (wd) i/o (wd) i/o i/o 68 nc i/o i/o i/o i/o i/o 1- 76 70 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 71 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 74 i/o i/o i/o i/o vcc vcc 77 i/o i/o i/o i/o vcc vcc 78 gnd gnd gnd gnd vcc vcc 79 vcc vcc vcc vcc vcc vcc 80 nc vcc vcc vcc gnd gnd 81 i/o i/o i/o i/o tck, i/o tck, i/o 83 i/o i/o i/o i/o gnd gnd 85 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 86 i/o i/o (wd) i/o (wd) i/o (wd) i/o i /o 89 nc i/o i/o i/o i/o i/o 90 nc i/o i/o i/o i/o i/o 91 i/o qclkb , i/o i/o qclkb , i/o i/o i/o 93 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 94 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 95 nc i/o i/o i/o i/o i/o 96 nc nc i/o i/o i/o i/o 97 nc nc i/o i/o i/o i/o 98 vcc vcc vcc vcc i/o i/o 100 i/o i/o (wd) i/o (wd) i/o (wd) i/o i /o 101 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 103 i/o sdo , i/o tdo , i/o tdo , i/o vcc vcc 104 i/o i/o i/o i/o gnd gnd 105 gnd gnd gnd gnd i/o i/o 106 nc vcc vcc vcc tdo , i/o sdo/tdo , i/o 107 i/o i/o i/o i/o i/o (wd) i/o (wd) 108 i/o i/o i/o i/o i/o (wd) i/o (wd) 110 i/o i/o i/o i/o vcc vcc 112 nc nc i/o i/o i/o i/o 113 nc nc i/o i/o i/o i/o 114 nc nc i/o i/o i/o (wd) i/o (wd) 115 nc nc i/o i/o i/o (wd) i/o (wd) 117 i/o i/o i/o i/o qclkb , i/o qclkb , i/o 121 i/o i/o i/o i/o i/o (wd) i/o (wd) 122 i/o i/o i/o i/o i/o (wd) i/o (wd) 126 gnd gnd gnd gnd i/o i/o (wd) 127 i/o i/o i/o i/o i/o i/o (wd) 128 i/o tck, i/o tck, i/o tck, i/o i/o i/o 129 gnd gnd gnd gnd vcc vcc 130 vcc vcc vcc vcc gnd gnd 131 gnd gnd gnd gnd i/o i/o 132 vcc vcc vcc vcc i/o i/o 133 vcc vcc vcc vcc i/o i/o 136 vcc vcc vcc vcc i/o i/o 137 i/o i/o i/o i/o i/o (wd) i/o (wd) 138 i/o i/o i/o i/o i/o (wd) i/o (wd) 141 nc i/o i/o i/o i/o (wd) i/o (wd) 208-pin pqfp package, 208-pin rqfp package (continued) pin number a1280xl function a32100dx function a32140dx function a32200dx- pq208 function a32200dx- rq208 function a32300dx function 1- 77 integrator series fpgas C 1200xl and 3200dx familes 142 i/o i/o i/o i/o i/o (wd) i/o (wd) 144 i/o i/o i/o i/o qclka, i/o qclka, i/o 146 nc nc i/o i/o i/o i/o 147 nc nc i/o i/o i/o i/o 148 nc nc i/o i/o i/o i/o 149 nc nc i/o i/o vcc vcc 150 gnd gnd gnd gnd i/o i/o 151 i/o i/o i/o i/o i/o (wd) i/o (wd) 152 i/o i/o i/o i/o i/o (wd) i/o (wd) 154 i/o i/o i/o i/o tdi, i/o tdi, i/o 155 i/o i/o i/o i/o tms , i/o tms , i/o 156 i/o i/o i/o i/o gnd gnd 157 gnd gnd gnd gnd vcc vcc 159 sdi,i/o sdi, i/o sdi,i/o sdi,i/o i/o i/o 161 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 162 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 164 vcc vcc vcc vcc i/o i/o 165 nc nc i/o i/o i/o i/o 166 nc nc i/o i/o i/o i/o 168 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 169 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 171 nc qclkd , i/o i/o qclkd , i/o i/o i/o 176 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 177 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 178 pra,i/o pra, i/o pra,i/o pra,i/o vcc vcc 180 clka,i/o clka, i/o clka,i/o clka,i/o i/o i/o 181 nc i/o i/o i/o vcc vcc 182 nc vcc vcc vcc vcc vcc 183 vcc vcc vcc vcc i/o i/o 184 gnd gnd gnd gnd i/o i/o 186 clkb ,i/o clkb clkb ,i/o clkb ,i/o i/o i/o 187 i/o i/o i/o i/o gnd gnd 188 prb ,i/o prb , i/o prb ,i/o prb ,i/o i/o i/o 190 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 191 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 193 nc i/o i/o i/o i/o i/o 194 nc nc i/o (wd) i/o (wd) i/o i/o 195 nc i/o i/o (wd) i/o (wd) i/o i/o 196 i/o qclkc , i/o i/o qclkc , i/o i/o i/o 197 nc nc i/o i/o i/o i/o 201 nc i/o i/o i/o i/o i/o 202 vcc vcc vcc vcc i/o i/o 203 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 204 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 206 i/o i/o i/o i/o mode mode (gnd) 207 dclk,i/o dclk, i/o dclk,i/o dclk,i/o vcc vcc 208 i/o i/o i/o i/o gnd gnd 208-pin pqfp package, 208-pin rqfp package (continued) pin number a1280xl function a32100dx function a32140dx function a32200dx- pq208 function a32200dx- rq208 function a32300dx function 1- 78 package pin assignments (continued) 240-pin rqfp package (top view) notes: 1. i/o (wd) : denotes i/o pin with an associated wide decode module 2. wide decode i/o (wd) can also be general purpose user i/o 3. nc : denotes no connection 4. all unlisted pin numbers are user i/os 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 6. rqfp has an exposed circular metal heatsink on the top surface. 240-pin rqfp exposed heatsink 1 240 1- 79 integrator series fpgas C 1200xl and 3200dx familes 240-pin rqfp package pin number a32200dx function a32300dx function pin number a32200dx function a32300dx function 2 dclk, i/o dclk, i/o 120 gnd gnd 6 i/o (wd) i/o (wd) 121 gnd gnd 7 i/o (wd) i/o (wd) 123 tdo , i/o tdo , i/o 8 vcc vcc 125 i/o (wd) i/o (wd) 15 qclkc , i/o qclkc , i/o 126 i/o (wd) i/o (wd) 17 i/o (wd) i/o (wd) 128 vcc vcc 18 i/o (wd) i/o (wd) 132 i/o (wd) i/o (wd) 21 i/o (wd) i/o (wd) 133 i/o (wd) i/o (wd) 22 i/o (wd) i/o (wd) 135 qclkb , i/o qclkb , i/o 24 prb , i/o prb , i/o 142 i/o (wd) i/o (wd) 26 clkb , i/o clkb , i/o 143 i/o (wd) i/o (wd) 28 gnd gnd 147 i/o i/o (wd) 29 vcc vcc 148 i/o i/o (wd) 30 vcc vcc 150 vcc vcc 32 clka, i/o clka, i/o 151 vcc vcc 33 i/o i/o (wd) 152 gnd gnd 34 pra, i/o pra, i/o 159 i/o (wd) i/o (wd) 37 i/o (wd) i/o (wd) 160 i/o (wd) i/o (wd) 38 i/o (wd) i/o (wd) 163 i/o (wd) i/o (wd) 45 qclkd , i/o qclkd , i/o 164 i/o (wd) i/o (wd) 47 i/o (wd) i/o (wd) 166 qclka, i/o qclka, i/o 48 i/o (wd) i/o (wd) 172 vcc vcc 52 vcc vcc 174 i/o (wd) i/o (wd) 54 i/o (wd) i/o (wd) 175 i/o (wd) i/o (wd) 55 i/o (wd) i/o (wd) 178 tdi, i/o tdi, i/o 57 sdi, i/o sdi, i/o 179 tms , i/o tms , i/o 59 vcc vcc 180 gnd gnd 60 gnd gnd 181 vcc vcc 61 gnd gnd 182 gnd gnd 71 vcc vcc 192 vcc vcc 85 vcc vcc 206 vcc vcc 88 vcc vcc 209 vcc vcc 89 vcc vcc 210 vcc vcc 90 vcc vcc 219 vcc vcc 91 gnd gnd 227 vcc vcc 92 tck, i/o tck, i/o 237 gnd gnd 94 gnd gnd 238 mode (gnd) mode (gnd) 108 vcc vcc 239 vcc vcc 118 vcc vcc 240 gnd gnd 119 gnd gnd 1- 80 package pin assignments (continued) 176-pin tqfp package (top view) notes: 1. i/o (wd) : denotes i/o pin with an associated wide decode module 2. wide decode i/o (wd) can also be general purpose user i/o 3. nc : denotes no connection 4. all unlisted pin numbers are user i/os 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 176-pin tqfp 176 1 1- 81 integrator series fpgas C 1200xl and 3200dx familes 176-pin tqfp package pin number a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function 1 gnd gnd gnd gnd gnd 2 mode mode mode mode mode 8 nc nc nc nc i/o 10 nc nc i/o i/o i/o 11 nc nc i/o i/o i/o 13 nc vcc vcc vcc vcc 18 gnd gnd gnd gnd gnd 19 nc i/o i/o i/o i/o 20 nc i/o i/o i/o i/o 22 nc i/o i/o i/o i/o 23 gnd gnd gnd gnd gnd 24 nc vcc vcc vcc vcc 25 vcc vcc vcc vcc vcc 26 nc i/o i/o i/o i/o 27 nc i/o i/o i/o i/o 28 vcc vcc vcc vcc vcc 29 nc nc i/o i/o i/o 33 nc nc nc nc i/o 37 nc nc i/o i/o i/o 38 nc nc nc nc i/o 45 gnd gnd gnd gnd gnd 46 i/o i/o i/o tms , i/o tms , i/o 47 i/o i/o i/o tdi, i/o tdi, i/o 48 i/o nc i/o i/o i/o 49 i/o i/o i/o i/o i/o (wd) 50 i/o i/o i/o i/o (wd) i/o (wd) 51 i/o i/o i/o i/o (wd) i/o 52 nc vcc vcc vcc vcc 54 nc i/o (wd) i/o i/o i/o 55 nc i/o (wd) i/o i /o i/o (wd) 56 i/o i/o i/o i/o i/o (wd) 57 nc nc nc qclka, i/o i/o 59 i/o i/o (wd) i/o i/o (wd) i/o (wd) 60 i/o i/o (wd) i/o i/o (wd) i/o (wd) 61 nc i/o i/o i/o i/o 64 nc i/o i/o i/o i/o 66 nc i/o i/o i/o i/o 67 gnd gnd gnd gnd gnd 68 vcc vcc vcc vcc vcc 69 i/o i/o (wd) i/o i/o i/o (wd) 70 i/o i/o (wd) i/o i/o i/o (wd) 72 i/o i/o i/o i/o (wd) i/o 73 i/o i/o (wd) i/o i/o (wd) i/o 1- 82 74 nc nc i/o i/o i/o 75 i/o i/o (wd) i/o i/o i/o 76 i/o i/o i/o qclkb , i/o i/o 77 nc nc nc i/o i/o (wd) 78 nc nc i/o i/o (wd) i/o (wd) 79 i/o i/o i/o i/o (wd) i/o 80 nc i/o (wd) i/o nc i/o 81 i/o i/o (wd) i/o i/o i/o 82 nc vcc vcc vcc vcc 84 i/o i/o i/o i/o (wd) i/o (wd) 85 i/o i/o i/o i/o (wd) i/o (wd) 86 nc nc i/o i/o i/o 87 i/o i/o i/o tdo , i/o tdo , i/o 89 gnd gnd gnd gnd gnd 96 nc nc i/o i/o i/o 97 nc i/o i/o i/o i/o 101 nc nc nc nc i/o 103 nc i/o i/o i/o i/o 106 gnd gnd gnd gnd gnd 107 nc i/o i/o i/o i/o 108 nc i/o i/o tck, i/o tck, i/o 109 gnd gnd gnd gnd gnd 110 vcc vcc vcc vcc vcc 111 gnd gnd gnd gnd gnd 112 vcc vcc vcc vcc vcc 113 vcc vcc vcc vcc vcc 114 nc i/o i/o i/o i/o 115 nc i/o i/o i/o i/o 116 nc vcc vcc vcc vcc 117 i/o nc i/o i/o i/o 121 nc nc nc i/o i/o 124 nc nc i/o i/o i/o 125 nc nc i/o i/o i/o 126 nc nc nc nc i/o 133 gnd gnd gnd gnd gnd 135 sdi,i/o sdi,i/o sdi,i/o sdi, i/o sdi,i/o 136 nc nc i/o i/o i/o 137 i/o i/o i/o i/o (wd) i/o (wd) 138 i/o i/o i/o i/o (wd) i/o (wd) 139 i/o i/o (wd) i/o i/o i/o 140 nc vcc vcc vcc vcc 141 i/o i/o (wd) i/o i/o i/o 142 i/o i/o i/o i/o (wd) i/o 176-pin tqfp package (continued) pin number a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function 1- 83 integrator series fpgas C 1200xl and 3200dx familes 143 nc i/o i/o i/o (wd) i/o 144 nc i/o (wd) i/o i/o i/o (wd) 145 nc nc nc nc i/o (wd) 146 i/o i/o (wd) i/o qclkd , i/o i/o 147 nc i/o i/o i/o i/o 149 i/o i/o (wd) i/o i/o i/o 150 i/o i/o (wd) i/o i/o (wd) i/o (wd) 151 nc i/o i/o i/o (wd) i/o (wd) 152 pra,i/o pra,i/o pra,i/o pra, i/o pra,i/o 154 clka,i/o clka,i/o clka,i/o clka, i/o clka,i/o 155 vcc vcc vcc vcc vcc 156 gnd gnd gnd gnd gnd 158 clkb ,i/o clkb ,i/o clkb ,i/o clkb , i/o clkb ,i/o 160 prb ,i/o prb ,i/o prb ,i/o prb , i/o prb ,i/o 161 nc i/o i/o i/o (wd) i/o (wd) 162 i/o i/o (wd) i/o i/o (wd) i/o (wd) 163 i/o i/o (wd) i/o i/o i/o 164 i/o i/o i/o qclkc , i/o i/o 165 nc nc nc nc i/o (wd) 166 nc i/o i/o i/o i/o (wd) 168 nc i/o i/o i /o i/o 169 i/o i/o (wd) i/o i/o i/o 170 nc vcc vcc vcc vcc 171 i/o i/o (wd) i/o i/o (wd) i/o (wd) 172 i/o i/o i/o i/o (wd) i/o (wd) 173 nc nc i/o i/o i/o 175 dclk,i/o dclk,i/o dclk,i/o dclk, i/o dclk,i/o 176-pin tqfp package (continued) pin number a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function 1- 84 package pin assignments (continued) 100-pin cpga (top view) signal p ad number location pra or i/o 85 a7 prb or i/o 92 a4 mode 2 c2 sdi or i/o 77 c8 dclk or i/o 100 c3 clka or i/o 87 c6 clkb or i/o 90 d6 gnd 7, 20, 32, 44, 55, 70, 82, 94 e3, g3, j5, j7, g9, f11, d10, c7, c5 v cc 15, 38, 64, 88 f3, g1, k6, f9, f10, e11, b6 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 1 a 2 3 4 5 6 7 8 9 10 11 b c d e f g h j k l a b c d e f g h j k l 100-pin cpga 1 2 3 4 5 6 7 8 9 10 11 or ientation pin 1- 85 integrator series fpgas C 1200xl and 3200dx familes package pin assignments (continued) 132-pin cpga (top view) signal p ad number location pra or i/o 113 b8 prb or i/o 121 c6 mode 2 a1 sdi or i/o 101 b12 dclk or i/o 132 c3 clka or i/o 115 b7 clkb or i/o 119 b6 gnd 9, 10, 26, 27, 41, 58, 59, 73, 74, 92, 93, 107, 108, 125, 126 e3, f4, j2, j3, l5, l9, m9, k12, j11, h13, e12, e11, c9, b9, b5, c5 v cc 18, 19, 49, 50, 83, 84, 116, 117 g3, g2, g4, l7, k7, g10, g11, g12, g13, d7, c7 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 132-pin cpga a b c d e f g h j k l m n a b c d e f g h j k l m n orientation pin 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 1- 86 package pin assignments (continued) 176-pin cpga (top view) signal p ad number location pra or i/o 152 c9 prb or i/o 160 d7 mode 2 c3 sdi or i/o 135 b14 dclk or i/o 175 b3 clka or i/o 154 a9 clkb or i/o 158 b8 gnd 1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89 101, 106, 111, 121, 126, 133, 145, 156, 165 d4, e4, g4, h4, k4, l4, m4, m6, m8, m10, m12 k12, j12, j13, h12, f12, e12, d12, d10, c8, d6 v cc 13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170 f4, h2, h3, j4, m5, n8, m11, j14, h13, h14, g12, d11, d8, d5 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 1 a 2 3 4 5 6 7 8 9 10 11 b c d e f g h j k l 176-pin cpga 1 2 3 4 5 6 7 8 9 10 11 12 12 13 13 14 14 15 15 m n p r a b c d e f g h j k l m n p r 1- 87 integrator series fpgas C 1200xl and 3200dx familes package pin assignments (continued) 84-pin cqfp notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. pin #1 inde x 1 84 84-pin cqfp 1- 88 84-pin cqfp package pin number a32100dx function pin number a32100dx function 1 gnd 51 tck, i/o 2 mode (gnd) 52 vks (gnd) 7 vcc 53 vpp (vcc) 10 gnd 55 vsv (vcc) 11 vcc 56 vcc 12 vsv (vcc) 59 gnd 17 gnd 63 gnd 22 gnd 64 sdi 23 tms , i/o 65 i/o (wd) 24 tdi, i/o 66 i/o (wd) 25 i/o (wd) 67 i/o (wd) 26 i/o (wd) 68 i/o (wd) 28 qclka, i/o 69 qclkd , i/o 30 i/o (wd) 70 i/o (wd) 32 gnd 71 i/o (wd) 33 vcc 72 pra, i/o 34 i/o (wd) 73 clka, i/o 35 i/o (wd) 74 vcc 36 qclkb , i/o 76 clkb , i/o 37 i/o (wd) 77 prb , i/o 38 gnd 78 i/o (wd) 39 i/o (wd) 79 i/o (wd) 40 i/o (wd) 80 qclkc , i/o 41 i/o (wd) 81 gnd 42 sdo , i/o 82 i/o (wd) 43 gnd 83 i/o (wd) 50 gnd 84 dclk, i/o 1- 89 integrator series fpgas C 1200xl and 3200dx familes package pin assignments (continued) 172-pin cqfp signal p ad number clka or i/o 150 clkb or i/o 154 dclk or i/o 171 gnd 7, 17, 22, 32, 37, 55, 65, 75, 98, 103, 106, 118, 123, 141, 152, 161 mode 1 pra or i/o 148 prb or i/o 156 sdi or i/o 131 v cc 12, 23, 24, 27, 66, 80, 107, 109, 110, 113, 136, 151, 166 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 172-pin cqfp pin #1 index 172 1 1- 90 |
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