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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit mc-45v16ab642 data sheet document no. e0027n10 (1st edition) (previous no. m15112ej2v0ds00) date published january 2001 cp (k) printed in japan 16m-word by 64-bit virtualchannel tm dynamic ram module unbuffered type elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the mc-45v16ab642 is a 16,777,216 words by 64 bits virtualchannel dynamic ram module on which 8 pieces of 128m virtualchannel dram : pd45v128821 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? 16,777,216 words by 64 bits organization ? clock frequency and access time from clk part number read clock access time maximum supply current ma latency frequency from clk operating refresh mhz (max.) ns (max.) prefetch restore channel auto self read / write (burst) MC-45V16AB642KF-A75 2 133 5.4 1,200 520 1,840 16 ? fully standard synchronous dynamic ram, with all signals referenced to a positive clock edge ? dual internal banks controlled by ba0 (bank select) ? wrap sequence (interleave) ? burst length (4) ? read latency (2) ? prefetch read latency (4) ? auto precharge and without auto precharge ? auto refresh and self refresh ? single 3.3 v 0.3 v power supply ? interface: lvttl ? refresh cycle: 4k cycles/64 ms ? 168-pin dual in-line memory module (pin pitch = 1.27 mm) ? unbuffered type ? serial pd
data sheet e0027n10 2 mc-45v16ab642 *"!+!,)-)! part number clock frequency mhz (max.) read latency prefetch read latency package mounted devices MC-45V16AB642KF-A75 133 2 4 168-pin dual in-line 8 pieces of pd45v128821g5 memory module (socket type) (10.16 mm (400) tsop (ii)) edge connector : gold plated 34.93 mm height
data sheet e0027n10 3 mc-45v16ab642 %! )!,+)! 168-pin dual in-line memory module socket type (edge connector: gold plated) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 v ss dq32 dq33 dq34 dq35 vcc dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 vcc nc v ss nc nc vcc /cas dqmb4 dqmb5 nc /ras v ss a1 a3 a5 a7 a9 ba0 (a13) a11 vcc clk1 nc v ss cke0 nc dqmb6 dqmb7 nc vcc nc nc nc nc v ss dq48 dq49 dq50 dq51 vcc dq52 nc nc nc v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 vcc dq60 dq61 dq62 dq63 v ss clk3 nc sa0 sa1 sa2 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 v ss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 nc nc v ss nc nc vcc /we dqmb0 dqmb1 /cs0 nc v ss a0 a2 a4 a6 a8 a10 a12 vcc vcc clk0 v ss nc /cs2 dqmb2 dqmb3 nc vcc nc nc nc nc v ss dq16 dq17 dq18 dq19 vcc dq20 nc nc nc v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 vcc dq28 dq29 dq30 dq31 v ss clk2 nc wp sda scl vcc dq46 dq47 nc a0 - a12 : address inputs [row: a0 - a12, column: a0 - a7] ba0 (a13) : virtualchannel dram bank select dq0 - dq63 : data inputs/outputs clk0 - clk3 : clock input cke0 : clock enable input /cs0, /cs2 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqmb0 - dqmb7 : dq mask enable sa0 - sa2 : address input for eeprom sda : serial data i/o for pd scl : clock input for pd v cc : power supply v ss : ground wp : write protect nc : no connection /xxx indicates active low signal.
data sheet e0027n10 4 mc-45v16ab642 )'1+- dqmb0 /cs0 /we dqmb2 /cs2 dqm d0 /cs /we dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 d1 dqm /cs /we dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 d6 dqm /cs /we dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 dq 7 d7 dqm /cs /we dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 d3 dqm /cs /we dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 dq 0 dq 4 dqm d2 /cs /we dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 dq 7 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dqmb1 dqmb7 dqmb6 dqmb3 dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 d4 dqm /cs /we dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 4 dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 dq 0 d5 dqm /cs /we dq 5 dq 7 dq 6 dq 4 dq 3 dq 2 dq 1 dq 0 dqmb4 dqmb5 a0 - a12 a0 - a12 : d0 - d7 ba0 a13 : d0 - d7 /ras /ras : d0 - d7 /cas /cas : d0 - d7 cke0 cke : d0 - d7 v cc d0 - d7 d0 - d7 ss v c clk1, clk3 10 pf clk2 clk : d2, d3, d6, d7 3.3 pf clk0 clk : d0, d1, d4, d5 3.3 pf serial pd scl sda a0 a1 a2 sa0 sa1 sa2 wp 47 k ? remarks 1. the value of all resistors is 10 ? except wp. 2. d0 - d7: pd45v128821 (8m words 8 bits 2 banks)
data sheet e0027n10 5 mc-45v16ab642 "''("',')!& ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 8 w operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il ? 0.3 +0.8 v operating ambient temperature t a 0 70 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a12, ba0 (a13), /ras, /cas, /we 38 62 pf c i2 clk0, clk2 24 40 c i3 cke0 32 52 c i4 /cs0, /cs2 17 29 c i5 dqmb0 - dqmb7 7 13 data input/output capacitance c i/o dq0 - dq63 7 13 pf
data sheet e0027n10 6 mc-45v16ab642 '"&'&2
"')--"!*"*("!+ )!*)!&!"&& "<&")"*4 parameter symbol test condition grade min. max. unit notes operating current (prefetch i cc1 p t rc t rc (min.) -a75 1,200 ma 1 mode at one bank active) prefetch is executed one time during t rc . operating current (restore i cc1 r t rc t rc (min.) -a75 1,200 ma 1 mode at one bank active) precharge standby current i cc2 p cke v il (max.) , t ck = 15 ns 9.6 ma in power down mode i cc2 ps cke v il (max.) , t ck = 9.6 precharge standby current in non power down mode i cc2 n cke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , input signals are changed one time during 30 ns. 160 ma i cc2 ns cke v ih (min.) , t ck = , input signals are stable. 80 active standby current in i cc3 p cke v il (max.) , t ck = 15 ns 48 ma power down mode i cc3 ps cke v il (max.) , t ck = 48 active standby current in i cc3 n cke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , 240 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke v ih (min.) , t ck = , input signals are stable. 160 operating current i cc4 t ck t ck (min.) , i o = 0 ma -a75 520 ma 2 (burst mode) background : precharge standby auto refresh current i cc5 t rcf t rcf (min.) -a75 1,840 ma 3 self refresh current i cc6 cke 0.2 v -a75 16 ma input leakage current i i (l) v i = 0 to 3.6 v, all other pins not under test = 0 v C8 +8 a output leakage current i o (l) d out is disabled, v o = 0 to 3.6 v C1.5 +1.5 a high level output voltage v oh i o = C 4.0 ma 2.4 v low level output voltage v ol i o = + 4.0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck (min.) . 2 . i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) .
data sheet e0027n10 7 mc-45v16ab642 '"&'&2
"')--"!*"*("!+ )!*)!&!"&&) "<&"!)"*4 "& )!*)!& ? ac measurements assume t t = 1 ns. ? reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . ? if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max.) . ? an access time is measured at 1.4 v. t ck t s t h t ds valid valid valid valid valid t ac hi-z hi-z t ac t lz t oh t hz t dh t ds t dh t ch t cl clk (input) command address dqm data (input) data (output) cke t cks t ckh t ck t cl
data sheet e0027n10 8 mc-45v16ab642 ' '"&'& parameter symbol -a75 unit note min. max. clock cycle time t ck2 7.5 ? ns access time from clk t ac2 ? 5.4 ns 1 clk high level width t ch 2.5 ? ns clk low level width t cl 2.5 ? ns data-out hold time t oh 2.7 ? ns 1 data-out low-impedance time t lz 0 ? ns data-out high-impedance time t hz2 2.5 5.4 ns data-in setup time t ds 1.5 ? ns data-in hold time t dh 0.8 ? ns address, command, dqm setup time t s 1.5 ? ns address, command, dqm hold time t h 0.8 ? ns cke setup time t cks 1.5 ? ns cke hold time t ckh 0.8 ? ns cke setup time (power down exit) t cksp 1.5 ? ns transition time t t 0.5 30 ns refresh time (4,096 refresh cycle) t ref ? 64 ms mode register set cycle time t rsc 2 ? clk note 1. output load. output z = 50 ? 50 pf
data sheet e0027n10 9 mc-45v16ab642 ' '"&'&2'1+)!*)'1+)!*)(")!4 parameter symbol -a75 unit notes min. max. same bank operation act to act / ref command period t rc 67.5 ? ns ref to ref / act command period t rcf 67.5 ? ns act to pre command period t ras 52.5 120,000 ns pre to act / ref command period t rp 20 ? ns act to pfc / pfca command delay time t apd 15 ? ns act to pfr command delay time (prefetch read operation) t aprd 15 ? ns pfc to pre command delay time t ppl 22.5 ? ns pfca / pfr to act / ref command delay time t pal 45 ? ns rst / rsta to act(r) note1 command delay time t rad 7.5 30 ns 2 same, other bank operation act(r) note1 to pfc / pfca / pfr command delay time t rpd 37.5 ? ns pfc to pfc / pfca command delay time t ppd 22.5 ? ns other bank operation act to act / act(r) or act(r) to act command delay time t rrd 15 ? ns act(r) to act(r) command delay time t rrdr 30 ? ns pfc / pfca to rst / rsta command delay time t prd 22.5 ? ns notes 1. act (r) command is act command after rst command. 2. the another background operation and same channel foreground operation are illegal while t rad period.
data sheet e0027n10 10 mc-45v16ab642 ' '"&'&2$)"+)!*)$)"+)!*)(")!4 parameter symbol -a75 unit note min. max. read/write to read/write command delay time t ccd 7.5 ? ns ac characteristics (background to foreground operation) (after same channel prefetch/restore) parameter symbol -a75 unit note min. max. pfc/pfca to read/write command delay time t pcd 15 ? ns act(r) to read/write command delay time t rcd 30 ? ns 1 note 1. act (r) command is act command after rst command.
data sheet e0027n10 11 mc-45v16ab642 "% (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written 80h 1 0 0 0 0 0 0 0 128 bytes into serial pd memory 1 total number of bytes of serial pd 08h 0 0 0 0 1 0 0 0 256 bytes memory 2 fundamental memory type 08h 0 0 0 0 1 0 0 0 vc dram 3 number of row addresses 0dh 0 0 0 0 1 1 0 1 13 rows 4 number of column addresses 08h 0 0 0 0 1 0 0 0 8 columns 5 number of banks 01h 0 0 0 0 0 0 0 1 1 bank 6 data width 40h 0 1 0 0 0 0 0 0 64 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface standard 01h 0 0 0 0 0 0 0 1 lvttl 9 read latency (/cas latency) = 2 -a75 75h 0 1 1 1 0 1 0 1 7.5 ns cycle time 10 read latency (/cas latency) = 2 -a75 54h 0 1 0 1 0 1 0 0 5.4 ns access time 11 dimm configuration type 00h 0 0 0 0 0 0 0 0 none 12 refresh rate / type 80h 1 0 0 0 0 0 0 0 normal 13 vc dram width 08h 0 0 0 0 1 0 0 0 8 14 error checking dram width 00h 0 0 0 0 0 0 0 0 none 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 04h 0 0 0 0 0 1 0 0 4 17 number of banks on each vc dram 02h 0 0 0 0 0 0 1 0 2 banks 18 read latency (/cas latency) supported 02h 0 0 0 0 0 0 1 0 2 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 01h 0 0 0 0 0 0 0 1 0 21 vc dram module attributes 00h 0 0 0 0 0 0 0 0 22 vc dram device attributes : general 0eh 0 0 0 0 1 1 1 0 23-26 00h 0 0 0 0 0 0 0 0 27 t rp (min.) -a75 14h 0 0 0 1 0 1 0 0 20 ns 28 t rrd (min.) -a75 0fh 0 0 0 0 1 1 1 1 15 ns 29 t apd (min.) -a75 0fh 0 0 0 0 1 1 1 1 15 ns 30 t ras (min.) -a75 34h 0 0 1 1 0 1 0 0 52.5 ns
data sheet e0027n10 12 mc-45v16ab642 (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 31 module bank density 20h 0 0 1 0 0 0 0 0 128m bytes 32 address and command signal -a75 15h 0 0 0 1 0 1 0 1 1.5 ns input setup time 33 address and command signal -a75 08h 0 0 0 0 1 0 0 0 0.8 ns input hold time 34 data signal input setup time -a75 15h 0 0 0 1 0 1 0 1 1.5 ns 35 data signal input hold time -a75 08h 0 0 0 0 1 0 0 0 0.8 ns 36 prefetch read latency -a75 04h 0 0 0 0 0 1 0 0 4 clocks 37 t pcd (min.) -a75 0fh 0 0 0 0 1 1 1 1 15 ns 38 number of segment addresses 02h 0 0 0 0 0 0 1 0 2 bits 39 number of channels 04h 0 0 0 0 0 1 0 0 16 40 depth of channels 08h 0 0 0 0 1 0 0 0 256 bits 41-61 62 spd revision 02h 0 0 0 0 0 0 1 0 2.0 63 checksum for bytes 0 - 62 -a75 34h 0 0 1 1 0 1 0 0 64-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91-92 revision code 93-94 manufacturing date 95-98 assembly serial number 99-125 mfg specific timing charts please refer to the pd45v128421, 45v128821, 45v128161 data sheet (e0025n).
data sheet e0027n10 13 mc-45v16ab642 %'1+"<!+ 168 pin dual in-line module (socket type) item millimeters b a d 6.35 c 36.83 d1 2.0 133.35 11.43 d2 g 6.35 e 54.61 h 1.27 (t.p.) i 8.89 3.125 j y2 2.26 24.495 z1 z2 2.26 3.0 min. k 42.18 l 17.78 m x 2.54 0.10 y1 3.0 min. a1 133.35 0.13 m1 15.15 m2 19.78 n 3.0 max. p 1.0 q r2.0 r2 9.53 s 3.0 t u 4.0 min. 1.27 0.1 v 0.2 0.15 r1 4.0 0.10 w 1.0 0.05 34.93 0.13 r2 f1 r1 j h d q u t detail of b part d2 p d1 a (optional holes) s n z1 a (area b) y1 c b e a1 (area a) l m y2 z2 f2 detail of a part w x v k g i b m2 (area a) m1 (area b) f1 f2 3.18 2.44
data sheet e0027n10 14 mc-45v16ab642 revision history edition / date page description this edition previous edition type of edition location nec corporation (m15112e) 1st edition / ? ? ? ? sep. 2000 2nd edition / p.1, 2 p.1, 2 deletion -a10 dec. 2000 p.6, 8, 9, 10, 11, 12 p.6, 8, 9, 10, 11, 12 -a10 specs elpida memory, inc. (e0027n) 1st edition / ? ? ? republished by elpida memory, inc. jan. 2001
data sheet e0027n10 15 mc-45v16ab642 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-45v16ab642 the names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company. caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. m8e 00. 4 the information in this document is current as of december, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of elpida's data sheets or data books, etc., for the most up-to-date specifications of elpida semiconductor products. not all products and/or types are available in every country. please check with an elpida memory, inc. for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of elpida. elpida assumes no responsibility for any errors that may appear in this document. elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of elpida semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while elpida endeavours to enhance the quality, reliability and safety of elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. elpida semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of elpida semiconductor products is "standard" unless otherwise expressly specified in elpida's data sheets or data books, etc. if customers wish to use elpida semiconductor products in applications not intended by elpida, they must contact an elpida memory, inc. in advance to determine elpida's willingness to support a given application. (note) (1) "elpida" as used in this statement means elpida memory, inc. and also includes its majority-owned subsidiaries. (2) "elpida semiconductor products" means any semiconductor product developed or manufactured by or for elpida (as defined above). ? ? ? ? ? ?

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