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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd43256b 256k-bit cmos static ram 32k-word by 8-bit data sheet document no. m10770ejfv0ds00 (15th edition) date published november 2008 printed in japan 1990, 1993, 1994 description the pd43256b is a high speed, low power, and 262,144 bits ( 32,768 words by 8 bits) cmos static ram. battery backup is available. and a and b versions are wide voltage operations. the pd43256b is packed in 28-pin plastic dip, 28-pin plast ic sop and 28-pin plastic tsop (i) (8 x 13.4 mm). features ? 32,768 words by 8 bits organization ? fast access time: 70, 85, 100, 120 ns (max.) ? low voltage operation (a version: v cc = 3.0 to 5.5 v, b version: v cc = 2.7 to 5.5 v) ? low v cc data retention: 2.0 v (min.) ? /oe input for easy application part number access time operating supply operating ambient supply current ns (max.) voltage temperature at operating at standby at data retention v c ma (max.) a (max.) a (max.) note1 pd43256b-xxl 70, 85 4.5 to 5.5 0 to 70 45 50 3 pd43256b-xxll 15 2 pd43256b-axx 85, 100 note2 , 120 note2 3.0 to 5.5 pd43256b-bxx note2 100, 120 2.7 to 5.5 notes 1. t a 40 c, v cc = 3.0 v 2. access time: 85 ns (max.) (v cc = 4.5 to 5.5 v)
2 pd43256b data sheet m10770ejfv0ds ordering information part number package access time operati ng supply operating ambient remark ns (max.) voltage temperature v c pd43256bcz-70l 28-pin plastic dip 70 4.5 to 5.5 0 to 70 l version pd43256bcz-85l (15.24 mm (600)) 85 pd43256bcz-70ll 70 ll version pd43256bcz-85ll 85 pd43256bgu-70l 28-pin plastic sop 70 l version pd43256bgu-85l (11.43 mm (450)) 85 pd43256bgu-70ll 70 ll version pd43256bgu-85ll 85 pd43256bgu-a85 85 3.0 to 5.5 a version pd43256bgu-a10 100 pd43256bgu-a12 120 pd43256bgu-b12 120 2.7 to 5.5 b version pd43256bgw-70ll-9jl 28-pin plastic tsop (i) 70 4.5 to 5.5 ll version pd43256bgw-85ll-9jl (8x13.4) (normal bent) 85 pd43256bgu-70l-a 28-pin plastic sop 70 4.5 to 5.5 l version pd43256bgu-85l-a (11.43 mm (450)) 85 pd43256bgu-70ll-a 70 ll version pd43256bgu-85ll-a 85 pd43256bgu-a85-a 85 3.0 to 5.5 a version pd43256bgu-a10-a 100 pd43256bgu-a12-a 120 pd43256bgu-b10-a 100 2.7 to 5.5 b version pd43256bgu-b12-a 120 pd43256bgw-70ll-9jl-a 28-pin plastic tsop (i) 70 4.5 to 5.5 ll version pd43256bgw-85ll-9jl-a (8x13.4) (normal bent) 85 remark products with -a at the end of t he part number are lead-free products.
3 data sheet m10770ejfv0ds pin configurations (marking side) /xxx indicates active low signal. 28-pin plastic dip (15.24 mm (600)) [ pd43256bcz-xxl ] [ pd43256bcz-xxll ] a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd v cc /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a0 - a14 : address inputs i/o1 - i/o8 : data inputs / outputs /cs : chip select /we : write enable /oe : output enable v cc : power supply gnd : ground remark refer to package drawings for the 1-pin index mark.
4 pd43256b data sheet m10770ejfv0ds 28-pin plastic sop (11.43 mm (450)) [ pd43256bgu-xxl ] [ pd43256bgu-xxll ] [ pd43256bgu-axx ] [ pd43256bgu-bxx ] [ pd43256bgu-xxl-a ] [ pd43256bgu-xxll-a ] [ pd43256bgu-axx-a ] [ pd43256bgu-bxx-a ] a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd v cc /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a0 - a14 : address inputs i/o1 - i/o8 : data inputs / outputs /cs : chip select /we : write enable /oe : output enable v cc : power supply gnd : ground remark refer to package drawings for the 1-pin index mark.
5 data sheet m10770ejfv0ds 28-pin plastic tsop (i) (8x13.4) (normal bent) [ pd43256bgw-xxll-9jl ] [ pd43256bgw-axx-9jl ] [ pd43256bgw-bxx-9jl ] [ pd43256bgw-xxll-9jl-a ] [ pd43256bgw-axx-9jl-a ] [ pd43256bgw-bxx-9jl-a ] /oe a11 a9 a8 a13 /we v cc a14 a12 a7 a6 a5 a4 a3 a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a0 - a14 : address inputs /oe : output enable i/o1 - i/o8 : data inputs / outputs v cc : power supply /cs : chip select gnd : ground /we : write enable remark refer to package drawings for the 1-pin index mark.
6 pd43256b data sheet m10770ejfv0ds block diagram address buffer memory cell array 262,144 bits input data controller a0 a14 i/o8 sense amplifier / switching circuit column decoder /we i/o1 v cc gnd /cs /oe address buffer row decoder output data controller truth table /cs /oe /we mode i/o supply current h not selected high impedance i sb l h h output disable i cca l l write d in l l h read d out remark : v ih or v il
7 data sheet m10770ejfv0ds electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ?0.5 note to +7.0 v input / output voltage v t ?0.5 note to v cc + 0.5 v operating ambient temperature t a 0 to 70 c storage temperature t stg ?55 to +125 c note ?3.0 v (min.) (pulse width : 50 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition pd43256b-xxl pd43256b-axx pd43256b-bxx unit pd43256b-xxll min. max. min. max. min. max. supply voltage v cc 4.5 5.5 3.0 5.5 2.7 5.5 v high level input voltage v ih 2.2 v cc +0.5 2.2 v cc +0.5 2.2 v cc +0.5 v low level input voltage v il ?0.3 note +0.8 ?0.3 note +0.5 ?0.3 note +0.5 v operating ambient temperature t a 0 70 0 70 0 70 c note ?3.0 v (min.) (pulse width: 50 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 5 pf input / output capacitance c i/o v i/o = 0 v 8 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are periodica lly sampled and not 100% tested.
8 pd43256b data sheet m10770ejfv0ds dc characteristics (recommended operating c onditions unless otherwise noted) (1/2) parameter symbol test condition pd43256b-xxl pd43256b-xxll unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /oe = v ih or ?1.0 +1.0 ?1.0 +1.0 a /cs = v ih or /we = v il operating supply current i cca1 /cs = v il , minimum cycle time, i i/o = 0 ma 45 45 ma i cca2 /cs = v il , i i/o = 0 ma 10 10 i cca3 /cs 0.2 v, cycle = 1 mhz, 10 10 i i/o = 0 ma, v il 0.2 v, v ih v cc ? 0.2 v standby supply current i sb /cs = v ih 3 3 ma i sb1 /cs v cc ? 0.2 v 1.0 50 0.5 15 a high level output voltage v oh1 i oh = ?1.0 ma 2.4 2.4 v v oh2 i oh = ?0.1 ma v cc ?0.5 v cc ?0.5 low level output voltage v ol i ol = 2.1 ma 0.4 0.4 v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of package types.
9 data sheet m10770ejfv0ds dc characteristics (recommended operating c onditions unless otherwise noted) (2/2) parameter symbol test condition pd43256b-axx pd43256b-bxx unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /oe = v ih or ?1.0 +1.0 ?1.0 +1.0 a /cs = v ih or /we = v il operating supply current i cca1 /cs = v il , pd43256b-axx 45 ? ma minimum cycle time, pd43256b-bxx ? 45 i i/o = 0 ma v cc 3.3 v ? 20 i cca2 /cs = v il , i i/o = 0 ma 10 10 v cc 3.3 v ? 5 i cca3 /cs 0.2 v, cycle = 1 mhz, i i/o = 0 ma, 10 10 v il 0.2 v, v ih v cc ? 0.2 v v cc 3.3 v ? 5 standby supply current i sb /cs = v ih 3 3 ma v cc 3.3 v ? 2 i sb1 /cs v cc ? 0.2 v 0.5 15 0.5 15 a v cc 3.3 v ? 0.5 10 high level output voltage v oh1 i oh = ?1.0 ma, v cc 4.5 v 2.4 2.4 v i oh = ?0.5 ma, v cc < 4.5 v 2.4 2.4 v oh2 i oh = ?0.02 ma v cc ?0.1 v cc ?0.1 low level output voltage v ol i ol = 2.1 ma, v cc 4.5 v 0.4 0.4 v i ol = 1.0 ma, v cc < 4.5 v 0.4 0.4 v ol1 i ol = 0.02 ma 0.1 0.1 remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of package types.
10 pd43256b data sheet m10770ejfv0ds ac characteristics (recommended operati ng conditions unless otherwise noted) ac test conditions [ pd43256b-70l, pd43256b-85l, pd43256b-70ll, pd43256b-85ll ] input waveform (rise and fall time 5 ns) test points 0.8 v 2.2 v 1.5 v 1.5 v output waveform output load ac characteristics should be measur ed with the following output load conditions. figure 1 figure 2 (t aa , t acs , t oe , t oh ) (t chz , t clz , t ohz , t olz , t whz , t ow ) +5 v i/o (output) 1.8 k 5 pf c l 990 +5 v i/o (output) 1.8 k 100 pf c l 990 remark c l includes capacitance of the pr obe and jig, and stray capacitance. [ pd43256b-a85, pd43256b-a10, pd43256b-a12, pd43256b-b10, pd43256b-b12 ] input waveform (rise and fall time 5 ns) test points 0.5 v 2.2 v 1.5 v 1.5 v output waveform output load ac characteristics should be measur ed with the following output load conditions. t aa , t acs , t oe , t oh t chz , t clz , t ohz , t olz , t whz , t ow 1ttl + 100 pf 1ttl + 5 pf
11 data sheet m10770ejfv0ds read cycle (1/2) parameter symbol v cc 4.5 v unit condition pd43256b-70 pd43256b-85 pd43256b-a85/a10/a12 pd43256b-b10/b12 min. max. min. max. read cycle time t rc 70 85 ns address access time t aa 70 85 ns note /cs access time t acs 70 85 ns /oe access time t oe 35 40 ns output hold from address change t oh 10 10 ns /cs to output in low impedance t clz 10 10 ns /oe to output in low impedance t olz 5 5 ns /cs to output in high impedance t chz 30 30 ns /oe to output in high impedance t ohz 30 30 ns note see the output load . remark these ac characteristics are in common regardless of package types and l, ll versions. read cycle (2/2) parameter symbol v cc 3.0 v v cc 2.7 v unit condition pd43256b -a85 pd43256b -a10 pd43256b -a12 pd43256b -b10 pd43256b -b12 min. max. min. max. min. max. min. max. min. max. read cycle time t rc 85 100 120 100 120 ns address access time t aa 85 100 120 100 120 ns note /cs access time t acs 85 100 120 100 120 ns /oe access time t oe 50 60 60 60 60 ns output hold from address change t oh 10 10 10 10 10 ns /cs to output in low impedance t clz 10 10 10 10 10 ns /oe to output in low impedance t olz 5 5 5 5 5 ns /cs to output in high impedance t chz 35 35 40 35 40 ns /oe to output in high impedance t ohz 35 35 40 35 40 ns note see the output load . remark these ac characteristics are in common regardless of package types.
12 pd43256b data sheet m10770ejfv0ds read cycle timing chart t ohz t rc t oh t chz t olz t oe t clz t acs t aa high impedance data out /oe (input) /cs (input) address (input) i/o (output) remark in read cycle, /we should be fixed to high level.
13 data sheet m10770ejfv0ds write cycle (1/2) parameter symbol v cc 4.5 v unit condition pd43256b-70 pd43256b-85 pd43256b-a85/a10/a12 pd43256b-b10/b12 min. max. min. max. write cycle time t wc 70 85 ns /cs to end of write t cw 50 70 ns address valid to end of write t aw 50 70 ns write pulse width t wp 55 60 ns data valid to end of write t dw 30 35 ns data hold time t dh 0 0 ns address setup time t as 0 0 ns write recovery time t wr 0 0 ns /we to output in high impedance t whz 30 30 ns note output active from end of write t ow 10 10 ns note see the output load . remark these ac characteristics are in common regardless of package types and l, ll versions. write cycle (2/2) parameter symbol v cc 3.0 v v cc 2.7 v unit condition pd43256b -a85 pd43256b -a10 pd43256b -a12 pd43256b -b10 pd43256b -b12 min. max. min. max. min. max. min. max. min. max. write cycle time t wc 85 100 120 100 120 ns /cs to end of write t cw 70 70 90 70 90 ns address valid to end of write t aw 70 70 90 70 90 ns write pulse width t wp 60 60 80 60 80 ns data valid to end of write t dw 60 60 70 60 70 ns data hold time t dh 0 0 0 0 0 ns address setup t as 0 0 0 0 0 ns write recovery t wr 0 0 0 0 0 ns /we to output in high impedance t whz 30 35 40 35 40 ns note output active from end of write t ow 10 10 10 10 10 ns note see the output load . remark these ac characteristics are in common regardless of package types.
14 pd43256b data sheet m10770ejfv0ds write cycle timing chart 1 (/we controlled) t wc t cw t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /cs (input) i/o (input / output) t aw t wp t as t wr /we (input) cautions 1. /cs or /we should be fixed to high level during address transition. 2. when i/o pins are in the output state, therefore the input signals must not be applied to the output. remarks 1. write operation is done during t he overlap time of a low level /cs and a low level /we. 2. when /we is at low level, the i/o pins are al ways high impedance. when /w e is at high level, read operation is executed. t herefore /oe should be at high level to make the i/o pins high impedance. 3. if /cs changes to low level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state.
15 data sheet m10770ejfv0ds write cycle timing chart 2 (/cs controlled) t wc t as t cw t dw t dh data in high impedance address (input) /cs (input) i/o (input) high impedance t aw t wp t wr /we (input) cautions 1. /cs or /we should be fixed to high level during address transition. 2. when i/o pins are in the output state, therefore the input signals must not be applied to the output. remark write operation is done during t he overlap time of a low level /cs and a low level /we.
16 pd43256b data sheet m10770ejfv0ds low v cc data retention characteristics (t a = 0 to 70 c) parameter symbol test condition pd43256b-xxl pd43256b-xxll unit pd43256b-axx pd43256b-bxx min. typ. max. min. typ. max. data retention supply voltage v ccdr /cs v cc ? 0.2 v 2.0 5.5 2.0 5.5 v data retention supply current i ccdr v cc = 3.0 v, /cs v cc ? 0.2 v 0.5 20 note1 0.5 7 note2 a chip deselection to data retention mode t cdr 0 0 ns operation recovery time t r 5 5 ms notes 1. 3 a (t a 40 c) 2. 2 a (t a 40 c), 1 a (t a 25 c) data retention timing chart v ih (min.) v ccdr (min.) v il (max.) v cc /cs /cs v cc ? 0.2 v gnd 4.5 v note t cdr data retention mode t r note a version : 3.0 v, b version : 2.7 v remark the other pins (address, /oe, /we, i/o) can be in high impedance state.
17 data sheet m10770ejfv0ds package drawings item millimeters a b c f g h i j k 38.10 max. 2.54 (t.p.) 3.6 0.3 0.51 min. 4.31 max. 2.54 max. l 0.25 15.24 (t.p.) 5.72 max. 13.2 n 1.2 min. p28c-100-600a1-2 d 0.50 0.10 m 0.25 + 0.10 ? 0.05 r 0 - 15 notes each lead centerline is located within 0.25 mm of its true position (t.p.) at maximum material condition. item "k" to center of leads when formed parallel. 1. 2. 28 1 15 14 a m r k l b j g i c f d m n 28-pin plastic dip (15.24 mm (600)) h
18 pd43256b data sheet m10770ejfv0ds 28 15 114 s ? 3 item millimeters a b c e f g h j 18.0 1.27 (t.p.) 2.95 max. 2.55 0.1 11.8 0.3 1.27 max. 0.12 1.7 0.2 m 0.2 0.1 n p28gu-50-450a-4 p3 + 7 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. d 0.42 + 0.08 ? 0.07 k 0.22 0.05 + 0.6 ? 0.05 l 0.7 0.2 0.10 i 8.4 0.1 28-pin plastic sop (11.43 mm (450)) m f e dm c g b l j k p detail of lead end a s n i h
19 data sheet m10770ejfv0ds + 7 ? 3 28-pin plastic tsop( i ) (8x13.4) item millimeters notes 1. each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. p28gw-55-9jl-2 m 0.08 n 0.10 h 12.4 0.2 i 11.8 0.1 j 0.8 0.2 s 1.2 max. a 8.0 0.1 b 0.6 max. c 0.55 (t.p.) g 1.0 k 0.145 l 0.5 0.1 p 13.4 0.2 q 0.1 0.05 r3 d 0.22 + 0.08 ? 0.07 m detail of lead end q r g b c dm l k + 0.025 ? 0.015 s 2. "a" excludes mold flash. (includes mold flash : 8.4mm max.) 1 14 28 15 s n s a j p i h
20 pd43256b data sheet m10770ejfv0ds recommended soldering conditions please consult with our sales offices for soldering conditions of the pd43256b. types of surface mount device pd43256bgu-xxl : 28-pin plastic sop (11.43 mm (450)) pd43256bgu-xxll : 28-pin plastic sop (11.43 mm (450)) pd43256bgu-axx : 28-pin plastic sop (11.43 mm (450)) pd43256bgu-bxx : 28-pin plastic sop (11.43 mm (450)) pd43256bgw-xxll-9jl : 28-pin plastic tsop (i) (8x13.4) (normal bent) pd43256bgu-xxl-a : 28-pin plastic sop (11.43 mm (450)) pd43256bgu-xxll-a : 28-pin plastic sop (11.43 mm (450)) pd43256bgu-axx-a : 28-pin plastic sop (11.43 mm (450)) pd43256bgu-bxx-a : 28-pin plastic sop (11.43 mm (450)) pd43256bgw-xxll-9jl-a : 28-pin plastic tsop (i) (8x13.4) (normal bent) types of through hole mount device pd43256bcz-xxl : 28-pin plastic dip (15.24 mm (600)) pd43256bcz-xxll : 28-pin plastic dip (15.24 mm (600)) soldering process so ldering conditions wave soldering (only to leads) solder temperature : 260 c or below, flow time : 10 seconds or below partial heating method terminal temperature : 300 c or below, time : 3 seconds or below (per one lead) caution do not jet molten solder on the surface of package.
21 data sheet m10770ejfv0ds revision history edition/ page type of description date this previous revision edition edition 15th edition/ through through modification ordering information revised. nov. 2008
22 pd43256b data sheet m10770ejfv0ds [ memo ]
23 data sheet m10770ejfv0ds 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd43256b the information in this document is current as of november, 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers mu st incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics pr oduct depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if cu stomers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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