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? 2006 microchip technology inc. ds21945d-page 1 mcp4021/2/3/4 features ? non-volatile digital po tentiometer in sot-23, soic, msop and dfn packages ? 64 taps: 63 resistors with taps to terminal a and terminal b ? simple up/down (u/d ) protocol ? power-on recall of saved wiper setting ? resistance values: 2.1 k , 5 k , 10 k or 50 k ? low tempco: - absolute (rheostat): 50 ppm (0c to 70c typ.) - ratiometric (potentiometer): 10 ppm (typ.) ? low wiper resistance: 75 (typ.) ? wiperlock? technology to secure the wiper setting in non-volati le memory (eeprom) ? high-voltage tolerant digital inputs: up to 12.5v ? low-power operation: 1 a max static current ? wide operating voltage: 2.7v to 5.5v ? extended temperature range: -40c to +125c ? wide bandwidth (-3 db) operation: - 4 mhz (typ.) for 2.1 k device description the mcp4021/2/3/4 devices are non-volatile, 6-bit digital potentiometers that can be configured as either a potentiometer or rheost at. the wiper setting is controlled through a simple up/down (u/d ) serial interface. these device?s implement microchip?s wiperlock tech- nology, which allows application-specific calibration settings to be secure d in the eeprom without requiring the use of an add itional write-protect pin. package types block diagram device features . a w b mcp4021 soic, msop, dfn mcp4022 sot-23-6 mcp4023 sot-23-6 mcp4024 sot-23-5 rheostat potentiometer potentiometer rheostat a v ss w 1 2 3 4 8 7 6 5 v dd u/d nc b cs 4 1 2 3 5 w cs v dd v ss u/d 4 1 2 3 6 a cs v dd v ss u/d 5 w a w b 4 1 2 3 6 a cs v dd v ss u/d 5 w a w w a b b v dd v ss u/d w b (resistor array) wiper register cs wiperlock? eeprom and a 2-wire interface and control logic power-up and brown-out control technology device wiper configuration memory type resistance (typical) # of steps v dd operating range control interface wiperlock? technology options (k )wiper ( ) mcp4021 potentiometer (1) ee 2.1, 5.0, 10.0, 50 .0 75 64 2.7v - 5.5v u/d yes mcp4022 rheostat ee 2.1, 5.0, 10.0, 50.0 75 64 2.7v- 5.5v u/d yes mcp4023 potentiometer ee 2.1, 5.0, 10.0, 50.0 75 64 2.7v - 5.5v u/d yes mcp4024 rheostat ee 2.1, 5.0, 10.0, 50.0 75 64 2.7v - 5.5v u/d yes note 1: floating either terminal (a or b) allows the device to be used in rheostat mode. low-cost nv digital pot with wiperlock? technology
mcp4021/2/3/4 ds21945d-page 2 ? 2006 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ............................................................................................................. 6.5v cs and u/d inputs w.r.t v ss.................................... -0.3v to 12.5v a, b and w terminals w.r.t v ss.................... -0.3v to v dd + 0.3v current at input pins ..................................................10 ma current at supply pins ...............................................10 ma current at potentiometer pins ...................................2.5 ma storage temperature .....................................-65c to +150c ambient temp. with power applied ................-55c to +125c esd protection on all pins ........... 4kv (hbm), 400v (mm) maximum junction temperature (t j ) . .........................+150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent dam age to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ac/dc characteristics electrical specifications: unless otherwise indicated, all paramete rs apply across the specified operating ranges. t a = -40c to +125c, 2.1 k , 5k , 10 k and 50 k devices . typical specifications represent values for v dd = 5.5v, v ss = 0v, t a = +25c. parameters sym min typ max units conditions operating voltage range v dd 2.7 ? 5.5 v cs input voltage v cs v ss ? 12.5 v the cs pin will be at one of three input levels (v il , v ih or v ihh ). ( note 6 ) supply current i dd ? 45 ? a 5.5v, cs = v ss , f u/d = 1 mhz ? 15 ? a 2.7v, cs = v ss , f u/d = 1 mhz ? 0.3 1 a serial interface inactive (cs = v ih , u/d = v ih ) ? 0.6 3 ma ee write cycle, t a = +25c resistance ( 20%) r ab 1.68 2.1 2.52 k -202 devices (note 1) 4.0 5 6.0 k -502 devices (note 1) 8.0 10 12.0 k -103 devices (note 1) 40.0 50 60.0 k -503 devices (note 1) resolution n 64 taps no missing codes step resistance r s ? r ab / 63 ? note 6 note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . (-202 devices v a = 4v). 3: mcp4021/23 only, test conditions are: i w = 1.9 ma, code = 00h. 4: mcp4022/24 only, test conditions are: 5: resistor terminals a, w and b? s polarity with respect to each other is not restricted. 6: this specification by design 7: non-linearity is affected by wiper resistance (r w ), which changes significantly ov er voltage and temperature. see section 6.0 ?resistor? for additional information. 8: the mcp4021 is externally connected to match the configurations of the mcp4022 and mcp4024 , and then tested. device resistance current at voltage comments 5.5v 2.7v 2.1 k 2.25 ma 1.1 ma mcp4022 includes v wzse mcp4024 includes v wfse 5k 1.4 ma 450 a 10 k 450 a 210 a 50 k 90 a 40 a
? 2006 microchip technology inc. ds21945d-page 3 mcp4021/2/3/4 wiper resistance ( note 3, note 4) r w ? 70 125 5.5v ? 70 325 2.7v nominal resistance tempco r/ t ? 50 ? ppm/c t a = -20c to +70c ? 100 ? ppm/c t a = -40c to +85c ? 150 ? ppm/c t a = -40c to +125c ratiometeric tempco v wa / t ? 10 ? ppm/c mcp4021 and mcp4023 only, code = 1fh full-scale error v wfse -0.5 -0.1 +0.5 lsb code 3fh ( mcp4021/23 only) zero-scale error v wzse -0.5 +0.1 +0.5 lsb code 00h ( mcp4021/23 only) monotonicity n yes bits potentiometer integral non-linearity inl -0.5 0.25 +0.5 lsb mcp4021/23 only (note 2) potentiometer differential non-linearity dnl -0.5 0.25 +0.5 lsb mcp4021/23 only (note 2) resistor terminal input voltage range (terminals a, b and w) v a, v w, v b vss ? v dd v note 5, note 6 maximum current through a, w or b i w ?? 2.5 ma note 6 leakage current into a, w or b i wl ? 100 ? na mcp4021 a = w = b = v ss ? 100 ? na mcp4022/23 a = w = v ss ? 100 ? na mcp4024 w = v ss capacitance (p a )c aw ? 75 ? pf f =1 mhz, code = 1fh capacitance (p w )c w ? 120 ? pf f =1 mhz, code = 1fh capacitance (p b )c bw ? 75 ? pf f =1 mhz, code = 1fh bandwidth -3 db bw ? 1 ? mhz code = 1f, output load = 30 pf bandwidth -3 db bw ? 4 ? mhz code = 1f, output load = 30 pf ?2 ?mhz ?1 ?mhz ? 200 ? khz ac/dc characteristi cs (continued) electrical specifications: unless otherwise indicated, all paramete rs apply across the specified operating ranges. t a = -40c to +125c, 2.1 k , 5k , 10 k and 50 k devices . typical specifications represent values for v dd = 5.5v, v ss = 0v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . (-202 devices v a = 4v). 3: mcp4021/23 only, test conditions are: i w = 1.9 ma, code = 00h. 4: mcp4022/24 only, test conditions are: 5: resistor terminals a, w and b? s polarity with respect to each other is not restricted. 6: this specification by design 7: non-linearity is affected by wiper resistance (r w ), which changes significantly ov er voltage and temperature. see section 6.0 ?resistor? for additional information. 8: the mcp4021 is externally connected to match the configurations of the mcp4022 and mcp4024 , and then tested. device resistance current at voltage comments 5.5v 2.7v 2.1 k 2.25 ma 1.1 ma mcp4022 includes v wzse mcp4024 includes v wfse 5k 1.4 ma 450 a 10 k 450 a 210 a 50 k 90 a 40 a
mcp4021/2/3/4 ds21945d-page 4 ? 2006 microchip technology inc. rheostat integral non-linearity mcp4021 ( note 4, note 8 ) mcp4022 and mcp4024 (note 4) r-inl -0.5 0.25 +0.5 lsb 2.1 k 5.5v -8.5 +4.5 +8.5 lsb 2.7v (note 7) -0.5 0.25 +0.5 lsb 5 k 5.5v -5.5 +2.5 +5.5 lsb 2.7v (note 7) -0.5 0.25 +0.5 lsb 10 k 5.5v -3 +1 +3 lsb 2.7v (note 7) -0.5 0.25 +0.5 lsb 50 k 5.5v -1 +0.25 +1 lsb 2.7v (note 7) rheostat differential non-linearity mcp4021 ( note 4, note 8 ) mcp4022 and mcp4024 (note 4) r-dnl -0.5 0.25 +0.5 lsb 2.1 k 5.5v -1 +0.5 +2 lsb 2.7v (note 7) -0.5 0.25 +0.5 lsb 5 k 5.5v -1 +0.25 +1.25 lsb 2.7v (note 7) -0.5 0.25 +0.5 lsb 10 k 5.5v -1 0 +1 lsb 2.7v (note 7) -0.5 0.25 +0.5 lsb 50 k 5.5v -0.5 0 +0.5 lsb 2.7v (note 7) digital inputs/outputs (cs , u/d ) input high voltage v ih 0.7 v dd ?? v input low voltage v il ??0.3v dd v high-voltage input entry voltage v ihh 8.5 ? 12.5 (6) v threshold for wiperlock? technology high-voltage input exit voltage v ihh ??v dd +0.8 (6) v cs pull-up/pull-down resistance r cs ?16 ? k v dd = 5.5v, v cs = 3v cs weak pull-up/pull-down current i pu ? 170 ? a v dd = 5.5v, v cs = 3v input leakage current i il -1 ? 1 a v in = v dd cs and u/d pin capacitance c in , c out ?10 ? pff c = 1 mhz ac/dc characteristi cs (continued) electrical specifications: unless otherwise indicated, all paramete rs apply across the specified operating ranges. t a = -40c to +125c, 2.1 k , 5k , 10 k and 50 k devices . typical specifications represent values for v dd = 5.5v, v ss = 0v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . (-202 devices v a = 4v). 3: mcp4021/23 only, test conditions are: i w = 1.9 ma, code = 00h. 4: mcp4022/24 only, test conditions are: 5: resistor terminals a, w and b? s polarity with respect to each other is not restricted. 6: this specification by design 7: non-linearity is affected by wiper resistance (r w ), which changes significantly ov er voltage and temperature. see section 6.0 ?resistor? for additional information. 8: the mcp4021 is externally connected to match the configurations of the mcp4022 and mcp4024 , and then tested. device resistance current at voltage comments 5.5v 2.7v 2.1 k 2.25 ma 1.1 ma mcp4022 includes v wzse mcp4024 includes v wfse 5k 1.4 ma 450 a 10 k 450 a 210 a 50 k 90 a 40 a
? 2006 microchip technology inc. ds21945d-page 5 mcp4021/2/3/4 ram (wiper) value value range n 0h ? 3fh hex eeprom endurance e ndurance ? 1m ? cycles eeprom range n 0h ? 3fh hex initial factory setting n 1fh hex wiperlock technology = off power requirements power supply sensitivity ( mcp4021 and mcp4023 only) pss ? 0.0015 0.0035 %/% v dd = 4.5v to 5.5v, v a = 4.5v, code = 1fh ? 0.0015 0.0035 %/% v dd = 2.7v to 4.5v, v a = 2.7v, code = 1fh ac/dc characteristi cs (continued) electrical specifications: unless otherwise indicated, all paramete rs apply across the specified operating ranges. t a = -40c to +125c, 2.1 k , 5k , 10 k and 50 k devices . typical specifications represent values for v dd = 5.5v, v ss = 0v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . (-202 devices v a = 4v). 3: mcp4021/23 only, test conditions are: i w = 1.9 ma, code = 00h. 4: mcp4022/24 only, test conditions are: 5: resistor terminals a, w and b? s polarity with respect to each other is not restricted. 6: this specification by design 7: non-linearity is affected by wiper resistance (r w ), which changes significantly ov er voltage and temperature. see section 6.0 ?resistor? for additional information. 8: the mcp4021 is externally connected to match the configurations of the mcp4022 and mcp4024 , and then tested. device resistance current at voltage comments 5.5v 2.7v 2.1 k 2.25 ma 1.1 ma mcp4022 includes v wzse mcp4024 includes v wfse 5k 1.4 ma 450 a 10 k 450 a 210 a 50 k 90 a 40 a
mcp4021/2/3/4 ds21945d-page 6 ? 2006 microchip technology inc. figure 1-1: increment timing waveform. cs u/d t lcur t lo t hi t luc w t cshi t s 1/f ud t cslo t s t lcuf t luc t lcuf serial timing characteristics electrical specifications: unless otherwise noted, all parameters app ly across the specified operating ranges. extended (e): v dd = +2.7v to 5.5v, t a = -40c to +125c. parameters sym min typ max units conditions cs low time t cslo 5??s cs high time t cshi 500 ? ? ns u/d to cs hold time t luc 500 ? ? ns cs to u/d low setup time t lcuf 500 ? ? ns cs to u/d high setup time t lcur 3??s u/d high time t hi 500 ? ? ns u/d low time t lo 500 ? ? ns up/down toggle frequency f ud ?? 1mhz wiper settling time t s 0.5 ? ? s 2.1 k , c l = 100 pf 1??s5k , c l = 100 pf 2??s10k , c l = 100 pf 10 5 ? s 50 k , c l = 100 pf wiper response on power-up t pu ?200? ns internal eeprom write time twc ? ? 5 ms @25c ? ? 10 ms -40c to +125c
? 2006 microchip technology inc. ds21945d-page 7 mcp4021/2/3/4 figure 1-2: decrement timing waveform. cs u/d t lcur t hi t lo w t s t cslo t luc t cshi t luc t lcuf t s 1/f ud serial timing characteristics electrical specifications: unless otherwise noted, all parameters app ly across the specified operating ranges. extended (e): v dd = +2.7v to 5.5v, t a = -40c to +125c. parameters sym min typ max units conditions cs low time t cslo 5??s cs high time t cshi 500 ? ? ns u/d to cs hold time t luc 500 ? ? ns cs to u/d low setup time t lcuf 500 ? ? ns cs to u/d high setup time t lcur 3??s u/d high time t hi 500 ? ? ns u/d low time t lo 500 ? ? ns up/down toggle frequency f ud ?? 1mhz wiper settling time t s 0.5 ? ? s 2.1 k , c l = 100 pf 1??s5k , c l = 100 pf 2??s10k , c l = 100 pf 10 5 ? s 50 k , c l = 100 pf wiper response on power-up t pu ?200? ns internal eeprom write time twc ? ? 5 ms @25c ? ? 10 ms -40c to +125c
mcp4021/2/3/4 ds21945d-page 8 ? 2006 microchip technology inc. figure 1-3: high-voltage increment timing waveform. cs u/d t hcur t lo t hi t huc w t cshi t s 1/f ud t cslo t s t hcuf t huc t hcuf 5v 12v serial timing characteristics electrical specifications: unless otherwise noted, all parameters app ly across the specified operating ranges. extended (e): v dd = +2.7v to 5.5v, t a = -40c to +125c. parameters sym min typ max units conditions cs low time t cslo 5??s cs high time t cshi 500 ? ? ns u/d high time t hi 500 ? ? ns u/d low time t lo 500 ? ? ns up/down toggle frequency f ud ?? 1mhz hv u/d to cs hold time t huc 1.5 ? ? s hv cs to u/d low setup time t hcuf 8??s hv cs to u/d high setup time t hcur 4.5 ? ? s wiper settling time t s 0.5 ? ? s 2.1 k , c l = 100 pf 1??s5k , c l = 100 pf 2??s10k , c l = 100 pf 10 5 ? s 50 k , c l = 100 pf wiper response on power-up t pu ?200? ns internal eeprom write time twc ? ? 5 ms @25c ? ? 10 ms -40c to +125c
? 2006 microchip technology inc. ds21945d-page 9 mcp4021/2/3/4 figure 1-4: high-voltage decrement timing waveform. cs u/d t hcur t hi t lo w t s t cslo t huc t cshi t huc t hcuf t s 5v 12v 1/f ud serial timing characteristics electrical specifications: unless otherwise noted, all parameters app ly across the specified operating ranges. extended (e): v dd = +2.7v to 5.5v, t a = -40c to +125c. parameters sym min typ max units conditions cs low time t cslo 5??s cs high time t cshi 500 ? ? ns u/d high time t hi 500 ? ? ns u/d low time t lo 500 ? ? ns up/down toggle frequency f ud ?? 1mhz hv u/d to cs hold time t huc 1.5 ? ? s hv cs to u/d low setup time t hcuf 8??s hv cs to u/d high setup time t hcur 4.5 ? ? s wiper settling time t s 0.5 ? ? s 2.1 k , c l = 100 pf 1??s5k , c l = 100 pf 2??s10k , c l = 100 pf 10 5 ? s 50 k , c l = 100 pf wiper response on power-up t pu ?200? ns internal eeprom write time twc ? ? 5 ms @25c ? ? 10 ms -40c to +125c
mcp4021/2/3/4 ds21945d-page 10 ? 2006 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ?70?c/w thermal resistance, 6l-sot-23 ja ?120?c/w thermal resistance, 8l-dfn (2x3) ja ?85?c/w thermal resistance, 8l-msop ja ?206?c/w thermal resistance, 8l-soic ja ?163?c/w
? 2006 microchip technology inc. ds21945d-page 11 mcp4021/2/3/4 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-1: device current (i dd ) vs. u/d frequency (f u/d ) and ambient temperature (v dd = 2.7v and 5.5v). figure 2-2: write current (i write ) vs. ambient temperature and v dd . figure 2-3: device current (i shdn ) vs. ambient temperature and v dd . (cs = v dd ). figure 2-4: cs pull-up/pull-down resistance (r cs ) and current (i cs ) vs. cs input voltage (v cs ) (v dd = 5.5v). figure 2-5: cs high input entry/exit threshold vs. ambient temperature and v dd . note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 10 20 30 40 50 60 70 80 0.20 0.40 0.60 0.80 1.00 f u/d (mhz) device current (i dd ) (a) 2.7v -40c 2.7v 25c 2.7v 85c 2.7v 125c 5.5v -40c 5.5v 25c 5.5v 85c 5.5v 125c 0.0 100.0 200.0 300.0 400.0 500.0 600.0 -40 25 85 125 ambient temperature (c) device current (i dd ) (a) v dd = 2.7v v dd = 5.5v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -40 25 85 125 ambient temperature (c) device current (i dd ) (a) v dd = 2.7v v dd = 5.5v 0 50 100 150 200 250 987654321 v cs (v) r cs (kohms) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 ics (a) i cs r cs 0 2 4 6 8 10 12 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) cs v pp threshold (v) 1.8v entry 2.7v entry 5.5v entry 1.8v exit 2.7v exit 5.5v exit
mcp4021/2/3/4 ds21945d-page 12 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-6: 2.1 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-7: 2.1 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). figure 2-8: 2.1 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-9: 2.1 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). 0 20 40 60 80 100 120 140 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 100 200 300 400 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.1 -0.05 0 0.05 0.1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 20 40 60 80 100 120 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.4 -0.2 0 0.2 0.4 0.6 0.8 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 100 200 300 400 500 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -2 0 2 4 6 8 10 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
? 2006 microchip technology inc. ds21945d-page 13 mcp4021/2/3/4 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-10: 2.1 k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-11: 2.1 k ? r wb ( ) vs. wiper setting and ambient temperature. 2000 2020 2040 2060 2080 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) v dd = 2.7v v dd = 5.5v 0 500 1000 1500 2000 2500 0 8 16 24 32 40 48 56 64 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
mcp4021/2/3/4 ds21945d-page 14 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-12: 2.1 k ? low-voltage decrement wiper settling time (v dd = 2.7v). figure 2-13: 2.1 k ? low-voltage decrement wiper settling time (v dd = 5.5v). figure 2-14: 2.1 k ? power-up wiper response time. figure 2-15: 2.1 k ? low-voltage increment wiper settling time (v dd = 2.7v). figure 2-16: 2.1 k ? low-voltage increment wiper settling time (v dd = 5.5v). u/d wiper u/d wiper wiper v dd u/d wiper u/d wiper
? 2006 microchip technology inc. ds21945d-page 15 mcp4021/2/3/4 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-17: 5k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-18: 5k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). figure 2-19: 5k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v) figure 2-20: 5k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). 0 20 40 60 80 100 120 140 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 50 100 150 200 250 300 350 400 450 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.125 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 20 40 60 80 100 120 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 100 200 300 400 500 600 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -1 0 1 2 3 4 5 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
mcp4021/2/3/4 ds21945d-page 16 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-21: 5k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-22: 5k ? r wb ( ) vs. wiper setting and ambient temperature. 4800 4825 4850 4875 4900 4925 4950 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v vdd 5.5v vdd v dd = 2.7v v dd = 5.5v 0 1000 2000 3000 4000 5000 6000 0 8 16 24 32 40 48 56 64 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
? 2006 microchip technology inc. ds21945d-page 17 mcp4021/2/3/4 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-23: 5k ? low-voltage decrement wiper settling time (v dd = 2.7v). figure 2-24: 5k ? low-voltage decrement wiper settling time (v dd = 5.5v). figure 2-25: 5k ? low-voltage increment wiper settling time (v dd = 2.7v). figure 2-26: 5k ? low-voltage increment wiper settling time (v dd = 5.5v). u/d wiper u/d wiper u/d wiper u/d wiper
mcp4021/2/3/4 ds21945d-page 18 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-27: 10 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-28: 10 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). figure 2-29: 10 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-30: 10 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). 0 20 40 60 80 100 120 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 50 100 150 200 250 300 350 400 450 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.125 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 20 40 60 80 100 120 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 100 200 300 400 500 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -2.5 -1.5 -0.5 0.5 1.5 2.5 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
? 2006 microchip technology inc. ds21945d-page 19 mcp4021/2/3/4 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-31: 10 k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-32: 10 k ? r wb ( ) vs. wiper setting and ambient temperature. 10050 10070 10090 10110 10130 10150 10170 10190 10210 10230 10250 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) nominal resistance (r ab ) (ohms) v dd = 2.7v v dd = 5.5v 0 2000 4000 6000 8000 10000 12000 0 8 16 24 32 40 48 56 64 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
mcp4021/2/3/4 ds21945d-page 20 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-33: 10 k ? low-voltage decrement wiper settling time (v dd = 2.7v). figure 2-34: 10 k ? low-voltage decrement wiper settling time (v dd = 5.5v). figure 2-35: 10 k ? low-voltage increment wiper settling time (v dd = 2.7v). figure 2-36: 10 k ? low-voltage increment wiper settling time (v dd = 5.5v). u/d wiper u/d wiper u/d wiper u/d wiper
? 2006 microchip technology inc. ds21945d-page 21 mcp4021/2/3/4 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-37: 50 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-38: 50 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). figure 2-39: 50 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-40: 50 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 2.7v). 0 40 80 120 160 200 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.15 -0.1 -0.05 0 0.05 0.1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 100 200 300 400 500 600 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 50 100 150 200 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -0.1 -0.05 0 0.05 0.1 0.15 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw 0 100 200 300 400 500 600 0 8 16 24 32 40 48 56 wiper setting (decimal) wiper resistance (rw)(ohms) -1.5 -1 -0.5 0 0.5 1 1.5 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw
mcp4021/2/3/4 ds21945d-page 22 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-41: 50 k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-42: 50 k ? r wb ( ) vs. wiper setting and ambient temperature. 48000 48200 48400 48600 48800 49000 49200 49400 49600 49800 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) nominal resistance (r ab ) (ohms) v dd = 2.7v v dd = 5.5v 0 10000 20000 30000 40000 50000 60000 0 8 16 24 32 40 48 56 64 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
? 2006 microchip technology inc. ds21945d-page 23 mcp4021/2/3/4 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-43: 50 k ? low-voltage decrement wiper settling time (v dd = 2.7v). figure 2-44: 50 k ? low-voltage decrement wiper settling time (v dd = 5.5v). figure 2-45: 50 k ? power-up wiper response time. figure 2-46: 50 k ? low-voltage increment wiper settling time (v dd = 2.7v). figure 2-47: 50 k - low-voltage increment wiper settling time (v dd = 5.5v). u/d wiper u/d wiper v dd wiper u/d wiper u/d wiper
mcp4021/2/3/4 ds21945d-page 24 ? 2006 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-48: gain vs. frequency (-3 db bandwidth). figure 2-49: gain vs. frequency (-3 db bandwidth) test circuit. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 -40 25 125 temperature (c) -3db frequency (mhz) 2.1 k : 5 k : 10 k : 50 k : v in - + +5v v out 2.5v dc offset gnd a b dut w ~
? 2006 microchip technology inc. ds21945d-page 25 mcp4021/2/3/4 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 positive power supply input (v dd ) the v dd pin is the device?s positive power supply input. the input power supply is relative to v ss and can range from 2.7v to 5.5v. a decoupling capacitor on v dd (to v ss ) is recommended to achieve maximum performance. 3.2 ground (v ss ) the v ss pin is the device ground reference. 3.3 potentiometer terminal a the terminal a pin is connec ted to the internal potenti- ometer?s terminal a (available on some devices). the potentiometer?s terminal a is the fixed connection to the 0x3f terminal of the digital potentiometer. the terminal a pin is available on the mcp4021, mcp4022 and mcp4023 devices. the terminal a pin does not have a polarity relative to the terminal w or b pins. the terminal a pin can support both positive and negative current. the voltage on teminal a must be between v ss and v dd . the terminal a pin is not available on the mcp4024. the potentiometer?s terminal a is internally floating. 3.4 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potenti- ometer?s terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminals a or b pins. the terminal w pin can support both positive and negative current. the voltage on teminal w must be between v ss and v dd . 3.5 potentiometer terminal b the terminal b pin is connected to the internal potenti- ometer?s terminal b (available on some devices). the potentiometer?s terminal b is the fixed connection to the 0x00 terminal of the digital potentiometer. the terminal b pin is available on the mcp4021 device. the terminal b pin does not have a polarity relative to the terminal w or a pins. the terminal b pin can support both positive and negative current. the voltage on teminal b must be between v ss and v dd . the terminal b pin is not available on the mcp4022, mcp4023 and mcp4024 devices. for the mcp4023 and mcp4024, the internal potenti- ometer?s terminal b is internally connected to v ss . terminal b does not have a polarity relative to termi- nals w or a. terminal b can support both positive and negative current. for the mcp4022, terminal b is internally floating. pin number symbol pin type buffer type function mcp4021 (soic-8) mcp4022 mcp4023 (sot-23-6) mcp4024 (sot-23-5) 111v dd p ? positive powe r supply input 222v ss p ? ground 3 6 ? a i/o a potentiometer terminal a 455wi/oapotentiome ter wiper terminal 544cs i ttl chip select input 6 ? ? b i/o a potentiometer terminal b 7 ? ? nc ? ? no connection 833u/d i ttl increment/decrement input legend: ttl = ttl compatible input a = analog input i = input o = output p = power
mcp4021/2/3/4 ds21945d-page 26 ? 2006 microchip technology inc. 3.6 chip select (cs ) the cs pin is the chip select input. forcing the cs pin to v il enables the serial commands. these commands can increment and decrem ent the wiper. depending on the command, the wiper may (or may not) be saved to non-volatile memeory (eeprom). forcing the cs pin to v ihh enables the high-voltage serial commands. these commands can increment and decrement the wiper and enable or disable the wiperlock technology. the wiper is saved to non -volatile memory (eeprom). the cs pin has an internal pull-up resistor. the resistor will become ?disabled? when the voltage on the cs pin is below the v ih level. this means that when the cs pin is ?floating?, the cs pin will be pulled to the v ih level (serial communication (the u/d pin) is ignored). and when the cs pin is driven low (v il ), the resistance becomes very large to reduce the device current consumption when serial commands are occurring. see figure 2-4 for additional information. 3.7 increment/decrement (u/d ) the u/d pin input is used to increment or decrement the wiper on the digital potentiometer. an increment moves the wiper one step toward terminal a, while a decrement moves the wiper one step toward terminal b.
? 2006 microchip technology inc. ds21945d-page 27 mcp4021/2/3/4 4.0 general overview the mcp402x devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. applications generally suited for the mcp402x devices include: ? set point or offset trimming ? sensor calibration ? selectable gain and offset amplifier designs ? cost-sensitive mechanical trim pot replacement the digital potentiometer is available in four nominal resistances (r ab ), where the nominal resistance is defined as the resistance between terminal a and terminal b. the four nominal resistances are 2.1 k , 5k , 10 k and 50 k . there are 63 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 63 resistors thus providing 64 possible settings (including terminal a and terminal b). figure 4-1 shows a block diagram for the resistive network of the device. equation 4-1 shows the calculation for the step resistance, while equation 4-2 illustrates the calculation used to determine the resistance between the wiper and terminal b. figure 4-1: resistor block diagram. equation 4-1: r s calculation equation 4-2: r wb calculation 1 lsb is the ideal resistance difference between two successive codes. if we use n = 1 and r w = 0 in equation 4-2 , we can calculate the step size for each increment or decrement command. the mcp4021 device offers a voltage divider (potentiometer) with all terminals available on pins. the mcp4022 is a true rheostat, with terminal a and the wiper (w) of the variable resistor available on pins. the mcp4023 device offers a voltage divider (potenti- ometer) with terminal b connected to ground. the mcp4024 device is a rheostat device with terminal a of the resistor floating, terminal b connected to ground, and the wiper (w) available on pin. the mcp4021 can be externally configured to implement any of the mcp4022, mcp4023 or mcp4024 configurations. 4.1 serial interface a 2-wire synchronous serial protocol is used to increment or decrement the digital potentiometer?s wiper terminal. the increment/decrement (u/d ) protocol utilizes the cs and u/d input pins. both inputs are tolerant of signals up to 12.5v without damaging the device. the cs pin can differenciate between two high-voltage levels, v ih and v ihh . this enables additional commands without requiring additional input pins. the high-voltage commands (v ihh on the cs pin) are similar to the standard commands, except that they control (enable, disable, ...) the state of the non-volatile wiperlock technolgy feature. the simple u/d protocol uses t he state of the u/d pin at the falling edge of the cs pin to determine if increment or decrement mo de is desired. subsequent rising edges of the u/d pin move the wiper. the wiper value will not underflow or overflow. the new wiper setting can be saved to eeprom, if desired, by selecting the state of the u/d pin during the rising edge of the cs pin. the non-volatile wiper enables the mcp4021/2/3/4 to operate stand alone (without microcontroller control). r s a r s r s r s b n = 63 n = 62 n = 61 n = 1 n = 0 r w (1) w 01h analog mux r w (1) 00h r w (1) 3dh r w (1) 3eh r w (1) 3fh note 1: the wiper resistance is tap dependent. that is, each tap selection resistance has a small variation. this variation effects the smaller resistance devices (2.1 k ) more. r s r ab 63 --------- = r wb r ab n 63 ------------- - r w + = n = 0 to 63 (decimal)
mcp4021/2/3/4 ds21945d-page 28 ? 2006 microchip technology inc. 4.2 the wiperlock? technology the mcp4021/2/3/4 device?s wiperlock technology allows application-specific calibration settings to be secured in the eeprom without requiring the use of an additional write-protect pin. the wiperlock technology prevents the serial commands from doing the following: ? incrementing or decrem enting the wiper setting ? writing the wiper setting to the non-volatile memory enabling and disabling the wiperlock technology feature requires high-voltage serial commands (cs =v ihh ). incrementing and decrementing the wiper requires high-voltage commands when the feature is enabled. the high-voltage threshold (v ihh ) is intended to prevent the wiper setting from being altered by noise or intentional transitions on the u/d and cs pins, while still providing flexibility for production or calibration environments. both the cs and u/d input pins are tolerant of signals up to 12v. this allows the flexibility to multiplex the digital pot?s control signals onto application signals for manufacturing/calibration. 4.3 power-up when the device powers up, the last saved wiper setting is restored. while v dd < v min (2.7v), the electrical performance may not meet the data s heet specifications (see figure 4-2 ). the wiper may be unknown or initialized to the value stored in the eeprom. also the device may be capable of incrementing, decrementing and writing to its eeprom, if a valid command is detected on the cs and u/d pins. the default settings of the mcp4021/2/3/4 device?s from the factory are shown in ta b l e 4 - 1 . table 4-1: default factory settings selection it is good practice in your manufacturing flow to configure the device to your desired settings. 4.4 brown out if the device v dd is below the specified minimum voltage, care must be taken to ensure that the cs and u/d pins do not ?create? any of the serial commands. when the device v dd drops below v min (2.7v), the electrical performance may not meet the data sheet specifications (see figure 4-2 ). the wiper may be unknown or initialized to the value stored in the eeprom. also the device may be capable of incrementing, decrementing and writing to its eeprom if a valid command is detected on the cs and u/d pins. 4.5 serial interface inactive the serial interface is inactive any time the cs pin is at v ih and all write cycles are completed. figure 4-2: power-up and brown-out. package code default por wiper setting wiper code wiperlock? technology setting typical r ab value -202 mid-scale 1fh disabled 2.1 k -502 mid-scale 1fh disabled 5.0 k -103 mid-scale 1fh disabled 10.0 k -503 mid-scale 1fh disabled 50.0 k v wp v ss v dd 2.7v eeprom write protect outside specified ac/dc range
? 2006 microchip technology inc. ds21945d-page 29 mcp4021/2/3/4 5.0 serial interface 5.1 overview the mcp4021/2/3/4 utilizes a simple 2-wire interface to increment or decrement the digital potentiometer?s wiper terminal (w), store the wiper setting in non-vola- tile memory and turn the wiperlock technology feature on or off. this interface uses the chip select (cs ) pin, while the u/d pin is the up/down input. the increment/decrement protocol enables the device to move one step at a time through the range of possible resistance values. the wiper value is initialized with the value stored in the internal eeprom upon power-up. a wiper value of 00h connects the wiper to terminal b. a wiper value of 3fh connects the wiper to terminal a. increment commands move the wiper toward terminal a, but will not increment to a value greater than 3fh. decrement commands move the wiper toward terminal b, but will not decrement below 00h. refer to section 1.0 ?electri cal characteristics? , ac/dc electrical characteristics table for detailed input threshold and timing specifications. communication is unidirectiona l. therefore, the value of the current wiper settin g cannot be read out of the mcp402x device. 5.2 serial commands the mcp402x devices support 10 serial commands. the commands can be grouped into the following types: ? serial commands ? high-voltage serial commands all the commands are shown in table 5-1 . the command type is determined by the voltage level on the cs pin. the initial state that the cs pin must be driven is v ih . from v ih , the two levels that the cs pin can be driven are: ?v il ?v ihh if the cs pin is driven from v ih to v il , a serial command is selected. if the cs pin is driven from v ih to v ihh , a high-voltage serial command is selected. high-voltage serial commands control the state of the wiperlock technology. this is a unique feature, where the user can determine whet her or not to ?lock? or ?unlock? the wiper state. high-voltage serial commands increment/decrement the wiper regardless of the status of the wiperlock technology. table 5-1: commands command name saves wiper value in eeprom high voltage on cs pin? after command wiper is ?locked?/ ?unlocked? works when wiper is ?locked?? increment without writin g wiper setting to eeprom ??unlocked note 1 increment with writing wiper setting to eeprom yes ? unlocked note 1 decrement without writin g wiper setting to eeprom ??unlocked note 1 decrement with writing wiper setting to eeprom yes ? unlocked note 1 write wiper setting to eeprom yes ? unlocked note 1 high-voltage increment and disable wiperlock technology yes yes unlocked yes high-voltage increment and enable wiperlock technology yes yes locked yes high-voltage decrement and disable wiperlock technology yes yes unlocked yes high-voltage decrement and enable wiperlock technology yes yes locked yes write wiper setting to eepr om and disable wiperlock technology yes yes unlocked yes write wiper setting to eepr om and enable wiperlock technology yes yes locked yes note 1: this command will only complete if wiper is ?unlocked? (wiperlock technology is disabled).
mcp4021/2/3/4 ds21945d-page 30 ? 2006 microchip technology inc. 5.2.1 increment without writing wiper setting to eeprom this mode is achieved by initializing the u/d pin to a high state (v ih ) prior to achieving a low state (v il ) on the cs pin. subsequent rising edges of the u/d pin increment the wiper setting toward terminal a. this is shown in figure 5-1 . after the wiper is incremented to the desired position, the cs pin should be forced to v ih to ensure that ?unexpected? transitions (on the u/d pin do not cause the wiper setting to increment. driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired increment occurs. the eeprom value has not been updated to this new wiper value, so if the device voltage is lowered below the ram retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with the wiper setting in the eeprom. after the cs pin is driven to v ih (from v il ), any other serial command may immediately be entered. this is since an eeprom write cycle (t wc ) is not active. figure 5-1: increment without writing wiper setting to eeprom. note: the wiper value will not overflow. that is, once the wiper value equals 0x3f, subsequent increment commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x+1 x x+2 x+3 x+4 x xxxx note: if wiperlock technology enabled, wiper will not move. v ih v ih 5 6 v il v il
? 2006 microchip technology inc. ds21945d-page 31 mcp4021/2/3/4 5.2.2 increment with writing wiper setting to eeprom this mode is achieved by initializing the u/d pin to a high state (v ih ) prior to achieving a low state (v il ) on the cs pin. subsequent rising edges of the u/d pin increment the wiper setting toward terminal a. this is shown in figure 5-2 . after the wiper is incremented to the desired position, the u/d pin should be driven low (v il ). then when the cs pin is forced to v ih , the wiper value is written to the eeprom. therefore, if the de vice voltage is lowered below the ram retention vo ltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the eeprom). to ensure that ?unexpecte d? transitions on the u/d pin do not cause the wiper setting to increment, the u/d pin should be driven low and the cs pin forced to v ih as soon as possible (within device specifications) after the last desired increment occurs. after the cs pin is driven to v ih (from v il ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-2: increment with writing wiper setting to eeprom. note: the wiper value will not overflow. that is, once the wiper value equals 0x3f, subsequent increment commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x+1 x x+2 x+3 x+4 x xxxx x+4 note: if wiperlock technology enabled, wiper will not move. v ih v ih v ih 5 6 v il v il t wc
mcp4021/2/3/4 ds21945d-page 32 ? 2006 microchip technology inc. 5.2.3 decrement without writing wiper setting to eeprom this mode is achieved by initializing the u/d pin to a low state (v il ) prior to achieving a low state (v il ) on the cs pin. subsequent rising edges of the u/d pin will decrement the wiper setting toward terminal b. this is shown in figure 5-3 . after the wiper is decremented to the desired position, the u/d pin should be forced low (v il ) and the cs pin should be forced to v ih . this will ensure that ?unexpected? transitions on the u/d pin do not cause the wiper setting to decrement. driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired increment occurs. the eeprom value has not been updated to this new wiper value, so, if the device voltage is lowered below the ram retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with the wiper setting in the eeprom. after the cs pin is driven to v ih (from v il ), any other serial command may immediately be entered, since an eeprom write cycle (t wc ) is not started. figure 5-3: decrement without writing wiper setting to eeprom. note: the wiper value will not underflow. that is, once the wiper value equals 0x00, subsequent decrement commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x-1 x x-2 x-3 x-4 x xxxx note: if wiperlock technology enabled, wiper will not change. v ih v ih 5 6 v il v il v il
? 2006 microchip technology inc. ds21945d-page 33 mcp4021/2/3/4 5.2.4 decrement with writing wiper setting to eeprom this mode is achieved by initializing the u/d pin to a low state (v il ) prior to achieving a low state (v il ) on the cs pin. subsequent rising edges of the u/d pin decrement the wiper setting (toward terminal b). this is shown in figure 5-4 . after the wiper is decremented to the desired position, the u/d pin should remain high (v ih ). then when the cs pin is raised to v ih , the wiper value is written to the eeprom. therefore, if the de vice voltage is lowered below the ram retention vo ltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the eeprom). to ensure that ?unexpecte d? transitions on the u/d pin do not cause the wiper setting to decrement, the u/d pin should be driven low (v il ) and the cs pin forced to v ih as soon as possible (within device specifications) after the last desired increment occurs. after the cs pin is driven to v ih (from v il ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-4: decrement with writing wi per setting to eeprom. note: the wiper value will not underflow. that is, once the wiper value equals 0x00, subsequent decrement commands are ignored. eeprom u/d cs wiper wiperlock? technology wiperlock technology enable wiperlock technology disable x-1 x x-2 x-3 x-4 x xxxx x-4 1 2 3 4 note: if wiperlock technology enabled, wiper will not change. v ih v ih 5 6 v il v il t wc
mcp4021/2/3/4 ds21945d-page 34 ? 2006 microchip technology inc. 5.2.5 write wiper setting to eeprom to write the current wiper setting to eeprom, force both the cs pin and u/d pin to v ih . then force the cs pin to v il . before there is a rising edge on the u/d pin, force the cs pin to v ih . this causes the wiper setting value to be written to eeprom. when the cs pin is forced to v ih , the wiper value is written to the eeprom. t herefore, if the device voltage is lowered below the ram retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the eeprom). to ensure that ?unexpecte d? transitions on the u/d pin do not cause the wiper setting to increment, force the cs pin to v ih as soon as possible (within device specifications) after the u/d pin is forced to v il . after the cs pin is driven to v ih (from v il ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-5: write wiper setting to eeprom. note: after the u/d pin is forced to v il , each rising edge on the u/d pin will cause the wiper to increment. this is the same command as the ? incre- ment with writing wiper setting to eeprom ? command, but the u/d pin is held at v il, so the wiper is not incre- mented. eeprom u/d cs wiper wiperlock? technology wiperlock technology enable wiperlock technology disable x+4 x x+4 v ih v ih v ih 5 6 v il v il t wc
? 2006 microchip technology inc. ds21945d-page 35 mcp4021/2/3/4 5.2.6 high-voltage increment and disable wiperl ock technology this mode is achieved by initializing the u/d pin to a high state (v ih ) prior to the cs pin being driven to v ihh . subsequent rising edges of the u/d pin increment the wiper setting toward terminal a. set the u/d pin to the high state (v ih ) prior to forcing the cs pin to v ih . this begins a write cycle and disables the wiperlock technology feature (see figure 5-6 ). after the cs pin is driven to v ih (from v ihh ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-6: high-voltage increment and disable wiperlock? technology. note: the wiper value will not overflow. that is, once the wiper value equals 0x3f, subsequent increment commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x+1 x x+2 x+3 x+4 x xxxx x+4 v ihh v ih v ih v ih 5 6 v il v ih t wc
mcp4021/2/3/4 ds21945d-page 36 ? 2006 microchip technology inc. 5.2.7 high-voltage increment and enable wiperlock technology this mode is achieved by initializing the u/d pin to a high state (v ih ) prior to the cs pin being driven to v ihh . subsequent rising edges of the u/d pin increment the wiper setting toward terminal a. set the u/d pin to the low state (v il ) prior to forcing the cs pin to v ih . this begins a write cycle and enables the wiperlock technology feature (see figure 5-7 ). after the cs pin is driven to v ih (from v ihh ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-7: high-voltage increment and enable wiperlock? technology. note: the wiper value will not overflow. that is, once the wiper value equals 0x3f, subsequent increment commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x+1 x x+2 x+3 x+4 x xxxx x+4 v ihh v ih v ih 5 6 v il v ih v il t wc
? 2006 microchip technology inc. ds21945d-page 37 mcp4021/2/3/4 5.2.8 high-voltage decrement and disable wiperloc k technology this mode is achieved by initializing the u/d pin to a low state (v il ) prior to the cs pin being driven to v ihh . subsequent rising edges of the u/d pin decrement the wiper setting toward terminal b. set the u/d pin to the low state (v il ) prior to forcing the cs pin to v ih . this begins a write cycle and disables the wiperlock technology feature (see figure 5-8 ). after the cs pin is driven to v ih (from v ihh ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-8: high-voltage decrement and disable wiperlock? technology. note: the wiper value will not underflow. that is, once the wiper value equals 0x00, subsequent decrement commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x xxxx x-4 x-1 x x-2 x-3 x-4 v ihh v ih v ih 5 6 v il v ih v il t wc
mcp4021/2/3/4 ds21945d-page 38 ? 2006 microchip technology inc. 5.2.9 high-voltage decrement and enable wiperlock technology this mode is achieved by initializing the u/d pin to the low state (v il ) prior to driving the cs pin to v ihh . subsequent rising edges of the u/d pin decrement the wiper setting toward terminal b. set the u/d pin to a high state (v ih ) prior to forcing the cs pin to v ih . this begins a write cycle and enables the wiperlock technology feature (see figure 5-9 ). after the cs pin is driven to v ih (from v ihh ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-9: high-voltage decrement and enable wiperlock? technology. note: the wiper value will not underflow. that is, once the wiper value equals 0x00, subsequent decrement commands are ignored. eeprom u/d cs wiper 1 2 3 4 wiperlock? technology wiperlock technology enable wiperlock technology disable x xxxx x-4 x-1 x x-2 x-3 x-4 v ihh v dd v ih v ih 5 6 v ih v il t wc
? 2006 microchip technology inc. ds21945d-page 39 mcp4021/2/3/4 5.2.10 write wiper setting to eeprom and disable wiperlock technology this mode is achieved by keeping the u/d pin static (either at v il or at v ih ), while the cs pin is driven from v ih to v ihh and then returned to v ih . when the falling edge of the cs pin occurs (from v ihh to v ih ), the wiper value is written to eepr om and the wiperlock technology is disabled (see figure 5-10 ). to ensure that ?unexpecte d? transitions on the u/d pin do not cause the wiper setting to change, force the cs pin to v ih as soon as possible (within device specifications) after the cs pin is forced to v ihh . after the cs pin is driven to v ih (from v ihh ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-10: write wiper setting to eeprom and disable wiperlo ck? technology. eeprom u/d cs wiper wiperlock? technology x+4 x x+4 wiperlock technology enable wiperlock technology disable v ihh v ih v il v ih v ih t wc
mcp4021/2/3/4 ds21945d-page 40 ? 2006 microchip technology inc. 5.2.11 write wiper setting to eeprom and enable wiperlock technology this mode is achieved by initializing the u/d and cs pins to a high state (v ih ) prior to the cs pin being driven to v ihh (from v ih ). set the u/d pin to a low state (v il ) prior to forcing the cs pin to v ih (from v ihh ). this begins a write cycle and enables the wiperlock technology feature (see figure 5-11 ). to ensure that ?unexpecte d? transitions on the u/d pin do not cause the wiper setting to increment, force the cs pin to v ih as soon as possible (within device specifications) after the u/d pin is forced to v il . after the cs pin is driven to v ih (from v ihh ), all other serial commands are igno red until the eeprom write cycle (t wc ) completes. figure 5-11: write wiper setting to eeprom and enable wiperlock? technology. eeprom u/d cs wiper wiperlock? technology x+4 x x+4 wiperlock technology enable wiperlock technology disable v ihh v ih v ih v ih v il t wc
? 2006 microchip technology inc. ds21945d-page 41 mcp4021/2/3/4 5.3 cs high voltage depending on the requirement s of the system, the use of high voltage (v ihh ) on the cs pin, may or may not be required during syst em operation. table 5-2 shows possible system applications, and whether a high voltage (v ihh ) is required on the system. the mcp402x supports six high-voltage commands (the cs input voltage must meet the v ihh specification). table 5-2: high-voltage applications 5.3.1 techniques to force the cs pin to v ihh the circuit in figure 5-12 shows a method using the tc1240a doubling charge pump. when the shdn pin is high, the tc1240a is off, and the level on the cs pin is controlled by the pic? microcontrollers (mcus) io2 pin. when the shdn pin is low, the tc1240a is on and the v out voltage is 2 * v dd . the resistor r 1 allows the cs pin to go higher than the voltage such that the pic mcu?s io2 pin ?clamps? at approximately v dd . figure 5-12: using the tc1240a to generate the v ihh voltage. the circuit in figure 5-13 shows the method used on the mcp402x non-volatile digital potentiometer evaluation board. this method requires that the system voltage be approximat ely 5v. this ensures that when the pic10f206 enters a brown-out condition, there is an insufficent voltage level on the cs pin to change the stored value of the wiper. the mcp402x non-volatile digital potentiometer evaluation board user?s guide (ds51546) contains a complete schematic. gp0 is a general purpose i/o pin, while gp2 can either be a general purpose i/o pin or it can output the internal clock. for the serial commands, configure the gp2 pin as an input (high impedence). the ou tput state of the gp0 pin will determine the voltage on the cs pin (v il or v ih ). for high-voltage serial commands, force the gp0 output pin to output a high level (v oh ) and configure the gp2 pin to output the internal clock. this will form a charge pump and increase the voltage on the cs pin (when the system voltage is approximately 5v). figure 5-13: mcp402x non-volatile digital potentiometer evaluation board (mcp402xev) implementation to generate the v ihh voltage. system operation high voltage production calibration only - system should not update wiper setting from calibration unit wiperlock? technogy disabled during system operation not required wiper setting can be updated and ?locked? during system operation required cs pic ? mcu mcp402x r 1 io1 io2 c 2 tc1240a v in shdn c+ c- v out c 1 cs pic10f206 mcp402x r 1 gp0 gp2 c 2 c 1
mcp4021/2/3/4 ds21945d-page 42 ? 2006 microchip technology inc. 6.0 resistor digital potentiometer applications can be divided into two categories: ? rheostat configuration ? potentiometer (or voltage divider) configuration figure 6-1 shows a block diagram for the mcp402x resistors. figure 6-1: resistor block diagram. step resistance (r s ) is the resistance from one tap setting to the next. this value will be dependent on the r ab value that has been selected. table 6-1 shows the typical step resistances for each device. the total resistance of the device has minimal variation due to operating voltage (see figure 2-6 , figure 2-17 , figure 2-27 or figure 2-37 ). table 6-1: typical step resistances terminal a and b, as well as the wiper w, do not have a polarity. these terminals can support both positive and negative current. r s a r s r s r s b n = 63 n = 62 n = 61 n = 1 n = 0 r w (1) w 01h analog mux r w (1) 00h r w (1) 3dh r w (1) 3eh r w (1) 3fh note 1: the wiper resistance is tap dependent. that is, each tap selection resistance has a small variation. this variation effects the smaller resistance devices (2.1 k ) more. part number typical resistance ( ) total (r ab ) step (r s ) mcp402x-203e 2100 33.33 mcp402x-503e 5000 79.37 mcp402x-104e 10000 158.73 mcp402x-504e 50000 793.65
? 2006 microchip technology inc. ds21945d-page 43 mcp4021/2/3/4 6.1 resistor configurations 6.1.1 rheostat configuration when used as a rheostat, two of the three digital potentiometer?s terminals are used as a resistive element in the circuit. with terminal w (wiper) and either terminal a or terminal b, a variable resistor is created. the resistance will depend on the tap setting of the wiper and the wiper?s resistance. the resistance is controlled by changing the wiper setting. the unused terminal (b or a) should be left floating. figure 6-2 shows the two possible resistors that can be used. reversing the polarity of the a and b terminals will not affect operation. figure 6-2: rheostat configuration. this allows the control of the total resistance between the two nodes. the total resistance depends on the ?starting? terminal to the wiper terminal. at the code 00h, the r bw resistance is minimal (r w ), but the r aw resistance in maximized (r ab + r w ). conversely, at the code 3fh, the r aw resistance is minimal (r w ), but the r bw resistance in maximized (r ab + r w ). the resistance step size (r s ) equates to one lsb of the resistor. the change in wiper-to-end terminal resistance over temperature is shown in figure 2-6 , figure 2-17 , figure 2-27 and figure 2-37 . the most variation over temperature will occur in the first few codes due to the wiper resistance coefficient affecting the total resistance. the remaining codes are dominated by the total resistance tempco r ab . 6.1.2 potentiometer configuration when used as a potentiometer, all three terminals are tied to different nodes in the circuit. this allows the potentiometer to output a voltage proportional to the input voltage. this configuration is sometimes called voltage divider mode. the potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in figure 6-3 . reversing the polarity of the a and b terminals will not affect operation. figure 6-3: potentiometer configuration. the temperature coefficient of the r ab resistors is minimal by design. in this c onfiguration, the resistors all change uniformally, so minimal variation should be seen. the wiper resistor temperat ure coefficient is different from the r ab temperature coefficient. the voltage at node v 3 ( figure 6-3 ) is not dependent on this wiper resistance, just the ratio of the r ab resistors, so this temperature coefficient in most cases can be ignored. note: to avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure t he current flow never exceeds 2.5 ma. a b w resistor r aw r bw or note: to avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure t he current flow never exceeds 2.5 ma. a b w v 1 v 3 v 2
mcp4021/2/3/4 ds21945d-page 44 ? 2006 microchip technology inc. 6.2 wiper resistance wiper resistance is the series resistance of the wiper. this resistance is typically measured when the wiper is positioned at either zero-scale (00h) or full-scale (3fh). the wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error. the wiper resistance in rheostat applications can create significant non-linearit y as the wiper is moved toward zero-scale (00h). the lower the nominal resistance, the greater the possible error. wiper resistance is significant depending on the devices operating voltage. as the device voltage decreases, the wiper resistance increases (see figure 6-4 and ta b l e 6 - 2 ). in a rheostat configuration, this change in voltage needs to be taken into account, particularly for the lower resistance devices. for the 2.1 k device, the maximum wiper resistance at 5.5v is approximately 6% of the total resistance, while at 2.7v, it is approximately 15.5% of the total resistance. in a potentiometer configur ation, the wiper resistance variation does not effect the output voltage seen on the terminal w pin. the slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages), where resistance increases faster than the voltage drop (at low voltages). figure 6-4: relationship of wiper resistance (r w ) to voltage since there is minimal variation of the total device resistance over voltage, at a constant temperature (see figure 2-6 , figure 2-17 , figure 2-27 or figure 2-37 ), the change in wiper resistance over voltage can have a significant impact on the inl and dnl error. table 6-2: typical step resistances and relationship to wiper resistance r w v dd note: the slope of the resistance has a linear area (at the higher voltages) and a non- linear area (at the lower voltages). resistance ( )r w / r s (%) (1) r w / r ab (%) (2) typical wiper (r w ) r w = typical r w = max @ 5.5v r w = max @ 2.7v r w = typical r w = max @ 5.5v r w = max @ 2.7v total (r ab ) step (r s ) typical max @ 5.5v max @ 2.7v 2100 33.33 75 125 325 225.0% 375.0% 975.0% 3.57% 5.95% 15.48% 5000 79.37 75 125 325 94.5% 157.5% 409.5% 1.5% 2.50% 6.50% 10000 158.73 75 125 325 47.25% 78.75% 204.75% 0.75% 1.25% 3.25% 50000 793.65 75 125 325 9.45% 15.75% 40.95% 0.15% 0.25% 0.65% note 1: r s is the typical value. the variation of this resistance is minimal over voltage. 2: r ab is the typical value. the variation of this resistance is minimal over voltage.
? 2006 microchip technology inc. ds21945d-page 45 mcp4021/2/3/4 6.3 operational characteristics understanding the operational characteristics of the device?s resistor components is important to the system design. 6.3.1 accuracy 6.3.1.1 integral non-linearity (inl) inl error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. these endpoints are from 0x00 to 0x3f. refer to figure 6-5 . positive inl means higher resistance than ideal. negative inl means lower resistance than ideal. figure 6-5: inl accuracy. 6.3.1.2 differential non-linearity (dnl) dnl error is the measure of variations in code widths from the ideal code width. a dnl error of zero would imply that every code is exactly 1 lsb wide. figure 6-6: dnl accuracy. 6.3.1.3 ratiometric temperature coefficient the ratiometric temperature coefficient quantifies the error in the ratio r aw /r wb due to temperature drift. this is typically the critical error when using a potentiometer device (mcp4021 and mcp4023) in a voltage divider configuration. 6.3.1.4 absolute temperature coefficient the absolute temperature co efficient quantifies the error in the end-to-end resistance (nominal resistance r ab ) due to temperature drift. this is typically the critical error when using a rheostat device (mcp4022 and mcp4024) in an adjustabl e resistor configuration. 111 110 101 100 011 010 001 000 digital input code actual transfer function inl < 0 ideal transfer function inl < 0 digital pot output 111 110 101 100 011 010 001 000 digital input code actual transfer function ideal transfer function narrow code < 1 lsb wide code, > 1 lsb digital pot output
mcp4021/2/3/4 ds21945d-page 46 ? 2006 microchip technology inc. 6.3.2 monotonic operation monotonic operation means that the device?s resistance increases with every step change (from terminal a to terminal b or terminal b to terminal a). the wiper resistance is different at each tap location. when changing from one tap position to the next (either increasing or decreasing), the r w is less than the r s . when this change occurs , the device voltage and temperature are ?the same? for the two tap positions. figure 6-7: resistance, r bw . 0x3f 0x3e 0x3d 0x03 0x02 0x01 0x00 digital input code resistance (r bw ) r w (@ tap) r s0 r s1 r s3 r s62 r s63 r bw = r sn + r w(@ tap n ) n = 0 n = ?
? 2006 microchip technology inc. ds21945d-page 47 mcp4021/2/3/4 7.0 design considerations in the design of a system with the mcp402x devices, the following considerations should be taken into account: ? the power supply ? the layout 7.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-fr equency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 7-1 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 7-1: typical microcontroller connections. 7.2 layout considerations inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp402x?s performance. careful board layout will minimize these effects and increase the signal-to- noise ratio (snr). bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the sili con is capable of providing. particularly harsh environm ents may require shielding of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. v dd v dd v ss v ss mcp4021/2/3/4 0.1 f pic ? microcontroller 0.1 f u/d cs w b a
mcp4021/2/3/4 ds21945d-page 48 ? 2006 microchip technology inc. 8.0 applications examples non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. the mcp4 021/2/3/4 devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within cmos process limitations (v dd = 2.7v to 5.5v). 8.1 set point threshold trimming applications that need accu rate detection of an input threshold event often need several sources of error eliminated. use of comp arators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applica- tions, the input source variation is beyond the designer?s control. if the entire system can be calibrated after assembly in a controlled environment (like factory test), these s ources of error are minimized, if not entirely eliminated. figure 8-1 illustrates a common digital potentiometer configuration. this configuration is often referred to as a ?windowed voltage divider?. note that r 1 and r 2 are not necessary to create the voltage divider, but their presence is useful when the desired threshold has limited range. it is ?windowed? because r 1 and r 2 can narrow the adjustable range of v trip to a value much less than v dd ? v ss . if the output range is reduced, the magnitude of each output step is reduced. this effectively increases the trimming resolution for a fixed digital potentiometer resolution. this technique may allow a lower-cost digital potentiometer to be utilized (64 steps instead of 256 steps). the mcp4021?s and mcp4023?s low dnl performance is critical to meeting calibration accuracy in production without having to use a higher precision digital potentiometer. equation 8-1: calculating the wiper setting from the desired v trip figure 8-1: using the digital potentiometer to set a precise output voltage. 8.1.1 trimming a threshold for an optical sensor if the application has to calibrate the threshold of a diode, transistor or resistor, a variation range of 0.1v is common. often, the desired resolution of 2 mv or better is adequate to accura tely detect the presence of a precise signal. a ?windowed? voltage divider, utilizing the mcp4021 or mcp4023, would be a potential solution as shown in figure 8-2 . figure 8-2: set point or threshold calibration. v trip v dd r 2 r wb + r 1 r ab r 2 ++ ---------------------------------- - ?? ?? = r ab r nominal = r wb r ab d 63 ----- - ?? ?? ? = d v trip v dd -------------- ?? ?? r 1 r ab r 2 ++ () r 2 ? () ? ?? ?? 63 ? = where: d = digital potentiometer wiper setting (0-63) v dd v out r 2 a r 1 w b mcp4021 cs u/d v trip 0.1 f comparator v cc+ v cc? v dd r sense r 1 r 2 b a v dd w mcp4021 cs u/d mcp6021
? 2006 microchip technology inc. ds21945d-page 49 mcp4021/2/3/4 8.2 operational amplifier applications figure 8-3 , figure 8-4 and figure 8-5 illustrate typical amplifier circuits that could replace fixed resistors with the mcp4021/2/3/4 to achieve digitally-adjustable analog solutions. figure 8-4 shows a circuit t hat allows a non-inverting amplifier to have its? offset and gain to be independently trimmed. the mcp4021 is used along with resistors r1 and r2 to set the offset voltage. the sum of r1 + r2 resistance should be significantly greater (> 100 times) the resistance value of the mcp4021. this allows each increment or decrement in the mcp4021 to be a fine adjustment of the offset vo ltage. the input voltage of the op amp (v in ) should be centered at the op amps v w voltage. the gain is adjusted by the mcp4022. if the resistance value of the mcp4022 is small compared to the resistance value of r3, then this is a fine adjustment of the gain. if the resistance value of the mcp4022 is equal (or large) compared to the resistance value of r3, then this is a course adjustment of the gain. in gerneral, trim the course adjustments first and then trim the fine adjustments. figure 8-3: trimming offset and gain in an inverting amplifier. figure 8-4: trimming offset and gain in a non-inverting amplifier. figure 8-5: programmable filter. op amp v in v out b a w + ? mcp4021 r 1 r 2 b a v dd w r 3 r 4 mcp402x mcp6001 op amp v in v out ? + r 1 r 2 b a v dd w r 3 mcp6291 mcp4021 mcp4022 w a v dd v w op amp v in v out b a w + ? mcp4021 r 1 r 2 b a v dd w mcp4022 r 3 r 4 f c 1 2 r eq c ?? ----------------------------- = pot 1 pot 2 r eq r 1 r ab r wb ? + () r 2 r wb + () r w + || = thevenin equivalent mcp6021
mcp4021/2/3/4 ds21945d-page 50 ? 2006 microchip technology inc. 8.3 temperature sensor applications thermistors are resistors with very predictable variation with temp erature. thermistors are a popular sensor choice when a low-cost, temperature-sensing solution is desired. unfo rtunately, thermistors have non-linear characteristics that are undesirable, typically requiring trimming in an application to achieve greater accuracy. there are several common solutions to trim and linearize thermistors. figure 8-6 and figure 8-7 are simple methods for linearizing a 3-terminal ntc thermistor. both are simple voltage dividers using a positive temperature coefficient (ptc) resistor (r 1 ) with a transfer function capable of compensating for the lineararity error in the negative temperature coefficient (ntc) thermistor. the circuit, illustrated by figure 8-6 , utilizes a digital rheostat for trimming the offset error caused by the thermistor?s part-to-part vari ation. this solution puts the digital potentiometer?s r w into the voltage divider calculation. the mcp4021/2/3/4?s r ab temperature coefficient is 50 ppm (-20c to +70c). r w ?s error is substantially greater than r ab ?s error because r w varies with v dd , wiper setting and te mperature. for the 50 k devices, the error introduced by r w is, in most cases, insignificant as long as the wiper setting is > 6. for the 2 k devices, the error introduced by r w is significant because it is a higher percentage of r wb . for these reasons, the circuit illustrated in figure 8-6 is not the most optimum method for ?exciting? and linearizing a thermistor. figure 8-6: thermistor calibration using a digital potentiometer in a rheostat configuration. the circuit illustrated by figure 8-7 utilizes a digital potentiometer for trimming the offset error. this solution removes r w from the trimming equation along with the error associated with r w . r 2 is not required, but can be utilized to reduce the trimming ?window? and reduce variation due to the digital potentiometer?s r ab part-to-part variability. figure 8-7: thermistor calibration using a digital potentiomete r in a potentiometer configuration. 8.4 wheatstone bridge trimming another common configuration to ?excite? a sensor (such as a strain gauge, pressure sensor or thermistor) is the wheatstone bridge configuration. the wheat- stone bridge provides a differential output instead of a single-ended output. figure 8-8 illustrates a wheatstone bridge utilizing one to three digital potentiometers. the digital potentiometers in this example are used to trim t he offset and gain of the wheatstone bridge. figure 8-8: wheatstone bridge trimming. ntc v dd mcp4022 v out thermistor r 1 r 2 w a ntc v dd mcp4021 v out thermistor r 1 r 2 v dd mcp4022 v out 2.1 k mcp4022 50 k mcp4022 50 k
? 2006 microchip technology inc. ds21945d-page 51 mcp4021/2/3/4 9.0 development support 9.1 evaluation/demonstration boards currently there are three boards that are available that can be used to evaluate the mcp4021/2/3/4 family of devices. 1. the mcp402x digital potentiomenter evalua- tion board kit (mcp402xev) contains a simple demonstration board utilizing a pic10f206, the mcp4021 and a blank pcb, which can be populated with any desired mcp4021/2/3/4 device in a sot-23-5, sot-23-6 or 150 mil soic 8-pin package. this board has two push buttons to control when the pic ? microcontroller generates mcp402x serial commands. the example firmware dem- onstrates the following commands: ? increment ? decrement ? high-voltage increment and enable wiperlock technology ? high-voltage decrement and enable wiperlock technology ? high-voltage increment and disable wiperlock technology ? high-voltage decrement and disable wiperlock technology the populated board (with the mcp4021) can be used to evaluate the other mcp402x devices by appropriately jumpering the pcb pads. 2. the sot-23-5/6 eval uation board (vsupev2) can be used to evaluate the characteristics of the mcp4022, mcp4023 and mcp4024 devices. 3. the 8-pin soic/msop/ tssop/dip evaluation board (soic8ev) can be used to evaluate the characteristics of the mcp4021 device in either the soic or msop package. 4. the mcp4xxx digital po tentiomete r daughter board allows the system designer to quickly evaluate the operation of microchip technol- ogy's mcp42xxx and mcp402x digital poten- tiometers. the board supports two mcp42xxx devices and an mcp402x device, which can be replaced with an mcp401x device. the board also has a voltage doubler device (tc1240a), which can be used to show the wiperlock? technology feature of the mcp4021. these boards may be purchased directly from the microchip web site at www.microchip.com.
mcp4021/2/3/4 ds21945d-page 52 ? 2006 microchip technology inc. 10.0 packaging information 10.1 package marking information 5-lead sot-23 ( mcp4024 ) example: xxnn dp25 part number code mcp4024t-202e/ot dpnn mcp4024t-502e/ot dqnn mcp4024t-103e/ot drnn mcp4024t-503e/ot dsnn note: applies to 5-lead sot-23 6-lead sot-23 ( mcp4022 / mcp4023 ) example: xxnn ba25 part number code mcp402 2 mcp402 3 mcp402 x t-202e/ch bann benn mcp402 x t-502e/ch bbnn bfnn mcp402 x t-103e/ch bcnn bgnn mcp402 x t-503e/ch bdnn bhnn note: applies to 6-lead sot-23 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2006 microchip technology inc. ds21945d-page 53 mcp4021/2/3/4 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead msop (mcp4021) example: xxxxxx ywwnnn 402122 530256 example: 8-lead dfn (2x3) (mcp4021) xxx yww nnn aaa 530 256 8-lead soic (150 mil) (mcp4021) example: xxxxxxxx xxxxyyww nnn 402153e sn^^ 0530 256 3 e part number code mcp4021t-202e/mc aaa mcp4021t-502e/mc aab mcp4021t-103e/mc aac mcp4021t-503e/mc aad note: applies to 8-lead dfn part numbers code 8l-msop 8l-soic mcp4021-202e/ms mcp4021-202e/sn 22 mcp4021-502e/ms mcp4021-502e/sn 52 mcp4021-103e/ms mcp4021-103e/sn 13 mcp4021-503e/ms mcp4021-503e/sn 53
mcp4021/2/3/4 ds21945d-page 54 ? 2006 microchip technology inc. 5-lead plastic small outline transistor (ot) (sot-23) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging 1 p d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 b mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 f foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: eiaj equivalent: sc-74a drawing no. c04-091 * controlling parameter revised 09-12-05
? 2006 microchip technology inc. ds21945d-page 55 mcp4021/2/3/4 6-lead plastic small outline transistor (ch) (sot-23) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging 1 d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 bsc .075 bsc p1 outside lead pitch 0.95 bsc .038 bsc p pitch 6 6 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: jeita (formerly eiaj) equivalent: sc-74a * controlling parameter drawing no. c04-120 bsc: basic dimension. theoretically exact value shown without tolerances. see asme y14.5m revised 09-12-05
mcp4021/2/3/4 ds21945d-page 56 ? 2006 microchip technology inc. 8-lead plastic dual-flat no-lead package (mc) 2x3x0.9 mm body (dfn) ? saw singulated note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging number of pins pitch overall height standoff contact thickness overall length overall width exposed pad length exposed pad width contact width contact length contact-to-exposed pad units dimension limits n e a a1 a3 d e d2 e2 b l k 0.80 0.00 1.30 1.50 0.18 0.30 0.20 8 0.50 bsc 0.90 0.02 0.20 ref 2.00 bsc 3.00 bsc ? ? 0.25 0.40 ? 1.00 0.05 1.75 1.90 0.30 0.50 ? min nom max millimeters notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. significant characteristic 4. package is saw singulated 5. dimensioning and tolerancing per asme y14.5m bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. microchip technology drawing no. c04?123, sept. 8, 2006 a3 a1 note 2 note 1 note 1 e2 d2 bottom view exposed pad k l 1 2 n e b top view 2 1 n d e a
? 2006 microchip technology inc. ds21945d-page 57 mcp4021/2/3/4 8-lead plastic micro small outline package (ms) (msop) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging l l1 ? c a2 a1 a b 2 1 note 1 e e e1 d n number of pins pitch overall height molded package thickness standoff overall width molded package width overall length foot length footprint foot angle lead thickness lead width units dimension limits n e a a2 a1 e e1 d l l1 ? c b ? 0.75 0.00 0.40 0 0.08 0.22 8 0.65 bsc ? 0.85 ? 4.90 bsc 3.00 bsc 3.00 bsc 0.60 0.95 ref ? ? ? 1.10 0.95 0.15 0.80 8 0.23 0.40 min nom max millimeters notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. microchip technology drawing no. c04?111, sept. 8, 2006
mcp4021/2/3/4 ds21945d-page 58 ? 2006 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2006 microchip technology inc. ds21945d-page 59 mcp4021/2/3/4 appendix a: revision history revision d (october 2006) ? changed the eeprom write cycle time (t wc ) from a maximum of 5 ms to a maximum of 10 ms (overvoltage and temperature) with a typical of 5ms ? for the 10 k device, the rheostat differential non-linearity specification at 2.7v was changed from 0.5 lsb to 1.0 lsb ? figure 2-9 in section 2.0 ?typical performance curves? was updated with the correct data. ? added figure 2-48 for -3 db bandwidth information. ? updated available development tools. ? added disclaimer to package outline drawings. revision c (november 2005) ? enhanced descriptions ? reordered sections ? added 8-lead msop and dfn packages revision b (april 2005) ? updated part numbers in product identifcation section (pis) ? added appendix a: revision history revision a (april 2005) ? original release of this document
mcp4021/2/3/4 ds21945d-page 60 ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. ds21945d-page 61 mcp4021/2/3/4 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp4021: single potentiometer with u/d interface mcp4021t: single potentiometer with u/d interface (tape and reel) (soic, msop) mcp4022: single rheostat with u/d interface mcp4022t: single rheostat with u/d interface (tape and reel) (sot-23-6) mcp4023: single potentiometer to gnd with u/d interface mcp4023t: single potentiometer to gnd with u/d interface (tape and reel) (sot-23-6) mcp4024: single rheostat to gnd with u/d interface mcp4024t: single rheostat to gnd with u/d interface (tape and reel)(sot-23-5) resistance version: 202 = 2.1 k 502 = 5 k 103 = 10 k 503 = 50 k temperature range: e = -40c to +125c package: ch = plastic small outline transistor, 6-lead mc = plastic dual flat no lead (2x3x0.9 mm), 8-lead ms = plastic msop, 8-lead sn = plastic soic, (150 mil body), 8-lead ot = plastic small outline transistor, 5-lead part no. x /xx package temperature range device examples: a) mcp4021-103e/ms: 10 k , 8-ld msop b) mcp4021-103e/sn: 10 k , 8-ld soic c) mcp4021t-103e/mc: t/r, 10 k , 8-ld dfn d) mcp4021t-103e/ms: t/r, 10 k , 8-ld msop e) mcp4021t-103e/sn: t/r, 10 k , 8-ld soic f) mcp4021-202e/ms: 2.1 k , 8-ld msop g) mcp4021-202e/sn: 2.1 k , 8-ld soic h) mcp4021t-202e/mc: t/r, 2.1 k , 8-ld dfn i) mcp4021t-202e/ms: t/r, 2.1 k , 8-ld msop j) mcp4021t-202e/sn: t/r, 2.1 k , 8-ld soic k) mcp4021-502e/ms: 5 k , 8-ld msop l) mcp4021-502e/sn: 5 k , 8-ld soic m) mcp4021t-502e/mc: t/r, 5 k , 8-ld dfn n) mcp4021t-502e/ms: t/r, 5 k , 8-ld msop o) mcp4021t-502e/sn: t/r, 5 k , 8-ld soic p) mcp4021-503e/ms: 50 k , 8-ld msop q) mcp4021-503e/sn: 50 k , 8-ld soic r) mcp4021t-503e/mc: t/r, 50 k , 8-ld dfn s) mcp4021t-503e/ms: t/r, 50 k , 8-ld msop t) mcp4021t-503e/sn: t/r, 50 k , 8-ld soic a) mcp4022t-202e/ch 2.1 k , 6-ld sot-23 b) mcp4022t-502e/ch 5 k , 6-ld sot-23 c) mcp4022t-103e/ch 10 k , 6-ld sot-23 d) mcp4022t-503e/ch 50 k , 6-ld sot-23 a) mcp4023t-202e/ch 2.1 k , 6-ld sot-23 b) mcp4023t-502e/ch 5 k , 6-ld sot-23 c) mcp4023t-103e/ch 10 k , 6-ld sot-23 d) mcp4023t-503e/ch 50 k , 6-ld sot-23 a) mcp4024t-202e/ot 2.1 k , 5-ld sot-23 b) mcp4024t-502e/ot 5 k , 5-ld sot-23 c) mcp4024t-103e/ot 10 k , 5-ld sot-23 d) mcp4024t-503e/ot 50 k , 5-ld sot-23 xxx resistance version
mcp4021/2/3/4 ds21945d-page 62 ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. ds21945d-page 63 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm , mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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