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general description the max3882 is a deserializer combined with clock and data recovery and limiting amplifier ideal for con- verting 2.488gbps/2.67gbps serial data to 4-bit-wide, 622mbps/667mbps parallel data for sdh/sonet appli- cations. the device accepts serial nrz input data as low as 10mv p-p of 2.488gbps/2.67gbps and generates four parallel lvds data outputs at 622mbps/667mbps. included is an additional high-speed serial data input for system loopback diagnostic testing. for data acqui- sition, the max3882 does not require an external refer- ence clock. however, if needed, the loopback input can be connected to an external reference clock of 155mhz/167mhz or 622mhz/667mhz to maintain a valid clock output in the absence of input data transi- tions. additionally, a ttl-compatible loss-of-lock output is provided. the device provides a vertical threshold adjustment to compensate for optical noise generated by edfas in wdm transmission systems. the max3882 operates from a single +3.3v supply and consumes 610mw. the max3882a operates at 2.488gbps only. the max3882? jitter performance exceeds all sdh/ sonet specifications. the device is available in a 6mm ? 6mm 36-pin qfn package. features ? no reference clock required for data acquisition ? input data rates: 2.488gbps or 2.67gbps ? fully integrated clock and data recovery with limiting amplifier and 1:4 demultiplexer ? parallel output rate: 622mbps/667mbps ? differential input range: 10mv p-p to 1.6v p-p with- out threshold adjust ? differential input range: 50mv p-p to 600mv p-p with threshold adjust ? 0.65ui high-frequency jitter tolerance ? loss-of-lock ( lol ) indicator ? wide input threshold adjust range: ?70mv ? maintain valid clock output in absence of data transitions ? system loopback input available for system diagnostic testing ? operating temperature range -40? to +85? ? low power dissipation: 610mw at +3.3v max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier ________________________________________________________________ maxim integrated products 1 36 35 34 33 32 31 30 v ctrl v ref caz- caz+ v cc v cc frefset 29 rateset 10 11 12 13 14 15 16 gnd v cc _vco fil v cc _vco v cc _out gnd 17 pclk- 28 v cc _out 18 pclk+ 20 21 22 23 24 25 26 pd0+ pd1- pd1+ gnd pd2- pd2+ pd3- 8 7 6 5 4 3 2 sis slbi- slbi+ v cc qfn sdi- sdi+ v cc 1 gnd 27 pd3+ 19 pd0- 9 top view max3882 lol lref 11 12 13 14 15 16 17 gnd v cc _vco fil v cc _vco v cc _out gnd pclk- 35 34 33 32 31 30 29 v ref caz- caz+ v cc tqfn + v cc frefset rateset 28 123456789 27 26 25 24 23 22 21 20 19 v cc _out 18 pclk+ 10 lref 36 max3882a v ctrl sis slbi- slbi+ v cc sdi- sdi+ v cc gnd pd0+ pd1- pd1+ gnd pd2- pd2+ pd3- pd3+ pd0- lol pin configurations ordering information 19-2718; rev 1; 11/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code m ax 3882e g x -40 o c to +85 o c 36 qfn g3666-1 m ax 3882ae tx + -40 o c to +85 o c 36 tqfn t3666-2 sdh/sonet receivers and regenerators add/drop multiplexers digital cross-connects sdh/sonet test equipment dwdm transmission systems applications
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc ................................................-0.5 to +5.0v input voltage levels (sdi+, sdi-, slbi+, slbi-) ...........(v cc - 1.0v) to (v cc + 0.5v) input current levels (sdi+, sdi-, slbi+, slbi-)..............?0ma lvds output voltage levels (pclk? pd_?.......................................-0.5v to (v cc + 0.5v) voltage at lol , rateset, sis, lref , v ref , fil, caz+, caz-, v ctrl , frefset ..........................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85?) 36-lead qfn (derate 32.4mw/? above +85?) .......830mw operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? dc electrical characteristics (v cc = +3.0 to +3.6v, t a = -40? to +85?. typical values are at +3.3v and at t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units supply current i cc 185 230 ma single-ended input voltage range v is figure 1 v cc - 0.8 v cc + 0.4 v input common-mode voltage range figure 1 v cc - 0.4 v cc v input termination to v cc r in 42.5 50 57.5 ? differential input voltage range with threshold adjust enabled sdi+, sdi- figure 2 100 600 mv p-p threshold adjustment range v th figure 2 -170 +170 mv threshold-control voltage v ctrl (note 2) 0.302 2.097 v threshold-control linearity 5% threshold setting accuracy figure 2 -18 +18 mv 15mv |v th | 80mv -6 +6 threshold setting stability 80mv < |v th | 170mv -12 +12 mv v ref voltage output r l = 50k ? ? v od ? ?? v od ? 25 mv lvds offset output voltage 1.125 1.275 v lvds change in magnitude of output offset voltage for complementary states ?? v os ? 25 mv lvds differential output impedance 80 120 ?
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3.0 to +3.6v, t a = -40? to +85?. typical values are at +3.3v and at t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units lvds output current short together or short to gnd 12 ma lvttl input high voltage v ih 2.0 v lvttl input low voltage v il 0.8 v lvttl input current -10 +10 ? lvttl output high voltage v oh i oh = +20? 2.4 v lvttl output low voltage v ol i ol = -1ma 0.4 v note 1: at -40?, dc characteristics are guaranteed by design and characterization. note 2: voltage applied to v ctrl pin is from 0.302v to 2.097v when input threshold is adjusted from +170mv to -170mv. ac electrical characteristics (v cc = +3.0 to +3.6v, t a = -40? to +85?. typical values are at +3.3v and at t a = +25?, unless otherwise noted. the max3882a is guaranteed only at 2.488gbps.) (note 3) parameter symbol conditions min typ max units rateset = 0 (max3882/max3882a) 2.488 serial input data rate rateset = 1 (max3882) 2.667 gbps differential input voltage threshold adjust disabled sdi+, sdi- v id (note 4) figure 1 10 1600 mv p-p differential input voltage slbi+, slbi- 50 800 mv p-p jitter peaking j p f 2mhz 0.1 db jitter transfer bandwidth j bw 1.7 2.0 mhz f = 100khz 3.1 4.1 f = 1mhz 0.62 1.0 sinusoidal jitter tolerance f = 10mhz 0.44 0.6 ui p-p f = 100khz 4.1 f = 1mhz 0.75 sinusoidal jitter tolerance with threshold adjust enabled (note 5) f = 10mhz 0.41 ui p-p jitter generation j gen (note 6) 2.7 ps rms 100khz to 2.5ghz 17 differential input return loss 20log | s 11 | 2.5ghz to 4.0ghz 15 db tolerated consecutive identical digits ber = 10 -10 2000 bits max3882, 0011 pattern 0.6 1.0 max3882, prbs 2 23-1 pattern 0.6 max3882a, 0011 pattern 0.6 acquisition time (note 7) figure 4 max3882a, prbs 2 23-1 pattern 0.62 1.5 ms lol assert time figure 4 2.3 100.0 ?
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (v cc = +3.0 to +3.6v, t a = -40? to +85?. typical values are at +3.3v and at t a = +25?, unless otherwise noted. the max3882a is guaranteed only at 2.488gbps.) (note 3) parameter symbol conditions min typ max units low-frequency cutoff for dc offset cancellation loop caz = 0.1? 4 khz frefset = v cc , rateset = gnd 155 rateset = v cc (max3882 only) 167 frefset = gnd, rateset = gnd 622 reference clock frequency rateset = v cc (max3882 only) 667 mhz reference clock accuracy ?00 ppm vco frequency drift (note 8) 400 ppm rateset = 0 (max3882, max3882a) 622 data output rate rateset = 1 (max3882) 667 mbps rateset = 0 (max3882, max3882a) 622 clock output frequency rateset = 1 (max3882) 667 mhz output clock-to-data delay t ck-q (note 9) -80 +80 ps clock output duty cycle 45 50 55 % clock and data output rise/fall time t r , t f 20% to 80% 100 250 ps lvds differential skew t skew1 any differential pair 50 ps lvds channel-to-channel skew t skew2 pd_ 100 ps note 3: ac characteristics are guaranteed by design and characterization. note 4: jitter tolerance is guaranteed (ber 10 -10 ) within this input voltage range. input threshold adjust is disabled when v ctrl is connected to v cc . note 5: measured with the input amplitude set at 100mv p-p differential swing with a 20mv offset and an input edge speed of 145ps (4th-order bessel filter with f 3db = 1.8ghz). note 6: measured with 10mv p-p oc-48 differential input with prbs 2 23 - 1 and bw = 12khz to 20mhz. note 7: measured at oc-48 data rate using a 0.068? loop-filter capacitor. note 8: under lol condition, the cdr clock output is set by the external reference clock. note 9: relative to the falling edge of pclk+. see figure 3.
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier _______________________________________________________________________________________ 5 500ps/div recovered clock and data (input = 2.488gbps, 2 23 - 1 pattern, v in = 10mv p-p ) 200mv/div max3882 toc01 supply current vs. temperature max3882 toc02 temperature ( c) supply current (ma) 75 50 25 0 -25 170 180 190 200 210 220 230 240 250 260 160 -50 100 jitter tolerance (2.48832gbps, 2 23 - 1 pattern, v in = 16mv p-p with additional 0.15ui deterministic jitter ) max3882 toc03 jitter frequency (hz) jitter tolerance (ui p-p ) 100 1k 1 10 100 0.1 10 10k bellcore mask jitter tolerance vs. input amplitude (2.48832gbps, 2 23 - 1 pattern, with additional 0.15ui deterministic jitter) max3882 toc04 input amplitude (mv p-p ) jitter tolerance (ui p-p ) 1000 100 10 0.1 0.2 0.3 0.4 0.5 0.6 0 1 10,000 jitter frequency = 10mhz jitter transfer max3882 toc05 jitter frequency (khz) transfer (db) 1000 100 10 -35 -30 -25 -20 -15 -10 -5 0 5 -40 1 10,000 bellcore mask 20ps/div parallel clock output jitter max3882 toc06 f clk = 622.08mhz total wideband rms jitter = 2.720ps peak-to-peak jitter = 20.80ps bit-error rate vs. input amplitude max3882 toc07 input voltage (mv p-p ) bit-error ratio 4 3 2 1.00e-10 1.00e-09 1.00e-08 1.00e-07 1.00e-06 1.00e-05 1.00e-04 1.00e-11 15 pullin range (rateset = 0) max3882 toc08 ambient temperature ( c) frequency (ghz) 60 35 10 -15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 2.0 -40 85 t ypical operating characteristics (t a = +25?, unless otherwise noted.)
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (t a = +25?, unless otherwise noted.) jitter tolerance vs. v ctrl (2.67gbps, 2 23 - 1 pattern, v in = 100mv p-p ) max3882 toc09 v ctrl (v) sinusoidal jitter tolerance (ui p-p ) 1.25 1.20 1.15 1.10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 1.05 1.30 input filtered with an 1870mhz filter jitter frequency = 5mhz s11 max3882 toc10 frequency (mhz) db 3500 3000 2500 2000 1500 1000 500 -30 -20 -10 0 10 20 -40 0 4000 pin description pin name function 1, 11, 16, 23 gnd supply ground 2, 5, 31, 32 v cc +3.3v supply voltage 3 sdi+ positive data input. 2.488gbps/2.67gbps serial data stream, cml. 4 sdi- negative data input. 2.488gbps/2.67gbps serial data stream, cml. 6 slbi+ positive system loopback input or positive reference clock input, cml 7 slbi- negative system loopback input or negative reference clock input, cml 8 sis signal input selection, lvttl. low for normal data, high for system loopback. 9 lol loss-of-lock output, lvttl, active low 10 lref ttl control input for pll clock holdover. low for pll lock to reference clock, high for pll lock to input data. 12, 14 v cc _vco supply voltage for the vco 13 fil p ll loop - fi l ter c ap aci tor inp ut. c onnect a 0.068? l oop - fi l ter cap aci tor b etw een fil and v c c _ v c o. 15, 28 v cc _out supply voltage for lvds output buffers 17 pclk- negative clock output, lvds 18 pclk+ positive clock output, lvds 19 pd0- negative data output, lvds 20 pd0+ positive data output, lvds 21 pd1- negative data output, lvds 22 pd1+ positive data output, lvds
detailed description the max3882 deserializer with clock and data recovery and limiting amplifier converts 2.488gbps/2.67gbps serial data to clean 4-bit-wide, 622mbps/667mbps lvds parallel data. the device combines a limiting amplifier with a fully integrated phase-locked loop (pll), data retiming block, 4-bit demultiplexer, clock divider, and lvds output buffer (figure 5). the pll consists of a phase/frequency detector (pfd), loop filter, and voltage- controlled oscillator (vco). the max3882 is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. the max3882a operates at 2.488gbps only. the input signal to the device (sdi) passes through a dc offset control block, which balances the input signal to a zero crossing at 50%. the pll recovers the serial clock from the serial input data stream and produces the properly aligned data and the buffered recovered clock. the frequency of the recovered clock is divided by four and converted to differential lvds parallel out- put pclk. the demultiplexer generates 4-bit-wide 622mbps/667mbps parallel data. input amplifier the sdi inputs of the max3882 accept serial nrz data at 2.488gbps/2.67gbps with 10mv p-p to 1600mv p-p amplitude. the input sensitivity is 10mv p-p , at which the jitter tolerance is met for a ber of 10 -10 when the threshold adjust is not used. the input sensitivity is as low as 4mv p-p for a ber of 10 -10 . the max3882 is designed to directly interface with a transimpedance amplifier (max3277). for applications when vertical threshold adjustment is needed, the max3882 can be connected to the output of an agc amplifier (max3861). here, the input voltage range is 50mv p-p to 600mv p-p . see the design procedure section for decision threshold adjust. phase detector the phase detector in the max3882 produces a volt- age proportional to the phase difference between the incoming data and the internal clock. because of its feedback nature, the pll drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. frequency detector the digital frequency detector (fd) acquires frequency lock without using an external reference clock. the fre- quency difference between the received data and the vco clock is derived by sampling the in-phase and quadrature vco outputs on both edges of the data input signal. depending on the polarity of the frequency difference, the fd drives the vco until the frequency difference is reduced to zero. once frequency acquisi- tion is complete, the fd returns to a neutral state. false locking is eliminated by this digital frequency detector. max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier _______________________________________________________________________________________ 7 pin description (continued) pin name function 24 pd2- negative data output, lvds 25 pd2+ positive data output, lvds 26 pd3- negative data output, lvds, msb 27 pd3+ positive data output, lvds, msb 29 rateset sets the vco frequency. lvttl low for 2.488gbps operation, high for 2.67gbps operation. for max3882a, rateset must always be low. 30 frefset sets reference frequency. lvttl low for 622mhz/667mhz reference, high for 155mhz/167mhz reference. 33 caz+ positive capacitor input for dc offset-cancellation loop. connect a 0.1? capacitor between caz+ and caz-. 34 caz- negative capacitor input for dc offset-cancellation loop. connect a 0.1? capacitor between caz+ and caz-. 35 v ref 2.2v bandgap reference voltage output. optionally used for threshold adjustment. 36 v ctrl analog control input for threshold adjustment. connect to v cc to disable threshold adjust. ep exposed pad ground. the exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance.
max3882/max3882a vco tuning range the max3882 can operate at both oc-48 and oc-48 with fec data rates. select the data frequency using the rateset pin. loop filter and vco the fully integrated pll has a second-order transfer function, with a loop bandwidth (f l ) fixed at.1.7mhz. an external capacitor between v cc_ vco and fil sets the damping of the pll. all jitter specifications are based on the c fil capacitor being 0.068?. note that the pll jitter transfer bandwidth does not change as the exter- nal capacitor changes, but the jitter peaking, acquisi- tion time, and loop stability are affected. for an overdamped system (f z / f l ) < 0.25, the jitter peaking (j p ) of a second-order system can be approxi- mated by: j p = 20log(1 + f z / f l ) the pll zero frequency (f z ) is a function of the external capacitor (cfil) and can be approximated according to: f z = 1 / 2 (650)c fil figures 6 and 7 show the open-loop and closed-loop transfer functions. the pll acquisition time is also directly proportional to the external capacitor c fil . 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 8 _______________________________________________________________________________________ 800mv 5mv v cc v cc - 0.4v v cc + 0.4v v cc - 0.4v v cc - 0.8v v cc (b) dc-coupled single-ended input (a) ac-coupled single-ended input 5mv 800mv figure 1. definition of input voltage swing 0.3 +188 +170 +152 -152 -170 -188 v th (mv) threshold-setting stability (over temperature and power supply) threshold-setting accuracy (part-to-part variation over process) 1.1 1.3 2.1 v ctrl (v) figure 2. relationship between control voltage and threshold voltage t ck-q t ck pclk+ (pd+) - (pd-) figure 3. definition of clock-to-q delay lol output lol assert time acquisition time input data 2.488gbps prbs 2 23 - 1 2.488gbps prbs 2 23 - 1 figure 4. lol assert time and pll acquisition time measurement
loss-of-lock monitor the lol output indicates a pll lock failure, either due to excessive jitter present at data input or due to loss of input data. in the case of loss of input data, the lol indicates a loss-of-signal condition. the lol output is asserted low when the pll loses lock. output lvds interface: pd, pclk the max3882? clock and data outputs are lvds com- patible to minimize power dissipation, speed transition time, and improve noise immunity. these outputs com- ply with the ieee lvds specification. the differential output signal magnitude is 250mv to 400mv. design procedure the max3882 provides a differential output clock (pclk). table 1 shows the pin configuration for choos- ing the type of operation mode. decision threshold adjust decision threshold adjust is available for wdm applica- tions where optical amplifiers are used, generating spontaneous optical noise at data logic high. the deci- sion threshold adjust range is ?70mv. use the provid- ed 2.2v bandgap reference v ref pin or an outside source, such as an output from a dac to control the threshold voltage. the +170mv to -170mv threshold offset can be accomplished by varying the v ctrl volt- age from 0.3v to 2.1v, respectively. see figure 2. when using the v ref to generate voltage for threshold setting, see figure 8. connect v ctrl directly to v cc to disable threshold adjust. dc-offset cancellation loop filter a dc-offset cancellation loop is implemented to remove the dc offset of the limiting amplifier. to minimize the low-frequency pattern-dependent jitter associated with this dc-cancellation loop, the low-frequency cutoff is 10khz typical with caz = 0.1?, connected across caz+ and caz-. applications information clock holdover capability clock holdover is required in some applications where a valid clock needs to be provided to the upstream device in the absence of data transitions. to provide this function, an external reference clock rate of 155mhz/167mhz or 622mhz/667mhz must be applied to the slbi input. control input frefset selects which reference clock rate to use. the control lref selects whether the pll locks to the input data stream (sdi) or the reference clock (slbi). when lref is low, the input is switched to the reference clock input. this lref input can be driven by connecting the lol output pin directly or connecting to any other power monitor signal from the system. system loopback the max3882 is designed to allow system loopback testing. the user can connect the serializer output (max3892) directly to the slbi inputs of the max3882 for system diagnostics. see table 1 for selecting the system loopback operation mode. during system loop- back, lol cannot be connected to lref . interfacing the max3882 to correctly interface with the max3882? cml input and lvds outputs, refer to maxim application note hfan-1.0: interfacing between cml, pecl, and lvds . max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier _______________________________________________________________________________________ 9 table 1. operation modes frefset lref sis rateset operation mode description x1 00 normal operation: pll locked to data input at 2.488gbps x1 01 normal operation: pll locked to data input at 2.67gbps x1 10 system loopback: pll lock frequency at 2.488gbps x1 11 system loopback: pll lock frequency at 2.67gbps 10 x0 clock holdover: pll locked to reference frequency at 155mhz 10 x1 clock holdover: pll locked to reference frequency at 167mhz 00 x0 clock holdover: pll locked to reference frequency at 622mhz 00 x1 clock holdover: pll locked to reference frequency at 667mhz
max3882/max3882a layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled-impedance transmission lines to inter- face with the max3882 high-speed inputs and outputs. power-supply decoupling should be placed as close to the v cc as possible. to reduce feedthrough, isolate input signals from output signals. exposed paddle package the exposed pad, 36-pin qfn incorporates features that provide a very low thermal-resistance path for heat removal from the ic. the pad is electrical ground on the max3882 and should be soldered to the circuit board for proper thermal and electrical performance. 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 10 ______________________________________________________________________________________ d ck q 0 1 4-bit demultiplexer lpf pfd dc offset cancellation vco amp l vds logic bandgap reference v ref caz+ caz- caz pdo+ pdo- l vds pd1+ pd1- l vds pd2+ pd2- l vds pd3+ pd3- l vds pclk+ pclk- sdi+ sdi- v ctrl amp slbi+ slbi- frefset sis v cc fil pll div/4 lol lref rateset max3882 figure 5. functional diagram 1 10 100 1000 h o (j2 f) (db) c fil = 0.068 f f z = 3.6khz f = (khz) c fil = 0.01 f f z = 2.45khz open-loop gain figure 6. open-loop transfer function 1 10 100 1000 h o (j2 f) (db) c fil = 0.068 f f = (khz) c fil = 0.01 f closed-loop gain -3 0 figure 7. closed-loop transfer function
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier ______________________________________________________________________________________ 11 max3882/max3882a max3861 caz+ frefset pd3+ rateset slbi+ slbi- sdi+ sdi- v ctrl v ref r1 + r2 50k ? r2 r1 v cc v cc caz- fil sis +3.3v overhead termination pd1- pd1+ pd2- pd2+ pd3- this symbol represents a transmission line of characteristic impedance z 0 = 50 ? . *required only if overhead circuit does not include internal input termination. 0.068 f 0.1 f 0.1 f 0.1 f 100 ? * 100 ? * 100 ? * pd0- pd0+ 100 ? * pclk- pclk+ 100 ? * -3.3v 155mhz clock agc tia output lol lref +3.3v figure 8. connecting the max3882 with threshold adjust and clock holdover enabled
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 12 ______________________________________________________________________________________ max3882 caz+ frefset pd3+ rateset slbi+ slbi- sdi+ sdi- v ctrl v ref v cc v cc caz- fil sis +3.3v overhead termination pd1- pd1+ pd2- pd2+ pd3- this symbol represents a transmission line of characteristic impedance z 0 = 50 ? . *required only if overhead circuit does not include internal input termination. 0.068 f 0.01 f 0.1 f 0.1 f 0.1 f 100 ? * 100 ? * pd0- pd0+ pclk- pclk+ +3.3v system loopback tia lol lref +3.3v 100 ? * 100 ? * 100 ? * max3277 t ypical application circuits
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier ______________________________________________________________________________________ 13 max3882a caz+ frefset pd3+ rateset slbi+ slbi- sdi+ sdi- v ctrl v ref v cc v cc caz- fil sis +3.3v overhead termination pd1- pd1+ pd2- pd2+ pd3- this symbol represents a transmission line of characteristic impedance z 0 = 50 ? . *required only if overhead circuit does not include internal input termination. 0.068 f 0.01 f 0.1 f 0.1 f 0.1 f 100 ? * 100 ? * pd0- pd0+ pclk- pclk+ +3.3v system loopback tia lol lref +3.3v 100 ? * 100 ? * 100 ? * max3277 t ypical application circuits (continued)
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 14 ______________________________________________________________________________________ 36l,40l, qfn.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier ______________________________________________________________________________________ 15 u package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier 16 ______________________________________________________________________________________ qfn thin.eps e e l l a1 a2 a e/ 2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l f 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8m m l1 l e package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3882/max3882a 2.488gbps/2.67gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. f 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8m m 11. marking is for package orientation reference only. 12. number of leads shown for reference only. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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