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june 2007 i ? 2007 actel corporation see the actel website for the latest version of the datasheet. igloo tm low-power flash fpgas with flash*freeze tm technology features and benefits low power ? 1.2 v or 1.5 v core voltage for low power ? supports single-voltage system operation ? 5 w power consumption in flash*freeze mode ? low-power active fpga operation (from 25 w) ? flash*freeze technology enables ultra-low power consumption while maintaining fpga content ? flash*freeze pin allows easy entry to / exit from ultra- low-power flash*freeze mode high capacity ? 30 k to 1 million system gates ? up to 144 kbits of true dual-port sram ? up to 300 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal (6 copper), flash-based cmos process ? live-at-power-up (lapu) level 0 support ? single-chip solution ? retains programmed design when powered off in-system programming (isp) and security ? secure isp using on-chip 128-bit advanced encryption standard (aes) decryption (except agl030 devices) via jtag (ieee 1532?compliant) ?flashlock ? to secure fpga contents high-performance routing hierarchy ? segmented, hierarchical routing and clock structure ? high-performance, low-skew global network ? architecture supports ultra-high utilization advanced i/o ? 700 mbps ddr, lvds-capable i/os (agl250 and above) ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 4 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5v/1.8v/1.5v,3.3vpci/3.3vpci-x(except agl030), and lvcmos 2.5 v / 5.0 v input ? differential i/o standards: lvpecl, lvds, blvds, and m-lvds (agl250 and above) ? i/o registers on input, output, and enable paths ? hot-swappable and cold sparing i/os (agl030 only) ? programmable output slew rate (except agl030) and drive strength ? weak pull-up/down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the igloo family clock conditioning circuit (ccc) and pll (except agl030) ? six ccc blocks, one with an integrated pll ? configurable phase-shift, multiply/divide, delay capabilities and external feedback, multiply/divide, delay capabilities, an d external feedback ? wide input frequency range (1.5 mhz up to 250 mhz) embedded memory ? 1 kbit of flashrom user-nonvolatile memory ? srams and fifos with vari able-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations available) ? true dual-port sram (except 18) table 1 ? igloo product family igloo devices agl030 agl060 3 agl125 agl250 agl600 agl1000 system gates 30 k 60 k 125 k 250 k 600 k 1 m versatiles (d-flip-flops) 768 1,536 3,072 6,144 13,824 24,576 quiescent curren t (typical) in flash*freeze mode (a) 4 8 14 28 60 102 ram kbits (1,024 bits) ? 18 36 36 108 144 4,608-bit blocks ? 48 8 24 32 flashrom bits 1 k 1 k 1 k 1 k 1 k 1 k secure (aes) isp ? yes yes yes yes yes integrated pll in cccs ? 11 1 1 1 versanet globals 1 6 18 18 18 18 18 i/o banks 2 22 4 4 4 maximum user i/os 81 96 133 143 235 300 package pins cs qfn vqfp fbga qn132 vq100 cs196 qn132 vq100 fg144 cs196 qn132 vq100 fg144 cs196 3 qn132 vq100 fg144 fg144, fg256, fg484 fg144, fg256, fg484 notes: 1. six chip (main) and twelve quadrant global networks are available for agl060 and above. 2. for higher densities and support of additional features, refer to the igloo?e low-power flash fpgas with flash*freeze technology datasheet. 3. device/package support tbd. advanced v0.1 ?
igloo low-power flash fpgas wi th flash*freeze technology ii advanced v0.1 i/os per package 1 packaging tables pinout tables not published in this document will be added in future revi sions of the datasheet . for updates , contact your local actel sales representative. igloo devices agl030 agl060 6 agl125 agl250 2 agl600 agl1000 package dimensions (mm) i/o type single-ended i/o single-ended i/o single-ended i/o single-ended i/o 2 differential i/o pairs single-ended i/o 2 differential i/o pairs single-ended i/o 2 differential i/o pairs vq100 (14 14) 79 71 71 68 13 ? ? ? qn132 (8 8) 81 80 84 87 19 ? ? ? cs196 (8 8) ? 96 133 143 6 30 6 ?? ? fg144 (13 13) ? 96 97 97 24 97 25 97 25 fg256 (17 17) ? ? ? ? ? 177 43 177 44 fg484 (23 23) ? ? ? ? ? 235 60 300 74 notes: 1. when considering migrating your design to a lower- or higher-density device, refer to "package pin assignments" starting on page 4-1 to ensure compliance with design and board migration requirements. 2. each used differential i/o pair reduces the number of single-ended i/os available by two. 3. fg256 and fg484 are footprint-compatible packages. 4. when the flash*freeze pin is us ed to directly enable flash*fr eeze mode and not used as a regul ar i/o, the number of single-en ded user i/os available is reduced by one. 5. "g" indicates rohs-compliant packages. refer to "igloo ordering information" on page iii for the location of the "g" in the part number. 6. device/package support tbd.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 iii igloo ordering information note: *the dc and switching characteri stics for the ?f speed grade targets are based only on simulation. the characteristics provided for the ?f speed grade are subject to change after establishing fpga specifications. some restrict ions might be added and will be reflected in fu ture revisions of this document. the ?f speed grade is only supported in the commerci al temperature range. s pee d g ra d e blank = s tan d ar d f = 20% s lower than s tan d ar d* s upply volta g e 2 = 1.2 v or 1.5 v 5 = 1.5 v a g l1000 v2 f g _ part num b er i g loo devi c e s pa c ka g e type vq = very thin qua d flat pa c k (0.5 mm pit c h) qn = qua d flat pa c k no lea d s (0.5 mm pit c h) 144 i pa c ka g e lea d c ount g lea d -free pa c ka g in g appli c ation (temperature ran g e) blank = c ommer c ial (0 c to +70 c ) i= in d ustrial ( ? 40 c to +85 c ) blank = s tan d ar d pa c ka g in g g = roh s - c ompliant pa c ka g in g pp = pre-pro d u c tion e s =en g ineerin g s ample (room temperature only) 30,000 s ystem g ates a g l030 = 6 0,000 s ystem g ates a g l0 6 0= 125,000 s ystem g ates a g l125 = 250,000 s ystem g ates a g l250 = 6 00,000 s ystem g ates a g l 6 00 = 1,000,000 s ystem g ates a g l1000 = cs = c hip sc ale pa c ka g e (0.5 mm pit c h) f g = fine pit c h ball g ri d array (1.0 mm pit c h)
igloo low-power flash fpgas wi th flash*freeze technology iv advanced v0.1 temperature grade offerings speed grade and temperature grade matrix contact your local actel represen tative for device availability ( http://www.actel.com/c ontact/default.aspx ). package agl030 agl060 3 agl125 agl250 agl600 agl1000 qn132 c, ic, ic, ic, i ? ? vq100 c, i c, i c, i c, i ? ? cs196 ? c, i c, i c, i 3 ?? fg144 ? c, ic, ic, ic, ic, i fg256 ? ? ? ? c, i c, i fg484 ? ? ? ? c, i c, i notes: 1. c = commercial temperature range: 0c to 70c 2. i = industrial temperatur e range: ?40c to 85c 3. device/package support tbd temperature grade ?f 1 std. c 2 ?? i 3 ? ? notes: 1. the characteristics provided for the ?f sp eed grade are subject to change after esta blishing fpga specifications. some restri ctions might be added and will be reflected in future revisions of this document. the ?f speed grade is only supported in the commerci al temperature range. 2. c = commercial temperature range: 0c to 70c 3. i = industrial temperatur e range: ?40c to 85c
advanced v0.1 v table of contents igloo low-power flash fpgas with flash*freeze technology introduction and overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 device architecture introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 flash*freeze technology and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 power conservation techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 dc and switching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87 embedded flashrom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103 package pin assignments 132-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -1 100-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -6 144-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 9 256-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 datasheet information datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 export administration regulations (ear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

igloo low-power flash fpgas with flash*freeze technology advanced v0.1 1-1 introduction and overview general description the igloo family of flash fp gas, based on a 130-nm flash process, offers the lowest power fpga, a single-chip solution, small footprint pa ckages, reprogrammability, and an abundance of advanced features. the flash*freeze technology used in igloo devices enables entering and exitin g an ultra-low-power mode that consumes as little as 5 w while retaining sram and register data. flash*freeze technology simplifies power management through i/o and clock management with rapid recovery to operation mode. the low power active capabilit y (static idle) allows for ultra-low-power consumption (from 25 w) while the igloo device is completely fu nctional in the system. this allows the igloo device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. nonvolatile flash technology gives igloo devices the advantage of being a secure , low power, single-chip solution that is live at power-up (lapu). igloo is reprogrammable and offers time-to-market benefits at an asic-level unit cost. these features enable desi gners to create high-density systems using existing asic or fpga design flows and tools. igloo devices offer 1 kbit of on-chip, reprogrammable, nonvolatile flashrom storage as well as clock conditioning circuitry based on an integrated phase- locked loop (pll). the agl030 device has no pll or ram support. igloo devices ha ve up to 1 million system gates, supported with up to 144 kbits of true dual-port sram and up to 288 user i/os. flash*freeze technology the igloo device offers unique flash*freeze technology, allowing the device to enter and exit ultra- low-power flash*freeze mode. igloo devices do not need additional components to turn off i/os or clocks while retaining the design information, sram content, and registers. flash*freeze te chnology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufact uring or in the field. the ability of igloo v2 devices to support a 1.2 v core voltage allows further reduction in power consumption, thus achieving the lowest total system power. when the igloo device enters flash*freeze mode, the device automatically shuts off the clocks and inputs to the fpga core; when the device exits flash*freeze mode, all activity resumes and data is retained. the availability of low-pow er modes, combined with reprogrammability, a single- chip and single-voltage solution, and availability of small-footprint, high pin- count packages, make igloo devices the best fit for portable electronics. flash advantages low power flash-based igloo devices ex hibit power characteristics similar to those of an asic, making them an ideal choice for power-sensitive applications. igloo devices have only a very limited power-on current surge and no high- current transition period, both of which occur on many fpgas. igloo devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 v core voltage. low dynamic power consumption, combined with low static power consumption and flash*freeze technology, gives the igloo device the lowest total system power offered by any fpga. security the nonvolatile, flash-based igloo devices do not require a boot prom, so there is no vulnerable external bitstream that can be easily copied. igloo devices incorporate flashlock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an fpga with nonvolatile flash programming can offer. igloo devices utilize a 128-bit flash-based lock and a separate aes key to secure programmed intellectual property and configuration data. in addition, all flashrom data in igloo devices can be encrypted prior to loading, using the indus try-leading aes-128 (fips192) bit block cipher encryption standard. the aes standard was adopted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 des standard. igloo devices have a built-in aes decryption engine and a flash-based aes key that make them the most comprehensive programmable logic device security solution available today. igloo devices with aes-based
igloo low-power flash fpgas wi th flash*freeze technology 1-2 advanced v0.1 security allow for secure, remote field updates over public networks such as th e internet, and ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves. the contents of a programmed igloo device cannot be read back, although secure design verification is possible. security, built into the fp ga fabric, is an inherent component of the igloo fa mily. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. the igloo family, with flashlock and aes security, is unique in being highly resistant to both invasive and noninvasive attacks. your valuable ip is protected an d secure, making remote isp possible. an igloo device provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration information in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga structure, and no external configuration data needs to be loaded at system po wer-up (unlike sram-based fpgas). therefore, flash-based igloo fpgas do not require system configuration components such as eeproms or microcontro llers to load device configuration data. this redu ces bill-of-mat erials costs and pcb area, and increas es security and system reliability. live at power-up the actel flash-based igloo devices support level 0 of the lapu classification sta ndard. this feature helps in system component initializat ion, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. the lapu feature of flash- based igloo devices greatly simplifies total system design and reduces total system cost, often eliminating the need for cplds and clock generation plls that are used for these purpos es in a system. in addition, glitches and brownouts in system power will not corrupt the igloo device's flash config uration, and unlike sram- based fpgas, the device will not have to be reloaded when system power is re stored. this enables the reduction or complete removal of the configuration prom, expensive voltage monitor, brownout detection, and clock generator devices from the pcb design. flash- based igloo devices simplify total system design and reduce cost and design ri sk while increasing system reliability and improving sy stem initialization time. igloo flash fpgas allow the user to quickly enter and exit flash*freeze mode. this is done almost instantly (within 1 s) and the device retains configuration and data in registers and ra m. unlike sram-based fpgas the device does not need to reload configuration and design state from external memory components; instead it retains all necessary information to resume operation immediately. reduced cost of ownership advantages to the designer extend beyond low unit cost, performance, and ease of use. unlike sram-based fpgas, flash-based igloo devices allow all functionality to be live at power-up; no external boot prom is required. on-board security mechanisms prevent access to all the programming info rmation and enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. secure isp can be performed using the industry-standard aes algorithm. the igloo family device architecture mitigates the need for asic migration at higher user vo lumes. this makes the igloo family a cost-effective asic replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. refer to the "i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial)" section on page 3-4 for more information. firm errors firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energy of the collision can change the stat e of the conf iguration cell and thus change the logic, ro uting, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the co nsequence of this type of error can be a complete system failure. firm errors do not exist in the configuration memory of igloo flash- based fpgas. once it is programmed, the flash cell configuration element of igloo fpgas cannot be altered by high-energy neutrons and is therefore immune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. advanced flash technology the igloo family offers many benefits, including nonvolatility and reprogr ammability through an advanced flash-based, 130- nm lvcmos process with seven layers of metal. standard cmos design techniques are used to implement logic and control functions. the combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utiliz ation without compromising
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 1-3 device routability or performance. logic functions within the device are interconne cted through a four-level routing hierarchy. igloo family fpgas utilize design and process techniques to minimize power consumption in all modes of operation. advanced architecture the proprietary igloo architec ture provides granularity comparable to standard-ce ll asics. the igloo device consists of five distinct and programmable architectural features ( figure 1-1 and figure 1-2 on page 1-4 ): ? flash*freeze technology ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory 1 ? extensive cccs and plls 1 ? advanced i/o structure the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. the versatilit y of the igloo core tile as either a three-input lookup ta ble (lut) equivalent or as a d-flip-flop/latch wi th enable allows for efficient use of the fpga fabric. the versatile capability is unique to the actel proasic ? family of third-generation architecture flash fpgas. versatiles are co nnected with any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 v) programming of igloo devices via an ieee 1532 jtag interface. 1. the agl030 does not support pll or sram. note: *not supported by agl030 figure 1-1 ? igloo device architecture overview with two i/o banks (agl030, agl060, and agl125) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1
igloo low-power flash fpgas wi th flash*freeze technology 1-4 advanced v0.1 flash*freeze technology the igloo device has an ul tra-low power static mode, called flash*freeze mode, which retains all sram and register information and can still quickly return to normal operation. flash*fr eeze technology enables the user to quickly (within 1 s ) enter and exit flash*freeze mode by activating the flash*freeze pin while all power supplies are kept at their orig inal values. in addition, i/os and global i/os can still be dr iven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, sram information, and stat es. i/o states are tristated during flash*freeze mode or can be set to a certain state using weak pull-up or pull-down i/o attribute configuration. no power is consumed by the i/o banks, clocks, jtag pins, or pll, and the device consumes as little as 5 w in this mode. flash*freeze technology allo ws the user to switch to active mode on demand, thus simplifying the power management of the device. the flash*freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. it is also possible to use the flash*freeze pin as a regular i/o if flash*freeze mode usage is not planned, which is advantageous because of the inherent low power static (as low as 25 w) and dynamic capabilities of the igloo device. refer to figure 1-3 for an illustration of entering/exiting flash*freeze mode. for more information on how to use flash*freeze capability and other low power modes, refer to the "flash*freeze technology and low-power modes" section on page 2-50 . figure 1-2 ? igloo device architecture overview with four i/o banks (agl250, agl600, and agl1000) isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps ram block 4,608-bit dual-port sram or fifo block (agl600 and agl1000) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 figure 1-3 ? igloo flash*freeze mode a c tel i g loo fp g a flash * freeze mo d e c ontrol flash * freeze pin
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 1-5 versatiles the igloo core consists of versatiles, wh ich have been enhanced beyond the proasic plus ? core tiles. the igloo versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-4 for versatile configurations. for more information about versatiles, refer to the "versatile" section on page 2-2 . user nonvolat ile flashrom actel igloo devices have 1 kbit of on-chip, user- accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization an d/or inventory control ? subscription-based business models (for example, set-top boxes) ? secure key storage for secure communications algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written us ing the standard igloo ieee 1532 jtag programming interface. the core can be individually programmed (erased and written), and on- chip aes decryption can be used selectively to securely load data over public ne tworks (except in the agl030 device), as in security keys stored in the flashrom for a user design. the flashrom can be programmed via the jtag programming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the flashrom can only be programmed from the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. a 7-bit address from the fpga core defines which of the 8 banks and which of the 16 bytes within that bank ar e being read. the three most significant bits (msbs) of the flashrom address determine the bank, and the four least significant bits (lsbs) of the flashrom address define the byte. the actel igloo development software solutions, libero ? integrated design environment (ide) and designer, have extensive support for the flashrom. one such feature is auto-g eneration of sequential programming files for applic ations requiring a unique serial number in each part. another feature allows the inclusion of static data for system version control. data for the flashrom can be generated quickly and easily using actel libero ide and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. sram and fifo igloo devices (except the agl030 device) have embedded sram blocks along their north and south sides. each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. the individual blocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram blocks can be initialized via the device jtag port (rom emulation mode) using the ujtag macro (except in the agl030 device). figure 1-4 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
igloo low-power flash fpgas wi th flash*freeze technology 1-6 advanced v0.1 in addition, every sram bl ock has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fifo without using additional core versatiles. the fifo width and depth are programmable. the fifo al so features programmable almost empty (aempty) and almost full (afull) flags in addition to the normal em pty and full flags. the embedded fifo control unit contains the counters necessary for generation of the read and write address pointers. the embedded sr am/fifo blocks can be cascaded to create la rger configurations. pll and ccc igloo devices provide designers with very flexible clock conditioning capabilities. each member of the igloo family contains six cccs. one ccc (center west side) has a pll. the agl030 does not have a pll. the six ccc blocks are located at the four corners and the centers of the east and west sides. all six ccc blocks are usable ; the four corner cccs and the east ccc allow simple clock delay operations as well as clock spine access (refer to the "clock conditioning circuits" section on page 2-14 for more information). the inputs of the six ccc bloc ks are accessible from the fpga core or from one of several inputs located near the ccc that have dedicated connections to the ccc block. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz up to 250 mhz ? output frequency range (f out_ccc ) = 0.75 mhz up to 250 mhz ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50 % 1.5 % or better (for pll only) ? low output jitter: worst case < 2.5 % clock period peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time is 300 s (for pll only) ? exceptional tolerance to input period jitter? allowable input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment between adjacent phases of 40 ps (250 mhz / f out_ccc ) (for pll only) global clocking igloo devices have extensive support for multiple clocking domains. in addition to the ccc and pll support described above, there is a comprehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. i/os with advanced i/o standards the igloo family of fpgas features a flexible i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). igloo fpgas support many different i/o standards?single-ended and differential. the i/os are organized into banks, with two or four banks per device. refer to table 2-22 on page 2-47 for details on i/o bank configurat ion. the configuration of these banks determines the i/o standards supported (see table 2-22 on page 2-47 for more information). each i/o module contains several input, output, and enable registers ( figure 2-24 on page 2-34 ). these registers allow the implemen tation of the following: ? single-data-rate applications ? double-data-rate applications?ddr lvds, blvds, and m-lvds i/os for point-to-point communications see the "ddr module specifications" section on page 3- 71 for more information. igloo banks for the agl250 device and above support lvpecl, lvds, blvds, and m-lvds. blvds and m-lvds can support up to 20 loads.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 1-7 related documents application notes actel igloo?/e flash*freeze? te chnology and low power modes http://www.actel.com/doc uments/igloo_e_lp_an.pdf user?s guides smartgen cores reference guide http://www.actel.com/doc uments/genguide_ug.pdf designer user?s guide http://www.actel.com/doc uments/designer_ug.pdf fusion, igloo/e and proasic3/e macro library guide http://www.actel.com/docum ents/pa3_libguide_ug.pdf

igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-1 device architecture introduction flash technology advanced flash switch unlike sram fpgas, the igloo family uses a live-at- power-up isp flash switch as its programming element. flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate versatile inputs and outputs. in the flash switch, two transistors share the floating gate, which stores the programming information ( figure 2-1 ). one is the sensing transistor, which is only used for writ ing and verification of the floating gate voltage. th e other is the switching transistor. the latter is used to connect or separate routing nets, or to configure versatile logic. it is also used to erase the floating gate. dedicated high- performance lines are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the devi ce core. maximum core utilization is possible for virtually any design. the use of the flash switch technology also remo ves the possibility of firm errors, which are increasin gly common in sram-based fpgas. figure 2-1 ? igloo flash-based switch sensing switching switch in switch out word floating gate
igloo low-power flash fpgas wi th flash*freeze technology 2-2 advanced v0.1 device overview the igloo device family consists of six distinct programmable archit ectural features ( figure 2-2 and figure 2-3 on page 2-3 ): ? fpga fabric/core (versatiles) ? routing and clock resources (versanets) ? flashrom ? dedicated sram/fifo memory (except agl030) ? advanced i/o structure ? flash*freeze technology and low-power modes core architecture versatile the proprietary igloo fam ily architecture provides granularity comparable to ga te arrays. the igloo device core consists of a sea-of -versatiles architecture. as illustrated in figure 2-4 on page 2-4 , there are four inputs in a logic versatile cell, and each versatile can be configured using the ap propriate flash switch connections: ? any 3-input logic function ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set (on a fourth input) versatiles can flexibly map the logic and sequential gates of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. versatiles and larger functi ons can be connected with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-flop, set/clr is supported by a fourth input. the set/clr signal can only be routed to this fourth input over the versanet (global) network. however, if in the user?s design the set/clr signal is not routed over the versanet network, a compile warning message will be given, and the intended logic function will be implemented by two versatiles instead of one. the output of the versatile is f2 ( figure 2-4 on page 2-4 ) when the connection is to th e ultra-fast local lines, or yl when the connection is to the efficient long-line or very- long-line resources. note: *not supported by agl030 figure 2-2 ? igloo device architecture overview with two i/o banks (agl030, agl060, and agl125) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-3 figure 2-3 ? igloo device architecture overview with four i/o banks (agl250, agl600, and agl1000) isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps ram block 4,608-bit dual-port sram or fifo block (agl600 and agl1000) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
igloo low-power flash fpgas wi th flash*freeze technology 2-4 advanced v0.1 note: *this input can only be connected to the global clock distribution network. figure 2-4 ? igloo core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc * f2 yl
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-5 array coordinates during many place-and-rout e operations in the actel designer software tool, it is possible to set constraints that require array coordinates. table 2-1 provides array coordinates of core cells an d memory blocks. the array coordinates are measured from the lower left (0, 0). they can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and i/os. i/o and cell coordinates ar e used for placement constraints. two coordinate systems are needed because there is not a one-to-one correspondence between i/o cells and core cells. in addi tion, the i/o coordinate system changes depending on the die/package combination. it is not listed in table 2-1 . the designer chipplanner tool provides the array coordinates of all i/o locations. i/o and cell coordinates are used for placement constraints. however, i/o placement is easier by package pin assignment. figure 2-5 illustrates the array coordinates of an device. for more information on how to use array coordinates for region/placement constraints, see the designer user's guide or online help (available in the software) for igloo software tools. table 2-1 ? igloo array coordinates device versatiles memory rows all min. max. bottom top min. max. x y x y (x, y) (x, y) (x, y) (x, y) agl030???????? agl060 3 2 66 25 none (3, 26) (0, 0) (69, 29) agl125 3 2 130 25 none (3, 26) (0, 0) (133, 29) agl250 3 2 130 49 none (3, 50) (0, 0) (133, 53) agl600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) agl1000 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103) note: the vertical i/o tile coordi nates are not shown. west side c oordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east sid e coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. figure 2-5 ? array coordinates for agl600 top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (169, 1) to (192, 1) i/o tile memory blocks memory blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile (core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) (0, 79) (197, 1)
igloo low-power flash fpgas wi th flash*freeze technology 2-6 advanced v0.1 routing architecture routing resources the routing structure of igloo devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources; efficient long-line resources; high-speed, very-long-line resources; and the high-perfo rmance versanet networks. the ultra-fast local resources are dedicated lines that allow the output of each versatile to connect directly to every input of the eight surrounding versatiles ( figure 2-6 ). the exception to this is that th e set/clr input of a versatile configured as a d-flip-flop is driven only by the versatile global network. the efficient long-line resour ces provide routing for longer distances and higher-fanout co nnections. these resources vary in length (spanning one, two, or four versatiles), run both vertically and horizontally, and cover the entire igloo device ( figure 2-7 on page 2-7 ). each versatile can drive signals onto the efficien t long-line resources, which can access every input of every versatile. routing software automatically inserts active buffers to limit loading effects. the high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: le ngth +/?12 versatiles in the vertical direction and length +/?16 in the horizontal direction from a given core versatile ( figure 2-8 on page 2-8 ). very long lines in igloo devices have been enhanced over those in prev ious proasic families. this provides a significant performance boost for long-reach signals. the high-performance versan et global networks are low-skew, high-fanout nets that are accessible from external pins or internal logic ( figure 2-9 on page 2-10 ). these nets are typically used to distribute clocks, resets, and other high-fanout nets requiring minimum skew. the versanet networks are implemented as clock trees, and signals can be introduced at any junction. these can be employed hierarchically, with signals accessing every input on all versatiles. note: input to the core cell for the d-flip-flop set and reset is only available via the versanet global network connection. figure 2-6 ? ultra-fast local lines connected to the eight n earest neighbors l l l l l l inputs output ultra-fast local lines (connects a versatile to the adjacent versatile, i/o buffer, or memory block) l ll long lines
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-7 figure 2-7 ? efficient long-line resources l l llll l lllll l l llll l l llll l l llll spans 1 versatile spans 2 versatiles spans 4 versatiles spans 1 versatile spans 2 versatiles spans 4 versatiles versatile
igloo low-power flash fpgas wi th flash*freeze technology 2-8 advanced v0.1 figure 2-8 ? very-long-line resources high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring pad ring 1612 block of versatiles sram
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-9 clock resources (versanets) igloo devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has up to six cccs. the west ccc also contains a phase-locked loop (pll) core, delay lines, a phase shifter (0, 90, 180, 270), and cloc k multipliers/dividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the versanet global network. the east and west cccs each have access to three versanet global lines on each side of the chip (six total lines). the cccs at the four corners each have access to three quadrant global lin es in each quadrant of the chip (except agl030). advantages of the versanet approach one of the architectural bene fits of igloo is the set of powerful and low-delay versanet global networks. igloo offers six chip (main) global networks that are distributed from the center of the fpga array ( figure 2-9 on page 2-10 ). in addition, igloo devices have three regional globals in each of the four chip quadrants. each core versatile has access to nine global network resources: three quadrant and six chip (main) global networks, and a total of 18 globals on the device. each of these networks contains spines and ribs that reach all the versatiles in the quadrants ( figure 2-10 on page 2-11 ). this flexible versanet global network architecture allows users to map up to 144 different internal/external clocks in a igloo device. details on the versanet networks are given in table 2-2 on page 2-11 . the flexible use of the igloo versanet global network allows the designer to address several design requirements. user applications that are clock-resource-i ntensive can easily route external or gated internal clocks using versanet global routing networks. designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the versanet global network. in agl030 devices, all six versanets are driven from three southern i/os, located toward the east and west sides. each of these tiles can be configured to select a central i/o on its respective side or an internal routed signal as the input signal. the agl030 does not support any clock conditioning circuitry, nor does it contain the versanet global network concept of top and bottom spines. versanet global networks and spine access the igloo architecture contai ns a total of 18 segmented global networks that can access the versatiles, sram, and i/o tiles of the igloo device. there are nine global network resources in each device quadrant: three quadrant globals and six chip (main) global networks. each device has a total of 18 globals. these versanet global networks offer fast, low-skew routing resources for high-fanout nets, including clock signals. in addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 144internal/external clocks (in an agl1000 device) or other high-fanout nets in igloo devices. optimal usage of these low-sk ew networks can result in significant improvement in design performance on igloo devices. the nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, wh ich has three spines, and the chip (main) global network, which has six spines. note that there are three quadrant spines in each quadrant of the device (except for agl030). there are four quadrant global network regions per device ( figure 2-10 on page 2-11 ). the spines are the vertical branches of the global network tree, shown in figure 2-11 on page 2-12 . each spine in a vertical column of a chip (main) global network is further divided into two equal-length spine segments: one in the top and one in the bottom half of the die. each spine and its associated ribs cover a certain area of the igloo device (the "s cope" of the spine; see figure 2-9 on page 2-10 ). each spine is accessed by the dedicated global network mux tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or by another net defined by the user ( figure 2-12 on page 2-13 ). quadrant spines can be driven from user i/os on the north and south sides of the die. the ability to drive spines in the quadrant global networks can have a significant effect on system performance for high- fanout inputs to a design. details of the chip (main) gl obal network spine-selection mux are presented in figure 2-12 on page 2-13 . the spine drivers for each spine are located in the middle of the die. quadrant spines are driven from a north or south rib. access to the top and bottom ribs is from the corner ccc or from the i/os on the no rth and south sides of the device.
igloo low-power flash fpgas wi th flash*freeze technology 2-10 advanced v0.1 note: not applicable to the agl030 device. figure 2-9 ? overview of igloo versanet global network quadrant global pads top spine bottom spine pad ring pad ring pad ring i/o ring i/o ring chip (main) global pads spine-selection tree mux global pads high-performance versanet global network main (chip) global network global spine global ribs
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-11 note: not applicable to the agl030 device. figure 2-10 ? global network architecture table 2-2 ? igloo globals/spines/rows by device agl030 agl060 agl125 agl250 agl600 agl1000 global versanets (trees)* 6 9 9 9 9 9 versanet spines/tree 4 4 4 8 12 16 total spines 24 36 36 72 108 144 versatiles in each top or bottom spine 384 384 384 768 1,152 1,536 total versatiles 768 1,536 3,072 6,144 13,824 24,576 rows in each top or bottom spine ? 12 12 24 36 48 note: *there are six chip (main) globals and three gl obals per quadrant (except in the agl030 device). northwest quadrant global network southeast quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc
igloo low-power flash fpgas wi th flash*freeze technology 2-12 advanced v0.1 figure 2-11 ? igloo spines in a global clock tree network pa d rin g pa d rin g pa d rin g i/o rin g i/orin g c hip (main) g lo b al pa d s g lo b al pa d s hi g h-performan c e g lo b al network g lo b al s pine g lo b al ri b s sc ope of s pine (sha d e d area plus lo c al rams an d i/os) s pine- s ele c tion mux em b e dd e d ram blo c ks lo g i c tiles top s pine bottom s pine t1 b1 t2 b2 t3 b3 qua d rant g lo b al pa d s
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-13 clock aggregation clock aggregation allows fo r multi-spine clock domains. a mux tree provides the nece ssary flexibility to allow long lines or i/os to access do mains of one, two, or four global spines. signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allo wing i/os to feed directly into the clock system. as figure 2-13 indicates, this access system is contiguous. there is no break in the middl e of the chip for the north and south i/o versanet access. this is different from the quadrant clocks located in these ribs, which only reach the middle of the rib. figure 2-12 ? spine selection mu x of global tree figure 2-13 ? clock aggregation tree architecture internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux
igloo low-power flash fpgas wi th flash*freeze technology 2-14 advanced v0.1 clock conditioning circuits overview of clock conditioning circuitry in igloo devices, the cccs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. the cccs are available in si x chip locations?each of the four chip corners and the middle of the east and west chip sides. each ccc can implement up to three independent global buffers (with or without programmable delay) or a pll function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximum of three global outputs for a given ccc. a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb , or clkc-glc) of a given ccc. a pll macro uses the clka ccc input to drive its reference clock. it uses the gla and, optionally, the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) global output cannot be reused if the yb (or yc) output is used ( figure 2-14 on page 2-15 ). refer to the "pll macro" section on page 2-16 for more information. each global buffer, as well as the pll reference clock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ?the fpga core the ccc block is fully conf igurable, either via flash configuration bits set in the programming bitstream or through an asynchronous in terface. this asynchronous interface is dynamically access ible from inside the igloo device to permit parameter changes (such as divide ratios) during device operation. to increase the versatility and flexibility of the clock conditioning system, the ccc configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. this latter mode allows the user to dynamically reconfigure the ccc without the need for core programming. the shift register is accessed through a simple serial interface. refer to the "ccc electrical specifications" section on page 2-19 for more information. global buffers with no programmable delays the clkbuf and clkbuf_lvpecl/lvds/blvds/m-lvds macros are composite macros that include an i/o macro driving a global buffer, which uses a hardwired connection. the clkbuf, clkbuf_lvpecl/lvds/blvds/m-lvds, and clkint macros are pass-through clock sources and do not use the pll or provide any programmable delay functionality. the clkint macro provides a global buffer function driven by the fpga core. many specific clkbuf macros support the wide variety of single-ended and differential i/o standards supported by igloo devices. the available clkbuf macros are described in the fusion, igloo/e and proasic3/e macro library guide . global buffer with programmable delay the clkdly macro is a pass-through clock source that does not use the pll, but prov ides the ability to delay the clock input using a programmable delay. the clkdly macro takes the selected cl ock input and adds a user- defined delay element. this macro generates an output clock phase shift from the input clock. the clkdly macro can be driven by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. many specific inbuf macros support the wide variety of single-ended and differential i/o standards supported by the igloo family. the available inbuf macros are described in the fusion, igloo/e and proasic3/e macro library guide . the clkdly macro can be driven directly from the fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga regular routing fabric. in this case, users must instantiate a special macro, pllint, to differentiate from the hardwired i/o connection described earlier. the visual clkdly configurat ion in the smartgen part of the libero ide and designer tools allows the user to select the desired amount of delay and configures the delay elements appropriately. smartgen also allows the user to select the input clock source. smartgen will automatically instantiate the special macro, pllint, when needed.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-15 notes: 1. visit the actel website for future applic ation notes concerning dynamic pll reconfiguration. the pll is only supported on the west center ccc. the agl030 has no pll support. refer to the "pll macro" section on page 2-16 for signal descriptions. 2. refer to the fusion, igloo/e and proasic3/e macro library guide for more information. 3. many standard-specific inbuf macros (for example, inbuf_lvds) support the wide va riety of single-ended and differential i/o standards supported by the igloo family. the available inbuf macros are described in the fusion, igloo/e and proasic3/e macro library guide . figure 2-14 ? igloo ccc options oadiv[4:0]* oamux[2:0]* dlygla[4:0]* obdiv[4:0]* obmux[2:0]* dlyyb[4:0]* dlyglb[4:0]* ocdiv[4:0]* ocmux[2:0]* dlyyc[4:0]* dlyglc[4:0]* findiv[6:0]* fbdiv[6:0]* fbdly[4:0]* fbsel[1:0]* xdlysel* vcosel[2:0]* clka extfb gla lock glb yb glc yc powerdown clkdly macro clk gl dlygl[4:0] clkbuf_lvds/lvpecl macro padn padp padn padp y y y a pad y pad y clkint macro clkbuf macro input lvds/lvpecl macro pll macro inbuf* macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) gla or glb or glc clock source clock conditioning output for inbuf* driving a pll macro or clkdly macro, the i/o will be hard-routed to the ccc, i.e. will be placed by software to a dedicate global i/o.
igloo low-power flash fpgas wi th flash*freeze technology 2-16 advanced v0.1 pll macro 1 the pll functionality of the clock conditioning block is supported by the pll macro. note that the pll macro reference clock uses the clka input of the ccc block, which is only accessible from the global a[0:2] package pins. refer to figure 2-15 on page 2-17 for more information. the pll macro provides five derived clocks (three independent) from a single reference clock. the pll macro also provides power-down input and lock output signals. see figure 2-17 on page 2-18 for more information. inputs: ? clka: selected clock input ? powerdown (active low): disables plls. the default state is powerdown on (active low). ? extfb: allows an external signal to be compared to a reference clock in the pll core's phase detector outputs: ? lock: indicates that pll output has locked on the input reference signal ? gla, glb, glc: outputs to respective global networks ? yb, yc: allows output from the ccc to be routed back to the fpga core as previously described, the p ll allows up to five flexible and independently configurable clock outputs. figure 2-20 on page 2-21 illustrates the various clock output options and delay elements. as illustrated, the pll suppo rts three dist inct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b and c global network access, respectively, and/or routed to the device core (yb and yc). there are five delay elements to support phase control on all five outputs (gla, glb, glc, yb, and yc). there is also a delay elemen t in the feedback loop that can be used to advance the clock relative to the reference clock. the pll macro reference clock can be driven by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. the pll macro reference clock can be driven directly from the fpga core. the pll macro reference clock can also be driven from an i/o that is routed throug h the fpga regular routing fabric. in this case, users mu st instantiate a special macro, pllint, to differentiate from the hardwired i/o connection described earlier. during power-up, the pll outputs will toggle around the maximum frequency of the vco gear selected. toggle frequencies can range from 40 mhz to 250 mhz. this will continue as long as the clock input (clka) is constant (high or low). this can be prevented by low assertion of the powerdown signal. the visual pll configuration in smartgen, part of the libero ide and designer tool s, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. smartgen also allows the user to select the various delays and phase shift values nece ssary to adjust the phases between the reference clock (clka) and the derived clocks (gla, glb, glc, yb, an d yc). smartgen also allows the user to select the i nput clock source. smartgen automatically instantiates the special macro, pllint, when needed. 1. the agl030 device has no ccc, and thus does not include a pll.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-17 notes: 1. represents the global input pins. globals have direct access to the clock conditioning block and are not routed via the fpga fabric. refer to the "user i/o naming convention" section on page 2-56 for more information. 2. instantiate the routed clock source input as follows: a) connect the output of a logic element to the clock input of a pll, clkdly, or clkint macro. b) do not place a clock source i/o (inbuf or inbuf_lvpec l/lvds/blvds/m-lvds/ddr) in a relevant global pin location. 3. lvds-, blvds-, and m-lvds?based clock sources are only ava ilable on agl250 through agl1000 devices. agl030, agl060, and agl125 support single-ended clock sources only. the agl030 device does not contain a pll. figure 2-15 ? clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint note: the agl030 device does not support this feature. figure 2-16 ? clkbuf and clkint + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2 clkbuf clkint clkbuf_lvds/lvpecl padn padp y pad y y a
igloo low-power flash fpgas wi th flash*freeze technology 2-18 advanced v0.1 table 2-3 ? available igloo i/o standards within clkbuf and clkbuf_lvds/lvpecl macros clkbuf macros clkbuf_lvcmos5 clkbuf_lvcmos33 1 clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_lvds 2 clkbuf_lvpecl notes: 1. by default, the clkbuf ma cro uses the 3.3 v lvttl i/o technology. for more details, refer to the fusion, igloo/e and proasic3/e macro library guide . 2. blvds and m-lvds standards are supported by clkbuf_lvds. note: *visit the actel website for future application notes concerning the dynamic pll. the agl030 device does not contain a pll. figure 2-17 ? ccc/pll macro note: the clkdly macro uses progra mmable delay element type 2. figure 2-18 ? clkdly oadiv[4:0]* oamux[2:0]* dlygla[4:0]* obdiv[4:0]* obmux[2:0]* dlyyb[4:0]* dlyglb[4:0]* ocdiv[4:0]* ocmux[2:0]* dlyyc[4:0]* dlyglc[4:0]* findiv[6:0]* fbdiv[6:0]* fbdly[4:0]* fbsel[1:0]* xdlysel* vcosel[2:0]* clka extfb gla lock glb yb glc yc powerdown clkdly clk gl dlygl[4:0]
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-19 ccc electrical specifications timing characteristics table 2-4 ? igloo ccc/pll specification for igloo v2 or v5 devices, 1.5 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 250 mhz clock conditioning circuitry output frequency f out_ccc 0.75 250 mhz delay increments in programmable delay blocks 1, 2 330 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 1.00 1.20 % 24 mhz to 100 mhz 1.75 2.00 % 100 mhz to 250 mhz 2.50 5.60 % acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 0.97 11.3 ns delay range in block: programmable delay 2 1, 2 0.025 11.3 ns delay range in block: fixed delay 1, 2 3 ns notes: 1. this delay is a function of voltage and temperature. see table 3-6 on page 3-6 for deratings. 2. t j = 25c, v cc = 1.5 v 3. the agl030 device does not support pll. 4. tracking jitter is defined as the variation in clock edge pos ition of pll outputs with refere nce to pll input clock edge. tra cking jitter does not measure the variation in pll output peri od, which is covered by period jitter parameter.
igloo low-power flash fpgas wi th flash*freeze technology 2-20 advanced v0.1 table 2-5 ? igloo ccc/pll specification for igloo v2 devices, 1.2 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 200 mhz clock conditioning circuitry output frequency f out_ccc 0.75 200 mhz delay increments in programmable delay blocks 1, 2 530 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 1.00 1.20 % 24 mhz to 100 mhz 1.75 2.00 % 100 mhz to 250 mhz 2.50 5.60 % acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 1.74 18.2 ns delay range in block: programmable delay 2 1, 2 0.025 18.2 ns delay range in block: fixed delay 1, 2 4.5 ns notes: 1. this delay is a function of voltage and temperature. see table 3-7 on page 3-6 for deratings. 2. t j = 25c, v cc = 1.2 v 3. the agl030 device does not support pll. 4. tracking jitter is defined as the variation in clock edge posi tion of pll outputs with reference to pll input clock edge. tra cking jitter does not measure the variation in pll output peri od, which is covered by period jitter parameter. note: peak-to-peak jitter measurements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-19 ? peak-to-peak jitter definition t perio d _max t perio d _min output s i g nal
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-21 ccc physical implementation 2 the ccc is composed of the following ( figure 2-20 ): ? pll core ? 3 phase selectors ? 6 programmable delays and 1 fixed delay that advances/delays phase ? 5 programmable frequency dividers that provide frequency multiplication/division (not shown in figure 2-20 because they are automatically configured based on the user's required frequencies) ? 1 dynamic shift register that provides ccc dynamic reconfiguration capability ccc programming the ccc block is fully configur able, either via static flash configuration bits in the array, set by the user in the programming bitstream, or through an asynchronous dedicated shift register dynamically accessible from inside the igloo device. the dedicated shift register permits changes in parameters such as pll divide ratios and delays during device op eration. this latter mode allows the user to dynami cally reconfigure the pll without the need for core programming. the register file is accessed through a simple serial interface. 2. the agl030 device does not contain a pll. notes: 1. refer to the "clock conditioning circuits" section on page 2-14 and table 2-4 on page 2-19 and table 2-5 on page 2-20 for signal descriptions. 2. clock divider and clock multiplier blocks are not shown in this figure or in smartgen. they are automatically configured base d on the user's required frequencies. figure 2-20 ? igloo pll block pll core phase select phase select phase select gla clka glb yb glc yc fixed delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 four-phase output extfb
igloo low-power flash fpgas wi th flash*freeze technology 2-22 advanced v0.1 nonvolatile memory (nvm) overview of user nonvolatile flashrom igloo devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the fpga core fabric. the flashrom is arranged in 8 banks of 128 bits during programming. the 128 bits in each bank are addressable as 16 bytes during the read back of the flashrom from the fpga core ( figure 2-21 ). the flashrom can only be programmed via the ieee 1532 jtag port. it cannot be programmed directly from the fpga core. when programming, each of the eight 128-bit banks can be select ively reprogrammed. the flashrom can only be reprogrammed on a bank boundary. programming involves an automatic, on-chip bank erase prior to reprogramming the bank. the flashrom supports synchrono us read. the address is latched on the rising edge of the clock, and the new output data is stable after the falling edge of the same clock cycle. refer to figure 3-43 on page 3-102 for the timing diagram . the flashrom can be read on byte boundaries. the upper three bits of the flashrom address from the fpga core define the bank being accessed. the lower four bits of the flashrom address from the fpga core define which of the 16 bytes in the bank is being accessed. figure 2-21 ? flashrom architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-23 sram and fifo 3 igloo devices (agl250, agl600, and agl1000) have embedded sram blocks along their north and south sides; agl060 and agl125 devices have embedded sram blocks on the north side only. the agl030 does not include sram or fifo. to meet the needs of high- performance designs, the memory blocks operate strictly in synchronous mode for both read and write operations. the read and wr ite clocks are completely independent, and each may operate at any desired frequency up to 250 mhz. ? 4k1, 2k2, 1k4, 5129 (dual-port ram?2 read, 2 write or 1 read, 1 write) ? 5129, 25618 (2-port ram?1 read and 1 write) ? sync write, sync pipelined / nonpipelined read the igloo memory block includes dedicated fifo control logic to generate internal addresses and external flag logic (full, empty, afull, aempty). block diagrams of the memory modules are illustrated in figure 2-22 on page 2-24 . simultaneous dual-port read /write and write/write operations at the same addr ess are allowed when certain timing requirements are met. during ram operation, addr esses are sourced by the user logic and the fifo controller is ignored. in fifo mode, the internal addresses are generated by the fifo controller and routed to the ram array by internal muxes. refer to figure 2-23 on page 2-25 for more information about the implementation of the embedded fifo controller. the igloo architecture enable s the read and write sizes of rams to be organized independently, allowing for bus conversion. for example, the write side size can be set to 25618 and the read size to 5129. both the write width and read width for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. the different dw configurations are: 25618, 5129, 1k4, 2k2, and 4k1. refer to the allowable rw and ww values supported for each of the ram macro types in table 2-6 on page 2-26 . when widths of one, two, or four are selected, the ninth bit is unused. for example, when writing nine-bit values and reading four-bit values, on ly the first four bits and the second four bits of each nine-bit value are addressable for read operat ions. the ninth bit is not accessible. conversely, when writing fo ur-bit values and reading nine-bit values, the ninth bi t of a read operation will be undefined. the ram blocks employ little-endian byte order for read and write operations. 3. the agl030 device does not support sram or fifo.
igloo low-power flash fpgas wi th flash*freeze technology 2-24 advanced v0.1 note: the agl030 device does not support sram or fifo. figure 2-22 ? supported basic ram macros fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-25 note: the agl030 device does not support sram or fifo. figure 2-23 ? igloo ram block with embedded fifo controller c nt 12 e = e = c nt 12 afval aeval s ub 12 r c lk wd w c lk reset rblk ren e s top wblk wen f s top rd[17:0] wd[17:0] r c lk w c lk radd[ j :0] wadd[ j :0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram
igloo low-power flash fpgas wi th flash*freeze technology 2-26 advanced v0.1 signal descript ions for ram4k9 4 the following signals are us ed to configure the ram4k9 memory element: widtha and widthb these signals enable the ram to be configured in one of four allowable aspect ratios ( table 2-6 ). blka and blkb these signals are active low and will enable the respective ports when assert ed. when a blkx signal is deasserted, that port?s outp uts hold the previous value. wena and wenb these signals switch the ra m between read and write modes for the respective ports. a low on these signals indicates a write operation, and a high indicates a read. clka and clkb these are the clock signals fo r the synchronous read and write operations. these can be driven independently or with the same driver. pipea and pipeb these signals are used to sp ecify pipelined read on the output. a low on pipea or pipeb indicates a nonpipelined read , and the data appears on the corresponding output in the same clock cycle. a high indicates a pipelined read , and data appears on the corresponding output in the next clock cycle. wmodea and wmodeb these signals are used to co nfigure the behavior of the output when the ram is in write mode. a low on these signals makes the output reta in data from the previous read. a high indicates pass-through behavior, wherein the data being written will appear immediately on the output. this signal is overridden when the ram is being read. reset this active low signal resets the control logic, forces the output hold state registers to zero, disables reads and writes from the sram block, and clears the data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are disabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. refer to the tables beginning with table 3-147 on page 3-93 for the specifications. addra and addrb these are used as r ead or write addresses, and they are 12 bits wide. when a depth of less than 4 k is specified, the unused high-order bits must be grounded ( table 2-7 ). dina and dinb these are the input data signals, and they are nine bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused high-order signals must be grounded ( table 2-8 ). douta and doutb these are the nine-bit output data signals. not all nine bits are valid in all config urations. as with dina and dinb, high-order bits may not be used ( table 2-8 ). the output data on unused pins is undefined. 4. the agl030 device does not support sram or fifo. table 2-6 ? allowable aspect ratio settings for widtha[1:0] widtha[1:0] widthb[1:0] dw 00 00 4k1 01 01 2k2 10 10 1k4 11 11 5129 note: the aspect ratio settings are constant and cannot be changed on the fly. table 2-7 ? address pins unused /used for various supported bus widths dw addrx unused used 4k1 none [11:0] 2k2 [11] [10:0] 1k4 [11:10] [9:0] 5129 [11:9] [8:0] note: the "x" in addrx implies a or b. table 2-8 ? unused/used input and output data pins for various supported bus widths dw dinx/doutx unused used 4k1 [8:1] [0] 2k2 [8:2] [1:0] 1k4 [8:4] [3:0] 5129 none [8:0] note: the "x" in dinx or doutx implies a or b.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-27 signal descripti ons for ram512x18 5 ram512x18 has slightly different behavior than ram4k9, as it has dedicated read and write ports. ww and rw these signals enable the ram to be configured in one of the two allowable aspect ratios ( table 2-9 ). wd and rd these are the input and output data signals, and they are 18 bits wide. when a 5129 aspect ratio is used for write, wd[17:9] are unused and must be grounded. if this aspect ratio is used for read, rd[17:9] are undefined. waddr and raddr these are read and write ad dresses, and they are nine bits wide. when the 25618 aspe ct ratio is used for write or read, waddr[8] or raddr[8 ] are unused and must be grounded. wclk and rclk these signals are the write a nd read clocks, respectively. they can be clocked on the rising or falling edge of wclk and rclk. wen and ren these signals are the write and read enables, respectively. they are both active low by default. these signals can be configured as active high. reset this active low signal resets the control logic, forces the output hold state registers to zero, disables reads and writes from the sram bloc k, and clears the data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are disabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and writ e clocks. refer to the tables beginning with table 3-148 on page 3-94 for the specifications. pipe this signal is used to sp ecify pipelined read on the output. a low on pipe indicates a nonpipelined read, and the data appears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. clocking the dual-port sram blocks are only clocked on the rising edge. smartgen allows fallin g-edge-triggered clocks by adding inverters to the netlis t, hence achieving dual-port sram blocks that are clocked on either edge (rising or falling). for dual-port sram, each port can be clocked on either edge and/or by separate clocks by port. igloo devices support in version (bubble pushing) throughout the fpga architecture, including the clock input to the sram modules. inversions added to the sram clock pin on the design schematic or in the hdl code will be automatically accounted for during design compile without incurring additional delay in the clock path. the two-port sram can be clocked on the rising or falling edge of wclk and rclk. if negative-edge ram and fifo clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automati cally used within the igloo development tools, without performance penalty. modes of operation there are two read mode s and one write mode: ? read nonpipelined (synchronous?1 clock edge): in the standard read mode, new data is driven onto the rd bus in the same clock cycle following ra and ren valid. the read address is registered on the read port clock active edge, and data appears at rd after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchro nous?2 clock edges): the pipelined mode incurs an additional clock delay from address to data bu t enables operation at a much higher frequency. the read address is registered on the read po rt active clock edge, and the read data is registered and appears at rd after the second read clock edge. setting pipe to on enables this mode. ? write (synchronous?1 clock edge): on the write clock active edge, the write data is written into the sram at the write ad dress when wen is high. the setup times of the write address, write enables, and write data are minimal with respect to the write clock. writ e and read transfers are described with timing requirements in the "ddr module specifications" section on page 3-71 . 5. the agl030 device does not support sram or fifo. table 2-9 ? aspect ratio settings for ww[1:0] ww[1:0] rw[1:0] dw 01 01 5129 10 10 25618 00, 11 00, 11 reserved
igloo low-power flash fpgas wi th flash*freeze technology 2-28 advanced v0.1 ram initialization each sram block can be indi vidually initialized on power- up by means of the jtag port using the ujtag mechanism (refer to the "jtag 1532" section on page 2-63 ). the shift register for a target block can be selected and loaded with the proper bit confi guration to enable serial loading. the 4,608 bits of data can be loaded in a single operation. signal descripti ons for fifo4k18 6 the following signals are used to configure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( table 2-10 ). wblk and rblk these signals are active low and will enable the respective ports when low. when the rblk signal is high, that port?s outputs hold the previous value. wen and ren read and write enables. wen is active low and ren is active high by default. these signals can be configured as active high or low. wclk and rclk these are the clock signals fo r the synchronous read and write operations. these can be driven independently or with the same driver. rpipe this signal is used to sp ecify pipelined read on the output. a low on rpipe indicates a nonpipelined read, and the data appears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. reset this active low signal resets the control logic and forces the output hold state registers to zero when asserted. it does not reset the contents of the memory array ( table 2-11 ). while the reset signal is active, read and write operations are disabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. refer to the tables beginning with table 3-151 on page 3-100 for the specifications. wd this is the input data bus an d is 18 bits wide. not all 18 bits are valid in all configurations. when a data width less than 18 is specified, unused higher-order signals must be grounded ( table 2-11 ). rd this is the output data bus a nd is 18 bits wide. not all 18 bits are valid in all configurat ions. like the wd bus, high- order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( table 2-11 ). estop, fstop estop is used to stop the fifo read counter from further counting once the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. fstop is used to stop the fifo write counter from further counting once the fifo is full (i.e., the full flag goes high). a high on this signal inhibits the counting. for more information on these signals, refer to the "estop and fstop usage" section on page 2-29 . full, empty when the fifo is full and no more data can be written, the full flag asserts high. the full flag is synchronous to wclk to inhibit writing immediately upon detection of a full condition and to prevent overflows. since the write address is compared to a resynchronized (and thus time-delayed) version of the read address, the full flag will remain asserted until tw o wclk active edges after a read operation eliminat es the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immediately upon detection of an empty condition and to prevent 6. the agl030 device does not support sram or fifo. table 2-10 ? aspect ratio setti ngs for ww[2:0] ww[2:0] rw[2:0] dw 000 000 4k1 001 001 2k2 010 010 1k4 011 011 5129 100 100 25618 101, 110, 111 101, 110, 111 reserved table 2-11 ? input data signal usage for different aspect ratios dw wd/rd unused 4k1 wd[17:1], rd[17:1] 2k2 wd[17:2], rd[17:2] 1k4 wd[17:4], rd[17:4] 5129 wd[17:9], rd[17:9] 25618 ?
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-29 underflows. since the read address is compared to a resynchronized (and thus time-delayed) version of the write address, the empty flag will remain asserted until two rclk active edges afte r a write operation removes the empty condition. for more information on these signals, refer to the "fifo flag usage consid erations" section . afull, aempty these are programmable flags and will be asserted on the threshold specified by afval and aeval, respectively. when the number of words stored in the fifo reaches the amount specified by aeval while reading, the aempty output will go high. likewise, when the number of words stored in the fifo reaches the amount specified by afval while writing, the afull output will go high. afval, aeval the aeval and afval pins are used to specify the almost-empty and almost-full threshold values. they are 12-bit signals. for more information on these signals, refer to the "fifo flag usage cons iderations" section . estop and fstop usage the estop pin is used to stop the read counter from counting any further once the fifo is empty (i.e., the empty flag goes high). likewise, the fstop pin is used to stop the write counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the ig loo device start the count at zero, reach the maximum depth for the configuration (e.g., 511 for a 5129 configurat ion), and then restart at zero. an example application for estop, where the read counter keeps counting, woul d be writing to the fifo once and reading the same content over and over without doing another write. fifo flag usage considerations the aeval and afval pins are used to specify the 12-bit aempty and afull threshold values. the fifo contains separate 12-bit write addr ess (waddr) and read address (raddr) counters. waddr is incremented every time a write operation is performed, and raddr is incremented every time a read operation is performed. whenever the difference between waddr and raddr is greater than or equal to afval, the afull output is asserted. likewise, whenever the diff erence between waddr and raddr is less than or equal to aeval, the aempty output is asserted. to hand le different read and write aspect ratios, afval and aeval are expressed in terms of total data bits instead of total data words. when users specify afval and aeval in terms of read or write words, the smartgen tool translates them into bit addresses and configures th ese signals automatically. smartgen configures the afu ll flag to assert when the write address exceeds the read address by at least a predefined value. in a 2k8 fifo, for example, a value of 1,500 for afval means that the afull flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). it will stay asserted until the diff erence between the write and read addresses drops below 1,500. the aempty flag is asse rted when the difference between the write address an d the read address is less than a predefined value. in the example above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the difference between the write address and the read addr ess to drop to 200. it will stay asserted until that diff erence rises above 200. note that the fifo can be configur ed with different read and write widths; in this case, the afval setting is based on the number of write data entr ies, and the aeval setting is based on the number of r ead data entries. for aspect ratios of 5129 and 25618, only 4,096 bits can be addressed by the 12 bits of afval and aeval. the number of words must be multiplied by 8 and 16 instead of 9 and 18. the smartgen t ool automatically uses the proper values. to avoid halfwords being written or read, which could happen if diff erent read and write aspect ratios were specified, the fifo will assert full or empty as soon as at least one word cannot be written or read. for example, if a two-bit wo rd is written and a four-bit word is being read, the fifo will remain in the empty state when the first word is written. this occurs even if the fifo is not completely empty, because in this case, a complete word cannot be read . the same is applicable in the full state. if a four-bit word is written and a two-bit word is read, the fifo is full and one word is read. the full flag will remain asserted because a complete word cannot be written at this point.
igloo low-power flash fpgas wi th flash*freeze technology 2-30 advanced v0.1 advanced i/os introduction igloo devices feature a flexible i/o structure, supporting a range of mixed voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v) through a bank-selectable voltage. table 2-12 , table 2-13 , and table 2-22 on page 2-47 show the voltages and the compatible i/o standards. i/os provide programmable slew rates (except agl030 ), drive strengths, and weak pull-up and pull-down circuits. 3.3 v pci and 3.3 v pci-x are 5 v?tolerant. see the "5 v input tolerance" section on page 2-40 for possible implementations of 5 v tolerance. all i/os are in a known state during power-up, and any power-up sequence is allowed without current impact. refer to the "i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial)" section on page 3-4 for more information. during power-up, before reaching activation levels, the i/o input and output buffers are disabled while the weak pull-up is enabled. activation levels are described in table 3-2 on page 3-2 . i/o tile the igloo i/o tile provides a flexible, programmable structure for implementi ng a large number of i/o standards. in addition, the registers available in the i/o tile in selected i/o banks ca n be used to support high- performance register inputs and outputs, with register enable if desired ( figure 2-24 on page 2-34 ). the registers can also be used to support the jesd-79c double data rate (ddr) standard within the i/o structure (see the "double data rate (ddr) support" section on page 2-35 for more information). as depicted in figure 2-24 on page 2-34 , all i/o registers share one clr port. the output register and output enable register share on e clk port. refer to the "i/o registers" section on page 2-34 for more information. i/o banks and i/o st andards compatibility i/os are grouped into i/o voltage banks. there are four i/o banks on the agl250 thr ough agl1000. th e agl030, agl060, and agl125 have two i/o banks. each i/o voltage bank has dedicated i/o supply and ground voltages (vmv/gndq for input buffers and v cci /gnd for output buffers). because of these dedicated supplies, only i/os with compatible standards can be assigned to the same i/o voltage bank. table 2-13 shows the required voltage compatibility values for each of these voltages. for more information about i/o and global assignments to i/o banks in a device, refer to the specific pin table for the device in the "package pin assignments" section on page 4-1 and the "user i/o naming convention" section on page 2-56 . i/o standards are comp atible if their v cci and vmv values are identical. vmv and gndq are "quiet" input power supply pins and are not used on agl030. in the agl030 device, all input s and disabled outputs are voltage tolerant up to 3.3 v. table 2-12 ? igloo supported i/o standards agl030 agl060 agl125 agl250 agl600 agl1000 single-ended lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v ?????? 3.3 v pci/pci-x ? ????? differential lvpecl, lvds, blvds, m-lvds ? ? ? ??? table 2-13 ? v cci voltages and compat ible igloo standards v cci and vmv (typical) compatible standards 3.3 v lvttl/lvcmos 3.3, pci 3.3, pci-x 3.3 lvpecl 2.5 v lvcmos 2.5, lvcmos 2.5/5.0, lvds, blvds, m-lvds 1.8 v lvcmos 1.8 1.5 v lvcmos 1.5
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-31 i/o banks igloo i/os are divided into multiple technology banks. the igloo family has two to four banks, and the number of banks is device-dependent. agl030, agl060, and agl125 support two i/o banks, whereas agl600 and agl1000 su pport four i/o banks. the bank types have different characteristics, such as drive strength, the i/o standards supported, and timing and power differences. there are three types of banks in the igloo family: advanced i/o banks, standard+ i/o banks, and standard i/o banks. advanced i/o banks offer single-ended and differential capabilities. these banks are available on the east and west sides of agl250, agl600, and agl1000 devices. standard+ i/o banks offer lv ttl/lvcmos and pci single- ended i/o standards. these banks are available on the north and south sides of agl250, agl600, and agl1000, and on all sides of agl125 and agl060. standard i/o banks offer lvttl/lvcmos single-ended i/o standards. these banks are available on all sides of agl030 devices. table 2-14 shows the i/o bank types, devices and bank locations supported, drive strength, slew rate control, and supported standards. table 2-14 ? igloo bank types definition and differences i/o bank type device and bank location drive strength slew rate control i/o standards supported lvttl/ lvcmos pci/pci-x lvpecl, lvds, blvds, m-lvds standard agl030 (all banks) refer to ta b l e 2 - 2 4 on page 2-48 . yes ? not supported not supported standard+ agl060 and agl125 (all banks) refer to ta b l e 2 - 2 5 on page 2-49 . yes ?? not supported north and south banks of agl250 to agl1000 devices refer to ta b l e 2 - 2 5 on page 2-49 . yes ?? not supported advanced east and west banks of agl250 to agl1000 devices refer to ta b l e 2 - 2 6 on page 2-49 . yes ?? ?
igloo low-power flash fpgas wi th flash*freeze technology 2-32 advanced v0.1 features supported on every i/o table 2-15 lists all features supported by transmitter/receiver for si ngle-ended and differential i/os. table 2-15 ? igloo i/o features feature description single-ended transmitter features ? hot insertion: agl030: hot insertion in every mode all other igloo devices: no hot insertion ? weak pull-up and pull-down ? 2 slew rates (except agl030) ? skew between output buffer enab le/disable time: 2 ns delay on rising edge and 0 ns delay on falling edge (see "selectable skew between output buffer enable and disable times" on page 2-45 for more information) ? 3 drive strengths ? 5 v?tolerant receiver ( "5 v output tolerance" section on page 2-44 ) ? lvttl/lvcmos 3.3 v outputs co mpatible with 5 v ttl inputs ( "5 v output tolerance" section on page 2-44 ) ? high performance ( ta b l e 2 - 1 6 ) single-ended receiver features ? elec trostatic discharge (esd) protection ? high performance ( ta b l e 2 - 1 6 ) ? separate ground plane for gndq pin and power plane for vmv pin are used for input buffer to reduce output-induced noise. differential receiver features (agl250 through agl1000) ? esd protection ? high performance ( ta b l e 2 - 1 6 ) ? separate ground plane for gndq pin and power plane for vmv pin are used for input buffer to reduce output-induced noise. cmos-style lvds, blvds, m-lvds, or lvpec l transmitter ? two i/os and external resistors are used to provide a cmos- style lvds, ddr lvds, blvds, and m-lvds/lvpecl transmitter solution. ? weak pull-up and pull-down ? high slew rate table 2-16 ? maximum i/o frequency for single-ended and differential i/os in all bank s in igloo devices (maximum drive strength and high slew selected) specification performance up to lvttl/lvcmos 3.3 v 200 mhz lvcmos 2.5 v 250 mhz lvcmos 1.8 v 200 mhz lvcmos 1.5 v 130 mhz pci 200 mhz pci-x 200 mhz lvds 350 mhz lvpecl 350 mhz
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-33 table 2-17 ? igloo maximum i/o frequency for si ngle-ended and differential i/os in all bank types (maximum drive strength and high slew selected )?for igloo v2 or v5 devices, 1.5 v dc core supply voltage specification performance up to lvttl/lvcmos 3.3 v 180 mhz lvcmos 2.5 v 230 mhz lvcmos 1.8 v 180 mhz lvcmos 1.5 v 120 mhz pci 180 mhz pci-x 180 mhz lvds 300 mhz lvpecl 300 mhz table 2-18 ? igloo maximum i/o frequency for si ngle-ended and differential i/os in all bank types (maximum drive strength and high slew selected)?for ig loo v2, 1.2 v dc core supply voltage specification performance up to lvttl/lvcmos 3.3 v tbd lvcmos 2.5 v tbd lvcmos 1.8 v tbd lvcmos 1.5 v tbd pci tbd pci-x tbd lvds tbd lvpecl tbd
igloo low-power flash fpgas wi th flash*freeze technology 2-34 advanced v0.1 i/o registers each i/o module contains seve ral input, output, and enable registers. refer to figure 2-24 for a simplified representation of the i/o block. the number of input registers is selected by a set of switches (not shown in figure 2-24 ) between registers to implement single-ended or differential data transmission to and from the fpga core. the designer software sets these switches for the user. a common clr/pre signal is employed by all i/o registers wh en i/o register combining is used. input register 2 does not have a clr/pre pin, as this regi ster is used for ddr implementation. note: igloo i/os have registers to s upport ddr functionality (see the "double data rate (ddr) support" section on page 2-35 for more information). figure 2-24 ? i/o block logical representation input register e = enable pin a y pad 1 2 3 4 5 6 oce ice ice input register input register clr/pre clr/pre clr/pre clr/pre clr/pre pull-up/down resistor control signal drive strength and slew-rate control output register output register to fpga core from fpga core output enable register oce i/o / clr or i/o / pre / oce i/o / q0 i/o / q1 i/o / iclk i/o / d0 i/o / d1 / ice i/o / oclk i/o / oe
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-35 double data rate (ddr) support igloo devices support 350 mhz ddr inputs and outputs. in ddr mode, new data is pr esent on every transition of the clock signal. clock and data lines have identical bandwidths and signal integrity requirements, making them very efficient for implementing very high-speed systems. high-speed ddr interfaces can be implemented using lvds. the ddr feature is pr imarily implemented in the fpga core periphery and is not limited to any i/o standard. input support for ddr the basic structure to support a ddr input is shown in figure 2-25 . three input registers are used to capture incoming data, which is pres ented to the core on each rising edge of the i/o register clock. each i/o tile on igloo devi ces supports ddr inputs. output support for ddr the basic ddr output structure is shown in figure 2-26 on page 2-36 . new data is presented to the output every half clock cycle. note: ddr macros and i/o registers do not require additional routing. the combiner automatically recognizes the ddr macro and pushes its registers to the i/o register area at the edge of the chip. the routing delay from the i/o registers to the i/o buffers is already taken into account in the ddr macro. figure 2-25 ? ddr input register support in igloo devices input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in x x x x x x e a b c d out_qr (to core)
igloo low-power flash fpgas wi th flash*freeze technology 2-36 advanced v0.1 hot-swap support hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in a powered-up system. the levels of ho t-swap support and examples of rela ted applications are described in table 2-19 on page 2-37 . the i/os also need to be configured in hot insertion mode if hot plugging compliance is required. the agl030 device has an i/o structure that allows the support of level 3 and level 4 hot-swap with on ly two levels of staging. figure 2-26 ? ddr output support in igloo devices data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x x a b d e c c b outbuf data_r (from core)
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-37 table 2-19 ? levels of hot-swap support hot- swapping level description power applied to device bus state card ground connection device circuitry connected to bus pins example of application with cards containing igloo devices compliance of igloo devices 1 cold-swap no ? ? ? system and card with actel fpga chip are powered down and the card is plugged into the system. then the power supplies are turned on for the system but not for the fpga on the card. agl030: compliant other igloo devices: compliant if the bus switch is used to isolate fpga i/os from the rest of the system. 2 hot-swap while reset yes held in reset state must be made and maintained for 1 ms before, during, and after insertion/ removal ? in the pci hot-plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. agl030: compliant i/os can but do not have to be set to hot insertion mode. other igloo devices: compliant 3 hot-swap while bus idle yes held idle (no ongoing i/o processes during insertion/ removal) same as level 2 must remain glitch-free during power-up or power-down board bus shared with card bus is "frozen," and there is no toggling activity on the bus. it is critical that the logic states set on the bus signal are not disturbed during card insertion/removal. agl030: compliant with 2 levels of staging (first: gnd, second: all other pins) other igloo devices: compliant: option 1 ? 2 levels of staging (f irst: gnd, second: all other pins) together with bus switch on the i/os option 2 ? 3 levels of staging (f irst: gnd, second: supplies, third: all other pins) 4 hot-swap on an active bus yes bus may have active i/o processes ongoing, but device being inserted or removed must be idle. same as level 2 same as level 3 there is activity on the system bus, and it is critical that the logic states set on the bus signal are not disturbed during card insertion/removal. agl030: compliant with 2 levels of staging (first: gnd, second: all other pins) other igloo devices: compliant: option 1 ? 2 levels of staging (f irst: gnd, second: all other pins) together with bus switch on the i/os option 2 ? 3 levels of staging (f irst: gnd, second: supplies, third: all other pins)
igloo low-power flash fpgas wi th flash*freeze technology 2-38 advanced v0.1 for boards and cards with three levels of staging, card power supplies must have time to reach their final values before the i/os are connected. pay attention to the sizing of power supply decoupling capacitors on the card to ensure that the power supp lies are not overloaded with capacitance. cards with three levels of staging should have the following sequence: ? grounds ?powers ? i/os and other pins for level 3 and level 4 compliance with the agl030 device, cards with two levels of staging should have the following sequence: ? grounds ? powers, i/os, and other pins cold-sparing support cold-sparing means that a subsystem with no power applied (usually a circuit boar d) is electrically connected to the system that is in op eration. this means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system. the agl030 device fully supports cold-sparing, since the i/o clamp diode is always off (see table 2-14 on page 2-31 ). for other igloo devices, si nce the i/o clamp diode is always active, cold-sparing can be accomplished either by employing a bus switch to isol ate the device i/os from the rest of the system or by drivi ng each igloo i/o pin to 0 v. if the agl030 is used in ap plications requiring cold- sparing, a discharge path from the power supply to ground should be provided. this can be done with a discharge resistor or a switched resistor. this is necessary because the agl030 does not have built-in i/o clamp diodes. if the resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitance is in parallel with the resistor). the rc time constant should ensure full discharge of supplies before cold- sparing functionality is requir ed. the resistor is necessary to ensure that the power pi ns are discharged to ground every time there is an in terruption of power to the device. i/o cold-sparing may add additional current if a pin is configured with either a pu ll-up or pull-down resistor and driven in the opposite direction. a small static current is induced on each i/o pin when the pin is driven to a voltage opposite to the weak pull resistor. the current is equal to the volt age drop across the input pin divided by the pull resistor. refer to table 3-38 on page 3-27 for the specific pull resistor value for the corresponding i/o standard. for example, assuming an lvttl 3.3 v input pin is configured with a weak pull- up resistor, a current will flow through the pull-up resistor if the input pin is driven low. for lvttl 3.3 v, the pull-up resistor is ~45 k , and the resulting current is equal to 3.3v/45k = 73 a for the i/o pin. this is true also when a weak pull-down is ch osen and the input pin is driven high. this current can be avoided by driving the input low when a weak pull-do wn resistor is used and driving it high when a weak pull-up resistor is used. this current draw can occur in the following cases: ? in active and static modes: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers wi th pull-up, driven low ? bidirectional buffers with pull-down, driven high ? output buffers with pull-up, driven low ? output buffers with pull-down, driven high ? tristate buffers with pull-up, driven low ? tristate buffers with pull-down, driven high ? in flash*freeze mode: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers wi th pull-up, driven low ? bidirectional buffers with pull-down, driven high electrostatic discha rge (esd) protection igloo devices are tested per jedec standard jesd22- a114-b. igloo devices contain clamp diodes at every i/o, global, and power pad. clamp diodes protect all device pads against damage from esd as well as from excessive voltage transients. each i/o has two clamp diodes. one diode has its positive (p) side connected to the pad and its negative (n) side connected to v cci . the second diode has its p side connected to gnd and i ts n side conn ected to the pad. during operation, these diodes are normally biased in the off state, except when transient voltage is significantly above v cci or below gnd levels. in agl030, the first diode is always off. in other igloo devices, the clamp diode is always on and cannot be switched off. by selecting the appropriate i/o configuratio n, the diode is turned on or off. refer to table 2-20 on page 2-39 for more information about the i/o standards and the clamp diode. the second diode is always connected to the pad, regardless of the i/o configuration selected.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-39 table 2-20 ? i/o hot-swap and 5 v input toleranc e capabilities in igloo devices i/o assignment clamp diode 1 hot insertion 5 v input tolerance 2 input buffer output buffer agl030 other igloo devices agl030 other igloo devices 3 agl030 other igloo devices 3.3 v lvttl/lvcmos no yes yes yes yes 2 yes 2 enabled/disabled 3.3 v pci, 3.3 v pci-x n/a yes n/a yes n/a yes 2 enabled/disabled lvcmos 2.5 v 5 no yes yes yes yes 2 yes 4 enabled/disabled lvcmos 2.5 v / 5.0 v 6 n/a yes n/a yes n/a yes 4 enabled/disabled lvcmos 1.8 v no yes yes yes no no enabled/disabled lvcmos 1.5 v no yes yes yes no no enabled/disabled differential, lvds/ blvds/m-lvds/ lvpecl n/a yes n/a yes n/a no enabled/disabled notes: 1. the clamp diode is always off for the agl030 device and always active for other igloo devices. 2. can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor. 3. refer to table 2-19 on page 2-37 for device-compliant information. 4. can be implemented with an external resistor and an internal clamp diode. 5. the lvcmos 2.5 v i/o standard is supported by the agl030 device only. in the smartgen core reference guide , select the lvcmos25 macro for lvcmos 2.5 v i/o st andard support for the agl030 device. 6. the lvcmos 2.5 v / 5.0 v i/o standard is supported by all igloo devices except agl030. in the smartgen core reference guide , select the lvcmos5 macro for lvcmos 2.5 v / 5.0 v i/o standard support for all igloo devices except agl030.
igloo low-power flash fpgas wi th flash*freeze technology 2-40 advanced v0.1 5 v input tolerance i/os can support 5 v input tolerance when lvttl 3.3 v, lvcmos 3.3 v, lvcmos 2.5 v, and lvcmos 2.5 v / 5.0 v configurations are used (see table 2-20 on page 2-39 for more details). there are four recommended solutions for achieving 5 v receiver tolerance (see figure 2-27 to figure 2-30 on page 2-43 for details of board and macro setups). all the solutions m eet a common requirement of limiting the voltage at the input to 3.6 v or less. in fact, the i/o absolute maximum volt age rating is 3.6 v, and any voltage above 3.6 v may cause long-term gate oxide failures. solution 1 the board-level design must ensure that the reflected waveform at the pad does no t exceed the limits provided in table 3-2 on page 3-2 . this is a requirement to ensure long-term reliability. this scheme will also work for a 3.3 v pci/ pci-x configuration, but the internal diode should not be used for clamping, and the voltage mu st be limited by the two external resistors as explained below. relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. here are some examples of possible resistor values (based on a simplified simulation model with no line effects and 10 transmitter output resistance, where rtx_out_high = (v cci ? v oh ) / i oh , rtx_out_low = v ol / i ol ). example 1 (high speed , high current): rtx_out_high = rtx_out_low = 10 r1 = 36 (5%), p(r1)min = 0.069 r2 = 82 (5%), p(r2)min = 0.158 imax_tx = 5.5 v / (82 0.95 + 36 0.95 + 10) = 45.04 ma t rise = t fall = 0.85 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise = t fall = 4 ns at c_pad_load = 50 pf (includes up to 25% safety margin) example 2 (low?medium sp eed, medium current): rtx_out_high = rtx_out_low = 10 r1 = 220 (5%), p(r1)min = 0.018 r2 = 390 (5%), p(r2)min = 0.032 imax_tx = 5.5 v / (220 0.95 + 390 0.95 + 10) = 9.17 ma t rise = t fall = 4 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise = t fall = 20 ns at c_pad_load = 50 pf (includes up to 25% safety margin) other values of resistors are also allowed as long as the resistors are sized appropriat ely to limit the voltage at the receiving end to 2.5 v < vin (rx) < 3.6 v when the transmitter sends a logic 1. th is range of vin_dc (rx) must be assured for any combination of transmitter supply (5 v 0.5 v), transmitter output resistance, and board resistor tolerances. temporary overshoots ar e allowed according to table 3-4 on page 3-3 . figure 2-27 ? igloo solution 1 solution 1 5.5 v 3.3 v requires two board resistors, lvcmos 3.3 v i/os igloo i/o input rext1 rext2
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-41 solution 2 the board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in table 3-4 on page 3-3 . this is a requirement to ensure long-term reliability. this scheme will also work for a 3.3 v pc i/pci-x configuration, but the internal diode should not be used for clamping, and the voltage must be limit ed by the external resistors and zener, as shown in figure 2-28 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 2-28 ? igloo solution 2 solution 2 5.5 v 3.3 v requires one board resistor, one zener 3.3 v diode, lvcmos 3.3 v i/os igloo i/o input rext1 zener 3.3v
igloo low-power flash fpgas wi th flash*freeze technology 2-42 advanced v0.1 solution 3 the board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in table 3-4 on page 3-3 . this is a requirement to ensure long-term reliability. this scheme will also work for a 3.3 v pc i/pci-x configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in figure 2-29 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 2-29 ? igloo solution 3 solution 3 requires a bus switch on the board, lvttl 3.3 v i/os. igloo i/o input 3.3 v 5.5 v 5.5 v bus switch idtqs32x23
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-43 solution 4 figure 2-30 ? igloo solution 4 table 2-21 ? comparison table for 5 v?compliant receiver scheme scheme board components speed current limitations 1 two resistors low to high 1 limited by transmitter's drive strength 2 resistor and zener 3.3 v medium limit ed by transmitter's drive strength 3 bus switch high n/a 4 minimum resistor value 2, 3, 4, 5 ? r = 47 at t j = 70c ? r = 150 at t j = 85c ? r = 420 at t j = 100c medium maximum diode current at 100% duty cycle, signal constantly at '1' ? 52.7 ma at t j = 70c / 10-year lifetime ? 16.5 ma at t j = 85c / 10-year lifetime ? 5.9 ma at t j = 100c / 10-year lifetime for duty cycles other than 100%, the currents can be increased by a factor of 1 / (duty cycle). example: 20% duty cycle at 70c maximum current = (1 / 0.2) 52.7 ma = 5 52.7 ma = 263.5 ma notes: 1. speed and current consumption increase as the board resistance values decrease. 2. resistor values ensure i/o diode long-term reliability. 3. at 70c, customers could still use 420 on every i/o. 4. at 85c, a 5 v solution on every other i/o is permitted, since the resistance is lower (150 ) and the current is higher. also, the designer can still use 420 and use the solution on every i/o. 5. at 100c, the 5 v solution on every i/o is permitted, since 420 are used to limit the current to 5.9 ma. solution 4 2.5 v 5.5 v 2.5 v requires one board resistor. available for lvcmos 2.5 v / 5.0 v. igloo i/o input rext on-chip clamp diode
igloo low-power flash fpgas wi th flash*freeze technology 2-44 advanced v0.1 5 v output tolerance igloo i/os must be set to 3.3 v lvttl or 3.3 v lvcmos mode to reliably drive 5 v ttl re ceivers. it is also critical that there be no external i/o pull-up resistor to 5 v, since this resistor would pull th e i/o pad voltage beyond the 3.6 v absolute maximum value and consequently cause damage to the i/o. when set to 3.3 v lvttl or 3.3 v lvcmos mode, igloo i/os can directly drive signals into 5 v ttl receivers. in fact, v ol =0.4v and v oh = 2.4 v in both 3.3 v lvttl and 3.3 v lvcmos modes exceeds the v il =0.8v and v ih = 2 v level requirements of 5 v ttl receivers. therefore, level 1 and level 0 will be recognized correctly by 5 v ttl receivers. simultaneous switching outputs (ssos) and printed circuit board layout ssos can cause signal integrity problems on adjacent signals that are not part of the sso bus. both inductive and capacitive coupling parasitics of bond wires inside packages and of tr aces on pcbs will transfer noise from sso busses onto signals adjacent to those busses. additionally, ssos can produce ground bounce noise and v cci dip noise. these two noise types are caused by rapidly changing currents through gnd and v cci package pin inductances during switching activities ( eq 2-1 and eq 2-2 ). ground bounce noise voltage = l(gnd) di/dt eq 2-1 v cci dip noise voltage = l(v cci ) di/dt eq 2-2 any group of four or more input pins switching on the same clock edge is considered an sso bus. the shielding should be done both on the board and inside the package unless otherwise described. in-package shielding can be ac hieved in several ways; the required shielding will vary depending on whether pins next to the sso bus are lvttl/lvcmos inputs, lvttl/lvcmos outputs, or gtl/sstl/hstl/lvds/lvpecl inputs and outputs. board traces in the vicinity of the sso bus have to be adequately shielded from mutual coupling and inductive noise that can be generated by the sso bus. also, noise generated by the sso bus needs to be reduced inside the package. pcbs perform an important function in feeding stable supply voltages to the ic and, at the same time, maintaining signal integrity between devices. key issues that need to considered are as follows: ? power and ground plane design and decoupling network design ? transmission line reflections and terminations
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-45 selectable skew between output buffer enable and disable times the configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time. figure 2-31 ? block diagram of output enable path figure 2-32 ? timing diagram (o ption 1: bypasses skew circuit) figure 2-33 ? timing diagram (o ption 2: enables skew circuit) enable (out) skew circuit output enable (from fpga core) i/o output buffers enable (in) mux skew select enable (in) enable (out) less than 0.1 ns less than 0.1 ns enable (in) enable (out) 1.2 ns (typical) less than 0.1 ns
igloo low-power flash fpgas wi th flash*freeze technology 2-46 advanced v0.1 at the system level, the skew circuit ca n be used in applications where transmission activities on bidirectional data lines need to be coordinated. this circuit, when selected , provides a timing margin th at can prevent bus contention and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. figure 2-34 presents an example of the skew circuit implem entation in a bidirectional communication system. figure 2-35 shows how bus contention is created, and figure 2-36 on page 2-47 shows how it can be avoided with the skew circuit. figure 2-34 ? example of implementation of skew circuits in bi directional transmission sy stems using igloo devices figure 2-35 ? timing diagram (bypasses skew circuit) transmitter 1: igloo i/o transmitter 2: generic i/o enable(t2) en (b1) en (b2) routing delay (t1) routing delay (t2) en (r1) enable (t1) skew or bypass skew bidirectional data bus transmitter enable/ disable en (b1) en (b2) enable (r1) transmitter 1: on enable (t2) transmitter 2: on enable (t1) bus contention transmitter 1: off transmitter 1: off transmitter 2: off
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-47 i/o software support in the igloo development software, default settings have been defined for the vari ous i/o standards supported. changes can be made to the default settin gs via the use of attributes; however, not all i/o attributes are applicable for all i/o standards. table 2-22 lists the valid i/o attributes that can be manipulated by the user for each i/o standard. single-ended i/o standards in igloo devices su pport up to five different drive strengths. figure 2-36 ? timing diagram (with skew circuit selected) en (b1) en (b2) transmitter 1: on enable (t2) transmitter 2: on transmitter 2: off enable (t1) result: no bus contention transmitter 1: off transmitter 1: off table 2-22 ? igloo i/o attributes vs. i/o standard applications i/o standard slew (output only) out_drive (output only) skew (all macros with oe)* res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v ????? ? lvcmos 2.5 v ????? ? lvcmos 2.5/5.0 v ????? ? lvcmos 1.8 v ????? ? lvcmos 1.5 v ????? ? pci (3.3 v) ??? pci-x (3.3 v) ???? lvds, blvds, m-lvds ?? lvpecl ? note: *applies to all igloo devices except agl030.
igloo low-power flash fpgas wi th flash*freeze technology 2-48 advanced v0.1 table 2-23 lists the default values for the above selectable i/o at tributes as well as those th at are preset for that i/o standard. see table 2-24 for slew and out_drive settings. weak pull-up and weak pull-down resistors igloo devices support optio nal weak pull-up and pull- down resistors on each i/o pin. when the i/o is pulled up, it is connected to the v cci of its corresponding i/o bank. when it is pulled down, it is connected to gnd. refer to table 3-38 on page 3-27 for more information. configuration of th e pull-up or pull-down of the i/o can be used to set the i/o to a certain state while the device is in flash*freeze mode. refer to the "flash*freeze technology and low-power modes" section on page 2- 50 for more information. the flash*freeze (ff) pin cannot be configured with a weak pull-down or pull-up i/o attribute as the signal needs to be driven at all times. slew rate control and drive strength igloo devices support output slew rate control: high and low. actel recommends the high slew rate option to minimize the propagation delay. this high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. selecting a low slew rate reduces this kind of noise but adds some delays in the system. low slew rate is recommended when bus transients are expected. driv e strength should also be selected according to the design requirements and noise immunity of the system. the output slew rate an d multiple drive strength controls are available in lvttl/lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 2.5 v / 5.0 v input, lvcmos 1.8 v, and lvcmos 1.5 v. all other i/o standards have a high output slew rate by default. for agl030, refer to table 2-24 ; for other igloo devices, refer to table 2-25 and table 2-26 for more information about the slew rate and dr ive strength specification. table 2-23 ? igloo i/o default attributes i/o standards slew (output only) out_drive (output only) skew (tribuf and bibuf only) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v see table 2-24 . see table 2-24 . off none 35 pf ? lvcmos 2.5 v off none 35 pf ? lvcmos 2.5/5.0 v off none 35 pf ? lvcmos 1.8 v off none 35 pf ? lvcmos 1.5 v off none 35 pf ? pci (3.3 v) off none 10 pf ? pci-x (3.3 v) off none 10 pf ? lvds, blvds, m-lvds off none 0 pf ? lvpecl off none 0 pf ? table 2-24 ? igloo output drive (out_drive) for st andard i/o bank type (agl030 device) i/o standards out_drive (ma) slew 2468 lvttl/lvcmos 3.3 v ???? high low lvcmos 2.5 v ???? high low lvcmos 1.8 v ?? ??highlow lvcmos 1.5 v ? ???highlow note: refer to table 2-14 on page 2-31 for i/o bank type definition.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-49 table 2-25 ? igloo output drive for standard+ i/o bank type i/o standards 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma slew lvttl ?????? high low lvcmos 3.3 v ?????? high low lvcmos 2.5 v ????? ?highlow lvcmos 1.8 v ???? ??highlow lvcmos 1.5 v ?? ????high low notes: 1. there will be a difference in ti ming between the standard+ i/o ba nks and the advanced i/o banks ( table 2-26 ). refer to the i/o timing tables beginning on page 3-31 and table 2-12 on page 2-30 for the standards supported by each device. 2. refer to table 2-14 on page 2-31 for i/o bank type definition. table 2-26 ? igloo output drive for advanced i/o bank type i/o standards 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma slew lvttl ??????? high low lvcmos 3.3 v ??????? high low lvcmos 2.5 v ??????? high low lvcmos 2.5/5.0 v ??????? high low lvcmos 1.8 v ?????? ? high low lvcmos 1.5 v ????? ??highlow notes: 1. there will be a difference in ti ming between the advanced i/o banks and the standard+ i/o banks ( table 2-25 ). refer to the i/o timing tables beginning on page 3-31 and table 2-12 on page 2-30 for the standards supported by each device. 2. refer to table 2-14 on page 2-31 for i/o bank type definition.
igloo low-power flash fpgas wi th flash*freeze technology 2-50 advanced v0.1 flash*freeze technology and low-power modes the actel igloo family offers ultra-low power consumption in active and st atic modes by utilizing the unique flash*freeze technology. igloo devices offer various power-saving modes that enable every system to utili ze modes that achieve the lowest total system power. low-power active capability (s tatic idle) allows for ultra- low power consumption (from 25 w) while the igloo device is operational in the system by maintaining sram, registers, i/os, and logic functions. flash*freeze technology provides an ultra-low-power static mode (flash*freeze mode) that retains all sram and register information with rapid recovery to active (operating) mode. the mech anism enables the user to quickly (within 1 s) enter an d exit flash*freeze mode by activating the flash*freeze (ff) pin while all power supplies are kept in their orig inal states. in addition, i/os and clocks connected to the fpga can still be driven or toggling without impact on device power consumption. while in flash*freeze mode, the device retains all core register states and sram information. no power is consumed by the i/o banks, clocks, jtag pins, or plls, and the igloo device consumes as little as 5 w in this mode. power conservation techniques igloo fpgas provide many ways to conserve power; however, there are also many design techniques that can be used to reduce power on the board. actel recommends that the user ti e any unused power supplies (such as v ccpll , v cci , vmv, and v pump ) and unused i/o signals to the ground plane. using low-voltage cmos i/o standard signals and the lowest drive strength will reduce switching and result with lower power consumption in active mode. low-power modes overview table 2-27 summarizes the igloo low-power modes that achieve power consumption reduction when the fpga or system is idle. table 2-27 ? igloo power modes summary mode v cci v cc core clocks ulsicc macro to enter mode to resume operation trigger active on on on on n/a initiate clock none ? static idle on on on off n/a stop clock initiate clock external flash*freeze type 1 on on on on ? n/a assert ff pin deassert ff pin external flash*freeze type 2 on on on on ? used to enter flash*freeze mode assert ff pin and assert lsicc deassert ff pin external sleep on off off off n/a shut down v cc turn on v cc supply external shutdown off off off off n/a shut down v cc and v cci supplies turn on v cc and v cci supplies external note: ? external clocks can be left toggling when while the device is in flash*freeze mode. cl ocks generated by th e embedded pll will b e turned off automatically.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-51 static (idle) mode in static (idle) mode, non e of the clock inputs is switching, and static power is the only power consumed by the device. this mode can be achieved by switching off the incoming clocks to the fpga benefitting from reduced power consumption. in addition, i/os draw only minimal leakage current. in this mode, embedded sram, i/os, and registers retain their values so the device can enter and exit this mode just by switching the clocks on or off. if the device embedded pll is used as the clock source, static (idle) mode can easily be entered by pulling low the pll powerdown pin (active low), which will turn off the pll. flash*freeze mode igloo fpgas offer an ultra-low static power mode to reduce power consumption while preserving the state of the registers and sram contents, without switching off any power supplies, inputs, or input clocks. flash*freeze technology enab les the user to switch to flash*freeze mode within 1 s, thus simplifying low- power design implementation. the flash*freeze (ff) pin (active low) is a dedicated pin used to enter or exit flash*freeze mode directly, or the pin can be routed internally to the fpga core to allow the user's logic to decide if and when it is safe to transition to this mode. if the ff pin is not used, it ca n be used as a regular i/o, benefitting from the inherent low power consumption of the igloo devices. the ff pin has a built-in glitch filter that ensures spurious glitches are filtered out to prevent entering or exiting flash*freeze mode accidentally. there are two ways to use flash*freeze mode. in flash*freeze type 1, enteri ng and exiting the mode is exclusively controlled by the assertion and deassertion of the ff pin. in flash*freeze mode type 2, entering and exiting the mode is controlled by both the ff pin and the user-defined lsicc sign al available in the ulsicc macro. refer to table 2-28 for flash*freeze (ff) pin and lsicc signal assertion and deassertion values. flash*freeze type 1: control by dedicated flash*freeze pin the device will enter flash* freeze mode 1 s after the dedicated ff pin is asserted, and returns to normal operation when the ff pin is deasserted ( figure 2-37 ). in this mode, ff pin assertion or deassertion is the only condition that determines entering or exiting flash*freeze mode after 1 s. this mode is implemented by enabling flash*freeze mode (default sett ing) in the compile option of the actel designer software. the ff pin threshold voltages are defined by v cci and the supported single-ended i/o standard in the corresponding i/o bank. figure 2-37 shows the concept of ff pin control in flash*freeze mode type 1. figure 2-38 on page 2-52 shows the timing diagram for entering and exiting flash*freeze mode type 1. table 2-28 ? flash*freeze mode type 1 and type 2 ? signal assertion and deassertion values signal assertion value deassertion value flash*freeze (ff) pin logic '0' logic '1' lsicc signal logic '1' logic '0' notes: 1. the flash*freeze (ff) pin is an active low signal and lsicc is an active high signal. 2. lsicc signal is used only in flash*freeze mode type 2. figure 2-37 ? igloo flash*freeze mode type 1 ? co ntrolled by the flash*freeze pin ff signal flash*freeze mode control flash*freeze (ff) pin flash*freeze technology actel igloo fpga flash*freeze mode
igloo low-power flash fpgas wi th flash*freeze technology 2-52 advanced v0.1 flash*freeze type 2: control by dedicated flash*freeze pin and internal logic the device can enter flash*freeze mode by activating the ff pin together with other user-defined control logic or delay circuitry within the fpga core ( figure 2-39 ). this method enables the design to perform important activities before allowing the device to enter flash*freeze mode, such as transitioning into a safe state or completing the processing of a critical event. the device will only enter flash*freeze mode when the flash*freeze pin is asserted and the ulsicc macro input signal, called the lsicc signal, is asserted. one condition is not sufficient to enter flash*freeze mode type 2; both the ff pin and lsicc signal must be asserted. when flash*freeze type 2 is implemented in the design, the ulsicc macro needs to be instantiated by the user. there are no functional differences with the device when ulsicc macro is instantiated or not, and lsicc signal is asserted or deasserted. the lsicc signal is used only to control entering flash*freeze mode. figure 2-40 on page 2-53 shows the timing diagram for entering and exiting flash*freeze mode type 2. after exiting flash*freeze mode type 2 by deasserting the flash*freeze pin, the lsicc signal needs to be deasserted by the user desi gn. this will prevent entering flash*freeze mode by asserting the flash*freeze pin only. refer to the actel igloo/e flash*freeze technology and low power modes application note for more information about the softwa re implementation of this mode. figure 2-38 ? flash*freeze mode type 1 ? timing diagram normal operation flash*freeze mode normal operation flash*freeze pin t = 1 s t = 1 s figure 2-39 ? igloo flash*freeze mode type 2 ? co ntrolled by flash*freeze pin and internal logic (lsicc signal) user design ff signal ff signal flash*freeze mode control flash*freeze (ff) pin enables entering flash*freeze mode actel igloo device flash*freeze mode delay circuit/ control logic ulsicc macro lsicc signal and flash*freeze technology
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-53 users can also assert the input of the lsicc signal internally during normal oper ation. in this case, there is no difference between flash*freeze mode type 1 and type 2, and the ff pin exclus ively controls entering and exiting flash*freeze mode. in flash*freeze mode type 2 operation, entering flash*freeze mode is done wi thin 1 s after asserting the last signal that triggers flash*freeze mode (ff pin or lsicc signal), assuming one of the signals is already asserted. in flash*freeze mode type 1 operation, entering flash*freeze mode is done within 1 s after asserting the ff pin only. in flash*freeze mode type 1 and type 2, exiting flash*freeze mode is done wi thin 1 s after deasserting the ff pin only. table 2-29 summarizes the flash*freeze mode implementations. figure 2-40 ? flash*freeze mode type 2 ? timing diagram lsicc signal normal operation flash*freeze mode normal operation flash*freeze pin t = 1 s t = 1 s table 2-29 ? flash*freeze mode usage flash*freeze mode type description flash*freeze pin state instantiate ulsicc macro lsicc signal operating mode 1 flash*freeze mode is controlled only by the ff pin. deasserted no n/a normal operation asserted no n/a flash*freeze mode 2 flash*freeze mode is controlled by the ff pin and lsicc signal. "don?t care" yes deasserted normal operation deasserted yes "don?t care" normal operation asserted yes asserted flash*freeze mode note: refer to table 2-28 on page 2-51 for flash*freeze pin and lsicc signal assertion and deassertion values.
igloo low-power flash fpgas wi th flash*freeze technology 2-54 advanced v0.1 i/o state in flash*freeze mode when the device enters flash*freeze mode, i/os will become tristated. if the weak pull-up or pull-down feature is used, the i/os will maintain the configured weak pull-up or pull-down st atus. this feature enables the design to set the i/o state to a certain level that is determined by the pull-up/- down configuration. for example, use the output buf fer and enable weak pull- down to drive a signal low to an external component while the igloo device is in flash*freeze mode. table 2-30 shows the i/o pad state based on the configuration and buffer type. note that configuring weak pull-up or pu ll-down for the ff pin is not allowed. flash*freeze mode design considerations entering flash*freeze mode ? the device was designed and optimized to enter flash*freeze mode only wh en power supplies are stable. if the device is be ing powered up while the ff pin is asserted (flash*freez e mode type 1) or both ff pin and lsicc signal are asserted (flash*freeze mode type 2), the device is expe cted to enter flash*freeze mode within 5 s after the i/os and fpga core have reached their activation levels. ? if the device is already powered up and then the ff pin is asserted, the device will enter flash*freeze mode within 1 s (type 1). in flash*freeze mode type 2 operation, entering flash*freeze mode is done within 1 s after both ff pin and lsicc signal are asserted. exiting flash*freeze mode is done within 1 s after deasserting the ff pin only. ? if an embedded pll is used, entering flash*freeze mode will automatically power down the pll. ? the pll output clocks will stop toggling within 1 s after the assertion of the ff pin in type 1, or after both ff pin and lsicc signal are asserted in type 2. at the same time, i/os will transition into the state specified in table 2-30 . the user design must ensure it is safe to enter flash*freeze mode. during flash*freeze mode ? inputs and input clocks to the fpga can toggle without any impact on static power consumption, assuming weak pull-up or pull-down is not selected. ? if weak pull-up or pull-do wn is selected and the input is driven to the opposite direction, power dissipation will occur. ? any toggling signals will be charging and discharging the package pin capacitance. ? outputs will be tristated, and the outp ut of the input or bidirectional buffer tied to the internal logic will be set to logic 1. refer to table 2-30 for more information. ? jtag operations such as jtag commands, jtag bypass, programming and authentication cannot be executed. the device must exit flash*freeze mode before jtag commands can be sent. ? the ff pin must be externally driven (deasserted) for the device to stay in flash*freeze mode. ? the ff pin is still active; i.e., the pin is used to exit flash*freeze mode when deasserted. table 2-30 ? flash*freeze mode (type 1 and type 2)?i/o pad state buffer type internal weak pull-up/-down i/o pad state in flash*freeze mode input enabled weak pull-up/pull-down* disabled tristate* output enabled weak pull-up/pull-down disabled tristate tristate output buffer e = 0 (tristate) n/a tristate e = 1 (output) n/a tristate bidirectional e = 0 (input ) enabled weak pul l-up/pull-down* disabled tristate* e = 1 (output) enabled weak pull-up/pull-down disabled tristate note: *internal core logic driven by this input buffer will be tied to logic 1 as long as the device is in flash*freeze mode.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-55 exiting flash*freeze mode ? if the embedded pll is used, the user design must allow maximum acquisition time for the pll to acquire the lock signal. ? within 0.5 s of deassertin g the ff pin, the input buffer can capture new in put values. within the next 0.5 s, the output buffers are able to drive the new output values from the core. sleep mode actel igloo fpgas support sleep mode when device functionality is not required. in sleep mode, the fpga core voltage supply (v cc ) is turned off (either grounded or floated) while other power supplies are left on, resulting in the fpga core being turned off to reduce power consumption. while th e igloo device is in sleep mode, the rest of the system can still be operating and driving the input buffers of the igloo device. the driven inputs do not pull up the internal power planes, and the current draw is limited to minimal leakage current. table 2-31 shows the power supply status in sleep mode. when the v cc power supply is powered off, the corresponding power pin can be left floating or grounded. shutdown mode for agl030 devices, shutdown mode can be used by turning off all power supplies when the device function is not needed. cold-sparing and hot-insertion features enable these devices to be powered down without turning off the entire system. when power returns, the live-at-power-up feature enab les operation of the device after reaching the voltage activation point. refer to the actel igloo/e flash*freeze technology and low power modes application note for more information on how to use tools and system implementation of the various power modes supported by igloo devices. table 2-31 ? sleep mode?power supply requirement for igloo devices power supplies igloo/e devices v cc powered off v cci = vmv powered on v jtag powered on v pump powered on
igloo low-power flash fpgas wi th flash*freeze technology 2-56 advanced v0.1 user i/o naming convention due to the comprehensive and flexible nature of igloo devi ce user i/os, a naming scheme is used to show the details of each i/o ( figure 2-41 and figure 2-42 on page 2-57 ). the name identifies to which i/o bank it belongs, as well as pairing and pin polarity for differential i/os. i/o nomenclature = ff/gmn/iouxwby gmn is only used for i/os that also have ccc access?i.e., global pins. ff = indicates the i/o dedicated for the flash*freeze mode activation pin g=global m = global pin location associated with each ccc on the device: a (northwest corner), b (northeas t corner), c (east middle), d (southeast corner), e (southwest corner), and f (west middle) n = global input mux and pin number of the associated global location m, either a0, a1, a2, b0, b1, b2, c0, c1, or c2. figure 2-15 on page 2-17 shows the three input pins per clock source mux at ccc location m. u = i/o pair number in the bank, starting at 00 from the northwest i/o bank and proceeding in a clockwise direction x = p or u (positive), n or v (negative) for differential pa irs, or r (regular?single-ende d) for the i/os that support single-ended and voltage-refe renced i/o standards only. w = d (differential pair), p (pair), or s (single-ended). d (d ifferential pair) if both me mbers of the pair are bonded out to adjacent pins or are separated only by one gnd or nc pin; p (pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or s (singl e-ended) if the i/o pair is not bonded out. for differential (d) pairs, adjacency for ball grid pa ckages means only vertical or horizontal. diagonal adjacency does not meet the requiremen ts for a true differential pair. b = bank y = bank number (0?3). the bank numb er starts at 0 from th e northwest i/o bank and proceeds in a clockwise direction. note: the agl030 device does not support a pll (v complf and v ccplf pins). figure 2-41 ? naming conventions of igloo devices with two i/o banks ? top view ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c" agl030 agl060 agl125 gnd v cc gnd v cci b1 v cc gnd v cci b0 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 v complf v ccplf gnd v cc v cci b1 gnd gnd v cc v cci b0 gnd vmv1 gndq gnd gnd v cci b1 v cci b1 v cc v cci b1 v cc gnd vmv1 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd gndq vmv0 gnd vcc gnd v cci b0 v cci b0 vcc v cci b0 gnd vmv0 gndq
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-57 figure 2-42 ? naming conventions of igloo devices with four i/o banks ? top view agl250 agl600 agl1000 gnd vcc gnd v cci b3 bank 3 bank 3 bank 1 bank 1 bank 2 bank 0 v complf v ccplf gnd v cc v cci b3 gnd vmv3 gndq gnd gnd v cci b2 v cci b2 v cc v cci b2 v cc gnd vmv2 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd v cc v cci b1 gnd v cc gnd v cci b1 gnd gndq vmv1 v cc v cci b0 gnd v cc v cci b0 gnd v cci b0 gnd vmv0 gndq ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c"
igloo low-power flash fpgas wi th flash*freeze technology 2-58 advanced v0.1 pin descriptions supply pins gnd ground ground supply volt age to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. this minimizes the noise transfer within the package and improves input signal integr ity. gndq must always be connected to gnd on the board. v cc core supply voltage supply voltage to the fpga core, nominally 1.5 v for igloo v5 devices and 1.2 v or 1.5 v for igloo v2 devices. v cc is required for powering the jtag state machine in addition to v jtag . even when an igloo device is in bypass mode in a jtag chain of interconnected devices, both v cc and v jtag must remain powered to allow jtag signals to pass through the igloo device. for igloo v2 devices, v cc can be switched dynamically from 1.2 v to 1.5 v or vice versa. this allows in system programming when v cc is at 1.5 v and the benefit of low-power operation when v cc is at 1.2 v. v cci bx i/o supply voltage supply voltage to the bank 's i/o output buffers and i/o logic. bx is the i/o bank number. there are eight i/o banks on igloo devices plus a dedicated v jtag bank. each bank can have a separate v cci connection. all i/os in a bank will run off the same v cci bx supply. v cci can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding v cci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to th e input buffers of each i/o bank. x is the bank number. within the package, the vmv plane is decoupled from the simultaneous switching noise originated from the output buffer v cci domain. this minimizes the noise transfer within the package and improves input signal integrity. each bank must have at least one vmv connection, and no vmv should be left uncon nected. all i/os in a bank run off the same vmvx supply. vmv is us ed to provide a quiet supply voltage to the input buffers of each i/o bank. vmvx can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corre sponding vmv pins tied to gnd. vmv and v cci should be at the same voltage within a given i/o bank. used vmv pins must be connected to the corresponding v cci pins of the same bank (i.e., vmv0 to v cci b0, vmv1 to v cci b1, etc.). v ccplf pll supply voltage 7 supply voltage to analog pll, nominally 1.5 v for igloo v5 devices and 1.2 v or 1.5 v for igloo v2 devices. if unused, v ccplf should be tied to either the power supply or gnd. v complf pll ground 7 ground to analog pll power supplies. unused v complf pins should be connected to gnd. v jtag jtag supply voltage igloo devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). is olating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the v jtag pin together with the trst pin could be tied to gnd. it should be noted that v cc is required to be powered for jtag operation; v jtag alone is insufficient. if an igloo device is in a jtag chain of interconnected boards, the board containing the igloo device can be powered down, provided both v jtag and v cc to the igloo part remain powered; otherwise, jtag signals will not be able to transition the igloo device, even in bypass mode. actel recommends that v pump and v jtag power supplies are kept separate with independent filtering capacitors rather than supplying them from a common rail. v pump programming supply voltage igloo devices support single-voltage isp programming of the configuration flash and flashrom. for programming, v pump should be 3.3 v nominal. during normal device operation, v pump can be left floating or can be tied (pulled up) to any voltage between 0 v and 3.45 v. programming power supply voltage (v pump ) range is 3.15 v to 3.45 v. when the v pump pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the ch arge pump circuitry. for proper programming, 0.01 f and 0.33 f capacitors (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. 7. the agl030 device does not support this feature.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-59 actel recommends that v pump and v jtag power supplies are kept separate with inde pendent filtering capacitors rather than supplying them from a common rail. user pins i/o user input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. input and output signal levels are compatible with the i/o standard selected. during programming, i/os be come tristated and weakly pulled up to v cci . with v cci , vmv, and v cc supplies continuously powered up, when the device transitions from programming to operating mode, the i/os are instantly configured to the desired user configuration. unused i/os are conf igured as follows: ? output buffer is disabled (with tristate value of high impedance). ? input buffer is disabled (with tristate value of high impedance). ? weak pull-up is programmed. gl globals gl i/os have access to certai n clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as i/os, since they have identical capabilities. unused gl pins are confi gured as inputs with pull-up resistors. see more detailed descriptions of global i/o connectivity in the "clock conditioning circuits" section on page 2-14 . all inputs labeled gc/gf are direct inputs into the quadrant clocks. fo r example, if gaa0 is used for an input, gaa1 and gaa2 are no longer available for input to the quadrant globals . all inputs labeled gc/gf are direct input into the chip -level globals, and the rest are connected to the quadrant globals. the inputs to the global network are multiplexed, and only one input can be used as a global input. refer to the "user i/o naming convention" section on page 2-56 for an explanation of the naming of global pins. ff flash*freeze m ode activation pin the ff pin is a dedicated input pin that is used to enter and exit flash*freeze mode. the ff pin is active low, has the same characteristics as a single-ended i/o, and must meet the maximum rise and fall time. when flash*freeze mode is not used in the design, the ff pin is available as a regular i/o. when flash*freeze mode is used, the ff pin must not be left floating to avoid accidentally entering flash*freeze mode. while in flash*freeze mode, the flash*freeze pin should be constantly asserted. the flash*freeze pin can be used with any single-ended i/o standard supported by th e i/o bank in which the pin is located, and input signal levels compatible with the i/o standard selected. the ff pi n should be treated as a sensitive asynchronous signal. when defining pin placement and board layout, simultaneously switching outputs (ssos) and their effects on sensitive asynchronous pins must be considered. unused ff or i/o pins are tristated with weak pull-up. this default configuration applies to both flash*freeze mode and normal operation mode. no user intervention is required. table 2-32 shows the flash*freeze pin location on the available packages for igloo devices. the flash*freeze pin location is independent of device, allowing migration to larger or smaller igloo devices while maintaining the same pin location on the board. table 2-32 ? flash*freeze pin location in igloo family packages (device-independent) package flash*freeze pin cs196 tbd qn132 b12 vq100 27 fg144 l3 fg256 t3 fg484 w6
igloo low-power flash fpgas wi th flash*freeze technology 2-60 advanced v0.1 jtag pins igloo devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). v cc must also be powered for the jtag state machine to operate, even if the device is in bypass mode; v jtag alone is insufficient. both v jtag and v cc to the igloo part must be supplied to allow jtag signals to transition the igloo device. isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selecti on and simplifies power supply and pcb design. if the jtag in terface is neither used nor planned for use, the v jtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used, actel recommends tying off tck to gnd through a resistor placed close to the fpga pin. this prevents jtag operation in case tms enters an undesired state. note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. refer to table 2-33 for more information. tdi test data input serial input for jtag boundary scan, isp, and ujtag usage. there is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jtag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of the ieee 1532 boundary scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. if jtag is not used, an external pull-down resistor could be included to ensure the test access port (tap) is held in reset mode. the resistor values must be chosen from table 2-33 and must satisfy the parallel resistance value requirement. the values in table 2-33 correspond to the resistor recommended when a single device is used and the equi valent parallel resistor when multiple devices are conn ected via a jtag chain. in critical applications, an upset in the jtag circuit could allow entrance to an undesired jtag state. in such cases, actel recommends tying off trst to gnd through a resistor placed close to the fpga pin. note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. special function pins nc no connect this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc do not connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. table 2-33 ? recommended tie-off values for the tck and trst pins v jtag tie-off resistance v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k notes: 1. equivalent parallel resistance if more than one device is on the jtag chain. 2. the tck pin can be pulled up/down. 3. the trst pin is pulled down.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-61 software tools overview of tools flow the igloo family of fpgas is fully supported by both actel libero ide and designer fpga development software. actel libero ide is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment (see the libero ide flow diagram located on the actel website). libero ide includes synplify ? ae from synplicity, ? viewdraw ? ae from mentor graphics, ? model sim ? hdl simulator from mentor graphics, waveformer lite tm ae from synapticad, ? palace tm ae physical synthesis from magma design automation, tm and designer software from actel. actel designer software is a place-and-route tool and provides a comprehensive suit e of backend support tools for fpga development. the designer software includes the following: ? smarttime?a world-class in tegrated static timing analyzer and constrain ts editor that supports timing-driven place-and-route ? netlistviewer?a design netlist schematic viewer ? chipplanner?a graphical floorplanner viewer and editor ? smartpower?a tool that enables the designer to quickly estimate the power consumption of a design ? pineditor?a graphical ap plication for editing pin assignments and i/o attributes ? i/o attribute editor?a to ol that displays all assigned and unassigned i/o macros and their attributes in a spreadsheet format with the designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. additionally, actel back-annotation flow is compatible with all the major simulators. another tool included in the design er software is the smartgen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel designer software is compatible with the most popular fpga design entry and verification tools from eda vendors such as mentor graphics, synplicity, synopsys, and cadence. ? the designer software is available for both the windows ? and unix operating systems. programming programming can be performed using tools such as silicon sculptor ii (bp micro sys tems) or flashpro3 (actel). the user can generate stp programming files from the designer software and use these files to program a device. the igloo device can be serialized with a unique identifier stored in the flashrom of each device. serialization is an automatic assignment of serial numbers that are stored within the stapl file used for programming. the area of the flashrom used for holding such identifiers is defined using smartgen, and the range of serial numbers to be used is defined at the time of stapl file generation with flashpoint. serial number values for stapl f ile generation can even be read from a file of predefined values. serialized programming using a serialized stapl file can be done through actel in-house programming (ihp), an external vendor using silicon sculpt or software, or the isp capabilities of the flashpro software. refer to the "isp" section on page 2-62 for programming conditions. security igloo devices have a built-in 128-bit aes decryption core (except the agl030 device). the decryption core facilitates secure in-sys tem programming of the fpga core array fabric and the flashrom. the flashrom and the fpga core fabric can be programmed independently of each other, allowing the flashrom to be updated without the need for change to the fpga core fabric. the aes master key is stored in on-chip nonvolatile memory (flash). the aes master key can be preloaded into parts in a secure programming environment (such as the actel in-house programming center), and then "blank" parts can be shipped to an untrusted programming or manufacturing center for final personalization with an ae s-encrypted bitstream. late- stage product changes or personalization can be implemented easily and securely by simply sending a stapl file with aes encrypted data. secure remote field updates over public networks (such as the internet) are possible by sending and programming a stapl file with aes-encrypted data.
igloo low-power flash fpgas wi th flash*freeze technology 2-62 advanced v0.1 128-bit aes decryption 8 the 128-bit aes standard (fips-192) block cipher is the nist (national institute of standards and technology) replacement for des (data encryption standard fips46-2). aes has been desi gned to protect sensitive government information well into the 21st century. it replaces the aging des, which nist adopted in 1977 as a federal information processing standard used by federal agencies to protect sensitiv e, unclassified information. the 128-bit aes standard has 3.4 10 38 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit aes cipher text using exhaustive techniques. ke ys are stored (securely) in igloo devices in nonvolatile flash memory. all programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programming verification is performed on-chip, ensuring that the contents of igloo devices remain secure. aes decryption can also be used on the 1,024-bit flashrom to allow for secure remote updates of the flashrom contents. this allows for easy, secure support for subscription model products. isp igloo devices support ieee 1532 isp via jtag and require a single v pump voltage of 3.3 v during programming. in addition, programming via a microcontroller in a target system can be achieved. igloo devices can be programmed in system when the device is using 1.5 v supply voltage to the fpga core. igloo v2 devices can operate using either 1.2 v core voltage or 1.5 v core voltag e hence when 1.2 v is used the device cannot be reprogrammed in the system although it has lower active power than with 1.5 v core voltage. igloo device can not be programmed in-system when the device is in flash*freeze mode. the igloo device should exit flash*freeze mode and be in normal operation for programming to start. programming operations could be achieved when the device is in normal operating mode and 1.5 v core voltage is used. 8. the agl030 device does not support aes decryption.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-63 jtag 1532 igloo devices support the jtag-based ieee 1532 standard for isp. in order to start jtag operations the igloo device should exit flash*freeze mode and be in normal operation for before starting to send jtag commands to the device. as part of this support, when a igloo device is in an unpro grammed state, all user i/o pins are disabled. this is achieved by keeping the global io_en signal deactivated, which also has the effect of disabling the input buffers. the sample/preload instruction captures the status of pads in parallel and shifts them out as new data is shifted in for loading into the boundary scan register. when the igloo device is in an unprogrammed state, the sample/preload instruction has no effect on i/o status; however, it will continue to shift in new data to be loaded into the bsr. therefore, when sample/preload is used on an unprogrammed device, the bsr will be loaded with undefined data. for jtag timing information on setup, hold, and fall times, refer to the flashpro user?s guide . boundary scan igloo devices are compatible with ieee standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. jtag operations are used during boundary sc an testing; therefore, the flash*freeze pin must be deasserted for successful boundary scan operations. the basic igloo boundary scan logic circuit is composed of the tap controller, test data registers, and instruction register ( figure 2-45 on page 2-65 ). this circuit supports all mandatory ieee 1149.1 instructions (extest, sample/preload, and bypass) and the optional idcode instruction ( table 2- 34 ). each test section is accessed through the tap, which has five associated pins: tck (tes t clock input), tdi, tdo (test data input and output), tms (test mode selector), and trst (test reset input). tms, tdi, and trst are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary scan test usage. refer to the "jtag pins" section on page 2-60 for pull-up/down recommendations for tdo and tck pins. table 2-35 gives pull-down recommendations for the trst and tck pins. table 2-34 ? boundary scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff table 2-35 ? trst and tck pull-down recommendations v jtag tie-off resistance* v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k note: *equivalent parallel resistance if more than one device is on jtag chain ( figure 2-43 ) note: tck is correctly wired with an equivalent tie-off resistance of 500 , which satisfies the table for v jtag of 1.5 v. the resistor values for trst are not appropriate in this case, as the tie-off resistance of 375 is below the recommended minimum for v jtag = 1.5 v, but would be appropriate for a v jtag setting of 2.5 v or 3.3 v. figure 2-43 ? parallel resistance on jtag chain of devices tdi tdi tdi tdi tdo tdo tdo tdo jtag header actel fpga 1 actel fpga 2 actel fpga 3 actel fpga 4 2 k 2 k 2 k 2 k 1.5 v tck trst vjtag gnd 1.5 k 1.5 k 1.5 k 1.5 k
igloo low-power flash fpgas wi th flash*freeze technology 2-64 advanced v0.1 the tap controller is a 4-bi t state machine (16 states) that operates as shown in figure 2-44 . the 1s and 0s represent the values that mu st be present on tms at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is oper ating in that state. the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architec ture. on power-up, the tap controller enters the test-logi c-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for five tck cycles. the trst pin may also be used to asyn chronously place the tap controller in the test-logic-reset state. igloo devices support three types of test data registers: bypass, device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device . this speeds up test data transfer to other devices in a test data path. the 32-bit device identification register is a shift register with four fields (lsb, id number, part number, and version). the boundary scan register observes and controls the state of each i/o pin. each i/o cell has three boundary scan register cells, each with serial-in, serial-out, parallel-in, and parallel-out pins. figure 2-44 ? tap state machine 1 test_logic_reset run_test_idle select_dr capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr select_ir capture_ir shift_ir exit1_ir pause_ir exit2_ir update_ir 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 2-65 the serial pins are used to serially conne ct all the boundary scan regi ster cells in a device into a boundary scan register chain, which starts at the tdi pin and en ds at the tdo pin. the pa rallel ports are connected to the internal core logic i/o tile and the input, output, an d control ports of an i/o buffer to capture an d load data into the register to control or observe the logic state of each i/o. figure 2-45 ? boundary scan chain in igloo device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers

igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-1 dc and switching characteristics general specifications dc and switching characteristics for ?f speed grade targets are based only on simulation. the characteristics provided for the ?f speed grade ar e subject to change after estab lishing fpga specifications. some restrictions might be added and will be reflected in futu re revisions of this documen t. the ?f speed grade is only supported in the commer cial temperature range. operating conditions stresses beyond those listed in table 3-1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended op erating conditions specified in table 3-2 on page 3-2 is not implied. table 3-1 ? absolute maximum ratings symbol parameter limits units v cc dc core supply voltage ?0.3 to 1.65 v v jtag jtag dc voltage ?0.3 to 3.75 v v pump programming voltage ?0.3 to 3.75 v v ccpll analog power supply (pll) ?0.3 to 1.65 v v cci dc i/o output buffer supply voltage ?0.3 to 3.75 v vmv dc i/o input buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (v cci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-inserti on mode is disabled) v t stg 2 storage temperature ?65 to +150 c t j 2 junction temperature +125 c notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undersho ot or overshoot according to the limits shown in table 3-4 on page 3-3 . 2. for flash programming and rete ntion maximum limits refer to table 3-3 on page 3-3 and for recommended operating limits refer to table 3-2 on page 3-2 .
igloo low-power flash fpgas wi th flash*freeze technology 3-2 advanced v0.1 table 3-2 ? recommended operating conditions symbol parameter commercial industrial units t j junction temperature 0 to 70 ?40 to +85 c v cc 1.5 v dc core supply voltage 1 1.425 to 1.575 1.425 to 1.575 v 1.2 v dc core supply voltage 2 1.14 to 1.26 1.14 to 1.26 v v jtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v v pump programming voltage programming mo de 3.15 to 3.45 3.15 to 3.45 v operation 5 0 to 3.45v 0 to 3.45v v v ccpll analog power supply (pll) 1.5 v dc core supply voltage 1 1.4 to 1.6 1.4 to 1.6 v 1.2 v dc core supply voltage 2 1.14 to 1.26 1.14 to 1.26 v v cci and vmv 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3 .0 to 3.6 3.0 to 3.6 v notes: 1. for igloo v2 or v5 devices 2. for igloo v2 devices only 3. the ranges given here are for power supplies only. the recommended input voltage ranges specific to each i/ o standard are giv en in table 3-22 on page 3-19 . vmv and v cci should be at the same voltage within a given i/o bank. 4. all parameters representing voltages are measured with respect to gnd un less otherwise specified. 5. v pump can be left floating during operation (not programming mode).
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-3 table 3-3 ? flash programming limits ? retention, storage and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 110 industrial 500 20 years 110 110 notes: 1. this is a stress rating only; functi onal operation at any condition other than those indicated is not implied. 2. these limits apply for program/ data retention only. refer to table 3-1 on page 3-1 and table 3-2 for device operating conditions and absolute limits. table 3-4 ? overshoot and undershoot limits (as measured on quiet i/os) 1 v cci and vmv average v cci ?gnd overshoot or unde rshoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of six clock cycles (estimat ed sso density over cycles). if the overshoot/undershoot occur s at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v. 3. this table refers only to overshoot/undershoot limits fo r simultaneous switching i/os and does not provide pci overshoot/undershoot limits.
igloo low-power flash fpgas wi th flash*freeze technology 3-4 advanced v0.1 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into every igloo de vice. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequence with minimized current spikes or su rges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 3-1 . there are five regions to consider during power-up. igloo i/os are activated only if all of the following three conditions are met: 1. v cc and v cci are above the minimum specified trip points ( figure 3-1 ). 2. v cci > v cc ? 0.75 v (typical) 3. chip is in the operating mode. v cci trip point: ramping up: 0.6 v < trip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < trip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v v cc and v cci ramp-up trip points are about 100 mv higher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current su rges. note the following: ? during programming, i/os become tristated and weakly pulled up to v cci . ? jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns delay from input buffer activation to make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design. figure 3-1 ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification. v cc = v cci + vt
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-5 thermal characteristics introduction the temperature variable in the actel designer software refers to the junction te mperature, not the ambient temperature. this is an im portant distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. eq 3-1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 3-1 where: t a = ambient temperature t = temperature gradient between junction (silicon) and ambient t = ja * p ja = junction-to-ambient of the package. ja numbers are located in table 3-5 . p = power dissipation package thermal ch aracteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the absolute maximum junction temperature is 110c. eq 3-2 shows a sample calcul ation of the absolute maximum power dissipation allowed for a 484-pin fbga package at commercial temp erature and in still air. eq 3-2 table 3-5 ? package thermal resistivities package type device pin count jc ja units still air 200 ft./min. 500 ft./min. quad flat no lead agl030 132 0.4 21.4 16.8 15.3 c/w agl060 132 0.3 21.2 16.6 15.0 c/w agl125 132 0.2 21.1 16.5 14.9 c/w agl250 132 0.1 21.0 16.4 14.8 c/w very thin quad flat pack (vqfp) all devices 100 10.0 35.3 29.4 27.1 c/w chip scale package (csp) all devices 196 57.8 47.6 43.3 c/w fine pitch ball grid array (fbga) see note* 144 3.8 26.9 22.9 21.5 c/w see note* 256 3.8 26.6 22.8 21.5 c/w see note* 484 3.2 20.5 17.0 15.9 c/w see note* 896 2.4 13.6 10.4 9.4 c/w agl060 144 18.6 55.2 49.4 47.2 c/w agl1000 144 6.3 31.6 26.2 24.2 c/w agl250 256 12.0 38.6 34.7 33.0 c/w agl1000 256 6.6 28.1 24.4 22.7 c/w agl1000 484 8.0 23.3 19.0 16.7 c/w note: *this information applies to all igloo devi ces except those listed below. detailed de vice/package thermal information for all igloo devices will be available in future revisions of the datasheet. maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -------- 110 c70 c ? 20.5c/w ------------------------------------ 1.951 w = = =
igloo low-power flash fpgas wi th flash*freeze technology 3-6 advanced v0.1 temperature and voltage derating factors calculating power dissipation quiescent supply current table 3-6 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, v cc = 1.425 v) for igloo v2 or v5 devices, 1.5 v dc core supply voltage array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.425 0.89 0.94 0.96 1.00 1.01 1.03 1.5 0.820.870.890.930.940.96 1.575 0.77 0.81 0.83 0.87 0.88 0.90 table 3-7 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, v cc = 1.14 v) for igloo v2, 1.2 v dc core supply voltage array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.14 0.91 0.94 0.97 1.00 1.01 1.02 1.2 0.790.820.840.870.880.89 1.26 0.71 0.74 0.76 0.78 0.79 0.80 table 3-8 ? quiescent supply current (i dd ), igloo flash*freeze mode ? core voltage agl030 agl060 agl125 agl250 agl600 agl1000 units typical (25c) 1.2 v 4 8 14 28 60 102 a 1.5 v 6 10 18 34 72 127 a note: ? i dd includes v cc , v pump , v cci , vmv, and i/o static curren ts in worst-case conditions. table 3-9 ? quiescent supply current (i dd ), igloo sleep mode (v cc = 0 v) ? agl030 agl060 agl125 agl250 agl600 agl1000 units v cci = 1.5 v (all banks) ty p i c a l ( 2 5 c ) 555999a v cci = 1.8 v (all banks) ty p i c a l ( 2 5 c ) 5 5 5 11 11 11 a v cci = 2.5 v (all banks) ty p i c a l ( 2 5 c ) 8 8 8 15 15 15 a v cci = 3.3 v (all banks) ty p i c a l ( 2 5 c ) 10 10 10 20 20 20 a note: ? i dd includes v cc , v pump , v cci , and vmv currents. values do not include i/o static contribution. table 3-10 ? quiescent supply current (i dd ), igloo shutdown mode (v cc , v cci = 0 v) ? core voltage agl030 units typical (25c) 1.2 v / 1.5 v 0 a note: ? i dd includes v cc , v pump , v cci , and vmv currents. values do not include i/o static contribution.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-7 power per i/o pin table 3-11 ? quiescent supply current, no igloo flash*freeze mode 1 core voltage agl030 agl060 agl125 agl250 agl600 agl1000 units i cca current 2 typical (25c) 1.2v 14 18 24 38 70 112 a 1.5v 16 20 28 44 82 137 a i cci or i jtag current 3, 4 3.3 v ty p i c a l ( 2 5 c ) 1.2 v / 1.5 v 5 5 5 5 5 5 a 2.5 v ty p i c a l ( 2 5 c ) 1.2 v / 1.5 v 4 4 4 4 4 4 a 1.8 v ty p i c a l ( 2 5 c ) 1.2 v / 1.5 v 3 3 3 3 3 3 a 1.5 v ty p i c a l ( 2 5 c ) 1.2 v / 1.5 v 2 2 2 2 2 2 a notes: 1. to calculate total device i dd , multiply the number of banks used by i cci and add i cca contribution. 2. includes v cc and v pump currents 3. per v cci or v jtag bank 4. values do not include i/o static contribution. table 3-12 ? summary of i/o input buffer power (per pin) ? default i/o software settings applicable to advanced i/o banks vmv (v) static power p dc2 (mw) 1 dynamic power p ac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.69 2.5 v lvcmos 2.5 ? 5.12 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.45 3.3 v pci 3.3 ? 18.11 3.3 v pci-x 3.3 ? 18.11 differential lvds 2.5 2.26 1.20 lvpecl 3.3 5.72 1.87 notes: 1. p dc2 is the static power (where applicable) measured on vmv. 2. p ac9 is the total dynamic power measured on v cc and vmv.
igloo low-power flash fpgas wi th flash*freeze technology 3-8 advanced v0.1 table 3-13 ? summary of i/o input buffer power (per pin) ? default i/o software settings applicable to standard plus i/o banks vmv (v) static power p dc2 (mw) 1 dynamic power p ac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.72 2.5 v lvcmos 2.5 ? 5.14 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.48 3.3 v pci 3.3 ? 18.13 3.3 v pci-x 3.3 ? 18.13 notes: 1. p dc2 is the static power (where applicable) measured on vmv. 2. p ac9 is the total dynamic power measured on v cc and vmv. table 3-14 ? summary of i/o input buffer power (per pin) ? default i/o software settings applicable to standard i/o banks vmv (v) static power p dc2 (mw) 1 dynamic power p ac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.79 2.5 v lvcmos 2.5 ? 5.19 1.8 v lvcmos 1.8 ? 2.18 1.5 v lvcmos (jesd8-11) 1.5 ? 1.52 notes: 1. p dc2 is the static power (where applicable) measured on vmv. 2. p ac9 is the total dynamic power measured on v cc and vmv.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-9 table 3-15 ? summary of i/o input buffer power (per pin) ? default i/o software settings 1 applicable to advanced i/o banks c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 149.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 103.12 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 differential lvds ? 2.5 7.74 88.92 lvpecl ? 3.3 19.54 166.52 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cc and vmv. table 3-16 ? summary of i/o input buffer power (per pin) ? default i/o software settings 1 applicable to standard plus i/o banks c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 452.67 2.5 v lvcmos 35 2.5 ? 258.32 1.8 v lvcmos 35 1.8 ? 133.59 1.5 v lvcmos (jesd8-11) 35 1.5 ? 92.84 3.3 v pci 10 3.3 ? 184.92 3.3 v pci-x 10 3.3 ? 184.92 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cc and vmv. table 3-17 ? summary of i/o input buffer power (per pin) ? default i/o software settings 1 applicable to standard i/o banks c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 431.08 2.5 v lvcmos 35 2.5 ? 247.36 1.8 v lvcmos 35 1.8 ? 128.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 89.46 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cc and vmv.
igloo low-power flash fpgas wi th flash*freeze technology 3-10 advanced v0.1 power consumption of various internal resources table 3-18 ? different components contributing to dynamic power consumption in igloo devices for igloo v2 or v5 devices, 1.5 v dc core supply voltage parameter definition device specific dynamic power (w/mhz) agl1000 agl600 agl250 agl125 agl060 agl030 p ac1 clock contribution of a global rib 14.48 12.77 11.03 11.03 9.3 9.3 p ac2 clock contribution of a global spine 2.48 1.85 1.58 0.81 0.81 0.41 p ac3 clock contribution of a versatile row 0.81 p ac4 clock contribution of a versatile used as a sequential module 0.11 p ac5 first contribution of a versatile used as a sequential module 0.057 p ac6 second contribution of a versatile used as a sequential module 0.207 p ac7 contribution of a versatile used as a combinatorial module 0.17 p ac8 average contribution of a routing net 0.7 p ac9 contribution of an i/o input pin (standard- dependent) see table 3-12 on page 3-7 through table 3-14 on page 3-8 . p ac10 contribution of an i/o output pin (standard-dependent) see table 3-15 on page 3-9 through table 3-17 on page 3-9 . p ac11 average contribution of a ram block during a read operation 25.00 p ac12 average contribution of a ram block during a write operation 30.00 p ac13 static pll contribution 2.55 mw p ac14 dynamic contribution for pll 2.60 note: *for a different output load, drive strengt h, or slew rate, actel recommends using the actel power spreadsheet calculator or smartpower tool in libero ide.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-11 table 3-19 ? different components contributing to dynamic power consumption in igloo devices for igloo v2, 1.2 v dc core supply voltage parameter definition device specific dynamic power (w/mhz) agl1000 agl600 agl250 agl125 agl060 agl030 pac1 clock contribution of a global rib 9.28 8.19 7.07 7.07 5.96 5.96 pac2 clock contribution of a global spine 1.59 1.19 1.01 0.52 0.52 0.26 pac3 clock contribution of a vers atile row 0.52 0.52 0.52 0.519 0.519 0.519 pac4 clock contribution of a versatile used as a sequential module 0.07 0.07 0.07 0.071 0.071 0.071 pac5 first contribution of a versatile used as a sequential module 0.05 0.05 0.05 0.045 0.045 0.045 pac6 second contribution of a versatile used as a sequential module 0.19 0.19 0.19 0.186 0.186 0.186 pac7 contribution of a versatile used as a combinatorial module 0.11 0.11 0.11 0.109 0.109 0.109 pac8 average contribution of a ro uting net 0.45 0.45 0.45 0.449 0.449 0.449 pac9 contribution of an i/o input pin (standard dependent) see table 3-12 on page 3-7 through table 3-14 on page 3-8 . pac10 contribution of an i/o output pin (standard dependent) see table 3-15 on page 3-9 through table 3-17 on page 3-9 . pac11 average contribution of a ram block during a read operation 25.00 pac12 average contribution of a ram block during a write operation 30.00 pac13 static pll contribution 2.55mw pac14 dynamic contribution for pll 2.60 note: *for a different output load, drive strengt h, or slew rate, actel recommends using the actel power spreadsheet calculator or smartpower tool in libero ide.
igloo low-power flash fpgas wi th flash*freeze technology 3-12 advanced v0.1 power calculation methodology this section describes a simplified method to estimate power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number and the frequency of each output clock generated ? the number of combinatorial and se quential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 3-20 on page 3-14 . ? enable rates of output buffers?guidelines are provided for typical applications in table 3-21 on page 3-14 . ? read rate and write rate to the memory?guidelin es are provided for typical applications in table 3-21 on page 3-14 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = p dc1 + n inputs * p dc2 + n outputs * p dc3 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row *p ac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guideline are provided in table 3-20 on page 3-14 . n row is the number of versatile rows used in the design?guidelin es are provided in table 3-20 on page 3-14 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. p ac1 , p ac2 , p ac3 , and p ac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 / 2 * p ac6 ) * f clk n s-cell is the number of versatiles used as sequential modules in the design . when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-20 on page 3-14 . f clk is the global clock signal frequency.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-13 combinatorial cells contribution?p c-cell p c-cell = n c-cell * 1 / 2 * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modu les in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-20 on page 3-14 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 / 2 * p ac8 * f clk n s-cell is the number versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modu les in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-20 on page 3-14 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 / 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate ?guidelines are provided in table 3-20 on page 3-14 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * 2 / 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate ?guidelines are provided in table 3-20 on page 3-14 . 1 is the i/o buffer enable rate ?guidelines are provided in table 3-21 on page 3-14 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 is the ram enable rate for write ope rations?guidelines are provided in table 3-21 on page 3-14 . pll contribution?p pll p pll = p ac13 + p ac14 *f clkout f clkin is the input clock frequency. f clkout is the output clock frequency. 1 1. the pll dynamic contribution depends on the input clock freq uency, the number of output clock signals generated by the pll, and the frequency of each output cloc k. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution.
igloo low-power flash fpgas wi th flash*freeze technology 3-14 advanced v0.1 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic element relative to a clock. it is a percentage. if the toggle rate of a net is 100 % , this means that this net switches at half the cloc k frequency. below are some examples: ? the average toggle rate of a shift register is 100 % because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25 % : ? bit 0 (lsb) = 100 % ? bit 1 = 50 % ? bit 2 = 25 % ?? ? bit 7 (msb) = 0.78125 % ? average toggle rate = (100 % + 50 % + 25 % + 12.5 % + . . . + 0.78125 % ) / 8. enable rate definition output enable rate is the average percentage of time during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100 % . table 3-20 ? toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10% table 3-21 ? enable rate guidelines reco mmended for power calculation component definition guideline 1 i/o output buffer enable rate 100% 2 ram enable rate for read operations 12.5% 3 ram enable rate for write operations 12.5%
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-15 user i/o characteristics timing model figure 3-2 ? timing model operating conditions: std. speed, commercial temperature range (t j = 70c), worst case v cc = 1.425 v, for dc 1.5v core voltag e, applicable to v2 and v5 devices dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvpecl (applicable to advanced i/o banks only)l lvpecl (applicable to advanced i/o banks only) lvds, blvds, m-lvds (applicable for advanced i/o banks only) lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 1.22 ns t pd = 1.20 ns t dp = 1.72 ns t pd = 1.80 ns t dp = 3.05 ns (advanced i/o banks) t pd = 1.49 ns t dp = 4.12 ns (advanced i/o banks) t pd = 0.86 ns t dp = 4.42 ns (advanced i/o banks) t pd = 0.92 ns t py = 0.87 ns (advanced i/o banks) t clkq = 0.90 ns t oclkq = 1.02 ns t sud = 0.82 ns t osud = 0.52 ns t dp = 3.05 ns (advanced i/o banks) t py = 0.87 ns (advanced i/o banks) t py = 1.35 ns t clkq = 0.90 ns t sud = 0.82 ns t py = 0.87 ns (advanced i/o banks) t iclkq = 0.43 ns t isud = 0.47 ns t py = 1.20 ns
igloo low-power flash fpgas wi th flash*freeze technology 3-16 advanced v0.1 figure 3-3 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50 % 50 % v ih v cc v il t dout (r) din gnd t dout (f) 50 % 50 % v cc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-17 figure 3-4 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) v trip v trip v oh v cc d 50 % 50 % v cc 0 v dout 50 % 50 % 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
igloo low-power flash fpgas wi th flash*freeze technology 3-18 advanced v0.1 figure 3-5 ? tristate output buffer timing model and delays (example) d clk q d clk q 10 % v cci t zl v trip 50 % t hz 90 % v cci t zh v trip 50 % 50 % t lz 50 % eout pad d e 50 % t eout (r) 50 % t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50 % t zhs v trip 50 % eout pad d e 50 % 50 % t eout (r) t eout (f) 50 % v cc v cc v cc v cci v cc v cc v cc v oh v ol v ol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-19 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 3-22 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings applicable to advanced i/o banks i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 12 12 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature. table 3-23 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings applicable to standard plus i/o banks i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 8 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 1.5 v lvcmos 4 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature. table 3-24 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings applicable to standard i/o banks i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 1.5 v lvcmos 2 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 22 note: currents are measured at 85c junction temperature.
igloo low-power flash fpgas wi th flash*freeze technology 3-20 advanced v0.1 table 3-25 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 i il i ih i il i ih a a a a 3.3 v lvttl /3.3 v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 3.3 v pci 10 10 15 15 3.3 v pci-x 10 10 15 15 notes: 1. commercial range (0c < t j < 70c) 2. industrial range (?40c < t j < 85c) summary of i/o timing characteristics ? def ault i/o software settings table 3-26 ? summary of ac measuring points standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 3.3 v pci 0.285 * v cci (rr) 0.615 * v cci (ff) 3.3 v pci-x 0.285 * v cci (rr) 0.615 * v cci (ff) table 3-27 ? i/o ac paramete r definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer de lay through the i/o interface t eout enable to output buffer tristate control delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-21 table 3-28 ? summary of i/o timing characteristics?software de fault settings, std. speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v applicable advanced i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 0.98 3.05 0.19 0.87 0.67 3.11 2.49 2.74 3.13 6.74 6.12 ns 2.5 v lvcmos 12 ma high 35pf ? 0.98 3.08 0.19 1.10 0.67 3.14 2.96 2.81 3.01 6.77 6.59 ns 1.8 v lvcmos 12 ma high 35pf ? 0.98 3.05 0.19 1.03 0.67 3.11 2.65 3.11 3.49 6.74 6.28 ns 1.5 v lvcmos 12 ma high 35pf ? 0.98 3.47 0.19 1.20 0.67 3.54 3.07 3.29 3.58 7.17 6.70 ns 3.3 v pci per pci spec high 10pf 25 2 0.98 2.38 0.19 0.75 0.67 2.43 1.82 2.74 3.13 6.06 5.45 ns 3.3 v pci-x per pci-x spec high 10pf 25 2 0.98 2.38 0.19 0.72 0.67 2.43 1.82 2.74 3.13 6.06 5.45 ns lvds 24 ma high ? ? 0.98 1.72 0.19 1.35 ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 0.98 1.72 0.19 1.20 ? ? ? ? ? ? ? ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. 2. resistance is used to meas ure i/o propagation delays as de fined in pci specifications. see figure 3-10 on page 3-55 for connectivity. this resistor is not required during normal operation.
igloo low-power flash fpgas wi th flash*freeze technology 3-22 advanced v0.1 table 3-29 ? summary of i/o timing characteristics?software de fault settings, std. speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v applicable standard plus i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 0.98 2.69 0.19 0.87 0.67 2.74 2.22 2.43 2.87 6.37 5.85 ns 2.5 v lvcmos 12 ma high 35pf ? 0.98 2.72 0.19 1.11 0.67 2.77 2.65 2.45 2.77 6.40 6.28 ns 1.8 v lvcmos 8 ma high 35pf ? 0.98 3.35 0.19 1.04 0.67 3.20 3.35 2.53 2.74 6.83 6.98 ns 1.5 v lvcmos 4 ma high 35pf ? 0.98 3.96 0.19 1.21 0.67 3.69 3.96 2.60 2.75 7.32 7.59 ns 3.3 v pci per pci spec high 10pf 25 2 0.98 2.0 20.190.750.672.061.542.432.875.695.17 ns 3.3 v pci-x per pci-x spec high 10pf 25 2 0.98 2.02 0.19 0.72 0.67 2.06 1.54 2.43 2.87 5.69 5.17 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 3-10 on page 3-55 for connectivity. this resistor is not required during normal operation. table 3-30 ? summary of i/o timing characteristics?software de fault settings, std. speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v applicable standard i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) units 3.3 v lvttl / 3.3 v lvcmos 8 ma high 35 pf ? 0.982.180.190.850.672.221.762.012.32 ns 2.5 v lvcmos 8 ma high 35pf ? 0.98 2.22 0.19 1.07 0.67 2.26 2.03 2.00 2.20 ns 1.8 v lvcmos 4 ma high 35pf ? 0.98 5.07 0.19 1.00 0.67 4.36 5.07 2.02 2.12 ns 1.5 v lvcmos 2 ma high 35pf ? 0.98 6.08 0.19 1.17 0.67 5.08 6.08 2.05 2.08 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. 2. resistance is used to measure i/o propagati on delays as defined in pci specifications. see figure 3-10 on page 3-55 for connectivity. this resistor is not required during normal operation.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-23 table 3-31 ? summary of i/o timing characteristics?software de fault settings, std. speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.14 v, worst case v cci = 3.0 v applicable advanced i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 1.57 3.57 0.26 0.98 1.11 3.64 2.97 3.23 3.92 9.45 8.78 ns 2.5 v lvcmos 12 ma high 35pf ? 1.57 3.56 0.26 1.20 1.11 3.63 3.39 3.28 3.77 9.44 9.20 ns 1.8 v lvcmos 12 ma high 35pf ? 1.57 3.47 0.26 1.11 1.11 3.53 3.05 3.56 4.17 9.34 8.85 ns 1.5 v lvcmos 12 ma high 35pf ? 1.57 3.85 0.26 1.27 1.11 3.92 3.45 3.74 4.21 9.73 9.26 ns 3.3 v pci per pci spec high 10pf 25 2 1.57 2.90 0.26 0.86 1.11 2.95 2.29 3.23 3.92 8.76 8.10 ns 3.3 v pci-x per pci- x spec high 10pf 25 2 1.57 2.90 0.26 0.86 1.11 2.95 2.29 3.23 3.92 8.76 8.10 ns lvds 24 ma high ? ? 1.57 2.19 0.26 1.52 ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 1.57 2.24 0.26 1.37 ? ? ? ? ? ? ? ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. 2. resistance is used to measure i/o propagatio n delays as defined in pci specifications. see figure 3-10 on page 3-55 for connectivity. this resistor is not required during normal operation.
igloo low-power flash fpgas wi th flash*freeze technology 3-24 advanced v0.1 table 3-32 ? summary of i/o timing characteristics?software de fault settings, std. speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.14 v, worst case v cci = 3.0 v applicable standard plus i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 1.57 3.19 0.26 0.97 1.11 3.25 2.66 2.91 3.62 9.06 8.46 ns 2.5 v lvcmos 12 ma high 35pf ? 1.57 3.20 0.26 1.20 1.11 3.25 3.04 2.92 3.50 9.06 8.85 ns 1.8 v lvcmos 8 ma high 35pf ? 1.57 3.71 0.26 1.11 1.11 3.60 3.71 2.98 3.38 9.41 9.52 ns 1.5 v lvcmos 4 ma high 35pf ? 1.57 4.30 0. 26 1.27 1.11 4.06 4.30 3.05 3.36 9.87 10.1 1 ns 3.3 v pci per pci spec high 10pf 25 2 1.57 2.52 0.26 0.85 1.11 2.57 1.98 2.91 3.62 8.37 7.78 ns 3.3 v pci-x per pci- x spec high 10pf 25 2 1.57 2.52 0.26 0.85 1.11 2.57 1.98 2.91 3.62 8.37 7.78 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. 2. resistance is used to measure i/o propagatio n delays as defined in pci specifications. see figure 3-10 on page 3-55 for connectivity. this resistor is not required during normal operation. table 3-33 ? summary of i/o timing characteristics?software de fault settings, std. speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.14 v, worst case v cci = 3.0 v applicable standard i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) units 3.3 v lvttl / 3.3 v lvcmos 8 ma high 35 pf ? 1.572.660.260.941.112.712.182.392.94 ns 2.5 v lvcmos 8 ma high 35pf ? 1.57 2.66 0.26 1.15 1.11 2.71 2.42 2.37 2.79 ns 1.8 v lvcmos 4 ma high 35pf ? 1.57 5.42 0.26 1.08 1.11 4.72 5.42 2.37 2.61 ns 1.5 v lvcmos 2 ma high 35pf ? 1.57 6.41 0.26 1.22 1.11 5.41 6.41 2.39 2.54 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. 2. resistance is used to measure i/o propagati on delays as defined in pci specifications. see figure 3-10 on page 3-55 for connectivity. this resistor is not required during normal operation.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-25 detailed i/o dc characteristics table 3-34 ? input capacitance symbol definition conditions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 3-35 ? i/o output buffer maximum resistances 1 applicable to advanced i/o banks standard drive strength r pull-down r pull-up ( ) 2 ( ) 3 3.3 v lvttl/ 3.3v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3v pci/pci-x per pci/pci-x specification 25 75 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and proce ss. for board design considerations and de tailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/downl oad/ibis/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
igloo low-power flash fpgas wi th flash*freeze technology 3-26 advanced v0.1 table 3-36 ? i/o output buffer maximum resistances 1 applicable to standard plus i/o banks standard drive strength rpull-down rpull-up ( ) 2 ( ) 3 3.3 v lvttl/ 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 25 75 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 3.3 v pci/pci-x per pci/pci-x specification 0 0 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and proce ss. for board design considerations and de tailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/downl oad/ibis/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-27 table 3-37 ? i/o output buffer maximum resistances 1 applicable to standard i/o banks standard drive strength r pull-down r pull-up ( ) 2 ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 2.5v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8v lvcmos 2 ma 200 225 4 ma 100 112 1.5v lvcmos 2 ma 200 224 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and proce ss. for board design considerations and de tailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/downl oad/ibis/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec table 3-38 ? i/o weak pull-up/pull-down resistances minimum and maximum we ak pull-up/pull-down resistance values v cci r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (v olspec ) / i (weak pull-up-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min)
igloo low-power flash fpgas wi th flash*freeze technology 3-28 advanced v0.1 table 3-39 ? i/o short currents i osh /i osl applicable to advanced i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 12 ma 74 65 16 ma 87 83 24 ma 124 169 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 51 45 12 ma 74 91 16 ma 74 91 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 6 ma 39 32 8 ma 55 66 12 ma 55 66 3.3 v pci/pci-x per pci/pci-x specification 109 103 note: *t j = 100c
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-29 table 3-40 ? i/o short currents i osh /i osl applicable to standard plus i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 109 103 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 12 ma 74 65 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 44 35 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 3.3 v pci/pci-x per pci/pci-x specification 109 103 note: *t j = 100c table 3-41 ? i/o short currents i osh /i osl applicable to standard i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 1.5 v lvcmos 2 ma 16 13 note: *t j = 100c
igloo low-power flash fpgas wi th flash*freeze technology 3-30 advanced v0.1 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, whic h is the worst case for this type of analysis. for example, at 110c, the short current condition would have to be sustained for more than three months to cause a reliability concern. the i/o design does not contain any short circuit protecti on, but such protec tion would only be needed in extremely prol onged stress conditions. table 3-42 ? short current event duration before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months 110c 3 months table 3-43 ? i/o input rise time, fall ti me, and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns * 20 years (110c) lvds/blvds.m-lvds/lvpecl no requirement 10 ns * 10 years (100c) note: *the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the ri se time and fall time of input buffers ca n be increased beyond the maximum value. the lo nger the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/charac terization of the system to ensure that there is no excessive noise coupling into input signals.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-31 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general purpose standard (eia/jesd) fo r 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 3-44 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 3-45 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
igloo low-power flash fpgas wi th flash*freeze technology 3-32 advanced v0.1 table 3-46 ? minimum and maximum dc input and output levels applicable to standard i/o banks 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-6 ? ac loading table 3-47 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.435 note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-33 timing characteristics applies to 1.5 v dc core voltage table 3-48 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 8.32 0.19 0.87 0.67 8.48 7.20 2.30 2.25 12.11 10.83 ns 6 ma std. 0.98 6.01 0.19 0.87 0.67 6. 12 5.19 2.56 2.70 9.75 8.82 ns 8 ma std. 0.98 6.01 0.19 0.87 0.67 6. 12 5.19 2.56 2.70 9.75 8.82 ns 12 ma std. 0.98 4.69 0.19 0.87 0.67 4. 77 4.11 2.74 2.99 8.40 7.74 ns 16 ma std. 0.98 4.40 0.19 0.87 0.67 4. 48 3.87 2.77 3.07 8.11 7.50 ns 24 ma std. 0.98 4.11 0.19 0.87 0.67 4. 19 3.86 2.82 3.36 7.82 7.49 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-49 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 6.25 0.19 0.87 0.67 6. 36 5.41 2.31 2.38 9.99 9.04 ns 6 ma std. 0.98 4.12 0.19 0.87 0.67 4. 19 3.46 2.57 2.84 7.82 7.09 ns 8 ma std. 0.98 4.12 0.19 0.87 0.67 4. 19 3.46 2.57 2.84 7.82 7.09 ns 12 ma std. 0.98 3.05 0.19 0.87 0.67 3.11 2.49 2.74 3.13 6.74 6.12 ns 16 ma std. 0.98 2.90 0.19 0.87 0.67 2. 95 2.29 2.78 3.20 6.58 5.92 ns 24 ma std. 0.98 2.70 0.19 0.87 0.67 2.75 1.95 2.83 3.50 6.38 5.58 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-50 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 7.78 0.19 0.87 0.67 7.92 6.75 2.03 2.08 11.55 10.38 ns 6 ma std. 0.98 5.47 0.19 0.87 0.67 5.58 4.80 2.27 2.49 9.21 8.43 ns 8 ma std. 0.98 5.47 0.19 0.87 0.67 5. 58 4.80 2.27 2.49 9.21 8.43 ns 12 ma std. 0.98 4.19 0.19 0.87 0.67 4. 27 3.74 2.43 2.75 7.90 7.37 ns 16 ma std. 0.98 4.19 0.19 0.87 0.67 4. 27 3.74 2.43 2.75 7.90 7.37 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-34 advanced v0.1 table 3-51 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 5.82 0.19 0.87 0.67 5. 92 5.08 2.03 2.19 9.55 8.71 ns 6 ma std. 0.98 3.72 0.19 0.87 0.67 3. 79 3.17 2.26 2.60 7.42 6.80 ns 8 ma std. 0.98 3.72 0.19 0.87 0.67 3. 79 3.17 2.26 2.60 7.42 6.80 ns 12 ma std. 0.98 2.69 0.19 0.87 0.67 2.74 2.22 2.43 2.87 6.37 5.85 ns 16 ma std. 0.98 2.69 0.19 0.87 0.67 2. 74 2.22 2.43 2.87 6.37 5.85 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-52 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 4.52 0.19 0.85 0. 67 4.60 4.03 1.79 1.83 ns 4 ma std. 0.98 4.52 0.19 0.85 0. 67 4.60 4.03 1.79 1.83 ns 6 ma std. 0.98 3.59 0.19 0.85 0. 67 3.66 3.30 2.01 2.23 ns 8 ma std. 0.98 3.59 0.19 0.85 0. 67 3.66 3.30 2.01 2.23 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-53 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 2.82 0.19 0.85 0. 67 2.87 2.36 1.78 1.92 ns 4 ma std. 0.98 2.82 0.19 0.85 0. 67 2.87 2.36 1.78 1.92 ns 6 ma std. 0.98 2.18 0.19 0.85 0. 67 2.22 1.76 2.01 2.32 ns 8 ma std. 0.98 2.18 0.19 0.85 0.67 2.22 1.76 2.01 2.32 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-35 applies to 1.2 v dc core voltage table 3-54 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 8.84 0.26 0.98 1.11 9.01 7.68 2.80 3.01 14.82 13.49 ns 6 ma std. 1.57 6.53 0.26 0.98 1.11 6.65 5.67 3.05 3.46 12.46 11.48 ns 8 ma std. 1.57 6.53 0.26 0.98 1.11 6.65 5.67 3.05 3.46 12.46 11.48 ns 12 ma std. 1.57 5.21 0.26 0.98 1.11 5.31 4.59 3.23 3.75 11.12 10.40 ns 16 ma std. 1.57 4.92 0.26 0.98 1.11 5.01 4.36 3.27 3.83 10.82 10.16 ns 24 ma std. 1.57 4.64 0.26 0.98 1.11 4.72 4.34 3.31 4.12 10.53 10.15 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-55 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 6.76 0.26 0.98 1.11 6.89 5.89 2.80 3.16 12.70 11.70 ns 6 ma std. 1.57 4.63 0.26 0.98 1.11 4.72 3.94 3.06 3.62 10.53 9.75 ns 8 ma std. 1.57 4.63 0.26 0.98 1.11 4.72 3.94 3.06 3.62 10.53 9.75 ns 12 ma std. 1.57 3.57 0.26 0.98 1.11 3.64 2.97 3.23 3.92 9.45 8.78 ns 16 ma std. 1.57 3.41 0.26 0.98 1.11 3. 48 2.77 3.27 3.99 9.29 8.57 ns 24 ma std. 1.57 3.22 0.26 0.98 1.11 3. 28 2.43 3.32 4.29 9.09 8.23 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-56 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 8.28 0.26 0.97 1.11 8.43 7.18 2.52 2.81 14.24 12.99 ns 6 ma std. 1.57 5.98 0.26 0.97 1.11 6.09 5.23 2.75 3.22 11.89 11.04 ns 8 ma std. 1.57 5.98 0.26 0.97 1.11 6.09 5.23 2.75 3.22 11.89 11.04 ns 12 ma std. 1.57 4.69 0.26 0.97 1.11 4.78 4.18 2.92 3.49 10.59 9.98 ns 16 ma std. 1.57 4.69 0.26 0.97 1.11 4.78 4.18 2.92 3.49 10.59 9.98 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-36 advanced v0.1 table 3-57 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 6.32 0.26 0.97 1.11 6.43 5.52 2.52 2.94 12.24 11.33 ns 6 ma std. 1.57 4.22 0.26 0.97 1.11 4.30 3.61 2.75 3.36 10.11 9.42 ns 8 ma std. 1.57 4.22 0.26 0.97 1.11 4.30 3.61 2.75 3.36 10.11 9.42 ns 12 ma std. 1.57 3.19 0.26 0.97 1.11 3.25 2.66 2.91 3.62 9.06 8.46 ns 16 ma std. 1.57 3.19 0.26 0.97 1.11 3. 25 2.66 2.91 3.62 9.06 8.46 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-58 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 5.00 0.26 0.94 1. 11 5.09 4.45 2.16 2.43 ns 4 ma std. 1.57 5.00 0.26 0.94 1. 11 5.09 4.45 2.16 2.43 ns 6 ma std. 1.57 4.07 0.26 0.94 1. 11 4.14 3.72 2.39 2.83 ns 8 ma std. 1.57 4.07 0.26 0.94 1. 11 4.14 3.72 2.39 2.83 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-59 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 3.29 0.26 0.94 1. 11 3.35 2.78 2.16 2.54 ns 4 ma std. 1.57 3.29 0.26 0.94 1. 11 3.35 2.78 2.16 2.54 ns 6 ma std. 1.57 2.66 0.26 0.94 1. 11 2.71 2.18 2.39 2.94 ns 8 ma std. 1.57 2.66 0.26 0.94 1.11 2.71 2.18 2.39 2.94 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-37 2.5 v lvcmos low-voltage cmos for 2.5 v is an ex tension of the lvcmos standard (jesd8-5) used for general purpose 2.5 v applications. it uses a 5 v?tolerant in put buffer and push-pull output buffer. table 3-60 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 3-61 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
igloo low-power flash fpgas wi th flash*freeze technology 3-38 advanced v0.1 table 3-62 ? minimum and maximum dc input and output levels applicable to standard i/o banks 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-7 ? ac loading table 3-63 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.235 note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-39 timing characteristics applies to 1.5 v dc core voltage table 3-64 ? 2.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 9.12 0.19 1.10 0.67 9.10 9.12 2.33 2.05 12.73 12.75 ns 6 ma std. 0.98 6.56 0.19 1.10 0.67 6.68 6.37 2.61 2.58 10.31 10.00 ns 8 ma std. 0.98 6.56 0.19 1.10 0.67 6.68 6.37 2.61 2.58 10.31 10.00 ns 12 ma std. 0.98 5.16 0.19 1.10 0.67 5. 26 4.91 2.81 2.91 8.89 8.54 ns 16 ma std. 0.98 4.83 0.19 1.10 0.67 4. 92 4.61 2.85 3.00 8.55 8.24 ns 24 ma std. 0.98 4.60 0.19 1.10 0.67 4. 64 4.60 2.91 3.34 8.27 8.23 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-65 ? 2.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 7.02 0.19 1.10 0.67 6.40 7.02 2.33 2.13 10.03 10.65 ns 6 ma std. 0.98 4.31 0.19 1.10 0.67 4. 23 4.31 2.61 2.67 7.86 7.94 ns 8 ma std. 0.98 4.31 0.19 1.10 0.67 4. 23 4.31 2.61 2.67 7.86 7.94 ns 12 ma std. 0.98 3.08 0.19 1.10 0.67 3.14 2.96 2.81 3.01 6.77 6.59 ns 16 ma std. 0.98 2.92 0.19 1.10 0.67 2. 97 2.68 2.85 3.10 6.60 6.31 ns 24 ma std. 0.98 2.72 0.19 1.10 0.67 2. 77 2.19 2.91 3.45 6.40 5.82 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-66 ? 2.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 8.62 0.19 1.11 0.67 8.53 8.62 2.01 1.90 12.16 12.25 ns 6 ma std. 0.98 5.99 0.19 1.11 0.67 6. 10 5.93 2.27 2.38 9.73 9.56 ns 8 ma std. 0.98 5.99 0.19 1.11 0.67 6. 10 5.93 2.27 2.38 9.73 9.56 ns 12 ma std. 0.98 4.64 0.19 1.11 0.67 4. 72 4.51 2.45 2.68 8.35 8.14 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-40 advanced v0.1 table 3-67 ? 2.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.98 6.63 0.19 1.11 0.67 5. 97 6.63 2.01 1.97 9.60 10.26 ns 6 ma std. 0.98 3.97 0.19 1.11 0.67 3. 83 3.97 2.27 2.46 7.46 7.60 ns 8 ma std. 0.98 3.97 0.19 1.11 0.67 3. 83 3.97 2.27 2.46 7.46 7.60 ns 12 ma std. 0.98 2.72 0.19 1.11 0.67 2.77 2.65 2.45 2.77 6.40 6.28 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-68 ? 2.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 5.03 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns 4 ma std. 0.98 5.03 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns 6 ma std. 0.98 4.01 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns 8 ma std. 0.98 4.01 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-69 ? 2.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 2.87 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns 4 ma std. 0.98 2.87 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns 6 ma std. 0.98 2.22 0.19 1.07 0. 67 2.26 2.03 2.00 2.20 ns 8 ma std. 0.98 2.22 0.19 1.07 0.67 2.26 2.03 2.00 2.20 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-41 applies to 1.2 v core voltage table 3-70 ? 2.5 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 9.56 0.26 1.20 1.11 9.60 9.56 2.80 2.78 15.40 15.37 ns 6 ma std. 1.57 7.04 0.26 1.20 1.11 7.17 6.80 3.09 3.31 12.98 12.61 ns 8 ma std. 1.57 7.04 0.26 1.20 1.11 7.17 6.80 3.09 3.31 12.98 12.61 ns 12 ma std. 1.57 5.65 0.26 1.20 1.11 5.75 5.35 3.28 3.65 11.56 11.15 ns 16 ma std. 1.57 5.32 0.26 1.20 1.11 5.42 5.04 3.33 3.74 11.22 10.85 ns 24 ma std. 1.57 5.04 0.26 1.20 1.11 5.13 5.03 3.38 4.07 10.94 10.84 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-71 ? 2.5 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 7.45 0.26 1.20 1.11 6.89 7.45 2.80 2.89 12.69 13.26 ns 6 ma std. 1.57 4.74 0.26 1.20 1.11 4.72 4.74 3.09 3.43 10.52 10.55 ns 8 ma std. 1.57 4.74 0.26 1.20 1.11 4.72 4.74 3.09 3.43 10.52 10.55 ns 12 ma std. 1.57 3.56 0.26 1.20 1.11 3.63 3.39 3.28 3.77 9.44 9.20 ns 16 ma std. 1.57 3.40 0.26 1.20 1.11 3. 46 3.10 3.33 3.86 9.27 8.91 ns 24 ma std. 1.57 3.20 0.26 1.20 1.11 3. 26 2.62 3.39 4.21 9.07 8.43 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-72 ? 2.5 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 9.01 0.26 1.20 1.11 9.01 9.01 2.49 2.60 14.82 14.82 ns 6 ma std. 1.57 6.47 0.26 1.20 1.11 6.59 6.32 2.74 3.08 12.39 12.13 ns 8 ma std. 1.57 6.47 0.26 1.20 1.11 6.59 6.32 2.74 3.08 12.39 12.13 ns 12 ma std. 1.57 5.11 0.26 1.20 1.11 5.21 4.90 2.92 3.39 11.01 10.71 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-42 advanced v0.1 table 3-73 ? 2.5 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 1.57 7.02 0.26 1.20 1.11 6.45 7.02 2.48 2.70 12.26 12.83 ns 6 ma std. 1.57 4.36 0.26 1.20 1.11 4.32 4.36 2.74 3.19 10.12 10.17 ns 8 ma std. 1.57 4.36 0.26 1.20 1.11 4.32 4.36 2.74 3.19 10.12 10.17 ns 12 ma std. 1.57 3.20 0.26 1.20 1.11 3.25 3.04 2.92 3.50 9.06 8.85 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-74 ? 2.5 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 5.47 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns 4 ma std. 1.57 5.47 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns 6 ma std. 1.57 4.46 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns 8 ma std. 1.57 4.46 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-75 ? 2.5 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 3.31 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns 4 ma std. 1.57 3.31 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns 6 ma std. 1.57 2.66 0.26 1.15 1. 11 2.71 2.42 2.37 2.79 ns 8 ma std. 1.57 2.66 0.26 1.15 1.11 2.71 2.42 2.37 2.79 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-43 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 3-76 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 16 16 74 91 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 3-77 ? minimum and maximum dc input and output levels applicable to standard plus i/o i/o banks 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 44 35 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
igloo low-power flash fpgas wi th flash*freeze technology 3-44 advanced v0.1 table 3-78 ? minimum and maximum dc input and output levels applicable to standard i/o banks 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 17 22 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-8 ? ac loading table 3-79 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.935 note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-45 timing characteristics 1.5 v dc core voltage table 3-80 ? 1.8 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 12.31 0.19 1.10 0.67 11.39 12.31 2.40 1.61 15.02 15.94 ns 4 ma std. 0.98 8.42 0.19 1.10 0.67 8.47 8.42 2.74 2.45 12.10 12.05 ns 6 ma std. 0.98 6.61 0.19 1.10 0.67 6.73 6.39 2.98 2.86 10.36 10.02 ns 8 ma std. 0.98 6.18 0.19 1.10 0.67 6. 29 5.98 3.03 2.97 9.92 9.61 ns 12 ma std. 0.98 5.98 0.19 1.10 0.67 5. 98 5.98 3.11 3.39 9.61 9.61 ns 16 ma std. 0.98 5.98 0.19 1.10 0.67 5. 98 5.98 3.11 3.39 9.61 9.61 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-81 ? 1.8 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 9.50 0.19 1.03 0.67 7.42 9.50 2.39 1.65 11.05 13.13 ns 4 ma std. 0.98 5.66 0.19 1.03 0.67 4. 85 5.66 2.74 2.53 8.48 9.29 ns 6 ma std. 0.98 3.75 0.19 1.03 0.67 3. 56 3.75 2.98 2.95 7.19 7.38 ns 8 ma std. 0.98 3.34 0.19 1.03 0.67 3. 36 3.34 3.03 3.06 6.99 6.97 ns 12 ma std. 0.98 3.05 0.19 1.03 0.67 3.11 2.65 3.11 3.49 6.74 6.28 ns 16 ma std. 0.98 3.05 0.19 1.03 0.67 3. 11 2.65 3.11 3.49 6.74 6.28 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-82 ? 1.8 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 11.68 0.19 1.11 0.67 10.76 11.68 2.00 1.51 14.39 15.31 ns 4 ma std. 0.98 7.89 0.19 1.11 0.67 7.81 7.89 2.31 2.27 11.44 11.52 ns 6 ma std. 0.98 6.02 0.19 1.11 0.67 6. 13 5.91 2.53 2.65 9.76 9.54 ns 8 ma std. 0.98 6.02 0.19 1.11 0.67 6. 13 5.91 2.53 2.65 9.76 9.54 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-46 advanced v0.1 table 3-83 ? 1.8 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 9.00 0.19 1.04 0.67 6.99 9.00 2.00 1.55 10.62 12.63 ns 4 ma std. 0.98 5.23 0.19 1.04 0.67 4. 46 5.23 2.31 2.35 8.09 8.86 ns 6 ma std. 0.98 3.35 0.19 1.04 0.67 3. 20 3.35 2.53 2.74 6.83 6.98 ns 8 ma std. 0.98 3.35 0.19 1.04 0.67 3.20 3.35 2.53 2.74 6.83 6.98 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-84 ? 1.8 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 11.67 0.19 1.00 0.67 10.55 11.67 1.72 1.28 ns 4 ma std. 0.98 7.89 0.19 1.00 0. 67 7.74 7.89 2.02 2.04 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-85 ? 1.8 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 8.83 0.19 1.00 0. 67 6.81 8.83 1.72 1.33 ns 4 ma std. 0.98 5.07 0.19 1.00 0.67 4.36 5.07 2.02 2.12 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-47 1.2 v dc core voltage table 3-86 ? 1.8 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 12.71 0.26 1.20 1.11 11.80 12.71 2.85 2.27 17.60 18.52 ns 4 ma std. 1.57 8.81 0.26 1.20 1.11 8.88 8.81 3.20 3.12 14.68 14.62 ns 6 ma std. 1.57 7.01 0.26 1.20 1.11 7.14 6.79 3.44 3.54 12.95 12.60 ns 8 ma std. 1.57 6.58 0.26 1.20 1.11 6.70 6.37 3.49 3.65 12.51 12.18 ns 12 ma std. 1.57 6.37 0.26 1.20 1.11 6.39 6.37 3.57 4.06 12.20 12.18 ns 16 ma std. 1.57 6.37 0.26 1.20 1.11 6.39 6.37 3.57 4.06 12.20 12.18 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-87 ? 1.8 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 9.90 0.26 1.11 1.11 7.84 9.90 2.85 2.32 13.65 15.71 ns 4 ma std. 1.57 6.06 0.26 1.11 1.11 5.28 6.06 3.19 3.21 11.08 11.86 ns 6 ma std. 1.57 4.14 0.26 1.11 1.11 3. 98 4.14 3.43 3.63 9.79 9.95 ns 8 ma std. 1.57 3.73 0.26 1.11 1.11 3. 79 3.73 3.49 3.74 9.59 9.54 ns 12 ma std. 1.57 3.47 0.26 1.11 1.11 3.53 3.05 3.56 4.17 9.34 8.85 ns 16 ma std. 1.57 3.47 0.26 1.11 1.11 3. 53 3.05 3.56 4.17 9.34 8.85 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-88 ? 1.8 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 12.03 0.26 1.20 1.11 11.14 12.03 2.46 2.14 16.94 17.84 ns 4 ma std. 1.57 8.24 0.26 1.20 1.11 8.19 8.24 2.77 2.91 14.00 14.05 ns 6 ma std. 1.57 6.39 0.26 1.20 1.11 6.51 6.26 2.98 3.29 12.32 12.07 ns 8 ma std. 1.57 6.39 0.26 1.20 1.11 6.51 6.26 2.98 3.29 12.32 12.07 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-48 advanced v0.1 table 3-89 ? 1.8 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 9.35 0.26 1.11 1.11 7.39 9.35 2.45 2.18 13.20 15.16 ns 4 ma std. 1.57 5.59 0.26 1.11 1.11 4.86 5.59 2.76 2.99 10.67 11.40 ns 6 ma std. 1.57 3.71 0.26 1.11 1.11 3. 60 3.71 2.98 3.38 9.41 9.52 ns 8 ma std. 1.57 3.71 0.26 1.11 1.11 3.60 3.71 2.98 3.38 9.41 9.52 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-90 ? 1.8 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 12.02 0.26 1.08 1.11 10.90 12.02 2.07 1.77 ns 4 ma std. 1.57 8.24 0.26 1.08 1. 11 8.09 8.24 2.37 2.53 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-91 ? 1.8 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 9.18 0.26 1.08 1. 11 7.17 9.18 2.07 1.81 ns 4 ma std. 1.57 5.42 0.26 1.08 1.11 4.72 5.42 2.37 2.61 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-49 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an ex tension of the lvcmos standard (jesd8-5) used for general-purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 3-92 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 16 13 10 10 4 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 33 25 10 10 6 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 6 6 39 32 10 10 8 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 8 8 55 66 10 10 12 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 12 12 55 66 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 3-93 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 0 0 10 10 4 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 0 0 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 3-94 ? minimum and maximum dc input and output levels applicable to standard i/o banks 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 13 16 10 10 notes: 1. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray.
igloo low-power flash fpgas wi th flash*freeze technology 3-50 advanced v0.1 figure 3-9 ? ac loading table 3-95 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 1.5 0.75 35 note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-51 timing characteristics 1.5 v dc core voltage table 3-96 ? 1.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 10.20 0.19 1.10 0.67 10.34 10.20 2.87 2.37 13.97 13.83 ns 4 ma std. 0.98 8.14 0.19 1.10 0.67 8.29 7.71 3.14 2.85 11.92 11.34 ns 6 ma std. 0.98 7.61 0.19 1.10 0.67 7.75 7.21 3.20 2.98 11.38 10.84 ns 8 ma std. 0.98 7.27 0.19 1.10 0.67 7.40 7.21 3.30 3.46 11.03 10.84 ns 12 ma std. 0.98 7.27 0.19 1.10 0.67 7.40 7.21 3.30 3.46 11.03 10.84 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-97 ? 1.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 6.79 0.19 1.20 0.67 5. 60 6.79 2.86 2.47 9.23 10.42 ns 4 ma std. 0.98 4.42 0.19 1.20 0.67 4. 07 4.42 3.14 2.96 7.70 8.05 ns 6 ma std. 0.98 3.72 0.19 1.20 0.67 3. 68 3.72 3.14 3.08 7.31 7.35 ns 8 ma std. 0.98 3.47 0.19 1.20 0.67 3. 54 3.07 3.29 3.58 7.17 6.70 ns 12 ma std. 0.98 3.47 0.19 1.20 0.67 3.54 3.07 3.29 3.58 7.17 6.70 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-98 ? 1.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 9.58 0.19 1.11 0.67 9.58 9.58 2.36 2.21 13.21 13.21 ns 4 ma std. 0.98 7.44 0.19 1.11 0.67 7. 58 7.15 2.61 2.65 11.21 10.78 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-52 advanced v0.1 table 3-99 ? 1.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.98 6.28 0.19 1.21 0.67 5. 18 6.28 2.35 2.30 8.81 9.91 ns 4 ma std. 0.98 3.96 0.19 1.21 0.67 3.69 3.96 2.60 2.75 7.32 7.59 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-100 ? 1.5 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 9.60 0.19 1.17 0. 67 9.53 9.60 2.05 1.99 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-101 ? 1.5 v lvcmos high slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.98 6.08 0.19 1.17 0.67 5.08 6.08 2.05 2.08 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-53 1.2 v dc core voltage table 3-102 ? 1.5 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 10.59 0.26 1.20 1.11 10.70 10.59 3.32 3.01 16.51 16.39 ns 4 ma std. 1.57 8.49 0.26 1.20 1.11 8.64 8.09 3.59 3.49 14.45 13.90 ns 6 ma std. 1.57 7.96 0.26 1.20 1.11 8.10 7.59 3.65 3.62 13.91 13.39 ns 8 ma std. 1.57 7.62 0.26 1.20 1.11 7.76 7.59 3.75 4.10 13.57 13.40 ns 12 ma std. 1.57 7.62 0.26 1.20 1.11 7.76 7.59 3.75 4.10 13.57 13.40 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-103 ? 1.5 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 7.17 0.26 1.27 1.11 5.98 7.17 3.31 3.10 11.79 12.97 ns 4 ma std. 1.57 4.80 0.26 1.27 1.11 4.46 4.80 3.58 3.59 10.27 10.61 ns 6 ma std. 1.57 4.10 0.26 1.27 1.11 4. 06 4.10 3.59 3.72 9.87 9.91 ns 8 ma std. 1.57 3.85 0.26 1.27 1.11 3. 92 3.45 3.74 4.21 9.73 9.26 ns 12 ma std. 1.57 3.85 0.26 1.27 1.11 3.92 3.45 3.74 4.21 9.73 9.26 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-104 ? 1.5 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 9.92 0.26 1.20 1.11 9.91 9.92 2.81 2.81 15.72 15.73 ns 4 ma std. 1.57 7.77 0.26 1.20 1.11 7.92 7.49 3.06 3.25 13.73 13.30 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-54 advanced v0.1 table 3-105 ? 1.5 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v applicable to standard plus banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 1.57 6.62 0.26 1.27 1.11 5.55 6.62 2.80 2.90 11.36 12.43 ns 4 ma std. 1.57 4.30 0.26 1.27 1.11 4.06 4.30 3.05 3.36 9.87 10.11 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-106 ? 1.5 v lcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 9.93 0.26 1.22 1. 11 9.83 9.93 2.39 2.45 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-107 ? 1.5 v lcmos high slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v applicable to standard banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 1.57 6.41 0.26 1.22 1.11 5.41 6.41 2.39 2.54 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-55 3.3 v pci, 3.3 v pci-x peripheral component interfac e for 3.3 v standard specifies support fo r 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pci/p ci-x specifications for the datapath; actel loadings for enable path characterization are described in figure 3-10 . ac loadings are defined per pci/pci-x specifications for the datapath; actel loading fo r tristate is described in table 3- 110 . table 3-108 ? minimum and maximum dc input and output levels applicable to advanced and standard plus i/os 3.3 v pci/pci-x v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min, v ma ma max, ma 1 max, ma 1 a 2 a 2 per pci specification per pci curves 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. table 3-109 ? minimum and maximum dc input and output levels applicable to standard i/os 3.3 v pci/pci-x v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min, v ma ma max, ma 1 max, ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 13 16 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. figure 3-10 ? ac loading table 3-110 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 3.3 0.285 * v cci for t dp(r) 0.615 * v cci for t dp(f) 10 note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. test point enable path r to v for t /t /t cci lz zl zls 10 pf for t /t /t /t zh zhs zls zl 5 pf for t hz /t lz r to gnd for t /t /t hz zh zh s r = 1 k test point datapath r = 25 r to v cci for t dp (f) r to gnd for t dp (r)
igloo low-power flash fpgas wi th flash*freeze technology 3-56 advanced v0.1 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 3-111 ? 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.98 2.38 0.19 0.72 0.67 2.43 1.82 2.74 3.13 6.06 5.45 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-112 ? 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.98 2.02 0.19 0.72 0.67 2.06 1.54 2.43 2.87 5.69 5.17 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-113 ? 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 1.57 2.90 0.26 0.86 1.11 2.95 2.29 3.23 3.92 8.76 8.10 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-114 ? 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 1.57 2.52 0.26 0.85 1.11 2.57 1.98 2.91 3.62 8.37 7.78 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-57 differential i/o characteristics physical implementation configuration of th e i/o modules as a differential pair is handled by actel designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjunction with the embedded input register (inreg), output register (outreg), enable register (enreg), and double data rate (ddr). however, there is no support for bidirectional i/os or tristates with the lvpecl standards. lvds low-voltage differential si gnaling (ansi/tia/eia-644) is a high-speed, differential i/o standard. it requires that one data bit be carried through two signal lines, so two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitter and receiver is shown in an example in figure 3-11 . the building blocks of the lvds transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvpecl implementation because the output standard specifications are different. along with lvds i/o, igloo also supports bus lvds structure and multipoint lvds (m-lvds) configuration (up to 40 nodes). figure 3-11 ? lvds circuit diagram and board-level implementation table 3-115 ? minimum and maximum dc input and output levels dc parameter description min. typ. max. units v cci supply voltage 2.375 2.5 2.625 v v ol output low voltage 0.9 1.075 1.25 v v oh output high voltage 1.25 1.425 1.6 v v i input voltage 0 ? 2.925 v v odiff differential output voltage 250 350 450 mv v ocm output common-mode voltage 1.125 1.25 1.375 v v icm input common-mode voltage 0.05 1.25 2.35 v v idiff input differential voltage 100 350 ? mv notes: 1. 5% 2. differential input voltage = 350 mv table 3-116 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.075 1.325 cross point note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. 140 100 zo = 50 zo = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12
igloo low-power flash fpgas wi th flash*freeze technology 3-58 advanced v0.1 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage blvds/m-lvds bus lvds (blvds) and multipoint lvds (m-lvds) specifications extend the exi sting lvds standard to high- performance multipoint bus applications. multidrop and multipoint bus configurations may contain any combination of drivers, receiv ers, and transce ivers. actel lvds drivers provide the hi gher drive current required by blvds and m-lvds to acco mmodate the loading. the drivers require series termina tions for better signal quality and to control voltage swing. termination is also required at both ends of the bus since the driver can be located anywhere on the bus. these configurations can be implemented using the tr ibuf_lvds and bibuf_lvds macros along with appropria te terminations. multipoint designs using actel lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sample application is given in figure 3-12 . the input and output buffer delays are available in the lvds section in table 3- 117 and table 3-118 . example: for a bus consisting of 20 equidistant loads, the following terminations provid e the required differential voltage, in worst-case indust rial operating conditions, at the farthest receiver: r s =60 and r t =70 , given z 0 =50 (2") and z stub =50 (~1.5"). table 3-117 ? lvds ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard banks speed grade t dout t dp t din t py units std. 0.98 1.72 0.19 1.35 ns note: for specific junction temperature and voltage supply levels, refer to table 3-6 on page 3-6 and table 3-7 on page 3-6 for derating values. table 3-118 ? lvds ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v applicable to standard banks speed grade t dout t dp t din t py units std. 1.57 2.19 0.26 1.52 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 and table 3-7 on page 3-6 for derating values. figure 3-12 ? blvds/m-lvds multipoint appl ication using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-59 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differential i/o standa rd. it requires that one data bit be carried through two signal lines. like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitter and receiver is shown in an example in figure 3-13 . the building blocks of the lvpec l transmitter-receiver are one transmitter macro, one re ceiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvds implementation because the output standard spec ifications are different. figure 3-13 ? lvpecl circuit diagram and board-level implementation table 3-119 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units v cci supply voltage 3.0 3.3 3.6 v v ol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v v oh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v v il , v ih input low, input high voltages 0 3.3 0 3.6 0 3.9 v v odiff differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 v v ocm output common-mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 v v icm input common-mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v v idiff input differential voltage 300 300 300 mv table 3-120 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.64 1.94 cross point note: *measuring point = v trip. see table 3-26 on page 3-20 for a complete table of trip points. 187 w 100 zo = 50 zo = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12
igloo low-power flash fpgas wi th flash*freeze technology 3-60 advanced v0.1 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 3-121 ? lvpecl ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard banks speed grade t dout t dp t din t py units std. 0.98 1.72 0.19 1.35 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-122 ? lvpecl ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v applicable to standard banks speed grade t dout t dp t din t py units std. 1.57 2.24 0.26 1.37 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-61 i/o register specifications fully registered i/o buffers with synchr onous enable and asynchronous preset figure 3-14 ? timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive edge triggered data output register and enable output register with: active high enable active high preset postive edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
igloo low-power flash fpgas wi th flash*freeze technology 3-62 advanced v0.1 table 3-123 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of th e output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the ou tput enable register j, h t oesue enable setup time for the ou tput enable register k, h t oehe enable hold time for the ou tput enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time fo r the output enable register i, h t oerecpre asynchronous preset recovery time for the output enab le register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 3-14 on page 3-61 for more information.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-63 fully registered i/o buffers with synchr onous enable and asynchronous clear figure 3-15 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enab le clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive edge triggered data output register and enable output register with active high enable active high clear positive edge triggered
igloo low-power flash fpgas wi th flash*freeze technology 3-64 advanced v0.1 table 3-124 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the output enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the output enable register kk, hh t oehe enable hold time for the ou tput enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time for the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa note: *see figure 3-15 on page 3-63 for more information.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-65 input register timing characteristics 1.5 v dc core voltage figure 3-16 ? input register timing diagram 50 % preset clear out_1 clk data enable t isue 50 % 50 % t isud t ihd 50 % 50 % t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 3-125 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t iclkq clock-to-q of the input data register 0.43 ns t isud data setup time for the input data register 0.47 ns t ihd data hold time for the input data register 0.00 ns t isue enable setup time for the input data register 0.67 ns t ihe enable hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.81 ns t ipre2q asynchronous preset-to-q of th e input data register 0.81 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.19 ns t ickmpwh clock minimum pulse width high fo r the input data register 0.31 ns t ickmpwl clock minimum pulse width low fo r the input data register 0.28 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-66 advanced v0.1 1.2 v dc core voltage table 3-126 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t iclkq clock-to-q of the input data register 0.70 ns t isud data setup time for the input data register 0.98 ns t ihd data hold time for the input data register 0.00 ns t isue enable setup time for the input data register 1.04 ns t ihe enable hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 1.22 ns t ipre2q asynchronous preset-to-q of th e input data register 1.22 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.19 ns t ickmpwh clock minimum pulse width high fo r the input data register 0.31 ns t ickmpwl clock minimum pulse width low fo r the input data register 0.28 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-67 output register timing characteristics 1.5 v dc core voltage figure 3-17 ? output register timing diagram preset clear dout clk data_out enable t osue 50 % 50 % t osud t ohd 50 % 50 % t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 3-127 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t oclkq clock-to-q of the output data register 1.02 ns t osud data setup time for the output data register 0.52 ns t ohd data hold time for the output data register 0.00 ns t osue enable setup time for the output data register 0.70 ns t ohe enable hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 1.37 ns t opre2q asynchronous preset-to-q of the output data register 1.37 ns t oremclr asynchronous clear removal time for the output data register 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 ns t owpre asynchronous preset minimum pulse width for the output data register 0.19 ns t ockmpwh clock minimum pulse width high for the output data register 0.31 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-68 advanced v0.1 1.2 v dc core voltage table 3-128 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t oclkq clock-to-q of the output data register 1.56 ns t osud data setup time for the output data register 1.17 ns t ohd data hold time for the output data register 0.00 ns t osue enable setup time for the output data register 1.13 ns t ohe enable hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 2.01 ns t opre2q asynchronous preset-to-q of the output data register 2.01 ns t oremclr asynchronous clear removal time for the output data register 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 ns t owpre asynchronous preset minimum pulse width for the output data register 0.19 ns t ockmpwh clock minimum pulse width high for the output data register 0.31 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-69 output enable register timing characteristics 1.5 v dc core voltage figure 3-18 ? output enable register timing diagram 50 % preset clear eout clk d_enable enable t oesue 50 % 50 % t oesud t oehd 50 % 50 % t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 3-129 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t oeclkq clock-to-q of the output enable register 0.77 ns t oesud data setup time for the ou tput enable register 0.52 ns t oehd data hold time for the output enable register 0.00 ns t oesue enable setup time for the ou tput enable register 0.74 ns t oehe enable hold time for the output enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 1.15 ns t oepre2q asynchronous preset-to-q of th e output enable register 1.15 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time fo r the output enable register 0.24 ns t oerempre asynchronous preset removal time for the output enable register 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-70 advanced v0.1 1.2 v dc core voltage table 3-130 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t oeclkq clock-to-q of the output enable register 1.13 ns t oesud data setup time for the ou tput enable register 1.17 ns t oehd data hold time for the output enable register 0.00 ns t oesue enable setup time for the ou tput enable register 1.24 ns t oehe enable hold time for the output enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 1.69 ns t oepre2q asynchronous preset-to-q of th e output enable register 1.69 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time fo r the output enable register 0.24 ns t oerempre asynchronous preset removal time for the output enable register 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-71 ddr module specifications input ddr module figure 3-19 ? input ddr timing model table 3-131 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
igloo low-power flash fpgas wi th flash*freeze technology 3-72 advanced v0.1 timing characteristics 1.5 v dc core voltage figure 3-20 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 3-132 ? input ddr prop agation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.49 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.66 ns t ddrisud data setup for input ddr 0.51 ns t ddrihd data hold for input ddr 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.83 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.99 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.24 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.19 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.31 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.28 ns f ddrimax maximum frequency for input ddr tbd mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-73 1.2 v dc core voltage table 3-133 ? input ddr prop agation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.78 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.96 ns t ddrisud data setup for input ddr 0.94 ns t ddrihd data hold for input ddr 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 1.25 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 1.44 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.24 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.19 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.31 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.28 ns f ddrimax maximum frequency for input ddr tbd mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-74 advanced v0.1 output ddr module figure 3-21 ? output ddr timing model table 3-134 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x x a b d e c c b outbuf data_r (from core)
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-75 timing characteristics 1.5 v dc core voltage figure 3-22 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 3-135 ? output ddr prop agation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t ddroclkq clock-to-out of ddr for output ddr 1.09 ns t ddrosud1 data_f data setup for output ddr 0.68 ns t ddrosud2 data_r data setup for output ddr 0.68 ns t ddrohd1 data_f data hold for output ddr 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 1.39 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.24 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.19 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.31 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.28 ns f ddomax maximum frequency for the output ddr tbd mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-76 advanced v0.1 1.2 v dc core voltage table 3-136 ? output ddr prop agation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t ddroclkq clock-to-out of ddr for output ddr 1.63 ns t ddrosud1 data_f data setup for output ddr 1.11 ns t ddrosud2 data_r data setup for output ddr 1.18 ns t ddrohd1 data_f data hold for output ddr 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 2.01 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.24 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.19 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.31 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.28 ns f ddomax maximum frequency for the output ddr tbd mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-77 versatile characteristics versatile specifications as a combinatorial module the igloo library offers all combinations of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the fusion, igloo/e and proasic3/e macro library guide . figure 3-23 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
igloo low-power flash fpgas wi th flash*freeze technology 3-78 advanced v0.1 figure 3-24 ? timing model and waveforms net a y b len g th = 1 versatile net a y b len g th = 1 versatile net a y b len g th = 1 versatile net a y b len g th = 1 versatile nand2 or any c om b inatorial lo g i c nand2 or any c om b inatorial lo g i c nand2 or any c om b inatorial lo g i c nand2 or any c om b inatorial lo g i c t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where e dg es are appli c a b le for a parti c ular c om b inatorial c ell fanout = 4 t pd t pd t pd 50% v cc v cc v cc 50% g nd a, b, c 50% 50% 50% (rr) (rf) g nd out out g nd 50% (ff) (fr) t pd t pd
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-79 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 3-137 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v combinatorial cell equation parameter std. units inv y = !a t pd 1.12 ns and2 y = a b t pd 0.86 ns nand2 y = !(a b) t pd 0.92 ns or2 y = a + b t pd 1.20 ns nor2 y = !(a + b) t pd 1.12 ns xor2 y = a bt pd 1.40 ns maj3 y = maj(a , b, c) t pd 1.34 ns xor3 y = a b ct pd 1.80 ns mux2 y = a !s + b s t pd 1.49 ns and3 y = a b c t pd 1.22 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-138 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v combinatorial cell equation parameter std. units inv y = !a t pd 2.12 ns and2 y = a b t pd 1.46 ns nand2 y = !(a b) t pd 1.63 ns or2 y = a + b t pd 2.34 ns nor2 y = !(a + b) t pd 2.12 ns xor2 y = a bt pd 2.50 ns maj3 y = maj(a , b, c) t pd 2.50 ns xor3 y = a b ct pd 3.17 ns mux2 y = a !s + b s t pd 2.87 ns and3 y = a b c t pd 2.31 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-80 advanced v0.1 versatile specifications as a sequential module the igloo library offers a wide variety of sequential cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e and proasic3/e macro library guide . figure 3-25 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-81 timing characteristics 1.5 v dc core voltage figure 3-26 ? timing model and waveforms pre clr out clk data en t sue 50 % 50 % t sud t hd 50 % 50 % t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 3-139 ? register delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t clkq clock-to-q of the core register 0.90 ns t sud data setup time for the core register 0.82 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 0.73 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.61 ns t pre2q asynchronous preset-to-q of the core register 0.62 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 ns t rempre asynchronous preset removal time for the core register 0.00 ns t recpre asynchronous preset recovery time for the core register 0.24 ns t wclr asynchronous clear minimum pulse width for the core register 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.56 ns t ckmpwl clock minimum pulse width low for the core register 0.56 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-82 advanced v0.1 1.2 v dc core voltage table 3-140 ? register delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t clkq clock-to-q of the core register 1.65 ns t sud data setup time for the core register 1.19 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 1.31 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.89 ns t pre2q asynchronous preset-to-q of the core register 0.90 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 ns t rempre asynchronous preset removal time for the core register 0.00 ns t recpre asynchronous preset recovery time for the core register 0.24 ns t wclr asynchronous clear minimum pulse width for the core register 0.46 ns t wpre asynchronous preset minimum pulse width for the core register 0.46 ns t ckmpwh clock minimum pulse width high for the core register 0.95 ns t ckmpwl clock minimum pulse width low for the core register 0.95 ns note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-83 global resource characteristics agl250 clock tree topology clock delays are device-specific. figure 3-27 is an example of a global tree used for clock routing. the global tree presented in figure 3-27 is driven by a ccc located on the west side of the agl250 device. it is used to drive all d-flip- flops in the device. figure 3-27 ? example of global tree use in an agl250 device for clock routing central global rib versatile rows global spine ccc
igloo low-power flash fpgas wi th flash*freeze technology 3-84 advanced v0.1 global tree timing characteristics global clock delays include the central rib delay, the spin e delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o st andard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilit ies, refer to the "clock conditioning circuits" section on page 2-14 . table 3-141 to table 3-146 on page 3-86 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics 1.5 v dc core voltage table 3-141 ? agl030 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.23 1.44 ns t rckh input high delay for global clock 1.25 1.52 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.30 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single el ement is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthes t sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-142 ? agl125 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.38 1.74 ns t rckh input high delay for global clock 1.41 1.85 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single el ement is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthes t sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-85 1.2 v dc core voltage table 3-143 ? agl600 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.50 1.85 ns t rckh input high delay for global clock 1.55 1.98 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.48 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single el ement is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthes t sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values. table 3-144 ? agl030 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.84 2.13 ns t rckh input high delay for global clock 1.93 2.33 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.49 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single el ement is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthes t sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-86 advanced v0.1 table 3-145 ? agl125 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.12 2.60 ns t rckh input high delay for global clock 2.21 2.85 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.73 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single el ement is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthes t sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values. table 3-146 ? agl600 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.27 2.74 ns t rckh input high delay for global clock 2.39 3.02 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.74 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single el ement is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthes t sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-87 embedded sram and fifo characteristics sram figure 3-28 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
igloo low-power flash fpgas wi th flash*freeze technology 3-88 advanced v0.1 timing waveforms figure 3-29 ? ram read for pass-through output figure 3-30 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-89 figure 3-31 ? ram write, output retained (wmode = 0) figure 3-32 ? ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
igloo low-power flash fpgas wi th flash*freeze technology 3-90 advanced v0.1 figure 3-33 ? write access after write onto same address c lk1 c lk2 wen_b1 wen_b2 add1 add2 di1 di2 do2 (pass-throu g h) do2 (pipeline d ) a 0 t ah t a s t ah t a s t dh t cc kh t d s t c kq1 t c kq2 d 1 a 1 d 2 a 3 d 3 a 0 d 0 d n d 0 d n d 0 a 0 a 4 d 4
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-91 figure 3-34 ? read access after write onto same address c lk1 c lk2 wen_b1 wen_b2 add1 add2 di1 do2 (pass-throu g h) do2 (pipeline d ) a 0 t ah t a s t ah t a s t dh t d s t wro t c kq1 t c kq2 d 0 a 0 a 1 a 4 d n d n d 0 d 0 d 1 a 2 d 2 a 3 d 3
igloo low-power flash fpgas wi th flash*freeze technology 3-92 advanced v0.1 figure 3-35 ? write access after read onto same address figure 3-36 ? ram reset a 0 a 1 a 0 a 0 a 1 a 3 d 1 d 2 d 3 t ah t a s t ah t a s t c kq1 t c kq1 t c kq2 t cc kh c lk1 add1 wen_b1 do1 (pass-throu g h) do1 (pipeline d ) c lk2 add2 di2 wen_b2 d n d n d 0 d 1 d 0 clk reset_b do d n t cyc t ckh t ckl t rstbq d m
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-93 timing characteristics 1.5 v dc core voltage table 3-147 ? ram4k9 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t as address setup time 0.84 ns t ah address hold time 0.16 ns t ens ren_b, wen_b setup time 0.82 ns t enh ren_b, wen_b hold time 0.16 ns t bks blk_b setup time 1.67 ns t bkh blk_b hold time 0.16 ns t ds input data (di) setup time 0.72 ns t dh input data (di) hold time 0.36 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 3.60 ns clock high to new data valid on do (f low-through, wmode = 1) 3.12 ns t ckq2 clock high to new data valid on do (pipelined) 1.84 ns t wro address collision clk-to-clk delay for reliable re ad access after write on same address 1.23 ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address 2.58 ns t rstbq reset_b low to data out low on do (flow through) 2.10 ns reset_b low to data out low on do (pipelined) 2.10 ns t remrstb reset_b removal 0.61 ns t recrstb reset_b recovery 3.24 ns t mpwrstb reset_b minimum pulse width 0.56 ns t cyc clock cycle time 5.17 ns f max maximum frequency 193 mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-94 advanced v0.1 table 3-148 ? ram512x18 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t as address setup time 0.84 ns t ah address hold time 0.16 ns t ens ren_b, wen_b setup time 0.74 ns t enh ren_b, wen_b hold time 0.08 ns t ds input data (di) setup time 0.72 ns t dh input data (di) hold time 0.36 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 4.29 ns t ckq2 clock high to new data valid on do (pipelined) 1.75 ns t wro address collision clk-to-clk delay for reliable re ad access after write on same address tbd ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address tbd ns t rstbq reset_b low to data out low on do (flow through) 2.10 ns reset_b low to data out low on do (pipelined) 2.10 ns t remrstb reset_b removal 0.61 ns t recrstb reset_b recovery 3.24 ns t mpwrstb reset_b minimum pulse width 0.56 ns t cyc clock cycle time 5.17 ns f max maximum frequency 193 mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-95 1.2 v dc core voltage table 3-149 ? ram4k9 commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t as address setup time 1.53 ns t ah address hold time 0.29 ns t ens ren_b, wen_b setup time 1.50 ns t enh ren_b, wen_b hold time 0.29 ns t bks blk_b setup time 3.05 ns t bkh blk_b hold time 0.29 ns t ds input data (di) setup time 1.33 ns t dh input data (di) hold time 0.66 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 6.61 ns clock high to new data valid on do (f low-through, wmode = 1) 5.72 ns t ckq2 clock high to new data valid on do (pipelined) 3.38 ns t wro address collision clk-to-clk delay for reliable re ad access after write on same address 1.23 ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address 4.65 ns t rstbq reset_b low to data out low on do (flow through) 3.86 ns reset_b low to data out low on do (pipelined) 3.86 ns t remrstb reset_b removal 1.12 ns t recrstb reset_b recovery 5.93 ns t mpwrstb reset_b minimum pulse width 1.01 ns t cyc clock cycle time 9.30 ns f max maximum frequency 108 mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-96 advanced v0.1 table 3-150 ? ram512x18 commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t as address setup time 1.53 ns t ah address hold time 0.29 ns t ens ren_b, wen_b setup time 1.36 ns t enh ren_b, wen_b hold time 0.15 ns t ds input data (di) setup time 1.33 ns t dh input data (di) hold time 0.66 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 7.88 ns t ckq2 clock high to new data valid on do (pipelined) 3.20 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address tbd ns t rstbq reset_b low to data out low on do (flow through) 3.86 ns reset_b low to data out low on do (pipelined) 3.86 ns t remrstb reset_b removal 1.12 ns t recrstb reset_b recovery 5.93 ns t mpwrstb reset_b minimum pulse width 1.01 ns t cyc clock cycle time 9.30 ns f max maximum frequency 108 mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-97 fifo figure 3-37 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
igloo low-power flash fpgas wi th flash*freeze technology 3-98 advanced v0.1 timing waveforms figure 3-38 ? fifo reset figure 3-39 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-99 figure 3-40 ? fifo full flag and afull flag assertion figure 3-41 ? fifo empty flag and ae mpty flag deassertion figure 3-42 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
igloo low-power flash fpgas wi th flash*freeze technology 3-100 advanced v0.1 timing characteristics 1.5 v dc core voltage table 3-151 ? fifo worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units t ens ren_b, wen_b setup time 2.03 ns t enh ren_b, wen_b hold time 0.16 ns t bks blk_b setup time 0.30 ns t bkh blk_b hold time 0.00 ns t ds input data (di) setup time 0.77 ns t dh input data (di) hold time 0.25 ns t ckq1 clock high to new data valid on do (flow-through) 3.39 ns t ckq2 clock high to new data valid on do (pipelined) 1.83 ns t rckef rclk high to empty flag valid 3.60 ns t wckff wclk high to full flag valid 3.42 ns t ckaf clock high to almost empty/full flag valid 13.10 ns t rstfg reset_b low to empty/full flag valid 3.55 ns t rstaf reset_b low to almost empty/full flag valid 12.97 ns t rstbq reset_b low to data out low on do (flow-through) 2.06 ns reset_b low to data out low on do (pipelined) 2.06 ns t remrstb reset_b removal 0.61 ns t recrstb reset_b recovery 3.24 ns t mpwrstb reset_b minimum pulse width 0.56 ns t cyc clock cycle time 5.17 ns f max maximum frequency for fifo 193 mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-101 1.2 v dc core voltage table 3-152 ? fifo worst commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units t ens ren_b, wen_b setup time 4.13 ns t enh ren_b, wen_b hold time 0.31 ns t bks blk_b setup time 0.47 ns t bkh blk_b hold time 0.00 ns t ds input data (di) setup time 1.56 ns t dh input data (di) hold time 0.49 ns t ckq1 clock high to new data valid on do (flow-through) 6.80 ns t ckq2 clock high to new data valid on do (pipelined) 3.62 ns t rckef rclk high to empty flag valid 7.23 ns t wckff wclk high to full flag valid 6.85 ns t ckaf clock high to almost empty/full flag valid 26.61 ns t rstfg reset_b low to empty/full flag valid 7.12 ns t rstaf reset_b low to almost empty/full flag valid 26.33 ns t rstbq reset_b low to data out low on do (flow-through) 4.09 ns reset_b low to data out low on do (pipelined) 4.09 ns t remrstb reset_b removal 1.23 ns t recrstb reset_b recovery 6.58 ns t mpwrstb reset_b minimum pulse width 1.01 ns t cyc clock cycle time 9.30 ns f max maximum frequency for fifo 108 mhz note: for specific junction temperature an d voltage supply levels, refer to table 3-7 on page 3-6 for derating values.
igloo low-power flash fpgas wi th flash*freeze technology 3-102 advanced v0.1 embedded flashrom characteristics timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage figure 3-43 ? timing diagram a 0 a 1 t s u t hold t s u t hold t s u t hold t c kq2 t c kq2 t c kq2 c lk a dd ress data d 0 d 0 d 1 table 3-153 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units t su address setup time 0.58 ns t hold address hold time 0.00 ns t ck2q clock to out 34.47 ns f max maximum clock frequency 15 mhz table 3-154 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units t su address setup time 0.59 ns t hold address hold time 0.00 ns t ck2q clock to out 52.90 ns f max maximum clock frequency 10 mhz
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 3-103 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtain complete jtag timing, add i/ o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 3-15 for more details. timing characteristics table 3-155 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time ns t dihd test data input hold time ns t tmssu test mode select setup time ns t tmdhd test mode select hold time ns t tck2q clock to q (data out) ns t rstb2q reset to q (data out) ns f tckmax tck maximum frequency 20 20 20 mhz t trstrem resetb removal time ns t trstrec resetb recovery time ns t trstmpw resetb minimum pulse ns note: for specific junction temperature an d voltage supply levels, refer to table 3-6 on page 3-6 for derating values.

igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4 -1 package pin assignments 132-pin qfn note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . note: this is the top view of the package. pin a1 mark a48 a36 a25 a1 a12 a37 a13 a24 b44 b33 b23 b34 b12 b22 c40 c30 c21 b1 b11 c1 c10 c31 c11 c20 optional corner pad (4)
igloo low-power flash fpgas wi th flash*freeze technology 4-2 advanced v0.1 132-pin qfn pin number agl030 function a1 io80rsb1 a2 io77rsb1 a3 nc a4 io76rsb1 a5 gec0/io73rsb1 a6 nc a7 geb0/io71rsb1 a8 io69rsb1 a9 nc a10 v cc a11 io67rsb1 a12 io64rsb1 a13 io59rsb1 a14 io56rsb1 a15 nc a16 io55rsb1 a17 io53rsb1 a18 v cc a19 io50rsb1 a20 io48rsb1 a21 io45rsb1 a22 io44rsb1 a23 io43rsb1 a24 tdi a25 trst a26 io40rsb0 a27 nc a28 io39rsb0 a29 io38rsb0 a30 io36rsb0 a31 io35rsb0 a32 gdc0/io32rsb0 a33 nc a34 v cc a35 io30rsb0 a36 io27rsb0 a37 io22rsb0 a38 io19rsb0 a39 nc a40 io18rsb0 a41 io16rsb0 a42 io14rsb0 a43 v cc a44 io11rsb0 a45 io08rsb0 a46 io06rsb0 a47 io05rsb0 a48 io02rsb0 b1 io81rsb1 b2 io78rsb1 b3 gnd b4 io75rsb1 b5 nc b6 gnd b7 io70rsb1 b8 nc b9 gnd b10 io66rsb1 b11 io63rsb1 b12 ff/io60rsb1 b13 io57rsb1 b14 gnd b15 io54rsb1 b16 io52rsb1 b17 gnd b18 io49rsb1 b19 io46rsb1 b20 gnd b21 io42rsb1 b22 tms b23 tdo b24 io41rsb0 132-pin qfn pin number agl030 function b25 gnd b26 nc b27 io37rsb0 b28 gnd b29 gda0/io33rsb0 b30 nc b31 gnd b32 io29rsb0 b33 io26rsb0 b34 io23rsb0 b35 io20rsb0 b36 gnd b37 io17rsb0 b38 io15rsb0 b39 gnd b40 io12rsb0 b41 io09rsb0 b42 gnd b43 io04rsb0 b44 io01rsb0 c1 io82rsb1 c2 io79rsb1 c3 nc c4 io74rsb1 c5 gea0/io72rsb1 c6 nc c7 nc c8 v cci b1 c9 io65rsb1 c10 io62rsb1 c11 io61rsb1 c12 io58rsb1 c13 nc c14 nc c15 io51rsb1 c16 v cci b1 132-pin qfn pin number agl030 function
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-3 c17 io47rsb1 c18 nc c19 tck c20 nc c21 v pump c22 v jtag c23 nc c24 nc c25 nc c26 gdb0/io34rsb0 c27 nc c28 v cci b0 c29 io28rsb0 c30 io25rsb0 c31 io24rsb0 c32 io21rsb0 c33 nc c34 nc c35 v cci b0 c36 io13rsb0 c37 io10rsb0 c38 io07rsb0 c39 io03rsb0 c40 io00rsb0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number agl030 function
igloo low-power flash fpgas wi th flash*freeze technology 4-4 advanced v0.1 132-pin qfn pin number agl125 function a1 gab2/io69rsb1 a2 io130rsb1 a3 v cci b1 a4 gfc1/io126rsb1 a5 gfb0/io123rsb1 a6 v ccplf a7 gfa1/io121rsb1 a8 gfc2/io118rsb1 a9 io115rsb1 a10 v cc a11 geb1/io110rsb1 a12 gea0/io107rsb1 a13 gec2/io104rsb1 a14 io100rsb1 a15 v cc a16 io99rsb1 a17 io96rsb1 a18 io94rsb1 a19 io91rsb1 a20 io85rsb1 a21 io79rsb1 a22 v cc a23 gdb2/io71rsb1 a24 tdi a25 trst a26 gdc1/io61rsb0 a27 v cc a28 io60rsb0 a29 gcc2/io59rsb0 a30 gca2/io57rsb0 a31 gca0/io56rsb0 a32 gcb1/io53rsb0 a33 io49rsb0 a34 v cc a35 io44rsb0 a36 gba2/io41rsb0 a37 gbb1/io38rsb0 a38 gbc0/io35rsb0 a39 v cci b0 a40 io28rsb0 a41 io22rsb0 a42 io18rsb0 a43 io14rsb0 a44 io11rsb0 a45 io07rsb0 a46 v cc a47 gac1/io05rsb0 a48 gab0/io02rsb0 b1 io68rsb1 b2 gac2/io131rsb1 b3 gnd b4 gfc0/io125rsb1 b5 v complf b6 gnd b7 gfb2/io119rsb1 b8 io116rsb1 b9 gnd b10 geb0/io109rsb1 b11 vmv1 b12 ff/geb2/io105rsb1 b13 io101rsb1 b14 gnd b15 io98rsb1 b16 io95rsb1 b17 gnd b18 io87rsb1 b19 io81rsb1 b20 gnd b21 gndq b22 tms b23 tdo b24 gdc0/io62rsb0 132-pin qfn pin number agl125 function b25 gnd b26 nc b27 gcb2/io58rsb0 b28 gnd b29 gcb0/io54rsb0 b30 gcc1/io51rsb0 b31 gnd b32 gbb2/io43rsb0 b33 vmv0 b34 gba0/io39rsb0 b35 gbc1/io36rsb0 b36 gnd b37 io26rsb0 b38 io21rsb0 b39 gnd b40 io13rsb0 b41 io08rsb0 b42 gnd b43 gac0/io04rsb0 b44 gndq c1 gaa2/io67rsb1 c2 io132rsb1 c3 v cc c4 gfb1/io124rsb1 c5 gfa0/io122rsb1 c6 gfa2/io120rsb1 c7 io117rsb1 c8 v cci b1 c9 gea1/io108rsb1 c10 gndq c11 gea2/io106rsb1 c12 io103rsb1 c13 v cci b1 c14 io97rsb1 c15 io93rsb1 c16 io89rsb1 132-pin qfn pin number agl125 function
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-5 c17 io83rsb1 c18 v cci b1 c19 tck c20 vmv1 c21 v pump c22 v jtag c23 v cci b0 c24 nc c25 nc c26 gca1/io55rsb0 c27 gcc0/io52rsb0 c28 v cci b0 c29 io42rsb0 c30 gndq c31 gba1/io40rsb0 c32 gbb0/io37rsb0 c33 v cc c34 io24rsb0 c35 io19rsb0 c36 io16rsb0 c37 io10rsb0 c38 v cci b0 c39 gab1/io03rsb0 c40 vmv0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number agl125 function
igloo low-power flash fpgas wi th flash*freeze technology 4-6 advanced v0.1 100-pin vqfp note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . note: this is the top view of the package. 1 100-pin vqfp 100
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-7 100-pin vqfp pin number agl030 function 1gnd 2 io82rsb1 3 io81rsb1 4 io80rsb1 5 io79rsb1 6 io78rsb1 7 io77rsb1 8 io76rsb1 9gnd 10 io75rsb1 11 io74rsb1 12 gec0/io73rsb1 13 gea0/io72rsb1 14 geb0/io71rsb1 15 io70rsb1 16 io69rsb1 17 v cc 18 v cci b1 19 io68rsb1 20 io67rsb1 21 io66rsb1 22 io65rsb1 23 io64rsb1 24 io63rsb1 25 io62rsb1 26 io61rsb1 27 ff/io60rsb1 28 io59rsb1 29 io58rsb1 30 io57rsb1 31 io56rsb1 32 io55rsb1 33 io54rsb1 34 io53rsb1 35 io52rsb1 36 io51rsb1 37 v cc 38 gnd 39 v cci b1 40 io49rsb1 41 io47rsb1 42 io46rsb1 43 io45rsb1 44 io44rsb1 45 io43rsb1 46 io42rsb1 47 tck 48 tdi 49 tms 50 nc 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 io41rsb0 58 io40rsb0 59 io39rsb0 60 io38rsb0 61 io37rsb0 62 io36rsb0 63 gdb0/io34rsb0 64 gda0/io33rsb0 65 gdc0/io32rsb0 66 v cci b0 67 gnd 68 v cc 69 io31rsb0 70 io30rsb0 71 io29rsb0 72 io28rsb0 100-pin vqfp pin number agl030 function 73 io27rsb0 74 io26rsb0 75 io25rsb0 76 io24rsb0 77 io23rsb0 78 io22rsb0 79 io21rsb0 80 io20rsb0 81 io19rsb0 82 io18rsb0 83 io17rsb0 84 io16rsb0 85 io15rsb0 86 io14rsb0 87 v cci b0 88 gnd 89 v cc 90 io12rsb0 91 io10rsb0 92 io08rsb0 93 io07rsb0 94 io06rsb0 95 io05rsb0 96 io04rsb0 97 io03rsb0 98 io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number agl030 function
igloo low-power flash fpgas wi th flash*freeze technology 4-8 advanced v0.1 100-pin vqfp pin number agl125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 v complf 13 gfa0/io122rsb1 14 v ccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 v cc 18 v cci b1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 ff/geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 v cc 38 gnd 39 v cci b1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 v cci b0 67 gnd 68 v cc 69 io47rsb0 70 gbc2/io45rsb0 71 gbb2/io43rsb0 72 io42rsb0 100-pin vqfp pin number agl125 function 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 v cci b0 88 gnd 89 v cc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 100-pin vqfp pin number agl125 function
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-9 144-pin fbga note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . note: this is the bottom view of the package. 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a1 ball pad corner
igloo low-power flash fpgas wi th flash*freeze technology 4-10 advanced v0.1 144-pin fbga pin number agl125 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io11rsb0 a6 gnd a7 io18rsb0 a8 v cc a9 io25rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io69rsb1 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io08rsb0 b6 io14rsb0 b7 io19rsb0 b8 io22rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv0 c1 io132rsb1 c2 gfa2/io120rsb1 c3 gac2/io131rsb1 c4 v cc c5 io10rsb0 c6 io12rsb0 c7 io21rsb0 c8 io24rsb0 c9 io27rsb0 c10 gba2/io41rsb0 c11 io42rsb0 c12 gbc2/io45rsb0 d1 io128rsb1 d2 io129rsb1 d3 io130rsb1 d4 gaa2/io67rsb1 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io43rsb0 d10 io28rsb0 d11 io44rsb0 d12 gcb1/io53rsb0 e1 v cc e2 gfc0/io125rsb1 e3 gfc1/io126rsb1 e4 v cci b1 e5 io68rsb1 e6 v cci b0 e7 v cci b0 e8 gcc1/io51rsb0 e9 v cci b0 e10 v cc e11 gca0/io56rsb0 e12 io46rsb0 f1 gfb0/io123rsb1 f2 v complf f3 gfb1/io124rsb1 f4 io127rsb1 f5 gnd f6 gnd f7 gnd f8 gcc0/io52rsb0 f9 gcb0/io54rsb0 f10 gnd f11 gca1/io55rsb0 f12 gca2/io57rsb0 144-pin fbga pin number agl125 function g1 gfa1/io121rsb1 g2 gnd g3 v ccplf g4 gfa0/io122rsb1 g5 gnd g6 gnd g7 gnd g8 gdc1/io61rsb0 g9 io48rsb0 g10 gcc2/io59rsb0 g11 io47rsb0 g12 gcb2/io58rsb0 h1 v cc h2 gfb2/io119rsb1 h3 gfc2/io118rsb1 h4 gec1/io112rsb1 h5 v cc h6 io50rsb0 h7 io60rsb0 h8 gdb2/io71rsb1 h9 gdc0/io62rsb0 h10 v cci b0 h11 io49rsb0 h12 v cc j1 geb1/io110rsb1 j2 io115rsb1 j3 v cci b1 j4 gec0/io111rsb1 j5 io116rsb1 j6 io117rsb1 j7 v cc j8 tck j9 gda2/io70rsb1 j10 tdo j11 gda1/io65rsb0 j12 gdb1/io63rsb0 144-pin fbga pin number agl125 function
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-11 k1 geb0/io109rsb1 k2 gea1/io108rsb1 k3 gea0/io107rsb1 k4 gea2/io106rsb1 k5 io100rsb1 k6 io98rsb1 k7 gnd k8 io73rsb1 k9 gdc2/io72rsb1 k10 gnd k11 gda0/io66rsb0 k12 gdb0/io64rsb0 l1 gnd l2 vmv1 l3 ff/geb2/io105rsb1 l4 io102rsb1 l5 v cci b1 l6 io95rsb1 l7 io85rsb1 l8 io74rsb1 l9 tms l10 v jtag l11 vmv1 l12 trst m1 gndq m2 gec2/io104rsb1 m3 io103rsb1 m4 io101rsb1 m5 io97rsb1 m6 io94rsb1 m7 io86rsb1 m8 io75rsb1 m9 tdi m10 v cci b1 m11 v pump m12 gndq 144-pin fbga pin number agl125 function
igloo low-power flash fpgas wi th flash*freeze technology 4-12 advanced v0.1 144-pin fbga pin number agl600 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io10rsb0 a6 gnd a7 io34rsb0 a8 v cc a9 io50rsb0 a10 gba0/io58rsb0 a11 gba1/io59rsb0 a12 gndq b1 gab2/io173pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io13rsb0 b6 io19rsb0 b7 io31rsb0 b8 io39rsb0 b9 gbb0/io56rsb0 b10 gbb1/io57rsb0 b11 gnd b12 vmv1 c1 io173ndb3 c2 gfa2/io161ppb3 c3 gac2/io172pdb3 c4 v cc c5 io16rsb0 c6 io25rsb0 c7 io28rsb0 c8 io42rsb0 c9 io45rsb0 c10 gba2/io60pdb1 c11 io60ndb1 c12 gbc2/io62ppb1 d1 io169pdb3 d2 io169ndb3 d3 io172ndb3 d4 gaa2/io174ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io54rsb0 d8 gbc1/io55rsb0 d9 gbb2/io61pdb1 d10 io61ndb1 d11 io62npb1 d12 gcb1/io70ppb1 e1 v cc e2 gfc0/io164ndb3 e3 gfc1/io164pdb3 e4 v cci b3 e5 io174npb3 e6 v cci b0 e7 v cci b0 e8 gcc1/io69pdb1 e9 v cci b1 e10 v cc e11 gca0/io71ndb1 e12 io72ndb1 f1 gfb0/io163npb3 f2 v complf f3 gfb1/io163ppb3 f4 io161npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io69ndb1 f9 gcb0/io70npb1 f10 gnd f11 gca1/io71pdb1 f12 gca2/io72pdb1 144-pin fbga pin number agl600 function g1 gfa1/io162ppb3 g2 gnd g3 v ccplf g4 gfa0/io162npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io86ppb1 g9 io74ndb1 g10 gcc2/io74pdb1 g11 io73ndb1 g12 gcb2/io73pdb1 h1 v cc h2 gfb2/io160pdb3 h3 gfc2/io159psb3 h4 gec1/io146pdb3 h5 v cc h6 io80pdb1 h7 io80ndb1 h8 gdb2/io90rsb2 h9 gdc0/io86npb1 h10 v cci b1 h11 io84psb1 h12 v cc j1 geb1/io145pdb3 j2 io160ndb3 j3 v cci b3 j4 gec0/io146ndb3 j5 io129rsb2 j6 io131rsb2 j7 v cc j8 tck j9 gda2/io89rsb2 j10 tdo j11 gda1/io88pdb1 j12 gdb1/io87pdb1 144-pin fbga pin number agl600 function
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-13 k1 geb0/io145ndb3 k2 gea1/io144pdb3 k3 gea0/io144ndb3 k4 gea2/io143rsb2 k5 io119rsb2 k6 io111rsb2 k7 gnd k8 io94rsb2 k9 gdc2/io91rsb2 k10 gnd k11 gda0/io88ndb1 k12 gdb0/io87ndb1 l1 gnd l2 vmv3 l3 ff/geb2/io142rsb2 l4 io136rsb2 l5 v cci b2 l6 io115rsb2 l7 io103rsb2 l8 io97rsb2 l9 tms l10 v jtag l11 vmv2 l12 trst m1 gndq m2 gec2/io141rsb2 m3 io138rsb2 m4 io123rsb2 m5 io126rsb2 m6 io134rsb2 m7 io108rsb2 m8 io99rsb2 m9 tdi m10 v cci b2 m11 v pump m12 gndq 144-pin fbga pin number agl600 function
igloo low-power flash fpgas wi th flash*freeze technology 4-14 advanced v0.1 256-pin fbga note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . note: this is the bottom view of the package. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-15 256-pin fbga pin number agl600 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io11rsb0 a6 io16rsb0 a7 io18rsb0 a8 io28rsb0 a9 io34rsb0 a10 io37rsb0 a11 io41rsb0 a12 io43rsb0 a13 gbb1/io57rsb0 a14 gba0/io58rsb0 a15 gba1/io59rsb0 a16 gnd b1 gab2/io173pdb3 b2 gaa2/io174pdb3 b3 gndq b4 gab1/io03rsb0 b5 io13rsb0 b6 io14rsb0 b7 io21rsb0 b8 io27rsb0 b9 io32rsb0 b10 io38rsb0 b11 io42rsb0 b12 gbc1/io55rsb0 b13 gbb0/io56rsb0 b14 io52rsb0 b15 gba2/io60pdb1 b16 io60ndb1 c1 io173ndb3 c2 io174ndb3 c3 vmv3 c4 io07rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io20rsb0 c8 io24rsb0 c9 io33rsb0 c10 io39rsb0 c11 io44rsb0 c12 gbc0/io54rsb0 c13 io51rsb0 c14 vmv0 c15 io61npb1 c16 io63pdb1 d1 io171ndb3 d2 io171pdb3 d3 gac2/io172pdb3 d4 io06rsb0 d5 gndq d6 io10rsb0 d7 io19rsb0 d8 io26rsb0 d9 io30rsb0 d10 io40rsb0 d11 io45rsb0 d12 gndq d13 io50rsb0 d14 gbb2/io61ppb1 d15 io53rsb0 d16 io63ndb1 e1 io166pdb3 e2 io167npb3 e3 io172ndb3 e4 io169ndb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io25rsb0 256-pin fbga pin number agl600 function e9 io31rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 e13 gbc2/io62pdb1 e14 io67ppb1 e15 io64ppb1 e16 io66pdb1 f1 io166ndb3 f2 io168npb3 f3 io167ppb3 f4 io169pdb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io62ndb1 f14 io64npb1 f15 io65ppb1 f16 io66ndb1 g1 io165ndb3 g2 io165pdb3 g3 io168ppb3 g4 gfc1/io164ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 256-pin fbga pin number agl600 function
igloo low-power flash fpgas wi th flash*freeze technology 4-16 advanced v0.1 g13 gcc1/io69ppb1 g14 io65npb1 g15 io75pdb1 g16 io75ndb1 h1 gfb0/io163npb3 h2 gfa0/io162ndb3 h3 gfb1/io163ppb3 h4 v complf h5 gfc0/io164npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io69npb1 h13 gcb1/io70ppb1 h14 gca0/io71npb1 h15 io67npb1 h16 gcb0/io70npb1 j1 gfa2/io161ppb3 j2 gfa1/io162pdb3 j3 v ccplf j4 io160ndb3 j5 gfb2/io160pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io73ppb1 j13 gca1/io71ppb1 j14 gcc2/io74ppb1 j15 io80ppb1 j16 gca2/io72pdb1 256-pin fbga pin number agl600 function k1 gfc2/io159pdb3 k2 io161npb3 k3 io156ppb3 k4 io129rsb2 k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io73npb1 k14 io80npb1 k15 io74npb1 k16 io72ndb1 l1 io159ndb3 l2 io156npb3 l3 io151ppb3 l4 io158psb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io87npb1 l14 io85ndb1 l15 io85pdb1 l16 io84pdb1 m1 io150pdb3 m2 io151npb3 m3 io147npb3 m4 gec0/io146npb3 256-pin fbga pin number agl600 function m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io117rsb2 m9 io110rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io94rsb2 m14 gdb1/io87ppb1 m15 gdc1/io86pdb1 m16 io84ndb1 n1 io150ndb3 n2 io147ppb3 n3 gec1/io146ppb3 n4 io140rsb2 n5 gndq n6 gea2/io143rsb2 n7 io126rsb2 n8 io120rsb2 n9 io108rsb2 n10 io103rsb2 n11 io99rsb2 n12 gndq n13 io92rsb2 n14 v jtag n15 gdc0/io86ndb1 n16 gda1/io88pdb1 p1 geb1/io145pdb3 p2 geb0/io145ndb3 p3 vmv2 p4 io138rsb2 p5 io136rsb2 p6 io131rsb2 p7 io124rsb2 p8 io119rsb2 256-pin fbga pin number agl600 function
igloo low-power flash fpgas with flash*freeze technology advanced v0.1 4-17 p9 io107rsb2 p10 io104rsb2 p11 io97rsb2 p12 vmv1 p13 tck p14 v pump p15 trst p16 gda0/io88ndb1 r1 gea1/io144pdb3 r2 gea0/io144ndb3 r3 io139rsb2 r4 gec2/io141rsb2 r5 io132rsb2 r6 io127rsb2 r7 io121rsb2 r8 io114rsb2 r9 io109rsb2 r10 io105rsb2 r11 io98rsb2 r12 io96rsb2 r13 gdb2/io90rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io137rsb2 t3 ff/geb2/io142rsb2 t4 io134rsb2 t5 io125rsb2 t6 io123rsb2 t7 io118rsb2 t8 io115rsb2 t9 io111rsb2 t10 io106rsb2 t11 io102rsb2 t12 gdc2/io91rsb2 256-pin fbga pin number agl600 function t13 io93rsb2 t14 gda2/io89rsb2 t15 tms t16 gnd 256-pin fbga pin number agl600 function

igloo low-power flash fpgas with flash*freeze technology advanced v0.1 5-1 datasheet information datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are design ated as ?product brief,? ?advanced, ? ?production,? and ?web-only.? the definition of these categories are as follows: product brief the product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. unmarked (production) this datasheet version contains informat ion that is considered to be final. export administration regulations (ear) the products described in this datasheet are subject to th e export administration regu lations (ear). they could require an approved export license prior to export from th e united states. an export in cludes release of product or disclosure of technology to a foreign nati onal inside or outsid e the united states. the actel products described in this advanced status data sheet may not have completed actel?s qualification process. actel may amend or enhance products during the product intr oduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life- support, and other high-relia bility applications. con sult actel?s terms an d conditions for specif ic liability exclusions relating to life-support applic ations. a reliability report covering all of actel?s products is available on the actel website at http://www.actel.com/doc uments/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. c ontact your local actel sales office for additional reliability information.
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