View ADG1411YRUZ-REEL7_6729722.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1.5 ? on resistance, 15 v/ + 12 v/5 v, i cmos, quad spst switches adg1411/adg1412/adg1413 rev. b information furnished by analog dev ices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u .s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 C 2011 analog devices, inc. all rights reserved. features 1.5 ? on resistance 0. 3 ? on - resistance flatness 0. 1 ? on - resistance match between channels c ontinuous current per channel lfcsp package: 2 5 0 ma tssop package : 190 ma fully specified at +12 v, 15 v, and 5 v no v l supply required 3 v logic - compat ible inputs rail - to - rail operation 16- lead tssop and 16 - lead , 4 mm 4 mm lfcsp qualified for automotive applications applications automated test equipment data acquisition systems battery - powered systems sample - and - hold systems audio signal routing video signal routing communication s systems relay replacement functional block dia gram in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 adg1411 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 adg1412 switches shown for a logic 1 input. in2 s2 d2 in3 s3 d3 in1 s1 d1 in4 s4 d4 adg1413 06815-001 figure 1. general description the adg1411/adg1412/adg1413 are monolithic complemen - tary metal - oxide semiconductor (cmos) devices containing fo ur independently selectable switches designed on an i cmos ? process. i cmos (industrial cmos) is a modular manufacturing process combining high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics c apable of 33 v operation in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos com - ponents can tolerate high supply voltages while providing increased performan ce, dramatically lower power consumption, and reduced package size. the on - resistance profile is very flat over the full analog input range , ensuring excellent linearity and low distortion when switching signals. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery - powered instruments. the adg1411/adg1412/adg1413 contain four independent single - pole/single - throw (spst) switches. the adg1411 and adg1412 differ only in that the digital control logic is inverted. the adg1411 switches are turned on with logic 0 on the appropriate control input, whereas the adg1412 switches are turned on with logic 1. the adg1413 has two switches with digital control logic similar to that of the adg1411; the logic is inv erted on the other two switches. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. the adg1413 exhibits break - before - make switching action for use in multiplexer applications. inherent in the design is low charge injection , which results in minimum transients when the digital inputs are switched. product highlights 1. 2 .6 ? maximum on resistance over temperature. 2. minimum d istortion . 3. ultralow power dissipation: <0.03 w. 4. 16- lead tssop and 16 - lead, 4 mm 4 mm lfcsp packages.
adg1411/adg1412/adg1413 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 +12 v single supply ..................................................................... 4 5 v dual supply ......................................................................... 5 absolute maximum ratings ............................................................6 esd caution ...................................................................................6 pin configurations and function descriptions ............................7 typical performance characteristics ..............................................8 terminology .................................................................................... 12 test circuits ..................................................................................... 13 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 automotive products ................................................................. 16 revision history 3 / 11 rev. a to rev. b changes to features section ............................................................ 1 change s to table 5, added exposed pad notation ...................... 3 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 40 added automotive products section ........................................... 40 3 /09 rev. 0 to rev. a changes to power requireme nts , i dd , digital inputs = 5 v parameter , table 1 ............................................................................. 3 changes to power requirements , i dd , digital inputs = 5 v parameter table 2 .............................................................................. 4 5 /0 8 revision 0: initial version
adg1411/adg1412/adg1413 rev. b | page 3 of 16 specifications 15 v dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 1.5 ? typ v s = 10 v, i s = ?10 ma; see figure 23 1.8 2 . 3 2. 6 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels , ? r on 0.1 ? typ v s = 10 v , i s = ?10 ma 0.1 8 0. 1 9 0. 21 ? max on - resistance flatness, r flat(on) 0. 3 ? typ v s = 10 v , i s = ?10 ma 0.3 6 0. 4 0. 4 5 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0. 03 na typ v s = 10 v, v d = ? 10 v; see figure 24 0.5 5 2 12.5 na max dr ain off leakage, i d (off) 0. 0 3 na typ v s = 10 v, v d = ? 10 v; see figure 24 0. 55 2 12.5 na max channel on leakage, i d , i s (on) 0.15 na typ v s = v d = 10 v; see figure 25 2 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 .5 pf typ dynamic characteristics 1 t on 100 ns typ r l = 3 00 ?, c l = 35 pf 150 170 190 ns max v s = 10 v; see figure 30 t off 90 ns typ r l = 300 ?, c l = 35 pf 120 140 1 60 ns max v s = 10 v; see figure 30 break - before - mak e time delay, t d (adg1413 only) 25 ns typ r l = 300 ?, c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 31 charge injection , q inj ? 20 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 32 off isolation ? 80 db typ r l = 50 ?, c l = 5 pf, f = 100 k hz; see figure 26 channel - to - channel crosstalk ? 100 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.01 4 % typ r l = 110 ?, 15 v p - p , f = 20 hz to 20 khz ; see figure 29 ?3 db bandwidth 170 mhz typ r l = 50 ?, c l = 5 pf; see figure 28 insertion loss ? 0. 35 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 c s (off) 2 3 pf typ v s = 0 v, f = 1 mhz c d (off) 2 3 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 116 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 220 a typ digital inputs = 5 v 3 8 0 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 4.5/16.5 v min/ v max gnd = 0 v 1 guaranteed by design; not subject to production test.
adg1411/adg1412/adg1413 rev. b | page 4 of 16 + 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/commen ts analog switch analog signal range 0 v to v dd v on resistance, r on 2.8 ? typ v s = 0 v to 10 v, i s = ?10 ma; see figure 23 3 .5 4 .3 4. 8 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between c hannels , ? r on 0.1 3 ? typ v s = 0 v to 10 v , i s = ?10 ma 0. 21 0. 23 0.2 5 ? max on - resistance flatness, r flat(on) 0.6 ? typ v s = 0 v to 10 v , i s = ?10 ma 1 .1 1. 2 1. 3 ? max leakage currents v dd = 10.8 v, v ss = 0 v source off leakage, i s ( off) 0.0 2 na typ v s = 1 v/10 v, v d = 10 v/0 v; see figure 24 0.55 2 12.5 na max drain off leakage, i d (off) 0. 02 na typ v s = 1 v/10 v, v d = 10 v/0 v; see figu re 24 0.55 2 12.5 na max channel on leakage, i d , i s (on) 0.15 na typ v s = v d = 1 v/ 10 v; see figure 25 1. 5 4 30 na max digital inputs input high voltage, v inh 2.0 v min input lo w voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3.5 pf typ dynamic characteristics 1 t on 1 70 ns typ r l = 300 ? , c l = 35 pf 250 295 330 ns max v s = 8 v; see figure 30 t off 75 ns typ r l = 300 ? , c l = 35 pf 135 165 190 ns max v s = 8 v; see figure 30 break - before - make time delay, t d (adg1413 only) 100 n s typ r l = 300 ? , c l = 35 pf 40 ns min v s1 = v s2 = 8 v; see figure 31 charge injection , q inj 30 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf; see figure 32 off isolation ? 80 db typ r l = 50 ? , c l = 5 pf, f = 100 k hz; see figure 26 channel - to - channel crosstalk ? 100 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 ?3 db bandwidth 130 mhz typ r l = 50 ? , c l = 5 pf; see figure 28 insertion loss ? 0. 5 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 c s (off) 38 pf typ v s = 6 v, f = 1 mhz c d (off) 40 pf typ v s = 6 v, f = 1 mhz c d , c s (on) 104 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max 220 a typ digital inputs = 5 v 380 a max v d d 5/16.5 v min/ v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
adg1411/adg1412/adg1413 rev. b | page 5 of 16 5 v dual supply v dd = 5 v 10%, v ss = ? 5 v 10%, gnd = 0 v, unless otherwise noted. table 3 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 3 . 3 ? typ v s = 4.5 v, i s = ?10 ma; see figure 23 4 4. 9 5. 4 ? max v dd = +4.5 v, v ss = ?4.5 v on - resi stance match between channels, ? r on 0.1 3 ? typ v s = 4.5 v, i s = ?10 ma 0. 22 0. 23 0.2 5 ? max on - resistance flatness, r fl at(on) 0. 9 ? typ v s = 4.5 v; i s = ?10 ma 1 .1 1. 2 4 1. 3 1 ? max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off) 0.03 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 24 0.55 2 12.5 na max drain off leakage, i d (off) 0. 0 3 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 24 0.55 2 12.5 na max channel on leakage, i d , i s (on) 0.0 5 na typ v s = v d = 4.5 v; see figure 25 1.0 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digita l input capacitance, c in 3 .5 pf typ dynamic characteristics 1 t on 275 ns typ r l = 300 ? , c l = 35 pf 400 465 510 ns max v s = 3 v; see figure 30 t off 175 ns typ r l = 300 ? , c l = 35 pf 290 320 380 ns max v s = 3 v; see figure 30 break - before - make ti me delay, t d (adg1413 only) 100 ns typ r l = 300 ? , c l = 35 pf 50 ns min v s1 = v s2 = 3 v; see figure 31 charge injection , q inj 30 pc typ v s = 0 v, r s = 0 ? , c l = 1 nf; see figure 32 off isolation ? 80 db typ r l = 50 ? , c l = 5 pf, f = 1 00 k hz; see figure 26 channel - to - channel crosstalk ? 100 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.03 % typ r l = 110 ?, 5 v p - p , f = 20 hz to 20 khz ; see figure 29 ?3 db bandwidth 1 30 mhz typ r l = 50 ? , c l = 5 pf; see figure 28 insertion loss ? 0. 5 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 28 c s (off) 3 2 pf typ v s = 0 v, f = 1 mhz c d (off) 33 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 116 pf typ v s = 0 v, f = 1 mhz power requirements v dd = + 5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1.0 a max v dd /v ss 4.5/16.5 v min/ v max gnd = 0 v 1 guaranteed by design; not subject to production test.
adg1411/adg1412/adg1413 rev. b | page 6 of 16 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4 . parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occur s first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s x or d x pins 5 00 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current per channel at 25c 16- lead tssop 190 ma 16- lead lfcsp 250 ma continuous current per c hannel at 125c 16- lead tssop 90 ma 16- lead lfcsp 1 00 ma operating temperature range automotive (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 1 6 - lead tssop, ja thermal impedance ( four - layer board ) 112c/w 16- lead lfcsp, ja thermal impedance 30.4c/w reflow soldering peak temperature, pb free 260(+0/ ? 5)c 1 overvoltages at the in x , sx, and d x pins are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent dam age to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for e xtended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
adg1411/adg1412/adg1413 rev. b | page 7 of 16 pin configurations a nd function descript ions in1 1 d1 2 s1 3 v ss 4 in2 16 d2 15 s2 14 v dd 13 gnd 5 nc 12 s4 6 s3 11 d4 7 d3 10 in4 8 in3 9 nc = no connect adg1411/ adg1412/ adg1413 top view (not to scale) 06815-002 figure 2 . tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 2. nc = no connect. pin 1 indicator 1 s1 2 v ss 3 gnd 4 s4 11 v dd 12 s2 10 nc 9 s3 5 d4 6 in4 7 in3 8 d3 15 in1 16 d1 14 in2 13 d2 top view (not to scale) adg1411/ adg1412/ adg1413 06815-003 figure 3 . lfcsp pin configuration table 5 . pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 in1 logic control input. 2 16 d1 drain terminal. this pin c an be an input or output. 3 1 s1 source terminal. this pin can be an input or output. 4 2 v ss most negative power supply potential. 5 3 gnd ground (0 v) reference. 6 4 s4 source terminal. this pin can be an input or output. 7 5 d4 drain terminal. this pin can be an input or output . 8 6 in4 logic control input. 9 7 in3 logic control input. 10 8 d3 drain terminal. this pin can be an input or output. 11 9 s3 source terminal. this pin can be an input or output. 12 10 nc no connection. 13 11 v dd most positive power supply potentia l. 14 12 s2 source terminal. this pin can be an input or output. 15 13 d2 drain terminal. this pin can be an input or output. 16 14 in2 logic control input. n/a 1 0 ep exposed pad. tie the exposed pad to the substrate, v ss . 1 n/a means not applicable. table 6 . adg1411/adg1412 truth table adg1411 inx adg1412 inx switch condition 0 1 on 1 0 off table 7 . adg1413 truth table adg1413 inx s1, s 4 s2, s 3 0 off on 1 on off
adg1411/adg1412/adg1413 rev. b | page 8 of 16 typical performance characteristics 2.5 2.0 1.5 1.0 0.5 0 ?16.5 ?12.5 ?8.5 ?4.5 ?0.5 3.5 7.5 15.5 on resistance ( ?) v s or v d (v) 11.5 v dd = +16.5v, v ss = ?16.5v t a = 25c i s = ?10ma v dd = +15v, v ss = ?15v v dd = +13.5v, v ss = ?13.5v v dd = +12v, v ss = ?12v v dd = +10v, v ss = ?10v 06815-104 figure 4. on resistance vs. v d or v s , dual supply 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?7 ?6 ?5 ?3 ?1 ?4 ?2 0 1 6 on resistance ( ?) v s or v d (v) 3 4 7 5 2 t a = 25c i s = ?10ma v dd = +7v, v ss = ?7v v dd = +5.5v, v ss = ?5.5v v dd = +5v, v ss = ?5v v dd = +4.5v, v ss = ?4.5v 06815-105 figure 5. on resistance vs. v d or v s , dual supply 7 6 5 4 3 2 1 0 0 14 12 10 8 6 4 2 on resistance ( ?) v s or v d (v) t a = 25c i s = ?10ma v dd = 15v, v ss = 0v v dd = 13.2v, v ss = 0v v dd = 12v, v ss = 0v v dd = 10.8v, v ss = 0v v dd = 8v, v ss = 0v v dd = 5v, v ss = 0v 06815-106 figure 6 . on resistance vs. v d or v s , single supp ly 3.0 2.5 2.0 1.5 1.0 0.5 0 ?15 15 10 5 0 ?5 ?10 on resistance ( ?) v s or v d (v) v dd = +15v v ss = ?15v i s = ?10ma t a = +25c t a = +85c t a = +125c t a = ?40c 06815-107 figure 7. on resistance vs. v d or v s for different temperatures, 15 v dual supply 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 on resistance ( ?) v s or v d (v) v dd = +5v v ss = ?5v i s = ?10ma t a = +25c t a = +85c t a = +125c t a = ?40c 06815-108 figure 8 . on resistance vs. v d or v s for different temperatures, 5 v dual supply 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 12 10 8 6 4 2 on resistance ( ?) v s or v d (v) v dd = 12v v ss = 0v i s = ?10ma t a = +25c t a = +85c t a = +125c t a = ?40c 06815-109 figure 9 . on resistance vs. v d or v s for different temperatures, +12 v single supply
adg1411/adg1412/adg1413 rev. b | page 9 of 16 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 on resistance ( ?) v s or v d (v) v dd = +5v v ss = ?5v t a = 125c i s = 100ma t a = 25c i s = 190ma 06815-010 figure 10 . on resistance vs. v d or v s for different current l evels, 5 v dual supply 1.5 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 120 100 80 60 40 20 leakage (na) temperature (c) v dd = +15v v ss = ?15v v bias = +10v/?10v 06815-005 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? figure 11 . leakage curren ts vs. temperature, 15 v dual supply 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 120 80 100 60 40 20 leakage (na) temperature (c) v dd = +5v v ss = ?5v v bias = +4.5v/?4.5v 06815-006 i d (off) ? + i s (off) + ? i d , i s (on) ++ i d , i s (on) ? ? i d (off) + ? i s (off) ? + figure 12 . leakage currents vs. temperature, 5 v dual supply 9 8 7 6 5 4 3 2 1 0 ?1 0 120 80 100 60 40 20 leakage (na) temperature (c) 06815-007 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) ++ i d , i s (on) ? ? v dd = 12v v ss = 0v v bias = 1v/10v figure 13 . leakage currents vs. temperature, +12 v single supply 80 70 60 50 40 30 20 10 0 0 14 12 10 8 6 4 2 i dd (a) logic, inx (v) t a = 25c i dd per logic input v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v 06815-008 figure 14 . i dd vs. logic level 600 400 200 0 ?200 ?400 ?600 ?15 ?10 ?5 0 5 10 15 charge injection (pc) v s (v) v dd = +15v, v ss = ?15v v dd = +12v, v ss = 0v v dd = +5v, v ss = ?5v t a = 25c 06815-012 figure 15 . charge injection vs. source voltage
adg1411/adg1412/adg1413 rev. b | page 10 of 16 300 0 50 100 150 200 250 ?40 ?20 0 20 40 60 80 120 time (ns) temperature (c) 100 06815-013 15v ds t on 15v ds t off 12v ss t on 12v ss t off figure 16 . t on /t off times vs. temperature for single supply (ss) and dual supply (d s ) 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1k 10k 100k 1m 10m 1g 100m off isolation (db) frequency (hz) v dd = +15v v ss = ?15v t a = 25c 06815-014 figure 17 . off isolation vs. frequency , 15 v dual supply 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10k 100k 1m 10m 100m 1g crosstalk (db) frequency (hz) v dd = +15v v ss = ?15v t a = 25c 06815-015 figure 18 . crosstalk vs. frequency , 15 v dual supply 0 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 10k 100k 1m 10m 1g 100m insertion loss (db) frequency (hz) v dd = +15v v ss = ?15v t a = 25c 06815-016 figure 19 . on response vs. frequency , 15 v dual supply 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1k 10k 100k 1m 10m acpsrr (db) frequency (hz) v dd = +15v v ss = ?15v v p-p = 0.62v t a = 25c no decoupling capacitors decoupling capacitors on supplies 06815-017 figure 20 . acpsrr vs. frequency , 15 v dual supply 0.028 0.024 0.026 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 10 100 1k 10k 100k thd + n (%) frequency (hz) v dd = +15v v ss = ?15v t a = 25c v s = 20v p-p v s = 15v p-p 06815-117 v s = 10v p-p figure 21 . thd + n vs. frequency, 15 v dual supply
adg1411/adg1412/adg1413 rev. b | page 11 of 16 1 0.1 0.01 0.001 10 100 1k 10k 100k thd + n (%) frequency (hz) v dd = +5v v ss = ?5v t a = 25c v s = 10v p-p v s = 5v p-p v s = 2.5v p-p 06815-118 figure 22 . thd + n vs. frequency , 5 v dual supply
adg1411/adg1412/adg1413 rev. b | page 12 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d , v s the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness is defined as the difference between the maximum and minimum value o f on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl , i inh the input current of the digital input when high or when low. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off sw itch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t on the delay between applying the digital control input and th e output switching on. see figure 30. t off the delay between applying the digital control input and the output switching off. charge injection a measure of the glitch impulse transferred from the digital input to the analog out put during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency a t which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. total harmonic distortion + noise ( thd + n ) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. ac power supply rejection ratio ( acpsrr ) a measure of the p ar ts ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulat ed by a sine wave of 0.62 v p - p. the ratio of the amplitude of the signal on the output to the amplitude of the modulation is the acpsrr.
adg1411/adg1412/adg1413 rev. b | page 13 of 16 test circuits sx dx v s i s v1 r on = v1/i s 06815-020 figure 23 . on resistance sx dx v s a a v d i s (off) i d (off) 06815-021 figure 24 . off lea kage sx dx a v d i d (on) nc nc = no connect 06815-022 figure 25 . on leakage v out 50 network analyzer r l 50 inx v in sx dx 50 off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 06815-026 figure 26 . off isolation channel-to-channel crosstalk = 20 log v out gnd s1 dx s2 v out network analyzer r l 50 r l 50 v s v s v dd v ss 0.1f v dd 0.1f v ss 06815-027 figure 27 . channel - to - channel crosstalk v out 50 network analyzer r l 50 inx v in sx dx insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 06815-028 figure 28 . bandwidth
adg1411/adg1412/adg1413 rev. b | page 14 of 16 v out r s audio precision r l 110 ? inx v in sx dx v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 06815-029 figure 29 . thd + noise v s inx sx dx gnd r l 300 c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss adg1412 adg14 1 1 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 06815-023 figure 30 . switching times v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300 c l 35pf v out2 v out1 v dd v ss 0.1f v dd 0.1f v ss v in v out1 v out2 adg1413 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300 c l 35pf 06815-024 figure 31 . break - before - make time delay inx v out adg1412 adg1411 v in v in v out off v out on q inj = c l v out sx dx v dd v ss v dd v ss v s r s gnd c l 1nf 06815-025 figure 32 . charge injection
adg1411/adg1412/adg1413 rev. b | page 15 of 16 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 33 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max pin 1 indic a t or 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq t o p view 12 max 0.80 max 0.65 ty p sea ting plane pin 1 indic a t or coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed p ad bot t om view 031006- a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 34 . 16 - lead lead frame chip scale package [lfcsp _vq ] 4 mm 4 mm body, very thin quad (cp - 16 - 13 ) dimensions shown in milli meters
adg1411/adg1412/adg1413 rev. b | page 16 of 16 ordering guide model 1 , 2 temperature range package description package option adg1411yruz ?40c to +125c 16- lead thin shrink small outline package (tssop) ru -16 adg1411yruz - reel7 ?40c to +125c 16- lead thin shrink small outline package (tsso p) ru -16 adg1411ycpz - reel ?40c to +125c 16- lead lead frame chip scale package ( lfcsp_vq ) cp -16-13 adg1411ycpz - reel7 ? 40c to +125c 16- lead lead frame chip scale package ( lfcsp_vq ) cp -16-13 adg1411wbcpz - reel ? 40c to +125c 16- lead lead frame chi p scale package (lfcsp_vq) cp -16-13 adg1412yruz ? 40c to +125c 16- lead thin shrink small outline package (tssop) ru -16 adg1412yruz - reel7 ? 40c to +125c 16- lead thin shrink small outline package (tssop) ru -16 adg1412ycpz - reel ? 40c to +125c 16-le ad lead frame chip scale package ( lfcsp_vq ) cp -16-13 adg1412ycpz - reel7 ? 40c to +125c 16- lead lead frame chip scale package ( lfcsp_vq ) cp -16-13 adg1413yruz ? 40c to +125c 16- lead thin shrink small outline package (tssop) ru -16 adg1413yruz - reel7 ? 40c to +125c 16- lead thin shrink small outline package (tssop) ru -16 adg1413ycpz - reel ? 40c to +125c 16- lead lead frame chip scale package ( lfcsp_vq ) cp -16-13 adg1413ycpz - reel7 ? 40c to +125c 16- lead lead frame chip scale package ( lfcsp_vq ) cp -16-13 1 z = rohs compliant part. 2 w = qualified for automotive applications. automotive products the ad g1411 w model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that th is automotive model may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade product shown is available for use in automotive applications. contact your local analog devices account representative for specific product ordering informati on and to obtain the specific automotive reliability reports for th is model . ? 2008 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06815 - 0 - 3/11(b)

▲Up To Search▲

Price & Availability of ADG1411YRUZ-REEL7

	To Download ADG1411YRUZ-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .