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? 2007 microchip technology inc. ds22040c-page 1 25aa010a/25lc010a 25aa320a/25lc320a 25aa020a/25lc020a 25aa640a/25lc640a 25aa040a/25lc040a 25aa128/25lc128 25aa080a/25lc080a 25aa256/25lc256 25aa080b/25lc080b 25aa512/25lc512 25aa160a/25lc160a 25aa1024/25lc1024 25aa160b/25lc160b features: ? max clock speed - 10 mhz (1k-256k) - 20 mhz (512k-1m) ? byte and page-level write operations ? low-power cmos technology - typical write current: 5 ma - typical read current: 5 ma @ 10 mhz 7 ma @ 20 mhz - typical standby current: 1 a ? write cycle time: 5 ms max. 6 ms max. (25xx1024) ? self-timed erase and write cycles ? erase functions (25xx512 and 25xx1024) - page erase: 6 ms max. - sector erase: 15 ms max. - chip erase: 15 ms max. ? built-in write protection - power on/off data protection circuitry - write enable latch - write-protect pin ? block/sector write protection - protect none, 1/4, 1/2 or all of array ? sequential read ? high reliability - data retention: > 200 years - esd protection: > 4000v - endurance > 1m erase/write cycles ? available in standard 8-pin and 6-pin packages ? temperature ranges supported: - industrial (i): -40c to +85c - automotive (e): -40c to +125c pin function table description: microchip technology inc. supports the serial periph- eral interface (spi) compatible serial bus architecture with low-voltage serial electrically erasable proms (eeprom) that range in density from 1 kbits up to 1 mbits. byte-level and page-level functions are sup- ported, but the higher density 512 kbit and 1 mbit devices also feature sector and chip erase functions typically associated with flash-based products. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. the entire series of spi compatible devices are avail- able in the standard 8-lead pdip and soic pack- ages, as well as the more advanced packages such as the 8-lead tssop, msop, 2x3 dfn, 5x6 dfn and 6-lead sot-23. all packages are rohs compliant with a pb-free (matte tin) finish. pin diagrams (not to scale) name function cs chip select so serial data output wp write-protect v ss ground si serial data input sck serial clock input hold hold input v cc supply voltage dfn cs so wp v ss hold sck si 5 6 7 8 4 3 2 1 v cc (mf) cs so wp v ss 1 2 3 4 8 7 6 5 v cc hold sck si (p, sn, sm) cs so wp v ss 1 2 3 4 8 7 6 5 v cc hold sck si pdip/soic v ss 1 2 34 6 5 v dd cs so (ot) sot-23 sck si cs so wp v ss 1 2 3 4 8 7 6 5 v cc hold sck si (mc) dfn tssop/msop (st, ms) spi serial eeprom family data sheet
25aaxxxx/25lcxxxx ds22040c-page 2 ? 2007 microchip technology inc. device selection table part number density (bits) organization v cc range max speed (mhz) page size (bytes) temp. range packages 25lc010a 1k 128 x 8 2.5-5.5v 10 16 i, e p, ms, sn, st, mc, ot 25aa010a 1k 128 x 8 1.8-5.5v 10 16 i p, ms, sn, st, mc, ot 25lc020a 2k 256 x 8 2.5-5.5v 10 16 i, e p, ms, sn, st, mc, ot 25aa020a 2k 256 x 8 1.8-5.5v 10 16 i p, ms, sn, st, mc, ot 25lc040a 4k 512 x 8 2.5-5.5v 10 16 i, e p, ms, sn, st, mc, ot 25aa040a 4k 512 x 8 1.8-5.5v 10 16 i p, ms, sn, st, mc, ot 25lc080a 8k 1024 x 8 2.5-5.5v 10 16 i, e p, ms, sn, st 25aa080a 8k 1024 x 8 1.8-5.5v 10 16 i p, ms, sn, st 25lc080b 8k 1024 x 8 2.5-5.5v 10 32 i, e p, ms, sn, st 25aa080b 8k 1024 x 8 1.8-5.5v 10 32 i p, ms, sn, st 25lc160a 16k 2048 x 8 2.5-5.5v 10 16 i, e p, ms, sn, st 25aa160a 16k 2048 x 8 1.8-5.5v 10 16 i p, ms, sn, st 25lc160b 16k 2048 x 8 2.5-5.5v 10 32 i, e p, ms, sn, st 25aa160b 16k 2048 x 8 1.8-5.5v 10 32 i p, ms, sn, st 25lc320a 32k 4096 x 8 2.5-5.5v 10 32 i, e p, ms, sn, st 25aa320a 32k 4096 x 8 1.8-5.5v 10 32 i p, ms, sn, st 25lc640a 64k 8192 x 8 2.5-5.5v 10 32 i, e p, ms, sn, st 25aa640a 64k 8192 x 8 1.8-5.5v 10 32 i p, ms, sn, st 25lc128 128k 16,384 x 8 2.5-5.5v 10 64 i, e p, sn, sm, st, mf 25aa128 128k 16,384 x 8 1.8-5.5v 10 64 i p, sn, sm, st, mf 25lc256 256k 32,768 x 8 2.5-5.5v 10 64 i, e p, sn, sm, st, mf 25aa256 256k 32,768 x 8 1.8-5.5v 10 64 i p, sn, sm, st, mf 25lc512 512k 65,536 x 8 2.5-5.5v 20 128 i, e p, sm, mf 25aa512 512k 65,536 x 8 1.8-5.5v 20 128 i p, sm, mf 25lc1024 1024k 131,072 x 8 2.5-5.5v 20 256 i, e p, sm, mf 25aa1024 1024k 131,072 x 8 1.8-5.5v 20 256 i p, sm, mf
? 2007 microchip technology inc. ds22040c-page 3 25aaxxxx/25lcxxxx 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature under bias................................................................................................. ............-40c to +125c esd protection on all pins..................................................................................................... ..................................... 4 kv table 1-1: dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: this is an overview of ac and dc characteristics. please refer to the device data sheet for production specs. dc characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units test conditions densities d001 v ih high-level input voltage .7 v cc v cc + 1 v all d002 v il low-level input voltage -0.3 0.3 v cc vv cc 2.7v (note 1) all d003 v il -0.3 0.2 v cc vv cc 2.7v (note 1) all d004 v ol low-level output voltage ? 0.4 v i ol = 2.1 ma, v cc = 4.5v all d005 v ol ?0.2vi ol = 1.0 ma, v cc = 2.5v all d006 v oh high-level output voltage v cc -0.5 ? v i oh = -400 aall d007 i li input leakage current ? 1 acs = v cc , v in = v ss or v cc all d008 i lo output leakage current ? 1 acs = v cc , v out = v ss or v cc all d009 c int internal capacitance (all inputs and outputs) ?7pft a = 25c, clk = 1.0 mh z , v cc = 5.0v (n ote 1) all d010 i cc read operating current ?10 5 ma v cc = 5.5v; f clk = 20.0 mhz; vcc = 2.5v; f clk = 10.0 mhz 512k and 1m 2.5 0.5 6 2.5 ma v cc = 5.5v; f clk = 10.0 mhz; vcc = 2.5v; f clk = 5.0 mhz 1k-256k d011 i cc w rite ?7 5 ma v cc = 5.5v vcc = 2.5v 512k and 1m 0.16 0.15 5 3 ma v cc = 5.5v v cc = 2.5v 1k-256k d012 i ccs standby current ? 20 12 acs = v cc = 5.5v, 125c cs = v cc = 5.5v, 85c (inputs tied to v cc or v ss ) 512k and 1m ?5 1 acs = v cc = 5.5v, 125c cs = v cc = 5.5v, 85c (inputs tied to v cc or v ss ) 1k-256k d13 i ccspd deep power-down current ? 1 acs = v cc = 5.5v (inputs tied to v cc or v ss ) 512k and 1m note 1: this parameter is periodically sampled and not 100% tested.
25aaxxxx/25lcxxxx ds22040c-page 4 ? 2007 microchip technology inc. table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions densities 1f clk clock frequency ? ? ? 20 10 2 mhz 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m ? ? ? 10 5 3 mhz 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 2t css cs setup time 25 50 250 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 50 100 150 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 3t csh cs hold time (note 3) 50 100 150 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 100 200 250 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 4t csd cs disable time 50 ? ns 1k-256k 5t su data setup time 5 10 50 ?ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 10 20 30 ?ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 6t hd data hold time 10 20 100 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 20 40 50 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 7t r clk rise time (note 1) ? 20 ns 512k and 1m ? 100 ns 128k and 256k ? 500 ns 8k and 16k ? 2000 ns 1k-4k, 32k-64k 8t f clk fall time (note 1) ? 20 ns 512k and 1m ? 100 ns 128k and 256k ? 500 ns 8k and 16k ? 2000 ns 1k-4k, 32k-64k note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but established by characterization and qualification. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site: www.microchip.com. 3: includes t hi time.
? 2007 microchip technology inc. ds22040c-page 5 25aaxxxx/25lcxxxx 9t hi clock high time 25 50 250 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 50 100 150 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 10 t lo clock low time 25 50 250 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 50 100 150 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 11 t cld clock delay time 50 ? ns all 12 t cle clock enable time 50 ? ns all 13 t v output valid from clock low ?25 50 250 ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m ?50 100 160 ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 14 t ho output hold time (note 1) 0?ns 15 t dis output disable time (note 1) ?25 50 250 ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m ?40 80 160 ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 16 t hs hold setup time 10 20 100 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 20 40 80 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 17 t hh hold hold time 10 20 100 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 20 40 80 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k table 1-2: ac characteristics (continued) ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions densities note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but established by characterization and qualification. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site: www.microchip.com. 3: includes t hi time.
25aaxxxx/25lcxxxx ds22040c-page 6 ? 2007 microchip technology inc. 18 t hz hold low to output high-z (note 1) 15 30 150 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 30 60 160 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 19 t hv hold high to output valid 15 30 150 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 512k and 1m 30 60 160 ? ns ns ns 4.5 v cc 5.5 2.5 v cc < 4.5 1.8 v cc < 2.5 1k-256k 20 t rel cs high to standby mode ?100 s1.8v v cc 5.5v 512k and 1m 21 t pd cs high to deep power-down ?100 s1.8v v cc 5.5v 512k and 1m 22 t ce chip erase cycle time ?15ms1.8v v cc 5.5v 512k and 1m 23 t se sector erase cycle time ?15ms1.8v v cc 5.5v 512k and 1m 24 t wc internal write cycle time ? 6 ms byte or page mode and page erase 512k and 1m ? 5 ms byte or page mode 1k-256k 25 ? endurance (note 2) > 1m ? e/w cycles per page 512k and 1m per byte 1k-256k table 1-2: ac characteristics (continued) ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions densities note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but established by characterization and qualification. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site: www.microchip.com. 3: includes t hi time. table 1-3: ac test conditions ac waveform: v lo = 0.2v ? v hi = v cc - 0.2v (note 1) v hi = 4.0v (note 2) c l = 30 pf ? timing measurement reference level input output 0.5 v cc 0.5 v cc note 1: for v cc 4.0v. 2: for v cc > 4.0v.
? 2007 microchip technology inc. ds22040c-page 7 25aaxxxx/25lcxxxx figure 1-1: hold timing figure 1-2: serial input timing figure 1-3: serial output timing cs sck so si hold 17 16 16 17 19 18 don?t care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 mode 1,1 mode 0,0 2 4 cs sck so 10 9 13 msb out lsb out 3 15 don?t care si mode 1,1 mode 0,0 14
25aaxxxx/25lcxxxx ds22040c-page 8 ? 2007 microchip technology inc. 2.0 functional description 2.1 principles of operation the 25-series of serial eeproms is designed to inter- face directly with the serial peripheral interface (spi) port of many of today's popular microcontroller families, including microchip's pic ? microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly in firmware to match the spi protocol. this family of eeproms contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire operation. table 2-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses and data are transferred msb first, lsb last. data (si) is sampled on the first rising edge of sck after cs goes low. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input and place the eeprom in ?hold? mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. block diagram table 2-1: instruction set 2.2 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the eeprom followed by the address. after the correct read instruc- tion and address are sent, the data stored in the mem- ory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incre- mented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address 00000h, allowing the read cycle to be continued indefi- nitely. the read operation is terminated by raising the cs pin. see figure 2-1a/b/c for byte read. si so sck cs hold wp status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss instruction name instruction format description instructions for all devices. read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register additional instructions for 25xx512 and 25xx1024 pe 0100 0010 page erase ? erase one page in memory array se 1101 1000 sector erase ? erase one sector in memory array ce 1100 0111 chip erase ? erase all sectors in memory array rdid 1010 1011 release from deep power-down and read electronic signature dpd 1011 1001 deep power-down mode
? 2007 microchip technology inc. ds22040c-page 9 25aaxxxx/25lcxxxx table 2-2: read/write sequence addressing figure 2-1a: read sequence with either 8-bit or 9-bit addressing figure 2-1b: read sequence with 16-bit addressing density address bits highest address page size 1k 7 007f 16 bytes 2k 8 00ff 16 bytes 4k 9 01ff 16 bytes 8k 10 03ff 16 or 32 bytes* 16k 11 07ff 16 or 32 bytes* 32k 12 0fff 32 bytes 64k 12 1fff 32 bytes 128k 14 3fff 64 bytes 256k 15 7fff 64 bytes 512k 16 ffff 256 bytes 1024k 17 1ffff 256 bytes note: version a ? 16 bytes version b ? 32 bytes so si sck cs 0 234567891011 1 01 a 8* 0 0 0 01 a 7 a 6 a 5 a 4 a 1 a 0 76543210 data out high-impedance a 3 a 2 lower address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction+address msb * a 8 is a don?t care for 1k and 2k upper address bit. so si sck cs 0 234567891011 21222324252627282930 31 1 01 0 0 0 0 01 a 15 a 14 a 13 a 12 a 2 a 1 a 0 76543210 instruction 16-bit address data out high-impedance
25aaxxxx/25lcxxxx ds22040c-page 10 ? 2007 microchip technology inc. figure 2-1c: read sequence with 24-bit addressing 2.3 write sequence prior to any attempt to write data to the eeprom, the write enable latch must be set by issuing the wren instruction (figure 2-4). this is done by setting cs low and then clocking out the proper instruction into the eeprom. after all eight bits of the instruction are transmitted, cs must be brought high to set the write enable latch. if the write operation is initiated immedi- ately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. a write sequence includes an automatic, self timed erase cycle. it is not required to erase any portion of the memory prior to issuing a write command. once the write enable latch is set, the user may pro- ceed by setting cs low, issuing a write instruction, followed by the address and then the data to be written. depending upon the density, a page of data that ranges from 16 bytes to 256 bytes can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. see table 2-2 for information on page sizes. in the 24xx512 and 24xx1024 devices, the entire page is always refreshed regardless of whether the entire page is written. for this reason, endurance for these devices is specified per page. so si sck cs 0 234567891011 29303132333435363738 39 1 01 0 0 0 0 01 a 23 a 22 a 21 a 20 a 2 a 1 a 0 76543210 instruction 24-bit address data out high-impedance note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or ?page size?), and end at addresses that are inte- ger multiples of page size ? 1. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previ- ously stored there), instead of being writ- ten to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
? 2007 microchip technology inc. ds22040c-page 11 25aaxxxx/25lcxxxx for the data to be actually written to the array, cs must be brought high after the least significant bit (d0) of the nth data byte has been clocked in. if cs is brought high at any other time, the write operation will not be completed. refer to figure 2-2a/b/c and figure 2-3a/ b/c/d for more detailed illustrations on the byte write sequence and the page write sequence, respectively. while the write is in progress, the status register may be read to check the status of the wip and wel bits (figure 2-6). a read attempt of a memory array location will not be possible during a write cycle. when the write cycle is completed, the write enable latch is reset. figure 2-2a: byte write sequence with either 8-bit or 9-bit addressing figure 2-2b: byte write sequence with 16-bit addressing figure 2-2c: byte write sequence with 24-bit addressing si cs 91011 00 a 8* 0 0 0 01 76543210 data byte sck 0 234567 18 instruction+address msb lower address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23 twc so high-impedance * upper address bit a 8 is a don?t care for 1k and 2k. so si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 a 15 a 14 a 13 a 12 a 2 a 1 a 0 76543210 instruction 16-bit address data byte high-impedance sck 0 234567 18 twc so si cs 9 1011 29303132333435363738 39 00 0 0 0 0 01 a 23 a 22 a 21 a 20 a 2 a 1 a 0 76543210 instruction 24-bit address data byte high-impedance sck 0 234567 1 8 twc
25aaxxxx/25lcxxxx ds22040c-page 12 ? 2007 microchip technology inc. figure 2-3a: page write sequence with either 8-bit or 9-bit addressing figure 2-3b: page write sequence with 16-bit addressing si cs 91011 00 a 8 * 0 0 0 01 76543210 data byte 1 sck 0 234567 18 si cs 33 34 35 38 39 76543210 data byte n (16 max) sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23 * upper address bit a 8 is a don?t care for 1k and 2k. si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 a 15 a 14 a 13 a 12 a 2 a 1 a 0 76543210 instruction 16-bit address data byte 1 sck 0 234567 1 8 si cs 41 42 43 46 47 76543210 data byte n (16/32 max) sck 32 34 35 36 37 38 39 33 40 76543210 data byte 3 76543210 data byte 2 44 45
? 2007 microchip technology inc. ds22040c-page 13 25aaxxxx/25lcxxxx figure 2-3c: page write sequence with 24-bit addressing 2.4 write enable ( wren ) and write disable ( wrdi ) the eeprom contains a write enable latch. see table 2-4 for the write-protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: ? power-up ? wrdi instruction successfully executed ? wrsr instruction successfully executed ? write instruction successfully executed ?wp pin is brought low (1k, 2k, 4k only) additional instructions available on 25xx512 and 25xx1024: ? pe instruction successfully executed ? se instruction successfully executed ? ce instruction successfully executed figure 2-4: write enable sequence ( wren ) si cs 9 1011 29303132333435363738 39 00 0 0 0 0 01 a 23 a 22 a 21 a 20 a 2 a 1 a 0 76543210 instruction 24-bit address data byte 1 sck 0 234567 1 8 si cs 49 50 51 54 55 76543210 data byte n (256 max) sck 40 42 43 44 45 46 47 41 48 76543210 data byte 3 76543210 data byte 2 52 53 sck 0 234567 1 si high-impedance so cs 01 0000 0 1
25aaxxxx/25lcxxxx ds22040c-page 14 ? 2007 microchip technology inc. figure 2-5: write disable sequence ( wrdi ) 2.5 read status register instruction ( rdsr ) the read status register instruction ( rdsr ) provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: table 2-3: status register the write-in-process (wip) bit indicates whether the eeprom is busy with a write operation. when set to a ? 1 ?, a write is in progress, when set to a ? 0 ?, no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch and is read-only. when set to a ? 1 ?, the latch allows writes to the array, when set to a ? 0 ?, the latch prohibits writes to the array. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the status register. these commands are shown in figure 2-4 and figure 2-5. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction. these bits are nonvolatile and are shown in table 2-4. see figure 2-6 for the rdsr timing sequence. figure 2-6: read status register timing sequence ( rdsr ) sck 0 234567 1 si high-impedance so cs 01 0000 0 1 0 76543210 w/r ? ? ? w/r w/r r r wpen x x x bp1 bp0 wel wip w/r = writable/readable. r = read-only. note: wpen bit not available in 24xx010a, 24xx020a and 24xx040a devices. so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 1 8 3
? 2007 microchip technology inc. ds22040c-page 15 25aaxxxx/25lcxxxx 2.6 write status register instruction ( wrsr ) the write status register instruction ( wrsr ) allows the user to write to the nonvolatile bits in the status reg- ister as shown in table 2-3. the user is able to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two, or all four of the segments of the array. the partitioning is controlled as is shown in table 2-4. in eeprom densities starting at 8 kbits and higher, the write-protect enable (wpen) bit is a nonvolatile bit that is available as an enable bit for the wp pin. the write-protect (wp ) pin and the write-protect enable (wpen) bit in the status register control the pro- grammable hardware write-protect feature. hardware write protection is enabled when wp pin is low and the wpen bit is high. hardware write protection is disabled when either the wp pin is high or the wpen bit is low. when the chip is hardware write-protected, only writes to nonvolatile bits in the status register are disabled. see table 2-6 for a matrix of functionality on the wpen bit. see figure 2-7 for the wrsr timing sequence. table 2-4: array protection table 2-5: array protected address locations figure 2-7: write status register timing sequence ( wrsr ) bp1 bp0 array addresses write-protected array addresses unprotected 00 none all (sectors 0, 1, 2 and 3) 01 upper 1/4 (sector 3) lower 3/4 (sectors 0, 1 and 2) 10 upper 1/2 (sectors 2 and 3) lower 1/2 (sectors 0 and 1) 11 all (sectors 0, 1, 2 and 3) none density upper 1/4 (sector 3) upper 1/2 (sectors 2 and 3) all sectors 1k 60h-7fh 40h-7fh 00h-7fh 2k c0h-ffh 80h-ffh 00h-ffh 4k 180h-1ffh 100h-1ffh 000h-1ffh 8k 300h-3ffh 200h-3ffh 000h-3ffh 16k 600h-7ffh 400h-7ffh 000h-7ffh 32k c00h-fffh 800h-fffh 000h-fffh 64k 1800h-1fffh 1000h-1fffh 0000h-1fffh 128k 3000h-3fffh 2000h-3fffh 0000h-3fffh 256k 6000h-7fffh 4000h-7fffh 0000h-7fffh 512k c000h-ffffh 8000h-ffffh 0000h-ffffh 1024k 18000h-1ffffh 10000h-1ffffh 00000h-1ffffh so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 18 3
25aaxxxx/25lcxxxx ds22040c-page 16 ? 2007 microchip technology inc. 2.7 data protection the following protection has been implemented to prevent inadvertent writes to the array: ? the write enable latch is reset on power-up ? a write enable instruction must be issued to set the write enable latch ? after a byte write, page write or status register write, the write enable latch is reset ?cs must be set high after the proper number of clock cycles to start an internal write cycle ? access to the array during an internal write cycle is ignored and programming is continued 2.8 power-on state the serial eeprom powers on in the following state: ? the device is in low-power standby mode (cs = 1 ) ? the write enable latch is reset ? so is in high-impedance state ? a high-to-low-level transition on cs is required to enter active state table 2-6: write-protec t functionality matrix 2.9 page erase the page erase is a typical flash function that has been implemented only on the 512 kbit and 1024 kbit serial eeproms. this function is used to erase all bits (ffh) inside a given page. a write enable ( wren ) instruction must be given prior to attempting a page erase. this is done by setting cs low and then clocking out the proper instruction into the eeprom. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. the page erase function is entered by driving cs low, followed by the instruction code (figure 2-8a/b) and two or three address bytes. any address inside the page to be erased is a valid address. cs must then be driven high after the last bit if the address or the page erase will not execute. once the cs is driven high, the self-timed page erase cycle is started. the wip bit in the status register can be read to determine when the page erase cycle is complete. if a page erase function is given to an address that has been protected by the block protect bits (bp0, bp1) then the sequence will be aborted and no erase will occur. figure 2-8a: page erase sequence with 24-bit addressing wel (sr bit 1) wpen (sr bit 7) * wp (pin 3) protected blocks unprotected blocks status register 0xx protected protected protected 10x protected writable writable 110 (low) protected writable protected 111 (high) protected writable writable x = don?t care * = wpen bit is not available on 24xx010a/020a/040a. so si sck cs 0 234567891011 293031 1 00 0 0 0 1 01 a 23 a 22 a 21 a 20 a 2 a 1 a 0 instruction 24-bit address high-impedance
? 2007 microchip technology inc. ds22040c-page 17 25aaxxxx/25lcxxxx figure 2-8b: page erase sequence with 16-bit addressing 2.10 sector erase the sector erase is a typical flash function that has been implemented only on the 512 kbit and 1024 kbit serial eeproms. this function is used to erase all bits (ffh) inside a given sector. a write enable (wren) instruction must be given prior to attempting a sector erase. this is done by setting cs low and then clocking out the proper instruction into the eeprom. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. the sector erase function is entered by driving cs low, followed by the instruction code (figure 2-9a/b), and two or three address bytes. any address inside the sector to be erased is a valid address. cs must then be driven high after the last bit if the address or the sector erase will not execute. once the cs is driven high, the self-timed sector erase cycle is started. the wip bit in the status register can be read to determine when the sector erase cycle is complete. if a sector erase instruction is given to an address that has been protected by the block protect bits (bp0, bp1) then the sequence will be aborted and no erase will occur. see table 2-2 and table 2-3 for sector addressing. figure 2-9a: sector erase sequence with 24-bit addressing so si sck cs 0 234567891011 212223 1 00 0 0 0 1 01 a 15 a 14 a 13 a 12 a 2 a 1 a 0 instruction 16-bit address high-impedance so si sck cs 0 234567891011 293031 1 00 1 1 0 1 10 a 23 a 22 a 21 a 20 a 2 a 1 a 0 instruction 24-bit address high-impedance
25aaxxxx/25lcxxxx ds22040c-page 18 ? 2007 microchip technology inc. figure 2-9b: sector erase sequence with 16-bit addressing 2.11 chip erase the chip erase function will erase all bits (ffh) in the array. a write enable ( wren ) instruction must be given prior to executing a chip erase. this is done by setting cs low and then clocking out the proper instruction into the eeprom. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. the chip erase function is entered by driving the cs low, followed by the instruction code (figure 2-10) onto the si line. the cs pin must be driven high after the eighth bit of the instruction code has been given or the chip erase function will not be executed. once the cs pin is driven high, the self-timed chip erase function begins. while the device is executing the chip erase function the wip bit in the status register can be read to determine when the chip erase function is complete. the chip erase function is ignored if either of the block protect bits (bp0, bp1) are not ? 0 ?, meaning ?, ?, or all of the array is protected. figure 2-10: chip erase sequence 2.12 deep power-down mode deep power-down mode is available on the high-density 25xx512 and 25xx1024 serial eeproms and is the lowest power consumption state for these devices. while in the deep power-down mode, these devices will not respond to any of the read or write commands, and therefore it can be used as an additional software write protection feature. the deep power-down mode is entered by driving cs low, followed by the instruction code (figure 2-11) onto the si line, followed by driving cs high. if the cs pin is not driven high after the eighth bit of the instruction code has been given, the device will not execute deep power-down. once the cs line is driven high, there is a delay (t dp ) before the current settles to its lowest consumption. all instructions given during deep power-down mode are ignored except the read electronic signature command (rdid). the rdid command will release the device from deep power-down and outputs the electronic signature on the so pin, and then returns the device to standby mode after delay (t rel ). so si sck cs 0 234567891011 212223 1 00 1 1 0 1 10 a 15 a 14 a 13 a 12 a 2 a 1 a 0 instruction 16-bit address high-impedance sck 0 234567 1 si high-impedance so cs 11 1000 1 1
? 2007 microchip technology inc. ds22040c-page 19 25aaxxxx/25lcxxxx deep power-down mode automatically releases at device power-down. once power is restored to the device, it will power-up in the standby mode. figure 2-11: deep power-down sequence sck 0 234567 1 si high-impedance so cs 10 0111 1 0
25aaxxxx/25lcxxxx ds22040c-page 20 ? 2007 microchip technology inc. 2.13 release from deep power-down and read electronic signature once a device has entered deep power-down mode all instructions are ignored except the release from deep power-down and read electronic signature command. this command can also be used when the device is not in deep power-down, to read the electronic signature out on the so pin unless another command is being executed such as erase, program or write status register. release from deep power-down mode and read electronic signature is entered by driving cs low, followed by the rdid instruction code (figure 2-12a/ b).then a dummy address of 24 bits (a23-a0) for the 25xx1024 and 16 bits (a15-a0) for the 25xx512 can be sent. after the last bit of the dummy address is clocked in, the 8-bit electronic signature is clocked out on the so pin. after the signature has been read out at least once, the sequence can be terminated by driving cs high. the device will then return to standby mode and will wait to be selected so it can be given new instructions. if additional clock cycles are sent after the electronic signature has been read once, it will continue to output the signature on the so line until the sequence is terminated. figure 2-12a: release from deep power-down and read electronic signature (24-bits) figure 2-12b: release from deep power-down and read electronic signature (16-bits) driving cs high after the 8-bit rdid command, but before the electronic signature has been transmitted, will still ensure the device will be taken out of deep power-down mode. however, there is a delay t rel that occurs before the device returns to standby mode (iccs), as shown in figure 2-13. so si sck cs 0 234567891011 29303132333435363738 39 1 01 1 0 1 0 11 a 23 a 22 a 21 a 20 a 2 a 1 a 0 76543210 instruction 24-bit address electronic signature out high-impedance 0 101001 0 manufacturers id 0x29 t rel so si sck cs 0 234567891011 21222324252627282830 31 1 01 1 0 1 0 11 a 15 a 14 a 13 a 12 a 2 a 1 a 0 76543210 instruction 16-bit address electronic signature out high-impedance 0 101001 0 manufacturers id 0x29 t rel
? 2007 microchip technology inc. ds22040c-page 21 25aaxxxx/25lcxxxx figure 2-13: release from deep power-down so si sck cs 0 234567 1 01 1 0 1 0 11 instruction high-impedance t rel
25aaxxxx/25lcxxxx ds22040c-page 22 ? 2007 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initi- ated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go into standby mode as soon as the programming cycle is complete. when the device is deselected, so goes to the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 3.2 serial output (so) the so pin is used to transfer data out of the eeprom. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 write-protect (wp ) the wp pin is a hardware write-protect input pin. in the lower densities of 4 kbits and below, a logic low on this pin will reset the write enable latch and programming will be inhibited. however, if a write cycle is already in progress, wp going low will not change or disable the write cycle. see table 2-4 for the write-protect functionality matrix. in densities of 8 kbits and higher the wp pin is used in conjunction with the wpen bit in the status register to prohibit writes to the nonvolatile bits in the status register. when wp is low and wpen is high, writing to the nonvolatile bits in the status register are dis- abled. all other operations will function normally. when wp is set to a logic high, all functions, including writes to the nonvolatile bits in the status register will oper- ate normally. if the wpen bit is set, a logic low on the wp pin during a status register write sequence will disable writing to the status register. if an internal write cycle has already begun, wp going low will have no effect on the write in progress. the wp pin function is blocked when the wpen bit in the status register is low. this allows the user to install the eeprom in a system with wp pin grounded and still be able to write to the status register. the wp pin functions will be enabled when the wpen bit is set to a logic high. 3.4 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock 3.5 serial clock (sck) the sck is used to synchronize the communication between a master and the eeprom. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 3.6 hold (hold ) the hold pin is used to suspend transmission to the eeprom while in the middle of a serial sequence with- out having to retransmit the entire sequence again. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to- low transition. the eeprom must remain selected during this sequence. the si, sck and so pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial commu- nication will not resume. pulling the hold line low at any time will tri-state the so line. name pin number function cs 1 chip select input so 2 serial data output wp 3 write-protect pin v ss 4 ground si 5 serial data input sck 6 serial clock input hold 7 hold input v cc 8 supply voltage
? 2007 microchip technology inc. ds22040c-page 23 25aaxxxx/25lcxxxx 4.0 packaging information 4.1 package marking information xxxxxnnn xxxxxxxx yyww 8-lead pdip i/p 1l7 25lc080a 0628 example: pb-free 3 e 8-lead pdip package marking (pb-free) device line 1 marking device line 1 marking 25aa010a 25aa010a 25lc010a 25lc010a 25aa020a 25aa020a 25lc020a 25lc020a 25aa040a 25aa040a 25lc040a 25lc040a 25aa080a 25aa080a 25lc080a 25lc080a 25aa080b 25aa080b 25lc080b 25lc080b 25aa160a 25aa160a 25lc160a 25lc160a 25aa160b 25aa160b 25lc160b 25lc160b 25aa320a 25aa320a 25lc320a 25lc320a 25aa640a 25aa640a 25lc640a 25lc640a 25aa128 25aa128 25lc128 25lc128 25aa256 25aa256 25lc256 25lc256 25aa512 25aa512 25lc512 25lc512 25aa1024 25aa1024 25lc1024 25lc1024 note: t = temperature grade (i, e). legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
25aaxxxx/25lcxxxx ds22040c-page 24 ? 2007 microchip technology inc. xxxxyyww xxxxxxxt nnn 8-lead soic sn 0628 25l080ai 1l7 example: pb-free 3 e 8-lead soic package marking (pb-free) device line 1 marking device line 1 marking 25aa010a 25aa01at 25lc010a 25lc01at 25aa020a 25aa02at 25lc020a 25lc02at 25aa040a 25aa04at 25lc040a 25lc04at 25aa080a 25a080at 25lc080a 25l080at 25aa080b 25a080bt 25lc080b 25l080bt 25aa160a 25a160at 25lc160a 25l160at 25aa160b 25a160bt 25lc160b 25l160bt 25aa320a 25aa32at 25lc320a 25lc32at 25aa640a 25aa64at 25lc640a 25lc64at 25aa128 (2) 25aa128t 25lc128 25lc128t 25aa256 (2) 25aa256t 25lc256 25lc256t 25aa512 (2) 25aa512t 25lc512 25lc512t 25aa1024 (3) 25aa1024 25lc1024 25lc1024 note 1: t = temperature grade (i, e). 2: density available in sn and sm versions. 3: density only available in sm. legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2007 microchip technology inc. ds22040c-page 25 25aaxxxx/25lcxxxx 8-lead tssop package marking (pb-free) device line 1 marking device line 1 marking 25aa010a 5a1a 25lc010a 5l1a 25aa020a 5a2a 25lc020a 5l2a 25aa040a 5a4a 25lc040a 5l4a 25aa080a 5a8a 25lc080a 5l8a 25aa080b 5a8b 25lc080b 5l8b 25aa160a 5aaa 25lc160a 5laa 25aa160b 5aab 25lc160b 5lab 25aa320a 5aba 25lc320a 5lba 25aa640a 5aca 25lc640a 5lca 25aa128 5ad 25lc128 5ld 25aa256 5ae 25lc256 5le note: t = temperature grade (i, e). nnn xxxx tyww 8-lead tssop 1l7 5l8a i628 example: pb-free legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
25aaxxxx/25lcxxxx ds22040c-page 26 ? 2007 microchip technology inc. 8-lead msop package marking (pb-free) device line 1 marking device line 1 marking 25aa010a 5a1at 25lc010a 5l1at 25aa020a 5a2at 25lc020a 5l2at 25aa040a 5a4at 25lc040a 5l4at 25aa080a 5a8at 25lc080a 5l8at 25aa080b 5a8bt 25lc080b 5l8bt 25aa160a 5aaat 25lc160a 5laat 25aa160b 5aabt 25lc160b 5labt 25aa320a 5abat 25lc320a 5lbat 25aa640a 5acat 25lc640a 5lcat note: t = temperature grade (i, e). 8-lead msop example: pb-free xxxxxxt ywwnnn 5l8ai 6281l7 legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2007 microchip technology inc. ds22040c-page 27 25aaxxxx/25lcxxxx 6-lead sot-23 package marking (pb-free) device i-temp marking device i-temp marking e-temp marking 25aa010a 12nn 25lc010a 15nn 16nn 25aa020a 22nn 25lc020a 25nn 26nn 25aa040a 32nn 25lc040a 35nn 36nn 6-lead sot-23 xxnn example: pb-free 32l7 legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
25aaxxxx/25lcxxxx ds22040c-page 28 ? 2007 microchip technology inc. 8-lead 2x3 dfn package marking (pb-free) device i-temp marking device i-temp marking e-temp marking 25aa010a 401 25lc010a 404 405 25aa020a 411 25lc020a 414 415 25aa040a 421 25lc040a 424 425 note: nn = alphanumeric traceability code. 8-lead 2x3 dfn example: pb-free 421 627 l7 xxx yww nn legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2007 microchip technology inc. ds22040c-page 29 25aaxxxx/25lcxxxx 8-lead 6x5 dfn-s package marking (pb-free) device line 1 marking device line 1 marking 25aa128 25aa128 25lc128 25lc128 25aa256 25aa256 25lc256 25lc256 25aa512 25aa512 25lc512 25lc512 25aa1024 25aa1024 25lc1024 25lc1024 note: t = temperature grade (i, e) 8-lead 6x5 dfn-s example: pb-free xxxxxxx xxxxxxx xxyyww nnn 25aa128 xxx-i/ mf0610 017 legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
25aaxxxx/25lcxxxx ds22040c-page 30 ? 2007 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 n e1 note 1 d 12 3 a a1 a2 l b1 b e e e b c microchip technology drawing c04-018 b
? 2007 microchip technology inc. ds22040c-page 31 25aaxxxx/25lcxxxx 8-lead plastic small outline (sn) ? narrow, 3.90 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a ? ? 1.75 molded package thickness a2 1.25 ? ? standoff a1 0.10 ? 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 4.90 bsc chamfer (optional) h 0.25 ? 0.50 foot length l 0.40 ? 1.27 footprint l1 1.04 ref foot angle 0 ? 8 lead thickness c 0.17 ? 0.25 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h microchip technology drawing c04-057 b
25aaxxxx/25lcxxxx ds22040c-page 32 ? 2007 microchip technology inc. 8-lead plastic small outline (sm) ? medium, 5.28 mm body [soij] notes: 1. soij, jeita/eiaj standard, formerly called soic. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a 1.77 ? 2.03 molded package thickness a2 1.75 ? 1.98 standoff a1 0.05 ? 0.25 overall width e 7.62 ? 8.26 molded package width e1 5.11 ? 5.38 overall length d 5.13 ? 5.33 foot length l 0.51 ? 0.76 foot angle 0 ? 8 lead thickness c 0.15 ? 0.25 lead width b 0.36 ? 0.51 mold draft angle top ? ? 15 mold draft angle bottom ? ? 15 l c a2 a1 a b 12 e e e1 n d microchip technology drawing c04-056b
? 2007 microchip technology inc. ds22040c-page 33 25aaxxxx/25lcxxxx 8-lead plastic thin shrink small outline (st) ? 4.4 mm body [tssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.65 bsc overall height a ? ? 1.20 molded package thickness a2 0.80 1.00 1.05 standoff a1 0.05 ? 0.15 overall width e 6.40 bsc molded package width e1 4.30 4.40 4.50 molded package length d 2.90 3.00 3.10 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 ? 8 lead thickness c 0.09 ? 0.20 lead width b 0.19 ? 0.30 d n e e1 note 1 12 b e c a a1 a2 l1 l microchip technology drawing c04-086 b
25aaxxxx/25lcxxxx ds22040c-page 34 ? 2007 microchip technology inc. 8-lead plastic micro small outline package (ms) [msop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.65 bsc overall height a ? ? 1.10 molded package thickness a2 0.75 0.85 0.95 standoff a1 0.00 ? 0.15 overall width e 4.90 bsc molded package width e1 3.00 bsc overall length d 3.00 bsc foot length l 0.40 0.60 0.80 footprint l1 0.95 ref foot angle 0 ? 8 lead thickness c 0.08 ? 0.23 lead width b 0.22 ? 0.40 d n e e1 note 1 1 2 e b a a1 a2 c l1 l microchip technology drawing c04-111 b
? 2007 microchip technology inc. ds22040c-page 35 25aaxxxx/25lcxxxx 6-lead plastic small outline transistor (ot) [sot-23] notes: 1. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.127 mm per side. 2. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 6 pitch e 0.95 bsc outside lead pitch e1 1.90 bsc overall height a 0.90 ? 1.45 molded package thickness a2 0.89 ? 1.30 standoff a1 0.00 ? 0.15 overall width e 2.20 ? 3.20 molded package width e1 1.30 ? 1.80 overall length d 2.70 ? 3.10 foot length l 0.10 ? 0.60 footprint l1 0.35 ? 0.80 foot angle 0 ? 30 lead thickness c 0.08 ? 0.26 lead width b 0.20 ? 0.51 b e 4 n e1 pin 1 id by laser mark d 1 2 3 e e 1 a a1 a2 c l l1 microchip technology drawing c04-028 b
25aaxxxx/25lcxxxx ds22040c-page 36 ? 2007 microchip technology inc. 8-lead plastic dual flat, no lead package (mc) ? 2x3x0.9 mm body [dfn] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. package is saw singulated. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.50 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall length d 2.00 bsc overall width e 3.00 bsc exposed pad length d2 1.30 ? 1.75 exposed pad width e2 1.50 ? 1.90 contact width b 0.18 0.25 0.30 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 ? ? d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a 3 a1 a note 2 bottom view top view microchip technology drawing c04-123 b
? 2007 microchip technology inc. ds22040c-page 37 25aaxxxx/25lcxxxx 8-lead plastic dual flat, no lead package (mf) ? 6x5 mm body [dfn-s] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. package is saw singulated. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a 0.80 0.85 1.00 standoff a1 0.00 0.01 0.05 contact thickness a3 0.20 ref overall length d 5.00 bsc overall width e 6.00 bsc exposed pad length d2 3.90 4.00 4.10 exposed pad width e2 2.20 2.30 2.40 contact width b 0.35 0.40 0.48 contact length l 0.50 0.60 0.75 contact-to-exposed pad k 0.20 ? ? note 2 a1 a a 3 note 1 12 e n d exposed pad note 1 2 1 e2 l n e b k bottom view top view d2 microchip technology drawing c04-122 b
25aaxxxx/25lcxxxx ds22040c-page 38 ? 2007 microchip technology inc. appendix a: revision history revision a (05/2007) original release of document. (package drawings rev. ap) revision b (06/2007) ? updated the 6-lead sot-23 packaging information ? updated the product identification system information ? minor corrections throughout document revision c (08/2007) removed ?preliminary? status for 512, 640a and 1024 devices.
? 2007 microchip technology inc. ds22040c-page 39 25aaxxxx/25lcxxxx the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
25aaxxxx/25lcxxxx ds22040c-page 40 ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22040c 25aaxxxx/25lcxxxx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. ds22040c-page 41 25aaxxxx/25lcxxxx product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx package temperature range device part examples: a) 25aa010a-i/sn: 1k b) 25aa040a-i/ms: 4k c) 25lc040at-i/ot: 4k d) 25lc1024-i/sm: 1m e) 25lc040at-i/mc device: eeprom series ? 25 voltage ? aa = 1.8v-5.5v lc = 2.5v-5.5v density: 010a = 1 kbit 020a = 2 kbit 040a = 4 kbit 080a = 8 kbit 080b = 8 kbit 160a = 16 kbit 160b = 16 kbit 320a = 32 kbit 640a = 64 kbit 128 = 128 kbit 256 = 256 kbit 512 = 512 kbit 1024 = 1024 kbit (1mbit) temperature range: i = -40c to +85c e = -40c to +125c packaging medium: t = tape and reel (t/r) blank = std. pkg. package: p = 8-lead plastic dip (300 mil body) sn = 8-lead plastic soic (3.90 mm body) sm = 8-lead plastic soic (5.28 mm body) st = 8-lead plastic tssop (4.4 mm) ms = 8-lead plastic msop (3.0 mm) mc = 8-lead 2x3 mm dfn (t/r only) mf = 8-lead 6x5 mm dfn ot = 6-lead sot-23 (t/r only) number x packaging medium
25aaxxxx/25lcxxxx ds22040c-page 42 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds22040c-page 43 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip tec hnology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are tr ademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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