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dm2200 edram 4mb x 1 enhanced dynamic ram product specification ?1996 enhanced memory systems inc., 1850 ramtron drive, colorado springs, co 80921 telephone (800) 545-dram; fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2108-001 the information contained herein is subject to change without notice. enhanced reserves the right to change or discontinue this product without notice. features n 2kbit sram cache memory for 12ns random reads within a page n fast 4mbit dram array for 30ns access to any new page n write posting register for 12ns random writes and burst writes within a page (hit or miss) n 256-byte wide dram to sram bus for 14.2 gigabytes/sec cache fill n on-chip cache hit/miss comparators maintain cache coherency on writes n hidden precharge and refresh cycles n extended 64ms refresh period for low standby power n 300 mil plastic soj and tsop-ii package options n +5 and +3.3 volt power supply voltage options n low power, self refresh mode option n industrial temperature range option description the 4mb enhanced dram (edram) combines raw speed with innovative architecture to offer the optimum cost-performance solution for high performance local or system main memory. in most high speed applications, no-wait-state performance can be achieved without secondary sram cache and without interleaving main memory banks at system clock speeds through 50mhz. two-way interleave will allow no- wait-state operation at clock speeds greater than 100mhz without the need of secondary sram cache. the edram outperforms conventional sram cache plus dram memory systems by minimizing processor wait states for all possible bus events, not just cache hits. the combination of data and address latching, 2k of fast on-chip sram cache, and simplified on-chip cache control allows system level flexibility, performance, and overall memory cost reduction not available with any other high density memory component. architectural similarity with jedec drams allows a single memory controller design to support either slow jedec drams or high speed edrams. a system designed in this manner can provide a simple upgrade path to higher system performance. architecture the edram architecture has a simple integrated sram cache which allows it to operate much like a page mode or static column dram. the edrams sram cache is integrated into the dram array as tightly coupled row registers. memory reads always occur from the cache row register. when the internal comparator detects a page hit, only the sram is accessed and data is available in 12ns from column address. when a page read miss is detected, the new dram row is loaded into the cache and data is available at the output all within 30ns from row enable. subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. since reads occur from the sram cache, the dram precharge can occur simultaneously without degrading performance. the on-chip refresh counter with independent refresh bus allows the edram to be refreshed during cache reads. memory writes are internally posted in 12ns and directed to the dram array. during a write hit, the on-chip address comparator activates a parallel write path to the sram cache to maintain coherency. the edram delivers 12ns cycle page mode memory /cal a 0-10 w/r /f /re v v sense amps & column write select column decoder row add latch cc ss 2048 x 1 cache (row register) memory array (2048 x 2048) a 0-10 /g /s /we column add latch 11 bit comp last row read add latch i/o control and data latches refresh counter row decoder row add and refresh control a 0-9 d q functional diagram soj pin configuration tsop-ii pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v ss * v ss v ss q d nc nc nc /g v cc v cc v ss v ss /we /s /f nc w/r nc /cal a 10 nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc a 0 nc a 1 nc a 3 a 4 nc a 5 /re v cc v ss v ss a 6 a 7 a 8 nc a 2 nc a 9 v cc v cc* * reserved for future use 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 a 6 21 8 19 7 20 27 28 0 a 1 a 3 a 4 a 5 /re v cc v ss a 6 a 7 a 8 a 2 a 9 v cc v ss q /we /s /f w/r /cal /g v cc v ss a 10 d nc nc enhanced memory systems inc.
writes. memory writes do not affect the contents of the cache row register except during a cache hit. by integrating the sram cache as row registers in the dram array and keeping the on-chip control simple, the edram is able to provide superior performance over standard slow 4mb drams. by eliminating the need for srams and cache controllers, system cost, board space, and power can all be reduced. functional description t he edram is designed to provide optimum memory performance with high speed microprocessors. as a result, it is possible to perform simultaneous operations to the dram and sram cache sections of the edram. this feature allows the edram to hide precharge and refresh operation during sram cache reads and maximize sram cache hit rate by maintaining valid cache contents during write operations even if data is written to another memory page. these new functions, in conjunction with the faster basic dram and cache speeds of the edram, minimize processor wait states. edram basic operating modes the edram operating modes are specified in the table below . hit and miss t er minology in this datasheet, ?it?and ?iss?always refer to a hit or miss to the page of data contained in the sram cache row register . this is always equal to the contents of the last row that was read from (as modified by any write hit data). w riting to a new page does not cause the cache to be modified. dram read hit a dram read request is initiated by clocking /re with w/r low and /f & /cal high. the edram compares the new row address to the last row read address latch (lrr - an 11-bit latch loaded on each /re active read miss cycle). if the row address matches the lrr, the requested data is already in the sram cache and no dram memory reference is initiated. the data specified by the column address is available at the output pins at the greater of times t ac or t gqv . since no dram activity is initiated, /re can be brought high after time t re1 , and a shorter precharge time, t rp1 , is allowed. it is possible to access additional sram cache locations by providing new column addresses to the multiplex address inputs. new data is available at the output at time t ac after each column address change. during read cycles, it is possible to operate in either static column mode with /cal=high or page mode with /cal clocked to latch the column address. in page mode, data valid time is determined by either t ac or t cqv . dram read miss a dram read request is initiated by clocking /re with w/r low and /f & /cal high. the edram compares the new row address to the lrr address latch (an 11-bit latch loaded on each /re active read miss cycle). if the row address does not match the lrr, the requested data is not in sram cache and a new row must be fetched from the dram. the edram will load the new row data into the sram cache and update the lrr latch. the data at the specified column address is available at the output pins at the greater of times t rac , t ac , and t gqv . it is possible to bring /re high after time t re since the new row data is safely latched into sram cache. this allows the edram to precharge the dram array while data is accessed from sram cache. it is possible to access additional sram cache locations by providing new column addresses to the multiplex address inputs. new data is available at the output at time t ac after each column address change. during read cycles, it is possible to operate in either static column mode with /cal=high or page mode with /cal clocked to latch the column address. in page mode, data valid time is determined by either t ac or t cqv . dram w rite hit if a dram write request is initiated by clocking /re while w/r, /cal, /we, and /f are high, the edram will compare the new row address to the lrr address latch (an 11-bit address latch loaded on each /re active read miss cycle). if the row address matches, the edram will write data to both the dram array and selected sram cache simultaneously to maintain coherency . the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low . the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . with /g enabled and /we disabled, it is possible to perform cache read operations while the /re is activated in write hit mode. this allows read-modify-write, write-verify , or random read-write sequences within the page with 12ns cycle times (the first read cannot complete until after time t rac2 ). at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . it is possible to perform 1- 2 function /s unallowed mode h /re w/r /f a 0-10 comment l x h x unallowed mode (except -l option) standby current, internal refresh clock (-l option) low power self-refresh option h h h x internal refresh x x l x cache reads enabled read miss l l h row 1 lrr dram row to cache write hit l h h row = lrr write to dram and cache, reads enabled write miss l h h row 1 lrr write to dram, cache not updated, reads disabled read hit l l h /cal x l x h h h h /we x low power standby h h x x x 1ma standby current h h h x x h h x row = lrr no dram reference, data in cache h = high; l = low; x = don? care; = high-to-low transition; lrr = last row read edram basic operating modes
1-3 cache reads concurrently with precharge. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, the /cal input can be used as a byte write select in multi-chip systems. dram w rite miss if a dram write request is initiated by clocking /re while w/r, /cal, /we, and /f are high, the edram will compare the new row address to the lrr address latch (an 11-bit latch loaded on each /re active read miss cycle). if the row address does not match, the edram will write data to the dram array only and contents of the current cache are not modified. the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low . the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . during a write miss sequence, cache reads are inhibited and the output buffers are disabled (independently of /g) until time t wrr after /re goes high. at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . it is possible to perform cache reads concurrently with the precharge. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, /cal can be used as a byte write select in multi-chip systems. /re inactive operation it is possible to read data from the sram cache without clocking /re. this option is desirable when the external control logic is capable of fast hit/miss comparison. in this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles. this capability also allows the edram to perform cache read operations during precharge and refresh cycles to minimize wait states and reduce power . it is only necessary to select /s and /g and provide the appropriate column address to read data as shown in the table below . the row address of the sram cache accessed without clocking /re will be specified by the lrr address latch loaded during the last /re active read cycle. t o perform a cache read in static column mode, /cal is held high, and the cache contents at the specified column address will be valid at time t ac after address is stable. t o perform a cache read in page mode, /cal is clocked to latch the column address. the cache data is valid at time t ac after the column address is setup to /cal. on-chip sram interleave the dm2200 has an on-chip interleave of its sram cache which allows 8ns random accesses (t ac1 ) for up to three data words (burst reads) following an initial read access (hit or miss). the sram cache is integrated into the dram arrays in a 512 x 4 organization. it is converted into a 2k x 1 page organization by using an on-chip address multiplexer to select one of four bits to the output pin q (as shown below). the specific databit selected to the output is determined by column addresses a 9 and a 10 . system operation is consistent with the standard ?unctional description and timing diagrams shown in this specification. see the note in the read timing diagrams and ?witching characteristics?chart for the faster access and data hold times. inter nal refr esh if /f is active (low) on the assertion of /re, an internal refresh cycle is executed. this cycle refreshes the row address supplied by an internal refresh counter . this counter is incremented at the end of the cycle in preparation for the next /f refresh cycle. at least 1,024 /f cycles must be executed every 64ms. /f refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /f cycle. low power mode the edram enters its low power mode when /s is high. in this mode, the internal dram circuitry is powered down to reduce standby current to 1ma. low power , self-refr esh option when the low power , self-refresh option is specified when ordering the edram, the edram enters this mode when /re is clocked while /s, w/r, /f , and /we are high; and /cal is low . in this mode, the power is turned off to all i/o pins except /re to minimize chip power , and an on-board refresh clock is enabled to perform self-refresh cycles using the on-board refresh counter . the edram remains in this low power mode until /re is brought high again to terminate the mode. the edram /re input must remain high for t rp2 following exit from self-refresh mode to allow any on- going internal refresh to terminate prior to the next memory operation. +3.3 v olt power supply operation if the +3.3 volt power supply option is specified, the edram will operate from a +3.3 volt 0.3 volt power supply and all inputs and outputs will have l vttl/l vcmos compatible signal levels. the +3.3 volt edram will not accept input levels which exceed the power supply voltage. if mixed i/o levels are expected in your system, please specify the +5 volt version of the edram. /cal befor e /re refr esh (?cas befor e /ras? /cal before /re refresh, a special case of internal refresh, is discussed in the ?educed pin count operation?section below . function /s /g /cal a 0-8 cache read (static column) l h column address cache read (page mode) l column address h = high; l = low; x = don? care; = transitioning l l 2,048 bits 128 bits 1 bit q row address a 0-10 column address a 2-10 column address a 9, a 10 edram 4m dram array edram 2k sram cache 4 to 1 output selector dm2200 datapath ar chitectur e
/re only refr esh operation although /f refresh using the internal refresh counter is the recommended method of edram refresh, it is possible to perform an /re only refresh using an externally supplied row address. /re refresh is performed by executing a write cycle (w/r and /f are high) where /cal is not clocked. this is necessary so that the current cache contents and lrr are not modified by the refresh operation. all combinations of addresses a 0-9 must be sequenced e ver y 64ms refresh period. a 10 does not need to be cycled. read refresh cycles are not allowed because a dram refresh cycle does not occur when a read refresh address matches the lrr address latch. initialization cycles a minimum of 10 initialization (start-up) cycles are required before normal operation is guaranteed. at least eight /f refresh cycles and two read cycles to different row addresses are necessary to complete initialization. /re must be high for at least 300ns prior to initialization. unallowed mode read, write, or /re only refresh operations must not be performed to unselected memory banks by clocking /re when /s is high. reduced pin count operation although it is desirable to use all edram control pins to optimize system performance, it is possible to simplify the interface to the edram by either tying pins to ground or by tying one or more control inputs together . the /s input can be tied to ground if the low power standby modes are not required. the /cal and /f pins can be tied together if hidden refresh operation is not required. in this case, a cbr refresh (/cal before /re) can be performed by holding the combined input low prior to /re. a cbr refresh does not require that a row address be supplied when /re is asserted. the timing is identical to /f refresh cycle timing. the /we input can be tied to /cal if independent posting of column addresses and data are not required during write operations. in this case, both column address and write data will be latched by the combined input during writes. w/r and /g can be tied together if reads are not performed during write hit cycles. if these techniques are used, the edram will require only three control lines for operation (/re, /cas [combined /cal, /f , and /we], and w/r [combined w/r and /g]). the simplified control interface still allows the fast page read/write cycle times, fast random read/write times, and hidden precharge functions available with the edram. pin descriptions /re ?row enable this input is used to initiate dram read and write operations and latch a row address. it is not necessary to clock /re to read data from the edram sram row registers. on read operations, /re can be brought high as soon as data is loaded into cache to allow early precharge. /cal ?column addr ess latch this input is used to latch the column address and in combination with /we to trigger write operations. when /cal is high, the column address latch is transparent. when /cal is low , the column address latch is closed and the output of the latch contains the address present while /cal was high. w/r ?w rite/read this input along with /f specifies the type of dram operation initiated on the low going edge of /re. when /f is high, w/r specifies either a write (logic high) or read operation (logic low). /f ?refr esh this input will initiate a dram refresh operation using the internal refresh counter as an address source when it is low on the low going edge of /re. /we ?w rite enable this input controls the latching of write data on the input data pins. a write operation is initiated when both /cal and /we are low . /g ?output enable this input controls the gating of read data to the output data pins during read operations. /s ?chip select this input is used to power up the i/o and clock circuitry . when /s is high, the edram remains in its low power mode. /s must remain active throughout any read or write operation. with the exception of /f refresh cycles, /re should never be clocked when /s is inactive. d ?data input this input pin is used to write data to the edram. q ?data output this output pin is used to read data from the edram. a 0-10 ?multiplex addr ess these inputs are used to specify the row and column addresses of the edram data. the 11-bit row address is latched on the falling edge of /re. the11-bit column address can be specified at any other time to select read data from the sram cache or to specify the write column address during write cycles. v cc power supply these inputs are connected to the +5 or +3.3 volt power supply . v ss gr ound these inputs are connected to the power supply ground connection. 1- 4 pin names function a 0-10 address inputs row enable data in data out column address latch write/read control power (+5v or +3.3v) d q /cal w/r v cc /re pin names function /we /g /f /s chip select - active/standby control nc no connection write enable output enable refresh control ground v ss pin names
electrical characteristics t a = 0 to 70 c (commercial); -40 to 85 c (industrial) 1- 5 symbol parameters min max test conditions v cc supply voltage 4.75v all voltages referenced to v ss v ih v il i i(l) i o(l) v oh v ol ov v in vcc + 0.5 volts o v i/o vcc i out = - 5ma (-2ma for 3.3 volt option) i out = 4.2ma (2ma for 3.3 volt option) 0.8v 10? 0.4v 10? 2.4v vss-0.5v -10? -10? 2.4v input high voltage input low voltage input leakage current output leakage current output high level output low level 5.25v min max 3.3v option 3.0v v cc +0.3v 0.8v 5? 0.4v 5? 2.0v vss-0 .3v -5? -5? 2.4v 3.6v vcc+0.5v symbol operating current -15 max test condition i cc1 random read /re, /cal, and addresses cycling: t c = t c minimum all control inputs stable 3 v cc - 0.2v, output driven /re, /cal, /we, and addresses cycling: t c = t c minimum /cal, /we, and addresses cycling: t pc = t pc minimum 115ma 90ma 105ma fast page mode read static column read standby random write fast page mode write 180ma i cc2 i cc3 i cc4 i cc5 i cc6 150ma 33mhz typ (1) 65ma 55ma 1ma 200 ? 1ma 1ma 50ma 110ma 135ma notes 2, 3, 5 2, 4, 5 2, 4, 5 2, 3 2, 4 /cal and addresses cycling: t pc = t pc minimum addresses cycling: t sc = t sc minimum (1) ?3mhz typ?refers to worst case i cc expected in a system operating with a 33mhz memory bus. see power applications note for further details. this parameter is not 100% tested or guaranteed. (2) i cc is dependent on cycle rates and is measured with cmos levels and the outputs op en. (3) i cc is measured with a maximum of one address change while /re = v il . (4) i cc is measured with a maximum of one address change while /cal = v ih . (5) /g is high. -12 max 225ma 145ma 110ma /s, /f, w/r, /we, and a 0-10 at 3 v cc - 0.2v /re and /cal at v ss + 0.2v, i/o open self-refresh option (-l) i cc7 190ma 135ma see ?stimating edram operating power?application note average typical operating current i cct 30ma 1 200 ? 200 ? r 1 = 828 w 5ns 5ns v il v il gnd + 5.0 (+3.3 volt option) output c l = 50pf r 2 = 295 w load circuit input waveforms v ih v ih (5.0 volt) r 1 = 1178 w (3.3 volt option) r 2 = 868 w (5.0 volt) (3.3 volt option) ac t est load and w avefor ms v in t iming reference point at v il and v ih ambient operating temperature (t a ) description ratings output voltage (v out ) power supply voltage (v cc ) storage temperature (t s ) static discharge voltage (per mil-std-883 method 3015) short circuit o/p current (i out ) - 1 ~ 7v - 1 ~ 7v input voltage (v in ) - 1 ~ 7v -40 ~ 85? -55 ~ 150? class 1 50ma 3.3v option rating - .5 ~ 4.6v - .5 ~ 4.6v - .5 ~ 4.6v -40 ~ 85? -55 ~ 150? class 1 20ma absolute maximum ratings (beyond which permanent damage could result) description max pins input capacitance input capacitance input capacitance 2pf a 0-9 /g input capacitance 7pf, 10pf (1) 6pf, 7pf (1) a 10 , /cal, /re, w/r, /we, /f, /s 6pf d output capacitance 6pf q capacitance (1) +5 v , dm2200-15 only .
symbol description t ac (1) t asc t asr t c t c1 t cae t cah t ch t cqv t crp t cwl t dh t ds t gqv (1) t gqx (2,3) column address access time for addresses a 0-8 column address setup time row enable cycle time row enable cycle time, cache hit (row=lrr), read cycle only row address setup time column address latch active time column address hold time column address latch high time (latch transparent) column address latch high to data valid column address latch inactive to data invalid for addresses a 0-8 column address latch setup time to row enable /we low to /cal inactive data input hold time data input setup time output enable access time output enable to output drive time 5 5 55 20 5 5 5 5 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min max units 12 5 0 15 0 5 t aqx1 column address change to output data invalid for addresses a 9 and a 10 ns 1 t ach column address valid to /cal inactive (write cycle) ns 12 8 5 5 5 65 25 5 5 5 5 0 5 min max 15 6 0 17 0 5 1 t aqx column address change to output data invalid for addresses a 0-8 ns 5 5 15 8 t ac1 (1) column address access time for addresses a 9 and a 10 ns 5 -12 -15 t cqx column address latch inactive to data invalid for addresses a 9 and a 10 1 ns 1 t cqx1 t nrs t pc t rac (1) t rac1 (1) t rah output turn-off delay from output disabled (/g - ) /cal, /g, /we, and w/r setup time for /re-only refresh, column address latch cycle time row address hold time row enable access time, on a cache miss t nrh /cal, /g, /we, and w/r hold time for /re-only refresh t msu /f and w/r mode select setup time t mh /f and w/r mode select hold time ns 0 5 0 5 ns 0 0 ns 5 5 ns 0 0 ns 5 5 ns 12 15 ns 30 35 ns 1.5 t gqz (4,5) t rac2 (1,6) row enable access time for a cache write hit ns 30 35 1 t chr /cal inactive lead time to /re inactive (write cycles only) -2 ns -2 t chw column address latch high to write enable low (multiple writes) 0 ns 0 row enable access time, on a cache hit (limit becomes t ac ) 15 17 ns t re row enable active time ns 30 35 100000 100000 switching characteristics v cc = 5v 5% (+5 v olt option), v cc = 3.3v 0.3v (+3.3 v olt option), c l = 50pf, t a = 0 to 70 c (commercial) ,t a = -40 to 85 c (industrial) 1- 6
1- 7 switching characteristics (continued) v cc = 5v 5% (+5 v olt option), v cc = 3.3v 0.3v% (+3.3 v olt option), c l = 50pf, t a = 0 to 70 c (commercial) ,t a = -40 to 85 c (industrial) symbol description t rgx t rp t rp1 t rrh t rsh t output enable don't care from row enable (write, cache miss), o/p hi z row precharge time row precharge time, cache hit (row=lrr) read cycle read hold time from row enable (write only) last write address latch to end of write row enable to column address latch low for second write 9 20 8 0 ns ns ns ns ns ns min max units 35 25 10 t rp2 row precharge time, self-refresh mode 100 ns 100 0 min max 10 t rqx1 (2,6) row enable high to output turn-on after write miss 0 ns 40 -12 -15 12 15 rsw ns t rwl last write enable to end of write ns 12 15 t sc column address cycle time ns 12 15 t shr select hold from row enable ns 0 0 t sqv (1) chip select access time ns 12 15 t sqx (2,3) output turn-on from select low ns 12 15 0 0 output turn-off from chip select ns 8 10 0 0 t ssr select setup time to row enable ns 5 5 t t transition time (rise and fall) ns 10 10 1 1 t wc write enable cycle time ns 12 15 t wch column address latch low to write enable inactive time ns 5 5 t wi write enable inactive time ns 5 5 (1) v out timing reference point at 1.5v (2) parameter defines time when output is enabled (sourcing or sinking current) and is not referenced to v oh or v ol (3) minimum specification is referenced from v ih and maximum specification is referenced from v il on input control signal (4) parameter defines time when output achieves open-circuit condition and is no t referenced to v oh or v ol (5) minimum specification is referenced from v il and maximum specification is referenced from v ih on input control signal (6) access parameter applies when /cal has not been asserted prior to t rac2 t wp t wrp t wrr write enable active time write enable setup time to row enable write to read recovery (following write miss) 16 ns ns ns 5 data turn-off from write enable low ns t wqx (2,5) data output turn-on from write enable high ns 0 t wqv (1) data valid from write enable high ns 18 5 0 12 5 5 15 12 15 0 0 12 15 t re1 t ref row enable active time, cache hit (row=lrr) read cycle refresh period ms 64 64 8 10 ns t whr write enable hold after /re ns 0 0 t sqz (4,5) t wqz (3,4) 12 0 15
1- 8 /re /f w/r a 0-10 /cal /g /s column 1 t sc t sc data 1 open t gqz t gqx t gqv t sqv t sqx t sqz q don? care or indeterminate /we column 2 column 3 column 4 data 2 data 3 data 4 ac t t aqx t aqx ac t t aqx ac t ac t t sc notes: 1. 2. data accessed during /re inactive read is from the row address specified during the last /re active read cycle. if column address 2, 3, or 4 modifies only address pin a 9 or a 10 , then t ac becomes t ac1 for data 2, 3, and 4, and t aqx becomes t aqx1 for data 1, 2, and 3. /re inactive cache read hit (static column mode)
1- 9 /re /f w/r a 0-10 /cal /g /s t cah column 1 column 2 t asc t cah t ch t cae t pc t cqv t ac t cqx data 1 open data 2 t gqz t gqx t gqv t ac t sqz t sqv t sqx row t asc q /we don? care or indeterminate notes: 1. 2. data accessed during /re inactive read is from the row address specified during the last /re active read cycle. if column address 2 modifies only address pin a 9 or a 10 , then t ac becomes t ac1 for data 2 and t cqx becomes t cqx1 for data 1. /re inactive cache read hit (page mode)
1- 10 /re t c1 row /f w/r a 0-10 /cal /g /s t re1 t msu t mh t rp1 t asr t rah column 1 t crp t sc t sc t rac1 data 1 open t gqz t gqx t gqv t ssr t sqz t shr t mh t msu q don? care or indeterminate /we column 2 column 3 column 4 data 2 data 3 data 4 ac t t aqx t aqx ac t t aqx ac t ac t t sc if column address 2, 3, or 4 modifies only address pin a 9 or a 10 , then t ac becomes t ac1 for data 2, 3, and 4, and t aqx becomes t aqx for data 1, 2, and 3. 1. notes: /re active cache read hit (static column mode)
1- 11 /re t c1 row /f w/r a 0-10 /cal /g /s t re1 t msu t mh t rp1 t asr t rah t cah column 1 column 2 t crp t asc t cah t ch t cae t pc t cqv t ac t rac1 t cqx data 1 open data 2 t gqz t gqx t gqv t ac t ssr t sqz t shr t mh t msu row t asc q /we don? care or indeterminate if column address 2 modifies only address pin a 9 or a 10 , then t ac becomes t ac1 for data 2 and t cqx becomes t cqx1 for data 1. notes: 1. /re active cache read hit (page mode)
1- 12 /re /f w/r a 0-10 /cal /g t c column 1 /s t re t rp t msu t msu t asr t mh t mh t rah t sc t crp t aqx t ac t ac t rac t aqx row column 2 row open data 1 data 2 t gqx t gqv t gqz t ssr t sqz t shr q /we don? care or indeterminate if column address 2 modifies only address pin a 9 or a 10 , then t ac becomes t ac1 for data 2, and t aqx becomes t aqx1 for data 1. notes: 1. /re active cache read miss (static column mode)
1-13 /re /f w/r a 0-10 /cal /g /s t msu t c t re t rp t mh t mh t rah t msu t asr t crp t cah t asc t asc t cah t ch t cae t pc t cqv t rac t cqx t ac open t ac t gqz t ssr t gqx t gqv t shr t sqz row column 1 column 2 row data 1 data 2 q /we don? care or indeterminate if column address 2 modifies only address pin a 9 or a 10 , then t ac becomes t ac1 for data 2, and t cqx becomes t cqx1 for data 1. notes: 1. /re active cache read miss (page mode)
1- 14 w/r t re column 1 t msu t msu t asr t mh t rah t rsw column 2 row column n t crp t cah t asc t cwl t cae t cwl t rsh t cae t wrp t wp t rrh t wch t wch t pc t wp t rwl t dh t dh t ds t ds t ac t wrr t gqx t rqx1 t gqv t ssr data 1 data 2 t ach t ach t chr t ch t whr t wi t wc cache (column n) open q d /re /f /cal /g /s /we t chw t rp t chr a 0-10 t cah don? care or indeterminate notes: 1. /g becomes a don? care after t rgx during a write miss. t mh burst w rite (hit or miss) followed by /re inactive cache reads
1- 15 /re /f w/r a 0-10 /cal /we /g t re /s column 1 t msu t msu t asr t mh t rah column 2 row column 3 t wrp t cqx t gqx t ssr d read data t whr t c t rp t crp t cae t ach t asc t rsh t wch t rrh t cqv t wp t cwl read data t rac2 t ac t aqx t ds t rwl t wqv t gqv t gqz t dh t gqz t gqv t wqx write data q t chr don? care or indeterminate t cah t ac t mh t chr notes: 1. if column address 2 modifies only address pin a 9 or a 10 , then t aqx becomes t aqx1 . read/w rite during w rite hit cycle (can include read-modify-w rite)
1- 16 /re /f t re t msu t mh don? care or indeterminate notes: 1. 2. during /f refresh cycles, the status of w/r, /we, a 0-10 , /cal, /s, and /g is a don? care. /re inactive cache reads may be performed in parallel with /f refresh cycles. t rp /f refr esh cycle t c /f t re t rp t asr t rah row t nrs t nrh t ssr t shr t msu t mh /re a 0-10 /cal, /we, /g, w/r /s don? care or indeterminate notes: 1. all binary combinations of a 0-9 must be refreshed every 64ms interval. a 10 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /re refresh is write cycle with no /cal active cycle. /re-only refr esh
1- 17 /f, w/r, /we, /s t rp2 t msu t mh t msu t mh /re don? care or indeterminate notes: 1. edram self refreshes as long as /re remains low. (low power self-refresh parts only). 2. when using the low power self refresh mode the following operations must be perf ormed: if row addresses are being refreshed in an evenly distributed manner over the refresh interval using /f refresh cycles, then at least one /f refresh cycle must be performed immediately after exit from the low power self refresh mode. if row addresses are being refreshed in any other manner (/f burst or /re distributed or burst), then all rows must be refresh immediately before entry to and immediately after exit from the low power self refresh. a 0-10 /cal low power self-refr esh mode option dm2200j 1 - 12i dynamic memory capacity in bits i/o width packaging system access time from cache in nanoseconds 12ns 15ns temperature range i = -40 to 85 o c (industrial) l = 0 to 70 o c, low power self-refresh power supply voltage no designator = +5 volts 1 = +3.3 volts j = 300 mil, plastic soj t = 300 mil, plastic tsop-ii i.e., power to which 2 is raised for i/o width (x1) no designator = 0 to 70 o c (commercial) i.e., power to which 2 is raised for total capacity (4mbit) par t numbering system
1- 18 optional pin 1 indicator inches (mm) 1 2 3 0.050 (1.27) seating plane 0.295 (7.493) 0.305 (7.747) 0.330 (8.382) 0.340 (8.636) 0.0091 (.23) 0.0125 (.32) 0.094 (2.39) 0.102 (2.59) 0.260 (6.604) 0.275 (6.985) 0.014 (.36) 0.019 (.48) 0.128 (3.251) 0.148 (3.759) 0.035 (0.89) 0.045 (1.14) 0.720 (18.288) 0.730 (18.542) 0.088 (2.24) 0.098 (2.48) mechanical data 28 pin 300 mil plastic soj package 0.040 (1.02) typ. inches (mm) 0.741 (18.81) max. 0.0315 (0.80) typ. 0.040 (1.02) typ. 0.016 (0.40) 0.008 (0.20) 0.040 (1.02) typ. 0.039 (1.00) typ. 0.004 (0.10) 0.000 (0.00) 0.044 (1.13) max. 0.010 (0.24) 0.004 (0.09) 0.308 (7.82) 0.292 (7.42) 0.371 (9.42) 0.355 (9.02) 0.024 (0.60) 0.016 (0.40) 0.039 (1.00) 0.023 (0.60) 7?typ. mechanical data 44 pin 300 mil plastic tsop-ii package the information contained herein is subject to change without notice. enhanced memory systems inc. assumes no responsibility fo r the use of any circuitry other than circuitry embodied in an enhanced product, nor does it convey or imply any license under patent or other rights.

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