preliminary information m2004-x2 datasheet rev 1.3 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m2004-x2 f requency t ranslation pll f amily integrated circuit systems, inc. g eneral d escription the m2004 variants -22, -32, -42, and -52 are vcso (voltage controlled saw oscillator) based clock generator plls designed for clock frequency translation and jitter attenuation in a high-speed data communications system. the clock multiplication ratio and output divider ratio are pin selectable. external loop components allow the tailoring of pll loop response. based on the m2004-02, these device variants add the hitless switching with phase build-out (hs/pbo) fe ature. hs/pbo ensures that reference clock reselection does not disrupt the output clock. in addition, a fixed narrow loop bandwidth feature (fixed nbw) is included in the some of the device variants. f eatures pin-compatible with m2004-02/-12, these new product variants offer new functions hitless switching with phase build-out to ensure sonet/sdh mtie and td ev compliance during reference clock reselection fixed narrow loop bandwidth feature available ideal for oc-48/192 data clock integrated saw (surface acoustic wave) delay line vcso frequency from 300 to 700mhz ** low phase jitter of < 0.5ps rms, typical (12khz to 20mhz or 50khz to 80mhz) pin-selectable configuration reference clock inputs support differential lvds, lvpecl, as well as single -ended lvcmos, lvttl industrial temperature available single 3.3v power supply small 9 x 9 mm smt (surface mount) package p in a ssignment (9 x 9 mm smt) figure 1: pin assignment * this sheet covers only parts numbered m2004-22, -32, -42, -52. see m2004-02/-12 product data sheet for m2004-02 & m2004-12. ** specify vcso center fr equency at time of order. s implified b lock d iagram figure 2: simplified block diagram example input / output frequency combinations input (mhz) vcso ** (mhz) output (mhz) application 19.44 622.08 77.76 oc-12 / 48 /192 77.76 311.04 155.52 622.08 table 1: example input / output frequency combinations device variants and corresponding functions variant hitless switching / phase build-out triggered by fixed nbw phase transient mux reselection m2004-02 no no no m2004-12 ? yes ? yes no m2004-22 no no ? yes m2004-32 ? yes ? yes ? yes m2004-42 no ? yes no m2004-52 no ? yes ? yes table 2: device variants and corresponding functions m2004-x2 (top view) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 m0 gnd ref_clk dif_ref ndif_ref ref_sel nc nc vcc nc mr nfout fout gnd n1 n0 vcc gnd m1 m2 m3 m4 m5 vcc dnc dnc dnc nop_in op_out vc nvc nop_out op_in gnd gnd gnd 19 20 21 22 23 24 25 26 27 ref_sel dif_ref ref_clk 0 m2004-x2 fout nfout m divider n divider vcso 1 6 m5:0 n1:0 2 mr ndif_ref loop filter m2004-x2 frequency translation pll family *
m2004-x2 datasheet rev 1.3 2 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2004- x 2 f requency t ranslation pll f amily preliminary information p in d escriptions number name i/o configuration description 1, 2, 3, 10, 14, 26 gnd ground power supply ground connections. 4 9 op_in nop_in input external loop filter c onnections. see figure 4, external loop filter, on pg. 5. 5 8 nop_out op_out output 6 7 nvc vc input 11, 19, 33 vcc power power supply connection, connect to + 3.3 v. 12 13 n0 n1 input internal pull-down resistor 1 note 1: for typical values of internal pull-down and pull-up resistors, see dc characteristics on pg. 7. n divider (output divider) inputs n1 : n0 . lvcmos/lvttl. see table 6, n divider pin selection , on pg. 3. 15 16 fout nfout output no internal terminator clock output pair. differential lvpecl. 17 mr input internal pull-down resistor 1 reset: logic 1 resets m and n dividers and forces fout to low and nfout to high. logic 0 enables the outputs. lvcmos/lvttl. 18 20 21 nc nc nc no connection. 22 ref_sel input internal pull-down resistor 1 referenc e clock input selection. lvcmos/lvttl. see table 4, reference clock input selection, on pg. 3. ref_sel triggers hitless switching (hs/pbo) when toggled. 23 24 ndif_ref input internal pull-up resistor 1 reference clock input pair. differential lvpecl or lvds. dif_ref internal pull-down resistor 1 25 ref_clk input internal pull-down resistor 1 reference clock input. lvcmos/lvttl. 27 28 29 30 31 m0 m1 m2 m3 m4 input internal pull-down resistor 1 m divider (feedback divider) inputs m5 : m0 . see table 5, m divider pin selection, on pg. 3. 32 m5 internal pull-up resistor 1 34, 35, 36 dnc do not connect. table 3: pin descriptions
m2004-x2 datasheet rev 1.3 3 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m2004- x 2 f requency t ranslation pll f amily preliminary information integrated circuit systems, inc. d etailed b lock d iagram figure 3: detailed block diagram pll d ivider s election t ables reference clock input selection m divider pin selection n divider pin selection m2004-x2 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop r in r in op_in nop_in m divider m = 3-63 mux 1 0 n divider n = 1,2,4,8 pin configuration register 6 m5:0 n1:0 phase detector loop filter amplifier external loop filter components ref_sel ref_clk fout nfout mr 2 dif_ref ndif_ref ref_sel pin setting (pin 22) reference input selection 0 dif_ref, ndif_ref 1 ref_clk table 4: reference clock input selection m5:0 pin settings (pins 32 - 27) m5 - m0 definition sample input clock freq (mhz) f vcso = f vcso = 622.08 1 , 625.00 2 note 1: f vcso = 622.08 mhz (e.g., m2004-22-622.0800) note 2: f vcso = 625.00 mhz (e.g., m2004-22-625.0000) 5 3 4 3 2 1 0 note 3: m5 pin has a pull-up resister; m4-m0, pull-down. feedback divider value ?m? 0 0 0 0 1 1 m = 3 minimum 0 0 0 1 0 0 m = 4 155.52 156.25 0 0 1 0 0 0 m = 8 77.76 0 1 0 0 0 0 m = 16 38.80 0 1 1 0 0 1 m = 25 25.00 1 0 0 0 0 0 m = 32 19.44 1 1 1 1 1 1 m = 63 table 5: m divider pin selection n1:0 settings (pin 13 and 12) n1 n0 n divider value sample output frequency (mhz) 1 (fout, nfout) note 1: f vcso = 622.08mhz (e.g., m2004-22-622.0800) 0 0 1 622.08 0 1 2 311.04 1 0 4 155.52 1 1 8 77.76 table 6: n divider pin selection . . . . . . . . . . . . . . .
m2004-x2 datasheet rev 1.3 4 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2004- x 2 f requency t ranslation pll f amily preliminary information f unctional d escription the m2004-x2 is a pll (phase locked loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. an internal high ?q? saw delay line provides a low jitter clock signal. the device can be pin-configured for feedback divider and output divider values. output is lvpecl compatible. external loop f ilter component values set the pll bandwidth to optimize jitter attenuation characteristics. the m2004-x2 is ideal for clock jitter attenuation and frequency translation in 2.5 or 10 gb optical network line card applications. added features and device variants hitless switching with phase build-out (hs/pbo) provides sonet/sdh mtie and tdev compliance during a reference clock reselection when using the internal mux (and also when using an external mux, in two device variants). a fixed narrow loop bandwidth feature (fixed nbw) is included in some of the device variants. all of the variants of the device are defined as follows: ? the m2004-02 is the base variant (it omits both hs/pbo and fixed nbw). ? the m2004-12 includes hs/pbo triggered by either a phase transient or internal mux reselection. ? the m2004-22 includes hs/pbo ? triggered by internal mux reselection only ? and fixed nbw. ? the m2004-32 includes hs/pbo ? triggered by either a phase transient or internal mux reselection ? and fixed nbw. ? the m2004-42 includes hs/pbo triggered by internal mux reselection only. ? the m2004-52 includes hs/pbo ? triggered by internal mux reselection only ? and fixed nbw. input reference clocks an internal input mux is provided for input reference clock selection. one input reference clock is selected from between a single-ended lvcmos / lvttl clock input or a differential lvpecl or lvds clock input pair. the maximum input frequency is 175mhz. pll operation the m2004-x2 is a complete clock pll. it uses a phase detector and configurable dividers to synchronize the output of the vcso with the selected reference clock. the ?m divider? divides the vcso output frequency, feeding the result into the phase detector. the selected input reference clock is fed into the other input of the phase detector. the phase detector compares its two inputs. it then causes the vcso to increase or decrease in speed as needed to phase- and frequency- lock the vcso to the reference input. the value of m directly affects closed loop bandwidth. the m divider the relationship between the vcso center frequency (fvcso), the m divider, and the input reference frequency (fref_clk) is: the product of m and the input frequency must be such that it falls within the ?lock? range of the vcso. see apr in ac characteristics on pg. 8. n divider and outputs the m2004-x2 provides one differential lvpecl output pair: fout, nfout. by using the n divider, the output frequency can be the vcso center frequency (fvcso) or 1/2, 1/4, or 1/8 fvcso. the n1 and n0 pins select the value for the n divider. see table 6 , m divider pin selection , on pg. 3. when the n divider is included, the complete relation- ship for the output frequency (fout) is defined as: configuration of m and n dividers the m and n dividers can be set by pin configuration using the input pins m0 - m5 , n0 , and n1 . the data on pins m5:0 and pins n1:0 is passed directly to the m and n dividers. the divider configuration of the m2004-x2 is reset when the input pin mr is set high. mr is set low for divider configuration to be operational. device variants and corresponding functions variant hitless switching / phase build-out triggered by fixed nbw phase transient mux reselection m2004-02 no no no m2004-12 ? yes ? yes no m2004-22 no no ? yes m2004-32 ? yes ? yes ? yes m2004-42 no ? yes no m2004-52 no ? yes ? yes table 7: device varian ts and corresponding functions fvcso fref_clk m = fout fvcso n ------------------- = fref_clk m n -------- =
m2004-x2 datasheet rev 1.3 5 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m2004- x 2 f requency t ranslation pll f amily preliminary information integrated circuit systems, inc. hitless switching and phase build-out a proprietary automatic hitless switching (hs) function is included in the m2004-22, m2004-32, m2004-42, and m2004-52. the hs function provides sonet/sdh mtie and tdev compliance during a reference clock reselection when using the internal mux. two variants are additionally triggered by reference clock reselection when using an external mux (through detection of the resulting phase transient). * a phase build-out (pbo) function is also incorporated to absorb most of the phase change in the reference clock input. the combined hs/pbo function is armed after the device locks to the input clock reference. once armed, hs/pbo is triggered according to device variant as follows: ? in the m2004-22, m2004-42 and m2004-52, hs/pbo is only triggered by changing ref_sel to switch the input reference clock. ? in the m2004-32, hs/pbo is triggered by either reselection of the input mux or by detection at the phase detector of an input phase transient beyond 4ns. once triggered, the hs function narrows loop band- width to control mtie durin g locking to the new input phase. ** with proper configuration of the external loop filter, the output clocks will comply with mtie and tdev specifications for gr-253 (sonet) and itu g.813 (sdh) during input reference clock changes. the phase build-out (pbo) function enables the pll to absorb most of the phase change of the input clock. the pbo function selects a new vcso clock edge for the phase detector feedback clock, selecting the edge closest in phase to the new input clock phase. this reduces re-lock time, the generation of wander, and extra output clock cycles. when the pll locks to within 2 ns of the input clock phase, the pll returns to normal loop bandwidth and the hs/pbo function is re-armed. external loop filter to provide stable pll operation, and thereby a low jitter output clock, the m2004-x2 requires the use of an external loop filter components. these are connected to the provided filter pins (see figure 4). due to the differential signal path design, the implementation consists of two identical complementary rc filters as shown in figure 4, below. figure 4: external loop filter pll bandwidth is affected by the ?m? value as well as the vcso frequency. see table 8, external loop filter component values for m2004-42, on pg. 6. in addition, loop bandwidth is affected by the fixed narrow loop bandwidth (fixed nbw) feature. see table 8, external loop filter component values for m2004-42, on pg. 6. fixed narrow loop bandwidth (fixed nbw) *** a fixed narrow loop bandwidth feature (fixed nbw) is included in the m2004-22, m2004-32, and m2004-52. these device variants have a narrower loop bandwidth than the other variants. the internal resistor rin is 2016 m ? , increased from 16 k ? . this lowers the loop bandwidth by a factor of 125 (2 / 0.016) and lowers the damping factor by a factor of 11.18 (the square root of 125), using the same loop components. pll simulator tool available a free pc software utility is available on the ics website (www.icst.com). the m2000 timing modules pll simulator is a downloadable application that simulates pll jitter and wander transfer characteristics. this enables the user to set appropriate external loop component values in a given application. * transient-triggered hs/pbo is not suitable for use with an unstable reference clock that would induce phase jitter beyond 2 ns at the phase detector (e.g., stratum dpll clock sources and unstable recovered network clocks intended for loop timing configuration). therefore, all of the hs/pbo devices offer the internal mux-triggered hs/pbo capability. ** in the m2004-32 and m2004-52, the fixed nbw function permanently enables narrow bandwidth, therefore pbo is the only actively-triggered function. *** the m2004-02, m2004-12, and m2004-42 do not include fixed nbw. c post c post v c nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in 6 7 5 49 8
m2004-x2 datasheet rev 1.3 6 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2004- x 2 f requency t ranslation pll f amily preliminary information external loop filter component values for m2004-42 1 vcso parameters: k vco = 800khz/v, r in = 16k ? , vcso bandwidth = 700khz. see ac characteristics on pg. 8 for pll loop constants. device configuration example external loop filter co mponent values nominal performance using these values f ref (mhz) f vcso (mhz) m divider value r loop c loop r post c post pll loop bandwidth damping factor passband peaking (db) 19.44 622.08 32 13 k ? 0.47 f 33 k ? 220 pf 3.8k hz 5.6 0.06 19.44 622.08 32 39 k ? 0.022 f 20 k ? 220 pf 12.7k hz 7.7 0.03 19.44 622.08 32 2.2k ? 10.0 f 22 k ? 3300 pf 710 hz 4.4 0.10 155.52 622.08 4 3.9 k ? 0.47 f 39 k ? 100 pf 11.0k hz 4.7 0.09 155.52 622.08 4 750 ? 10.0 f 7.5 k ? 1000 pf 1.6k hz 4.2 0.10 table 8: external loop filter component values for m2004-42 note 1: k vco , vcso bandwidth, m divider value, and external loop filter component values determine loop bandwidth, damping factor, and passband peaking. for pll simulator software, go to www.icst.com. external loop filter component values for m2004-22, m2004-32, and m2004-52 1 vcso parameters: k vco = 800khz/v, r in = 2016k ? , vcso bandwidth = 700khz. see ac characteristics on pg. 8 for pll loop constants. device configuration example external loop filter co mponent values nominal performance using these values f ref (mhz) f vcso (mhz) m divider value r loop c loop r post c post pll loop bandwidth damping factor passband peaking (db) 19.44 622.08 32 120 k ? 0.47 f 50 k ? 1000 pf 265 hz 4.6 0.09 19.44 622.08 32 660 k ? 0.022 f 50 k ? 1000 pf 1.83k hz 5.5 0.07 19.44 622.08 32 22k ? 10.0 f 50 k ? 5000 pf 47 hz 3.9 0.12 155.52 622.08 4 50 k ? 0.47 f 33 k ? 500 pf 866 hz 5.4 0.07 155.52 622.08 4 27 k ? 2.0 f 50 k ? 500 pf 500 hz 6.0 0.05 77.76 622.08 8 50 ? 1.0 f 33 k ? 500 pf 414 hz 5.6 0.06 table 9: external loop filter component values for m2004-22, m2004-32, and m2004-52 note 1: k vco , vcso bandwidth, m divider value, and external loop filter component values determine loop bandwidth, damping factor, and passband peaking. for pll simulator software, go to www.icst.com.
m2004-x2 datasheet rev 1.3 7 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m2004- x 2 f requency t ranslation pll f amily preliminary information integrated circuit systems, inc. e lectrical s pecifications a bsolute m aximum r atings 1 symbol parameter rating unit v i inputs - 0.5 to v cc + 0.5 v v o outputs - 0.5 to v cc + 0.5 v v cc power supply voltage 4.6 v t s storage temperature - 45 to + 100 o c table 10: absolute maximum ratings note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress sp ecifications only. functional operati on of product at these conditions or any conditions beyond those listed in recommended conditions of operation, dc characteristics, or ac characteristics is not implied. exposure to absolute maximum rating condi tions for extended periods may affect product reliability . r ecommended c onditions of o peration symbol parameter min typ max unit v cc positive supply voltage 3.135 3.3 3.465 v t a ambient operating temperature commercial 0 + 70 o c industrial -40 + 85 o c table 11: recommended conditions of operation dc characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), f vcso = f out = 622-675 mhz, outputs terminated with 50 ? to v cc - 2v t a = -40 o c to + 85 o c (industrial) symbol parameter min typ max unit conditions power supply v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 162 ma differential input: lvds / lvpecl v p - p peak to peak input voltage 1 note 1: single-ended measurement. see figure 6, differential input level on pg. 9. dif_ref, ndif_ref 0.15 v v cmr common mode input 1 0.5 v cc - 0 .85 v lvcmos / lvttl input v ih input high voltage ref_clk, ref_sel, mr, n0:n1, m0:m5 2 v cc + 0.3 v v il input low voltage - 0.3 1.3 v inputs with pull-down i ih input high current dif_ref, ref_clk, ref_sel, mr, n0:n1, m0:m4 150 a v cc = v in = 3.456v i il input low current - 5 a r pulldown internal pull-down resistor 51 k ? inputs with pull-up i ih input high current ndif_ref, m5 5 a v cc = 3.456v v in = 0 v i il input low current -1 50 a r pullup internal pull-up resistor 51 k ? all inputs c in input capacitance all inputs 4 pf differential outputs v oh output high voltage fout, nfout v cc - 1.4 v cc - 1.0 v v ol output low voltage v cc - 2.0 v cc - 1.7 v v p - p peak to peak output voltage 2 note 2: single-ended measurement. see figure 5, input and output rise and fall time on pg. 9. 0.4 0.85 v table 12: dc characteristics
m2004-x2 datasheet rev 1.3 8 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2004- x 2 f requency t ranslation pll f amily preliminary information e lectrical s pecifications ( continued ) ac characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), f vcso = f out = 622-675 mhz, outputs terminated with 50 ? to v cc - 2v t a = -40 o c to + 85 o c (industrial) symbol parameter min typ max unit conditions f in input frequency dif_ref, ndif_ref, ref_clk 1 175 mhz f out output frequency fout, nfout 38 700 mhz apr vcso pull-range commercial 120 200 ppm industrial 50 150 ppm pll loop constants 1 note 1: parameters needed for pll simulator software; see tables 8 and 9, external loop filter component values, on pg. 6. k vco vco gain 800 khz/v r in internal loop resistor m2004-42 16 k ? m2004-22, m2004-32, m2004-52 2016 k ? bw vcso vcso bandwidth 700 khz phase noise and jitter n single side band phase noise @ 622.08 mhz 1 khz offset - 72 dbc/hz 10 khz offset - 94 dbc/hz 100 khz offset - 123 dbc/hz j(t) jitter (rms) 12 khz to 20 mhz 0.5 ps 50 khz to 80 mhz 0.5 ps odc output duty cycle 2 note 2: see parameter measurement information on pg. 9. n = 2, 4, or 8 45 50 55 % n = 1 40 50 60 % t r output rise time 2 for fout, nfout f out =155.52mhz n = 4 (n1:0 = 10) 350 450 550 ps 20 % to 80 % f out =311.04mhz n = 2 (n1:0 = 01) 325 425 500 ps f out =622.08mhz n = 1 (n1:0 = 00) 200 275 350 ps t f output fall time 2 for fout, nfout f out =155.52mhz n = 4 (n1:0 = 10) 350 450 550 ps 20 % to 80 % f out =311.04mhz n = 2 (n1:0 = 01) 325 425 500 ps f out =622.08mhz n = 1 (n1:0 = 00) 200 275 350 ps t lock pll lock time 100 ms mtie mean time interval error 3 m2004-22, m2004-32, m2004-42, m2004-52 note 3: requires proper loop filter settings. consult factory. compliant with gr-253-core table 13: ac characteristics
m2004-x2 datasheet rev 1.3 9 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m2004- x 2 f requency t ranslation pll f amily preliminary information integrated circuit systems, inc. p arameter m easurement i nformation input and output rise and fall time figure 5: input and output rise and fall time differential input level figure 6: differential input level output duty cycle figure 7: output duty cycle d evice p ackage - 9 x 9mm c eramic l eadless c hip c arrier mechanical dimensions: figure 8: device package - 9 x 9mm ceramic leadless chip carrier 20% 80% t r 20% t f 80% clock inputs and outputs v p - p v cc - 0.85 ndif_clk dif_clk cross points v p-p v cmr + 0.5 nfout fout t pw t period (output pulse width) t period t pw odc =
preliminary information m2004-x2 datasheet rev 1.3 10 of 10 revised 10sep2003 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high reliability, or other extraordina ry environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. m2004- x 2 f requency t ranslation pll f amily o rdering i nformation figure 9: ordering information consult ics for the availabilit y of other vcso frequencies. example part numbers vcso freq (mhz) temperature part number 622.08 commercial m2004-22 - 622.0800 or m2004-32 - 622.0800 or m2004-42 - 622.0800 or m2004-52 - 622.0800 industrial m2004-22 i 622.0800 or m2004-32 i 622.0800 or m2004-42 i 622.0800 or m2004-52 i 622.0800 table 14: example part numbers -02 none (base) part number: m2004- x2 - xxx.xxxx frequency (mhz) ? - ? = 0 to + 70 o c (commercial) consult ics for available vcso frequencies i = - 40 to + 85 o c (industrial) temperature added features -12 hs/pbo device variant feature key hs/pbo = hitless switching with -32 hs/pbo fixed nbw fixed nbw = fixed narrow bandwidth -22 -52 hs/pbo fixed nbw -42 hs/pbo phase build-out see table 7, on pg. 4 for product differentiation. fixed nbw see m2004-02/-12 product data sheet
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