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| ht82j30r/ht82j30a 16 channel a/d mcu with spi interface rev. 1.00 1 december 20, 2006 general description the ht82j30r/ht82j30a are 8-bit high performance, risc architecture microcontroller devices specifically designed for a/d applications that interface directly to analog signals, such as those from sensors. the mask version ht82j30a is fully pin and functionally compatible with the otp version ht82j30r device. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, watchdog timer, spi interfaces, power down and wake-up functions, en- hance the versatility of these devices to suit a wide range of a/d application possibilities such as sensor signal processing, motor driving, industrial control, con - sumer products, subsystem controllers, etc. with the provision of dual spi interfaces the devices are espe - cially suitable for joystick encoder applications. the ht82j30a is under development and will be avail - able soon. features operating voltage: f sys =4mhz: 2.2v~5.5v crystal clock mode f sys =12mhz: 2.7v~3.7v rc clock mode 35 bidirectional i/o lines (max.) 2 interrupt inputs shared with i/o lines 8-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler on-chip crystal and rc oscillator watchdog timer 4096 15 program memory rom 216 8 data memory ram pfd function for sound generation halt function and wake-up feature reduces power consumption up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 6-level subroutine nesting 16 channel 8-bit resolution a/d converter 1 channel (6+2)-bit pwm output shared with an i/o line bit manipulation instruction 15-bit table read instruction 63 powerful instructions lvr reset voltage of 3v 0.3v all instructions executed in one or two machine cycles pb2, pb3, pd4, pd7 can be optioned as either cmos or nmos outputs integrated dual spi interfaces 28-pin skdip/sop and 44-pin qfp packages technical document tools information faqs application note
block diagram pin assignment ht82j30r/ht82j30a rev. 1.00 2 december 20, 2006 ! " # " $ % & # " " & & # " # ' ( ) " * " " + , ( - , . / 0 1 1 1 1 - 1 0 0 / & # 2 * 3 4 / 4 * 3 / , . . 5 - 0 4 6 $ 6 , 6 / 6 - 0 6 1 . 6 1 . $ 6 1 . 6 1 4 7 ) 2 8 5 0 / , 9 5 0 , / 0 5 9 , / . $ 6 1 . 6 1 / 0 , / . 6 1 0 6 1 , . 1 , 1 1 : . 1 , / 0 5 9 , / 0 5 9 , / 0 5 9 , , , , , , / , , , 0 , 5 , 9 / / / / , / / 1 , , 1 1 . 1 , 4 6 $ 6 , 6 / 6 5 9 , / / 0 . 6 1 . $ 6 1 . 6 1 0 6 1 1 0 0 1 1 1 / / 0 / , . pin description pin name i/o options description pa0~pa2 pa3/pfd pa4/tmr pa5/int0 pa6/int1 pa7 i/o pull-high* wake-up pa3 or pfd bidirectional 8-bit input/output port. each individual pin on this port can be config - ured as a wake-up input by a configuration option. software instructions deter - mine if the pin is a cmos output or schmitt trigger input. configuration options determine which pin on this port have pull-high resistors. the pfd, tmr and ex - ternal interrupt input are pin-shared with pa3, pa4, and pa5 , pa6, respectively. pb0/an0~ pb7/an7 i/o pull-high* bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pin on this port have pull-high resistors. pb is pin-shared with the a/d input pins. the a/d inputs are selected via software instructions once selected as an a/d input, the i/o function and pull-high resistor functions are disable automatically. pb2, pb3 has cmos or nmos output option. pc0/an8~ pc7/an15 i/o pull-high* bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pin on this port have pull-high resistors. pb is pin-shared with the a/d input pins. the a/d inputs are selected via software instructions once selected as an a/d input, the i/o function and pull-high resistor functions are disabled automatically. pd0/pwm0 pd1/scs _a pd2/sck_a pd3/sdi_a pd4/sdo_a pd5~pd6 pd7/sdo_b i/o pull-high* pd0 or pwm bi-directional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pin on this port have pull-high resistors. pd0 is pin-shared with the pwm output se - lected via configuration option. pd1~pd4 are pin-shared with spi interface a. pd4, pd7 have cmos or nmos output options. pd7 is pin-shared with the spi interface b. pf0/sdi_b pf1/sck_b pf2/scs _b i/o pull-high* bidirectional 3-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pin on this port have pull-high resistors. pf0~pf2 is pin-shared with the spi interface b. osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an external rc network or external crystal, de- termined by configuration option, for the internal system clock. if the rc system clock is selected, pin osc2 can be used to measure the system clock at 1/4 sys- tem frequency. res i schmitt trigger reset input. active low vdd positive power supply vss negative power supply, ground avdd analog positive power supply avss analog negative power supply vref 8-bit a/d reference voltage input pin note: * the pull-high resistors of each i/o port are controlled by options. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature...............................0 cto70 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht82j30r/ht82j30a rev. 1.00 3 december 20, 2006 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =12mhz at 56k rc mode 2.7 3.7 v i dd operating current (crystal osc, rc osc) 3v no load, f sys =12mhz adc disable 12ma 5v 46ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports, tmr and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset configuration option: 3v 2.1 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k v ad a/d input voltage 0 v dd v e ad a/d conversion error 3v 0.5 1 lsb 5v 0.5 1 lsb i adc only adc enable, others disable 3v no load 0.5 1 ma 5v 1.5 3 ma ht82j30r/ht82j30a rev. 1.00 4 december 20, 2006 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (rc osc) 2.2v~2.6v 1000 4000 khz 2.7v~5.5v 1000 12000 14000 khz f timer timer i/p frequency (tmr) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t wdt1 watchdog time-out period (wdt osc) 2 15 2 16 t wdtosc t wdt2 watchdog time-out period (system clock) 2 17 2 18 *t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 t sys t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 76 t ad t adcs a/d sample time 32 t ad t cs_sk spi scs to sck time 50 ns t spick spi clock time 400 ns note: *t sys = 1/f sys1 or 1/f sys2 ht82j30r/ht82j30a rev. 1.00 5 december 20, 2006 functional description ht82j30r/ht82j30a rev. 1.00 6 december 20, 2006 execution flow the system clock for the microcontroller is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter controls the sequence in which the instructions stored in the program memory are executed and its contents specify a full range of program memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, a conditional skip execution, loading the pcl register, a subroutine call, an initial reset, an internal interrupt, an external interrupt or a return from a subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise the program proceeds with the next instruction. the lower byte of the program counter is a readable and writeable register. moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. , / , / , / . # ) ; < = # ; 7 < . # ) ; > < = # ; < . # ) ; > < = # ; > < > > % & 2 # ? ; 2 % < execution flow mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 int0 external interrupt 000000000100 int1 external interrupt 000000011000 timer/event counter overflow 000000001000 reserved 000000001100 spi_a interrupt 000000010000 spi_b interrupt 000000010100 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits ht82j30r/ht82j30a rev. 1.00 7 december 20, 2006 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 4k 15 bits, addressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the external interrupt service program. if the int0 input pin is activated, the inter - rupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter inter - rupt service program. if a timer interrupt results from a timer/event counter overflow, and if the interrupt is en - abled and the stack is not full, the program begins exe - cution at location 008h. location 00ch this location is reserved for the a/d converter inter - rupt service program. if the interrupt is activated, when the a/d conversion is completed, if the interrupt is enabled and the stack is not full, the program begins execution at this location. location 010h location 010h is reserved for when 8 bits of data have been received or transmitted successfully from serial interface a. when the related interrupts are enabled, and the stack is not full, the program begins execution at location 010h. location 014h location 014h is reserved for when 8 bits of data have been received or transmitted successfully from serial interface b. when the related interrupts are enabled, and the stack is not full, the program begins execution at location 014h. location 018h this location is reserved for the external interrupt ser - vice program. if the int1 input pin is activated, the in - terrupt is enabled and the stack is not full, the program begins execution at this location. table location any location in the program memory space can be used as a look-up table. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to the tblh register. only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are trans- ferred to the lower portion of tblh. any unused bits are read as 0 . the table higher-order byte register, tblh, is read only. the table pointer, tblp, is a read/write register, which indicates the table location. before accessing the table, the location must be placed in tblp. the tblh register is read only and cannot be restored. if the main routine and the isr (interrupt ser - vice routine) both employ the table read instruction, the contents of tblh in the main routine are likely to be changed by the table read instruction used in the isr and errors can occur. in other words, using the table read instruction in the main routine and the isr simul - taneously should be avoided. however, if the table @ & * . a " & % " 8 ! a " = 2 ! a " 8 " # " " 2 " b " 8 ! a " 6 ! a " 6 1 ! a " = 2 ! a " ( ? 7 ! a 2 ; 4 ' & < ( ? 7 ! a 2 ; 4 ' & < c 5 c / c c c / c 5 c . . . c . . c c program memory instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: *11~*0: table location bits p11~p8: current program counter bits @7~@0: table pointer bits ht82j30r/ht82j30a rev. 1.00 8 december 20, 2006 read instruction has to be applied in both the main rou - tine and the isr, the interrupt is supposed to be dis - abled prior to the table read instruction. it should not be enabled until tblh has been backed up. all table re - lated instructions require two cycles to complete the operation. these areas may function as normal pro - gram memory depending upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub- sequently executed, stack overflow occurs and the first entry will be lost as only the most recent 6 return ad- dresses are stored. data memory ram the data memory is designed with 226 8 bits. the data memory is divided into 2 functional groups: special func - tion registers and general purpose data memory. most of them are read/write, but some are read only. reading any unused locations will return the result 00h . the general purpose data memory, addressed from 28h to ffh, is used for data and control informa - tion under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through the memory pointer registers mp. indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation of [00h] accesses data memory pointed to by mp. reading location 00h itself indirectly will return the result 00h. writing indirectly results in no operation. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) ! # " 2 ! & % c c c , c / c c c 0 c 5 c 9 c c 1 c c c c . c c c c , c / c c c 0 c 5 c 9 c c 1 c c c c . c @ & ' ' & d d + 2 ! & % ; 1 % & < . . c c c c , c / c ' " # ' ' & & " " & ( 1 ( 1 ( c 1 1 4 . . 1 6 1 6 1 6 1 1 6 1 c c 0 c 5 c ram mapping ht82j30r/ht82j30a rev. 1.00 9 december 20, 2006 logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the op - eration sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flags. in addi - tion, operations related to the status register may give different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt in - struction. the pdf flag can be affected only by exe - cuting the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. interrupt the microcontroller provides two external interrupts, an internal timer/event counter overflow interrupt, an a/d converter end-of-conversion interrupt and two spi inter - rupts. the interrupt control registers intc and intc1 both contains the interrupt control bits to set the en - able/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked by clearing the emi bit. this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flags are recorded. if a certain interrupt requires servicing within the service routine, the programmer may set the emi bit and the corre - sponding bit of intc or intc1 to allow interrupt nesting. if the stack is full, the interrupt request will not be ac - knowledged, even if the related interrupt is enabled, un - til the sp is decreased. if immediate service is desired, the stack has to be prevented from becoming full. all interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the pro - gram counter onto the stack and then branching to sub - routines at a specified location in the program memory. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which corrupts the de - sired control sequence, the programmer should save these contents first. external interrupts are triggered by a high to low transi- tion on pins int0 or int1 which will in turn set the re- lated interrupt request flag, which is bit 4 of intc or bit 6 of intc1. when the respective interrupt is enabled, the stack is not full and the external interrupt is active, a sub- routine call to location 004h or 018h will occur. the ex- ternal interrupt request flag and emi bits will cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (bit 5 of intc), caused by a timer overflow. when the inter - rupt is enabled, the stack is not full and the timer/event bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register ht82j30r/ht82j30a rev. 1.00 10 december 20, 2006 counter interrupt request flag is set, a subroutine call to location 00ch will occur. the related interrupt request flag will be reset and the emi bit cleared to disable fur- ther interrupts. the a/d converter end-of-conversion interrupt is initial- ized by setting the a/d end-of-conversion interrupt re- quest flag (bit 6 of intc), caused by an end of a/d conversion. when the interrupt is enabled, the stack is not full and the end of a/d conversion interrupt request flag is set, a subroutine call to location 0ch will occur. the related interrupt request flag will be reset and the emi bit cleared to disable further interrupts. there are two serial interface interrupts, which will be generated when the interface receives or transmits 8-bits of data. these interrupts are indicated by the in - terrupt flags, sif_a; bit 4 of intc1, and sif_b; bit 5 of intc1. the serial interface interrupts are enabled by setting the serial interface interrupt control bits, esii_a; bit 0 of intc1 and esii_b; bit 1 of intc1. after the re - spective interface is enabled by setting the corresponding sben bit, which is bit 4 of either sbcr_a or sbcr_b, if the stack is not full and the corresponding sif_a or sif_b bit is set, a subroutine call to location 10h or 14h occurs. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bits are set to 1 (if the stack is not full). to return from the interrupt subroutine, a ret or reti instruction may be executed. reti will set the emi bit to enable further interrupts, but ret will not. interrupts, occurring in the interval between rising edge of two consecutive t2 pulses, will be serviced on the later of the two t2 pulses, if the corresponding interrupts are enabled. in the case of simultaneous requests the priorities in the follow table apply. these can be masked by clearing the emi bit. interrupt source priority vector int0 external interrupt 1 04h timer/event counter overflow 2 08h end of a/d conversion interrupt 3 0ch spi_a interrupt 4 10h spi_b interrupt 5 14h int1 external interrupt 6 18h the timer/event counter interrupt request flag (tf), exter - nal interrupt request flag (eif), a/d converter request flag (adf), enable timer/event counter bit (eti), enable exter - nal interrupt bit (eei), enable a/d converter interrupt bit (eadi) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eei, eti, eadi are used to control the enabling/disabling of interrupts. these bits bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei_a controls the external interrupt (1= enabled; 0= disabled) 2 eti controls the timer/event counter interrupt (1= enabled; 0= disabled) 3 eadi controls the a/d converter interrupt (1= enabled; 0= disabled) 4 eif_a external interrupt request flag (1= active; 0= inactive) 5 tf internal timer/event counter request flag (1= active; 0= inactive) 6 adf end of a/d conversion interrupt request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc (0bh) register bit no. label function 0 esii_a controls the serial interface interrupt (1= enabled; 0= disabled) 1 esii_b controls the serial interface interrupt (1= enabled; 0= disabled) 2 eei_b controls the int1 external interrupt (1= enabled; 0= disabled) 3, 7 unused bits, read as 0 4 sif_a serial interface interrupt request flag (1= active; 0= inactive) 5 sif_b serial interface interrupt request flag (1= active; 0= inactive) 6 eif_b int1 external interrupt request flag (1= active; 0= inactive) intc1 (1eh) register ht82j30r/ht82j30a rev. 1.00 11 december 20, 2006 prevent the requested interrupt from being serviced. once the interrupt request flags (tf, eif, adf) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. interrupts of - ten occur in an unpredictable manner or need to be ser - viced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged if a call in - struction is executed in the interrupt subroutine. oscillator configuration there are 2 oscillator circuits in the microcontroller. both of them are designed for system clocks, namely the external rc oscillator, the external crystal oscillator and the internal rc oscillator, the choice of which is de- termined by configuration options. the power down mode stops the system oscillator to conserve power. if an rc oscillator is used, an external resistor between osc1 and vdd is required and the resistance must range from 47k to 750k . the system clock, divided by 4, is available on osc2, which can be used to syn- chronize external logic. the rc oscillator provides the most cost effective solution. however, the oscillation frequency may vary with vdd, temperature and pro - cess variations. it is, therefore, not suitable for timing sensitive operations where an accurate oscillator fre - quency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. instead of a crystal, a resonator can also be connected between osc1 and osc2 to obtain a fre - quency reference, but two external capacitors connected between osc1 and osc2 and ground are required. the wdt oscillator is a free running on-chip rc oscillator, and no external components are required. even if the sys - tem enters the power down mode, the system clock is stopped, but the wdt oscillator still works within a period of 65 s at 5v. the wdt oscillator can be disabled by op - tions to conserve power. watchdog timer wdt the clock source of wdt is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), chosen via a configuration op - tion. this timer is designed to prevent software malfunctions or the program jumping to unknown loca - tions. the watchdog timer can be disabled by a config - uration option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. if the internal oscillator, which is an rc oscillator with a nominal period of 65 s at 5v, is selected, it is first di - vided by 32768~65536 to get a time-out period of ap - proximately 2.1s~4.3s. this time-out period may vary with temperature, vdd and process variations. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt instruction will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to . but in the power-down mode, the overflow will initialize a warm reset , and only the program counter and the sp are re- set to zero. to clear the contents of the wdt, three methods are adopted; an external reset (a low level on the res pin), a software instruction or a halt instruc - tion. the software instructions include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depend - ing on the configuration option clr wdt times selec - tion option .ifthe clr wdt is selected (i.e. clr wdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clr wdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may re - set the chip as a result of a time-out. % & 2 # ? / 5 7 a " ! " 2 # 4 * 0 7 a " 4 " 7 * - * ( 4 watchdog timer % & 2 & # " 2 2 & # " 2 2 ! ' " * 3 / system oscillator ht82j30r/ht82j30a rev. 1.00 12 december 20, 2006 power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. the wdt and wdt prescaler will be cleared and re - sume counting again (if the wdt clock comes from the wdt oscillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the power-down mode by means of an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external re - set causes a device initialization and the wdt overflow performs a warm reset . after the to and pdf flags are examined, the reason for chip reset can be deter - mined. the pdf flag is cleared by a system power-up or executing the clr wdt instruction and is set when executing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others re - main in their original status. the port a wake-up and interrupt methods of wake-up can be considered as a continuation of normal execu- tion. each bit in port a can be independently selected to wake-up the device using configuration options. awak- ening from an i/o port stimulus, the program will resume execution of the next instruction. if it awakens from an interrupt, two sequences may occur. if the related inter- rupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next in - struction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. if an in - terrupt request flag is set to 1 before entering the power-down mode, the wake-up function of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume nor - mal operation. in other words, a dummy period will be in - serted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt sub - routine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy pe - riod has finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the power-down mode. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during power-down is different from other chip reset conditions, since it can perform a warm reset that resets only the program counter and sp, leaving the other circuits in their original state. some registers remain unchanged during other reset condi - tions. most registers are reset to their initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish be - tween different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys- tem reset (power-up, wdt time-out or res reset) or the system awakes from the power-down mode. when a system reset occurs, the sst delay is added during the reset period. any wake-up from power-down will enable the sst delay. an extra option load time delay is added during a system reset (power-up, wdt time-out at normal mode or res reset). ht82j30r/ht82j30a rev. 1.00 13 december 20, 2006 the functional unit chip reset status is shown below. program counter 000h interrupt disable prescaler clear wdt clear. after a master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack ? ? e . f e . f reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. " 7 ) " ! & reset timing chart 4 & 4 c ( 2 ' & % & & 7 a " " ! ! 2 reset configuration the register states is summarized in the table. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pf ---- -111 ---- -111 ---- -111 ---- -111 --- -uuu ht82j30r/ht82j30a rev. 1.00 14 december 20, 2006 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* pfc ---- -111 ---- -111 ---- -111 ---- -111 --- -uuu intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu pwm xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu sbcr_a 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu sbdr_a xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sbcr_b 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu sbdr_b xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown timer/event counter a timer/event counter (tmr) is implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up counter whose clock may come from an external source or the system clock. using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. while using the in- ternal clock allows the user to generate an accurate time base. the timer/event counter can generate pfd signal by us- ing an external or internal clock. the pfd frequency is determined by the equation f int /[2 (256-n)]. there are 2 registers related to the timer/event counter; tmr and tmrc. two physical registers are mapped to the tmr location; writing to tmr places the start value into the timer/event counter preload register. reading tmr retrieves the contents of the timer/event counter. the tmrc register is a timer/event counter control reg - ister, which defines some options. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from the external tmr pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to measure a high or low level duration of the external tmr pin. the counting is based on f int . in the event count or timer mode, once the timer/event counter starts counting, it will count from the current con - tents in the timer/event counter to ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates an interrupt re - quest flag (tf; bit 5 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr pin has re - ceived a transient from low to high (or high to low if the te bit is 0 ) it will start counting until the tmr pin re - turns to its original level and resets the ton bit. the measured result will remain in the timer/event counter even if the activated transient occurs again. in other words, only a one cycle measurement can be imple- mented. until the ton bit is again set, the cycle mea- surement will not function even if it receives further transient pulses. note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of a counter overflow, the counter is reloaded from the timer/event counter preload register and issues an interrupt request just like the other two modes. to en - able the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width mea - surement mode, the ton bit will be cleared automati - cally after the measurement cycle is completed. but in the other two modes the ton bit can only be reset by in - structions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the opera - tion mode is, writin ga0toetican disable the interrupt service. in the case of a timer/event counter off condition, writ - ing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. the timer/event counter will still operate until an over - flow occurs. when the timer/event counter is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the programmer. ht82j30r/ht82j30a rev. 1.00 15 december 20, 2006 the bit0~bit2 of the tmrc can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. the overflow signal of the timer/event counter can be used to generate the pfd signal. input/output ports there are 35 bidirectional input/output lines in the microcontroller, labeled as pa, pb, pc, pd and pf, which are mapped to the data memory of [12h], [14h], [16h], [18h] and [22h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the in - puts must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, 18h or 22h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pfc) to control the input/output configura - tion. with this control register, a cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. to function as an in - put, the corresponding latch of the control register must bit no. label function 0 1 2 psc0 psc1 psc2 defines the prescaler stages, psc2, psc1, psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3te defines the tmr active edge of the timer/event counter: in event counter mode (tm1,tm0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (tm1,tm0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 ton enable or disable the timer counting (0=disable; 1=enable) 5 unused bits, read as 0 6 7 tm0 tm1 defines the operating mode (tm1, tm0)= 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc (0eh) register 2 & 4 " ' ) & ' 2 5 7 1 " " 8 2 ' " & 5 7 1 " " 8 1 & 2 ' 8 * 2 g ! . 5 7 & & # 2 5 7 * 3 * - ; > < ! 4 " # " timer/event counter ht82j30r/ht82j30a rev. 1.00 16 december 20, 2006 write 1 . the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, all i/os except pb2, pb3, pd2, pd7 are cmos types. there are options to define pb2, pb3, pd2, pd7 as either cmos or nmos types. these con - trol registers are mapped to locations 13h, 15h, 17h,19h and 23h. after a device reset, these input/output lines remain at high levels or a floating state, depending upon the pull-high configuration options. each bit of these in - put/output latches can be set or cleared using the set [m].i and clr [m].i instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. each i/o line has a pull-high option. once a pull-high op- tion is selected, the i/o line has a pull-high resistor connected, otherwise, there are none. take note that a non-pull-high i/o line operating as an input will be in a floating state. pin pa3 is pin-shared with the pfd signal. if the pfd configuration option is selected, the output signal on pa3, if setup as an output, will be the pfd signal gener- ated by the timer/event counter overflow signal. if setup as an input then the pin will retain its input function. once the pfd configuration option is selected, the pfd output signal is controlled by the pa3 data register. writ - ing a 1 to the pa3 data register will enable the pfd output function and writing 0 will force pin pa3 to re - main at 0 . the i/o functions of pa3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. pa6, pa5 and pa4 are pin-shared with the int0 , int1 and tmr pins respectively. pb and pc can also be used as a/d converter inputs. the a/d function will be described later. there are two spi interfaces which are shared with pins pd1~pd4, pd7 and pf0~pf2. the spi function will be described later. there is a pwm function shared with pin pd0. if the pwm function is enabled, the pwm signal will ap - pear on pin pd0 (if pd0 is setup as an output). writing a 1 to the pd0 data register will enable the pwm output function and writing a 0 will force the pd0 to remain at 0 . the i/o functions of pd0 are shown in the table. i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0 logical input logical output logical input pwm it is recommended that unused or not bonded out i/o . ; , < 4 ? 7 ! ! " * / 2 % * 2 % % & 4 ? 7 ! ; 2 % < ' " & , . ; 4 < h $ 2 1 " 2 2 7 c " ) ! " 1 & 4 " 2 " & ) " ! & ' 2 " & 4 " " & 1 " - , . / 0 1 - 1 0 0 5 - 0 4 h h $ h input/output ports ht82j30r/ht82j30a rev. 1.00 17 december 20, 2006 lines should be set as output pins using software in - structions to minimise power consumption should they be inadvertently setup as floating inputs. pulse width modulator pwm the microcontroller provides a single channel (6+2) bit pulse width modulator output shared with pin pd0. its data register is known as pwm. the frequency source for the pwm counter comes from f sys . the pwm regis - ter is an eight bit register. if the configuration option se - lects pin pd0 to be a pwm output, and if the pin is setup as an output by setting bit pdc.0 to 0 , then writing 1 to the pd0 data register will enable the pwm output func - tion. writing a 0 will force the pd0 to stay at 0 . a pwm cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). each modula - tion cycle has 64 pwm input clock periods. in a (6+2) bit pwm function, the contents of the pwm register is di - vided into two groups. group 1 of the pwm register is denoted by dc which has the value of pwm.7~pwm.2. group 2 is denoted by ac which has the value of pwm.1~pwm.0. in a pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i k i 4 j k 4 i 4 j k 4 i 4 j k , 4 4 # % # 2 @ * 3 / / / / / / / / / / / / / / / / / / / / ' 2 " # % # 2 4 ' 2 " ! " ' @ / * 3 ' 2 " # % # 2 ' 2 " # % # 2 ' 2 " # % # 2 , ' 2 " # % # 2 pwm ht82j30r/ht82j30a rev. 1.00 18 december 20, 2006 a/d converter a 16 channel 8-bit resolution a/d converter is integrated within the microcontroller. the a/d reference voltage is vdd. the a/d converter contains several special regis - ters, which are adr, adcr and acsr. the adr regis - ter is the a/d result register and is read-only. after an a/d conversion has completed, the adr register is read to obtain the conversion result data. the eocb flag will also be automatically cleared to indicate the end of con - version. the adcr register is the a/d converter control register, which selects the analog channel, contains the start a/d conversion control bit and the end of a/d con - version flag. to initiate an a/d conversion, the analog channel is first selected and then the start bit is given a falling edge. when the conversion is complete, the eocb bit will be cleared and an a/d converter interrupt is generated. the acsr register selects the a/d clock source as well as selecting which pins are to be used as a/d inputs. bits 0~3 of adcr are used to select an ana - log input channel. there are a total of 16 channels to se - lect. bits 3~6 of adsr are used to select which pins on port b and port c are setup as normal i/os or a/d in - puts. the eocb bit in the adcr registers, is end of a/d conversion flag. this bit can be monitored to check when the a/d conversion has completed. the start bit in the adcr register is used to initiate a/d conversion process. providing the start bit with a rising edge will reset and start the a/d conversion. when checking for the end of an a/d conversion, the start bit should re- main at 0 and the eocb bit monitored until it is cleared to 0 which indicates the end of conversion. bit 7 of the acsr register is used for testing purposes only and should not be used. bits 1 and bit 0 are used to select the a/d converter clock source. when the a/d conversion has completed, the a/d inter - rupt request flag is set. the eocb bit is set to 1 auto - matically when the start bit is set to 1 . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d7 d6 d5 d4 d3 d2 d1 d0 adr (21h) register acs3 acs2 acs1 acs0 analog channel 0000 an0 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1010 an10 1011 an11 1100 an12 1101 an13 1110 an14 1111 an15 bit no. label function 0~3 acs0~ acs3 analog channel selection 4~5 reserved bit 6 eocb indicates end of a/d conversion (read only). (0 = end of a/d conversion) 7 start starts the a/d conversion. (0 1 0= start; 0 1= reset a/d converter and set eocb to 1 ) adcr (22h) register bit no. label function 0 1 adcs0 adcs1 adcs1,adcs0 : selects the a/d converter clock source 0, 0: f sys /2 0, 1: f sys /8 1, 0: undefined 1, 1: undefined (f wdt for test only) 2 unused bit, read as 0 . 3~6 pcr0~ pcr3 port b & port c configuration selection. if pcr0, pcr1 and pcr2, pcr3 are all zero, the adc circuit is power off to reduce power consumption 7 test for internal test only, read as 1 . acsr (23h) register ht82j30r/ht82j30a rev. 1.00 19 december 20, 2006 pcr3 pcr2 pcr1 pcr0 15 14 13 12 11 10 9876543210 0000pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6pb5pb4pb3pb2pb1pb0 0001pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6pb5pb4pb3pb2pb1an0 0010pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6pb5pb4pb3pb2an1an0 0011pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6pb5pb4pb3an2an1an0 0100pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6pb5pb4an3an2an1an0 0101pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6pb5an4an3an2an1an0 0110pc7pc6pc5pc4pc3pc2pc1pc0pb7pb6an5an4an3an2an1an0 0111pc7pc6pc5pc4pc3pc2pc1pc0pb7an6an5an4an3an2an1an0 1000pc7pc6pc5pc4pc3pc2pc1pc0an7an6an5an4an3an2an1an0 1001pc7pc6pc5pc4pc3pc2pc1an8an7an6an5an4an3an2an1an0 1010pc7pc6pc5pc4pc3pc2an9an8an7an6an5an4an3an2an1an0 1011pc7pc6pc5pc4pc3 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 1100pc7pc6pc5pc4 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 1101pc7pc6pc5 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 1110pc7pc6 an13 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 1111 an15 an14 an13 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0 # 8 & " " 0 # 8 & " " 1 1 1 1 1 1 , - , - g 7 & ' * # 8 & " @ * " 1 # * " " @ 2 # 2 # ) 2 e 1 ' & ! & & e # 8 " & ! g ' * * ' # ! g # & ! " # 2 # ? & a * 3 * 3 5 @ & ' * # 8 1 1 & ! 2 " " , " " " & # " # % # 2 ' ' ' l # & ! 2 " " , ' * # 8 & " & ' * # 8 a/d conversion timing ht82j30r/ht82j30a rev. 1.00 20 december 20, 2006 example: using eoc polling method to detect end of conversion. clr intc ; disable a/d interrupt in interrupt control register mov a, 0010b mov adcr,a ; setup adcr register to configure port pb0~pb3 as a/d inputs and select ; an0 to be connected to the a/d converter mov a, 00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock start_conversion: clr .7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d polling_eoc: sz adcr.6 ; poll the adcr register eoc bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a, adr ; read conversion result from the high byte adrh register mov adr_buffer,a ; save result to user defined register : : jmp start_conversion ; start next a/d conversion example: using interrupt method to detect end of conversion. set intc ; enable a/d interrupt in interrupt control register mov a, 0010b mov adcr,a ; setup adcr register to configure port pb0~pb3 as a/d inputs and select ; an0 to be connected to the a/d converter mov a, 00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock : start_conversion: clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d : : ; interrupt service routine eoc_service routine: mov a_buffer,a ; save acc to user defined register mov a,adr ; read conversion result from the high byte adrh register mov adr_buffer,a ; save result to user defined register clr .7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d mov a,a_buffer ; restore acc from temporary storage reti ht82j30r/ht82j30a rev. 1.00 21 december 20, 2006 mentioned in the description. two corresponding registers, sbcr and sbdr are unique to the serial interface and provide control, status, and data storage. sbcr_a, sbcr_b: serial bus control register bit7 (cks) clock source selection: f sio =f sys /4, select as 0 bit6 (m1), bit5 (m0) master/slave mode and baud rate selection m1, m0: 00 master mode, baud rate= f sio 01 master mode, baud rate= f sio /4 10 master mode, baud rate= f sio /16 11 slave mode bit4 (sben) serial bus enable/disable (1/0) enable: (scs dependent on csen bit) disable enable: sck, sdi, sdo, scs =0 (sckb= 0 ) and waiting for writing data to sbdr (txrx buffer) master mode: write data to sbdr (txrx buffer) start transmission/reception automatically master mode: when the data has been transferred, set trf slave mode: when an sck (and scs dependent on csen) is received, data in the txrx buffer is shifted-out and data on sdi is shifted-in. disable: sck (sck ), sdi, sdo, scs floating bit3 (mls) msb or lsb (1/0) shift first control bit bit2 (csen) serial bus selection signal enable/dis- able (scs ), when csen=0, scsb is floating. bit1 (wcol) this bit is set to 1 if data is written to the sbdr register (txrx buffer) when data is transferred, writing will be ignored if data is written to sbdr (txrx buffer) when data is transferred. bit0 (trf) data transferred or data received used to generate an interrupt. note: data reception is still in operation when the mcu enters the power-down mode. sbdr_a, sbdr_b: serial bus data register data written to sbdr write data to the txrx buffer only data read from sbdr read from sbdr only operating mode description: master transmitter: clock transmission and data i/o started by writing to sbdr master clock transmission initiated by writing to sbdr slave transmitter: data i/o started by clock reception slave receiver: data i/o started by clock reception 0 / , , / 0 6 6 1 0 / , , / 0 6 6 1 $ 6 $ 6 1 6 6 1 1 6 1 6 1 . ( 1 6 1 6 1 . ( @ d d & # ) ' e $ 1 ( 4 ( . 0 / , 0 / , 1 @ ( 1 ( + 1 @ ( 1 + 6 $ $ 6 $ spi serial interface there are two spi interfaces, with each interface containing four basic signals and pins. these are sdi (serial data in - put), sdo (serial data output), sck (serial clock) and scs (slave select pin). note that each of these pin names will be suffixed with either an a or b to denote which sci interface is being used, however to minimise repetition, this will not be ht82j30r/ht82j30a rev. 1.00 22 december 20, 2006 clock polarity= rising (sck ) or falling (sck): 1 or 0 (mask option). modes operations master 1. select cks and select m1, m0 = 00,01,10 2. select csen, mls (the same as the slave) 3. set sben 4. writing data to sbdr data is stored in txrx buffer output sck (and scs ) signals go to step 5 (sio internal operation data stored in txrx buffer, and sdi data is shifted into txrx buffer data transferred, data in txrx buffer is latched into sbdr) 5. check wcol; wcol= 1 clear wcol and go to step 4; wcol= 0 go to step 6 6. check trf or waiting for sbi (serial bus interrupt) 7. read data from sbdr 8. clear trf 9. go to step 4 slave 1. cks don t care and select m1, m0= 11 2. select csen, mls (the same as the master) 3. set sben 4. writing data to sbdr data is stored in txrx buffer waiting for master clock signal (and scs ): sck go to step 5 (sio internal operations sck (scs ) received output data in txrx buffer and sdi data is shifted into txrx buffer data transferred, data in txrx buffer is latched into sbdr) 5. check wcol; wcol= 1 clear wcol, go to step 4; wcol= 0 go to step 6 6. check trf or wait for sbi (serial bus interrupt) 7. read data from sbdr 8. clear trf 9. go to step 4 operation of serial interface wcol: master/slave mode, set while writing to sbdr when data is transferring (transmitting or receiving) and this writing will then be ignored. wcol function can be enabled/disabled by mask option. wcol is set by sio and cleared by users. data transmission and reception are still working when the mcu enters the halt mode. cpol is used to select the clock polarity of sck. it is a mask option. mls: msb or lsb first selection. csen: chip select function enable/disable, csen=1 scs signal function is active. master should output scs signal before scl signal is set and slave data transfer - ring should be disabled (or enabled) before (after) scs signal is received. csen= 0, scs signal is not needed, scs pin (master and slave) should be floating. csen has 2 options: csen mask option is used to enable/dis- able software csen function. if csen mask option is disabled, the software csen is always disabled. if csen mask option is enabled, software csen function can be used. sben= 1 serial bus standby; scs (csen= 1) = 1; scs = floating (csen= 0); sdi= floating; sdo= 1; mas - ter sck= output 1/0 (dependent on cpol mask option), slave sck= floating. sben= 0 serial bus disabled; scs =sdo=1, sdi=sck= floating in master mode, sdi=sdo=sck= floating, scs =1 in slave mode. trf is set by sio and cleared by users. when data transfer (transmission and reception) is completed, trf is set to generate sbi (serial bus interrupt). ht82j30r/ht82j30a rev. 1.00 23 december 20, 2006 $ 0 / , , / 0 0 / , , / 0 0 / , $ ( 4 ( . 1 1 k k ' g " ' 1 1 1 k k ' g " ' 1 ; " * ! 2 2 7 ) " ) ' < $ * 2 0 1 * 2 / , 0 / , 1 ; # " 8 ' " & < 1 * * ( 1 & & 2 8 2 1 ' 2 # ? $ 2 # ? 2 " % 1 2 1 & % . 2 1 4 " 1 4 ( . 2 . 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" & 2 8 1 ' & ' & @ d d & # ) ' e ht82j30r/ht82j30a rev. 1.00 24 december 20, 2006 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as when changing a battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in its origi - nal state for longer than 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. the lvr uses an or function with the external res signal to perform a chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera - tion at 4mhz system clock. e , e e e 9 ( e e ( e 9 & " 2 & f f 2 ! " & ( # 2 low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before starting normal operation. *2: since a low voltage has to be maintained in its original state for longer than 1ms, therefore a 1ms delay enters the reset mode. ht82j30r/ht82j30a rev. 1.00 25 december 20, 2006 options the following table shows all kinds of options in the microcontroller. all of the options must be defined to ensure proper system functioning. items options 1 lock or unlock (1/0) 2 pa0~pa7 wake-up enable or disable (1/0) options 3 wdt clock source (fs) : wdtosc/ ftid (0/1) 4 clr wdt instruction(s): one or two clear wdt instruction(s) (1/0) 5 wdt enable or disable (0/1) 6 pa pull-high enable or disable (1/0) 7 pb pull-high enable or disable (1/0) by nibble 8 pc pull-high enable or disable (1/0) by nibble 9 pd pull-high enable or disable (1/0) by nibble 10 pf pull-high enable or disable (1/0) by nibble 11 pwm enable or disable 12 pfd enable or disable 13 system oscillators 0/1: rc/crystal 14 low voltage reset: enable or disable 15 lvr voltage: 3.0v/3.8v (0/1) 16 sio_a (serial interface) enable or disable (default disable) 17 sio_a_ cpol: clock polarity 1/0 : clock polarity rising or falling edge (default falling edge) 18 sio_a_wcol: enable or disable (default disable) 19 sio_a_csen: enable or disable, csen mask option is used to enable or disable software csen function (default disable) 20 pd4, pb2, pb3, pd7 cmos or nmos output (default cmos) 21 sio_b (serial interface) enable or disable (default disable) 22 sio_ b_cpol: clock polarity 1/0: clock polarity rising/falling edge (default falling edge) 23 sio_b_wcol: enable or disable (default disable) 24 sio_b_csen: enable or disable, csen mask option is used to enable or disable software csen function (default disable) application circuits note: the resistance and capacitance for the reset circuit should be designed to ensure that vdd is stable and re - mains within a valid range of the operating voltage before bringing res high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for refer - ence only) crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k 4mhz resonator (3 pins) 0pf 12k 4mhz resonator (2 pins) 10pf 12k 3.58mhz crystal 0pf 10k 3.58mhz resonator (2 pins) 25pf 10k 2mhz crystal & resonator (2 pins) 25pf 10k 1mhz crystal 35pf 27k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. ht82j30r/ht82j30a rev. 1.00 26 december 20, 2006 - 0 4 ! " , ? m m 0 ? ! ! " . ) 8 2 & & a 2 a 2 g / 0 ! . ! ' " " # " e . f ? e . e . f ? # $ % , . / 1 1 0 0 - 5 0 - . - . instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht82j30r/ht82j30a rev. 1.00 27 december 20, 2006 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht82j30r/ht82j30a rev. 1.00 28 december 20, 2006 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 29 december 20, 2006 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 30 december 20, 2006 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 31 december 20, 2006 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 32 december 20, 2006 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 33 december 20, 2006 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 34 december 20, 2006 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 35 december 20, 2006 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 36 december 20, 2006 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 37 december 20, 2006 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 38 december 20, 2006 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 39 december 20, 2006 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 40 december 20, 2006 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht82j30r/ht82j30a rev. 1.00 41 december 20, 2006 package information 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 330 375 0 15 ht82j30r/ht82j30a rev. 1.00 42 december 20, 2006 5 / 1 . + c 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 ht82j30r/ht82j30a rev. 1.00 43 december 20, 2006 5 / 1 . l + c 44-pin qfp (10 10) outline dimensions symbol dimensions in mm min. nom. max. a13 13.4 b 9.9 10.1 c13 13.4 d 9.9 10.1 e 0.8 f 0.3 g 1.9 2.2 h 2.7 i 0.25 0.5 j 0.73 0.93 k 0.1 0.2 l 0.1 0 7 ht82j30r/ht82j30a rev. 1.00 44 december 20, 2006 , / / / 1 . + c n $ , , , ( product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 62 1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ht82j30r/ht82j30a rev. 1.00 45 december 20, 2006 1 carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24 0.3 p cavity pitch 12 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 ht82j30r/ht82j30a rev. 1.00 46 december 20, 2006 4 . $ 1 ht82j30r/ht82j30a rev. 1.00 47 december 20, 2006 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holmate.com copyright 2006 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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