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x25043/45 1 obsolete product description the x25043/45 combines three popular functions, watchdog timer, voltage supervision, and e 2 prom in a single package. this combination lowers the system cost and reduces the board space requirements. the watchdog timer provides an independent protec- tion system for microcontrollers. during a system failure, the x25043/45 watchdog will respond with a reset / reset signal after a selectable time-out interval. the user selects the interval from three preset values. once selected, the interval does not change, even after cy- cling the power. the system is protected from low voltage conditions by the x25043/45 low v cc detection circuits. when v cc drops below the minimum v cc trip point, the system is reset. reset is asserted until v cc returns and stabilizes. the memory portion of the x25043/45 is a cmos 4096- bit serial e 2 prom, internally organized as 512 x 8. the x25043/45 features a serial peripheral interface (spi) and software protocol allowing operation on a simple three-wire bus. the x25043/45 utilizes xicor? proprietary direct write cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years. 4k x25043/45 512 x 8 bit ?icor, inc. 1994, 1995, 1996 patents pending characteristics subject to change without notice 3844-6.5 2/24/99 t4/c2/d2 ns direct write is a trademark of xicor, inc. programmable watchdog supervisory e 2 prom features programmable watchdog timer low v cc detection reset signal valid to v cc = 1v 1mhz clock rate 512 x 8 bits serial e 2 prom ? byte page mode low power cmos ?0 a standby current ?ma active current 2.7v to 5.5v power supply block lock tm ?rotect 1/4, 1/2 or all of e 2 prom array built-in inadvertent write protection ?ower-up/power-down protection circuitry ?rite latch ?rite protect pin high reliability ?ndurance: 100,000 cycles per byte ?ata retention: 100 years ?sd protection: 2000v on all pins available packages ?-lead pdlp ?-lead soic ?4-lead tssop x25043 = active low reset x25045 = active high reset die photograph a pplication n o tes av ailable an11 ?an21 3844 ill f01 programmable voltage sensor programmable voltage sensor reset control logic reset control logic high voltage generator and control high voltage generator and control 4k bits e 2 prom 4k bits e 2 prom w a t c h d o g t i m e r w a t c h d o g t i m e r serial interface logic serial interface logic
x25043/45 2 obsolete product pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte ad- dresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin is latched on the rising edge of the clock input, while data on the so pin changes after the falling edge of the clock input. chip select ( cs ) when cs is high, the x25043/45 is deselected and the so output pin is at high impedance and, unless an internal write operation is underway, the x25043/45 will be in the standby power mode. cs low enables the x25043/45, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. write protect ( wp ) when wp is low, nonvolatile writes to the x25043/45 are disabled, but the part otherwise functions normally. when wp is held high, all functions, including nonvola- tile writes operate normally. wp going low while cs is still low will interrupt a write to the x25043/45. if the internal write cycle has already been initiated, wp going low will have no affect on a write. reset ( reset , reset) x25043/45, reset /reset is an active low/high, open drain output which goes active whenever v cc falls below the mimimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 200ms. reset /reset also goes active if the watchdog timer is enabled and cs remains either high or low longer than the watchdog time-out period. a falling edge of cs will reset the watchdog timer. pin names symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage reset /reset reset output 3844 pgm t01.1 pin configuration 3844 ill f02.3 cs so wp v ss 1 2 3 4 8 7 6 5 v cc reset/reset sck si 8-lead dip/soic x25043/45 14-lead tssop x25043/45 cs so nc nc nc wp v ss v cc reset/reset nc nc nc sck si 14 13 12 11 10 9 8 1 2 3 4 5 6 7
x25043/45 3 obsolete product principles of operation the x25043/45 is a 512 x 8 e 2 prom designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the x25043/45 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising sck. cs must be low and wp input must be high during the entire operation. the x25043/45 monitors the bus and provides a reset /reset output if there is no bus activity within the preset time period. table 1 contains a list of the instructions and their operation codes. all instructions, addresses and data are transferred msb first. bit 3 of the read and write instructions contain the higher order address bit, a 8 . data input is sampled on the first rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then resume operations. write enable latch the x25043/45 contains a ?rite enable?latch. this latch must be set before a write operation will be completed internally. the wren instruction will set the latch and the wrdi instruction will reset the latch. this latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. the latch is also reset if wp is brought low. status register the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is format- ted as follows: 76 5 4 3210 xx wd1 wd0 bl1 bl0 wel wip 3844 pgm t02 when issuing, wren, wrdi and rdsr commands, it is not necessary to send a byte address or data. the write-in-process (wip) bit indicates whether the x25043/45 is busy with a write operation. when set to a ?? a write is in progress, when set to a ?? no write is in progress. during a write, all other bits are set to ?? the wip bit is read-only. the write enable latch (wel) bit indicates the status of the ?rite enable?latch. when set to a ?? the latch is set, when set to a ?? the latch is reset. the wel bit is read- only and is set by the wren instruction and reset by wrdi instruction or successful completion of a write cycle. the block protect (bl0 and bl1) bits indicate the extent of protection employed. these nonvolatile bits are set by issuing the wrsr instruction and allows the user to select one of four levels of protection and program the watchdog timer. the x25043/45 is divided into four 1024-bit segments. one, two, or all four of the segments may be locked. that is, the user may read the segments but will be unable to alter (write) data within the selected segments. the partitioning is controlled as illustrated below with the state of bl1 and bl0. status register bits array addresses bl1 bl0 protected 00 none 01 $180?1ff 10 $100?1ff 11 $000?1ff 3844 pgm t04 the watchdog timer (wd0 and wd1) bits allow setting of the watchdog time-out function as shown in the table below. these nonvolatile bits are set by issuing the wrsr instruction. status register bits watchdog time-out wd1 wd0 (typical) 00 1.4 seconds 01 600 milliseconds 10 200 milliseconds 11 disabled 3844 pgm t03
x25043/45 4 obsolete product clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the e 2 prom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the x25043/45, followed by the 8-bit byte address. bit 3 of the read instruction contains address a 8 . this bit is used to select the upper or lower half of the device. after the read opcode and byte address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the byte address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached ($1ff) the address counter rolls over to address $000, allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read e 2 prom array operation sequence illustrated in figure 1. to read the status register the cs line is first pulled low to select the device followed by the 8-bit rdsr instruction. after the read status register opcode is sent, the contents of the status register is shifted out on the so line as shown in figure 2. write sequence prior to any attempt to write data into the x25043/45 the ?rite enable?latch must first be set by issuing the wren instruction (see figure 3). cs is first taken low, then the wren instruction is clocked into the x25043/45. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction the write operation will be ignored. to write data to the e 2 prom memory array, the user issues the write instruction, followed by the address and then the data to be written. bit 3 of the write instruction contains address a 8 . this bit is used to select the upper or lower half of the device. this is minimally a twenty-four clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to four bytes of data to the x25043/45. the only restriction is the four bytes must reside on the same page. a page address begins with address x xxxx xx00 and ends with x xxxx xx11. if the byte address counter reaches x xxxx xx11 and the clock continues the counter will roll back to the first address of the page and overwrite any data that may have been written. for the write operation (byte or page write) to be completed, cs can only be brought high after the twenty-fourth, thirty-second, fortieth, or forty-eighth clock. if it is brought high at any other time, the write operation will not be completed. refer to figure 4 and 5 below for a detailed illustration of the write sequences. while the write is in progress, following a status register or e 2 prom write sequence the status register may be read to check the wip bit. during this time the wip bit will be high and all other bits in the status register will be undefined. reset /reset operation the reset (x25043) output is designed to go low whenever v cc has dropped below the minimum trip point and/or the watchdog timer has reached its pro- grammable time-out limit. table 1. instruction set instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register (block lock bits) read 0000 a 8 011 read data from memory array beginning at selected address write 0000 a 8 010 write data to memory array beginning at selected address (1 to 4 bytes) 3844 pgm t05.1 *instructions are shown msb in leftmost position. instructions are transferred msb first.
x25043/45 5 obsolete product figure 1. read e 2 prom array operation sequence the reset (x25045) output is designed to go high whenever v cc has dropped below the minimum trip point and/or the watchdog timer has reached its pro- grammable time-out limit. operational notes the x25043/45 powers-up in the following state: the device is in the low power standby state. ? high to low transition on cs is required to enter an active state and receive an instruction. so pin is high impedance. the ?rite enable?latch is reset. data protection the following circuitry has been included to prevent inadvertent writes: the ?rite enable?latch is reset upon power-up. ? wren instruction must be issued to set the ?rite enable?latch. cs must come high at the proper clock count in order to start a write cycle. the ?rite enable?latch is reset when wp is brought low. figure 2. read status register operation sequence 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 3844 ill f15 012345678910111213141516171819202122 3844 fhd f04 76543210 data out cs sck si so msb high impedance instruction byte address 7 6543210 8 9th bit of address
x25043/45 6 obsolete product figure 3. write enable latch sequence 01234567891011121314151617181920212223 3844 fhd f06 cs sck si so high impedance instruction byte address data byte 76543210 76543210 8 9th bit of address figure 4. byte write operation sequence 01234567 3844 fhd f05 cs si sck high impedance so symbol table wa veform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x25043/45 7 obsolete product figure 5. page write operation sequence figure 6. write status register operation sequence 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 sck si cs 01234567891011121314151617181920212223 3844 fhd f07 sck si instruction byte address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte 4 76543210 76543210 8 9th bit of address 0123456789 cs sck si so high impedance instruction data byte 76543210 10 11 12 13 14 15 3844 ill f08
x25043/45 8 obsolete product notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. absolute maximum ratings* temperature under bias .................. ?5 c to +135 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to v ss ...... ?.0v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c recommended operating conditions temp min. max. commercial 0 c70 c industrial ?0 c +85 c 3844 pgm t06.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v. symbol test max. units conditions c out (2) output capacitance (so, reset , reset) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp )6pfv in = 0v 3844 pgm t10.2 power-up timing symbol parameter min. max. units t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms 3844 pgm t09 supply voltage limits x25043/45 5v 10% x25043/45-2.7 2.7 to 5.5v 3844 pgm t07.3 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc v cc supply current (active) 3 ma sck = v cc x 0.1/v cc x 0.9 @ 1mhz, so = open i sb1 v cc standby current 50 a cs = v cc , v in = v ss or v cc , v cc = 5.5 i sb2 v cc standby current 20 a cs = v cc , v in = v ss or v cc , v cc = 2.7v i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v il (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2ma v oh1 output high voltage v cc ?.8 v i oh = ?.6ma, v cc = 4.5v v oh2 output high voltage v cc ?.4 v i oh = ?4ma, v cc = 2.7v volrs reset output low voltage 0.4 v i ol = 1ma 3844 pgm t08.3
x25043/45 9 obsolete product equivalent a.c. load circuit at 5v vcc a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 3844 pgm t11 notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. a.c. characteristics (over recommended operating conditions, unless otherwise specified) data input timing symbol parameter min. max. units f sck clock frequency 0 1 mhz t cyc cycle time 1000 ns t lead cs lead time 500 ns t lag cs lag time 500 ns t wh clock high time 500 ns t wl clock low time 400 ns t su data setup time 100 ns t h data hold time 100 ns t ri (3) input rise time 2 s t fi (3) input fall time 2 s t cs cs deselect time 500 ns t wc (4) write cycle time 10 ms 3844 pgm t12.2 5v output 100pf 3844 fhd f12.2 5v 4.6k ? reset/reset 100pf data output timing symbol parameter min. max. units f sck clock frequency 0 1 mhz t dis output disable time 500 ns t v output valid from clock low 400 ns t ho output hold time 0 ns t ro (3) output rise time 300 ns t fo (3) output fall time 300 ns 3844 pgm t13.1
x25043/45 10 obsolete product serial output timing serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis 3844 fhd f09 t lag sck cs si so msb in t su t ri t lag 3844 fhd f10 t lead t h lsb in t cs t fi high impedance
x25043/45 11 obsolete product power-up and power-down timing symbol parameter min. typ. max. units t wdo watchdog timeout period, wd1=1,wd0=0 100 200 300 ms wd1=0,wd0=1 450 600 800 ms wd1=0,wd0=0 1 1.4 2 sec t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 100 400 ms 3844 pgm t15.3 cs vs reset /reset timing notes: (5) this parameter is periodically sampled and not 100% tested. reset output timing symbol parameter min. typ. max. units v trip reset trip point voltage, 5v device 4.25 4.5 v reset trip point voltage, 2.7v device 2.55 2.7 v t purst power-up reset timeout 100 400 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 10 s t r (5) v cc rise time 0 ns v rvalid reset valid v cc 1v 3844 pgm t14.3 reset /reset output timing vcc 3844 fhd f13.1 t purst t purst t r t f t rpd reset (x25043) 0 volts v trip v trip reset (x25045) cs 3844 fhd f14.1 t cst reset t wdo t rst reset t wdo t rst
x25043/45 12 obsolete product packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
x25043/45 13 obsolete product packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x25043/45 14 obsolete product packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f32
x25043/45 15 obsolete product device ordering information v cc limits blank = 5v 10% 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package p = 8-lead plastic dip s = 8-lead soic v = 14-lead tssop limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue prod uction and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,88 3, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expe cted to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. part mark convention x25043/45 p t -v x25043/45 x x blank = 8-lead soic p = 8-lead plastic dip v = 14-lead tssop blank = 5v 10%, 0 c to +70 c i = 5v 10%, ?0 c to +85 c f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?0 c to +85 c

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