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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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rev.1.40 apr 14, 2006 page 1 of 38 rej03b0124-0140 rej03b0124-0140 rev.1.40 apr 14, 2006 r8c/18 group, r8c/19 group single-chip 16-bit cmos mcu 1. overview these mcus are fabricated using a high-performa nce silicon gate cmos process, embedding the r8c/tiny series cpu core, and is packaged in a 20-pin molded-plastic lssop, sdip or a 28-pin plastic molded-hwqfn. it implements sophisticated instructions for a high level of instruction efficiency. with 1 mbyte of address space, they are capable of executing instruct ions at high speed. furthermore, the r8c/19 grou p has on-chip data flash rom (1 kb 2 blocks). the difference between the r8c/18 group and r8c/19 group is only the presence or absence of data flash rom. their periphera l functions are the same. 1.1 applications electric household appliances, office equipment, hou sing equipment (sensors, security systems), general industrial equipment, audio equipment, etc.
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 2 of 38 rej03b0124-0140 1.2 performance overview table 1.1 outlines the functions and specifications for r8c/18 group and table 1.2 outlines the functions and specifications for r8c/19 group. table 1.1 functions and specifications for r8c/18 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) operation mode single-chip address space 1 mbyte memory capacity refer to table 1.3 product information for r8c/18 group peripheral functions ports i/o ports: 13 pins (including led drive port) input port: 3 pins led drive ports i/o ports: 4 pins timers timer x: 8 bits 1 channel, timer z: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits 1 channel (input capture and output compare circuits) serial interfaces 1 channel clock synchronous serial i/o, uart 1 channel uart comparator 1-bit comparator: 1 circuit, 4 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable, count source protection mode interrupts internal: 10 sources, external: 4 sources, software: 4 sources, priority levels: 7 levels clock generation circuits 2 circuits ? main clock oscillation circuit (with on-chip feedback resistor) ? on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has frequency adjustment function oscillation stop detection function main clock oscillation st op detection function voltage detection circuit on-chip power-on reset circuit on-chip electric characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) current consumption typ. 9 ma (vcc = 5.0 v, f(xin) = 20 mhz, comparator stopped) typ. 5 ma (vcc = 3.0v, f(xin) = 10 mhz, comparator stopped) typ. 35 a (vcc = 3.0 v, wait mode, peripheral clock off) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 100 times operating ambient temperature -20 to 85 c -40 to 85 c (d version) package 20-pin molded-plastic lssop 20-pin molded-plastic sdip 28-pin molded-plastic hwqfn
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 3 of 38 rej03b0124-0140 table 1.2 functions and specifications for r8c/19 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) operation mode single-chip address space 1 mbyte memory capacity refer to table 1.4 product information for r8c/19 group peripheral functions ports i/o ports: 13 pins (including led drive port) input port: 3 pins led drive ports i/o ports: 4 pins timers timer x: 8 bits 1 channel, timer z: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits 1 channel (input capture and output compare circuits) serial interfaces 1 channel clock synchronous serial i/o, uart 1 channel uart comparator 1-bit comparator: 1 circuit, 4 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable, count source protection mode interrupts internal: 10 sources, external: 4 sources, software: 4 sources, priority levels: 7 levels clock generation circuits 2 circuits ? main clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (h igh speed, low speed) high-speed on-chi p oscillator has frequency adjustment function oscillation stop detection function main clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electric characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) current consumption typ. 9 ma (vcc = 5.0 v, f(xin) = 20 mhz, comparator stopped) typ. 5 ma (vcc = 3.0 v, f(xin) = 10mhz, comparator stopped) typ. 35 a (vcc = 3.0 v, wait mode, peripheral clock off) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 10,000 times (data flash) 1,000 times (program rom) operating ambient temperature -20 to 85 c -40 to 85 c (d version) package 20-pin molded-plastic lssop 20-pin molded-plastic sdip 28-pin molded-plastic hwqfn
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 4 of 38 rej03b0124-0140 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c/tiny series cpu core 8 4 1 3 timers timer x (8 bits) timer z (8 bits) timer c (16 bits) comparator (1 bit 4 channels) system clock generator xin-xout high-speed on-chip oscillator low-speed on-chip oscillator uart or clock synchronous serial i/o (8 bits 1 channel) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports port p1 port p3 port p4 notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. uart (8 bits 1 channel) peripheral functions
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 5 of 38 rej03b0124-0140 1.4 product information table 1.3 lists product information for r8c/18 gro up and table 1.4 lists product information for r8c/19 group. (d): under development figure 1.2 type number, memory size, and package of r8c/18 group table 1.3 product information for r8c/18 group current of apr. 2006 type no. rom capacity ram capacity package type remarks r5f21181sp 4 kbytes 384 bytes plsp0020jb-a flash memory version r5f21182sp 8 kbytes 512 bytes plsp0020jb-a r5f21183sp 12 kbytes 768 bytes plsp0020jb-a r5f21184sp 16 kbytes 1 kbyte plsp0020jb-a r5f21181dsp (d) 4 kbytes 384 bytes plsp0020jb-a d version R5F21182DSP (d) 8 kbytes 512 bytes plsp0020jb-a r5f21183dsp (d) 12 kbytes 768 bytes plsp0020jb-a r5f21184dsp (d) 16 kbytes 1 kbyte plsp0020jb-a r5f21181dd 4 kbytes 384 bytes prdp 0020ba-a flash memory version r5f21182dd 8 kbytes 512 bytes prdp0020ba-a r5f21183dd 12 kbytes 768 bytes prdp0020ba-a r5f21184dd 16 kbytes 1 kbyte prdp0020ba-a r5f21182np 8 kbytes 512 bytes pwqn0028ka-b flash memory version r5f21183np 12 kbytes 768 bytes pwqn0028ka-b r5f21184np 16 kbytes 1 kbyte pwqn0028ka-b type no. r 5 f 21 18 4 d sp package type: sp: plsp0020jb-a dd: prdp0020ba-a np: pwqn0028ka-b classification d: operating ambient temperature -40c to 85c no symbol: operating ambient temperature -20c to 85c rom capacity 2: 8 kb 3: 12 kb 4: 16 kb r8c/18 group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductors
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 6 of 38 rej03b0124-0140 (d): under development figure 1.3 type number, memory size, and package of r8c/19 group table 1.4 product information for r8c/19 group current of apr. 2006 type no. rom capacity ram capacity package type remarks program rom data flash r5f21191sp 4 kbytes 1 kbyte 2 384 bytes plsp0020jb-a flash memory version r5f21192sp 8 kbytes 1 kbyte 2 512 bytes plsp0020jb-a r5f21193sp 12 kbytes 1 kbyte 2 768 bytes plsp0020jb-a r5f21194sp 16 kbytes 1 kbyt e 2 1 kbyte plsp0020jb-a r5f21191dsp (d) 4 kbytes 1 kbyte 2 384 bytes plsp0020jb-a d version r5f21192dsp (d) 8 kbytes 1 kbyte 2 512 bytes plsp0020jb-a r5f21193dsp (d) 12 kbytes 1 kbyte 2 768 bytes plsp0020jb-a r5f21194dsp (d) 16 kbytes 1 kbyte 2 1 kbyte plsp0020jb-a r5f21191dd 4 kbytes 1 kbyte 2 384 bytes prdp0020ba-a flash memory version r5f21192dd 8 kbytes 1 kbyte 2 512 bytes prdp0020ba-a r5f21193dd 12 kbytes 1 kbyte 2 768 bytes prdp0020ba-a r5f21194dd 16 kbytes 1 kbyte 2 1 kbyte prdp0020ba-a r5f21192np 8 kbytes 1 kbyte 2 512 bytes pwqn0028ka-b flash memory version r5f21193np 12 kbytes 1 kbyte 2 768 bytes pwqn0028ka-b r5f21194np 16 kbytes 1 kbyte 2 1 kbyte pwqn0028ka-b type no. r 5 f 21 19 4 d sp package type: sp: plsp0020jb-a dd: prdp0020ba-a np: pwqn0028ka-b classification d: operating ambient temperature -40c to 85c no symbol: operating ambient temperature -20 c to 85c rom capacity 2: 8 kb 3: 12 kb 4: 16 kb r8c/19 group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductors
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 7 of 38 rej03b0124-0140 1.5 pin assignments figure 1.4 shows pin assignments for plsp0020jb-a package (top view), figure 1.5 shows pin assignments for prdp0020ba-a package (top view) and figure 1.6 shows pin assignments for pwqn0028ka-b package (top view). figure 1.4 pin assignments for plsp0020jb-a package (top view) 1 2 3 4 5 6 7 8 9 10 20 p3_4/cmp1_1 19 p3_3/tcin/int3/cmp1_0 18 p1_0/ki0/an8/cmp0_0 17 p1_1/ki1/an9/cmp0_1 16 p4_2/vref 15 p1_2/ki2/an10/cmp0_2 14 p1_3/ki3/an11/tzout 13 p1_4/txd0 12 p1_5/rxd0/cntr01/int11 11 p1_6/clk0 p3_5/cmp1_2 p3_7/cntr0/txd1 reset xout/p4_7 (1) vss/avss xin/p4_6 vcc/avcc mode p4_5/int0/rxd1 p1_7/cntr00/int10 pin assignments (top view) package: plsp0020jb-a(20p2f-a) r8c/18 group r8c/19 group note: 1. p4_7 is an input-only port.
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 8 of 38 rej03b0124-0140 figure 1.5 pin assignments for prdp0020ba-a package (top view) 1 2 3 4 5 6 7 8 9 10 20 p3_4/cmp1_1 19 p3_3/tcin/int3/cmp1_0 18 p1_0/ki0/an8/cmp0_0 17 p1_1/ki1/an9/cmp0_1 16 p4_2/vref 15 p1_2/ki2/an10/cmp0_2 14 p1_3/ki3/an11/tzout 13 p1_4/txd0 12 p1_5/rxd0/cntr01/int11 11 p1_6/clk0 p3_5/cmp1_2 p3_7/cntr0/txd1 reset xout/p4_7 (1) vss/avss xin/p4_6 vcc/avcc mode p4_5/int0/rxd1 p1_7/cntr00/int10 r8c/18 group r8c/19 group package: prdp0020ba-a(20p4b) note: 1. p4_7 is an input-only port. pin assignments (top view)
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 9 of 38 rej03b0124-0140 figure 1.6 pin assignments for pwqn0028ka-b package (top view) p1_4/txd0 p1_5/rxd0/cntr01/int11 p1_6/clk0 p1_7/cntr00/int10 p4_5/int0/rxd1 mode vcc/avcc p1_1/an9/ki1/cmp0_1 p1_0/an8/ki0/cmp0_0 pin assignment (top view) package: pwqn0028ka-b(28pjw-b) r8c/18 group r8c/19 group notes: 1. p4_7 is a port for the input. 14 13 12 11 10 9 8 22 23 24 25 26 27 28 p3_3/tcin/int3/cmp1_0 p3_4/cmp1_1 p3_5/cmp1_2 p3_7/cntr0/txd1 reset 1 2 3 4 5 6 7 21 20 19 18 17 16 15 nc xout/p4_7 (1) vss/avss nc nc xin/p4_6 nc p1_3/an11/ki3/tzout p1_2/an10/ki2/cmp0_2 nc nc nc p4_2/vref nc
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 10 of 38 rej03b0124-0140 1.6 pin functions table 1.5 lists pin functions, table 1.6 lists pin name information by pin number of plsp0020jb-a, prdp0020ba-a packages, and table 1.7 lists pin na me information by pin number of pwqn0028ka- b package. i: input o: output i/ o: input and output table 1.5 pin functions type symbol i/o type description power supply input vcc vss i apply 2.7 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss i power supply for the comparator connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. main clock input xin i these pins are provided for main clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. to use an external clock, input it to the xin pin and leave the xout pin open. main clock output xout o int interrupt int0 , int1 , int3 iint interrupt input pins key input interrupt ki0 to ki3 i key input interrupt input pins timer x cntr0 i/o timer x i/o pin cntr0 o timer x output pin timer z tzout o timer z output pin timer c tcin i timer c input pin cmp0_0 to cmp0_2, cmp1_0 to cmp1_2 o timer c output pins serial interface clk0 i/o transfer clock i/o pin rxd0, rxd1 i serial data input pins txd0, txd1 o serial data output pins reference voltage input vref i reference voltage input pin to comparator comparator an8 to an11 i analog input pins to comparator i/o port p1_0 to p1_7, p3_3 to p3_5, p3_7, p4_5 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. p1_0 to p1_3 also function as led drive ports. input port p4_2, p4_6, p4_7 i input-only ports
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 11 of 38 rej03b0124-0140 table 1.6 pin name information by pin number of plsp0020jb-a, prdp0020ba-a packages pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface comparator 1 p3_5 cmp1_2 2p3_7 cntr0 txd1 3 reset 4xoutp4_7 5 vss/avss 6xinp4_6 7 vcc/avcc 8mode 9p4_5 int0 rxd1 10 p1_7 int10 cntr00 11 p1_6 clk0 12 p1_5 int11 cntr01 rxd0 13 p1_4 txd0 14 p1_3 ki3 tzout an11 15 p1_2 ki2 cmp0_2 an10 16 vref p4_2 17 p1_1 ki1 cmp0_1 an9 18 p1_0 ki0 cmp0_0 an8 19 p3_3 int3 tcin/cmp1_0 20 p3_4 cmp1_1
r8c/18 group, r8c/19 group 1. overview rev.1.40 apr 14, 2006 page 12 of 38 rej03b0124-0140 table 1.7 pin name information by pin number of pwqn0028ka-b package pin number control pin port i/o pin of peripheral function interrupt timer serial interface comparator 1nc 2xoutp4_7 3 vss/avss 4nc 5nc 6xinp4_6 7nc 8 vcc/avcc 9mode 10 p4_5 int0 rxd1 11 p1_7 int10 cntr00 12 p1_6 clk0 13 p1_5 int11 cntr01 rxd0 14 p1_4 txd0 15 nc 16 p1_3 ki3 tzout an11 17 p1_2 ki2 cmp0_2 an10 18 nc 19 nc 20 vref p4_2 21 nc 22 p1_1 ki1 cmp0_1 an9 23 p1_0 ki0 cmp0_0 an8 24 p3_3 int3 tcin/cmp1_0 25 p3_4 cmp1_1 26 p3_5 cmp1_2 27 p3_7 cntr0 txd1 28 reset
r8c/18 group, r8c/19 group 2. ce ntral processing unit (cpu) rev.1.40 apr 14, 2006 page 13 of 38 rej03b0124-0140 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4-high order bits of intb are intbh and the 16-low bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r0l (low-order of r0) r1h (high-order of r1) r1l (low-order of r1)
r8c/18 group, r8c/19 group 2. ce ntral processing unit (cpu) rev.1.40 apr 14, 2006 page 14 of 38 rej03b0124-0140 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, arithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r 0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indire ct addressing and address register relative addressing. it is also used for transfer, arit hmetic and logic operations. a1 is analogous to a0. a1 can be combined with a0 and used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates t he start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide, indicates the address of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointer (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operat ion results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. r egister bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when the operation results in an overflow; otherwise to 0.
r8c/18 group, r8c/19 group 2. ce ntral processing unit (cpu) rev.1.40 apr 14, 2006 page 15 of 38 rej03b0124-0140 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt request is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. if a requested interrupt has higher priority than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/18 group, r8c/19 group 3. memory rev.1.40 apr 14, 2006 page 16 of 38 rej03b0124-0140 3. memory 3.1 r8c/18 group figure 3.1 is a memory map of r8c/18 group. the r8c/18 group has 1 mbyte of address space from addresses 00000h to fffffh. the internal rom area is allocated lower addresses, beginning with address 0ffffh. for example, a 16-kbyte internal rom is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. they store the starting address of each interrupt routine. the internal ram is allocated higher addresses, beginning with address 00400h. for example, a 1- kbyte internal ram area is allocated addresse s 00400h to 007ffh. the internal ram is used not only for storing data but also for calling subroutine s and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresses within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.1 memory map of r8c/18 group undefined instruction overflow brk instruction address match single step watchdog timer ? oscillation stop detection ? voltage monitor 2 address break (reserved) reset part number internal rom internal ram size address 0yyyyh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom expanded area internal ram sfr (see 4. special function registers (sfrs) ) 0ffffh 0ffdch size address 0xxxxh note: 1. the blank regions are reserved. do not access locations in these regions. r5f21184sp, r5f21184dsp, r5f21184dd, r5f21184np r5f21183sp, r5f21183dsp, r5f21183dd, r5f21183np r5f21182sp, R5F21182DSP, r5f21182dd, r5f21182np r5f21181sp, r5f21181dsp, r5f21181dd 16 kbytes 12 kbytes 8 kbytes 4 kbytes 0c000h 0d000h 0e000h 0f000h 1 kbyte 768 bytes 512 bytes 384 bytes 007ffh 006ffh 005ffh 0057fh
r8c/18 group, r8c/19 group 3. memory rev.1.40 apr 14, 2006 page 17 of 38 rej03b0124-0140 3.2 r8c/19 group figure 3.2 is a memory map of r8c/19 group. t he r8c/19 group has 1 mbyte of address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower addresses, beginning with address 0ffffh. for example, a 16-kbyte internal rom area is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. they store the starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram is allocated higher addresses, beginning with address 00400h. for example, a 1- kbyte internal ram area is allocated addresse s 00400h to 007ffh. the internal ram is used not only for storing data but also for calling subroutine s and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresses within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/19 group undefined instruction overflow brk instruction address match single step watchdog timer ? oscillation stop detection ? voltage monitor 2 address break (reserved) reset part number internal rom internal ram size address 0yyyyh 16 kbytes 12 kbytes 8 kbytes 4 kbytes 0c000h 0d000h 0e000h 0f000h 1 kbyte 768 bytes 512 bytes 384 bytes 007ffh 006ffh 005ffh 0057fh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) expanded area internal ram sfr (see 4. special function registers (sfrs) ) 0ffffh 0ffdch size address 0xxxxh 02bffh 02400h internal rom (data flash) (1) notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. r5f21194sp, r5f21194dsp, r5f21194dd, r5f21194np r5f21193sp, r5f21193dsp, r5f21193dd, r5f21193np r5f21192sp, r5f21192dsp, r5f21192dd, r5f21192np r5f21191sp, r5f21191dsp, r5f21191dd
r8c/18 group, r8c/19 group 4. spec ial function registers (sfrs) rev.1.40 apr 14, 2006 page 18 of 38 rej03b0124-0140 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.4 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register. 3. after hardware reset. 4. after power-on reset or voltage monitor 1 reset. 5. software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h address match interrupt enable register aier 00h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00011111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h x0h 0013h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h x0h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 001dh 001eh int0 input filter select register int0f 00h 001fh 0020h high-speed on-chip oscillator control register 0 hra0 00h 0021h high-speed on-chip oscillator control register 1 hra1 when shipping 0022h high-speed on-chip oscillator control register 2 hra2 00h 0023h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 00h (3) 01000000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (2) vw1c 0000x000b (3) 0100x001b (4) 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh
r8c/18 group, r8c/19 group 4. spec ial function registers (sfrs) rev.1.40 apr 14, 2006 page 19 of 38 rej03b0124-0140 table 4.2 sfr information (2) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh comparator conversion interrupt control register adic xxxxx000b 004fh 0050h compare 1 interrupt control register cmp1ic xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h 0056h timer x interrupt control register txic xxxxx000b 0057h 0058h timer z interrupt control register tzic xxxxx000b 0059h int1 interrupt control register int1ic xxxxx000b 005ah int3 interrupt control register int3ic xxxxx000b 005bh timer c interrupt control register tcic xxxxx000b 005ch compare 0 interrupt control register cmp0ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/18 group, r8c/19 group 4. spec ial function registers (sfrs) rev.1.40 apr 14, 2006 page 20 of 38 rej03b0124-0140 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. when the output compare mode is selected (the tcc13 bit in the tcc1 register = 1), the value is set to ffff 16 . address register symbol after reset 0080h timer z mode register tzmr 00h 0081h 0082h 0083h 0084h timer z waveform output control register pum 00h 0085h prescaler z register prez ffh 0086h timer z secondary register tzsc ffh 0087h timer z primary register tzpr ffh 0088h 0089h 008ah timer z output control register tzoc 00h 008bh timer x mode register txmr 00h 008ch prescaler x register prex ffh 008dh timer x register tx ffh 008eh timer count source setting register tcss 00h 008fh 0090h timer c register tc 00h 0091h 00h 0092h 0093h 0094h 0095h 0096h external input enable register inten 00h 0097h 0098h key input enable register kien 00h 0099h 009ah timer c control register 0 tcc0 00h 009bh timer c control register 1 tcc1 00h 009ch capture, compare 0 register tm0 00h 009dh 00h (2) 009eh compare 1 register tm1 ffh 009fh ffh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h uart transmit/receive control register 2 ucon 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh
r8c/18 group, r8c/19 group 4. spec ial function registers (sfrs) rev.1.40 apr 14, 2006 page 21 of 38 rej03b0124-0140 table 4.4 sfr information (4) (1) x: undefined notes: 1. the blank regions, 0100h to 01b2h and 01b8h to 02ffh are al l reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a program. use a flash programmer to write to it. address register symbol after reset 00c0h a/d register ad xxh 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00000xxxb 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h 00e1h port p1 register p1 xxh 00e2h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 xxh 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch pull-up control register 0 pur0 00xx0000b 00fdh pull-up control register 1 pur1 xxxxxx0xb 00feh port p1 drive capacity control register drr 00h 00ffh timer c output control register tcout 00h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 0ffffh optional function select register ofs (note 2)
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 22 of 38 rej03b0124-0140 5. electrical characteristics notes: 1. v cc = 2.7 to 5.5 v at t opr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. typical values when average output current is 100 ms. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage v cc = av cc -0.3 to 6.5 v av cc analog supply voltage v cc = av cc -0.3 to 6.5 v v i input voltage -0.3 to v cc +0.3 v v o output voltage -0.3 to v cc +0.3 v p d power dissipation t opr = 25 c300mw t opr operating ambient temperature -20 to 85 / -40 to 85 (d version) c t stg storage temperature -65 to 150 c table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc supply voltage 2.7 ? 5.5 v av cc analog supply voltage ? v cc ? v v ss supply voltage ? 0 ? v av ss analog supply voltage ? 0 ? v v ih input ?h? voltage 0.8v cc ? v cc v v il input ?l? voltage 0 ? 0.2v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh (peak) ?? -60 ma i oh(peak) peak output ?h? current ?? -10 ma i oh(avg) average output ?h? current ?? -5 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol (peak) ?? 60 ma i ol(peak) peak output ?l? currents except p1_0 to p1_3 ?? 10 ma p1_0 to p1_3 drive capacity high ?? 30 ma drive capacity low ?? 10 ma i ol(avg) average output ?l? current except p1_0 to p1_3 ?? 5ma p1_0 to p1_3 drive capacity high ?? 15 ma drive capacity low ?? 5ma f (xin) main clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 23 of 38 rej03b0124-0140 notes: 1. v cc = 2.7 to 5.5 v at t opr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. if f1 exceeds 10 mhz, divided f1 and ensure t he comparator conversion operating clock frequency ( ad ) is 10 mhz or below. 3. if avcc is less than 4.2 v, divided f1 and ensure the comparator conversion operating clock frequency ( ad ) is f1/2 or below. figure 5.1 port p1, p3, and p4 measurement circuit table 5.3 comparator characteristics symbol parameter conditions standard unit min. typ. max. ? resolution ?? 1bit ? absolute accuracy ad = 10 mhz (3) ?? 20 mv t conv conversion time ad = 10 mhz (3) 1 ?? s v ref reference voltage 0 ? av cc v v ia analog input voltage 0 ? av cc v ? comparator conversion operating clock frequency (2) 1 ? 10 mhz p1 p3 p4 30pf
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 24 of 38 rej03b0124-0140 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. if emergency processing is required, a su spend request can be generated independent of th is characteristic. in that case the normal time delay to suspend can be applied to the request.how ever, we recommend that a suspend request with an interval of less than 650 s is only used once because, if the suspend state co ntinues, erasure cannot operate and the incidence of erasure error rises. 5. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, aver aging the number of erase operations between block a and block b can further reduce the effective number of rewrites. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring programming/erasure failure rate in formation should contact thei r renesas technical support representative. 8. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/18 group 100 (3) ?? times r8c/19 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (8) ambient temperature = 55 c20 ?? year
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 25 of 38 rej03b0124-0140 notes: 1. v cc = 2.7 to 5.5 v at t opr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. if emergency processing is required, a suspend request can be generated independent of this characte ristic. in that case the normal time delay to suspend can be applied to the request. howe ver, we recommend that a suspend request with an interval of less than 650 s is only used once because, if the suspend state continues, erasure cannot operate and the incidence of erasure error rises. 5. in a system that executes multiple pr ogramming operations, the actu al erasure count can be redu ced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of re writes can be minimized by pr ogramming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, a ttempt to execute the clear status regist er command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring programming/erasure failure rate info rmation should contact their renesas technical support representative. 8. -40 c for d version. 9. the data hold time includes time that the power supply is off or th e clock is not supplied. figure 5.2 transition time to suspend table 5.5 flash memory (data flash block a, block b) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature -20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year fmr46 suspend request (maskable interrupt request) fixed time (97 s) t d(sr-sus) clock-dependent time access restart
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 26 of 38 rej03b0124-0140 notes: 1. the measurement condition is v cc = 2.7 v to 5.5 v and t opr = -40 c to 85 c. 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. 3. ensure that v det2 > v det1 . notes: 1. the measurement condition is v cc = 2.7 v to 5.5 v and t opr = -40 c to 85 c. 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca27 bit in the vca2 register to 0. 4. ensure that v det2 > v det1 . table 5.6 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (3) 2.70 2.85 3.00 v ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 600 ? na t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 100 s vccmin mcu operating voltage minimum value 2.7 ?? v table 5.7 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level (4) 3.00 3.30 3.60 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 600 ? na t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 27 of 38 rej03b0124-0140 notes: 1. this condition is not appl icable when using with vcc 1.0 v. 2. when turning power on after the time to hold the external power below effective voltage (v por1 ) exceeds10 s, refer to table 5.9 reset circuit electrical characteristics (when not using voltage monitor 1 reset) . 3. t w(por2) is the time to hold the external power below effective voltage (v por2 ). notes: 1. when not using voltage monitor 1, use with vcc 2.7 v. 2. t w(por1) is the time to hold the external power below effective voltage (v por1 ). figure 5.3 reset circuit electrical characteristics table 5.8 reset circuit electrical characte ristics (when using voltage monitor 1 reset) symbol parameter condition standard unit min. typ. max. v por2 power-on reset valid voltage -20 c to p r 85 c ?? v det1 v t w(vpor2-vdet1) supply voltage rising time when power-on reset is deasserted (1) -20 c to p r 85 c, t w(por2) 0s (3) ?? 100 ms table 5.9 reset circuit electrical characteri stics (when not using voltage monitor 1 reset) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage -20 c topr 85 c ?? 0.1 v t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted 0 c topr 85 c, t w(por1) 10 s (2) ?? 100 ms t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted -20 c topr < 0 c, t w(por1) 30 s (2) ?? 100 ms t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted -20 c topr < 0 c, t w(por1) 10 s (2) ?? 1ms t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted 0 c topr 85 c, t w(por1) 1 s (2) ?? 0.5 ms notes: 1. hold the voltage inside the mcu operation voltage range (vccmin or above) within the sampling time. 2. the sampling clock can be selected. refer to 7. voltage detection circuit for details. 3. v det1 indicates the voltage detection level of the voltage detection 1 circuit. refer to 7. voltage detection circuit for details. v det1 (3) v por1 internal reset signal (?l? valid) t w(por1) t w(vpor1?vdet1) sampling time (1, 2) v det1 (3) 1 f ring-s 32 1 f ring-s 32 v por2 vccmin t w(por2) t w(vpor2?vdet1)
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 28 of 38 rej03b0124-0140 notes: 1. the measurement condition is v cc = 5.0 v and t opr = 25 c. 2. refer to 10.6.4 high-speed on-chip oscillator clock for notes on high-speed on-chip oscillator clock. 3. the standard value shows when the hra1 register is assumed as the value in shipping and the hra2 register value is set to 00h. notes: 1. the measurement condition is v cc = 2.7 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until cpu clock supply starts after t he interrupt is acknowledged to exit stop mode. table 5.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency when the reset is deasserted v cc = 5.0 v, t opr = 25 c ? 8 ? mhz ? high-speed on-chip oscillat or frequency temperature supply voltage dependence (2) 0 to +60 c/5 v 5 % (3) 7.76 ? 8.24 mhz -20 to +85 c/2.7 to 5.5 v (3) 7.68 ? 8.32 mhz -40 to +85 c/2.7 to 5.5 v (3) 7.44 ? 8.32 mhz table 5.11 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 29 of 38 rej03b0124-0140 note: 1. v cc = 4.2 to 5.5 v at t opr = -20 to 85 c / -40 to 85 c, f(xin) = 20 mhz, unless otherwise specified. table 5.12 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except x out i oh = -5 ma v cc ? 2.0 ? v cc v i oh = -200 av cc ? 0.3 ? v cc v x out drive capacity high i oh = -1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except p1_0 to p1_3, x out i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v p1_0 to p1_3 drive capacity high i ol = 15 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v drive capacity low i ol = 200 a ?? 0.45 v x out drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , cntr0, cntr1, tcin, rxd0 0.2 ? 1.0 v reset 0.2 ? 2.2 v i ih input ?h? current vi = 5 v ?? 5.0 a i il input ?l? current vi = 0 v ?? -5.0 a r pullup pull-up resistance vi = 0 v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? f ring-s low-speed on-chip oscillator frequency 40 125 250 khz v ram ram hold voltage during stop mode 2.0 ?? v
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 30 of 38 rej03b0124-0140 table 5.13 electrical char acteristics (2) [vcc = 5 v] (topr = -40 to 85 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss , comparator is stopped high-speed mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 814ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5 ? ma medium- speed mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 3 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode main clock off high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz no division ? 48ma main clock off high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 fmr47 = 1 ? 110 300 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = 0 ? 40 80 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = 0 ? 38 76 a stop mode main clock off, topr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = 0 ? 0.8 3.0 a
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 31 of 38 rej03b0124-0140 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at ta = 25 c) [v cc = 5 v] figure 5.4 xin input timing diagram when v cc = 5 v figure 5.5 cntr0 input, cntr1 input, int1 input timing diagram when v cc = 5 v notes: 1. when using timer c input capture mode, adjust the cycle time to (1/timer c count source frequency x 3) or above. 2. when using timer c input capture mode, adjust the pulse width to (1/timer c count source frequency x 1.5) or above. figure 5.6 tcin input, int3 input timing diagram when v cc = 5 v table 5.14 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns table 5.15 cntr0 input, cntr1 input, int1 input symbol parameter standard unit min. max. t c(cntr0) cntr0 input cycle time 100 ? ns t wh(cntr0) cntr0 input ?h? width 40 ? ns t wl(cntr0) cntr0 input ?l? width 40 ? ns table 5.16 tcin input, int3 input symbol parameter standard unit min. max. t c(tcin) tcin input cycle time 400 (1) ? ns t wh(tcin) tcin input ?h? width 200 (2) ? ns t wl(tcin) tcin input ?l? width 200 (2) ? ns t wh(xin) t c(xin) t wl(xin) x in input v cc = 5 v t wh(cntr0) t c(cntr0) t wl(cntr0) cntr0 input v cc = 5 v t wh(tcin) t c(tcin) t wl(tcin) tcin input v cc = 5 v
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 32 of 38 rej03b0124-0140 i = 0 or 1 figure 5.7 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the int0 input filter select bit, use an int0 input high width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the int0 input filter select bit, use an int0 input low width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. figure 5.8 external interrupt int0 input timing diagram when v cc = 5 v table 5.17 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.18 external interrupt int0 input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 250 (1) ? ns t w(inl) int0 input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 5 v t w(inl) t w(inh) int0 input v cc = 5 v
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 33 of 38 rej03b0124-0140 note: 1. v cc = 2.7 to 3.3 v at t opr = -20 to 85 c / -40 to 85 c, f(xin) = 10 mhz, unless otherwise specified. table 5.19 electrical characteristics (3) [v cc = 3v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except x out i oh = -1 ma v cc ? 0.5 ? v cc v x out drive capacity high i oh = -0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = -50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except p1_0 to p1_3, x out i ol = 1ma ?? 0.5 v p1_0 to p1_3 drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v x out drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , cntr0, cntr1, tcin, rxd0 0.2 ? 0.8 v reset 0.2 ? 1.8 v i ih input ?h? current vi = 3 v ?? 4.0 a i il input ?l? current vi = 0 v ?? -4.0 a r pullup pull-up resistance vi = 0 v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? f ring-s low-speed on-chip oscillator frequency 40 125 250 khz v ram ram hold voltage during stop mode 2.0 ?? v
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 34 of 38 rej03b0124-0140 table 5.20 electrical characteristics (4) [vcc = 3v] (topr = -40 to 85 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss , comparator is stopped high-speed mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 813ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 712ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5 ? ma medium- speed mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 3 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.6 ? ma high-speed on-chip oscillator mode main clock off high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz no division ? 3.5 7.5 ma main clock off high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 fmr47 = 1 ? 100 280 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = 0 ? 37 74 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = 0 ? 35 70 a stop mode main clock off, topr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = 0 ? 0.7 3.0 a
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 35 of 38 rej03b0124-0140 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at ta = 25 c) [v cc = 3 v] figure 5.9 xin input timing diagram when v cc = 3 v figure 5.10 cntr0 input, cntr1 input, int1 input timing diagram when v cc = 3 v notes: 1. when using the timer c input capture mode, adjust the cycle time to (1/timer c count source frequency 3) or above. 2. when using the timer c input capture mode, adjust the wi dth to (1/timer c count source frequency 1.5) or above. figure 5.11 tcin input, int3 input timing diagram when v cc = 3 v table 5.21 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns table 5.22 cntr0 input, cntr1 input, int1 input symbol parameter standard unit min. max. t c(cntr0) cntr0 input cycle time 300 ? ns t wh(cntr0) cntr0 input ?h? width 120 ? ns t wl(cntr0) cntr0 input ?l? width 120 ? ns table 5.23 tcin input, int3 input symbol parameter standard unit min. max. t c(tcin) tcin input cycle time 1,200 (1) ? ns t wh(tcin) tcin input ?h? width 600 (2) ? ns t wl(tcin) tcin input ?l? width 600 (2) ? ns x in input t wh(xin) t c(xin) t wl(xin) v cc = 3 v cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 3 v tcin input t wh(tcin) t c(tcin) t wl(tcin) v cc = 3 v
r8c/18 group, r8c/19 group 5. electrical characteristics rev.1.40 apr 14, 2006 page 36 of 38 rej03b0124-0140 i = 0 or 1 figure 5.12 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the int0 input filter select bit, use an int0 input high width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the int0 input filter select bit, use an int0 input low width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. figure 5.13 external interrupt int0 input timing diagram when v cc = 3 v table 5.24 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.25 external interrupt int0 input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 380 (1) ? ns t w(inl) int0 input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v inti input t w(inl) t w(inh) v cc = 3 v
rev.1.40 apr 14, 2006 page 37 of 38 rej03b0124-0140 r8c/18 group, r8c/19 group package dimensions package dimensions y index mark 1 10 11 20 f * 1 * 3 * 2 c b p e a d e h e include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. detail f a 1 a 2 l 0.32 0.22 0.17 b p previous code jeita package code renesas code plsp0020jb-a 20p2f-a mass[typ.] 0.1g p-lssop20-4.4x6.5-0.65 0.2 0.15 0.13 max nom min dimension in millimeters symbol reference 6.6 6.5 6.4 d 4.5 4.4 4.3 e 1.15 a 2 6.6 6.4 6.2 1.45 a 0.2 0.1 0 0.7 0.5 0.3 l 10 0 c 0.65 e 0.10 y h e a 1 0.53 0.77 2.028 1.528 4.5 a 1 b 3 15 e 1.778 c l 3.0 0.51 0.9 1.0 1.3 a e 6.15 6.3 6.45 d 18.8 19.0 19.2 reference symbol dimension in millimeters min nom max 0.22 0.27 0.34 p-sdip20-6.3x19-1.78 1.0g mass[typ.] 20p4b prdp0020ba-a renesas code jeita package code previous code b p 0.38 0.48 0.58 e 1 7.62 7.32 7.92 a 2 3.3 0 * 3 * 2 * 1 seating plane 20 11 10 1 c e 1 e a l a 2 a 1 b p b 3 e d include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2.
rev.1.40 apr 14, 2006 page 38 of 38 rej03b0124-0140 r8c/18 group, r8c/19 group package dimensions detail f a 1 a 2 a x 14 14 8 7 1 28 22 21 15 f 1 7 8 15 21 22 28 y e d b p l p d 2 e 1 previous code jeita package code renesas code pwqn0028ka- b 28pjw- b mass[typ.] 0.05g p-hwqfn28-5x5-0.50 0.7 0.6 0.5 0.25 0.2 0.15 max nom min dimension in millimeters symbol reference 5.1 5.0 4.9 d 5.1 5.0 4.9 e 0.75 a 2 0.8 a 0.05 0 0 2.0 e 1 l p 0.5 e 0.05 x a 1 b p y0.05 d 2 2.0 e
a - 1 revision history r8c/18 group, r8c/19 group datasheet rev. date description page summary 0.10 nov 15, 2004 ?
a - 2 revision history r8c/18 group, r8c/19 group datasheet 1.20 nov 01, 2005 16 table 4.1 sfr information(1); 0009h: ?xxxxxx00b? ?
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