ordering number : en4900a 63095 th (ot) no. 4900-1/9 overview the lc89971 and LC89971M are ccd delay lines for multi television systems. they incorporate a comb filter for chrominance signal and a 1h delay line for luminance signal. structure nmos + ccd functions two ccd shift registers (for chrominance and luminance signals) ccd drive circuits ccd stage count switching circuit ccd signal adder auto-bias circuit sync tip clamping circuit (luminance signal) center-bias circuit (chrominance signal) sample-and-hold circuit pll 4 frequency multiplier fsc clock output circuit rd voltage generator features 5 v single-voltage power supply built-in pll 4 frequency multiplier circuit allows 4 fsc operation from an fsc (3.58 mhz) input. control pin switchable to handle ntsc/m, pal/gbi and pal/m systems. built-in chrominance signal crosstalk exclusion comb filter features high precision comb characteristics in an adjustment-free circuit. built-in peripheral circuits allow applications to be constructed with a minimum number of external components. positive-phase signal input/positive-phase signal output (luminance signal) package dimensions unit: mm 3059-dip22s (375 mil) unit: mm 3045b-mfp24 sanyo: dip22s [lc89971] sanyo: mfp24 [LC89971M] lc89971, 89971m sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan multi-system ccd delay line mos ic specifications absolute maximum ratings at ta = 25? parameter symbol conditions ratings unit maximum supply voltage v dd max ?.3 to +6.0 v allowable power dissipation pd max lc89971 1200 mw LC89971M 600 mw operating temperature topr ?0 to +70 ? storage temperature tstg ?5 to +150 ?
allowable operating ranges at ta = 25 c electrical characteristics at v dd = 5.0 v, ta = 25 c, f clk = 3.579545 mhz, v clk = 500 mvp-p no. 4900- 2 /9 lc89971, 89971m continued on next page. parameter symbol switch states conditions min typ max unit sw1 sw2 sw3 sw4 i dd-1 a a a b supply current i dd-2 a b a b 1 45 55 65 ma i dd-3 b b a b chrominance system characteristics (with no y-in input) v inc-1 a a a b pin voltage (input) v inc-2 a b a b 2.0 2.4 2.8 v v inc-3 b b a b 2 v ouyc-1 a a a b pin voltage (output) v outc-2 a b a b 1.2 1.6 2.0 v v outc-3 b b a b g vc-1 a a a b voltage gain g vc-2 a b a b 3 ? 0 +2 db g vc-3 b b a b c d-1 a a a b comb depth c d-2 a b a b 4 ?0 ?5 db c d-3 b b a b l nc-1 a a a b linearity l nc-2 a b a b 5 ?.3 0.0 +0.3 db l nc-3 b b a b l ck4c-1 a a a b clock leakage (4 fsc) l ck4c-2 a b a b 10 50 mvrms l ck4c-3 b b a b 6 l ck1c-1 a a a b clock leakage (fsc) l ck1c-2 a b a b 0.8 1.5 mvrms l ck1c-3 b b a b n c-1 a a a b noise n c-2 a b a b 7 0.5 2.0 mvrms n c-3 b b a b z oc-1 a a a a, b output impedance z oc-2 a b a a, b 8 200 350 500 z oc-3 b b a a, b t dc-1 a a a b 0 h delay time t dc-2 a b a b 9 230 ns t dc-3 b b a b parameter symbol conditions min typ max unit supply voltage v dd 4.75 5.00 5.25 v clock input amplitude v clk 300 500 1000 mvp-p clock frequency f clk sine wave 3.579545 mhz clock signal input amplitude v in-c 350 500 mvp-p luminance signal input amplitude v in-y 400 572 mvp-p
continued from preceding page. test conditions 1. supply current with no signal input. 2. c-out voltage (center bias voltage) with no signal input. 3. measure the c-out output with 350 mvp-p sine wave signals input to c-in1 and c-in2. gvc = 20 log [db] test frequencies gvc-1 4.431395 mhz (pal/gbi) gvc-2 3.571628 mhz (pal/m) gvc-3 3.571628 mhz (ntsc/m) c-out output [mvp-p] 350 [mvp-p] no. 4900- 3 /9 lc89971, 89971m parameter symbol switch states conditions min typ max unit sw1 sw2 sw3 sw4 luminance system characteristics (with no c-in1 or c-in2 input) v iny-1 a a a b pin voltage (input) v iny-2 a b a b 1.7 2.1 2.5 v v iny-3 b b a b 10 v outy-1 a a a b pin voltage (output) v outy-2 a b a b 0.8 1.2 1.6 v v outy-3 b b a b g vy-1 a a a b voltage gain g vy-2 a b a b 11 ? 0 +2 db g vy-3 b b a b g fy-1 a a b b frequency responce g fy-2 a b b b 12 ? 0 +2 db g fy-3 b b b b d gy-1 a a a b differential gain d gy-2 a b a b 0 5 7 % d gy-3 b b a b 13 d py-1 a a a b differential phase d py-2 a b a b 0 5 7 deg d py-3 b b a b l sy-1 a a a b linearity l sy-2 a b a b 14 37 40 43 % l sy-3 b b a b l ck4y-1 a a a b clock leakage (4 fsc) l ck4y-2 a b a b 10 50 mvrms l ck4y-3 b b a b 15 l ck1y-1 a a a b clock leakage (fsc) l ck1y-2 a b a b 0.8 1.5 mvrms l ck1y-3 b b a b n y-1 a a a b noise n y-2 a b a b 16 0.5 2.0 mvrms n y-3 b b a b z oy-1 a a a c, b output impedance z oy-2 a b a c, b 17 250 400 550 z oy-3 b b a c, b t dy-1 a a a b 63.88 delay time t dy-2 a b a b 18 63.46 s t dy-3 b b a b 63.46
4. measure the comb depth from the c-out output with a 350 mvp-p sine wave signal of frequency fa input to c-in1 and c-in2 and with a frequency of fb input. cd = 20 log [db] test frequencies fa fb cd-1 4.431395 mhz 4.435303 mhz (pal/gbi) cd-2 3.571628 mhz 3.575561 mhz (pal/m) cd-3 3.571628 mhz 3.575561 mhz (ntsc/m) 5. measure the c-out output with a 200 mvp-p sine wave signal input to c-in1 and c-in2 and with 500 mvp-p sine wave signal input and calculate the difference in the gains. lnc = 20 log [db] test frequencies lnc-1 4.431395 mhz (pal/gbi) lnc-2 3.571628 mhz (pal/m) lnc-3 3.571628 mhz (ntsc/m) 6. measure the 4 fsc (14.3 mhz) and fsc (3.58 mhz) components in the c-out output with no input. 7. measure the noise in the c-out output with no input. measure the noise with a noise meter set up with a 200 khz high-pass filter and a 5 mhz low-pass filter. 8. let v1 be the c-out output with a 350 mvp-p sine wave input to c-in1 and c-in2 and sw3 set to a, and let v2 be the c-out output with sw3 set to b. zoc = 500 [ ] test frequencies zoc-1 4.431395 mhz (pal/gbi) zoc-2 3.571628 mhz (pal/m) zoc-3 3.571628 mhz (ntsc/m) 9. the c-out output delay time with respect to inputs to c-in1. (the ccd 2.5 bit delay) 10. y-out voltage (clamp voltage) with no signal input. 11. measure the y-out output with a 200 khz 400 mvp-p sine wave input to y-in. gvy = 20 log [db] 12. measure the y-out output with a 200 khz 200 mvp-p sine wave input to y-in and with a 3.3 mhz 200 mvp-p sine wave input. gfy = 20 log [db] note that v bias should be adjusted so that the circuit is biased to the clamp level plus 250 mv. y-out output with a 3.5 mhz input [mvp-p] y-out output with a 200 khz input [mvp-p] y-out output [mvp-p] 400 [mvp-p] v2 [mvp-p] ?v1 [mvp-p] v1 [mvp-p] output for a 200 mvp-p input [mvp-p] 200 [mvp-p] output for a 500 mvp-p input [mvp-p] 500 [mvp-p] c-out output with fb input [mvp-p] c-out output with fa input [mvp-p] no. 4900- 4 /9 lc89971, 89971m
13. input a five-level step waveform (see the figure below) to y-in and measure the differential gain and differential phase in the y-out output with a vector scope. 14. input a five-level step waveform (see the figure below) to y-in and measure the luminance level (y) and the sync level (s) in the y-out output. ls = 100 [%] 15. measure the 4 fsc (14.3 mhz) and fsc (3.58 mhz) components in the y-out output with no input. 16. measure the noise in the y-out output with no input. measure the noise with a noise meter set up with a 200 khz high-pass filter, a 4.2 mhz low-pass filter, and a 3.58 mhz trap filter. 17. let v1 be the y-out output with a 200 khz 400 mvp-p sine wave input and sw4 set to c, and let v2 be the c-out output with sw4 set to b. zoy = 500 [ ] 18. the y-out delay time with respect to y-in v2 [mvp-p] ?v1 [mvp-p] v1 [mvp-p] s [mv] y [mv] no. 4900- 5 /9 lc89971, 89971m
pin assignment [lc89971] pin assignment [LC89971M] no. 4900- 6 /9 lc89971, 89971m
block diagram control pin function switching voltage levels note: since the control pin has a built-in pull-down resistor ( 70 k ), the pin will be set to the low state if left open. fsc out pin function this pin provides a buffer output for the clock signal input to the clk pin. note: since this pin has a built-in pull-up resistor, the pin voltage will go to the supply voltage and output will cease if left ope n. no. 4900- 7 /9 lc89971, 89971m cont1 cont2 mode (representative example) chrominance signal delay luminance signal delay (ccd bits) (ccd bits) low low pal/gbi 2 h (1834.5) + 0 h (2.5) 1 h (914) low high pal/m 2 h (1822.5) + 0 h (2.5) 1 h (908) high low high high ntsc/m 1 h (912.5) + 0 h (2.5) 1 h (908) low/high symbol min typ max unit low v l ?.3 0.0 0.5 v high v h 2.0 5.0 6.0 v
test circuit [lc89971] test circuit [LC89971M] no. 4900- 8 /9 lc89971, 89971m
ps no. 4900- 9 /9 lc89971, 89971m this catalog provides information as of june, 1995. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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