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clock generator for intel ? grantsdale chipset cy28439-2 rev 1.0, november 21, 2006 page 1 of 21 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? compliant to intel ? ck410 ? supports intel prescott and tejas cpu ? selectable cpu frequencies ? differential cpu clock pairs ? 100 mhz differential src clocks (two selectable between fixed and overclocking) ? 96 mhz differential dot clock ? 48 mhz usb clocks ? 33 mhz pci clock ? dial-a-frequency ? ?watchdog ? two independent overclocking plls ? low-voltage frequency select input ?i 2 c support with readback capabilities ? ideal lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 3.3v power supply ? 56-pin ssop and tssop packages cpu src pci ref dot96 usb 24-48m x 2 x 6 x 9 x 2 x 1 x 1 x 1 block diagram pin configuration cy28439-2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pci3 vss_pci *fs_e/pci4 pci5 vss_pci vdd_pci pcif0 *fs_b/pcif2 **fs_a/pcif1 **sel24_48#/24_48m usb48 vss_48 dot96t dot96c vttpwrgd#/pd srct0 srcc0 vdd_src vss_src srct1 srcc1 srct2 srcc2 vss_src srct_satat srcc_satac vdd_src vdd_48 pci2 vdd_pci pci1 pci0 sreset# ref0/fs_c** ref1/fs_d** xin vss_ref vdd_ref sclk sdata cput0 cpuc0 vdd_cpu cput1 cpuc1 vss_cpu iref vssa vdda vdd_src srct4 srcc4 srct3 srcc3 vss_src xout vdd_re f vdd_cpu vdd_src vttpwr_gd#/pd pll reference vdd_src fs_[e:a] pll2 src pll1 cpu vdd_48mhz pll3 sata divider divider pll4 fixed divider divider iref re f cput cpuc srct (pci ex) srcc (pci ex) srct4_sata srcc4_sata dot96t dot96c watchdog timer sreset# i2c logic sdata sclk 14.318mhz crystal xin xout vdd_48 usb48 vdd_pci pci vdd_pci pcif vdd_48 24/48 * indicates internal pull-up ** indicates internal pull-down
cy28439-2 rev 1.0, november 21, 2006 page 2 of 21 pin description pin no. name type description 6,56 vdd_pci pwr 3.3v power supply for outputs . 1,5 vss_pci gnd ground for outputs . 3 fs_e/pci4 i,o, pu,se 3.3v-tolerant input for cpu frequency selection/33-mhz clock . refer to dc electrical specifications t able for vil_fs and vih_fs specifications. 2,4,53,54, 55 pci o, se 33 mhz clocks . 7pcif0 o,se 33 mhz free-running clock 8 fs_a/pcif1 i/o,pd, se 3.3v-tolerant input for cpu frequency selection/free-running 33-mhz clock . refer to dc electrical specifications t able for vil_fs and vih_fs specifications. 9 fs_b/pcif2 i/o, pu, se 3.3v-tolerant input for cpu frequency selection/free-running 33-mhz clock . refer to dc electrical specifications t able for vil_fs and vih_fs specifications . 16 vtt_pwrgd#/pd i, pd 3.3v lvttl input . this pin is a level sensitive strobe used to latch the fs_a, fs_b, fs_c,fs_d, fs_e, sel24_48. after vtt_pwrg d# (active low) assertion, this pin becomes a real-time input for asserting power-down (active high). 10 vdd_48 pwr 3.3v power supply for outputs . 11 sel24_48#/24_48 m i/o, pd, se latched select inpu t for 24-/48-mh z output/ 24-/48-mhz output 0 = 48 mhz, 1 = 24 mhz 12 usb48 i/o, 48 mhz clock output. 13 vss_48 gnd ground for outputs . 14,15 dot96t, dot96c o, dif fixed 96 mhz clock output . 17,18,21, 22,23,24, 30,31,32, 33 srct/c o, dif differential serial reference clocks . outputs have overclocking capability. 19,28,34 vdd_src pwr 3.3v power supply for outputs . 26,27 srct/c_satat/c o, dif differential serial reference clock . recommended output for sata. 20,25,29 vss_src gnd ground for outputs . 35 vdda pwr 3.3v power supply for pll . 36 vssa gnd ground for pll . 37 iref i a precision resistor is attached to this pin , which is connected to the internal current reference. 41 vdd_cpu pwr 3.3v power supply for outputs . 39,40,42,43 cput/c o, dif differential cpu clock outputs . 38 vss_cpu gnd ground for outputs . 45 sclk i smbus-compatible sclock . 44 sdata i/o smbus-compatible sdata . 46 vdd_ref pwr 3.3v power supply for outputs . 47 xout o, se 14.318 mhz crystal output . 48 xin i 14.318 mhz crystal input . 49 vss_ref gnd ground for outputs . 50 ref0/fs_c i/o, se, pd 3.3v-tolerant input for cpu frequency selection / reference clock . selects test mode if pulled to v ihfs_c when vtt_pwrgd# is asserted low. refer to dc electrical specificatio ns table for vilfs_ c,vimfs_c,vihfs_c specifications. 51 ref1/fs_d o, se, pd 3.3v-tolerant input for cpu frequency selection / reference clock . refer to dc electrical specifications t able for vil_fs and vih_fs specifications . 52 sreset# o, se 3.3v output for watchdog reset. this output is open drain type with a high (>100-k ) internal pull-up resistor.
cy28439-2 rev 1.0, november 21, 2006 page 3 of 21 frequency select pins (fs_[a:e]) host clock frequency selection is achieved by applying the appropriate logic levels to fs_a, fs_b, fs_c, fs_d, and fs_e inputs prior to vtt_pwrgd# assertion (as seen by the clock synthesizer). upon vtt_pwrgd# being sampled low by the clock chip (indicating processor vtt voltage is stable), the clock chip samples the fs_a, fs_b, fs_c, fs_d, and fs_e input values. for all logic levels of fs_a, fs_b, fs_c, fs_d, and fs_e, vtt_pwrgd# employs a one-shot functionality in that once a valid low on vtt_pwrgd# has been sampled, all further vtt_pwrgd#, fs_a, fs_b, fs_c, fs_d, and fs_e transitions will be ignored, except in test mode. fs_c is a three level input, when sampled at a voltage greater than 2.1v by vttpwrgd#, the device will enter test mode as selected by the voltage level on the fs_b input. serial data interface to enhance the flexibility and functi on of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initialize to their default sett ing upon power-up, and therefore use of this interface is optiona l. clock device register changes are normally made upon system initialization, if any are required. the interface ca nnot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read opera tions from the controller. for block write/read operation, t he bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines the corresponding byte write and byte read protocol. the slave rece iver address is 11010010 (d2h). figure 1. cpu and src frequency select tables fs_d fs_c fs_b fs_a cpu src cpu pll gear constant s cpu m divider cpu n default cpu n allowable range for da f src pll gear constants src m divider (not changeable b y user ) src n default src n allowable range for da f fsel_3 fsel_2 fsel_1 fsel_0 (mhz) (mhz) (g) 0 1 0 1 100 100 30 60 200 200 - 250 30 60 200 200 - 266 0 0 0 1 133.3333333 100 40 60 200 200 - 250 30 60 200 200 - 266 0 0 1 1 166.6666667 100 60 63 175 175 - 26 2 30 60 200 200 - 266 0 0 1 0 200 100 60 60 200 200 - 250 30 60 200 200 - 266 0 0 0 0 266.6666667 100 80 60 200 200 - 250 30 60 200 200 - 266 0 1 0 0 333.3333333 100 120 63 175 175 - 26 2 30 60 200 200 - 266 0 1 1 0 400 100 120 60 200 200 - 250 30 60 200 200 - 266 1 1 0 1 100.952381 100 30 63 212 212 - 26 2 30 60 200 200 - 266 1 0 0 1 133.968254 100 40 63 211 211 - 26 2 30 60 200 200 - 266 1 0 1 1 167 100 60 60 167 167 - 250 30 60 200 200 - 266 1 0 1 0 200.952381 100 60 63 211 211 - 26 2 30 60 200 200 - 266 1 0 0 0 266.6666667 100 80 60 200 200 - 250 30 60 200 200 - 266 1 1 0 0 334 100 120 60 167 167 - 250 30 60 200 167 - 266 1 1 1 0 400.6451613 100 120 6 2 207 207 - 25 8 30 60 200 167 - 266 x high low x tristate tristate tristate tristate tristate tristate x high high x ref/n ref/n ref/n ref/n ref/n ref/n input conditions output frequency
cy28439-2 rev 1.0, november 21, 2006 page 4 of 21 table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. for bl ock read or block write operations , these bits should be '0000000 ' table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits (skip this step if i 2 c_en bit set) 20 repeat start 28 acknowledge from slave 27:21 slave address ? 7 bits 36:29 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave ? 8 bits 38 not acknowledge 39 stop
cy28439-2 rev 1.0, november 21, 2006 page 5 of 21 control registers byte 0: control register 0 bit @pup name description 7 1 reserved reserved 6 1 src[t/c]4 src[t/ c]4 output enable 0 = disable (tri-state), 1 = enable 5 1 src[t/c]3 src[t/ c]3 output enable 0 = disable (tri-state), 1 = enable 4 1 sata[t/c] sata[t/c] output enable 0 = disable (tri-state), 1 = enable 3 1 src[t/c]2 src[t/ c]2 output enable 0 = disable (tri-state), 1 = enable 2 1 src[t/c]1 src[t/ c]1 output enable 0 = disable (tri-state), 1 = enable 1 1 reserved reserved 0 1 src[t/c]0 src[t/ c]0 output enable 0 = disable (tri-state), 1 = enable byte 1: control register 1 bit @pup name description 7 1 pcif0 pcif0 output enable 0 = disabled, 1 = enabled 6 1 dot_96[t/c] dot_96 mhz output enable 0 = disable (tri-state), 1 = enabled 5 1 24_48m 24_48 mhz output enable 0 = disabled, 1 = enabled 4 1 ref0 ref0 output enable 0 = disabled, 1 = enabled 3 0 reserved reserved 2 1 cpu[t/c]1 cpu[t/ c]1 output enable 0 = disable (tri-state), 1 = enabled 1 1 cpu[t/c]0 cpu[t/c]0 output enable 0 = disable (tri-state), 1 = enabled 0 1 cpu pll1 (cpu pll) spread spectrum enable 0 = spread off, 1 = spread on byte 2: control register 2 bit @pup name description 7 1 pci5 pci5 output enable 0 = disabled, 1 = enabled 6 1 pci4 pci4 output enable 0 = disabled, 1 = enabled 5 1 pci3 pci3 output enable 0 = disabled, 1 = enabled 4 1 pci2 pci2 output enable 0 = disabled, 1 = enabled 3 1 pci1 pci1 output enable 0 = disabled, 1 = enabled 2 1 pci0 pci0 output enable 0 = disabled, 1 = enabled 1 1 pcif2 pcif2 output enable 0 = disabled, 1 = enabled
cy28439-2 rev 1.0, november 21, 2006 page 6 of 21 0 1 pcif1 pcif1 output enable 0 = disabled, 1 = enabled byte 3: control register 3 bit @pup name description 7 0 reserved reserved, set = 0 6 0 src4 allow control of src[t/c] 4 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 5 0 src3 allow control of src[t/c] 3 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 4 0 sata[t/c] allow control of sata[t /c] with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 3 0 src2 allow control of src[t/c] 2 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 0 src1 allow control of src[t/c] 1 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 1 0 reserved reserved 0 0 src0 allow control of src[t/c] 0 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# byte 4: control register 4 bit @pup name description 7 hw fs_e fs_e reflects the value of the fs_e pin sampled on power-up. 0 = fs_e was low during vtt_pwrgd# assertion. 6 0 dot96[t/c] dot_pwrdwn drive mode 0 = driven in pwrdwn, 1 = tri-state 5 0 pcif2 allow control of src[t/c] 2 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 4 0 pcif1 allow control of pcif1 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 3 0 pcif0 allow control of pcif0 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 1 reserved reserved, set = 1 1 1 reserved reserved, set = 1 0 1 reserved reserved, set = 1 byte 5: control register 5 bit @pup name description 7 0 src[t/c] src[t/ c] stop drive mode 0 = driven when pci_stp# asserted,1 = tri-state when pci_stp# asserted 6 0 reserved reserved, set = 0 5 0 reserved reserved, set = 0 4 0 reserved reserved, set = 0 3 0 src[t/c][4:0] src[t/ c] pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted 2 0 reserved reserved, set = 0 1 0 cpu[t/c]1 cpu[t/c]1 pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted 0 0 cpu[t/c]0 cpu[t/c]0 pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted byte 2: control register 2 (continued) bit @pup name description
cy28439-2 rev 1.0, november 21, 2006 page 7 of 21 byte 6: control register 6 bit @pup name description 7 0 test_sel ref/n or tri-state select 0 = tri-state, 1 = ref/n clock 6 0 test_mode test clock mode entry control 0 = normal operation, 1 = ref/n or tri-state mode 5 hw fs_d fs_d reflects the value of the fs_d pin sampled on power-up. 0 = fs_d was low during vtt_pwrgd# assertion 4 1 ref ref output drive strength 0 = high, 1 = low 3 1 pci, pcif and src clock outputs except those set to free running sw pci_stp# function 0=sw pci_stp# as sert, 1= sw pc i_stp# deassert when this bit is set to 0, all stoppable pci, pcif and src outputs will be stopped in a synchronous manner with no short pulses. when this bit is set to 1, all stopped pci, pcif and src outputs will resume in a synchronous manner with no short pulses. 2 hw fs_c fs_c reflects the value of the fs_c pin sampled on power-up 0 = fs_c was low during vtt_pwrgd# assertion 1 hw fs_b fs_b reflects the value of the fs_b pin sampled on power-up 0 = fs_b was low during vtt_pwrgd# assertion 0 hw fs_a fs_a reflects the value of the fs_a pin sampled on power-up 0 = fs_a was low during vtt_pwrgd# assertion byte 7: vendor id bit @pup name description 7 0 revision code bit 3 revision code bit 3 6 0 revision code bit 2 revision code bit 2 5 0 revision code bit 1 revision code bit 1 4 0 revision code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 byte 8: control register 8 bit @pup name description 7 0 cpu_ss spread selection for cpu pll 0: ?0.5% (peak to peak) 1: ?1.0% (peak to peak) 6 0 cpu_dwn_ss spread selection for cpu pll 0: down spread. 1: center spread 5 0 src_ss_off src spread spectrum enable 0 = spread off, 1 = spread on 4 0 src_ss spread selection for src pll 0: ?0.5% (peak to peak) 1: ?1.0% (peak to peak) 3 0 reserved reserved, set = 0 2 1 usb usb 48-mhz output drive strength 0 = 2x, 1 = 1x 1 1 pci 33-mhz output drive strength 0 = 2x, 1 = 1x 0 0 reserved reserved
cy28439-2 rev 1.0, november 21, 2006 page 8 of 21 byte 9: control register 9 bit @pup name description 7 0 reserved reserved 60 50 40 3 0 fsel_d sw frequency selection bits. see figure 1 . 20 fsel_c 1 0 fsel_b 0 0 fsel_a byte 10: control register 10 bit @pup name description 7 0 recovery_frequency this bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: use hw settings 1: recovery n[8:0] 6 0 timer_sel timer_sel selects the wd reset function at sreset pin when wd time out. 0 = reset and reload recovery_frequency 1 = only reset 5 1 time_scale time_scale allows selection of wd time scale 0 = 294 ms 1 = 2.34 s 4 0 wd_alarm wd_alarm is set to ?1? when the watchdog times out. it is reset to ?0? when the system clears the wd_timer time stamp. 3 0 wd_timer2 watchdog time r time stamp selection 000: reserved (test mode) 001: 1 * time_scale 010: 2 * time_scale 011: 3 * time_scale 100: 4 * time_scale 101: 5 * time_scale 110: 6 * time_scale 111: 7 * time_scale 20 wd_timer1 10 wd_timer0 0 0 wd_en watchdog timer enable, when the bit is asserted, watchdog timer is triggered and time stamp of wd_timer is loaded 0 = disable, 1 = enable byte 11: control register 11 bit @pup name description 7 0 cpu_daf_n7 if prog_cpu_en is set, the va lues programmed in cpu_daf_n[8:0] and cpu_daf_m[6:0] will be used to de termine the cpu output frequency. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[e:a] register will be us ed. when it is set, the frequency ratio stated in the fsel[3:0] register will be used. 6 0 cpu_daf_n6 5 0 cpu_daf_n5 4 0 cpu_daf_n4 3 0 cpu_daf_n3 2 0 cpu_daf_n2 1 0 cpu_daf_n1 0 0 cpu_daf_n0
cy28439-2 rev 1.0, november 21, 2006 page 9 of 21 byte 12: control register 12 bit @pup name description 7 0 cpu_daf_n8 if prog_cpu_en is set, the values programmed is in cpu_fsel_n[8:0] and cpu_fsel_m[6:0] will be used to determine the cpu output frequency. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[e:a] register will be us ed. when it is set, the frequency ratio stated in the fsel[3:0] register will be used. 6 0 cpu_daf_m6 5 0 cpu_daf_m5 4 0 cpu_daf_m4 3 0 cpu_daf_m3 2 0 cpu_daf_m2 1 0 cpu_daf_m1 0 0 cpu_daf_m0 byte 13: control register 13 bit @pup name description 7 0 src_n7 src dial-a-frequency bit n7 6 0 src_n6 src dial-a-frequency bit n6 5 0 src_n5 src dial-a-frequency bit n5 4 0 src_n4 src dial-a-frequency bit n4 3 0 src_n3 src dial-a-frequency bit n3 2 0 src_n2 src dial-a-frequency bit n2 1 0 src_n1 src dial-a-frequency bit n1 0 0 src_n0 src dial-a-frequency bit n0 byte 14: control register 14 bit @pup name description 7 0 src_n8 src dial-a-frequency bit n8 6 0 sw_reset software reset. when set the device will asse rt a reset signal on sreset# upon completion of the block/word/byte wr ite that set it. after asserting and deasserting the sreset# this bit will self clear (set to 0). the sreset# pin must be enabled by latching sreset#_en on vtt_prwgd# to utilize this feature. 5 0 fs_[e:a] fs_override 0 = select operating frequency by fs(e:a) input pins 1 = select operating frequency by fsel_(4:0) settings 4 0 smsw_sel smooth switch select 0: select cpu_pll 1: select src_pll. 3 0 reserved reserved, set = 0 2 0 reserved reserved, set = 0 1 1 pcif free running 33-mhz output drive strength 0 = 2x, 1 = 1x 0 0 recovery_n8 watchdog recovery bit byte 15: control register 15 bit @pup name description 7 0 recovery n7 watchdog recovery bit 6 0 recovery n6 watchdog recovery bit 5 0 recovery n5 watchdog recovery bit 4 0 recovery n4 watchdog recovery bit 3 0 recovery n3 watchdog recovery bit
cy28439-2 rev 1.0, november 21, 2006 page 10 of 21 the cy28439-2 requires a parallel resonance crystal. substituting a series resonance crystal will cause the cy28439-2 to operate at the wrong frequency and violate the ppm specification. for most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. crystal loading crystal loading plays a critical role in achieving low ppm perfor- mance. to realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (cl). figure 2 shows a typical crystal configuration using the two trim capacitors. an important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. it?s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. this is not true. 2 0 recovery n2 watchdog recovery bit 1 0 recovery n1 watchdog recovery bit 0 0 recovery n0 watchdog recovery bit byte 16: control register 16 bit @pup name description 7 1 ref1 ref1 output enable 0 = disable, 1 = enable 6 1 usb48 usb48 output enable 0 = disable, 1 = enable 5 0 src_freq_sel src frequency selection 0: src frequency is selected via the fs_e pin 1: src frequency is initially set to 167 mhz. 4 0 reserved reserved 3 0 src_sata sata pll spread spectrum enable 0 = spread off, 1 = spread on 2 0 prog_src_en programmable src frequency enable 0 = disabled, 1 = enabled. 1 0 prog_cpu_en programmable cpu frequency enable 0 = disabled, 1 = enabled. 0 0 watchdog autorecovery watchdog autorecovery mode 0 = disable (manual), 1= enable (auto) byte 15: control register 15 (continued) bit @pup name description figure 2. crystal capacitive clarification table 4. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) motional (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 20 pf 0.1 mw 5 pf 0.016 pf 35 ppm 30 ppm 5 ppm
cy28439-2 rev 1.0, november 21, 2006 page 11 of 21 calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on both sides. use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ................................................... crystal load capacitance cle ............. .............. ..............actual loading seen by crystal using standard value trim capacitors ce .....................................................external trim capacitors cs ............................................. stray capacitance (terraced) ci .......................................................... internal capacitance (lead frame, bond wires etc.) cl ................................................... crystal load capacitance cle ............. .............. ..............actual loading seen by crystal using standard value trim capacitors ce .....................................................external trim capacitors cs ............................................. stray capacitance (terraced) ci .......................................................... internal capacitance (lead frame, bond wires etc.) dial-a-frequency (cpu and src) this feature allows the user to overclock their system by slowly stepping up the cpu or src frequency. when the program- mable output frequency feature is enabled, the cpu and src frequencies are determined by the following equation fcpu = g * n/m or fcpu=g2 * n, where g2 = g / m ?n? and ?m? are the values programmed in programmable frequency select n-value register and m-value register, respectively. ?g? stands for the pll gear constant, which is determined by the programmed value of fs[e:a]. see figure 1 for the gear constant for each frequency selection. the pci express only allows user control of the n register, the m value is fixed and documented in figure 1 . in this mode, the user writes the desired n and m value into the daf i2c registers. the us er cannot change only the m value and must change both the m and the n values at the same time, if they require a change to the m value. the user may change only the n value if required. associated register bits cpu_daf enable?this bit enables cpu daf mode. by default, it is not set. when set, the operating frequency is determined by the values ent ered into the cpu_daf_n register. note: the cpu_daf_n and m register must contain valid values before cpu_daf is set. default = 0, (no daf). cpu_daf_n?there will be nine bits (for 512 values) to linearly change the cpu frequency (limited by vco range). default = 0, (0000) the allowable values for n are detailed in the frequency select table in figure 1 . cpu daf m?there will be 7 bits (for 128 values) to linearly change the cpu frequency (limited by vco range). default = 0, the allowable values for m are detailed in the frequency select table in figure 1 . src_daf enable?this bit enables src daf mode. by default, it is not set. when set, the operating frequency is determined by the values ent ered into the src_daf_n register. note: the src_daf_n register must contain valid values before src_daf is set. default = 0, (no daf). src_daf_n?there are nine bits (for 512 values) to linearly change the cpu frequency (limited by vco range). default = 0, (0000) the allowable values for n are detailed in the frequency select table in figure 1 . recovery?the recovery mec hanism during cpu daf when the system locks up and the watchdog timer is enabled is determined by the ?watchdog recovery mode? and ?watchdog autorecovery enable? bits. the possible recovery methods are: (a) auto, (b) manual (by recovery n), (c) hw, and (d) no recovery, ju st send reset signal. there is no recovery mode for src dial-a-frequency. software frequency select this mode allows the user to select the cpu output frequencies using the software frequency select bits in the smbus register. fsel?there will be four bits (for 16 combinations) to select predetermined cpu frequencies from a table. the table selec- tions are detailed in section figure 1 . xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8pf trim 33pf pin 3 to 6p figure 3. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 () 1 = cle
cy28439-2 rev 1.0, november 21, 2006 page 12 of 21 fs_override?this bit allows the cpu frequency to be selected from hw or fsel sett ings. by default, this bit is not set and the cpu frequency is selected by hw. when this bit is set, the cpu frequency is selected by the fsel bits. default = 0. recovery?the recovery mechanism during fsel when the system locks up is determined by the ?watchdog recovery mode? and ?watchdog autorecovery enable? bits. the only possible recovery method is to (?) hardware settings. auto recovery or manual recovery can cause a wrong output frequency because the output divider may have changed with the selected cpu frequency and these recovery methods will not recover the original output divider setting. smooth switching the device contains one smooth sw itch circuit which is shared by the cpu pll and src pll. the smooth switch circuit ensures that when the ou tput frequency changes by overclocking, the transition fr om the old frequency to the new frequency is a slow, smooth transi tion containing no glitches. the rate of change of output frequency when using the smooth switch circuit is less than 1 mhz/0.667 s. the frequency overshoot and undershoot will be less than 2%. the smooth switch circuit can be assigned to either pll via register byte 14 bit 4. by default the smooth switch circuit is assigned to the cpu pll. either pll can still be overclocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. it is not recommended to enable overclocking and change the n values of both plls in the same smbus block write. watchdog timer the watchdog timer is used in the system in conjunction with overclocking. it is used to provid e a reset to a system that has hung up due to overclocking the cpu and the front side bus. the watchdog is enabled by the user and if the system completes its checkpoints, th e system will clear the timer. however, when the timer runs out, there will be a reset pulse generated on the sreset# pin for 20 ms that is used to reset the system. when the watchdog is enabled (wd_en = 1) the watchdog timer will start counting down from a value of watchdog_timer * time scale. if the watchdog timer reaches 0 before the wd_en bit is cleared then it will assert the sreset# signal and set the watchdog alarm bit to 1. to use the watchdog the sr eset# pin must be enabled by sreset_en pin being sampled low by vttpwrgd# assertion during system boot-up. at any point if during the watchdog timer countdown, if the time stamp or watchdog timer bits are changed the timer will reset and start counting down from the new value. after the reset pulse, the watchdog will stay inactive until either: 1. a new time stamp or watchdog timer value is loaded. 2. the wd_en bit is cleared and then set again. watchdog register bits the following register bits are associated with the watchdog timer: watchdog enable?this bit (by default) is not set, which disables the watchdog. when set, the watchdog is enabled. also, when there is a transition from low to high, the timer reloads. default = 0, disable watchdog timer?there will be three bits (for seven combina- tions) to select the timer value. default = 000?the value '000' is a reserved test mode. watchdog alarm?this bit is a flag and when it is set, it indicates that the timer has ex pired. this bit is not set by default. when the bit is set, the user is allowed to clear. default = 0. watchdog time scale?this bit selects the multiplier. when this bit is not set, the multiplier will be 250 ms. when set (by default), the mult iplier will be 3s. default = 1. watchdog reset mode?this selects the watchdog reset mode. when this bit is not set (by default), the watchdog will send a reset pulse and reload the recovery frequency, which depends on watchdog recovery mode setting. when set, it just sends a reset pulse. default = 0, reset & recover frequency. watchdog recovery mode?this bit selects the location to recover from. one option is to recover from the hw settings (already stored in smbus regi sters for readback capability) and the second is to recover from a register called ?recovery n?. default = 0 (recover from the hw setting). watchdog autorecovery enable?this bit by default is set and the recovered values are autom atically written into the ?watchdog recovery register? and reloaded by the watchdog function. when this bit is not set, the user is allowed to write to the ?watchdog recovery register?. the value stored in the ?watchdog recovery register? will be used for recovery. default = 1, autorecovery. watchdog recovery register?this is a nine-bit register to store the watchdog n recovery value. this value can be written by the autorecovery or user depending on the state of the ?watchdog autorecovery enable bit?. watchdog recovery modes there are two operating mo des that requires watchdog recovery. the modes are dial-a-frequency (daf) or frequency select. there are four different recovery modes: the following diagram lists the operating mode and the recovery mode associated with it. recover to hardware m,n, o when this recovery mode is se lected, in the event of a watchdog timeout, the original m, n, and o values that were latched by the hw fsel pins at chip boot-up should be reloaded. autorecovery when this recovery mode is se lected, in the event of a watchdog timeout, the m and n values stored in the recovery m and n registers should be reloaded. the current values of m and n will be latched into the internal recovery m and n registers by the wd_en bit being set.
cy28439-2 rev 1.0, november 21, 2006 page 13 of 21 manual recovery when this recovery mode is selected, in the event of a watchdog timeout, the n value as programmed by the user in the n recovery register, and the m value that is stored in the recovery m register (not accessible by the user) should be restored. the current m value should be latched into the m recovery register by the wd_en bit being set. no recovery if no recovery mode is select ed, in the event of a watchdog time out, the device should ju st assert the sreset# and keep the current values of m and n. software reset software reset is a reset function which is used to send out a pulse from sreset# pin. it is controlled by the sw_reset enable register bit. upon completion of the byte/word/block write in which the sw_reset bit was set, the device will send a reset pulse on the sreset# pin. the duration of the sreset# pulse should be the same as the duration of the sreset# pulse after a watchdog timer time out. after the sreset# pulse is asserted the sw_reset bit should be automatically cl eared by the device. pd (power-down) clarification the vtt_pwrgd# /pd pin is a dual-function pin. during initial power-up, the pin functions as vtt_pwrgd#. once vtt_pwrgd# has been sampled low by the clock chip, the pin assumes pd functionality. the pd pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. this signal is synchronized internal to the device prior to powering down the clock synthe- sizer. pd is also an asynchronous input for powering up the system. when pd is asserted high, all clocks need to be driven to a low value and held prior to turning off the vcos and the crystal oscillator. pd (power-down)?assertion when pd is sampled high by two consecutive rising edges of cpuc, all single-ended outputs will be held low on their next high-to-low transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# high-to-low transition within 4 clock periods. when the smbus pd drive mode bit corresponding to the differential (cpu, src, and dot) clock output of interest is programmed to ?0?, the clock output is held with ?diff clock? pin driven high at 2 x iref, and ?diff clock#? tri-state. if the control regist er pd drive mode bit corre- sponding to the output of inte rest is programmed to ?1?, then both the ?diff clock? and the ?diff clock#? are tri-state. note the example below shows cput = 133 mhz and pd drive mode = ?1? for all differential outputs. this diagram and description is applicable to valid cpu frequencies 100, 133, 166, 200, 266, 333, and 400 mhz. in the event that pd mode is desired as the initial power-on state, pd must be asserted high in less than 10 s after asserting vtt_pwrgd#. pd deassertion the power-up latency is less than 1.8 ms. this is the time from the deassertion of the pd pin or the ramping of the power supply until the time that stabl e clocks are output from the clock chip. all differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of pd deassertion to a voltage greater than 200 mv. after the clock chip?s internal pll is powered up and locked, all outputs will be enabled within a few clock cycles of each other. figure 5 is an example showing the relationship of clocks coming up. figure 4. power-down assertion timing waveform pd usb, 48mhz dot96t dot96c srct 100mhz srcc 100mhz cput, 133mhz pci, 33 mhz ref cpuc, 133mhz
cy28439-2 rev 1.0, november 21, 2006 page 14 of 21 figure 5. power-down deassertion timing waveform dot96c pd cpuc, 133mhz cput, 133mhz srcc 100mhz usb, 48mhz dot96t srct 100mhz tstable <1.8 ms pci, 33mhz ref tdrive_pwrdn# <300 ? , >200 mv fs_a, fs_b,fs_c vtt_pwrgd# pwrgd_vrm vdd clock gen clock state clock outputs clock vco 0.2-0.3 ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored figure 6. vtt_pwrg d# timing diagram vtt_pwrgd# = low delay >0.25 ms s1 power off s0 vdd_a = 2.0v sample inputs straps s2 normal operation wait for <1.8ms enable outputs s3 vtt_pwrgd# = toggle vdd_a = off figure 7. clock generator power-up/run state diagram
cy28439-2 rev 1.0, november 21, 2006 page 15 of 21 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-std-883e method 1012.1 ? 20 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description condition min. max. unit all v dd s 3.3v operating voltage 3.3 5% 3.135 3.465 v v ili2c input low voltage sdata, sclk ? 1.0 v v ihi2c input high voltage sdata, sclk 2.2 ? v v il_fs fs_[a:b,d:e] i nput low voltage v ss ? 0.3 0.35 v v ih_fs fs_[a:b,d:e] input high voltage 0.7 v dd + 0.5 v v ilfs_c fs_c low range 0 0.35 v v imfs_c fs_c mid range 0.7 1.7 v v ih fs_c fs_c high range 2.1 v dd v v il 3.3v input low voltage v ss ? 0.3 0.8 v v ih 3.3v input high voltage 2.0 v dd + 0.3 v i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 ? a i ih input high leakage current except in ternal pull-down resistors, 0 < v in < v dd ?5 a v ol 3.3v output low voltage i ol = 1 ma ? 0.4 v v oh 3.3v output high voltage i oh = ?1 ma 2.4 ? v i oz high-impedance output current ?10 10 a c in input pin capacitance 3 5 pf c out output pin capacitance 3 5 pf l in pin inductance ?7nh v xih xin high voltage 0.7v dd v dd v v xil xin low voltage 0 0.3v dd v i dd3.3v dynamic supply current at max. load and freq. per figure 10 ?500ma i pd3.3v power-down supply current pd asserted, outputs driven ? 70 ma i pt3.3v power-down supply current pd asserted, outputs tri-state ? 2 ma
cy28439-2 rev 1.0, november 21, 2006 page 16 of 21 ac electrical specifications parameter description c ondition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ? 10.0 ns t ccj xin cycle to cycle jitter as an average over 1- s duration ? 500 ps l acc long-term accuracy over 150 ms ? 300 ppm cpu at 0.7v (ssc refers to ?0.5% spread spectrum) t dc cput and cpuc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz cput and cpuc period measured at crossing point v ox 9.997001 10.00300 ns t period 133-mhz cput and cpuc period measured at crossing point v ox 7.497751 7.502251 ns t period 166-mhz cput and cpuc period measured at crossing point v ox 5.998201 6.001801 ns t period 200-mhz cput and cpuc period measured at crossing point v ox 4.998500 5.001500 ns t period 266-mhz cput and cpuc period measured at crossing point v ox 3.748875 3.751125 ns t period 333-mhz cput and cpuc period measured at crossing point v ox 2.999100 3.000900 ns t period 400-mhz cput and cpuc period measured at crossing point v ox 2.499250 2.500750 ns t periodss 100-mhz cput and cpuc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodss 133-mhz cput and cpuc period, ssc measured at crossing point v ox 7.497751 7.539950 ns t periodss 166-mhz cput and cpuc period, ssc measured at crossing point v ox 5.998201 6.031960 ns t periodss 200-mhz cput and cpuc period, ssc measured at crossing point v ox 4.998500 5.026634 ns t periodss 266-mhz cput and cpuc period, ssc measured at crossing point v ox 3.748875 3.769975 ns t periodss 333-mhz cput and cpuc period, ssc measured at crossing point v ox 2.999100 3.015980 ns t periodss 400-mhz cput and cpuc period, ssc measured at crossing point v ox 2.499250 2.513317 ns t periodabs 100-mhz cput and cpuc absolute period measured at crossing point v ox 9.912001 10.08800 ns t periodabs 133-mhz cput and cpuc absolute period measured at crossing point v ox 7.412751 7.587251 ns t periodabs 166-mhz cput and cpuc absolute period measured at crossing point v ox 5.913201 6.086801 ns t periodabs 200-mhz cput and cpuc absolute period measured at crossing point v ox 4.913500 5.086500 ns t periodabs 266-mhz cput and cpuc absolute period measured at crossing point v ox 3.663875 3.836125 ns t periodabs 333-mhz cput and cpuc absolute period measured at crossing point v ox 2.914100 3.085900 ns t periodabs 400-mhz cput and cpuc absolute period measured at crossing point v ox 2.414250 2.585750 ns t periodssabs 100-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 9.912001 10.13827 ns t periodssabs 133-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 7.412751 7.624950 ns t periodssabs 166-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 5.913201 6.116960 ns t periodssabs 200-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 4.913500 5.111634 ns t periodssabs 266-mhz cput and cpu c absolute period, ssc measured at crossing point v ox 3.663875 3.854975 ns t periodssabs 333-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 2.914100 3.100980 ns t periodssabs 400-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 2.414250 2.598317 ns t skew cpu0 to cpu1 measured at crossing point v ox ? 100 ps
cy28439-2 rev 1.0, november 21, 2006 page 17 of 21 t ccj cput/c cycle to cycle jitter m easured at crossing point v ox ?80ps l acc long term accuracy measured using frequency counter over 0.15 seconds. ? 300 ppm t r / t f cput and cpuc rise and fall times measured from v ol = 0.175 to v oh = 0.525v 130 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% t r rise time variation ? 125 ps t f fall time variation ? 125 ps v high voltage high math averages figure 10 660 850 mv v low voltage low math averages figure 10 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 10 . measure se ? 0.2 v src t dc srct and srcc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz srct and srcc period measured at crossing point v ox 9.997001 10.00300 ns t periodss 100-mhz srct and srcc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodabs 100-mhz srct and srcc absolute period measured at crossing point v ox 9.872001 10.12800 ns t periodssabs 100-mhz srct and srcc absolute period, ssc measured at crossing point v ox 9.872001 10.17827 ns t skew any srct/c to srct/c clock skew measured at crossing point v ox ? 250 ps t ccj srct/c cycle to cycle jitter m easured at crossing point v ox ?65ps l acc srct/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f srct and srcc rise and fall times measured from v ol = 0.175 to v oh = 0.525v 130 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% t r rise timevariation ? 125 ps t f fall time variation ? 125 ps v high voltage high math averages figure 10 660 850 mv v low voltage low math averages figure 10 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 10. measure se ? 0.2 v pci/pcif t dc pci duty cycle measurement at 1.5v 45 55 % t period spread disabled pcif/pci period measurement at 1.5v 29.99100 30.00900 ns t periodss spread enabled pcif/pci period, ssc measurement at 1.5v 29.9910 30.15980 ns t periodabs spread disabled pcif/pci period measurement at 1.5v 29.49100 30.50900 ns t periodssabs spread enabled pcif/pci period, ssc measurement at 1.5v 29.49100 30.65980 ns t high pcif and pci high time measurement at 2.4v 12.0 ? ns t low pcif and pci low time measurement at 0.4v 12.0 ? ns edge rate rising edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns edge rate falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns ac electrical specifications (continued) parameter description c ondition min. max. unit
cy28439-2 rev 1.0, november 21, 2006 page 18 of 21 t skew any pci clock to any pci clock skew measurement at 1.5v ? 500 ps t ccj pcif and pci cycle to cycle jitter measurement at 1.5v ? 500 ps dot t dc dot96t and dot96c duty cycle measured at crossing point v ox 45 55 % t period dot96t and dot96c period measured at crossing point v ox 10.41354 10.41979 ns t periodabs dot96t and dot96c absolute period measured at crossing point v ox 10.16354 10.66979 ns t ccj dot96t/c cycle to cycle jitter measured at crossing point v ox ? 250 ps l acc dot96t/c long term accuracy measured at crossing point v ox ? 100 ppm t ltj long term jitter measurement taken from cross point v ox @ 1 s ? 700 ps measurement taken from cross point v ox @ 10 s ? 700 ps t r / t f dot96t and dot96c rise and fall times measured from v ol = 0.175 to v oh = 0.525v 130 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% t r rise time variation ? 125 ps t f fall time variation ? 125 ps v high voltage high math averages figure 10 660 850 mv v low voltage low math averages figure 10 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 10. measure se ? 0.2 v usb48, 24_48m t dc usb duty cycle measurement at 1.5v 45 55 % t period usb period, measurement at 1.5v, mean value over 1 s 20.83125 20.83542 ns t periodabs usb period measurement at 1.5v, max. and min. values over 1 s 20.48125 21.18542 ns t period24 24m period measurement at 1.5v, mean value over 1 s 41.67083 41.66250 ns t period24abs 24m period measurement at 1.5v, max. and min. values over 1 s 41.57083 41.76250 ns l acc long accuracy measured at 1.5v using frequency counter over 0.15s ? 100 ppm t high usb high time (high drive) measurement at 2.0v 8.094 10.9 ns t low usb low time (high drive) measurement at 0.8v 7.694 11.5 ns t high24 usb high time (high drive) measurement at 2.0v 16.188 22.7 ns t low24 usb low time (high drive) measurement at 0.8v 15.388 22.6 ns edge rate rising edge rate (high drive) m easured between 0.8v and 2.0v 1.0 3.0 v/ns edge rate falling edge rate (high drive) m easured between 0.8v and 2.0v 1.0 3.0 v/ns t ccj usb cycle to cycle jitter (high drive) measurement taken@1.5v waveform ? 300 ps 24_48m cycle to cycle jitter (high driv e) measurement taken@1.5v waveform ? 350 ps t ltj long term jitter measurement taken from cross point v ox @ 1 s ? 700 ps ac electrical specifications (continued) parameter description c ondition min. max. unit
cy28439-2 rev 1.0, november 21, 2006 page 19 of 21 test and measurement set-up for pci single-ended signals and reference the following diagrams show the test load configurations for the single-ended pci, usb, and ref output signals. t ltj long term jitter measurement taken from cross point v ox @ 10 s ? 700 ps t ltj long term jitter measurement taken from cross point v ox @ 125 s ? 700 ps ref t dc ref duty cycle measurement at 1.5v 45 55 ns t period ref period measurement at 1.5v 69.8203 69.8622 ns t periodabs ref absolute period measurement at 1.5v 68.82033 70.86224 ns edge rate rising edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns edge rate falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj ref cycle to cycle jitter measurement at 1.5v ? 1000 ps enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms ac electrical specifications (continued) parameter description c ondition min. max. unit figure 8. single-ended load configuration pci/ usb ref 33 measurement point 5pf 60 12 measurement point 5pf 60 12 measurement point 5pf 60 figure 9. single-ended load configuration high drive option pci/ usb ref 12 measurement point 5pf 60 12 measurement point 5pf 60 12 measurement point 5pf 60 12 measurement point 5pf 60 12 measurement point 5pf 60
cy28439-2 rev 1.0, november 21, 2006 page 20 of 21 for differential cpu, src and dot96 output signals the following diagram shows the test load configuration for the differential cpu and src outputs. cput cpuc 33 33 49.9 49.9 measurement point 2pf 475 ir e f measurement point 2pf srct srcc 100 d ifferential dot96t dot96c figure 10. 0.7v single-ended load configuration 2.4v 0.4v 3.3v 0v t r t f 1.5v 3.3v si g nals t dc - - figure 11. single-ended output sign als (for ac parameters measurement) ordering information part number package type product flow lead-free cy28439oxc-2 56-pin ssop commercial, 0 to 85 c CY28439OXC-2T 56-pin ssop ? tape and reel commercial, 0 to 85 c cy28439zxc-2 56-pin tssop commercial, 0 to 85 c cy28439zxc-2t 56-pin tssop ? tape and reel commercial, 0 to 85 c
rev 1.0, november 21, 2006 page 21 of 21 cy28439-2 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.720 0.008 0.0135 0.730 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 28 56 29 0.110 0.005 0.010 56-lead shrunk small outline package o56 seating plane 1 bsc 0-8 max. gauge plane 28 29 56 1.100[0.043] 0.051[0.002] 0.851[0.033] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] dimensions in mm[inches] min. max. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.42gms part # z5624 standard pkg. zz5624 lead free pkg. 56-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z56

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