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mos integrated circuit pd8872 (5400 + 5400) pixels 3 color ccd linear image sensor data sheet document no. s15330ej4v0ds00 (4th edition) date published february 2006 ns cp (n) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. the mark shows major revised points. the revised points can be easily searched by copying an "" in the pdf file and specifying it in the "find what:" field. description the pd8872 is a color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the pd8872 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge transfer register. and it has reset feed-through level clamp ci rcuits and voltage amplifiers. t herefore, it is suitable for 1200 dpi/a4 color image scanners, color facsimiles and so on. features ? valid photocell : (5400 + 5400) staggered pixels 3 ? photocell pitch : 5.25 m ? line spacing : 63 m (12 lines) red line - green line, green line - blue line 10.5 m (2 lines) odd line - even line (for each color) ? color filter : primary colors (red, green a nd blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 48 dot/mm a4 (210 297 mm) size (shorter side) 1200 dpi us letter (8.5? 11?) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 10 mhz max. ? power supply : +12 v ? on-chip circuits : reset feed-through level clamp circuits voltage amplifiers ordering information part number package pd8872cy-a ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) remark the pd8872cy-a is a lead-free product.
data sheet s15330ej4v0ds 2 pd8872 block diagram 17 20 1 11 15 14 8 9 19 3 2 4 tg1 (blue) tg2 (green) tg3 (red) 1l rb 2 2l 1 2 1 gnd gnd v od v out 1 (blue) 21 v out 2 (green) 22 13 12 10 v out 3 (red) clb d14 d66 d67 d68 s10799 s10800 s1 s2 photocell (blue) d69 ccd analog shift register ccd analog shift register transfer gate transfer gate d14 s10799 s10800 s1 s2 photocell (green) ccd analog shift register ccd analog shift register transfer gate transfer gate d66 d14 s10799 s10800 s1 s2 photocell (red) ccd analog shift register ccd analog shift register transfer gate transfer gate d67 d68 d69 d66 d67 d68 d69 d70 d70 d70
data sheet s15330ej4v0ds 3 pd8872 pin configuration (top view) ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) ? pd8872cy-a caution connect the no connection pins (nc) to gnd. 1 2 3 4 5 6 7 8 9 10 11 nc no connection last stage shift register clock 2 v out 2 output signal 2 (green) v out 1 output signal 1 (blue) nc no connection 1 shift register clock 1 2 2l shift register clock 2 v out 3 output signal 3 (red) gnd ground nc no connection nc no connection nc no connection 10800 10800 10800 red green blue 1 1 1 tg1 transfer gate clock 1 (for blue) tg3 transfer gate clock 3 (for red) output drain voltage v od shift register clock 1 1 shift register clock 2 2 gnd ground reset gate clock rb reset feed-through level clamp clock clb 1l last stage shift register clock 1 transfer gate clock 2 (for green) tg2 22 21 20 19 18 17 16 15 14 13 12
data sheet s15330ej4v0ds 4 pd8872 photocell structure diagram photocell array structure diagram (line spacing) 5.25 m 2.75 m m 2.5 channel stopper aluminum shield blue photocell array blue photocell array green photocell array green photocell array 5.25 m 2 lines (10.5 m) 10 lines (52.5 m) 2 lines (10.5 m) 5.25 m 5.25 m 5.25 m 5.25 m 5.25 m red photocell array red photocell array 10 lines (52.5 m) 12 lines (63 m) 12 lines (63 m) 2 lines (10.5 m) 5.25 m 5.25 m 5.25 m
data sheet s15330ej4v0ds 5 pd8872 absolute maximum ratings (t a = + 25 c) parameter symbol ratings unit output drain voltage v od ? 0.3 to + 15 v shift register clock voltage v 1 , v 2 , v 1l , v 2l ? 0.3 to + 8 v reset gate clock voltage v rb ? 0.3 to + 8 v reset feed-through level clamp clock voltage v clb ? 0.3 to + 8 v transfer gate clock voltage v tg1 to v tg3 ? 0.3 to + 8 v operating ambient temperature note t a 0 to + 60 c storage temperature t stg ? 40 to + 70 c note use at the condition wi thout dew condensation. caution product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. recommended operating conditions (t a = + 25 c) parameter symbol min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v 1_h , v 2_h , v 1lh , v 2lh 4.75 5.0 5.5 v shift register clock low level v 1_l , v 2_l , v 1ll , v 2ll ? 0.3 0 + 0.25 v reset gate clock high level v rbh 4.5 5.0 5.5 v reset gate clock low level v rbl ? 0.3 0 + 0.5 v reset feed-through level clamp clock high level v clbh 4.5 5.0 5.5 v reset feed-through level clamp clock low level v clbl ? 0.3 0 + 0.5 v transfer gate clock high level v tg1h to v tg3h 4.75 v 1 _ h note v 1_h note v transfer gate clock low level v tg1l to v tg3l ? 0.3 0 + 0.15 v data rate f rb ? 2.0 10.0 mhz note when transfer gate clock high level (v tg1h to v tg3h ) is higher than shift register clock high level (v 1_h ), image lag can increase.
data sheet s15330ej4v0ds 6 pd8872 electrical characteristics t a = + 25 c, v od = 12 v, data rate (f rb ) = 2 mhz, storage time = 5.5 ms, input signal clock = 5 v p-p , light source : 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm) + ha-50 (heat absorbing filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 2.7 3.0 ? v red ser ? 0.505 ? lxs green seg ? 0.573 ? lxs saturation exposure blue seb ? 0.888 ? lxs photo response non-uniformity prnu v out = 1.0 v ? 6 20 % average dark signal ads light shielding ? 0.2 2.0 mv dark signal non-uniformit y dsnu light shielding ? 1.5 5.0 mv power consumption p w ? 360 540 mw output impedance z o ? 0.35 1.00 k ? red r r 4.15 5.94 7.73 v/lxs green r g 3.66 5.24 6.82 v/lxs response blue r b 2.36 3.38 4.39 v/lxs image lag il v out = 1.0 v ? 3.0 7.0 % offset level note 1 v os 4.5 6.0 7.5 v output fall delay time note 2 t d v out = 1.0 v, t1?, t2? = 5 ns ? 25 ? ns total transfer efficiency tte v out = 1.0 v, data rate = 10 mhz 92 98 ? % register imbalance ri v out = 1.0 v ? 1.0 4.0 % red ? 630 ? nm green ? 540 ? nm response peak blue ? 460 ? nm dr1 v sat /dsnu ? 2000 ? times dynamic range dr2 v sat / cds ? 3000 ? times reset feed-through noise notes 1, 3 rftn light shielding ? 2000 + 300 + 1000 mv random noise (cds) cds light shielding ? 1.0 ? mv notes 1. refer to timing chart 2, 3 . 2. when the fall time of 1l and 2l (t1?, t2?) is the typ. value (refer to timing chart 2, 3 ). 3. the reset feed-through noise changes by peripheral circuit of register, the driver circuit for rb and so on.
data sheet s15330ej4v0ds 7 pd8872 input pin capacitance (t a = + 25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c 1 1 9 ? 500 ? pf 14 ? 500 ? pf 1 total capacitance ? 1000 ? pf shift register clock pin capacitance 2 c 2 2 8 ? 500 ? pf 15 ? 500 ? pf 2 total capacitance ? 1000 ? pf last stage shift register clock pin capacitance c l 1l 4 ? 10 ? pf 2l 19 ? 10 ? pf reset gate clock pin capacitance c rb rb 2 ? 10 ? pf reset feed-through level clamp clock pin capacitance c clb clb 3 ? 10 ? pf transfer gate clock pin capacitance tg1 13 ? 200 ? pf tg2 12 ? 200 ? pf c tg tg3 10 ? 200 ? pf remarks 1. pins 9 and 14 ( 1), 8 and 15 ( 2) are each connected inside of the device. 2. c 1 and c 2 show the equivalent capacity of the r eal drive including the capacity of between 1 and 2.
data sheet s15330ej4v0ds 8 pd8872 timing chart 1-1 (bit clamp mode, for each color) note set the rb and clb to high level during this period. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 61 62 63 64 65 66 10866 10867 10868 10869 10870 10871 v out 1 to v out 3 rb clb 1l note invalid photocell (4 pixels) invalid photocell (4 pixels) valid photocell (10800 pixels) optical black (49 pixels) 1, 2l 2, tg1 to tg3 note
data sheet s15330ej4v0ds 9 pd8872 timing chart 1-2 (line clamp mode, for each color) note set the rb to high level during this period. remark inverse pulse of the tg1 to tg3 can be used as clb. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 61 62 63 64 65 66 10866 10867 10868 10869 10870 10871 v out 1 to v out 3 rb clb 1l note invalid photocell (4 pixels) invalid photocell (4 pixels) valid photocell (10800 pixels) optical black (49 pixels) 1, 2l 2, tg1 to tg3 tg1 to tg3) ( note
data sheet s15330ej4v0ds 10 pd8872 timing chart 2 (bit clamp mode, for each color) symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3 20 100 ? ns t4 30 150 ? ns t5, t6 0 25 ? ns t7 ? 5 note 25 ? ns t8 20 100 ? ns t9, t10 0 25 ? ns t11 5 25 ? ns note min. of t7 shows that the rb and clb overlap each other. v out clb rb 2 1 90% 10% 1l 2l 90% 10% 90% 10% rftn rftn v os t2 t1 t4 t6 t3 t5 t d t1' 10% 90% 10% t10 t11 t8 t9 t7 t2' 90% 10% 90% 10% t4 t6 t3 t5 t d t10 t11 t8 t9 t7 clb rb 90% 90% t7
data sheet s15330ej4v0ds 11 pd8872 timing chart 3 (line clamp mode, for each color) symbol min. typ. max. unit t1, t2 0 25 ? ns t1?, t2? 0 5 ? ns t3 20 100 ? ns t4 30 150 ? ns t5, t6 0 25 ? ns v out clb rb 2 1 90% 10% 1l 2l 90% 10% 90% 10% "h" rftn rftn v os t2 t1 t4 t6 t3 t5 t d t1' 10% t2' 90% 10% 90% 10% t4 t6 t3 t5 t d
data sheet s15330ej4v0ds 12 pd8872 tg1 to tg3, 1, 2 timing chart symbol min. typ. max. unit t7 ? 5 note 3 25 ? ns t9, t10 0 25 ? ns t12 5000 10000 50000 ns t13, t14 0 50 ? ns t15, t16 900 1000 ? ns t17, t18 200 400 ? ns t19 t12 t12 50000 ns t20, t21 0 50 ? ns t22, t23 0 350 ? ns notes 1. set the rb and clb to high level during this period. 2. set the rb to high level during this period. 3. min. of t7 shows that the rb and clb overlap each other. remark inverse pulse of the tg1 to tg3 can be used as clb. clb rb 90% 90% t7 rb clb (bit clamp mode) 2 tg1 to tg3 clb (line clamp mode) 1 10% 90% 90% 90% 90% 90% 10% t12 t13 t17 t7 t19 t9 t20 t10 t23 t21 t22 note 1 note 2 t18 t16 t15 t14
data sheet s15330ej4v0ds 13 pd8872 1, 2 cross points 1, 2l cross points 2, 1l cross points remark adjust cross points ( 1, 2), ( 1, 2l) and ( 2, 1l) with input resistance of each pin. 1 2 1.0 v to 4.0 v 1.0 v to 4.0 v 1 2l 2.0 v or more 0.5 v or more 2 1l 2.0 v or more 0.5 v or more
data sheet s15330ej4v0ds 14 pd8872 definitions of characteristic items 1. saturation voltage : v sat output signal voltage at whic h the response linearity is lost. 2. saturation exposure : se product of intensity of illumination (lx) and storag e time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. 4. average dark signal : ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. prnu (%) = x = x j : output voltage of valid pixel number j x x : maximum of ? x j ? x ? x 10800 j = 1 10800 x j 100 ? ? ads (mv) = d j : dark signal of valid pixel number j 10800 j = 1 10800 d j x register dark dc level v out x ?
data sheet s15330ej4v0ds 15 pd8872 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and volt age of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lxs). note that the response varies with a light source (spectral characteristic). 8. image lag : il the rate between the last output voltage and the next one after read out the data of a line. d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j ? ads ? j = 1 to 10800 ads dsnu register dark dc level v out v out tg light v out on off v 1 il (%) = v 1 v out 100
data sheet s15330ej4v0ds 16 pd8872 9. register imbalance: ri the rate of the difference between the averages of t he output voltage of odd and even pixels, against the average output voltage of all the valid pixels. 10. random noise (cds) : cds random noise cds is defined as the standard de viation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). cds is calculated by the following procedure. 1. one valid photocell in one read ing is fixed as measurement point. 2. the output level is measured dur ing the reset feed-through period which is averaged over 100 ns to get ?vd i ?. 3. the output level is measured during the video output time averaged over 100 ns to get ?vo i ?. 4. the correlated double sampling output is defined by the following formula. vcds i = vd i ? vo i 5. repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. calculate the standard deviation cds using the following formula equation. ri (%) = 2 n j = 1 j = 1 n 2 (v 2j ?1 ? v 2j ) 1 n n v j 100 n v j : number of valid pixels : output voltage of each pixel cds (mv) = , v = i = 1 100 (vcds i ? v) 2 i = 1 100 vcds i 100 100 1 reset feed-through video output
data sheet s15330ej4v0ds 17 pd8872 standard characteristic curves (reference value) dark output temperature characteristic storage time output voltage characteristic (t a = +25 c) operating ambient temperature t a ( c) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 400 500 600 700 800 100 80 60 40 20 0 b b g r g response ratio (%) wavelength (nm) total spectral response characteristics (without infrared cut filter and heat absorbing filter) (t a = +25 c)
data sheet s15330ej4v0ds 18 pd8872 application circuit example caution connect the no connection pins (nc) to gnd. remarks 1. the inverters shown in the above applicati on circuit example are the 74hc04 (data rate < 2 mhz) or the 74ac04 (2 data rate < 10 mhz). 2. inverters b1 to b3 in the above application circuit example are shown in the figure below. 47 f/25 v b1 to b3 equivalent circuit + 12 v 100 ? 100 ? ccd v out 2sc945 2 k ? v out 3 pd8872 v out 1 gnd nc nc nc nc gnd nc 1 2 2 2l tg3 clb 1l tg1 1 tg2 47 ? 4.7 ? 150 ? 4.7 ? 4.7 ? 10 ? 10 ? 4.7 ? 47 ? 150 ? 10 ? 122 21 20 19 18 17 16 15 14 13 12 2 3 4 5 6 7 9 8 10 11 v out 2 v od rb b3 +12 v 0.1 f 47 f/25 v 0.1 f 10 f/16 v tg 1 rb 2 clb b2 +5 v +5 v + 0.1 f 10 f/16 v 1l + + b1 2l
data sheet s15330ej4v0ds 19 pd8872 package drawing ccd linear image sensor 22-pin plastic dip (10.16 mm (400) ) pd8872cy 44.0 0.3 37.5 1st valid pixel 0.5 0.3 1 9.25 0.3 2.0 0.25 0.05 10.16 0.2 0.46 0.1 2.54 0.25 1.02 0.15 (5.42) 4.21 0.5 4.39 0.4 12 11 2.55 0.2 3 (1.79) 2 name dimensions refractive index plastic cap 42.9 8.35 0.7 1.5 1 1st valid pixel the center of the pin1 2 the surface of the ccd chip the top of the cap 3 the bottom of the package the surface of the ccd chip 22c-1ccd-pkg14-2 (unit : mm) 1 22 10.16 + 0.7 ? 0.2
data sheet s15330ej4v0ds 20 pd8872 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd8872cy-a : ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) process conditions partial heating method pin temperature : 300 c or below, heat time : 3 seconds or less (per pin) cautions 1. during assembly care should be taken to prevent solder or flux from contacting the plastic cap. the optical characteristics coul d be degraded by such contact. 2. soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. so the method cannot be guaranteed.
data sheet s15330ej4v0ds 21 pd8872 notes on handling the packages cleaning the plastic cap dust and dirt protecting mounting of the package operate and storage environments ethyl alcohol methyl alcohol isopropyl alcohol n-methyl pyrrolidone etoh meoh ipa nmp the optical characteristics of the ccd will be degraded if the cap is scratched during cleaning. don?t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. should dirt stick to a plastic cap surface, blow it off with an air blower. for dirt stuck through electricity ionized air is recommended. and if the plastic cap surface is grease stained, clean with our recommended solvents. care should be taken when cleaning the surface to prevent scratches. we recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. excessive pressure should not be applied to the cap during cleaning. if the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. the following are the recommended solvents for cleaning the ccd plastic cap. use of solvents other than these could result in optical or physical degradation in the plastic cap. please consult your sales office when considering an alternative solvent. the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with plastic cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) 1 2 electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m ? . 4 3 recommended solvents solvents symbol
data sheet s15330ej4v0ds 22 pd8872 [memo]
data sheet s15330ej4v0ds 23 pd8872 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd8872 the information in this document is current as of february, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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