 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| pd784046 subseries hardware 16-bit single-chip microcontrollers user? manual pd784044 pd784044(a) pd784046 pd784044(a1) pd78f4046 pd784044(a2) pd784046(a) pd784046(a1) pd784046(a2) document no. u11515ej3v0ud00 (3rd edition) date published march 2003 n cp(k) printed in japan c printed in japan
2 user? manual u11515ej3v0ud [memo] 3 user? manual u11515ej3v0ud fip and iebus are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. ethernet is a trademark of zerox corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 user s manual u11515ej3v0ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of november, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": 5 user s manual u11515ej3v0ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v ? lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user? manual u11515ej3v0ud major revisions in this edition the mark shows major revised points. page contents completion of development of the following products pd784046, 78f4046, 784046(a), 784046(a1), 784046(a2) chapter 1 general update of 78k/iv product lineup chapter 2 pin functions addition of description on bwd pin in table 2-6 i/o circuit type of each pin and recommended processing of unused pins chapter 14 asynchronous serial interface/3-wire serial i/o addition of cautions on start bit during uart transmission to 14.5 cautions chapter 18 standby function ?modification of figure 18-1 diagram of standby mode transition ?modification of description in 18.6 (5) a/d converter chapter 20 programming pd78f4046 ?addition of description on flashpro iii ?addition of 20.4 cautions addition of chapter 22 electrical specifications ( pd784044, 784046) addition of chapter 23 electrical specifications ( pd784044(a), 784046(a)) addition of chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) addition of chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) addition of chapter 26 electrical specifications ( pd78f4046) addition of chapter 27 timing charts addition of chapter 28 package drawing addition of chapter 29 recommended soldering conditions appendix a development tools ?addition of description on host machines and oss ?addition of sp78k4 to a.1 language processing software, modification of description in remark ?addition of description on flashpro iii in remark in a.2 flash memory writing tools ?addition and modification of description in a.3.1 hardware ?modification of description in remark in a.3.2 software ?addition of a.4 cautions on designing target system modification of description in appendix b embedded software throughout p. 33 p. 54 p. 354 p. 459 p. 472 p. 478 p. 480 p. 518 p. 524 p. 530 p. 536 p. 542 p. 548 p. 553 p. 554 p. 557 pp. 560, 561 p. 561 pp. 562, 563 p. 564 p. 565 p. 569 7 user? manual u11515ej3v0ud introduction intended reader this manual is intended for user engineers who understand the functions of the pd784046 subseries and wish to design application systems using this subseries. the relevant products are the following pd784046 subseries products. standard products : pd784044, 784046, 78f4046 special products : pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2) purpose the purpose of this manual is to give users an understanding of the various hardware functions of the pd784046 subseries. organization the pd784046 subseries manual is divided into two volumes ?the hardware volume (this manual) and the instruction volume. hardware volume instruction volume pin functions cpu functions internal block functions addressing interrupts instruction set other on-chip peripheral functions electrical specifications certain operating precautions apply to these products. these precautions are stated at the relevant points in the text of each chapter, and are also summarized at the end of each chapter. be sure to read them. how to read this manual readers are required a general knowledge of electrical and logic circuits and microcomputers. to readers using this manual for other than pd784046: this manual covers the functions of the pd784046 subseries. the relationship between these products is shown below. pd78f4046 pd784046, 784046(a), (a1), (a2) pd784044, 784044(a), (a1), (a2) on-chip flash memory product on-chip mask rom products flash memory 64 k ram 2048 rom 32 k ram 1024 rom 64 k ram 2048 8 user? manual u11515ej3v0ud if there are no particular differences in terms of function: the pd784046 is treated as the representative model. therefore, when using this manual for other products of the pd784046 subseries, pd784046 should be read as each product name as appropriate. for the differences between products, refer to 1.8 differences between pd784044, 784046, and 78f4046, 1.9 differences between pd784046 and pd784046(a), and 1.10 differences between pd784046(a), 784046(a1), and 784046(a2) . if there are functional differences: a separate description is given, mentioning the product name. the application examples presented in this manual are for the ?tandard?quality models in general-purpose electronic systems. if you wish to use the applications presented in this manual for electronic systems that require ?pecial?quality models, thoroughly study the parts and circuits to be actually used, and their quality grade. ? to check the details of a register when the register name is known: use appendix c register index . ? if the device operates strangely after debugging: cautions are summarized at the end of each chapter, so refer to the cautions for the relevant function. ? for a general understanding of the functions read in accordance with the contents . ? for the details of the instruction functions: refer to the separate 78k/iv series user? manual ?instruction (u10905e) . ? to find out about electrical specifications refer to the each chapter of electrical specifications. ? to find out about application examples of each function, refer to the application note separately available. legend significance in data notation : high-order digit on left, low-order digit on right active-low notation : (line above pin or signal name) note : explanation of item marked with note in the text caution : item to be especially noted remark : supplementary information numeric notations : binary ................. b or decimal .............. hexadecimal ....... h 9 user? manual u11515ej3v0ud register notation 7 b edc 6 1 5 0 4 3 a 2 1 1 0 0 write operation read operation 0 or 1 is written. the operation is not affected by either value. 0 must be written 1 must be written a value is written according to the function to be used. a value is read according to the operating status. 0 or 1 is read. 0 is read. 1 is read. where the bit number is marked with a circle, the bit name is reserved for nec electronics assembler and is defined as a sfr variable by the #pragma sfr directive for c compiler. code combinations marked ?etting prohibited?in the register notations in the text must not be written. easily confused characters : 0 (zero), o (letter o) : 1 (one), l (lower-case letter l), i (upper-case letter i) 10 user? manual u11515ej3v0ud related documents the related documents in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd784046 subseries user? manual - hardware this manual 78k/iv series application note - software fundamentals u10095e 78k/iv series user's manual - instructions u10905e documents related to development tools (user? manuals) document name document no. ra78k4 assembler package operation u15254e language u15255e structured assembler preprocessor u11743e cc78k4 c compiler operation u15557e language u15556e sm78k series ver. 2.30 or later system simulator operation (windows tm based) u15373e external part user open interface specification u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e rx78k4 real-time os fundamentals u10603e installation u10604e project manager ver 3.12 or later (windows based) u14610e documents related to development hardware tools (user? manuals) document name document no. ie-78k4-ns in-circuit emulator u13356e ie-784046-ns-em1 emulation board u13744e ie-784000-r in-circuit emulator u12903e ie-784046-r-em1 emulation board u11677e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 11 user? manual u11515ej3v0ud documents related to flash memory writing (user? manuals) document name document no. pg-fp3 flash memory programmer user? manual u13502e other related documents document name document no. semiconductor selection guide - products & packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 12 user? manual u11515ej3v0ud contents chapter 1 general .................................................................................................................. 32 1.1 features ........................................................................................................................... 34 1.2 ordering information ...................................................................................................... 35 1.3 quality grades ................................................................................................................ 35 1.4 pin configuration (top view) ........................................................................................ 36 1.5 system configuration example (ac servo motor control) ...................................... 38 1.6 block diagram ................................................................................................................. 39 1.7 list of functions ............................................................................................................. 40 1.8 differences between pd784044, 784046, and 78f4046 ........................................... 41 1.9 differences between pd784046 and pd784046(a) ................................................. 41 1.10 differences between pd784046(a), 784046(a1), and 784046(a2) .......................... 41 chapter 2 pin functions .......................................................................................................... 42 2.1 list of pin functions ...................................................................................................... 42 2.2 description of pin functions ........................................................................................ 46 2.3 i/o circuits of pins and processing of unused pins ................................................ 53 chapter 3 cpu architecture ................................................................................................. 56 3.1 memory space ................................................................................................................. 56 3.2 internal rom area .......................................................................................................... 59 3.3 base area ......................................................................................................................... 60 3.3.1 vector table area ................................................................................................................ 61 3.3.2 callt instruction table area ............................................................................................. 62 3.3.3 callf instruction entry area ............................................................................................ 62 3.4 internal data area ......................................................................................................... 62 3.4.1 internal ram area .............................................................................................................. 63 3.4.2 special function register (sfr) area ................................................................................. 66 3.4.3 external sfr area ............................................................................................................. 66 3.5 external memory space ................................................................................................. 66 3.6 memory mapping of pd78f4046 ................................................................................. 67 3.7 control registers ............................................................................................................ 68 3.7.1 program counter (pc) ........................................................................................................ 68 3.7.2 program status word (psw) .............................................................................................. 68 3.7.3 use of rss bit .................................................................................................................... 71 3.7.4 stack pointer (sp) .............................................................................................................. 73 3.8 general registers ........................................................................................................... 77 3.8.1 configuration ...................................................................................................................... 77 3.8.2 functions ............................................................................................................................ 79 3.9 special function registers (sfrs) .............................................................................. 82 3.10 cautions ........................................................................................................................... 88 13 user? manual u11515ej3v0ud chapter 4 clock generator .................................................................................................. 89 4.1 configuration and function .......................................................................................... 89 4.2 control registers ............................................................................................................ 91 4.2.1 standby control register (stbc) ....................................................................................... 91 4.2.2 oscillation stabilization time specification register (osts) ............................................. 92 4.3 clock generator operation ........................................................................................... 93 4.3.1 clock oscillator ................................................................................................................... 93 4.3.2 frequency divider ............................................................................................................... 93 4.4 cautions ........................................................................................................................... 94 4.4.1 when an external clock is input ........................................................................................ 94 4.4.2 when crystal/ceramic oscillation is used .......................................................................... 95 chapter 5 port functions ...................................................................................................... 98 5.1 digital input/output port ................................................................................................ 98 5.2 port 0 ...................................................................................................................... .......... 100 5.2.1 hardware configuration ...................................................................................................... 100 5.2.2 input/output mode/control mode setting ............................................................................ 101 5.2.3 operating status ................................................................................................................. 102 5.2.4 internal pull-up resistors .................................................................................................... 104 5.3 port 1 ...................................................................................................................... .......... 106 5.3.1 hardware configuration ...................................................................................................... 107 5.3.2 setting i/o mode/control mode .......................................................................................... 108 5.3.3 operating status ................................................................................................................. 109 5.4 port 2 ...................................................................................................................... .......... 112 5.4.1 hardware configuration ...................................................................................................... 113 5.4.2 setting i/o mode/control mode .......................................................................................... 115 5.4.3 operating status ................................................................................................................. 116 5.5 port 3 ...................................................................................................................... .......... 119 5.5.1 hardware configuration ...................................................................................................... 120 5.5.2 input/output mode/control mode setting ............................................................................ 122 5.5.3 operating status ................................................................................................................. 124 5.6 port 4 ..................................................................................................................... .......... 127 5.6.1 hardware configuration ..................................................................................................... 127 5.6.2 input/output mode/control mode setting ............................................................................ 128 5.6.3 operating status ................................................................................................................. 129 5.6.4 internal pull-up resistors .................................................................................................... 131 5.7 port 5 ..................................................................................................................... .......... 133 5.7.1 hardware configuration ...................................................................................................... 133 5.7.2 input/output mode/control mode setting ............................................................................ 134 5.7.3 operating status ................................................................................................................. 135 5.7.4 internal pull-up resistors .................................................................................................... 137 5.8 port 6 ..................................................................................................................... .......... 139 5.8.1 hardware configuration ...................................................................................................... 139 5.8.2 setting of i/o mode/control mode ..................................................................................... 140 5.8.3 operating status ................................................................................................................. 141 5.8.4 internal pull-up resistors .................................................................................................... 143 14 user? manual u11515ej3v0ud 5.9 port 7 ...................................................................................................................... .......... 145 5.9.1 hardware configuration ...................................................................................................... 145 5.9.2 notes ............................................................................................................................... .... 145 5.10 port 8 ............................................................................................................................... . 146 5.10.1 hardware configuration ...................................................................................................... 146 5.10.2 cautions .............................................................................................................................. 1 46 5.11 port 9 ............................................................................................................................... . 147 5.11.1 hardware configuration ...................................................................................................... 148 5.11.2 setting of i/o mode/control mode ..................................................................................... 150 5.11.3 operating status ................................................................................................................. 151 5.11.4 internal pull-up resistor ...................................................................................................... 153 5.12 port output data check function ................................................................................ 155 5.13 cautions ........................................................................................................................... 158 chapter 6 real-time output function ............................................................................... 160 6.1 configuration and function .......................................................................................... 160 6.2 real-time output port control register (rtpc) ........................................................ 161 6.3 operation ......................................................................................................................... 162 6.4 example of use ............................................................................................................... 163 6.5 cautions ........................................................................................................................... 165 chapter 7 outline of timer/counter ................................................................................. 166 chapter 8 timer 0 ......................................................................................................................... 170 8.1 function ........................................................................................................................... 170 8.2 configuration ................................................................................................................... 171 8.3 timer 0 control register ............................................................................................... 174 8.4 operation of timer register 0 (tm0) ............................................................................ 177 8.4.1 basic operation ................................................................................................................... 177 8.4.2 clear operation ................................................................................................................... 179 8.5 operation of capture/compare register ..................................................................... 180 8.5.1 compare operation ............................................................................................................ 180 8.5.2 capture operation .............................................................................................................. 182 8.6 basic operation of output control circuit ................................................................. 184 8.6.1 basic operation ................................................................................................................... 186 8.6.2 toggle output ...................................................................................................................... 186 8.6.3 set/reset output .................................................................................................................. 187 8.7 examples of use ............................................................................................................. 188 8.7.1 operation as interval timer ................................................................................................ 188 8.7.2 pulse width measurement operation ................................................................................. 191 8.8 cautions ........................................................................................................................... 194 chapter 9 timer 1 ......................................................................................................................... 197 9.1 function ........................................................................................................................... 197 9.2 configuration ................................................................................................................... 197 15 user? manual u11515ej3v0ud 9.3 timer 1 control register ............................................................................................... 200 9.4 operation of timer register 1 (tm1) ............................................................................ 203 9.4.1 basic operation ................................................................................................................... 203 9.4.2 clear operation .................................................................................................................. 205 9.5 operation of compare register .................................................................................... 207 9.6 basic operation of output control circuit ................................................................. 210 9.6.1 basic operation ................................................................................................................... 211 9.6.2 toggle output ...................................................................................................................... 211 9.6.3 set/reset output .................................................................................................................. 212 9.7 examples of use ............................................................................................................. 213 9.7.1 operation as interval timer (1) ........................................................................................... 213 9.7.2 operation as interval timer (2) ........................................................................................... 216 9.8 cautions ........................................................................................................................... 218 chapter 10 timers/counters 2 and 3 .................................................................................. 221 10.1 function ........................................................................................................................... 222 10.2 configuration ................................................................................................................... 223 10.3 timer/counter 2 control register ................................................................................ 226 10.4 operation of timer register 2 (tm2) ............................................................................ 230 10.4.1 basic operation ................................................................................................................... 230 10.4.2 clear operation ................................................................................................................... 232 10.5 external event counter function ................................................................................. 234 10.6 operation of compare register .................................................................................... 236 10.7 basic operation of output control circuit ................................................................. 239 10.7.1 basic operation ................................................................................................................... 239 10.7.2 toggle output ...................................................................................................................... 239 10.7.3 pwm output ........................................................................................................................ 241 10.7.4 ppg output ......................................................................................................................... 246 10.8 examples of use ............................................................................................................. 252 10.8.1 operation as interval timer (1) ........................................................................................... 252 10.8.2 operation as interval timer (2) ......................................................................................... 255 10.8.3 operation as pwm output ................................................................................................. 258 10.8.4 operation as ppg output ................................................................................................... 262 10.8.5 operation as external event counter ................................................................................. 267 10.9 cautions ........................................................................................................................... 269 chapter 11 timer 4 ....................................................................................................................... 271 11.1 function ........................................................................................................................... 271 11.2 configuration ................................................................................................................... 271 11.3 timer 4 control register ............................................................................................... 274 11.4 operation of timer register 4 (tm4) ............................................................................ 276 11.4.1 basic operation ................................................................................................................... 276 11.4.2 clear operation ................................................................................................................... 278 11.5 operation of compare register .................................................................................... 280 11.6 example of use ............................................................................................................... 282 11.6.1 operation as interval timer (1) ........................................................................................... 282 16 user? manual u11515ej3v0ud 11.6.2 operation as interval timer (2) ........................................................................................... 285 11.7 cautions ........................................................................................................................... 287 chapter 12 watchdog timer function ............................................................................... 289 12.1 configuration ................................................................................................................... 289 12.2 watchdog timer mode register (wdm) ....................................................................... 290 12.3 operation ......................................................................................................................... 292 12.3.1 count operation .................................................................................................................. 292 12.3.2 interrupt priorities ............................................................................................................... 292 12.4 cautions ........................................................................................................................... 293 12.4.1 general cautions on use of watchdog timer ..................................................................... 293 12.4.2 cautions on pd784046 subseries watchdog timer ........................................................ 293 chapter 13 a/d converter ...................................................................................................... 294 13.1 configuration ................................................................................................................... 294 13.2 a/d converter mode register (adm) ........................................................................... 298 13.3 a/d conversion result registers (adcr0 through adcr7) .................................... 301 13.4 operation ......................................................................................................................... 303 13.4.1 basic a/d converter operation ........................................................................................... 303 13.4.2 select mode ........................................................................................................................ 307 13.4.3 scan mode ......................................................................................................................... 309 13.4.4 a/d conversion operation start by software ................................................................... 311 13.4.5 a/d conversion operation start by hardware .................................................................. 313 13.5 external circuit of a/d converter ................................................................................. 316 13.6 cautions ........................................................................................................................... 316 chapter 14 asynchronous serial interface/3-wire serial i/o .............................. 318 14.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode .................................................................................................... 319 14.2 asynchronous serial interface mode .......................................................................... 320 14.2.1 configuration in asynchronous serial interface mode ...................................................... 320 14.2.2 asynchronous serial interface control registers ................................................................ 323 14.2.3 data format ......................................................................................................................... 327 14.2.4 parity types and operations ............................................................................................... 328 14.2.5 transmission ....................................................................................................................... 329 14.2.6 reception ............................................................................................................................ 330 14.2.7 receive errors .................................................................................................................... 331 14.2.8 transmitting/receiving data with macro service ................................................................ 333 14.3 3-wire serial i/o mode .................................................................................................... 335 14.3.1 configuration in 3-wire serial i/o mode ........................................................................... 335 14.3.2 clocked serial interface mode registers (csim1, csim2) ............................................... 338 14.3.3 basic operation timing ....................................................................................................... 339 14.3.4 operation when transmission only is enabled .................................................................. 341 14.3.5 operation when reception only is enabled ........................................................................ 342 14.3.6 operation when transmission/reception is enabled .......................................................... 343 14.3.7 corrective action in case of slippage of serial clock and shift operations ....................... 343 17 user? manual u11515ej3v0ud 14.4 baud rate generator ...................................................................................................... 344 14.4.1 baud rate generator configuration ..................................................................................... 344 14.4.2 baud rate generator control register ............................................................................. 346 14.4.3 baud rate generator operation ....................................................................................... 348 14.4.4 baud rate setting in asynchronous serial interface mode ............................................. 350 14.5 cautions ........................................................................................................................... 353 chapter 15 edge detection function ................................................................................ 359 15.1 edge detection function control registers ............................................................... 359 15.1.1 external interrupt mode registers (intm0, intm1) .......................................................... 359 15.1.2 interrupt valid edge flag registers (ief1, ief2) ................................................................ 362 15.1.3 noise protection control register (npc) ............................................................................ 364 15.2 edge detection for pin p20 ........................................................................................... 365 15.3 pin edge detection for pins p21 to p27 ...................................................................... 366 15.4 cautions ........................................................................................................................... 367 chapter 16 interrupt functions ......................................................................................... 368 16.1 interrupt request sources ............................................................................................ 369 16.1.1 software interrupts ............................................................................................................. 371 16.1.2 operand error interrupts .................................................................................................... 371 16.1.3 non-maskable interrupts .................................................................................................... 371 16.1.4 maskable interrupts ............................................................................................................ 371 16.2 interrupt processing modes .......................................................................................... 372 16.2.1 vectored interrupt processing ............................................................................................ 372 16.2.2 macro service ..................................................................................................................... 372 16.2.3 context switching ............................................................................................................... 372 16.3 interrupt processing control registers ...................................................................... 373 16.3.1 interrupt control registers ................................................................................................... 375 16.3.2 interrupt mask registers (mk0, mk1) ................................................................................ 381 16.3.3 in-service priority register (ispr) ...................................................................................... 383 16.3.4 interrupt mode control register (imc) ................................................................................ 384 16.3.5 watchdog timer mode register (wdm) .............................................................................. 385 16.3.6 program status word (psw) .............................................................................................. 386 16.4 software interrupt acknowledgment operations ....................................................... 387 16.4.1 brk instruction software interrupt acknowledgment operation ....................................... 387 16.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation ................................................................................................ 387 16.5 operand error interrupt acknowledgment operation ............................................... 388 16.6 non-maskable interrupt acknowledgment operation ............................................... 389 16.7 maskable interrupt acknowledgment operation ........................................................ 393 16.7.1 vectored interrupt ............................................................................................................... 395 16.7.2 context switching ............................................................................................................... 395 16.7.3 maskable interrupt priority levels ....................................................................................... 397 16.8 macro service function ................................................................................................. 403 16.8.1 outline of macro service function ...................................................................................... 403 16.8.2 types of macro service ...................................................................................................... 403 18 user? manual u11515ej3v0ud 16.8.3 basic operation of macro service (except cpu monitor modes 0 and 1) ....................... 407 16.8.4 operation on completion of macro servicing (except cpu monitor modes 0 and 1) ..... 408 16.8.5 macro service control register ........................................................................................... 409 16.8.6 macro service mode ........................................................................................................... 411 16.8.7 operation of macro service ............................................................................................... 411 16.9 when interrupt request and macro service are temporarily held pending ......... 423 16.10 instructions whose execution is temporarily suspended by an interrupt or macro service .................................................................................. 425 16.11 interrupt and macro service operation timing .......................................................... 425 16.11.1 interrupt acceptance processing time ............................................................................... 426 16.11.2 processing time of macro service ..................................................................................... 427 16.12 restoring interrupt function to initial state .............................................................. 428 16.13 cautions ........................................................................................................................... 429 chapter 17 local bus interface function ..................................................................... 431 17.1 memory extension function ......................................................................................... 431 17.1.1 memory extension mode register (mm) ............................................................................ 431 17.1.2 memory map with external memory extension ................................................................. 433 17.1.3 basic operation of local bus interface ............................................................................ 437 17.2 wait function .................................................................................................................. 440 17.2.1 wait function control registers ........................................................................................... 440 17.2.2 address waits ..................................................................................................................... 446 17.2.3 access waits ....................................................................................................................... 449 17.3 bus sizing function ....................................................................................................... 456 17.3.1 bus width specification register (bw) ............................................................................... 456 17.4 cautions ........................................................................................................................... 458 chapter 18 standby function ............................................................................................... 459 18.1 configuration and function .......................................................................................... 459 18.2 control registers ............................................................................................................ 461 18.2.1 standby control register (stbc) ....................................................................................... 461 18.2.2 oscillation stabilization time specification register (osts) ............................................. 462 18.3 halt mode ....................................................................................................................... 464 18.3.1 halt mode setting and operating states .......................................................................... 464 18.3.2 halt mode release ............................................................................................................ 464 18.4 stop mode ...................................................................................................................... 467 18.4.1 stop mode setting and operating states ......................................................................... 467 18.4.2 stop mode release ........................................................................................................... 468 18.5 idle mode ........................................................................................................................ 469 18.5.1 idle mode setting and operating states ........................................................................... 469 18.5.2 idle mode release ........................................................................................................... 470 18.6 check items when stop mode/idle mode is used .................................................. 471 18.7 cautions ........................................................................................................................... 473 19 user? manual u11515ej3v0ud chapter 19 reset function .................................................................................................... 474 19.1 reset function ................................................................................................................ 474 19.2 caution ............................................................................................................................. 47 7 chapter 20 programming pd78f4046 ................................................................................. 478 20.1 selecting communication mode ................................................................................... 478 20.2 function of flash memory programming ................................................................... 479 20.3 connecting flashpro ii/flashpro iii .............................................................................. 479 20.4 cautions ........................................................................................................................... 480 chapter 21 instruction operations ................................................................................... 482 21.1 legend .............................................................................................................................. 4 82 21.2 list of operations ........................................................................................................... 486 21.3 instructions listed by type of addressing ................................................................. 512 chapter 22 electrical specifications ( pd784044, 784046) ....................................... 518 chapter 23 electrical specifications ( pd784044(a), 784046(a)) ............................. 524 chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) .......................... 530 chapter 25 electrical specifications ( pd784044(a2), 784046(a2) .......................... 536 chapter 26 electrical specifications ( pd78f4046) .................................................... 542 chapter 27 timing charts ........................................................................................................ 548 chapter 28 package drawing ................................................................................................ 553 chapter 29 recommended soldering conditions ........................................................ 554 chapter 30 cautions on using development tools .................................................... 556 appendix a development tools ............................................................................................ 557 a.1 language processing software .................................................................................... 560 a.2 flash memory writing tools .......................................................................................... 561 a.3 debugging tools ............................................................................................................. 562 a.3.1 hardware ............................................................................................................................ 562 a.3.2 software .............................................................................................................................. 5 64 a.4 cautions on designing target system ........................................................................ 565 a.5 deminsions of conversion socket (ev-9200gc-80) and recommended board mounting pattern ............................................................. 567 20 user? manual u11515ej3v0ud appendix b embedded software ....................................................................................... 569 appendix c register index ...................................................................................................... 570 appendix d revision history ................................................................................................... 574 21 user? manual u11515ej3v0ud list of figures (1/8) figure no. title page 2-1 i/o circuits of pins .............................................................................................................................. 5 5 3-1 pd784044 memory map ................................................................................................................... 57 3-2 pd784046 memory map ................................................................................................................... 58 3-3 internal ram memory map ................................................................................................................ 64 3-4 format of internal memory size select register (ims) .................................................................... 67 3-5 format of program counter (pc) ....................................................................................................... 68 3-6 format of program status word (psw) ............................................................................................ 68 3-7 format of stack pointer (sp) ............................................................................................................. 73 3-8 data saved to stack area .................................................................................................................. 74 3-9 data restored from stack area ......................................................................................................... 75 3-10 format of general-purpose register ................................................................................................. 77 3-11 general-purpose register addresses ............................................................................................... 78 4-1 block diagram of clock generator ..................................................................................................... 89 4-2 clock oscillator external circuitry ..................................................................................................... 90 4-3 standby control register (stbc) format ......................................................................................... 91 4-4 format of oscillation stabilization time specification register (osts) .......................................... 92 4-5 signal extraction with external clock input ....................................................................................... 94 4-6 cautions on resonator connection ................................................................................................... 95 4-7 incorrect example of resonator connection ..................................................................................... 96 5-1 port configuration ............................................................................................................................... 98 5-2 block diagram of port 0 ...................................................................................................................... 100 5-3 format of port 0 mode register (pm0) ............................................................................................. 101 5-4 format of real-time output port control register (rtpc) ............................................................. 101 5-5 port specified as output port ............................................................................................................. 102 5-6 port specified as input port ............................................................................................................... 103 5-7 pull-up resistor option register l (puol) format ......................................................................... 104 5-8 pull-up resistor specification (port 0) .............................................................................................. 105 5-9 block diagram of port 1 ...................................................................................................................... 107 5-10 format of port 1 mode register (pm1) ............................................................................................. 108 5-11 format of port 1 mode control register (pmc1) .............................................................................. 108 5-12 port specified as output port ............................................................................................................. 109 5-13 port specified as input port ............................................................................................................... 110 5-14 control specification ........................................................................................................................... 111 5-15 block diagram of p20 (port 2) ........................................................................................................... 113 5-16 block diagram of p21 to p24 (port 2) ............................................................................................... 114 5-17 block diagram of p25 to p27 (port 2) ............................................................................................... 114 5-18 format of port 2 mode register (pm2) ............................................................................................. 115 5-19 format of port 2 mode control register (pmc2) .............................................................................. 115 5-20 port in output port mode .................................................................................................................... 116 5-21 port in input port mode ...................................................................................................................... 117 22 user? manual u11515ej3v0ud 5-22 port in control mode ........................................................................................................................... 118 5-23 block diagram of p30, p31, p33 and p36 (port 3) ........................................................................... 120 5-24 block diagram of p32 and p35 (port 3) ............................................................................................ 120 5-25 block diagram of p34 and p37 (port 3) ............................................................................................ 121 5-26 format of port 3 mode register (pm3) ............................................................................................. 122 5-27 format of port 3 mode control register (pmc3) .............................................................................. 123 5-28 port specified as output port ............................................................................................................. 124 5-29 port specified as input port ............................................................................................................... 125 5-30 control specification ........................................................................................................................... 126 5-31 block diagram of port 4 ...................................................................................................................... 127 5-32 format of port 4 mode register (pm4) ............................................................................................. 128 5-33 port specified as output port ............................................................................................................. 129 5-34 port specified as input port ............................................................................................................... 130 5-35 format of pull-up resistor option register l (puol) ...................................................................... 131 5-36 pull-up resistor specification (port 4) .............................................................................................. 132 5-37 block diagram of port 5 ...................................................................................................................... 133 5-38 format of port 5 mode register (pm5) ............................................................................................. 134 5-39 port specified as output port ............................................................................................................. 135 5-40 port specified as input port ............................................................................................................... 136 5-41 format of pull-up resistor option register l (puol) ..................................................................... 137 5-42 pull-up resistor specification (port 5) .............................................................................................. 138 5-43 block diagram of port 6 ...................................................................................................................... 139 5-44 format of port 6 mode register (pm6) ............................................................................................. 140 5-45 port specified as output port ............................................................................................................. 141 5-46 port specified as input port ............................................................................................................... 142 5-47 format of pull-up resistor option register l (puol) ..................................................................... 143 5-48 pull-up resistor specification (port 6) .............................................................................................. 144 5-49 block diagram of port 7 ...................................................................................................................... 145 5-50 block diagram of port 8 ...................................................................................................................... 146 5-51 block diagram of p90 to p93 (port 9) ............................................................................................... 148 5-52 block diagram of p94 (port 9) ........................................................................................................... 149 5-53 format of port 9 mode register (pm9) ............................................................................................. 150 5-54 format of port 9 mode control register (pmc9) .............................................................................. 150 5-55 port in output port mode .................................................................................................................... 151 5-56 port in input port mode ...................................................................................................................... 152 5-57 format of pull-up resistor option register h (puoh) ..................................................................... 153 5-58 specifying pull-up resistor (port 9) ................................................................................................... 154 5-59 format of port read control register (prdc) ................................................................................. 155 5-60 concept of control (in output port mode) .......................................................................................... 156 6-1 block diagram of real-time output port ............................................................................................ 160 6-2 format of real-time output port control register (rtpc) ............................................................. 161 6-3 operation timing of real-time output port ...................................................................................... 162 list of figures (2/8) figure no. title page 23 user? manual u11515ej3v0ud 6-4 operation timing of real-time output port ...................................................................................... 163 6-5 settings for real-time output function control register ................................................................ 164 6-6 setting procedure of real-time output function ............................................................................. 164 6-7 interrupt request processing when real-time output function is used ....................................... 165 7-1 block diagram of timer/counter ........................................................................................................ 167 8-1 block diagram of timer 0 ................................................................................................................... 172 8-2 format of timer unit mode register 0 (tum0) ................................................................................. 174 8-3 format of timer mode control register (tmc) ................................................................................. 175 8-4 format of timer output control register 0 (toc0) .......................................................................... 175 8-5 format of prescaler mode register (prm) ....................................................................................... 176 8-6 basic operation of timer register 0 (tm0) ....................................................................................... 178 8-7 clear operation of timer register 0 (tm0) ....................................................................................... 179 8-8 compare operation (timer 0) ............................................................................................................. 181 8-9 capture operation (timer 0) ............................................................................................................... 182 8-10 block diagram of timer output operation of timer 0 ....................................................................... 185 8-11 operation of toggle output ................................................................................................................ 186 8-12 operation of set/reset output (timer 0) ............................................................................................ 187 8-13 timing of interval timer operation .................................................................................................... 188 8-14 set contents of control register for interval timer operation ......................................................... 189 8-15 setting procedure of interval timer operation .................................................................................. 190 8-16 interrupt request processing of interval timer operation ............................................................... 190 8-17 timing of pulse width measurement ................................................................................................. 191 8-18 control register settings for pulse width measurement .................................................................. 192 8-19 pulse width measurement setting procedure ................................................................................... 193 8-20 interrupt request processing that calculates pulse width .............................................................. 193 8-21 operation when counting is started ................................................................................................. 194 8-22 operation when compare register (cc00 to cc03) is set to 0000h ............................................ 195 9-1 block diagram of timer 1 ................................................................................................................... 198 9-2 format of timer unit mode register 0 (tum0) ................................................................................. 200 9-3 format of timer mode control register (tmc) ................................................................................. 201 9-4 format of timer output control register 1 (toc1) .......................................................................... 201 9-5 format of prescaler mode register (prm) ....................................................................................... 202 9-6 basic operation of timer register 1 (tm1) ....................................................................................... 204 9-7 tm1 clear operation by match with compare register (cm10) ...................................................... 205 9-8 tm1 clear operation when ce1 bit is cleared (0) .......................................................................... 206 9-9 compare operation (timer 1) ............................................................................................................. 208 9-10 clearing tm1 after detection of match .............................................................................................. 209 9-11 block diagram of timer output operation of timer 1 ....................................................................... 210 9-12 operation of toggle output ................................................................................................................ 211 9-13 operation of set/reset output (timer 1) ............................................................................................ 212 list of figures (3/8) figure no. title page 24 user? manual u11515ej3v0ud 9-14 timing of interval timer operation (1) ............................................................................................... 213 9-15 control register settings for interval timer operation (1) ............................................................... 214 9-16 setting procedure of interval timer operation (1) ............................................................................ 215 9-17 interrupt request processing of interval timer operation (1) .......................................................... 215 9-18 timing of interval timer operation (2) ............................................................................................... 216 9-19 control register settings for interval timer operation (2) ............................................................... 217 9-20 setting procedure of interval timer operation (2) ............................................................................ 217 9-21 operation when counting is started ................................................................................................. 218 9-22 operation when compare register (cm10, cm11) is set to 0000h .............................................. 220 10-1 block diagram of timer/counter 2 ..................................................................................................... 224 10-2 format of timer unit mode register 2 (tum2) ................................................................................. 226 10-3 format of timer mode control register 2 (tmc2) ........................................................................... 227 10-4 format of timer output control register 2 (toc2) .......................................................................... 228 10-5 format of prescaler mode register 2 (prm2) .................................................................................. 229 10-6 basic operation of timer register 2 (tm2) ....................................................................................... 231 10-7 tm2 clear operation by match with compare register (cm20/cm21) .......................................... 232 10-8 tm2 clear operation when ce2 bit is cleared (0) .......................................................................... 233 10-9 timing of timer/counter 2 external event count ............................................................................. 234 10-10 compare operation (timer/counter 2) ................................................................................................ 237 10-11 tm2 clearance after match detection ............................................................................................... 238 10-12 operation of toggle output ................................................................................................................ 239 10-13 pwm pulse output ............................................................................................................................. 24 1 10-14 example of pwm output using tm2 ................................................................................................. 242 10-15 example of pwm output when cm20 = ffffh .............................................................................. 242 10-16 example of compare register (cm20) rewrite ................................................................................ 243 10-17 example of 100 % duty with pwm output ....................................................................................... 244 10-18 when timer/counter 2 is stopped during pwm signal output ....................................................... 245 10-19 example of ppg output using tm2 .................................................................................................. 247 10-20 example of compare register (cm20) rewrite ................................................................................ 248 10-21 example of 100 % duty with ppg output ........................................................................................ 249 10-22 example of extended ppg output cycle .......................................................................................... 250 10-23 when timer/counter 2 is stopped during ppg signal output ........................................................ 251 10-24 timing of interval timer operation (1) ............................................................................................... 252 10-25 control register settings for interval timer operation (1) ............................................................... 253 10-26 setting procedure of interval timer operation (1) ............................................................................ 254 10-27 interrupt request processing of interval timer operation (1) .......................................................... 254 10-28 timing of interval timer operation (2) ............................................................................................... 255 10-29 control register settings for interval timer operation (2) ............................................................... 256 10-30 setting procedure of interval timer operation (2) ............................................................................ 257 10-31 example of timer/counter 2 pwm signal output ............................................................................. 258 10-32 control register settings for pwm output operation ...................................................................... 259 10-33 setting procedure of pwm output ..................................................................................................... 260 list of figures (4/8) figure no. title page 25 user? manual u11515ej3v0ud 10-34 changing pwm output duty .............................................................................................................. 261 10-35 example of timer/counter 2 ppg signal output .............................................................................. 262 10-36 control register settings for ppg output operation ........................................................................ 263 10-37 setting procedure of ppg output ...................................................................................................... 265 10-38 changing ppg output duty ............................................................................................................... 266 10-39 external event counter operation ..................................................................................................... 267 10-40 control register settings for external event counter operation ..................................................... 268 10-41 setting procedure of external event counter operation .................................................................. 268 10-42 operation when counting is started ................................................................................................. 269 10-43 operation when compare register (cm20, cm21) is set to 0000h .............................................. 270 11-1 block diagram of timer 4 ................................................................................................................... 272 11-2 format of timer mode control register 4 (tmc4) ........................................................................... 274 11-3 format of prescaler mode register 4 (prm4) .................................................................................. 275 11-4 basic operation of timer register 4 (tm4) ....................................................................................... 277 11-5 tm4 clear operation by match with compare register (cm40, cm41) .......................................... 278 11-6 clear operation of tm4 when ce4 bit is cleared (0) ...................................................................... 279 11-7 compare operation (timer 4) ............................................................................................................. 281 11-8 tm4 clearance after match detection ............................................................................................... 281 11-9 timing of interval timer operation (1) ............................................................................................... 282 11-10 set contents of control registers for interval timer operation (1) ................................................. 283 11-11 setting procedure of interval timer operation (1) ............................................................................ 284 11-12 interrupt request processing of interval timer operation (1) .......................................................... 284 11-13 timing of interval timer operation (2) ............................................................................................... 285 11-14 set contents of control register for interval timer operation (2) ................................................... 286 11-15 setting procedure of interval timer operation (2) ............................................................................ 286 11-16 operation when count starts ............................................................................................................ 287 11-17 operation when compare register (cm40, cm41) is set to 0000h .............................................. 288 12-1 block diagram of watchdog timer ..................................................................................................... 289 12-2 format of watchdog timer mode register (wdm) ........................................................................... 291 13-1 block diagram of a/d converter ........................................................................................................ 295 13-2 example of capacitor connection on a/d converter pins ............................................................... 296 13-3 format of a/d converter mode register (adm) ............................................................................... 299 13-4 word access to a/d conversion result register ............................................................................. 301 13-5 byte access to a/d conversion result register ............................................................................... 302 13-6 basic operation of a/d converter ...................................................................................................... 304 13-7 relationship between analog input voltage and a/d conversion result ........................................ 305 13-8 operating timing in select mode (1-buffer mode) ............................................................................ 307 13-9 operation timing in select mode (4-buffer mode) ............................................................................ 309 13-10 operation timing in scan mode ......................................................................................................... 310 13-11 a/d conversion in select mode (1-buffer mode) started by software ............................................. 311 list of figures (5/8) figure no. title page 26 user? manual u11515ej3v0ud 13-12 a/d conversion in select mode (4-buffer mode) started by software ............................................. 312 13-13 a/d conversion in scan mode started by software ......................................................................... 312 13-14 a/d conversion in select mode (1-buffer mode) started by hardware ........................................... 313 13-15 a/d conversion in select mode (4-buffer mode) started by hardware ........................................... 314 13-16 a/d conversion in scan mode started by hardware ........................................................................ 315 13-17 example of capacitor connection on a/d converter pins ............................................................... 317 14-1 switching between asynchronous serial interface mode and 3-wire serial i/o mode .................. 319 14-2 block diagram of asynchronous serial interface .............................................................................. 321 14-3 formats of asynchronous serial interface mode register (asim) and asynchronous serial interface mode register 2 (asim2) ................................................................ 324 14-4 formats of asynchronous serial interface status register (asis) and asynchronous serial interface status register 2 (asis2) ............................................................... 326 14-5 data format of asynchronous serial interface transmit/receive .................................................... 327 14-6 interrupt timing of asynchronous serial interface transmission completion .................................. 329 14-7 interrupt timing of asynchronous serial interface reception completion ...................................... 330 14-8 timing of receive error ...................................................................................................................... 331 14-9 transmission/reception with macro service ..................................................................................... 334 14-10 example of 3-wire serial i/o system configuration ......................................................................... 335 14-11 block diagram of 3-wire serial i/o mode ......................................................................................... 336 14-12 formats of clocked serial interface mode register 1 (csim1) and clocked serial interface mode register 2 (csim2) .......................................................................... 338 14-13 timing of 3-wire serial i/o mode ...................................................................................................... 339 14-14 example of connection to 2-wire serial i/o ..................................................................................... 340 14-15 block diagram of baud rate generator ............................................................................................ 345 14-16 formats of baud rate generator control register (brgc) and baud rate generator control register 2 (brgc2) .......................................................................... 347 15-1 format of external interrupt mode register 0 (intm0) .................................................................... 360 15-2 format of external interrupt mode register 1 (intm1) .................................................................... 361 15-3 format of interrupt valid edge flag register 1 (ief1) ..................................................................... 362 15-4 format of interrupt valid edge flag register 2 (ief2) ..................................................................... 363 15-5 format of noise protection control register (npc) ......................................................................... 364 15-6 edge detection for pin p20 ................................................................................................................ 365 15-7 edge detection for pins p21 to p27 .................................................................................................. 366 16-1 interrupt control registers ( icn) .................................................................................................... 377 16-2 format of interrupt mask registers (mk0, mk1) .............................................................................. 382 16-3 format of in-service priority register (ispr) ................................................................................... 383 16-4 format of interrupt mode control register (imc) ............................................................................. 384 16-5 format of watchdog timer mode register (wdm) ........................................................................... 385 16-6 format of program status word (pswl) .......................................................................................... 386 16-7 context switching operation by execution of a brkcs instruction ................................................ 387 list of figures (6/8) figure no. title page 27 user? manual u11515ej3v0ud 16-8 return from brkcs instruction software interrupt (retcsb instruction operation) .................... 388 16-9 operations of non-maskable interrupt request acknowledgment ................................................... 390 16-10 algorithm of interrupt acknowledgment processing ......................................................................... 394 16-11 context switching operation by generation of an interrupt request .............................................. 395 16-12 return from interrupt that uses context switching by means of retcs instruction ..................... 396 16-13 examples of processing when another interrupt request is generated during interrupt processing ......................................................................................... 398 16-14 examples of processing of simultaneously generated interrupts ................................................... 401 16-15 differences in level 3 interrupt acknowledgment according to setting of interrupt mode control register (imc) ......................................................................... 402 16-16 differences between vectored interrupt and macro service processing ......................................... 403 16-17 example of macro service processing sequence ............................................................................ 407 16-18 operation on completion of macro service ...................................................................................... 408 16-19 basic configuration of macro service control word ......................................................................... 409 16-20 format of macro service control word ............................................................................................. 410 16-21 interrupt request generation and acknowledgment (unit: clocks) ................................................. 425 17-1 format of memory expansion mode register (mm) ......................................................................... 432 17-2 pd784044 memory map ................................................................................................................... 433 17-3 pd784046 memory map ................................................................................................................... 435 17-4 read timing (8 bits) ........................................................................................................................... 437 17-5 write timing (8 bits) ........................................................................................................................... 437 17-6 read timing (16 bits, even address access) ................................................................................... 438 17-7 write timing (16 bits, even address access) ................................................................................... 438 17-8 read timing (16 bits, odd address access) .................................................................................... 439 17-9 write timing (16 bits, odd address access) .................................................................................... 439 17-10 format of memory extension mode register (mm) .......................................................................... 440 17-11 format of programmable wait control register 1 (pwc1) .............................................................. 442 17-12 format of programmable wait control register 2 (pwc2) .............................................................. 444 17-13 read/write timing of address wait function .................................................................................... 446 17-14 format of port 9 mode control register (pmc9) .............................................................................. 449 17-15 wait control spaces ........................................................................................................................... 450 17-16 read timing of access wait function ............................................................................................... 451 17-17 write timing of access wait function ............................................................................................... 453 17-18 timing with external wait signal ........................................................................................................ 455 17-19 format of bus width specification register (bw) ............................................................................ 457 18-1 diagram of standby mode transition ................................................................................................. 459 18-2 diagram of standby function block ................................................................................................... 460 18-3 standby control register (stbc) format ......................................................................................... 461 18-4 format of oscillation stabilization time specification register (osts) .......................................... 463 18-5 stop mode release by nmi input .................................................................................................... 468 18-6 example of address/data bus processing ........................................................................................ 472 list of figures (7/8) figure no. title page 28 user? manual u11515ej3v0ud 19-1 acknowledgment of reset signal ...................................................................................................... 474 19-2 power-on reset operation ................................................................................................................ 474 19-3 timing on reset input ........................................................................................................................ 475 20-1 selecting format of communication mode ........................................................................................ 478 20-2 connecting flashpro ii/flashpro iii in 3-wire serial i/o mode ........................................................ 479 20-3 connecting flashpro ii/flashpro iii in uart mode .......................................................................... 480 a-1 development tool configuration ........................................................................................................ 558 a-2 distance between in-circuit emulator and conversion socket ........................................................ 565 a-3 target system connection conditions ............................................................................................... 566 a-4 dimensions of ev-9200gc-80 (reference) ........................................................................................ 567 a-5 recommended board mounting pattern of ev-9200gc-80 (reference) .......................................... 568 list of figures (8/8) figure no. title page 29 user? manual u11515ej3v0ud list of tables (1/3) table no. title page 1-1 differences between pd784044, 784046, and 78f4046 ................................................................ 41 1-2 differences between pd784046 and pd784046(a) ...................................................................... 41 1-3 differences between pd784046(a), 784046(a1), and 784046(a2) ............................................... 41 2-1 operation mode of port 0 ................................................................................................................... 46 2-2 operation mode of port 1 ................................................................................................................... 46 2-3 operation mode of port 2 ................................................................................................................... 47 2-4 operation mode of port 3 ................................................................................................................... 48 2-5 operation mode of port 9 ................................................................................................................... 50 2-6 i/o circuit type of each pin and recommended processing of unused pins ................................ 53 3-1 internal rom area .............................................................................................................................. 5 9 3-2 vector table ............................................................................................................................... .......... 61 3-3 internal ram area .............................................................................................................................. 6 3 3-4 register bank selection ..................................................................................................................... 70 3-5 correspondence between function names and absolute names ................................................... 81 3-6 special function registers (sfrs) list ............................................................................................. 83 5-1 port function ............................................................................................................................... ........ 99 5-2 operation mode of port 0 ................................................................................................................... 100 5-3 port 1 operating modes ..................................................................................................................... 106 5-4 operation mode of port 2 ................................................................................................................... 112 5-5 port 3 operating modes ..................................................................................................................... 119 5-6 operation mode of port 4 ................................................................................................................... 128 5-7 operation mode of port 5 ................................................................................................................... 134 5-8 operation mode of port 6 ................................................................................................................... 140 5-9 operation mode of port 9 ................................................................................................................... 147 5-10 operation mode of p90 through p93 ................................................................................................. 150 7-1 operations of timer/counters ............................................................................................................ 166 8-1 interval time of timer 0 ...................................................................................................................... 170 8-2 pulse width measurement range of timer 0 .................................................................................... 171 8-3 interrupt request signal from compare register (timer 0) .............................................................. 180 8-4 operation mode of timer output pin (timer 0) .................................................................................. 180 8-5 capture trigger signal to capture register (timer 0) ....................................................................... 182 8-6 toggle signal of timer output pin (timer 0) ...................................................................................... 184 8-7 set/reset signal of timer output pin (timer 0) ................................................................................. 184 8-8 toggle output of to00 through to03 (f clk = 16 mhz) ..................................................................... 187 9-1 interval time of timer 1 ...................................................................................................................... 197 9-2 interrupt request signal from compare register (timer 1) .............................................................. 207 9-3 operation mode of timer output pin (timer 1) .................................................................................. 207 30 user? manual u11515ej3v0ud 9-4 toggle signal of timer output pin (timer 1) ...................................................................................... 210 9-5 set/reset signal of timer output pin (timer 1) ................................................................................. 210 9-6 toggle output of to10 and to11 (f clk = 16 mhz) ............................................................................ 211 10-1 differences in name between timer/counter 2 and timer/counter 3 ............................................. 221 10-2 interval time of timer/counter 2 ........................................................................................................ 222 10-3 programmable square wave output range of timer/counter 2 ..................................................... 222 10-4 clock that can be input to timer/counter 2 .................................................................................... 223 10-5 interrupt request signal from compare register (timer/counter 2) ................................................ 236 10-6 interrupt request signal from compare register (timer/counter 3) ................................................ 236 10-7 toggle output of to20 and to21 (f clk = 16 mhz) ............................................................................ 240 10-8 pwm cycle of to20 and to21 (f clk = 16 mhz) ............................................................................... 241 10-9 setting ppg output (timer/counter 2) ................................................................................................ 246 10-10 setting ppg output (timer/counter 3) ................................................................................................ 246 10-11 ppg output of to20 and to21 (f clk = 16 mhz) ............................................................................... 247 11-1 interval time of timer 4 ...................................................................................................................... 271 11-2 interrupt request signal from compare register (timer 4) .............................................................. 280 13-1 conversion time set by fr bit .......................................................................................................... 300 13-2 time of a/d conversion ...................................................................................................................... 306 13-3 correspondence between analog input and a/d conversion result register (select mode: 1-buffer mode) ............................................................................................................. 307 13-4 correspondence between analog input and a/d conversion result register (select mode: 4-buffer mode) ............................................................................................................. 308 13-5 correspondence between analog input and a/d conversion result register (scan mode) .......... 310 14-1 differences between uart/ioe1 and uart2/ioe2 names ............................................................ 318 14-2 causes of receive error .................................................................................................................... 331 14-3 methods of baud rate setting ........................................................................................................... 350 14-4 examples of brgc settings when baud rate generator is used ................................................. 351 14-5 examples of settings when external baud rate input (asck) is used ......................................... 352 15-1 pins p20 to p27 and use of detected edge ..................................................................................... 359 16-1 processing modes of interrupt request ............................................................................................ 368 16-2 sources of interrupt request ............................................................................................................. 369 16-3 control registers ............................................................................................................................... . 373 16-4 interrupt control register flags corresponding to interrupt sources ............................................. 374 16-5 multiple interrupt processing .............................................................................................................. 397 16-6 interrupts for which macro service can be used ............................................................................ 404 16-7 classification of macro service mode ............................................................................................... 411 16-8 specifying operation of counter mode .............................................................................................. 412 list of tables (2/3) table no. title page 31 user? manual u11515ej3v0ud 16-9 specifying operation in block transfer mode .................................................................................... 413 16-10 specifying operation in block transfer mode (with memory pointer) .............................................. 415 16-11 interrupt acceptance processing time .............................................................................................. 426 16-12 macro service processing time ........................................................................................................ 427 18-1 operating states in halt mode ......................................................................................................... 464 18-2 halt mode release and operations after release ......................................................................... 465 18-3 operating states in stop mode ........................................................................................................ 467 18-4 stop mode release and operations after release ........................................................................ 468 18-5 operating states in idle mode ......................................................................................................... 469 18-6 idle mode release and operations after release .......................................................................... 470 19-1 pin status during reset input and after clearing reset ................................................................... 475 19-2 state of hardware after reset ............................................................................................................ 476 20-1 communication modes ....................................................................................................................... 478 20-2 major functions of flash memory programming. ............................................................................. 479 21-1 list of instructions by 8-bit addressing ............................................................................................. 512 21-2 list of instructions by 16-bit addressing ........................................................................................... 514 21-3 list of instructions by 24-bit addressing ........................................................................................... 516 21-4 list of instructions by bit manipulation instruction addressing ........................................................ 516 21-5 list of instructions by call/return instruction / branch instruction addressing ............................... 517 29-1 surface mounting type soldering conditions .................................................................................... 554 list of tables (3/3) table no. title page 32 user? manual u11515ej3v0ud chapter 1 general the pd784046 subseries comprises 78k/iv series products that incorporates 10-bit a/d converter. the 78k/iv series comprises 16-bit single-chip microcontrollers equipped with a high-performance cpu that has a function such as accessing a 1m-byte memory space. the following nine models are available in the pd784046 subseries: standard models : pd784044, 784046, 78f4046 special models : pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2) the pd784046 incorporates 64k-byte mask rom and 2048-byte ram, plus high-performance timer/counters, a 10-bit a/d converter, two independent serial interface channels, etc. the pd784044 is a version of the pd784046 with 32k-byte mask rom, and with 1024-byte ram. the pd78f4046 has on-chip flash memory instead of the mask rom of the pd784046. the pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), and 784046(a2) are the ?pecial?quality versions of the pd784044 and 784046. pd78f4046 pd784046 784046(a), (a1), (a2) pd784044 784044(a), (a1), (a2) on-chip flash memory product on-chip mask rom products these products can be used in the following application areas: [standard models] water heaters, vending machines fa field such as robots, and automatic machine tools [special models] control units of automotive appliances rom 32 k ram 1024 rom 64 k ram 2048 flash memory 64 k ram 2048 33 chapter 1 general user? manual u11515ej3v0ud 78k/iv series product lineup pd784026 pd784956a pd784908 pd784915 pd784928 pd784928y pd784046 pd784054 pd784216a pd784216ay pd784038 pd784038y pd784225y pd784225 pd784218ay pd784218a enhanced a/d converter, 16-bit timer, and power management enhanced internal memory capacity pin-compatible with the pd784026 supports i 2 c bus supports multimaster i 2 c bus 80-pin, rom correction added supports multimaster i 2 c bus enhanced internal memory capacity, rom correction added 100-pin, enhanced i/o and internal memory capacity on-chip 10-bit a/d converter for dc inverter control on-chip iebus tm controller software servo control on-chip analog circuit for vcrs enhanced timer supports multimaster i 2 c bus enhanced functions of the pd784915 standard models assp models supports multimaster i 2 c bus : products in mass-production pd784976a on-chip vfd controller/driver pd784938a enhanced functions of the pd784908, enhanced internal memory capacity, rom correction added. remark vfd (vacuum florescent display) is referred to as fip tm (florescent indicator panel) in some documents, but the functions of the two are the same. 34 chapter 1 general user s manual u11515ej3v0ud 1.1 features 78k/iv series minimum instruction execution time: 125 ns (at internal 16-mhz) internal memory rom mask rom : 64k bytes ( pd784046) 32k bytes ( pd784044) flash memory : 64k bytes ( pd78f4046) ram : 2048 bytes ( pd784046, 78f4046) 1024 bytes ( pd784044) i/o port: 65 pins timer/counter : 16-bit timer/counter unit x 2 units 16-bit timer x 3 units watchdog timer: 1 channel a/d converter: 10-bit resolution x 16 channels (av dd = 4.5 to 5.5 v) serial interface uart/ioe (3-wire serial i/o): 2 channels (with baud rate generator) interrupt controller (4 priority levels) vectored interrupt/macro service/context switching standby function halt/stop/idle mode supply voltage: v dd = 4.5 to 5.5 v 35 chapter 1 general user? manual u11515ej3v0ud 1.2 ordering information part number package internal rom pd784044gc- -3b9 80-pin plastic qfp (14 x 14) mask rom pd784046gc- -3b9 80-pin plastic qfp (14 x 14) mask rom pd78f4046gc-3b9 80-pin plastic qfp (14 x 14) flash memory pd784044gc(a)- -3b9 80-pin plastic qfp (14 x 14) mask rom pd784044gc(a1)- -3b9 80-pin plastic qfp (14 x 14) mask rom pd784044gc(a2)- -3b9 80-pin plastic qfp (14 x 14) mask rom pd784046gc(a)- -3b9 80-pin plastic qfp (14 x 14) mask rom pd784046gc(a1)- -3b9 80-pin plastic qfp (14 x 14) mask rom pd784046gc(a2)- -3b9 80-pin plastic qfp (14 x 14) mask rom remark indicates rom code suffix. 1.3 quality grades part number package internal rom pd784044gc- -3b9 80-pin plastic qfp (14 14) standard pd784046gc- -3b9 80-pin plastic qfp (14 14) standard pd78f4046gc-3b9 80-pin plastic qfp (14 14) standard pd784044gc(a)- -3b9 80-pin plastic qfp (14 14) special pd784044gc(a1)- -3b9 80-pin plastic qfp (14 14) special pd784044gc(a2)- -3b9 80-pin plastic qfp (14 14) special pd784046gc(a)- -3b9 80-pin plastic qfp (14 14) special pd784046gc(a1)- -3b9 80-pin plastic qfp (14 14) special pd784046gc(a2)- -3b9 80-pin plastic qfp (14 14) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of quality grade on the devices and its recommended applications. 36 chapter 1 general user? manual u11515ej3v0ud 1.4 pin configuration (top view) 80-pin plastic qfp (14 x 14) pd784044gc- -3b9, 784044gc(a)- -3b9, 784044gc(a1)- -3b9, 784044gc(a2)- -3b9 pd784046gc- -3b9, 784046gc(a)- -3b9, 784046gc(a1)- -3b9, 784046gc(a2)- -3b9 pd78f4046gc-3b9 note v pp is provided to the pd78f4046 only. caution do not directly connect the mode/v pp pin to v ss in the normal operation mode. p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 av ref av dd v ss v dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p22/intp1/to01 bwd p21/intp0/to00 mode/v pp note p20/nmi v ss v dd p13/to31 p12/to30 p11/to21 p10/to20 p03/rtp3 p02/rtp2 p01/rtp1 p00/rtp0 p37/asck2/sck2 p36/txd2/so2 p35/rxd2/si2 p34/asck/sck1 p33/txd/so1 p50/ad8 p51/ad9 p52/ad10 p53/ad11 p54/ad12 p55/ad13 p56/ad14 p57/ad15 p60/a16 p61/a17 p62/a18 p63/a19 p90/rd p91/lwr p92/hwr p93/astb p94/wait p30/to10 p31/to11 p32/rxd/si1 p87/ani15 p86/ani14 p85/ani13 p84/ani12 p83/ani11 p82/ani10 p81/ani9 p80/ani8 av ss v dd x2 x1 v ss clkout p27/intp6/ti3 p26/intp5/ti2 p25/intp4 p24/intp3/to03 reset p23/intp2/to02 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 37 chapter 1 general user s manual u11515ej3v0ud a16-a19 : address bus ad0-ad15 : address/data bus ani0-ani15 : analog input asck, asck2 : asynchronous serial clock astb : address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground bwd : bus width definition clkout : clock out hwr : high address write strobe intp0-intp6 : interrupt from peripherals lwr : low address write strobe mode : mode nmi : non-maskable interrupt p00-p03 : port 0 p10-p13 : port 1 p20-p27 : port 2 p30-p37 : port 3 p40-p47 : port 4 p50-p57 : port 5 p60-p63 : port 6 p70-p77 : port 7 p80-p87 : port 8 p90-p94 : port 9 rd : read strobe reset : reset rtp0-rtp3 : real-time port rxd, rxd2 : receive data sck1, sck2 : serial clock si1, si2 : serial input so1, so2 : serial output ti2, ti3 : timer input to00-to03, to10, to11, to20, to21, to30, to31 : timer output txd, txd2 : transmit data v dd : power supply v pp : programming power supply v ss : ground wait : wait x1, x2 : crystal 38 chapter 1 general user s manual u11515ej3v0ud 1.5 system configuration example (ac servo motor control) uart 3-wire serial i/o wdt pd784046 control panel display keypad i/o port external tester i/o interface circuit cpu-to-cpu communication rom 64 k bytes ram 2048 bytes macro service function port intp0-intp4 ani8-ani15 to10, to11, to20, to21 port ani0-ani7 intp5 ad0-ad15 limit switch driver/switching circuit current/voltage sensor signal input circuit ac motor rotary encoder rotary encoder interface encoder pulse counter 39 chapter 1 general user s manual u11515ej3v0ud 1.6 block diagram note v pp is only for pd78f4046. remark the internal rom and ram capacities differ depending on the products. programmable interrupt controller intp0-intp6 nmi to00-to03 intp0-intp3 to10, to11 a/d converter av dd av ss av ref intp4 ani0-ani15 watchdog timer timer 4 (16 bits) timer 1 (16 bits) timer 0 (16 bits) 78k/iv cpu core rom ram bus i/f bwd ad0-ad15 a16-a19 rd lwr, hwr astb wait clkout reset mode/v pp note x1 x2 system control p00-p03 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 p10-p12 p20 p21-p27 v dd v ss p30-p37 p40-p47 p50-p57 p60-p63 p70-p77 p80-p87 p90-p94 baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 txd/so1 rxd/si1 asck/sck1 txd2/so2 rxd2/si2 asck2/sck2 timer/counter2 (16 bits) to20, to21 intp5/ti2 to30, to31 intp6/ti3 rtp0-rtp3 real-time output port timer/counter3 (16 bits) 40 chapter 1 general user s manual u11515ej3v0ud 1.7 list of functions item part number pd784044 pd784046 pd78f4046 number of basic instructions 113 (mnemonics) general-purpose register 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time 125 ns (at internal 16 mhz operation) internal rom 32 kb 64 kb 64 kb memory (mask rom) (mask rom) (flash memory) ram 1024 b 2048 b memory space 1 mb with program and data memories combined i/o port total 65 lines input 17 lines i/o 48 lines pins with ancillary pin with pull- 29 pins functions note up resistor real-time output port 4 bits 1 timer/counter timer 0 (16 bits) : timer register 1 pulse output capture/compare register 4 toggle output set/reset output timer 1 (16 bits) : timer register 1 pulse output compare register 2 toggle output set/reset output timer/counter 2 (16 bits) : timer register 1 pulse output compare register 1 toggle output pwm/ppg output timer/counter 3 (16 bits) : timer register 1 pulse output compare register 2 toggle output pwm/ppg output a/d converter 10-bit resolution 16 channels (av dd = 4.5 to 5.5 v) serial interface uart/ioe (3-wire serial i/o): 2 channels (with baud rate generator) watchdog timer 1 channel interrupt hardware source 27 (internal: 23, external: 8 (shared with internal: 4) software source brk instruction, brkcs instruction, operand error non-maskable internal : 1, external : 1 maskable internal : 22, external: 7 (shared with internal: 4) 4 priority levels three processing formats: vectored interrupt/macro service/context switching bus sizing 8 bits/16 bits external data bus width selectable standby halt/stop/idle mode supply voltage v dd = 4.5 to 5.5 v package 80-pin plastic qfp (14 x 14) note the pins with ancillary functions are included in the i/o pins. 41 chapter 1 general user s manual u11515ej3v0ud 1.8 differences between the only difference between the pd784044 and pd784046 is the internal memory capacity. the pd78f4046 is a version of the pd784046 with internal rom replaced by a flash memory. the differences are shown in table 1-1. table 1-1. differences between part number pd784044 pd784046 pd78f4046 item internal rom 32k bytes 64k bytes 64k bytes (mask rom) (mask rom) (flash memory) internal ram 1024 bytes 2048 bytes function of pin 57 mode mode/v pp 1.9 differences between part number pd784044, 784046, 78f4046 pd784044(a), 784046(a) item quality grade standard special operating ambient temperature (t a ) 10 to +70 c 40 to +85 c operating frequency 8 to 32 mhz 8 to 25 mhz minimum instruction execution time 125 ns (operates at 16 mhz internally) 160 ns (operates at 12.5 mhz internally) dc characteristics v dd supply current differs. ac characteristics bus timing and serial operation differ. a/d converter characteristics conversion time and sampling time differ. 1.10 differences between part number pd784046(a) pd784046(a1) pd784046(a2) item operating ambient temperature (t a ) 40 to +85 c 40 to +110 c 40 to +125 c operating frequency 8 to 25 mhz 8 to 20 mhz minimum instruction execution time 160 ns (operates at 200 ns (operates at 10 mhz internally) 12.5 mhz internally) dc characteristics analog pin input leakage current, v dd supply current, and data retention current differ. ac characteristics bus timing and serial operation differ. a/d converter characteristics av ref current, a/d converter data retention current differ. remark the differences between the pd784044(a), 784044(a1), and 784044(a2) are the same as those in the table shown above. 42 user? manual u11515ej3v0ud chapter 2 pin functions 2.1 list of pin functions (1) port (1/2) pin name i/o dual-function pins function p00-p03 i/o port 0 (p0): 4-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once by software settings. p10 i/o to20 port 1 (p1): p11 to21 4-bit i/o port p12 to30 can be set in input/output mode bit-wise. p13 to31 p20 input nmi port 2 (p2): input only p21 i/o intp0/to00 8-bit i/o port can be set in input/output mode p22 intp1/to01 bit-wise. p23 intp2/to02 p24 intp3/to03 p25 intp4 p26 intp5/ti2 p27 intp6/ti3 p30 i/o to10 port 3 (p3): p31 to11 8-bit i/o port p32 rxd/si1 can be set in input/output mode bit-wise. p33 txd/so1 p34 asck/sck1 p35 rxd2/si2 p36 txd2/so2 p37 asck2/sck2 p40-p47 i/o ad0-ad7 port 4 (p4): 8-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once by software settings. p50-p57 i/o ad8-ad15 port 5 (p5): 8-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once by software settings. p60-p63 i/o a16-a19 port 6 (p6): 4-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once by software settings. 43 chapter 2 pin functions user? manual u11515ej3v0ud (1) port (2/2) pin name i/o dual-function pins function p70-p77 input ani0-ani7 port 7 (p7): 8-bit input port p80-p87 input ani8-ani15 port 8 (p8): 8-bit input port p90 i/o rd port 9 (p9): p91 lwr 5-bit i/o port p92 hwr can be set in input/output mode bit-wise. p93 astb pins in input mode can all be connected to pull-up resistors at once p94 wait by software settings. 44 chapter 2 pin functions user? manual u11515ej3v0ud (2) pins other than port pins (1/2) pin name i/o dual-function pins function rtp0-rtp3 output p00 to p03 real-time output nmi input p20 non-maskable interrupt request input intp0 p21/to00 external interrupt capture trigger signal of cc00 intp1 p22/to01 request input capture trigger signal of cc01 intp2 p23/to02 capture trigger signal of cc02 intp3 p24/to03 capture trigger signal of cc03 intp4 p25 conversion start trigger input of a/d converter intp5 p26/ti2 intp6 p27/ti3 to00 output p21/intp0 timer output from timer/counter to01 p22/intp1 to02 p23/intp2 to03 p24/intp3 to10 p30 to11 p31 to20 p10 to21 p11 to30 p12 to31 p13 ti2 input p26/intp5 external count clock input to timer/counter 2 ti3 p27/intp6 external count clock input to timer/counter 3 rxd input p32/si1 serial data input (uart0) rxd2 p35/si2 serial data input (uart2) txd output p33/so1 serial data output (uart0) txd2 p36/so2 serial data output (uart2) asck input p34/sck1 baud rate clock input (uart0) asck2 p37/sck2 baud rate clock input (uart2) si1 input p32/rxd serial data input (3-wire serial i/o1) si2 p35/rxd2 serial data input (3-wire serial i/o2) so1 output p33/txd serial data output (3-wire serial i/o1) so2 p36/txd2 serial data output (3-wire serial i/o2) sck1 i/o p34/asck serial clock input/output (3-wire serial i/o1) sck2 p37/asck2 serial clock input/output (3-wire serial i/o2) ad0-ad7 i/o p40 to p47 lower multiplexed address/data bus when external memory is connected ad8-ad15 note i/o p50 to p57 when 8-bit bus is specified higher address bus when external memory is connected when external 16-bit bus is specified higher multiplexed address/data bus when external memory is connected a16-a19 note output p60 to p63 higher address bus when external memory is connected rd output p90 read strobe to external memory note the number of pins used as address bus pins differs depending on the external address space (refer to chapter 17 local bus interface function ). 45 chapter 2 pin functions user? manual u11515ej3v0ud (2) pins other than port pins (2/2) pin name i/o dual-function pins function lwr output p91 when external 8-bit bus is specified write strobe to external memory when external 16-bit bus is specified write strobe to external memory located at lower position hwr p92 write strobe to external memory located at higher position when external 16-bit bus is specified astb output p93 timing signal output to externally latch address information output from ad0 through ad15 pins to access external memory wait input p94 inserts wait. bwd input sets bus width. mode input v pp note directly connect this pin to v ss in normal operating mode (this pin specifies test mode of ic). clkout output clock output. low level is output in the idle mode or stop mode, otherwise f xx (oscillation frequency) is always output. x1 input connect crystal for system clock oscillation (clock can be also input to x1). x2 reset input chip reset ani0-ani7 input p70 to p77 analog voltage input for a/d converter ani8-ani15 p80 to p87 av ref reference voltage for a/d converter av dd positive power for a/d converter av ss gnd for a/d converter v dd positive power v pp note input mode sets flash memory programming mode. applies high voltage when program is written/verified. v ss gnd note v pp is only for the pd78f4046. 46 chapter 2 pin functions user? manual u11515ej3v0ud 2.2 description of pin functions (1) p00 through p03 (port 0) ... 3-state i/o port 0 is a 4-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 0 mode register (pm0). each pin of this port is provided with a software programmable pull-up resistor. in addition to the i/o port function, port 0 also functions as a 4-bit real-time output port and can output the contents of port 0 buffer register (p0l) at any interval time. whether port 0 is used as a normal output port or real-time output port is specified by real-time output port control register (rtpc). when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 2-1. operation mode of port 0 pin name port mode real-time output port mode manipulation to use port 0 as real-time output port p00-p03 i/o port rtp0-rtp3 setting of p0ml bit of rtpc to 1 remark for details, refer to chapter 6 real-time output function . (2) p10 through p13 (port 1) ... 3-state i/o port 1 is a 4-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 1 mode register (pm1). in addition to the i/o port function, port 1 also functions as the timer output pins of timers/counters 2 and 3. the operation mode of this port is specified in 1-bit units by using port 1 mode control register (pmc1), as shown in table 2-2. the level of each pin can be read or tested regardless of the multiplexed function. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 2-2. operation mode of port 1 pin name port mode control signal output mode manipulation to use port 1 as control pins p10 i/o port to20 output setting of pmc10 bit of pmc1 to 1 p11 to21 output setting of pmc11 bit of pmc1 to 1 p12 to30 output setting of pmc12 bit of pmc1 to 1 p13 to31 output setting of pmc13 bit of pmc1 to 1 (a) port mode each pin of port 1 set in the port mode by the port 1 mode control register (pmc1) can be set in the input or output mode in 1-bit units by using the port 1 mode register (pm1). (b) control signal output mode the pins of port 1 can be used as control pins in 1-bit units if so specified by the port 1 mode control register (pmc1). (i) to20, to21 these pins are timer output pins of timer/counter 2. (ii) to30, to31 these pins are timer output pins of timer/counter 3. 47 chapter 2 pin functions user? manual u11515ej3v0ud (3) p20 through p27 (port 2) ... 3-state i/o port 2 is an 8-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 2 mode register (pm2) (however, p20 is input-only). in addition to the input/output port function, port 2 also functions as a control signal input pins such as for external interrupt signals, and to output the timer signal of timer 0 (refer to table 2-3 ). p21 through p24 serve as the timer output pins of timer 0 if so specified by port 2 mode control register (pmc2). the level of each pin of this port can always be read or tested regardless of the multiplexed function. all the eight pins are schmitt trigger input pins to prevent malfunctioning due to noise. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 2-3. operation mode of port 2 (n = 0 to 7) mode port mode control signal output mode set condition pmc2n = 0 pmc2n = 1 pm2n = 0 pm2n = 1 pm2n = p20 input port/nmi input note p21 output port input port/intp0 input to00 output p22 input port/intp1 input to01 output p23 input port/intp2 input to02 output p24 input port/intp3 input to03 output p25 input port/intp4 input p26 input port/intp5 input/ti2 input p27 input port/intp6 input/ti3 input note the nmi input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled. remark : don? care (a) port mode (i) function as port pin each port pin set in the port mode by the port 2 mode control register (pmc2) can be set in the input or output mode in 1-bit units by the port 2 mode register (pm2) (however, p20 is fixed in input only). (ii) function as control signal input pins if pmc2n (n = 0 to 7) bit of pmc2 is ??and if pm2n (n = 0 to 7) bit of pm2 is ?? the pins of port 2 can be used as the following control signal input pins. nmi (non-maskable interrupt) this pin inputs an external non-maskable interrupt request. whether the interrupt request is detected at the rising or falling edge can be specified by using external interrupt mode register 0 (intm0). 48 chapter 2 pin functions user? manual u11515ej3v0ud intp0 through intp6 (interrupt from peripherals) these pins input external interrupt requests. when the valid edge specified by external interrupt mode registers (intm0 and intm1) is detected on the intp0 to intp6 pins, an interrupt occurs (refer to chapter 15 edge detection function ). the intp0 through intp4 pins can also be used as external trigger input pins of each function, as follows: intp0 ... capture trigger input pin of capture/compare register 00 (cc00) of timer 0 intp1 ... capture trigger input pin of capture/compare register 01 (cc01) of timer 0 intp2 ... capture trigger input pin of capture/compare register 02 (cc02) of timer 0 intp3 ... capture trigger input pin of capture/compare register 03 (cc03) of timer 0 intp4 ... external trigger input pin of a/d converter (iii) ti2, ti3 (timer input) these are external clock input pins of timers/counters 2 and 3. (b) control signal output mode the p21 through p24 pins can be used as the timer output pins (to00 through to03) of timer 0 in 1-bit units if so specified by the port 2 mode control register (pmc2). (4) p30 through p37 (port 3) ... 3-state i/o port 3 is an 8-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 3 mode register (pm3). in addition to the input/output port function, port 3 also has a function to input or output control signals. the operation mode of each pin can be specified by using port 3 mode control register (pmc3), as shown in table 2- 4. the level of each pin of this port can always be read or tested regardless of the multiplexed function. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 2-4. operation mode of port 3 (n = 0 to 7) mode port mode control signal i/o mode setting condition pmc3n = 0 pmc3n = 1 p30 i/o port to10 output p31 to11 output p32 rxd/si1 input p33 txd/so1 output p34 asck input/sck1 i/o p35 rxd2/si2 input p36 txd2/so2 output p37 asck2 input/sck2 i/o 49 chapter 2 pin functions user? manual u11515ej3v0ud (a) port mode each port pin set in the port mode by the port 3 mode control register (pmc3) can be set in the input or output mode by the port 3 mode register (pm3). (b) control signal i/o mode each pin of port 3 can be set in the control mode in 1-bit units by using the port 3 mode control register (pmc3). (i) to10, to11 (timer output) these are timer output pins of timer 1. (ii) rxd, rxd2 (receive data) these are serial data input pins of the asynchronous serial interface. (iii) txd, txd2 (transmit data) these are serial data output pins of the asynchronous serial interface. (iv) si1, si2 (serial input) these are serial data input pins of the 3-wire serial i/o. (v) so1, so2 (serial output) these are serial data output pins of the 3-wire serial i/o. (vi) asck, asck2 (asynchronous serial clock) these are external baud rate clock input pins. (vii) sck1, sck2 (serial clock) these are serial clock i/o pins of the 3-wire serial i/o. (5) p40 through p47 (port 4) ... 3-state i/o port 4 is an 8-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 4 mode register (pm4). each pin is provided with a software programmable pull-up resistor. port 4 functions as the low-order multiplexed address/data bus (ad0 through ad7) if so specified by memory expansion mode register (mm) when an external memory or i/o is connected, in addition to the i/o port function. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. (6) p50 through p57 (port 5) ... 3-state i/o port 5 is an 8-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 5 mode register (pm5). each pin is provided with a software programmable pull-up resistor. this port functions as follows if so specified by memory expansion mode register (mm) when an external memory or i/o is connected: when external 8-bit bus is specified as the high-order address bus (ad8 through ad15) when external 16-bit bus is specified as the high-order multiplexed address/data bus (ad8 through ad15). when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. 50 chapter 2 pin functions user? manual u11515ej3v0ud (7) p60 through p63 (port 6) ... 3-state i/o port 6 is a 4-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 6 mode register (pm6). each pin is provided with a software programmable pull-up resistor. in addition to as an i/o port, this port also functions as the high-order address bus (a16 through a19) if so specified by the memory expansion mode register when an external memory or i/o is connected. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. (8) p70 through p77 (port 7) ... input port 7 is an 8-bit input port. in addition to as input port pins, its pins also function as an a/d converter analog input (low-order 8 channels) pins (ani0 through ani7), and can always input analog signals. this port is set in the analog input mode by using a/d converter mode register (adm). the level of each pin of this port can always be read or tested, regardless of the multiplexed function. (9) p80 through p87 (port 8) ... input port 8 is an 8-bit input port. in addition to functioning as input port pins, its pins also functions as an a/d converter analog input (high-order 8 channels) pins (ani8 through ani15), and can always input analog signals. this port is set in the analog input mode by using a/d converter mode register (adm). the level of each pin of this port can always be read or tested, regardless of the multiplexed function. (10) p90 through p94 (port 9) ... 3-state i/o port 9 is a 5-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 9 mode register (pm9). each pin is provided with a software programmable pull-up resistor. in addition to the i/o port function, port 9 also functions as control signal pins (refer to table 2-5 ). p90 through p93 function as read/write strobe signals and an address strobe signal if so specified by the memory extension mode register (mm) when an external memory or i/o is connected. p94 functions as a wait signal input pin if so specified by port 9 mode control register (pmc9). when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 2-5. operation mode of port 9 pin name port mode control signal i/o mode manipulation to use port 9 as control pins p90 i/o port rd specifying external memory expansion mode by p91 lwr mm0 through mm3 bits of mm p92 hwr p93 astb p94 wait setting of pmc94 bit of pmc9 to 1 remark for details, refer to chapter 17 local bus interface function . 51 chapter 2 pin functions user? manual u11515ej3v0ud (a) port mode each port pin not set in the control mode can be set in the input or output mode by using the port 9 mode register (pm9). (b) control signal i/o mode (i) rd (read strobe) this pin outputs a strobe signal to read an external memory. the operation of this pin is specified by the memory extension mode register (mm). (ii) lwr, hwr (low/high write strobe) these pins output strobe signals to write an external memory. the operations of these pins are specified by the memory extension mode register (mm). (iii) astb (address strobe) this is a timing signal output pin to latch the address information output from the ad0 through ad15 pins to access the external memory. the operation of this pin is specified by the memory extension mode register (mm). (iv) wait (wait) this pin inputs a wait signal. the operation of this pin is specified by the port 9 mode control register (pmc9). (11) bwd (bus width definition) ... input this pin specifies the width of the bus. depending on the setting of this pin, the value of the bus width specification register (bw) at reset differs as follows: bwd external bus width value of bw at reset 0 8 bits 0000h 1 16 bits 00ffh (12) mode (mode) ... input this pin is used by nec electronics for testing ic. be sure to directly connect this pin to v ss . (13) clkout (clock output) ... output clock output. low level is output in the idle mode or stop mode, otherwise f xx (oscillation frequency) is always output (14) x1, x2 (crystal) these pins are used to connect a crystal for internal clock oscillation. to supply an external clock, input the clock to the x1 pin. for the processing of the x2 pin at this time, refer to chapter 4 clock generator . (15) reset (reset) ... input active-low reset input (16) av ref (analog reference voltage) this pin inputs a reference voltage to the a/d converter. 52 chapter 2 pin functions user? manual u11515ej3v0ud (17) av dd (analog power supply) this is the power supply pin of the a/d converter. keep the potential at this pin same as that of the v dd pin. (18) av ss (analog ground) this is the gnd pin of the a/d converter. keep the potential at this pin same as that of the v ss pin. (19) v dd (power supply) this is a positive power supply. connect all the v dd pins to a positive power supply. (20) v pp note (programming power supply) this pin applies a flash memory programming voltage to the pd78f4046. if the input voltage of this pin is +5 v or higher, and the reset signal goes low, the pd78f4046 enters the flash memory programming mode. note v pp is provided on the pd78f4046 only. (21) v ss (ground) this is a gnd pin. ground all the v ss pins. 53 chapter 2 pin functions user? manual u11515ej3v0ud 2.3 i/o circuits of pins and processing of unused pins table 2-6 shows the i/o circuit type of each pin and recommended processing of the unused pins. for the i/o circuit type, refer to figure 2-1 . table 2-6. i/o circuit type of each pin and recommended processing of unused pins (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/rtp0-p03/rtp3 5-a i/o input: individually connect to v dd or v ss via resistor. p10 to p12 5 output: leave unconnected. p11/to21 p12/to30 p13/to31 p20/nmi 2 input connect to v ss . p21/intp0/to00 8 i/o input: individually connect to v dd or v ss via resistor. p22/intp1/to01 output: leave unconnected. p23/intp2/to02 p24/intp3/to03 p25/intp4 p26/intp5/ti2 p27/intp6/ti3 p30/to10 5 p31/to11 p32/rxd/si1 p33/txd/so1 p34/asck/sck1 8 p35/rxd2/si2 5 p36/txd2/so2 p37/asck2/sck2 8 p40/ad0-p47/ad7 5-a p50/ad8-p57/ad15 p60/a16-p63/a19 p70/ani0-p77/ani7 9 input connect to v ss . p80/ani8-p87/ani15 p90/rd 5-a i/o input: individually connect to v dd or v ss via resistor. p91/lwr output: leave unconnected. p92/hwr p93/astb p94/wait 54 chapter 2 pin functions user? manual u11515ej3v0ud table 2-6. i/o circuit type of each pin and recommended processing of unused pins (2/2) pin name i/o circuit type i/o recommended connection of unused pins bwd 1 input connect to v dd or v ss . mode directly connect to v ss . (mask rom product) mode/v pp (flash memory product) reset 2 clkout 3 output leave unconnected. av ref connect to v ss . av ss av dd connect to v dd . remark the circuit type numbers are serial in the 78k series but are not always so with some models (because some models are not provided with particular circuits). 55 chapter 2 pin functions user? manual u11515ej3v0ud figure 2-1. i/o circuits of pins type 2 schmitt trigger input with hysteresis characteristics type 1 p-ch in v dd n-ch in type 3 type 5 data output disable p-ch in/out v dd n-ch input enable type 5-a data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable type 8 data output disable p-ch in/out v dd n-ch in comparator + _ v ref (threshold voltage) p-ch n-ch input enable type 9 p-ch out v dd n-ch 56 user? manual u11515ej3v0ud chapter 3 cpu architecture 3.1 memory space the pd784046 can access a 1 m-byte memory space. the mapping of the internal data area (special function registers and internal ram) depends on the location instruction. a location instruction must be executed after reset release, and can only be used once. the program after reset release must be as follows: rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn (1) when location 0h instruction is executed the internal data area is mapped onto addresses 0f700h to 0ffffh in the pd784046, and onto addresses 0fb00h to 0ffffh in the pd784044. internal rom is mapped onto addresses 0 to 0f5ffh in the pd784046, and onto addresses 0 to 07fffh in the pd784044. the addresses 0f600h to 0ffffh of the 64 k-byte rom (00000h to 0ffffh) incorporated in the pd784046 cannot be used as rom when the location 0h instruction is executed. external memory is accessed in external memory extension mode. (2) when location 0fh instruction is executed the internal data area is mapped onto addresses ff700h to fffffh in the pd784046, and onto addresses ffb00h to fffffh in the pd784044. internal rom is mapped onto addresses 0 to 0ffffh in the pd784046, and onto addresses 0 to 07fffh in the pd784044. external memory is accessed in external memory extension mode. 57 chapter 3 cpu architecture user? manual u11515ej3v0ud figure 3-1. pd784044 memory map notes 1. accessed in the external memory extension mode. 2. base area or entry area by reset or interrupt. the internal ram is not reset. external memory note 1 (960k bytes) special function registers (sfrs) note 1 (256 bytes) internal ram (1k bytes) cannot be used (1280 bytes) internal rom (32k bytes) h general-purpose registers (128 bytes) macro service control word area (50 bytes) data area (512 bytes) program/data area (512 bytes) program/data area (32k bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) when location 0h instruction is executed cannot be used (1280 bytes) external memory note 1 (1013248 bytes) internal rom (32k bytes) when location 0fh instruction is executed special function registers (sfr s ) note 1 (256 bytes) internal ram (1k bytes) note 2 main ram peripheral ram f f f f f h h h h h h 0 f f 0 0 f 0 f d d 0 f 0 f f f f e 0 f f f f f 1 0 0 0 0 0 h h 0 f 0 f b a f f 0 0 h h 0 f 0 f 6 5 f f 0 0 h h 0 f 0 f 0 f 8 7 0 0 h 0 0 0 0 0 external memory note 1 (30208 bytes) h f f e f 0 h h 0 f 8 7 e e f f 0 0 h h 7 6 3 0 e e f f 0 0 h h 0 f 0 f d c f f 0 0 h 0 0 b f 0 h f f f 7 0 h h 0 f 0 f 0 f 1 0 0 0 h h 0 f 0 f 8 7 0 0 0 0 h h 0 f 8 7 0 0 0 0 0 0 h 0 0 0 0 0 h f f e f f h h 0 f 8 7 e e f f f f h h 7 6 3 0 e e f f f f h h 0 f 0 f d c f f f f h 0 0 b f f h h h h f f 0 0 f d d 0 f f f f f f f f f f f f h h 0 f 0 f 6 5 f f f f h h 0 f 0 f 0 f 8 7 0 0 h 0 0 0 0 0 h h 0 f 0 f 0 f 0 f 1 0 h h 0 f 0 f b a f f f f note 2 h h 0 f 4 3 0 0 0 0 0 0 h f f e f f 58 chapter 3 cpu architecture user s manual u11515ej3v0ud figure 3-2. pd784046 memory map notes 1. accessed in the external memory extension mode. 2. 2560 bytes in this area can be used as internal rom only when the location 0fh instruction is executed. 3. when the location 0h instruction is executed: 62976 bytes when the location 0fh instruction is executed: 65536 bytes 4. base area or entry area by reset or interrupt. the internal ram is not reset. external memory note 1 (960k bytes) note 1 internal ram (2k bytes) internal rom (62976 bytes) general-purpose registers (128 bytes) macro service control word area (50 bytes) data area (512 bytes) program/data area (1536 bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) when location 0h instruction is executed cannot be used (256 bytes) external memory note 1 (980480 bytes) internal rom (64k bytes) special function registers (sfrs) note 1 (256 bytes) internal ram (2k bytes) special function registers (sfrs) (256 bytes) cannot be used (256 bytes) program/data area note 3 note 2 peripheral ram main ram h 0 0 0 0 0 h f f 5 f 0 h 0 0 6 f 0 h f f 6 f 0 h f f f f f h f f e f 0 h 0 0 7 f 0 h 0 0 f f 0 h 0 d f f 0 h f d f f 0 h f f f f 0 h 0 0 0 0 1 note 4 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h 7 3 e f 0 h 6 0 e f 0 h 0 0 d f 0 h 0 0 7 f 0 h f f c f 0 h 0 0 5 f 0 h 0 0 0 0 0 h f 3 0 0 0 h 0 4 0 0 0 h f 7 0 0 0 h 0 8 0 0 0 h f f 7 0 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 0 1 0 h 0 0 0 0 0 h f f f f 0 h 0 0 0 0 1 h f f 5 f f h 0 0 6 f f h f f 6 f f h 0 0 7 f f h f f f f f h 0 0 f f f h 0 d f f f h f d f f f h f f e f f h f f e f f h 0 8 e f f h f 7 e f f h 7 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 7 f f h f f f f 0 note 4 when location 0fh instruction is executed 59 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.2 internal rom area the pd784046 subseries products incorporate rom which is used to store programs, table data, etc. if the internal rom area and internal data area overlap when the location 0h instruction is executed, the internal data area is accessed, and the overlapping part of the internal rom area cannot be accessed. table 3-1. internal rom area product name internal rom address space location 0h instruction location 0fh instruction pd784044 32 k 8 bits 00000h-07fffh 00000h-07fffh pd784046 64 k 8 bits 00000h-0f5ffh 00000h-0ffffh pd78f4046 the internal rom can be accessed at high speed. normally, fetches are performed at the same speed as external rom, but if the ifch bit of the memory extension mode register (mm) is set (1), the high-speed fetch function is used and internal rom fetches are performed at high speed (2-byte fetch performed in 2 system clocks). when the instruction execution cycle equal to an external rom fetch is selected, wait insertion is performed by the wait function, but when high-speed fetches are used, wait insertion is not performed for internal rom. reset input sets the instruction execution cycle equal to the external rom fetch cycle. 60 chapter 3 cpu architecture user? manual u11515ej3v0ud 3.3 base area the space from 0 to ffffh comprises the base area. the base area is the object for the following uses: reset entry address interrupt entry address callt instruction entry address 16-bit immediate addressing mode (with instruction address addressing) 16-bit direct addressing mode 16-bit register addressing mode (with instruction address addressing) 16-bit register indirect addressing mode short direct 16-bit memory indirect addressing mode the vector table area, callt instruction table area and callf instruction entry area are allocated to the base area. when the location 0h instruction is executed, the internal data area is located in the base area. note that, in the internal data area, program fetches cannot be performed from the internal high-speed ram area or special function register (sfr) area. also, internal ram area data should only be used after initialization has been performed. 61 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.3.1 vector table area the 64-byte area from 00000h to 0003fh is reserved as the vector table area. the vector table area stores the program start addresses used when a branch is made as the result of reset input or generation of an interrupt request. when context switching is used by an interrupt, the number of the register bank to be switched to is stored here. any portion not used as the vector table can be used as program memory or data memory. 16-bit values can be written to the vector table. therefore, branches can only be made within the base area. table 3-2. vector table vector table address interrupt cause 0003ch operand error 0003eh brk 00000h reset (reset input) 00002h nmi 00004h intwdt 00006h intov0 00008h intov1 0000ah intov4 0000ch intp0/intcc00 0000eh intp1/intcc01 00010h intp2/intcc02 00012h intp3/intcc03 00014h intp4 00016h intp5 00018h intp6 0001ah intcm10 0001ch intcm11 0001eh intcm20 00020h intcm21 00022h intcm30 00024h intcm31 00026h intcm40 00028h intcm41 0002ah intser 0002ch intsr/intcsi1 0002eh intst 00030h intser2 00032h intsr2/intcsi2 00034h intst2 00036h intad 62 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.3.2 callt instruction table area the 1-byte call instruction (callt) subroutine entry addresses can be stored in the 64-byte area from 00040h to 0007fh. the callt instruction references this table, and branches to a base area address written in the table as a subroutine. as the callt instruction is one byte in length, use of the callt instruction for subroutine calls written frequently throughout the program enables the program object size to be reduced. the table can contain up to 32 subroutine entry addresses, and therefore it is recommended that they be recorded in order of frequency. if this area is not used as the callt instruction table, it can be used as ordinary program memory or data memory. 3.3.3 callf instruction entry area a subroutine call can be made directly to the area from 00800h to 00fffh with the 2-byte call instruction (callf). as the callf instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of the direct subroutine call call instruction (3 or 4 bytes). writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device. if you wish to reduce the object size, writing an unconditional branch (br) instruction in this area and locating the subroutine itself outside this area will result in a reduced object size for subroutines that are called from five or more poin ts. in this case, only the 4 bytes of the br instruction are occupied in the callf entry area, enabling the object size to be reduc ed with a large number of subroutines. 3.4 internal data area the internal data area consists of the internal ram area and special function register area (refer to figures 3-1 and 3-2 ). the final address of the internal data area can be specified by means of the location instruction as either 0ffffh (when a location 0h instruction is executed) or fffffh (when a location 0fh instruction is executed). selection of the addresses of the internal data area by means of the location instruction must be executed once immediately after reset release, and once the selection is made, it cannot be changed. the program after reset release must be as shown in the example below. if the internal data area and another area are allocated to the same addresses, the internal data area is accessed and the other area cannot be accessed. example rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn caution when the location 0h instruction is executed, it is necessary to ensure that the program after reset release does not overlap the internal data area. it is also necessary to make sure that the entry addresses of the processing routines for non-maskable interrupts such as nmi do not overlap the internal data area. also, initialization must be performed for maskable interrupt entry areas, etc., before the internal data area is referenced. 63 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.4.1 internal ram area the pd784046 incorporates general-purpose static ram. this area is configured as follows: peripheral ram (pram) internal ram area internal high-speed ram (iram) table 3-3. internal ram area internal ram internal ram area product name peripheral ram: pram internal high-speed ram: iram pd784044 1024 bytes 512 bytes 512 bytes (0fb00h-0feffh) (0fb00h-0fcffh) (0fd00h-0feffh) pd784046 2048 bytes 1536 bytes pd78f4046 (0f700h-0feffh) (0f700h-0fcffh) remark the addresses in the table are the values that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. 64 chapter 3 cpu architecture user s manual u11515ej3v0ud the internal ram memory map is shown in figure 3-3. figure 3-3. internal ram memory map note pd784044 ............................. 00fb00h pd784046, 78f4046 ............ 00f700h remark the addresses in the figure are the values that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. 00feffh 00fe80h 00fe37h 00fe06h 00fe00h 00fdffh peripheral ram internal high-speed ram macro service control word area general-purpose register area short direct addressing 1 permissible range short direct addressing 2 permissible range 00fd20h 00fd1fh 00fd00h 00fcffh note 65 chapter 3 cpu architecture user s manual u11515ej3v0ud (1) internal high-speed ram (iram) the internal high-speed ram (iram) allows high-speed accesses to be made. the short direct addressing mode for high-speed accesses can be used on fd20h to feffh in this area. there are two kinds of short direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target address. the function is the same in both of these addressing modes. with some instructions, the word length is shorter with short direct addressing 2 than with short direct addressing 1. refer to the 78k/iv series user? manual ?instruction for details. a program fetch cannot be performed from iram. if a program fetch is performed from an address onto which iram is mapped, cpu inadvertent loop will result. the following areas are reserved in iram. general-purpose register area : fe80h to feffh macro service control word area : fe06h to fe37h macro service channel area : fe00h to feffh (the address is specified by the macro service control word) if the reserved function is not used in these areas, they can be used as ordinary data memory. remark the addresses in this text are those that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown in the text. (2) peripheral ram (pram) the peripheral ram (pram) is used as ordinary program memory or data memory. when used as program memory, the program must be written to the peripheral ram beforehand by a program. program fetches from peripheral ram are fast, with a 2-byte fetch being executed in 2 clocks. 66 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.4.2 special function register (sfr) area the on-chip peripheral hardware special function registers (sfrs) are mapped onto the area from 0ff00h to 0ffffh (refer to figures 3-1 and 3-2 ). the area from 0ffd0h to 0ffdfh is mapped as an external sfr area, and allows externally connected peripheral i/ os, etc., to be accessed in external memory extension mode (specified by the memory extension mode register (mm)). caution addresses onto which sfrs are not mapped should not be accessed in this area. if such an address is accessed by mistake, the cpu may become deadlocked. a deadlock can only be released by reset input. remark the addresses in this text are those that apply when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown in the text. 3.4.3 external sfr area in pd784046 subseries products, the 16-byte area from 0ffd0h to 0ffdfh in the sfr area (when the location 0h is executed; 0fffd0h to 0fffdfh when the location 0fh instruction is executed) is mapped as an external sfr area. when the external memory extension mode is externally connected peripheral i/os, etc., can be accessed using the address bus or address/data bus, etc. as the external sfr area can be accessed by sfr addressing, peripheral i/o and similar operations can be performed easily, the object size can be reduced, and macro service can be used. bus operations for accesses to the external sfr area are performed in the same way as for ordinary memory accesses. 3.5 external memory space the external memory space is a memory space that can be accessed in accordance with the setting of the memory extension mode register (mm). it can store programs, table data, etc., and can have peripheral i/o devices allocated to it. 67 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.6 memory mapping of pd78f4046 the pd78f4046 has 64k bytes of flash memory and 2048 bytes of internal ram. the pd78f4046 has a function to not use part of the internal memory (memory size select function). this function is effected by software. the memory size is changed by using the internal memory size select register (ims). this register can be read or written by using an 8-bit manipulation instruction. data can be only written to the ims of the pd78f4046, however. the ims of the pd784044 and 784046 retains the value at reset even if data is written to it. therefore, the value of the ims at reset differs depending on the model. in the case of the pd784044, it is cdh. the value of the ims of the pd784046 and 78f4046 is set to deh at reset. figure 3-4. format of internal memory size select register (ims) note the value at reset differs depending on the model. pd784044 : cdh pd784046, 78f4046 : deh cautions 1. writing to the internal memory size select register (ims) is valid only with the pd78f4046. the ims of the pd784044 and 784046 holds the value at reset even if data is written to it. 2. to develop a program for the pd784044 using the pd78f4046, set the value of the ims to cdh. when the value of the ims is set to cdh, the peripheral ram capacity of the pd78f4046 is 768 bytes, but the peripheral ram capacity of the pd784044 is 512 bytes. when using a mask rom, therefore, exercise care that addresses 0fa00h through 0faffh of the peripheral ram area of the pd78f4046 are not used (when the location 0h instruction is executed). 1 1 rom1 rom0 1 1 ram1 ram0 76543210 ims rom1 0 0 selects internal rom capacity 32k bytes invalid setting prohibited rom0 0 1 pd784044 pd784046 pd78f4046 invalid 64k bytes 32k bytes 64k bytes other ram1 0 1 selects peripheral ram capacity 512 bytes invalid setting prohibited ram0 1 0 pd784044 pd784046 pd78f4046 invalid 1.5k bytes 768 bytes 1.5k bytes other address : 0fffch on reset : note r/w ? 68 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.7 control registers control registers consist of the program counter (pc), program status word (psw), and stack pointer (sp). 3.7.1 program counter (pc) this is a 20-bit binary counter that holds address information on the next program to be executed (refer to figure 3-5 ). normally, the pc is incremented automatically by the number of bytes in the fetched instruction. when an instruction associated with a branch is executed, the immediate data or register contents are set in the pc. upon reset input, the 16-bit data in address 0 and 1 is set in the low-order 16 bits, and 0000 in the high-order 4 bits of the pc. figure 3-5. format of program counter (pc) 19 pc 0 3.7.2 program status word (psw) the program status word (psw) is a 16-bit register comprising various flags that are set or reset according to the result of instruction execution. read accesses and write accesses are performed in high-order 8-bit (pswh) and low-order 8-bit (pswl) units. individual flags can be manipulated by bit-manipulation instructions. the contents of the psw are automatically saved to the stack when a vectored interrupt request is acknowledged or a brk instruction is executed, and automatically restored when an reti or retb instruction is executed. when context switching is used, the contents are automatically saved in rp3, and automatically restored when an retcs or retcsb instruction is executed. reset input resets (0) all bits. 0 must always be written to the bits written as 0 in figure 3-6. the contents of bits written as - are undefined when read. figure 3-6. format of program status word (psw) 7 uf pswh symbol 6 rbs2 5 rbs1 4 rbs0 3 2 1 0 7 s pswl 6 z 5 rss 4 ac 3 ie 2 p/v 1 0 0 cy the flags are described below. (1) carry flag (cy) the carry flag records a carry or borrow resulting from an operation. this flag also records the shifted-out value when a shift/rotate instruction is executed, and functions as a bit accumulator when a bit-manipulation instruction is executed. the status of the cy flag can be tested with a conditional branch instruction. 69 chapter 3 cpu architecture user s manual u11515ej3v0ud (2) parity/overflow flag (p/v) the p/v flag performs the following two kinds of operation associated with execution of an operation instruction. the status of the p/v flag can be tested with a conditional branch instruction. parity flag operation set (1) when the number of bits set (1) as the result of execution of a logical operation instruction, shift/rotate instruction, or a chkl or chkla instruction is even, and reset (0) if odd. when a 16-bit shift instruction is executed, however, only the low-order 8 bits of the operation result are valid for the parity flag. overflow flag operation set (1) only when the numeric range expressed as a two s complement is exceeded as the result of execution of a arithmetic operation instruction, and reset (0) otherwise. more specifically, the value of this flag is the exclusive or of the carry into the msb and the carry out of the msb. for example, the two s complement range in an 8-bit arithmetic operation is 80h ( 128) to 7fh (+127), and the flag is set (1) if the operation result is outside this range, and reset (0) if within this range. example the operation of the overflow flag when an 8-bit addition instruction is executed is shown below. when the addition of 78h (+120) and 69h (+105) is performed, the operation result is e1h (+225), and the two s complement limit is exceeded, with the result that the p/v flag is set (1). expressed as a two s complement, e1h is -31. 78h (+120) = 0111 1000 +) 69h (+105) = +) 0110 1001 0 1110 0001 = 31 p/v = 1 cy when the following two negative numbers are added together, the operation result is within the two s complement range, and therefore the p/v flag is reset (0). fbh ( 5) = 1111 1011 +) f0h ( 16) = +) 1111 0000 1 1110 1011 = 21 p/v = 0 cy (3) interrupt request enable flag (ie) this flag controls cpu interrupt request acknowledgment operations. when 0 , interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be acknowledged. all other interrupts are disabled. when 1 , the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts. the ie flag is set (1) by execution of an ei instruction, and reset (0) by execution of a di instruction or acknowledgment of an interrupt. 70 chapter 3 cpu architecture user s manual u11515ej3v0ud (4) auxiliary carry flag (ac) the ac flag is set (1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset (0) otherwise. this flag is used when the adjba or adjbs instruction is executed. (5) register set selection flag (rss) the rss flag specifies the general-purpose registers that function as x, a, c and b, and the general-purpose register pairs (16-bit) that function as ax and bc. this flag is provided to maintain compatibility with the 78k/iii series, and must be set to 0 except when using a 78k/ iii series program. (6) zero flag (z) the z flag records the fact that the result of an operation is 0 . it is set (1) when the result of an operation is 0 , and reset (0) otherwise. the status of the z flag can be tested with a conditional branch instruction. (7) sign flag (s) the s flag records the fact that the msb is 1 as the result of an operation. it is set (1) when the msb is 1 as the result of an operation, and reset (0) otherwise. the status of the s flag can be tested with a conditional branch instruction. (8) register bank selection flag (rbs0 to rbs2) this is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (refer to table 3-4 ). it stores 3-bit information which indicates the register bank selected by execution of a sel rbn instruction, etc. table 3-4. register bank selection rbs2 rbs1 rbs0 specified register bank 0 0 0 register bank 0 0 0 1 register bank 1 0 1 0 register bank 2 0 1 1 register bank 3 1 0 0 register bank 4 1 0 1 register bank 5 1 1 0 register bank 6 1 1 1 register bank 7 (9) user flag (uf) this flag can be set and reset in the user program, and used for program control. 71 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.7.3 use of rss bit basically, the rss bit should be fixed at 0 at all times. the following explanation refers to the case where a 78k/iii series program is used, and the program used sets the rss bit to 1. this explanation can be skipped if the rss bit is fixed at 0. the rss bit is provided to allow the functions of a (r1), x (r0), b (r3), c (r2), ax (rp0) and bc (rp1) to be used by registers r4 to r7 (rp2, rp3) as well. effective use of this bit enables efficient programs to be written in terms of program size and program execution. however, careless use can result in unforeseen problems. therefore, the rss bit should always be set to 0. the rss bit should only be set to 1 when a 78k/iii series program is used. use of the rss bit set to 0 in all programs will improve programming and debugging efficiency. even when using a program in which the rss bit set to 1 is used, it is recommended that the program be amended if possible so that it does not set the rss bit to 1. (1) rss bit recommendations registers used by instructions for which the a, x, b, c and ax registers are directly entered in the operand column of the operation list (refer to 21.2. ) registers specified as implied by instructions that use the a, ax, b and c registers by means of implied addressing registers used in addressing by instructions that use the a, b and c registers in indexed addressing and based indexed addressing the registers used in these cases are switched as follows according to the rss bit. when rss = 0 a r1, x r0, b r3, c r2, ax rp0, bc rp1 when rss = 1 a r5, x r4, b r7, c r6, ax rp2, bc rp3 registers used other than those mentioned above are always the same irrespective of the value of the rss bit. with the nec electronics assembler (ra78k4), the register operation code generated when the a, x, b, c, ax and bc registers are described by those names is determined by the assembler rss pseudo-instruction. when the rss bit is set or reset, an rss pseudo-instruction must be written immediately before (or immediately after) the relevant instruction (refer to example below). 72 chapter 3 cpu architecture user s manual u11515ej3v0ud (2) operation code generation method with ra78k4 with ra78k4, if there is an instruction with the same function as an instruction for which a or ax is directly entered in the operand column of the instruction operation list, the operation code for which a or ax is directly entered in the operand column is generated first. example the function is the same when b is used as r in a mov a,r instruction, and when a is used as r and b is used as r in a movr,r instruction, and the same code (mov,a,b) is used in the assembler source program. in this case, ra78k4 generates code equivalent to the mov a, r instruction. if a, x, b, c, ax or bc is written in an instruction for which r, r , rp and rp are specified in the operand column, the a, x, b, c, ax and bc instructions generate an operation code that specifies the following registers according to the operand of the ra78k4 rss pseudo-instruction. register rss = 0 rss = 1 ar1r5 xr0r4 br3r7 cr2r6 ax rp0 rp2 bc rp1 rp3 if r0 to r7 or rp0 to rp4 is written as r, r , rp or rp in the operand column, an operation code in accordance with that specification is output (an operation code for which a or ax is directly entered in the operand column is not output.) r1, r3, r2 or r5, r7, r6 cannot be used for registers a, b and c used in indexed addressing and based indexed addressing. (3) operating precautions switching the rss bit has the same effect as having two register sets. however, when writing a program, care must be taken to ensure that the static program code and dynamic rss bit changes at the time of program execution always coincide. also, a program that sets rss to 1 cannot be used by a program that uses the context switching function, and therefore program usability is poor. moreover, since different registers are used with the same name, program readability is poor and debugging is difficult. therefore, if it is necessary to set rss to 1, these disadvantages must be fully taken into consideration when writing a program. a register not specified by the rss bit can be accessed by writing its absolute name. 73 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.7.4 stack pointer (sp) the stack pointer is a 24-bit register that holds the start address of the stack area (lifo type: 00000h to ffffffh) (refer to figure 3-7 ). it is used to address the stack area when subroutine processing or interrupt processing is performed. be sure to write 0 in the high-order 4 bits. the contents of the sp are decremented before a write to the stack area and incremented after a read from the stack area (refer to figures 3-8 and 3-9 ). the sp is accessed by dedicated instructions. the sp contents are undefined after reset input, and therefore the sp must always be initialized by an initialization program directly after reset release (before a subroutine call or interrupt acknowledgment). example sp initialization movg sp, #0fee0h;sp 0fee0h (when used from fedfh) figure 3-7. format of stack pointer (sp) 23 sp 0 74 chapter 3 cpu architecture user s manual u11515ej3v0ud figure 3-8. data saved to stack area push sfr instruction stack push sfrp instruction stack high-order byte low-order byte high-order byte undefined undefined pc15 to pc8 pc7 to pc0 pc15 to pc8 pc7 to pc0 pc19 to pc16 pc19 to pc16 pswh 7 to pswh 4 pswh 7 to pswh 4 pswl pswl r7 r6 r5 r4 rp3 rp2 ax a x middle-order byte low-order byte push rg instruction stack push psw instruction stack call, callf, callt instruction stack vectored interrupt stack push post, pushu post instruction (in case of push ax, rp2, rp3) stack sp sp 1 sp sp 1 sp sp 1 sp 2 sp sp 2 sp sp 1 sp 2 sp sp 2 sp sp 1 sp 2 sp 3 sp sp 3 sp sp 1 sp 2 sp 3 sp sp 3 sp sp 1 sp 2 sp 3 sp 4 sp sp 4 sp sp 1 sp 2 sp 3 sp 4 sp 5 sp 6 sp sp 6 ? ? ? ? ? ? ? ? ? 75 chapter 3 cpu architecture user s manual u11515ej3v0ud figure 3-9. data restored from stack area pop sfr instruction stack pop sfrp instruction stack high-order byte low-order byte high-order byte _ note _ note pc15 to pc8 pc7 to pc0 pc15 to pc8 pc7 to pc0 pc19 to pc16 pc19 to pc16 pswh 7 to pswh 4 pswh 7 to pswh 4 pswl pswl r7 r6 r5 r4 rp3 rp2 ax a x middle-order byte low-order byte pop rg instruction stack pop psw instruction stack ret instruction stack reti, retb instruction stack pop post, popu post instruction (in case of pop ax, rp2, rp3) stack sp sp+1 sp+1 sp sp sp+2 sp+1 sp sp sp+3 sp+2 sp+1 sp sp sp+3 sp+2 sp+1 sp sp sp+4 sp+3 sp+2 sp+1 sp sp sp+6 sp+5 sp+4 sp+3 sp+2 sp+1 sp sp sp+2 sp+1 sp ? ? ? ? ? ? ? ? ? note this 4-bit data is ignored. 76 chapter 3 cpu architecture user s manual u11515ej3v0ud cautions 1. with stack addressing, the entire 1 m-byte space can be accessed but a stack area cannot be reserved in the sfr area or internal rom area. 2. the stack pointer (sp) is undefined after reset input. moreover, non-maskable interrupts can still be acknowledged when the sp is in an undefined state. an unanticipated operation may therefore be performed if a non-maskable interrupt request is generated when the sp is in the undefined state directly after reset release. to avoid this risk, the program after reset release must be written as follows. rstvct cseg at 0 dw rststrt to initseg cseg base rststrt : location 0h ; or location 0fh movg sp, #stkbgn 77 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.8 general registers 3.8.1 configuration there are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a 16-bit general-purpose register. in addition, four of the 16-bit general-purpose registers can be combined with an 8-bit register for address extension, and used as 24-bit address specification registers. general-purpose registers other than the v, u, t and w registers for address extension are mapped onto internal ram. these register sets are provided in 8 banks, and can be switched by means of software or the context switching function. upon reset input, register bank 0 is selected. the register bank used during program execution can be checked by reading the register bank selection flag (rbs0, rbs1, rbs2) in the psw. figure 3-10. format of general-purpose register remark absolute names are shown in parentheses. 7070 a(r1) x(r0) ax(rp0) b (r3) c (r2) bc (rp1) r5 r4 rp2 r7 r6 rp3 r9 r8 vp (rp4) v vvp (rg4) r11 r10 up (rp5) u uup (rg5) d (r13) e (r12) de (rp6) t tde (rg6) h (r15) l (r14) hl (rp7) w whl (rg7) 0 23 15 8 banks 16 78 chapter 3 cpu architecture user s manual u11515ej3v0ud figure 3-11. general-purpose register addresses ? ? ? ? ? ? ? ...... ...... ...... note when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the address values shown above. caution r4, r5, r6, r7, rp2 and rp3 can be used as the x, a, c, b, ax and bc registers respectively by setting the rss bit of the psw to 1, but this function should only be used when using a 78k/iii series program. remark when the register bank is changed, and it is necessary to return to the original register bank, an sel rbn instruction should be executed after saving the psw to the stack with a push psw instruction. when returning to the original register bank, if the stack location does not change the pop psw instruction should be used. when the register bank is changed by a vectored interrupt processing program, etc., the psw is automatically saved to the stack when an interrupt is acknowledged and restored by an reti or retb instruction, so that, if only one register bank is used in the interrupt service routine, only an sel rbn instruction needs be executed, and execution of a push psw and pop psw instruction is not necessary. example when register bank 2 is specified push psw sel rb2 operations in register bank 2 pop psw operations in original register bank rbnk0 feffh note fe80h note rbnk1 rbnk2 rbnk3 rbnk4 rbnk5 rbnk6 rbnk7 h(r15) (fh) 8-bit processing 16-bit processing d(r13) (dh) r11 (bh) r9 (9h) r7 (7h) r5 (5h) b(r3) (3h) a(r1) (1h) 77 0 0 15 0 l(r14) (eh) e(r12) (ch) r10 (ah) r8 (8h) r6 (6h) r4 (4h) c(r2) (2h) x(r0) (0h) hl(rp7) (eh) de(rp6) (ch) up(rp5) (ah) vp(rp4) (8h) rp3 (6h) rp2 (4h) bc(rp1) (2h) ax(rp0) (0 h) 79 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.8.2 functions in addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by pairing two 8-bit registers. also, four of the 16-bit registers can be combined with an 8-bit register for address extension and manipulated in 24-bit units. each register can be used in a general-purpose way for temporary storage of an operation result and as the operand of an inter-register operation instruction. the area from 0fe80h to 0feffh (when the location 0h instruction is executed; 0ffe80h to 0ffeffh when the location 0fh instruction is executed) can be given an address specification and accessed as ordinary data memory irrespective of whether or not it is used as the general-purpose register area. as 8 register banks are provided in the 78k/iv series, efficient programs can be written by using different register banks for normal processing and processing in the event of an interrupt. the registers have the following specific functions. a (r1): register mainly used for 8-bit data transfers and operation processing. can be used in combination with all addressing modes for 8-bit data. can also be used for bit data storage. can be used as the register that stores the offset value in indexed addressing and based indexed addressing. x (r0): can be used for bit data storage. ax (rp0): register mainly used for 16-bit data transfers and operation processing. can be used in combination with all addressing modes for 16-bit data. axde: used for 32-bit data storage when a divux, macw or macsw instruction is executed. b (r3): has a loop counter function, and can be used by the dbnz instruction. can be used as the register that stores the offset value in indexed addressing and based indexed addressing. used as the macw and macsw instruction data pointer. c (r2): has a loop counter function, and can be used by the dbnz instruction. can be used as the register that stores the offset value in based indexed addressing. used as the counter in a string instruction and the sacw instruction. used as the macw and macsw instruction data pointer. rp2: used to save the low-order 16 bits of the program counter (pc) when context switching is used. rp3: used to save the high-order 4 bits of the program counter (pc) and the program status word (psw) (excluding bit 0 to bit 3 of pswh) when context switching is used. 80 chapter 3 cpu architecture user s manual u11515ej3v0ud vvp (rg4): has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. uup (rg5): has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means of the pushu and popu instructions. has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. de (rp6), hl (rp7): operate as the registers that store the offset value in indexed addressing and based indexed addressing. tde (rg6): has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. used as the pointer in a string instruction and the sacw instruction. whl (rg7): register used mainly for 24-bit data transfers and operation processing. has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. used as the pointer in a string instruction and the sacw instruction. 81 chapter 3 cpu architecture user s manual u11515ej3v0ud in addition to the function name that emphasizes the specific function of the register (x, a, c, b, e, d, l, h, ax, bc, vp, up, de, hl, vvp, uup, tde, whl), each register can also be described by its absolute name (r0 to r15, rp0 to rp7, rg4 to rg7). the correspondence between these names is shown in table 3-5. table 3-5. correspondence between function names and absolute names (a) 8-bit registers absolute name function name rss = 0 rss = 1 note r0 x r1 a r2 c r3 b r4 x r5 a r6 c r7 b r8 r9 r10 r11 r12 e e r13 d d r14 l l r15 h h (b) 16-bit registers absolute name function name rss = 0 rss = 1 note rp0 ax rp1 bc rp2 ax rp3 bc rp4 vp vp rp5 up up rp6 de de rp7 hl hl (c) 24-bit registers absolute name function name rg4 vvp rg5 uup rg6 tde rg7 whl note rss should only be set to 1 when a 78k/iii series program is used. remark r8 to r11 have no function name. 82 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.9 special function registers (sfrs) these are registers to which a special function is assigned, such as on-chip peripheral hardware mode registers, control registers, etc. they are mapped onto the 256-byte space from 0ff00h to 0ffffh note . note when the location 0h instruction is executed. when the location 0fh instruction is executed, the area is fff00h to fffffh. caution addresses onto which sfrs are not assigned should not be accessed in this area. if such an address is as accessed by mistake, the pd784046 may become deadlocked. a deadlock can only be released by reset input. a list of special function registers (sfrs) is given in table 3-6. the meaning of the items in the table is as explained below. symbol .............................. symbol that indicates the incorporated sfr. this is a reserved word in the nec electronics assembler (ra78k4). with the c compiler (cc78k4), this symbol can be used as a sfr variable by means of a #pragma sfr command. r/w .................................... indicates whether the corresponding sfr is read/write enabled. r/w: read/write enabled r : read-only w : write-only manipulable bit units ........ indicates the applicable manipulation bit units when the corresponding sfr is manipulated. a 16-bit-manipulable sfr can be written in the operand sfrp , and when specified by an address, an even address is specified. a bit-manipulable sfr can be written in a bit manipulation instruction. on reset ........................... indicates the status of the register after reset input. 83 chapter 3 cpu architecture user s manual u11515ej3v0ud table 3-6. special function registers (sfrs) list (1/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w undefined 0ff01h port 1 p1 0ff02h port 2 p2 note 2 0ff03h port 3 p3 r/w 0ff04h port 4 p4 0ff05h port 5 p5 0ff06h port 6 p6 0ff07h port 7 p7 r 0ff08h port 8 p8 0ff09h port 9 p9 r/w 0ff0eh port 0 buffer register p0l 0ff10h timer register 0 tm0 r 0000h 0ff11h 0ff12h capture/compare register 00 cc00 r/w undefined 0ff13h 0ff14h capture/compare register 01 cc01 0ff15h 0ff16h capture/compare register 02 cc02 0ff17h 0ff18h capture/compare register 03 cc03 0ff19h 0ff1ah timer register 1 tm1 r 0000h 0ff1bh 0ff1ch compare register 10 cm10 r/w undefined 0ff1dh 0ff1eh compare register 11 cm11 0ff1fh 0ff20h port 0 mode register pm0 ffh 0ff21h port 1 mode register pm1 0ff22h port 2 mode register pm2 note 3 0ff23h port 3 mode register pm3 0ff24h port 4 mode register pm4 0ff25h port 5 mode register pm5 0ff26h port 6 mode register pm6 0ff29h port 9 mode register pm9 0ff2eh real-time output port control register rtpc 00h 0ff2fh port read control register prdc notes 1. when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. bit 0 of p2 can only be read. bits 1 through 7 can be read/written. 3. bit 0 of pm2 is fixed to 1 by hardware. 84 chapter 3 cpu architecture user s manual u11515ej3v0ud table 3-6. special function registers (sfrs) list (2/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff30h timer unit mode register 0 tum0 r/w 00h 0ff31h timer mode control register tmc 0ff32h timer output control register 0 toc0 0ff33h timer output control register 1 toc1 0ff34h timer unit mode register 2 tum2 0ff35h timer mode control register 2 tmc2 0ff36h timer output control register 2 toc2 0ff37h timer mode control register 4 tmc4 0ff38h prescaler mode register prm 0ff39h prescaler mode register 2 prm2 0ff3ah prescaler mode register 4 prm4 0ff3bh noise protection control register npc 0ff3ch external interrupt mode register 0 intm0 0ff3dh external interrupt mode register 1 intm1 0ff3eh interrupt valid edge flag register 1 ief1 undefined 0ff3fh interrupt valid edge flag register 2 ief2 0ff41h port 1 mode control register pmc1 00h 0ff42h port 2 mode control register pmc2 note 2 0ff43h port 3 mode control register pmc3 0ff49h port 9 mode control register pmc9 0ff4eh pull-up resistor option register l puol 0ff4fh pull-up resistor option register h puoh 0ff50h timer register 2 tm2 r 0000h 0ff51h 0ff52h compare register 20 cm20 r/w undefined 0ff53h 0ff54h compare register 21 cm21 0ff55h 0ff56h timer register 3 tm3 r 0000h 0ff57h 0ff58h compare register 30 cm30 r/w undefined 0ff59h 0ff5ah compare register 31 cm31 0ff5bh 0ff60h timer register 4 tm4 r 0000h 0ff61h notes 1. when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. bits 0, and 5 through 7 of pmc2 are fixed to 0 by hardware. 85 chapter 3 cpu architecture user s manual u11515ej3v0ud table 3-6. special function registers (sfrs) list (3/5) address note special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff62h compare register 40 cm40 r/w undefined 0ff63h 0ff64h compare register 41 cm41 0ff65h 0ff6eh a/d converter mode register adm 00h 0ff70h a/d conversion result register 0 adcr0 r undefined 0ff71h 0ff71h a/d conversion result register 0h adcr0h 0ff72h a/d conversion result register 1 adcr1 0ff73h 0ff73h a/d conversion result register 1h adcr1h 0ff74h a/d conversion result register 2 adcr2 0ff75h 0ff75h a/d conversion result register 2h adcr2h 0ff76h a/d conversion result register 3 adcr3 0ff77h 0ff77h a/d conversion result register 3h adcr3h 0ff78h a/d conversion result register 4 adcr4 0ff79h 0ff79h a/d conversion result register 4h adcr4h 0ff7ah a/d conversion result register 5 adcr5 undefined 0ff7bh 0ff7bh a/d conversion result register 5h adcr5h 0ff7ch a/d conversion result register 6 adcr6 0ff7dh 0ff7dh a/d conversion result register 6h adcr6h 0ff7eh a/d conversion result register 7 adcr7 0ff7fh 0ff7fh a/d conversion result register 7h adcr7h 0ff84h clocked serial interface mode register 1 csim1 r/w 00h 0ff85h clocked serial interface mode register 2 csim2 0ff88h asynchronous serial interface mode register asim 0ff89h asynchronous serial interface mode register 2 asim2 0ff8ah asynchronous serial interface status register asis r 0ff8bh asynchronous serial interface status register 2 asis2 note when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 86 chapter 3 cpu architecture user s manual u11515ej3v0ud table 3-6. special function registers (sfrs) list (4/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff8ch serial receive buffer: uart0 rxb r undefined serial transmit shift register: uart0 txs w serial shift register: ioe1 sio1 r/w 0ff8dh serial receive buffer: uart2 rxb2 r serial transmit shift register: uart2 txs2 w serial shift register: ioe2 sio2 r/w 0ff90h baud rate generator control register brgc 00h 0ff91h baud rate generator control register 2 brgc2 0ffa8h in-service priority register ispr r 0ffaah interrupt mode control register imc r/w 80h 0ffach interrupt mask register 0l mk0l ffh 0ffach interrupt mask register 0 mk0 ffffh 0ffadh 0ffadh interrupt mask register 0h mk0h ffh 0ffaeh interrupt mask register 1l mk1l 0ffaeh interrupt mask register 1 mk1 ffffh 0ffafh 0ffafh interrupt mask register 1h mk1h ffh 0ffc0h standby control register note 2 stbc 30h 0ffc2h watchdog timer mode register note 2 wdm 00h 0ffc4h memory expansion mode register mm 20h 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 aaaah 0ffc9h 0ffcah bus width specification register bw note 3 0ffcbh 0ffcfh oscillation stabilization time specification register osts 00h 0ffd0h- external sfr area undefined 0ffdfh 0ffe0h interrupt control register (intov0) ovic0 43h 0ffe1h interrupt control register (intov1) ovic1 0ffe2h interrupt control register (intov4) ovic4 0ffe3h interrupt control register (intp0) pic0 0ffe4h interrupt control register (intp1) pic1 0ffe5h interrupt control register (intp2) pic2 notes 1. when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. these registers can be written only by using dedicated instructions mov stbc, #byte and mov wdm, #byte, and cannot be written by any other instructions. 3. the value of this register on reset differs depending on the setting of the bwd pin. bwd = 0: 0000h bwd = 1: 00ffh 87 chapter 3 cpu architecture user s manual u11515ej3v0ud table 3-6. special function registers (sfrs) list (5/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ffe6h interrupt control register (intp3) pic3 r/w 43h 0ffe7h interrupt control register (intp4) pic4 0ffe8h interrupt control register (intp5) pic5 0ffe9h interrupt control register (intp6) pic6 0ffeah interrupt control register (intcm10) cmic10 0ffebh interrupt control register (intcm11) cmic11 0ffech interrupt control register (intcm20) cmic20 0ffedh interrupt control register (intcm21) cmic21 0ffeeh interrupt control register (intcm30) cmic30 0ffefh interrupt control register (intcm31) cmic31 0fff0h interrupt control register (intcm40) cmic40 0fff1h interrupt control register (intcm41) cmic41 0fff2h interrupt control register (intser) seric 0fff3h interrupt control register (intsr) sric interrupt control register (intcsi1) csiic1 0fff4h interrupt control register (intst) stic 0fff5h interrupt control register (intser2) seric2 0fff6h interrupt control register (intsr2) sric2 interrupt control register (intcsi2) csiic2 0fff7h interrupt control register (intst2) stic2 0fff8h interrupt control register (intad) adic 0fffch internal memory size select register note 2 ims note 3 notes 1. when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. writing to ims is valid only with the flash memory model ( pd78f4046). when writing to ims with mask rom models ( pd784044, 784046), the value is not changed and remains the same as the value on reset. 3. the value on reset differs depending on the models. pd784044 : cdh pd784046, 78f4046 : deh 88 chapter 3 cpu architecture user s manual u11515ej3v0ud 3.10 cautions (1) program fetches cannot be performed from the internal high-speed ram area (0fd00h to 0feffh when the location 0h instruction is executed; ffd00h to ffeffh when the location 0fh instruction is executed). (2) special function registers (sfrs) addresses onto which sfrs are not assigned should not be accessed in the area 0ff00h to 0ffffh note . if such an address is accessed by mistake, the pd784046 may become deadlocked. a deadlock can only be released by reset input. note when the location 0h instruction is executed; fff00h to fffffh when the location 0fh instruction is executed. (3) writing to the internal memory size select register (ims) is valid only with the pd78f4046. the ims of the pd784044 and 784046 holds the value at reset even if data is written to it. (4) to develop a program for the pd784044 using the pd78f4046, set the value of the ims to cdh. when the value of the ims is set to cdh, the peripheral ram capacity of the pd78f4046 is 768 bytes, but the peripheral ram capacity of the pd784044 is 512 bytes. when using a mask rom, therefore, exercise care that addresses 0fa00h through 0faffh of the peripheral ram area of the pd78f4046 are not used (when the location 0h instruction is executed). (5) stack pointer (sp) operation with stack addressing, the entire 1 m-byte space can be accessed, but a stack area cannot be reserved in the sfr area or internal rom area. (6) stack pointer (sp) initialization the sp is undefined after reset input, while non-maskable interrupts can be acknowledged directly after reset release. therefore, an unforeseen operation may be performed if a non-maskable interrupt request is generated while the sp is in the undefined state directly after reset release. to minimize this risk, the following program should be coded without fail after reset release. rstvct cseg at 0 dw rststrt to initseg cseg base rststrt : location 0h ; or location 0fh movg sp, #stkbgn 89 user? manual u11515ej3v0ud chapter 4 clock generator 4.1 configuration and function the clock generator generates and controls the internal system clock (clk) supplied to the cpu and on-chip hardware. the clock generator block diagram is shown in figure 4-1. figure 4-1. block diagram of clock generator remark f xx : crystal/ceramic oscillation frequency f x : external clock frequency f clk : internal system clock frequency the clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the x1 and x2 pins. when standby mode (stop) is set, oscillation stops (refer to chapter 18 standby function ). an external clock can also be input. in this case, input the clock signal to the x1 pin. the processing of the x2 pin differs depending on the setting of the extc bit of the oscillation stabilization time specificati on register (osts), as follows: extc bit = 1: input a clock in reverse phase to the clock input to x1 pin to the x2 pin. extc bit = 0: leave the x2 pin unconnected. the frequency divider circuit divides the output (f xx or f x ) of the clock oscillator by two, to generate an internal system clock (f clk ). internal bus extc osts2 osts1 osts0 reset osts stp hlt reset stbc x1 x2 clock oscillator f xx or f x 1/2 f clk internal system clock (clk) frequency divider 90 chapter 4 clock generator user s manual u11515ej3v0ud figure 4-2. clock oscillator external circuitry (a) crystal/ceramic oscillation (b) external clock extc bit of .osts = 1 extc bit of .osts = 0 cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed by the dotted line. remark use of crystal resonator and ceramic resonator generally speaking, the oscillation frequency of a crystal resonator is extremely stable. it is therefore ideal for performing high-precision time management (in clocks, frequency meters, etc.). a ceramic resonator is inferior to a crystal resonator in terms of oscillation frequency stability, but it has three advantages: a fast oscillation start-up time, small size, and low price. it is therefore suitable for general use (when high-precision time management is not required). in addition, there are products with a built-in capacitor, etc., which enable the number of parts and mounting area to be reduced. v ss x2 pd784046 x1 open x1 x2 pd784046 x1 x2 pd784046 91 chapter 4 clock generator user s manual u11515ej3v0ud 4.2 control registers 4.2.1 standby control register (stbc) stbc is a register used to set the standby mode. refer to chapter 18 standby function for details of the standby modes. to prevent erroneous entry into standby mode due to an inadvertent program loop, the stbc register can only be written to by a dedicated instruction. this instruction is the mov stbc, #byte instruction, and has a special code configuration (4 b ytes). a write is only performed if the 3rd and 4th bytes of the op code are mutual complements. if the 3rd and 4th bytes of the op c ode are not mutual complements, a write is not performed, and an op error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction which is the source of the error. the error source address can thus be found from the return address saved on the stack area. an endless loop will result if restore from an operand error is simply performed with an retb instruction. since an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler ra78k4, only the correct dedicated instruction is generated when the mov stbc, #byte instruction is written), system initialization should be performed by the program. other write instructions ( mov stbc, a , and stbc, # byte , set1 stbc.7 , etc.) are ignored, and no operation is performed. that is, a write is not performed on the stbc, and an interrupt such as an operand error interrupt is not generated . the stbc can be read at any time with a data transfer instruction. reset input sets the stbc register contents to 30h. the format of the stbc is shown in figure 4-3. figure 4-3. standby control register (stbc) format caution if the stop mode is used when external clock input is used, the extc bit of the oscillation stabilization time specification register (osts) must be set (1) before setting the stop mode. if the stop mode is used when the extc bit of the osts is in the cleared (0) state when external clock input is used, the pd784046 may be damaged or suffer reduced reliability. when setting the extc bit to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. 001100stphlt 76543210 stp 0 0 1 1 cpu operating mode control normal mode halt mode stop mode idle mode hlt 0 1 0 1 stbc address : 0ffc0h on reset : 30h r/w 92 chapter 4 clock generator user s manual u11515ej3v0ud 4.2.2 oscillation stabilization time specification register (osts) osts is a register used to specify the operation of the oscillator. the extc bit of the osts specifies whether a crystal/ ceramic resonator or an external clock is used. the stop mode can be set during use of external clock input, only when the extc bit is set (1). the osts can be read/written to by an 8-bit manipulation instruction. reset input clears the osts register contents to 00h. the format of the osts is shown in figure 4-4. figure 4-4. format of oscillation stabilization time specification register (osts) cautions 1. when using a crystal/ceramic oscillation, the extc bit must be cleared (0). if the extc bit is set (1), oscillation will stop. 2. if the stop mode is used with external clock input, the extc bit must be set (1) before setting the stop mode. if the stop mode is used when the extc bit is in the cleared (0) state, the pd784046 may be damaged or suffer reduced reliability. 3. when setting the extc bit to 1 during external clock input, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. when the extc bit is set to 1, the pd784046 operates on only the clock input to the x2 pin. extc 0000 osts2 osts1 osts0 76543210 extc 0 1 selects external clock inputs clock in reverse phase to clock input x1 pin to x2 pin. osts2 selects oscillation stabilization time (for details, refer to figure 18-4 ). osts1 osts0 osts address : 0ffcfh on reset : 00h r/w opens x2 pin when crystal/ceramic oscillation is used or when external clock is used. 93 chapter 4 clock generator user s manual u11515ej3v0ud 4.3 clock generator operation 4.3.1 clock oscillator (1) when using crystal/ceramic oscillation the clock oscillator starts oscillating when the reset signal is input, and stops oscillation when the stop mode is set by the standby control register (stbc). oscillation is resumed when the stop mode is released. (2) when using external clock the clock oscillator supplies the clock input from the x1 pin to the internal circuitry when the reset signal is input. the oscillator operates as follows when the extc bit of the oscillation stabilization time specification register (osts) is set to 1. the clock oscillator supplies the clock input to the x2 pin to the internal circuitry. the necessary circuit stops operating during the crystal/ceramic oscillation of the clock oscillator, to reduce the power dissipation. the stop mode can be used even when the external clock is input. cautions 1. when using a crystal/ceramic oscillation, the extc bit of the oscillation stabilization time specifica- tion register (osts) must be cleared (0). if the extc bit is set (1), oscillation will stop. 2. if the stop mode is used with external clock input, the extc bit of the osts must be set (1) before setting the stop mode. if the stop mode is used when the extc bit is in the cleared (0) state, not only will the clock generator consumption current not be reduced, but the pd784046 may also be damaged or suffer reduced reliability. 3. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. 4.3.2 frequency divider the frequency divider divides the output from the clock oscillator by two, and supplies the result to the cpu and peripheral hardware. 94 chapter 4 clock generator user s manual u11515ej3v0ud 4.4 cautions the following cautions apply to the clock generator. 4.4.1 when an external clock is input (1) if the stop mode is used with external clock input, the extc bit of the oscillation stabilization time specification registe r (osts) must be set (1). if the stop mode is used when the extc bit is in the cleared (0) state, the pd784046 may be damaged or suffer reduced reliability. (2) when setting the extc bit of the osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin. (3) when an external clock is input, this should be performed with a hcmos device, or a device with the equivalent drive capability. (4) a signal should not be extracted from the x1 and x2 pins. if a signal is extracted, it should be extracted from point a in figure 4-5. figure 4-5. signal extraction with external clock input (5) the wiring connecting the x1 pin to the x2 pin via an inverter, in particular, should be made as short as possible. x1 pd784046 x2 a 95 chapter 4 clock generator user s manual u11515ej3v0ud 4.4.2 when crystal/ceramic oscillation is used (1) as the oscillator is a high-frequency analog circuit, considerable care is required. the following points, in particular, require attention. the wiring should be kept as short as possible. no other signal lines should be crossed. avoid lines carrying a high fluctuating current. the oscillator capacitor grounding point should always be at the same potential as the v ss pin. do not ground to a ground pattern carrying a high current. a signal should not be taken from the oscillator. if oscillation is not performed normally and stably, the microcontroller will not be able to operate normally and stably, either. also, if a high-precision oscillation frequency is required, consultation with the oscillator manufacturer is recommended. figure 4-6. cautions on resonator connection cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed by the dotted line. v ss x1 x2 pd784046 96 chapter 4 clock generator user s manual u11515ej3v0ud figure 4-7. incorrect example of resonator connection (a) wiring of connected circuits is too long (b) crossed signal lines (e) signal extracted (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potentials at points a, b, and c fluctuate) v ss x1 x2 pd784046 v ss x1 x2 pd784046 pnm v ss x1 x2 pd784046 high alternating current v ss x1 x2 pd784046 pnm v dd ab c high alternating current v ss x1 x2 pd784046 97 chapter 4 clock generator user s manual u11515ej3v0ud (2) when the device is powered on, and when restoring from the stop mode, sufficient time must be allowed for the oscillation to stabilize. generally speaking, the time required for oscillation stabilization is several milliseconds when a crystal resonator is used, and several hundred microseconds when a ceramic resonator is used. an adequate oscillation stabilization period should be secured by the following means: <1> when powering-on : reset input (reset period) <2> when returning from stop mode : (i) reset input (reset period) (ii) time of the oscillation stabilization timer that automatically starts at the valid edge of nmi signal (set by the oscillation stabilization time specification register (osts)) (3) the extc bit of the oscillation stabilization time specification register (osts) must be cleared (0). if the extc bit is set (1), oscillation will stop. 98 user? manual u11515ej3v0ud chapter 5 port functions 5.1 digital input/output port the pd784046 is provided with the ports shown in figure 5-1, enabling various kinds of control to be performed. the function of each port is shown in table 5-1. for port 0, ports 4 to 6, and port 9, connection of an internal pull-up resistor can be specified by software when used as input ports. figure 5-1. port configuration port 0 port 1 port 2 port 3 port 4 port 5 port 6 p00 p03 p10 p13 p20 p27 p30 p37 p40 p47 p50 p57 p60 p63 p70-p77 8 port 7 port 9 p80-p87 8 port 8 p90 p94 99 chapter 5 port functions user s manual u11515ej3v0ud table 5-1. port function port name pin name function specification of pull-up resistor by software port 0 p00-p03 can be set in input or output mode bit-wise. all pins in input mode port 1 p10-p13 port 2 p20-p27 can be set in input or output mode bit-wise (however, p20 is input-only). port 3 p30-p37 can be set in input or output mode bit-wise. port 4 p40-p47 all pins in input mode port 5 p50-p57 port 6 p60-p63 port 7 p70-p77 input port port 8 p80-p87 port 9 p90-p94 can be set in input or output mode bit-wise. all pins in input mode 100 chapter 5 port functions user s manual u11515ej3v0ud 5.2 port 0 port 0 is a 4-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 0 mode register (pm0). each pin incorporates a software programmable pull-up resistor. in addition to the i/o port function, port 0 can output the port 0 buffer register (p0l) contents at any time interval as 4- bit real-time output ports. the real-time output port control register (rtpc) is used to select whether this port is used as a normal output port or a real-time output port. when reset is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 5-2. operation mode of port 0 pin name port mode real-time output port mode manipulation to use port 0 as real-time output port pin p00-p03 i/o port rtp0-rtp3 setting of p0ml bit of rtpc to 1 remark for details, refer to chapter 6 real-time output function . 5.2.1 hardware configuration the port 0 hardware configuration is shown in figure 5-2. figure 5-2. block diagram of port 0 pm0n port 0 mode register rd p0 p0n n = 0-3 rd p0 pull-up resistor option register l wr puo wr p0l internal bus wr rtpc wr pm0 rd rtpc puo0 p0ml rd p0l wr out output latch trigger real-time output port control register p0ln buffer register selector p0n 101 chapter 5 port functions user s manual u11515ej3v0ud 5.2.2 input/output mode/control mode setting the port 0 input/output mode is set by means of the port 0 mode register (pm0) as shown in figure 5-3. figure 5-3. format of port 0 mode register (pm0) when port 0 is used as a real-time output port, the p0ml bit of the real-time output port control register (rtpc) should be set (1) (refer to figure 5-4 ). when p0ml bit is set, the respective pin output buffer is turned on and the output latch contents are output to the pin irrespective of the contents of pm0. figure 5-4. format of real-time output port control register (rtpc) 1111 pm03 pm02 pm01 pm00 76543210 pm0n 0 1 specifies i/o mode of p0n pin (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) pm0 address : 0ff20h on reset : ffh r/w 000000 trgp0 p0ml 76543210 trgp0 enables or disables data transfer from buffer register to output latch by intcm40 (refer to figure 6-2 ). p0ml 0 1 specifies control mode of p00 through p03 pins i/o port mode real-time output port mode rtpc address : 0ff2eh on reset : 00h r/w 102 chapter 5 port functions user s manual u11515ej3v0ud 5.2.3 operating status port 0 is an input/output port (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . writes cannot be performed to the output latch of a port specified as a real-time output port. however, the output latch contents can be read even if it is set to the real-time output port mode. note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-5. port specified as output port p0n n = 0-3 rd out wr port internal bus output latch 103 chapter 5 port functions user s manual u11515ej3v0ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction, etc. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-6. port specified as input port caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. output latch p0n n = 0-3 rd in wr port internal bus 104 chapter 5 port functions user s manual u11515ej3v0ud 5.2.4 internal pull-up resistors port 0 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo0 bit of the pull-up resistor option register l (puol) and the port 0 mode register (pm0). when puo0 bit is 1, the internal pull-up resistor of only the pin set in the input mode by the real-time output port control register (rtpc) and pm0 is valid when the puo bit is 1. figure 5-7. pull-up resistor option register l (puol) format caution when using port 0 as the real-time output port, be sure to reset the puo0 bit to ??to not connect the internal pull-up resistor. remark when stop mode is entered, setting 00h in puol is effective in reducing the current consumption. 0 puo6 puo5 puo4 0 0 0 puo0 76543210 puo6 specifies pull-up resistor of port 6 (refer to figure 5-47 ). puo0 0 1 specifies pull-up resistor of port 0 not used with port 0 used with port 0 puol address : 0ff4eh on reset : 00h r/w puo5 specifies pull-up resistor of port 5 (refer to figure 5-41 ). puo4 specifies pull-up resistor of port 4 (refer to figure 5-35 ). 105 chapter 5 port functions user s manual u11515ej3v0ud figure 5-8. pull-up resistor specification (port 0) p01 input buffer p00 p02 p03 v dd port 0 mode register (pm0) puo0 (puol) internal bus 106 chapter 5 port functions user s manual u11515ej3v0ud 5.3 port 1 port 1 is a 4-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 1 mode register (pm1). in addition to their input/output port function, port also functions as timer output pins of timer/counter 2 and 3. the operating mode can be specified bit-wise by means of the port 1 mode control register (pmc1), as shown in table 5-3. the level of any pin can be read and tested at any time irrespective of the dual-function pin operation. when reset is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 5-3. port 1 operating modes pin name port mode control signal output mode manipulation to use port 1 as control pins p10 i/o port to20 output setting of pmc10 bit of pmc1 (1) p11 to21 output setting of pmc11 bit of pmc1 (1) p12 to30 output setting of pmc12 bit of pmc1 (1) p13 to31 output setting of pmc13 bit of pmc1 (1) 107 chapter 5 port functions user s manual u11515ej3v0ud 5.3.1 hardware configuration the port 1 hardware configuration is shown in figure 5-9. figure 5-9. block diagram of port 1 rd p1n rd p1n output latch wr pmc1n wr p1n rd pmc1n port 1 mode register to output pmc1n p1n pm1n wr pm1n selector p1n n = 0-3 internal bus 108 chapter 5 port functions user s manual u11515ej3v0ud 5.3.2 setting i/o mode/control mode the input/output mode of port 1 is set by using the port 1 mode register (pm1) per pin, as shown in figure 5-10. port 1 also functions as the timer output pins of timers/counters 2 and 3, in addition to the i/o port function, and can be set in the control mode by using the port 1 mode control register (pmc1) as shown in figure 5-11. figure 5-10. format of port 1 mode register (pm1) figure 5-11. format of port 1 mode control register (pmc1) 1111 pm13 pm12 pm11 pm10 76543210 pm1n 0 1 specifies i/o mode of p1n pin (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) pm1 address : 0ff21h on reset : ffh r/w 0000 pmc13 pmc12 pmc11 pmc10 76543210 pmc13 0 1 specifies control mode of p13 pin i/o port mode to31 output mode pmc1 address : 0ff41h on reset : 00h r/w pmc12 0 1 specifies control mode of p12 pin i/o port mode to30 output mode pmc11 0 1 specifies control mode of p11 pin i/o port mode to21 output mode pmc10 0 1 specifies control mode of p10 pin i/o port mode to20 output mode 109 chapter 5 port functions user s manual u11515ej3v0ud 5.3.3 operating status port 1 is an input/output port, and also functions as timer output pins of timer/counter 2 and 3. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-12. port specified as output port internal bus output latch p1n n = 0-3 rd out wr port 110 chapter 5 port functions user s manual u11515ej3v0ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction, etc. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-13. port specified as input port caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port that has the i/o mode or port mode and control mode, the contents of the output latch of the pin set in the input mode or control mode become undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. output latch p1n n = 0-3 rd in wr port internal bus 111 chapter 5 port functions user s manual u11515ej3v0ud (3) when specified as control signal output by setting (1) bits of the port 1 mode control register (pmc1), the port 1 can be used as control signal outputs bit- wise irrespective of the setting of the port 1 mode register (pm1). when a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. figure 5-14. control specification when pm1n (n = 0 to 3) bits of pm1 is set (1), the control signal pin level can be read by executing a port read instruction. when pm1 is reset (0), the pd784046 internal control signal status can be read by executing a port read instruction. p1n n = 0-3 pm1n = 0 pm1n = 1 rd control (output) internal bus 112 chapter 5 port functions user s manual u11515ej3v0ud 5.4 port 2 port 2 is an 8-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 2 mode register (pm2) (however, p20 is input-only). in addition to the input/output port function, port 2 also has a function to input control signals such as external interrupt signals, and output the timer signal of timer 0 (refer to table 5-4 ). p21 through p24 serve as the timer output pins of timer 0 if so specified by port 2 mode control register (pmc2). the level of each pin of this port can always be read or tested regardless of the multiplexed function. all the eight pins are schmitt trigger input pins to prevent malfunctioning due to noise. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 5-4. operation mode of port 2 (n = 0 to 7) mode port mode control signal output mode set condition pmc2n = 0 pmc2n = 1 pm2n = 0 pm2n = 1 pm2n = p20 input port/nmi input note p21 output port input port/intp0 input to00 output p22 input port/intp1 input to01 output p23 input port/intp2 input to02 output p24 input port/intp3 input to03 output p25 input port/intp4 input p26 input port/intp5 input/ti2 input p27 input port/intp6 input/ti3 input note the nmi input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled. remark : don t care (1) port mode (a) function as port pin each port pin set in the port mode by the port 2 mode control register (pmc2) can be set in the input or output mode in 1-bit units by the port 2 mode register (pm2) (however, p20 is fixed in the input mode). (b) function as control signal input pins if pmc2n (n = 0 to 7) bit of pmc2 is 0 and if pm2n (n = 0-7) bit of pm2 is 1 , the pins of port 2 can be used as the following control signal input pins. (i) nmi (non-maskable interrupt) this pin inputs an external non-maskable interrupt request. whether the interrupt request is detected at the rising or falling edge can be specified by using external interrupt mode register 0 (intm0). 113 chapter 5 port functions user s manual u11515ej3v0ud (ii) intp0 through intp6 (interrupt from peripherals) these pins input external interrupt requests. when the valid edge specified by external interrupt mode registers (intm0 and intm1) is detected on the intp0 to intp6 pins, an interrupt occurs (refer to chapter 15 edge detection function ). the intp0 through intp4 pins can also be used as external trigger input pins of each function, as follows: intp0 ... capture trigger input pin of capture/compare register 00 (cc00) of timer 0 intp1 ... capture trigger input pin of capture/compare register 01 (cc01) of timer 0 intp2 ... capture trigger input pin of capture/compare register 02 (cc02) of timer 0 intp3 ... capture trigger input pin of capture/compare register 03 (cc03) of timer 0 intp4 ... external trigger input pin of a/d converter (iii) ti2, ti3 (timer input) these are external clock input pins of timers/counters 2 and 3. (2) control signal output mode the p21 through p24 pins can be used as the timer output pins (to00 through to03) of timer 0 in 1-bit units if so specified by the port 2 mode control register (pmc2). 5.4.1 hardware configuration the port 2 hardware configuration is shown figure 5-15 through 5-17. figure 5-15. block diagram of p20 (port 2) internal bus p20 rd p20 nmi edge detection circuit 114 chapter 5 port functions user s manual u11515ej3v0ud figure 5-16. block diagram of p21 to p24 (port 2) figure 5-17. block diagram of p25 to p27 (port 2) rd p2n rd p2n output latch wr pmc2n wr p2n internal bus rd pmc2n port 2 mode register to output pmc2n p2n pm2n wr pm2n selector p2n n = 1-4 intp n-1 edge detection circuit internal bus p2n (n = 5-7) rd p2n rd p2n wr p2n p2n rd pm2n pm2n wr pm2n port 2 mode register output latch edge detection circuit intp n-1 115 chapter 5 port functions user s manual u11515ej3v0ud 5.4.2 setting i/o mode/control mode the input/output mode of p21 through p27 is set per pin by using the port 2 mode register (pm2), as shown in figure 5-18. p20 is input-only. p21 through p24 also functions as timer output pins of timer 0, in addition to as input/output port pins. to use these pins as timer output pins, set them in the control mode by using the port 2 mode control register (pmc2) as shown in figure 5-19. figure 5-18. format of port 2 mode register (pm2) cautions 1. even when using the p21 through p27 pins in the output port mode or timer output mode, intpn (n = 0 to 6) interrupt occurs depending on edge detection of the pin level. therefore, mask the interrupt before using the pins. 2. even when using the p26 and p27 pins as ti2 and ti3 pins, interrupts intp5 and intp6 occur. therefore, mask the interrupts before using the pins. figure 5-19. format of port 2 mode control register (pmc2) pm27 pm26 pm25 pm24 pm23 pm22 pm21 1 76543210 pm2n 0 1 specifies input/output mode of p2n pin (n = 1 to 7) output mode (output buffer on) input mode (output buffer off) pm2 address : 0ff22h on reset : ffh r/w 0 0 0 pmc24 pmc23 pmc22 pmc21 0 76543210 pmc24 0 1 specifies control mode of p24 pin i/o port mode/intp3 input mode to03 output mode pmc2 address : 0ff42h on reset : 00h r/w pmc23 0 1 specifies control mode of p23 pin i/o port mode/intp2 input mode to02 output mode pmc22 0 1 specifies control mode of p22 pin i/o port mode/intp1 input mode to01 output mode pmc21 0 1 specifies control mode of p21 pin i/o port mode/intp0 input mode to00 output mode 116 chapter 5 port functions user s manual u11515ej3v0ud 5.4.3 operating status port 2 is an i/o port (however, the p20 pin is input-only). the p21 through p24 pins can also be used as timer output pins of timer 0. (1) in output port mode the output latch is valid, and data is transferred between the output latch and accumulator by a transfer instruction. the contents of the output latch can be freely set by a logical operation instruction. data that has been written to the output latch is retained until new data is written to the output latch note . note including when the other bits of the same port are manipulated by a bit manipulation instruction. figure 5-20. port in output port mode internal bus output latch p2n n = 1-7 rd out wr port 117 chapter 5 port functions user s manual u11515ej3v0ud (2) in input port mode the level of a port pin can be loaded to the accumulator by using a transfer instruction. even in this case, data can be written to the output latch. data transferred from the accumulator by a transfer instruction is stored to all the output latches regardless of whether the input or output mode is specified. however, because the output buffer of a bit (pin) set in the input mode is in the high-impedance state, its contents are not output to the port pin (the contents of the output latch are output to the port pin when the mode of the pin is changed from input to output). the contents of the output latch of the pin set in the input port cannot be loaded to the accumulator. figure 5-21. port in input port mode note p20 does not have the circuit enclosed by the dotted line in the above figure. caution although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port in 8-bit units. if such an instruction is executed to manipulate a port with some pins set in the input mode and the others in the control mode, the contents of the output latch are undefined (except when a pin is manipulated by the set1 or clr1 instruction). especially, care must be exercised if the mode of some pins must be changed between input and output. the same applies when manipulating the port by using the other 8-bit operation instructions. output latch p2n n = 0-7 rd in wr port internal bus note 118 chapter 5 port functions user s manual u11515ej3v0ud (3) pin in control mode p21 to p24 can be used to output control signals in 1-bit units regardless of the setting of the port 2 mode register (pm2), if the corresponding bit of the port 2 mode control register (pmc2) is set (1). when using each pin as a control signal pin, the status of the control signal can be checked by executing an instruction that reads the port. figure 5-22. port in control mode if the pm2n (n = 1 to 4) bit of pm2 is set (1), and if an instruction that reads the port is executed, the level of the corresponding control signal pin can be read. if the port read instruction is executed when the pm2n bit is reset (0), the status of the control signal in the pd784046 can be read. p2n n = 1-4 pm2n = 0 pm2n = 1 rd control (output) internal bus 119 chapter 5 port functions user s manual u11515ej3v0ud 5.5 port 3 port 3 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 3 mode register (pm3). in addition to its function as an input/output port, port 3 also has various dual-function control signal pin functions. the operating mode can be specified bit-wise by means of the port 3 mode control register (pmc3), as shown in table 5-5. the pin level of all pins can always be read or tested regardless of the dual-function pin operation. when reset is input, port 3 is set as an input port (output high impedance state), and the output latch contents are undefined. table 5-5. port 3 operating modes (n = 0 to 7) mode port mode control signal input/output mode setting condition pmc3n = 0 pmc3n = 1 p30 input/output port to10 output p31 to11 output p32 rxd/si1 input p33 txd/so1 output p34 asck input/sck1 input/output p35 rxd2/si2 input p36 txd2/so2 output p37 asck2 input/sck2 input/output (a) port mode each port specified as port mode by the port 3 mode control register (pmc3) can be specified as input/output bit- wise by means of the port 3 mode register (pm3). (b) control signal input/output mode pins can be set as control pins bit-wise by setting the port 3 mode control register (pmc3). (i) to10, to11 (timer output) these are timer output pins of timer 1. (ii) rxd, rxd2 (receive data) these are serial data input pins of the asynchronous serial interface. (iii) txd, txd2 (transmit data) these are serial data output pins of the asynchronous serial interface. (iv) si1, si2 (serial input) these are serial data input pins of the 3-wire serial i/o. (v) so1, so2 (serial output) these are serial data output pins of the 3-wire serial i/o. (vi) asck, asck2 (asynchronous serial clock) these are external baud rate clock input pins. (vii) sck1, sck2 (serial clock) these are serial clock i/o pins of the 3-wire serial i/o. 120 chapter 5 port functions user s manual u11515ej3v0ud 5.5.1 hardware configuration the port 3 hardware configuration is shown in figures 5-23 to 5-25. figure 5-23. block diagram of p30, p31, p33 and p36 (port 3) figure 5-24. block diagram of p32 and p35 (port 3) rd p3n rd p3n output latch wr pmc3n wr p3n internal bus rd pmc3n port 3 mode register to, so, txd output pmc3n p3n pm3n wr pm3n selector p3n n = 0, 1, 3 and 6 rd p3n p3n n = 2, 5 rd p3n wr p3n internal bus si, rxd input wr pm3n port 3 mode register output latch wr pmc3n rd pmc3n pm3n p3n pmc3n 121 chapter 5 port functions user s manual u11515ej3v0ud figure 5-25. block diagram of p34 and p37 (port 3) rd p3n p3n n = 4 and 7 rd p3n output latch wr pmc3n wr p3n internal bus asck, sck input rd pmc3n external sck wr pm3n port 3 mode register sck output pmc32 p32 pm32 selector 122 chapter 5 port functions user s manual u11515ej3v0ud 5.5.2 input/output mode/control mode setting the port 3 input/output mode is set for each pin by means of the port 3 mode register (pm3) as shown in figure 5-26. in addition to their input/output port function, port 3 pins also have a dual function as various control signal pins, and the control mode is specified by means of the port 3 mode control register (pmc3) as shown in figure 5-27. figure 5-26. format of port 3 mode register (pm3) pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 pm3n 0 1 specifies i/o mode of p3n pin (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm3 address : 0ff23h on reset : ffh r/w 123 chapter 5 port functions user s manual u11515ej3v0ud figure 5-27. format of port 3 mode control register (pmc3) pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 76543210 pmc37 0 1 specifies control mode of p37 pin i/o port mode asck2/sck2 i/o mode pmc3 address : 0ff43h on reset : 00h r/w pmc36 0 1 specifies control mode of p36 pin i/o port mode txd2/so2 output mode pmc35 0 1 specifies control mode of p35 pin i/o port mode rxd2/si2 input mode pmc34 0 1 specifies control mode of p34 pin i/o port mode asck/sck1 i/o mode pmc33 0 1 specifies control mode of p33 pin i/o port mode txd/so1 output mode pmc32 0 1 specifies control mode of p32 pin i/o port mode rxd/si1 input mode pmc31 0 1 specifies control mode of p31 pin i/o port mode to11 output mode pmc30 0 1 specifies control mode of p30 pin i/o port mode to10 output mode 124 chapter 5 port functions user s manual u11515ej3v0ud 5.5.3 operating status port 3 is an input/output port, with a dual function as various control pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-28. port specified as output port internal bus output latch p3n n = 0-7 rd out wr port 125 chapter 5 port functions user s manual u11515ej3v0ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-29. port specified as input port output latch p3n n = 0-7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs and pins specified as control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. 126 chapter 5 port functions user s manual u11515ej3v0ud (3) when specified as control signal input/output by setting (1) bits of the port 3 mode control register (pmc3), port 3 can be used as control signal input or output bit-wise irrespective of the setting of the port 3 mode register (pm3). when a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. figure 5-30. control specification p3n n = 0-7 pm3n = 0 pm3n = 1 rd control (output) internal bus control (input) (a) when port is control signal output when pm3n (n = 0 to 7) bits of the port 3 mode register (pm3) is set (1), the control signal pin level can be read by executing a port read instruction. when pm3n bit is reset (0), the pd784046 internal control signal status can be read by executing a port read instruction. (b) when port is control signal input only the port 3 mode register (pm3) is set (1), control signal pin levels can be read by executing a port read instruction. caution pins that function as input pins in the control mode may malfunction if the corresponding bits of the port 3 mode control register (pmc3) are rewritten while the pins are operating. therefore, write pmc3 on initializing the system. 127 chapter 5 port functions user? manual u11515ej3v0ud 5.6 port 4 port 4 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 4 mode register (pm4). each pin incorporates a software programmable pull-up resistor. in addition to its function as input/output port, port 4 also functions as the low-order multiplexed address/data bus (ad0 to ad7) when external memory or i/os are extended. when reset is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. 5.6.1 hardware configuration the port 4 hardware configuration is shown in figure 5-31. figure 5-31. block diagram of port 4 rd puo wr puo puo4 internal data bus v dd p4n n = 0-7 input/ output control circuit wr pm4n pm4n internal address bus port 4 mode register wr p4n p4n output latch rd p4n pull-up resistor option register l mm0-mm3 chapter 5 port functions 128 user s manual u11515ej3v0ud 5.6.2 input/output mode/control mode setting the port 4 input/output mode is set for each pin by means of the port 4 mode register (pm4) as shown in figure 5-32. when port 4 is used as the address/data bus, it is set by means of the memory extension mode register (mm: refer to figure 17-1 ) as shown in table 5-6. figure 5-32. format of port 4 mode register (pm4) table 5-6. operation mode of port 4 bits of mm operation mode remark mm3 mm2 mm1 mm0 0000 port (p40-p47) 0011 address/data bus (ad0-ad7) setting prohibited when 0100 external 16-bit bus specified 0101 0110 0111 1000 1001 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 76543210 pm4n 0 1 specifies i/o mode of p4n pin (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm4 address : 0ff24h on reset : ffh r/w 129 chapter 5 port functions user s manual u11515ej3v0ud 5.6.3 operating status port 4 is an input/output port, with a dual function as the address/data bus (ad0 to ad7). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-33. port specified as output port internal bus output latch p4n n = 0-7 rd out wr port chapter 5 port functions 130 user s manual u11515ej3v0ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, when a bit specified as an input port, the output latch contents cannot be loaded into an accumulator. figure 5-34. port specified as input port output latch p4n n = 0-7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. (3) when used as address/data bus (ad0 to ad7) used automatically when an external access is performed. input/output instructions should not be executed on port 4. 131 chapter 5 port functions user s manual u11515ej3v0ud 5.6.4 internal pull-up resistors port 4 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo4 bit of the pull-up resistor option register l (puol) and the port 4 mode register (pm4). when the puo4 bit is 1, the internal pull-up resistor of only the pin set in the input mode by the memory expansion mode register (mm) and pm4 is valid. figure 5-35. format of pull-up resistor option register l (puol) caution when using port 4 as the address/data bus, be sure to reset the puo4 bit to ??to not connect the internal pull-up resistor. remark when stop mode is entered, setting 00h in puol is effective in reducing the current consumption. 0 puo6 puo5 puo4 0 0 0 puo0 76543210 puo6 specifies pull-up resistor of port 6 (refer to figure 5-47 ). puol address : 0ff4eh on reset : 00h r/w puo4 0 1 specifies pull-up resistor of port 4. not used with port 4 used with port 4 puo5 specifies pull-up resistor of port 5 (refer to figure 5-41 ). puo0 specifies pull-up resistor of port 0 (refer to figure 5-7 ). chapter 5 port functions 132 user s manual u11515ej3v0ud figure 5-36. pull-up resistor specification (port 4) p41 input buffer p40 p42 p46 p47 v dd port 4 mode register (pm4) puo4 (puol) internal bus 133 chapter 5 port functions user s manual u11515ej3v0ud 5.7 port 5 port 5 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by means of the port 5 mode register (pm5). each pin incorporates a software programmable pull-up resistor. in addition to as an i/o port, port 5 also functions as follows when an external memory or i/o is connected: when external 8-bit bus is specified as the high-order address bus (ad8 through ad15) when external 16-bit bus is specified as the high-order multiplexed address/data bus (ad8 through ad15) when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. 5.7.1 hardware configuration the port 5 hardware configuration is shown in figure 5-37. figure 5-37. block diagram of port 5 rd puo wr puo puo5 internal data bus internal address bus v dd p5n n = 0-7 wr pm5n pm5n port 5 mode register wr p5n p5n output latch rd p5n pull-up resistor option register l mm0-mm3 input/ output control circuit chapter 5 port functions 134 user s manual u11515ej3v0ud 5.7.2 input/output mode/control mode setting the port 5 input/output mode is set for each pin by means of the port 5 mode register (pm5) as shown in figure 5-38. when port 5 pins can be used as port or address pins in 2-bit units, the setting is performed by means of the memory extension mode register (mm: refer to figure 17-1 ) as shown in table 5-7. figure 5-38. format of port 5 mode register (pm5) table 5-7. operation mode of port 5 bits of mm operation mode remark mm3 mm2 mm1 mm0 p50 p51 p52 p53 p54 p55 p56 p57 0000 port (p50-p57) 0011 setting prohibited when external 0100ad8ad9 port 16-bit bus specified. ad8-ad13 0101ad8ad9 ad10 ad11 port used as address bus 0110ad8ad9 ad10 ad11 ad12 ad13 port 0111ad8ad9 ad10 ad11 ad12 ad13 ad14 ad15 1000 1001 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 76543210 pm5n 0 1 specifies i/o mode of p5n pin (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm5 address : 0ff25h on reset : ffh r/w 135 chapter 5 port functions user s manual u11515ej3v0ud 5.7.3 operating status port 5 is an input/output port, with a dual function as the address/data bus (ad8 to ad15). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-39. port specified as output port internal bus output latch p5n n = 0-7 rd out wr port chapter 5 port functions 136 user s manual u11515ej3v0ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-40. port specified as input port output latch p5n n = 0-7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit operation instructions. (3) when used as address/data bus (ad8 to ad15) port 5 is automatically used when an external address/data bus is accessed. at this time, do not execute an i/o instruction to port 5. 137 chapter 5 port functions user s manual u11515ej3v0ud 5.7.4 internal pull-up resistors port 5 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo5 bit of the pull-up resistor option register l (puol) and the port 5 mode register (pm5). when puo5 bit is 1, the internal pull-up resistor of only the pin set in the input port by the memory expansion mode register (mm) and pm5 is valid. figure 5-41. format of pull-up resistor option register l (puol) caution when port 5 is used as the address/data bus, and 0 must be set in puo5 bit so that internal pull-up resistor connection is not performed. remark when stop mode is entered, setting 00h in puol is effective in reducing the current consumption. 0 puo6 puo5 puo4 0 0 0 puo0 76543210 puo6 specifies pull-up resistor of port 6 (refer to figure 5-47 ). puol address : 0ff4eh on reset : 00h r/w puo5 0 1 specifies pull-up resistor of port 5. not used with port 5 used with port 5 puo4 specifies pull-up resistor of port 4 (refer to figure 5-35 ). puo0 specifies pull-up resistor of port 0 (refer to figure 5-7 ). chapter 5 port functions 138 user s manual u11515ej3v0ud figure 5-42. pull-up resistor specification (port 5) p51 input buffer p50 p52 p56 p57 v dd port 5 mode register (pm5) puo5 (puol) internal bus 139 chapter 5 port functions user s manual u11515ej3v0ud 5.8 port 6 port 6 is a 4-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 6 mode register (pm6). each pin is provided with a software programmable pull-up resistor. in addition to as an i/o port, this port also functions as the high-order address bus (a16 through a19) if so specified when an external memory or i/o is connected. when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. 5.8.1 hardware configuration the port 6 hardware configuration is shown in figures 5-43. figure 5-43. block diagram of port 6 rd puo wr puo puo6 v dd p6n n = 0-3 wr pm6n wr p6n pm6n port 6 mode register p6n output latch rd p6n pull-up resistor option register l mm0-mm3 internal data bus internal address bus input/ output control circuit chapter 5 port functions 140 user s manual u11515ej3v0ud 5.8.2 setting of i/o mode/control mode the input/output mode of port 6 is set in 1-bit units by using the port 6 mode register (pm6) as shown in figure 5-44. port 6 can be used as port pins or address pins in 2-bit units. whether it is used as port pins or address pins is specified by using the memory extension mode register (mm: refer to figure 17-1 ), as shown in table 5-8. figure 5-44. format of port 6 mode register (pm6) table 5-8. operation mode of port 6 bits of mm operation mode remark mm3 mm2 mm1 mm0 p60 p61 p62 p63 0000 port (p60-p63) 0011 setting prohibited when external 0100 16-bit bus specified. 0101 0110 0111 1000a16a17 port 1001a16a17a18a19 1111 pm63 pm62 pm61 pm60 76543210 pm6n 0 1 specifies i/o mode of p6n pin (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) pm6 address : 0ff26h on reset : ffh r/w 141 chapter 5 port functions user s manual u11515ej3v0ud 5.8.3 operating status port 6 is an input/output port, with a dual function as the address bus (a16 to a19). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 5-45. port specified as output port internal bus output latch p6n n = 0-3 rd out wr port chapter 5 port functions 142 user s manual u11515ej3v0ud (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 5-46. port specified as input port caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in the control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit manipulation instructions. (3) when used as address bus (a16 to a19) port 6 is automatically used as an external access bus. at this time, do not execute an i/o instruction to port 6. output latch p6n n = 0-3 rd in wr port internal bus 143 chapter 5 port functions user s manual u11515ej3v0ud 5.8.4 internal pull-up resistors port 6 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the puo6 bit of the pull-up resistor option register l (puol) and the port 6 mode register (pm6). the internal pull-up resistor of only the pin set in the input mode by pm6 is valid when the puo6 bit is 1. even when port 6 is specified as the address bus, specifying the use of the internal pull-up resistor is valid. to not connect the internal pull-up resistor, either set the output mode by using the port 6 mode register (pm6) (pm6n = 0: n = 0 to 3), or reset puo6 to 0. figure 5-47. format of pull-up resistor option register l (puol) remark when stop mode is entered, setting 00h in puol is effective in reducing the current consumption. 0 puo6 puo5 puo4 0 0 0 puo0 76543210 puo5 specifies pull-up resistor of port 5 (refer to figure 5-41 ). puol address : 0ff4eh on reset : 00h r/w puo6 0 1 specifies pull-up resistor of port 6 not used with port 6 used with port 6 puo4 specifies pull-up resistor of port 4 (refer to figure 5-35 ). puo0 specifies pull-up resistor of port 0 (refer to figure 5-7 ). chapter 5 port functions 144 user s manual u11515ej3v0ud figure 5-48. pull-up resistor specification (port 6) p61 p60 p62 p63 v dd port 6 mode register (pm6) puo6 (puol) internal bus input buffer 145 chapter 5 port functions user s manual u11515ej3v0ud 5.9 port 7 port 7 is an 8-bit input port. in addition to functioning as input port pins, its pins also function as an a/d converter analo g input (low-order 8 channels) pins (ani0 through ani7), and can always input analog signals. this port is set in the analog input mode by using a/d converter mode register (adm) (refer to figure 13-3 ). the level of each pin of this port can always be read or tested, regardless of the multiplexed function. 5.9.1 hardware configuration figure 5-49 shows the hardware configuration of port 7. figure 5-49. block diagram of port 7 5.9.2 notes (1) do not apply a voltage outside the range of av ss to av ref to the p70 through p77 pins when they are used as ani0 through ani7. for details, refer to 13.6 cautions in chapter 13 a/d converter . (2) if some pins of port 7 are used for analog input and the others are used for digital input, and if the digital input changes at analog input sampling timing, the a/d conversion accuracy is affected. when a high accuracy is necessary, do not use analog input and digital input simultaneously. internal bus p7n n = 0-7 rd in a/d converter chapter 5 port functions 146 user s manual u11515ej3v0ud 5.10 port 8 port 8 is an 8-bit input port. in addition to functioning as input port pins, its pins also function as an a/d converter analo g input (high-order 8 channels) pins (ani8 through ani15), and can always input analog signals. this port is set in the analog input mode by using a/d converter mode register (adm) (refer to figure 13-3 ). the level of each pin of this port can always be read or tested, regardless of the multiplexed function. 5.10.1 hardware configuration figure 5-50 shows the hardware configuration of port 8. figure 5-50. block diagram of port 8 5.10.2 cautions (1) do not apply a voltage outside the range of av ss to av ref to the p80 through p87 pins when they are used as ani8 through ani15. for details, refer to 13.6 cautions in chapter 13 a/d converter . (2) if some pins of port 8 are used for analog input and the others are used for digital input, and if the digital input changes at analog input sampling timing, the a/d conversion accuracy is affected. when a high accuracy is necessary, do not use analog input and digital input simultaneously. internal bus p8n n = 0-7 rd in a/d converter 147 chapter 5 port functions user s manual u11515ej3v0ud 5.11 port 9 port 9 is a 5-bit i/o port with an output latch. this port can be set in the input or output mode in 1-bit units by using port 9 mode register (pm9). each pin is provided with a software programmable pull-up resistor. in addition to the i/o port function, port 9 also functions as control signal pins (refer to table 5-9 ). p90 through p93 functions as a read/write strobe signals and address strobe signal when an external memory or i/o is connected. p94 functions as a wait signal input pin if so specified by port 9 mode control register (pmc9). when reset is input, this port is set in the input mode (output high-impedance status), and the contents of the output latch are undefined. table 5-9. operation mode of port 9 pin name port mode control signal i/o mode manipulation to use port 9 as control pins p90 i/o port rd specifying external memory expansion mode by p91 lwr mm0 through mm3 bits of memory expansion p92 hwr mode register (mm) p93 astb p94 wait setting of pmc94 bit of pmc9 to 1 remark for details, refer to chapter 17 local bus interface function . (a) port mode each port pin not set in the control mode can be set in the input or output mode in 1-bit units by using the port 9 mode register (pm9). (b) control signal i/o mode (i) rd (read strobe) this pin outputs a strobe signal to read an external memory. the operation of this pin is specified by the memory expansion mode register (mm). (ii) lwr, hwr (low/high write strobe) these pins output strobe signals to write an external memory. the operations of these pins are specified by the memory expansion mode register (mm). (iii) astb (address strobe) this is a timing signal output pin to latch the address information output from the ad0 through ad15 pins to access the external memory. the operation of this pin is specified by the memory expansion mode register (mm). (iv) wait (wait) this pin inputs a wait signal. the operation of this pin is specified by the port 9 mode control register (pmc9). chapter 5 port functions 148 user s manual u11515ej3v0ud 5.11.1 hardware configuration figure 5-51 and figure 5-52 show the hardware configuration of port 9. figure 5-51. block diagram of p90 to p93 (port 9) rd out rd in wr puo output latch pull-up resistor option register h rd puo wr p9n port 9 mode register puo9 p9n wr pm9n selector internal bus p9n n = 0-3 v dd external extension mode pm9n rd, lwr, hwr and astb signals 149 chapter 5 port functions user s manual u11515ej3v0ud figure 5-52. block diagram of p94 (port 9) rd p94 p94 rd p94 v dd pull-up resistor option register h wr puo wr p94 internal bus wait input rd puo wr pm94 port 9 mode register wr pmc94 rd pmc94 puo9 pm94 p94 pmc94 output latch chapter 5 port functions 150 user s manual u11515ej3v0ud 5.11.2 setting of i/o mode/control mode the input/output mode of port 9 is set per pin by using the port 9 mode register (pm9) as shown in figure 5-53. in addition to as an i/o port function, port 9 also has the following functions. p90 through p93 can be used as rd, lwr, hwr, and astb pins, if so specified by the memory extension mode register (mm: refer to figure 17-1 ), as shown in table 5-10. p94 can be used as a wait pin if so specified by the port 9 mode control register (pmc9) as shown in figure 5-54. figure 5-53. format of port 9 mode register (pm9) table 5-10. operation mode of p90 through p93 bits of mm operation mode remark mm3 mm2 mm1 mm0 p90 p91 p92 p93 0000 port (p90-p93) 0011rdlwrhwr astb setting prohibited when external 0100 16-bit bus specified. 0101 0110 0111 1000 1001 figure 5-54. format of port 9 mode control register (pmc9) 1 1 1 pm94 pm93 pm92 pm91 pm90 76543210 pm9n 0 1 specifies i/o mode of p9n pin (n = 0 to 4) output mode (output buffer on) input mode (output buffer off) pm9 address : 0ff29h on reset : ffh r/w 0 0 0 pmc94 0000 76543210 pmc94 0 1 specifies control mode of p94 pin i/o port mode wait input mode pmc9 address : 0ff49h on reset : 00h r/w 151 chapter 5 port functions user s manual u11515ej3v0ud 5.11.3 operating status port 9 is an input/output port and is multiplexed with control pins. (1) in output port mode the output latch is valid, and data is transferred between the output latch and accumulator by a transfer instruction. the contents of the output latch can be freely set by a logical operation instruction. data that has been written to the output latch is retained until new data is written to the output latch note . note including when the other bits of the same port are manipulated by a bit manipulation instruction. figure 5-55. port in output port mode internal bus output latch p9n n = 0-4 rd out wr port chapter 5 port functions 152 user s manual u11515ej3v0ud (2) in input port mode the level of a port pin can be loaded to the accumulator by using a transfer instruction. even in this case, data can be written to the output latch. data transferred from the accumulator by a transfer instruction is stored to all the latches regardless of whether the input or output mode is specified. however, because the output buffer of a bit (pin) set in the input mode is in the high-impedance state, its contents are not output to the port pin (the contents of the output latch are output to the port pin when the mode of the pin is changed from input to output). the contents of the output latch of the pin set in the input port cannot be loaded to the accumulator. figure 5-56. port in input port mode caution although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port in 8-bit units. if such an instruction is executed to manipulate a port with some pins set in the input mode and the others in the control mode, the contents of the output latch are undefined (except when a pin is manipulated by the set1 or clr1 instruction). especially, care must be exercised if the mode of some pins must be changed between input and output. the same applies when manipulating the port by using the other 8-bit operation instructions. output latch p9n n = 0-4 rd in wr port internal bus 153 chapter 5 port functions user s manual u11515ej3v0ud (3) pin in control mode p90 through p93 these pins are automatically used as the rd, lwr, hwr, and astb pins when the external memory or i/o is accessed. at this time, do not execute an i/o instruction to p90 through p93. p94 this pin can be used as the wait pin, regardless of the setting of the port 9 mode register (pm9), if the pmc94 bit of the port 9 mode control register (pmc9) is set (1). when using p94 as the wait pin, the status of the wait pin can be read by executing an instruction that reads the port only when the pm94 bit of pm9 is set (1). caution the pin that functions as an input pin in the control mode (p94) may malfunction if the pmc94 bit of the port 9 mode control register (pmc9) is rewritten while the pin is operating. therefore, write pmc9 on initializing the system. 5.11.4 internal pull-up resistor port 9 is provided with pull-up resistors. when the port must be pulled up, the number of components and the mounting area can be reduced by using these internal pull-up resistor. whether the internal pull-up resistors are used or not is specified per pin by using the puo9 bit of the pull-up resistor option register h (puoh) and port 9 mode register (pm9). when the puo9 bit is 1, the internal pull-up resistor of only the pin specified as follows is valid. p90 through p93 : set in input port mode by memory extension mode register (mm) and pm9 p94 : set in input mode by pm9 even when p94 is specified as the wait pin, specifying its use as a pull-up resistor is valid. in order not to connect the internal pull-up resistor, either specify the output mode by using pm9 (pm94 = 0), or reset (0) in puo9. figure 5-57. format of pull-up resistor option register h (puoh) caution when using p90 through p93 as the rd, lwr, hwr, and astb pins, be sure to reset the puo9 bit to 0 in order not to connect the internal pull-up resistor. remark resetting puoh to 00h is effective for decreasing the current consumption when the stop mode is set. 000000 puo9 0 76543210 puoh address : 0ff4fh on reset : 00h r/w puo9 0 1 specifies pull-up resistor of port 9 not used with port 9 used with port 9 chapter 5 port functions 154 user s manual u11515ej3v0ud figure 5-58. specifying pull-up resistor (port 9) p91 p90 p92 p93 p94 v dd port 9 mode register (pm9) puo9 (puoh) internal bus input buffer 155 chapter 5 port functions user? manual u11515ej3v0ud 5.12 port output data check function the pd784046 has a function to read the status of a port pin even in the output mode, to improve the reliability of the system (pin access mode). therefore, the output data and the actual pin status can be checked as necessary. to read the pin status, set (1) bit 0 of the port read control register (prdc), and then read the port. when reset is input, prdc is reset to 00h. figure 5-59. format of port read control register (prdc) example to check the output data of ports 0 (p0), 4 (p4), and 5 (p5) by using the pin access mode. test: di ; disables interrupts mov a, #5ah ; test data = 5ah mov p0, a ; sets 5ah to output latch mov p4, a mov p5, a set1 prdc.0 ; sets pin access mode (sets prdc) cmp a, p0 ; compares pin level and output latch contents bne $err0 ; error if unmatch cmp a, p4 bne $err4 cmp a, p5 bne $err5 clr1 prdc.0 ; returns to normal mode (resets prdc) ei ; enables interrupts 0000000 prdc0 76543210 prdc address : 0ff2fh on reset : 00h r/w prdc0 0 1 specifies operation mode normal mode pin access mode chapter 5 port functions 156 user s manual u11515ej3v0ud cautions 1. if a bit manipulation instruction is executed to manipulate the port, it is not executed normally in the pin access mode (prdc0 = 1). after checking the port, be sure to reset the mode to the normal mode (prdc0 = 0). 2. if an interrupt occurs in the pin access mode (prdc0 = 1), a bit manipulation instruction may be executed with this mode maintained, causing malfunctioning. be sure to set the di status before checking the port. do not use a macro service that manipulates the port. 3. occurrence of the non-maskable interrupt cannot be prevented. take the following measures in the program, depending on the system: do not manipulate the port in the non-maskable interrupt routine. save the level of prdc.0 at the beginning of the non-maskable interrupt routine, and restore it on returning execution from the interrupt routine. if prdc.0 is set (1), the switch enclosed by the dotted line in the figure below is connected to the pin, and the pin level is read. if a bit manipulation instruction is executed in this status, the pin level is read and the bit is manipulated, affec ting the value of the output latch. when prdc.0 is reset (0), the normal operation is performed. figure 5-60. concept of control (in output port mode) dedicated instructions (chkl, chkla) that are used to frequently check the port status are available. these instructions compare the pin status with the contents of the output latch (in port mode), or the pin status with the level of the internal control output signal (in control mode) through exclusive or. internal bus wr port output latch rd out pxn prdc.0 = 0 prdc.0 = 1 157 chapter 5 port functions user s manual u11515ej3v0ud example to check the pin status and the contents of the output latch using the chkl or chkla instruction. test: set1 p0.3 ; sets bit 3 of port 0 chkl p0 ; checks port 0 bne $err1 ; branches to error processing (err1) if contents of output . latch do not match pin status . . err1: chkla p0 ; checks defective bit bt a.3, $bit03 ; bit 3? bt a.2, $bit02 ; bit 2? bt a.1, $bit01 ; bit 1? br $bit00 ; bit 0 is defective if all other bits are valid. cautions 1. use the chkl or chkla instruction when the prdc0 bit of the port read control register (prdc) is 0 (normal mode). 2. the result of comparison by the chkl or chkla instruction always matches, regardless of whether the pin set in the input port mode is set in the port mode or control mode. because the input level of the input-only pin is read when the chkl or chkla instruction is executed, because this pin does not have an output latch. in other words, executing the chkl or chkla instruction to the input-only pin is practically invalid, therefore, do not use the instruction to manipulate such a pin. 3. to check the output level of a port with some of its bits set in the control output mode and others in the port output mode, using the chkl or chkla instruction, execute the instruction after changing the input/output mode of the control output pin to the input mode (the output level of the control output pin changes asynchronously and therefore cannot be checked by the chkl or chkla instruction). chapter 5 port functions 158 user s manual u11515ej3v0ud 5.13 cautions (1) all the port pins go into a high-impedance state when the reset signal is input (the internal pull-up resistor is also disconnected from the pin). if it is necessary to prevent a pin from going into a high-impedance state during reset input, use an external circuit. (2) bits 1, 3, and 7 of the pull-up resistor option register l (puol) that specifies connection of the internal pull-up resistor , and bits 0 and 2 through 7 of the pull-up resistor option register h (puoh) are fixed to 0 . however, if 1 is written to these bits, 1 can be read with an in-circuit emulator. (3) the contents of the output latch are not initialized by reset input. to use a port as an output port, be sure to initialize the output latch before turning on the output buffer. unless the output buffer is initialized before the output buffer is turned on, unexpected data is output to the output port. in the same way, when using a port as control pins, be sure to initialize the internal peripheral hardware, and then set the port in the control mode. (4) although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port in 8-bit units. if such an instruction is executed to manipulate a port with some pins set in the input/output mode and the others in the port mode and in the control mode, the contents of the output latch are undefined (except when a pin is manipulated by the set1 or clr1 instruction). especially, care must be exercised if the mode of some pins must be changed between input and output. the same applies when manipulating the port by using the other 8-bit operation instructions. (5) to use port 0 as a real-time output port, be sure to reset the puo0 bit of the pull-up resistor option register l (puol) to 0 , in order not to connect the internal pull-up resistor. (6) even when using the p21 through p27 pins in the output port mode or timer output mode, intpn (n = 0 to 6) interrupt occurs depending on the edge detection of the pin level. mask the interrupt before using these pins. (7) even when using the p26 and p27 pins as ti2 and ti3 pins, interrupts intp5 and intp6 occur. mask the interrupts before using these pins. (8) the pins used as input pins in the control mode (p32, p34, p35, p37, and p94) may malfunction if the corresponding bit of the port n mode control register (pmcn: n = 3, 9) while these pins are operating. therefore, write pmcn on initializing the system. (9) when using ports 4 and 5, and p90 through p93 as pins in the external memory extension mode, be sure to reset the corresponding bits of the pull-up resistor option registers (puol, puoh) to 0 , in order not to connect the internal pull-up resistor. (10) do not apply a voltage outside the range of av ss to av ref to p70 through p77 and p80 through p87 used as ani0 through ani15. for details, refer to 13.6 cautions in chapter 13 a/d converter . (11) if some pins of ports 7 and 8 are used for analog input and the others are used for digital input, and if the digital input changes at analog input sampling timing, the a/d conversion accuracy is affected. when a high accuracy is necessary, do not use analog input and digital input simultaneously. 159 chapter 5 port functions user s manual u11515ej3v0ud (12) a bit manipulation instruction executed to manipulate the port is not executed normally in the pin access mode (prdc0 of port read control register (prdc) = 1). after checking the port, be sure to reset the mode to the normal mode (prdc0 = 0). (13) if an interrupt occurs in the pin access mode (prdc0 of prdc = 1), a bit manipulation instruction may be executed with this mode maintained, causing malfunctioning. be sure to set the di status before checking the port. do not use a macro service that manipulates the port. (14) occurrence of the non-maskable interrupt cannot be prevented in the pin access mode (prdc0 of prdc = 1). take the following measures by using the program, depending on the system: do not manipulate the port in the non-maskable interrupt routine. save the level of prdc.0 at the beginning of the non-maskable interrupt routine, and restore it on returning execution from the interrupt routine. (15) use the chkl or chkla instruction when the prdc0 bit of prdc is 0 (normal mode). (16) the result of comparison by the chkl or chkla instruction always matches, regardless of whether the pin set in the input port mode is set in the port mode or control mode. because the input level of the input-only pin is read when the chkl or chkla instruction is executed, because this pin does not have an output latch. in other words, executing the chkl or chkla instruction to the input-only pin is practically invalid, and therefore, do not use the instruction to manipulate such a pin. (17) to check the output level of a port with some of its bits set in the control output mode and others in the port output mode, by using the chkl or chkla instruction, execute the instruction after changing the input/output mode of the control output pin to the input mode (the output level of the control output pin changes asynchronously and therefore cannot be checked by the chkl or chkla instruction). 160 user? manual u11515ej3v0ud chapter 6 real-time output function 6.1 configuration and function the real-time output function is implemented by hardware, including primarily port 0 and the port 0 buffer registers (p0l), shown in figure 6-1. the real-time output function refers to the transfer to the output latch by hardware of data prepared in the p0l beforehand, simultaneously with the generation of an interrupt from timer 4 or external interrupt, and its output off-chip. the pins that output the data off-chip are called real-time output ports. 4 bits 1 channel are handled as real-time output data. by combining the real-time output function with the macro service function described later, the functions of a pattern generator with programmable timing are implemented without software intermediation. this is ideally suited to stepping motor control, for example. figure 6-1 shows the block diagram of the real-time output port. figure 6-1. block diagram of real-time output port internal bus 8 real-time output port control register (rtpc) output trigger control circuit intcm40 (from timer 4) 4 port 0 buffer register (p0l) 4 output latch (p0) rtp0 rtp3 rtp2 rtp1 4 161 chapter 6 real-time output function user s manual u11515ej3v0ud 6.2 real-time output port control register (rtpc) rtpc is an 8-bit register that specifies the function of port 0 (input/output port or real-time output port). this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 6-2 shows the format of this register. when reset is input, the value of this register is reset to 00h. figure 6-2. format of real-time output port control register (rtpc) caution when the p0ml bit is set (1), the output buffer of the corresponding port pin turns on regardless of the contents of the port 0 mode register (pm0), and the contents of the output latch of port 0 are output. before specifying port 0 as the real-time output port, therefore, initialize the contents of the output latch. 000000 trgp0 p0ml 76543210 rtpc address : 0ff2eh on reset : 00h r/w trgp0 0 1 enables or disables data transfer from buffer register to output latch by intcm40 enables disables p0ml 0 1 specifies control mode of p00 through p03 pins i/o port mode real-time output port mode 162 chapter 6 real-time output function user s manual u11515ej3v0ud 6.3 operation when port 0 is specified as the real-time output port (p0ml of the real-time output port control register (rtpc) = 1) and trgp of rtpc is reset to 0, the contents of the buffer register (p0l) are loaded to the output latch in synchronization with occurrence of the match interrupt (intcm40) of timer 4, and output to the rtp0 through rtp3 pins. the output data of the rtp0 through rtp3 pins can be changed to the value of the buffer register at time intervals specified by the value set in advance to the compare register of timer 4 (cm40). by using this real-time output port function and the macro service function in combination, the output data of the rtp0 through rtp3 pins can be sequentially changed at any interval time. figure 6-3. operation timing of real-time output port intcm40 interrupt request cpu operation timer 4 0h ffffh output latches p00-p03 timer started port 0 buffer register p0l d01 cm40 cm40 cm40 cm40 d01 d02 d00 port 0 buffer register and compare register overwrite by software processing or macro service (refer to 16.8 macro service function ) d03 d04 d02 d03 163 chapter 6 real-time output function user s manual u11515ej3v0ud 6.4 example of use each time the contents of timer 4 timer register 4 (tm4) and compare register (cm40) match, the contents of port 0 buffer register (p0l) are output to rtp0 through rtp3. at this time, the next data to be output and the timing at which the output is to be changed next are set in the service routine for the simultaneously generated interrupt (refer to figure 6-4 ). refer to chapter 11 timer 4 for the method of using timer/counter 1. the control register settings are shown in figure 6-5, the setting procedure in figure 6-6, and the processing in the interrupt processing routine in figure 6-7. figure 6-4. operation timing of real-time output port intcm40 interrupt request timer 4 0h ffffh output pins rtp0-rtp3 d01 d02 port 0 buffer register p0l d02 d03 cm40 cm40 cm40 cm40 output latches p00-p03 d01 d02 d03 d04 d03 d01 d00 d00 p0l and cm40 overwritten by intcm40 interrupt p0l contents transferred to output latch on match of tm4 and cm40 timer started output buffer turned on next data to be output is set in p0l initial output data is set in output latches p00 to p03 hi-z 164 chapter 6 real-time output function user s manual u11515ej3v0ud figure 6-5. settings for real-time output function control register figure 6-6. setting procedure of real-time output function 7 0 rtpc 6 0 5 0 4 0 3 0 2 0 1 1 0 1 p00 to p03 used as real-time output port (rtp0 to rtp3) data transfer to output latch from p0l by intp0 disabled real-time output port set initial value to p0 output latch set next value to be output in p0l set real-time output port control register (rtpc) set timer 4 intcm40 interrupt timer start 165 chapter 6 real-time output function user s manual u11515ej3v0ud figure 6-7. interrupt request processing when real-time output function is used 6.5 cautions (1) when p0ml bit of real-time output port control register (rtpc) is set (1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (pm0). the output latch contents should therefore be initialized before making a real-time output port specification. (2) when the port is specified as a real-time output port, values cannot be directly written to the output latch by software. therefore, the initial value of the output latch must be set by software before specifying use as a real-time output port. also, if the need arises to forcibly set the output data to a fixed value while the port is being used as a real-time output port, you should change the port to a normal output port by manipulating the real-time output port control register (rtpc), then write the value to be output to the output latch. timer interrupt interval time setting set next value to be output in p0l return 166 user? manual u11515ej3v0ud chapter 7 outline of timer/counter the pd784026 incorporates two 16-bit timer/counter units and three 16-bit time units. these timer/counter and timer units can be used as fifteen units of timers because the pd784046 supports fifteen interrupt requests. table 7-1. operations of timer/counters name timer 0 timer 1 timer/counter 2 timer/counter 3 timer 4 item operation interval timer 4 ch 2 ch 2 ch 2 ch 2 ch mode external event counter function timer output 4 ch 2 ch 2 ch 2 ch toggle output set/reset output pwm/ppg output real-time output overflow interrupt number of interrupt requests 5 3223 167 chapter 7 outline of timer/counter user? manual u11515ej3v0ud figure 7-1. block diagram of timer/counter (1/3) timer 0 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 timer 1 prescaler: f clk /8, f clk /16, f clk /32, f clk /64, f clk /128 prescaler timer register 0 (tm0) f clk intp0 intp1 intp2 intp3 intov0 edge detection capture/compare register 00 (cc00) intp0 intcc00 match to00 pulse output control edge detection capture/compare register 01 (cc01) intp1 intcc01 match to01 edge detection capture/compare register 02 (cc02) intp2 intcc02 match to02 pulse output control edge detection capture/compare register 03 (cc03) intp3 intcc03 match to03 f clk prescaler timer register 1 (tm1) compare register 10 (cm10) intcm10 match to10 pulse output control compare register 11 (cm11) intcm11 match to11 clear control intov1 168 chapter 7 outline of timer/counter user s manual u11515ej3v0ud figure 7-1. block diagram of timer/counter (2/3) timer/counter 2 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 timer/counter 3 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 f clk prescaler timer/register 2 (tm2) compare register 20 (cm20) intcm20 match to20 pulse output control compare register 21 (cm21) intcm21 match to21 clear control selector ti2/intp5 edge detection intp5 f clk prescaler timer/register 3 (tm3) compare register 30 (cm30) intcm30 match to30 pulse output control compare register 31 (cm31) intcm31 match to31 clear control selector ti3/intp6 edge detection intp6 169 chapter 7 outline of timer/counter user s manual u11515ej3v0ud figure 7-1. block diagram of timer/counter (3/3) timer 4 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 f clk prescaler timer register 4 (tm4) compare register 40 (cm40) intcm40 match to real-time output port compare register 41 (cm41) match intcm41 clear control intov4 170 user? manual u11515ej3v0ud chapter 8 timer 0 8.1 function timer 0 is a 16-bit free running timer. because this timer has four capture/compare registers and a toggle and set/reset timer output functions, it can be used as an interval timer or to measure pulse width. (1) interval timer when timer 0 is used as an interval timer, it generates an internal interrupt at interval set in advance. table 8-1. interval time of timer 0 minimum interval time note maximum interval time resolution 4/f clk (0.25 s) 2 16 4/f clk (16.4 ms) 4/f clk (0.25 s) 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) 8/f clk (0.5 s) 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) 16/f clk (1.0 s) 32/f clk (2.0 s) 2 16 32/f clk (131 ms) 32/f clk (2.0 s) 64/f clk (4.0 s) 2 16 64/f clk (262 ms) 64/f clk (4.0 s) ( ): at f clk = 16 mhz note the minimum interval time is limited by the data transfer processing time. consider the interrupt processing time or macro service processing time used (refer to table 16-11 interrupt acceptance processing time and table 16-12 macro service processing time ). chapter 8 timer 0 171 user? manual u11515ej3v0ud (2) pulse width measurement timer 0 can be used to detect the pulse width of a signal input to an external interrupt request input pin (intp0 to intp3). table 8-2. pulse width measurement range of timer 0 measurable pulse width note 1 resolution 4/f clk (0.25 s) note 2 ?2 16 4/f clk (16.4 ms) 4/f clk (0.25 s) 8/f clk (0.5 s) note 2 ?2 16 8/f clk (32.8 ms) 8/f clk (0.5 s) 16/f clk (1.0 s) note 2 ?2 16 16/f clk (65.5 ms) 16/f clk (1.0 s) 32/f clk (2.0 s) note 2 ?2 16 32/f clk (131 ms) 32/f clk (2.0 s) 64/f clk (4.0 s) note 2 ?2 16 64/f clk (262 ms) 64/f clk (4.0 s) ( ): at f clk = 16 mhz notes 1. the minimum measurable pulse width changes depending on the sampling clock selected by the noise protection control register (npc). the minimum measurable pulse width is either of the values in the above table and the table below, whichever greater. sampling clock minimum pulse width f clk 4/f clk (0.25 s) f clk /4 16/f clk (1.0 s) 2. this value is limited by the data transfer processing time. consider the interrupt processing time or macro service processing time used (refer to table 16-11 interrupt acceptance processing time and table 16- 12 macro service processing time ). 8.2 configuration timer 0 consists of the following registers: timer register (tm0) 1 capture/compare register (cc0n) 4 (n = 0 to 3) figure 8-1 shows the block diagram of timer 0. chapter 8 timer 0 172 user? manual u11515ej3v0ud figure 8-1. block diagram of timer 0 internal bus internal bus 1/8 es21 es20 es11 es10 es01 es00 external interrupt mode register 0 (intm0) external interrupt mode register 1 (intm1) es31 es30 1/8 16 capture/compare register 00 (cc00) 16 16 16 16 match capture/compare register 01 (cc01) capture/compare register 02 (cc02) 16 16 16 match 16 16 timer output control register 0 (toc0) ento03 1/8 alv03 ento02 alv02 ento01 alv01 ento00 alv00 edge detection circuit intp0 edge detection circuit intp1 edge detection circuit intp2 edge detection circuit intp3 intp0 intp1 intp2 intp3 capture trigger capture trigger capture trigger capture trigger f clk prescaler selector f clk /64 f clk /32 f clk /16 f clk /8 f clk /4 1/8 prm02 prm01 prm00 prescaler mode register (prm) timer unit mode register 0 (tum0) tom02 tom00 cms03 cms02 cms01 cms00 1/8 16 timer register 0 (tm0) 16 16 16 match capture/compare register 03 (cc03) 16 16 16 match overflow clear reset timer mode control register (tmc) 1/8 ce0 to03 intcc03 intov0 output control circuit to02 intcc02 output control circuit to01 intcc01 output control circuit to00 intcc00 output control circuit chapter 8 timer 0 173 user s manual u11515ej3v0ud (1) timer register 0 (tm0) tm0 is a timer register that counts up the count clock specified by the prescaler mode register (prm). counting of this timer register is enabled or disabled by the timer mode control register (tmc). the timer register can be only read by using a 16-bit manipulation instruction. when reset is input, tm0 is cleared to 0000h and stops counting. (2) capture/compare registers (cc00 through cc03) cc0n (n = 0 to 3) is a 16-bit register that can be used as a compare register to detect match between its value and the count value of tm0 or as a capture register to capture the count value of tm0. whether cc0n is used as a compare register or capture register is specified by the timer unit mode register 0 (tum0). this register can be read or written by using a 16-bit manipulation instruction. when reset is input, the value of this register is undefined. (a) as compare register when used as a compare register, cc0n functions as a 16-bit register that holds the value determining the cycle of the interval timer operation. when the contents of cc0n matches with the contents of tm0, an interrupt request (intcc0n: n = 0 to 3) and a timer output control signal are generated. when the ce0 bit of the timer mode control register (tmc) is 0 and timer 0 is stopped, the capture operation is not performed. (b) as capture register when used as a capture register, cc0n functions as a 16-bit register that captures the contents of tm0 in synchronization with the valid edge (capture trigger) input from an external interrupt input pin (intpn: n = 0 to 3). the contents of cc0n are retained until the next capture trigger is generated. (3) edge detection circuit the edge detection circuit detects the valid edge of an external input. it detects the valid edge of the intp0 through intp3 pin inputs, and generates an external interrupt request (intp0 to intp3) and capture trigger. the valid edge is specified by the external interrupt mode registers (intm0 and intm1) (for the details of intm0 and intm1, refer to figures 15-1 and 15-2 ). (4) output control circuit when the contents of cc0n (n = 0 to 3) and the contents of tm0 match, the timer output can be inverted. a square wave can be output from a timer output pin (to00 to to03) if so specified by the timer output control register 0 (toc0). the to00 and to02 pins can also output a set and reset signals if so specified by the timer unit mode register 0 (tum0). the timer output can be enabled or disabled by toc0. when the timer output is disabled, a fixed level is output to the to0n (n = 0 to 3) pin (the output level is fixed by toc0). (5) prescaler the prescaler generates a count clock by dividing the internal system clock. the clock generated by the prescaler is selected by the selector, and tm0 performs the count operation by using this clock as a count clock. (6) selector the selector selects one of the five signals generated by dividing the internal system clock as the count clock of tm0. chapter 8 timer 0 174 user s manual u11515ej3v0ud 8.3 timer 0 control register (1) timer unit mode register 0 (tum0) tum0 is a register that specifies the output mode of the timer output pins (to00, to02, and to10) of timers 0 and 1, controls the clear operation of the timer register 1 (tm1), and specifies the operations of the capture/compare registers (cc00 through cc03) of timer 0. this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 8-2 shows the format of tum0. when reset is input, the value of tum0 is cleared to 00h. figure 8-2. format of timer unit mode register 0 (tum0) tom10 clr1 tom02 tom00 cms03 cms02 cms01 cms00 76543210 tom10 specifies output mode of to10 pin (refer to figure 9-2 ). tum0 address : 0ff30h on reset : 00h r/w tom0n 0 1 specifies output mode of to0n pin (n = 0, 2) toggle output set/reset output clr1 controls clear operation of tm1 (refer to figure 9-2 ). cms0n 0 1 specifies operation of cc0n (n = 0 to 3) capture register compare register chapter 8 timer 0 175 user s manual u11515ej3v0ud (2) timer mode control register (tmc) tmc is a register that controls the count operation of timer registers 0 and 1 (tm0 and tm1). this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 8-3 shows the format of tmc. when reset is input, the value of this register is cleared to 00h. figure 8-3. format of timer mode control register (tmc) (3) timer output control register 0 (toc0) toc0 is a register that specifies the operation and active level of the timer output pins (to00 through to03) of timer 0. this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 8-4 shows the format of toc0. when reset is input, the value of this register is cleared to 00h. figure 8-4. format of timer output control register 0 (toc0) ce1 0 0 0 ce0 0 0 0 76543210 ce1 controls count operation of tm1 (refer to figure 9-3 ). tmc address : 0ff31h on reset : 00h r/w ce0 0 1 controls count operation of tm0 clears and stops counting enables counting ento03 alv03 ento02 alv02 ento01 alv01 ento00 alv00 76543210 toc0 address : 0ff32h on reset : 00h r/w ento0n 0 1 specifies operation of to0n pin (n = 0 to 3) outputs alv0n enables pulse output alv0n 0 1 specifies active level of to0n pin (n = 0 to 3) low level high level chapter 8 timer 0 176 user s manual u11515ej3v0ud (4) prescaler mode register (prm) prm is a register that specifies the count clock of timer registers 0 and 1 (tm0 and tm1). this register can be read or written by using an 8-bit manipulation instruction. figure 8-5 shows the format of prm. when reset is input, the value of this register is cleared to 00h. figure 8-5. format of prescaler mode register (prm) remark f clk : internal system clock 0 prm12 prm11 prm10 0 prm02 prm01 prm00 76543210 prm address : 0ff38h on reset : 00h r/w prm12 specifies count clock of tm1 (refer to figure 9-5 ). prm02 0 0 0 0 1 specifies count clock of tm0. f clk /4 f clk /8 f clk /16 f clk /32 f clk /64 setting prohibited prm11 prm10 prm01 0 0 1 1 0 prm00 0 1 0 1 0 count clock [hz] resolution [ s] 0.25 0.5 1.0 2.0 4.0 other (f clk = 16 mhz ) chapter 8 timer 0 177 user s manual u11515ej3v0ud 8.4 operation of timer register 0 (tm0) 8.4.1 basic operation timer 0 counts up by using the count clock specified by the prescaler mode register (prm). counting is enabled or disabled by the ce0 bit of the timer mode control register (tmc). when the ce0 bit is set (1) by software, tm0 is set to 0001h at the first count clock, and starts counting up. when the ce0 bit is cleared (0) by software , tm0 is immediately cleared to 0000h, and stops the capture operation and generation of the match signal. if the ce0 bit is set (1) while it has been already set (1), tm0 is not cleared but continues counting. if a count clock is input when tm0 reaches ffffh, tm0 is cleared to 0000h, and an overflow interrupt (intov0) occurs, but tm0 continues counting. when reset is input tm0 is cleared to 0000h and stops counting. chapter 8 timer 0 178 user s manual u11515ej3v0ud figure 8-6. basic operation of timer register 0 (tm0) (a) count started count stopped count started (c) operation when tm0 = ffffh (b) when ??is written to the ce0 bit again after the count starts tm0 ce0 0h 1h 2h 3h ffh 100h 101h 1h 2h 0h count started ce0 1 count stopped ce0 0 count started ce0 1 count clock tm0 ce0 0h 1h 2h 3h 4h 5h 6h 7h count started ce0 1 rewritten ce0 1 count clock tm0 intov0 interrupt request fffeh ffffh 0h count clock 1h chapter 8 timer 0 179 user s manual u11515ej3v0ud 8.4.2 clear operation timer register 0 (tm0) is cleared by clearing (0) the ce0 bit of the timer mode control register (tmc). tm0 is cleared as soon as the ce0 bit has been cleared (0). figure 8-7. clear operation of timer register 0 (tm0) (a) basic operation (c) restart after count clock input after clearance (b) restart before count clock input after clearance tm0 ce0 n count clock n-1 0 tm0 ce0 n 0 count clock n-1 1 2 3 if the ce0 bit is set (1) before this count clock, the count starts from 1 on the count clock. tm0 ce0 n count clock n-1 0 0 1 2 if the ce0 bit is set (1) from this count clock onward, the count starts from 1 on the count clock after the ce0 bit is set (1). chapter 8 timer 0 180 user s manual u11515ej3v0ud 8.5 operation of capture/compare register 8.5.1 compare operation timer 0 performs a compare operation by comparing the value set to a capture/compare register (cc00 to cc03) specified as a compare register with the count value of a timer register 0 (tm0). if the count value of tm0 matches with the value set in advance to cc0n (n = 0 to 3) as a result of counting by tm0, the timer sends a match signal to the output control circuit, and at the same time, generates an interrupt request signal (intcc0n: n = 0 to 3). table 8-3. interrupt request signal from compare register (timer 0) compare register interrupt request signal cc00 intcc00 cc01 intcc01 cc02 intcc02 cc03 intcc03 remark cc00 through cc03 are capture/compare registers. whether these registers are used as capture registers or compare registers is specified by the timer unit mode register 0 (tum0). timer 0 has four timer output pins (to00 through to03). table 8-4 shows the operation mode of each of these pins (for details, refer to 8.6 basic operation of output control circuit ). table 8-4. operation mode of timer output pin (timer 0) timer output pin output operation mode specification of operation mode to00 toggle set/reset tom00 bit of tum0 to01 toggle to02 toggle set/reset tom02 bit of tum0 to03 toggle chapter 8 timer 0 181 user s manual u11515ej3v0ud figure 8-8. compare operation (timer 0) intcc00 interrupt request tm0 count value 0h ffffh count started ce0 1 cc00 value cc01 value ffffh cc00 value cc01 value intcc01 interrupt request to00 pin output ento00 = 1 alv00 = 1 intov0 interrupt request match match match match to01 pin output ento01 = 1 alv01 = 0 inactive level inactive level chapter 8 timer 0 182 user s manual u11515ej3v0ud 8.5.2 capture operation in synchronization with an external trigger, timer 0 also performs a capture operation that captures and retains the count value of timer register 0 (tm0) to a capture register. as an external trigger, the valid edge detected from an external interrupt request input pin (intp0 to intp3) is used (capture trigger). in synchronization with this capture trigger, the count value of tm0 is captured to a capture/compare register (cc0n: n = 0 to 3) specified as a capture operation in synchronization with intpn (n = 0 to 3). the contents of cc00 through cc03 are retained until the following capture triggers each corresponding to cc00 to cc03 are generated. table 8-5. capture trigger signal to capture register (timer 0) capture register capture trigger signal cc00 intp0 cc01 intp1 cc02 intp2 cc03 intp3 remark cc00 through cc03 are capture/compare registers. whether these registers are used as capture registers or compare registers is specified by the timer unit mode register 0 (tum0). the valid edge of the capture trigger is specified by external interrupt mode registers (intm0 and intm1) if the capture trigger is specified so that both the rising and falling edges are valid, the width of an externally input pulse can be measure d. if the capture trigger is generated with either of the edges specified as valid, the cycle of an input pulse can be measured. chapter 8 timer 0 183 user s manual u11515ej3v0ud figure 8-9. capture operation (timer 0) remark dn: tm0 count value (n = 0, 1, 2, ... ) tm0 count value intp1 pin input intp1 interrupt request capture register (cc01) intp0 pin input intp0 interrupt request capture register (cc00) intov0 interrupt request ffffh d0 d1 d2 d3 d4 d5 d6 d7 count started ce0 1 d1 d2 d4 d5 d7 d0 d3 d6 0h chapter 8 timer 0 184 user s manual u11515ej3v0ud 8.6 basic operation of output control circuit the output control circuit controls the levels of the timer output pins (to00 through to03) by using the match signals from the compare registers (cc00 through cc03). the operation of the output control circuit is determined by the timer output control register 0 (toc0). note that the to01 and to03 pin outputs can be used for toggle operation only. the to00 and to02 pin outputs can be used for toggle or set/reset operation, according to the specification by the timer unit mode register 0 (tum0). to output the signals to00 through to03 to pins, the corresponding pins must be set in the control mode by using the port 2 mode control register (pmc2). table 8-6. toggle signal of timer output pin (timer 0) timer output toggle signal to00 intcc00 to01 intcc01 to02 intcc02 to03 intcc03 table 8-7. set/reset signal of timer output pin (timer 0) timer output set signal reset signal to00 intcc00 intcc01 to02 intcc02 intcc03 chapter 8 timer 0 185 user s manual u11515ej3v0ud figure 8-10. block diagram of timer output operation of timer 0 intcc00 intcc01 q t q s r q t selector to00 to01 intcc02 intcc03 q t q s r q t selector to02 to03 chapter 8 timer 0 186 user s manual u11515ej3v0ud 8.6.1 basic operation by setting (1) the ento0n (n = 0 to 3) bit of the timer output control register 0 (toc0), a pulse can be output from the to0n (n = 0 to 3) pin. clearing (0) ento0n bit sets the to0n to a fixed level. the fixed level is determined by the alv0n (n = 0 to 3) bit of the toc0. the level is high when alv0n bit is 0, and low when 1. 8.6.2 toggle output toggle output is an operating mode in which the output level is inverted each time the compare register (cc0n: n = 0 to 3) value coincides with the timer register 0 (tm0) value. the output level of timer output (to0n: n = 0 to 3) is inverted by a match between cc0n and tm0. when timer 0 is stopped by clearing (0) the ce0 bit of the timer mode control register (tmc), the output level at the time it was stopped is retained as is. figure 8-11. operation of toggle output ento00 tm0 count value 0h ffffh cc00 value cc01 value ffffh cc00 value cc01 value ffffh cc00 value cc01 value ffffh cc00 value cc01 value ffffh to00 output (alv00 = 1) ento01 instruction execution instruction execution instruction execution instruction execution to01 output (alv01 = 0) chapter 8 timer 0 187 user s manual u11515ej3v0ud table 8-8. toggle output of to00 through to03 (f clk = 16 mhz) count clock minimum pulse width note maximum pulse width f clk /4 4/f clk (0.25 s) 2 16 4/f clk (16.4 ms) f clk /8 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) f clk /16 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) f clk /32 32/f clk (2.0 s) 2 16 32/f clk (131 ms) f clk /64 64/f clk (4.0 s) 2 16 64/f clk (262 ms) note the minimum interval time is limited by the data transfer processing time. consider the interrupt processing time or macro service processing time used (refer to table 16-11 interrupt acceptance processing time and table 16-12 macro service processing time ). 8.6.3 set/reset output the set/reset output is an operation mode in which the timer output is set or reset each time the value of the compare register (cc0n: n = 0 to 3) matches with the value of timer register 0 (tm0). if cc00 = cc01 and cc02 = cc03, interrupt requests are simultaneously generated, and timer outputs (to00 and to02) are used as alv00 and alv02. when timer 0 is stopped by clearing (0) the ce0 bit of the timer mode control register (tmc), the output level at which the timer stops is retained as is. figure 8-12. operation of set/reset output (timer 0) tm0 count value intcc00 interrupt request intcc01 interrupt request to00 pin ento00 alv00 tom00 1 1 1 cc00 cc01 ffffh ffffh cc00 cc01 cc00 count started ce0 1 0h chapter 8 timer 0 188 user s manual u11515ej3v0ud 8.7 examples of use 8.7.1 operation as interval timer when timer register 0 (tm0) is made free-running and a fixed value is added to the compare register (cc0n: n = 0 to 3) in the interrupt processing routine, tm0 operates as an interval timer with the added fixed value as the cycle (refer to figure 8-13 ). this interval timer can count within the range shown in table 8-1 (internal system clock f clk = 16 mhz). since tm0 has four capture compare registers, four interval timers with different cycles can be constructed. taking an example where compare register cc00 is used, the control register settings are shown in figure 8-14, the setting procedure in figure 8-15, and the processing in the interrupt processing routine in figure 8-16. figure 8-13. timing of interval timer operation remark interval time = n x/f clk y n ffffh x = 4, 8, 16, 32, 64 y is limited by the data transfer processing time. consider the processing time of the interrupt used or the macro service processing time (refer to table 16-11 interrupt acceptance processing time and table 16-12 macro service processing time ). mod(2n) intcc00 interrupt request tm0 count value 0h ffffh compare register (cc00) n timer started mod(3n) mod(4n) ffffh n mod(2n) mod(3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program chapter 8 timer 0 189 user s manual u11515ej3v0ud figure 8-14. set contents of control register for interval timer operation (a) prescaler mode register (prm) (b) timer unit mode register 0 (tum0) 0 0 prm02 prm01 prm00 76543210 prm specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64) 0 1 76543210 tum0 specifies cc00 as compare register specifies to00 for toggle output : don t care chapter 8 timer 0 190 user s manual u11515ej3v0ud figure 8-15. setting procedure of interval timer operation figure 8-16. interrupt request processing of interval timer operation interval timer sets count value to cc00 cc00 n count starts ce0 1 intcc00 interrupt ; sets bit 3 of tmc to 1 sets prm sets tum0 intcc00 interrupt calculates timer value at which interrupt is generated next time cc00 cc00 + n other interrupt processing program reti chapter 8 timer 0 191 user s manual u11515ej3v0ud 8.7.2 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp0 through intp3) is measured. when the sampling clock is f clk both the high-level and low-level widths of pulses input to the intpn (n = 0 to 3) pin must be at least 4 system clocks (0.25 s: f clk = 16 mhz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. when a pulse width is measured, the pulse width in a range shown in table 8-2 can be measured (f clk = 16 mhz). how a pulse width is measured is explained below where the intp3 pin is used as an external input pin. as shown in figure 8-17, the timer register 0 (tm0) value being counted is fetched into the capture register (cc03) in synchronization with a valid edge (specified as both rising and falling edges) in the intp3 pin input, and held there. the pulse width is obtained from the product of the difference between the tm0 count value (dn) fetched into and held in the cc03 on detection of the nth valid edge and the count value (d n-1 ) fetched and held on detection of valid edge n-1, and the number of count clocks (x/f clk ; x = 4, 8, 16, 32, 64). the control register settings are shown in figure 8-18, the setting procedure in figure 8-19, and the processing at interrupt processing routine in figure 8-20. figure 8-17. timing of pulse width measurement remark dn: tm0 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64 d1 intp3 external input signal intp3 interrupt request tm0 count value 0h ffffh capture register (cc03) intov0 interrupt request d0 d0 d1 count started ffffh d2 d2 d3 capture capture capture capture (d1 _ d0) x/f clk (10000h _ d1+ d2) x/f clk (d3 _ d2) x/f clk d3 chapter 8 timer 0 192 user s manual u11515ej3v0ud figure 8-18. control register settings for pulse width measurement (a) prescaler mode register (prm) (b) timer unit mode register 0 (tum0) (c) external interrupt mode register 1 (intm1) 0 0 prm02 prm01 prm00 76543210 prm specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64) 7 tum0 6 5 4 3 0 2 1 0 specifies cc03 as capture register 7 intm1 6 5 4 3 2 : don t care 1 1 0 1 specifies both rising & falling edges as intp3 input valid edges chapter 8 timer 0 193 user s manual u11515ej3v0ud figure 8-19. pulse width measurement setting procedure figure 8-20. interrupt request processing that calculates pulse width pulse width measurement set intm1, set mk0l initialize capture value buffer memory x 0 0 start count ce0 1 enable interrupt ; specify both edges as intp3 input valid edges, release interrupt masking intp3 interrupt ; set 1 to bit 3 of tmc set prm set tum intp3 interrupt calculate pulse width y n = cc03 _ x n store capture value in memory x n+1 cc03 reti chapter 8 timer 0 194 user s manual u11515ej3v0ud 8.8 cautions (1) the prescaler uses one time base in common with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer 4). if one of the timers sets the ce bit to 1 , the time base starts counting. if another timer sets the ce bit to 1 while one timer is operating, the first count clock of the timer may be shortened because the time base has already started counting. for example, when using timer/counter 0 as an interval timer, the first interval time is shortened by up to 1 count clock. the second and those that follow are at the specified interval. figure 8-21. operation when counting is started (2) while timer 0 is operating (while the ce0 bit of the timer mode control register (tmc) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence in a contention the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. timer unit mode register 0 (tum0) timer output control register 0 (toc0) prescaler mode register (prm) count clock tm0 ce0 count start command (ce0 1) by software 1 0 234 chapter 8 timer 0 195 user s manual u11515ej3v0ud (3) if the contents of the compare register (cc0n: n = 0 to 3) match with those of tm0 operation when an instruction that stops timer register 0 (tm0) operation is executed, the counting operation of tm0 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm0, mask the interrupt in advance by using the interrupt mask register before stopping tm0. example program that may generate interrupt request program that does not generate interrupt request clr1 ce0 interrupt request or mk0l, #78h disables interrupt or mk0l, #78h from timer 0 clr1 ce0 from timer 0 occurs between clr1 pif0 clears interrupt request these instructions clr1 pif1 flag from timer 0 clr1 pif2 clr1 pif3 (4) match between timer register 0 (tm0) and compare register (cc0n: n = 0 to 3) is detected only when tm0 is incremented. therefore, the interrupt request is not generated even if the same value as tm0 is written to cc0n, and the timer output (to0n: n = 0 to 3) does not change. (5) when the compare register (cc00 to cc03) is set to 0000h, the compare operation is performed after counting by tm0. therefore, the match interrupt (intcc00 to intcc03) does not occur immediately after counting has been started. if cc0n (n = 0 to 3) is set to 0000h, tm0 counts up to ffffh, the timer overflows, and match interrupt intcc0n (n = 0 to 3) occurs. figure 8-22. operation when compare register (cc00 to cc03) is set to 0000h . . . . . . . . . . . . remark n = 0 to 3 interrupt occurred interrupt occurred count started 0h 1h 2h ffffh 0h 1h 2h ffffh 0h 1h 0000h match match count clock tm0 ce0 cc0n intcc0n chapter 8 timer 0 196 user s manual u11515ej3v0ud (6) if the timer output is enabled when the active level is changed, the output level of pins may change momentarily. to prevent this, enable the timer output after the active level have been changed. (7) to change the active level specification(alv0n bit (n = 0 to 3) of the timer output control register 0 (toc0)), change the active level specification after the timer output of the corresponding timer output pins has been disabled. 197 user? manual u11515ej3v0ud chapter 9 timer 1 9.1 function timer 1 is a 16-bit timer. in addition to a function as an interval timer, this timer has a toggle and set/reset function as timer output. when used as an interval timer, timer 1 generates an internal interrupt at interval determined in advance. table 9-1. interval time of timer 1 minimum interval time maximum interval time resolution 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) 8/f clk (0.5 s) 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) 16/f clk (1.0 s) 32/f clk (2.0 s) 2 16 32/f clk (131 ms) 32/f clk (2.0 s) 64/f clk (4.0 s) 2 16 64/f clk (262 ms) 64/f clk (4.0 s) 128/f clk (8.0 s) 2 16 128/f clk (524 ms) 128/f clk (8.0 s) ( ): at f clk = 16 mhz 9.2 configuration timer 1 consists of the following registers: timer register (tm1) 1 compare register (cm1n) 2 (n = 0, 1) figure 9-1 shows the block diagram of timer 1. chapter 9 timer 1 198 user? manual u11515ej3v0ud figure 9-1. block diagram of timer 1 internal bus internal bus 16 compare register 10 (cm10) 16 16 match 16 1/8 tom10 clr1 ento11 alv11 ento10 alv10 timer unit mode register 0 (tum0) timer output control register 1 (toc1) 1/8 output control circuit output control circuit to10 intcm10 to11 intcm11 reset intov1 ce1 1/8 timer mode control register (tmc) 16 1/8 compare register 11 (cm11) 16 16 match timer register (tm1) overflow clear selector prm12 prm11 prm10 f clk /128 f clk /64 f clk /32 f clk /16 f clk /8 prescaler f clk prescaler mode register (prm) chapter 9 timer 1 199 user s manual u11515ej3v0ud (1) timer register 1 (tm1) tm1 is a timer register that counts up the count clock specified by the prescaler mode register (prm). counting of this timer register is enabled or disabled by the timer mode control register (tmc). the timer register can be only read by using a 16-bit manipulation instruction. when reset is input, tm1 is cleared to 0000h and stops counting. (2) compare registers (cm10, cm11) cm1n (n = 0, 1) is a 16-bit register that holds the value determining the cycle of the interval timer operation. when the contents of cm1n matches with the contents of tm1, an interrupt request (intcm1n: n = 0, 1) and a timer output control signal are generated. the count value of tm1 can be cleared when its value matches with the contents of cm10. these compare registers can be read or written by using 16-bit manipulation instructions. when reset is input, their contents are undefined. (3) output control circuit when the contents of cm1n (n = 0, 1) and the contents of tm1 match, the timer output can be inverted. a square wave can be output from a timer output pin (to10, to11) if so specified by the timer output control register 1 (toc1). the to10 pin can also output a set and reset signals if so specified by the timer unit mode register 0 (tum0). the timer output can be enabled or disabled by toc1. when the timer output is disabled, a fixed level is output to the to1n (n = 0, 1) pin (the output level is fixed by toc1). (4) prescaler the prescaler generates a count clock by dividing the internal system clock. the clock generated by the prescaler is selected by the selector, and tm1 performs the count operation by using this clock as a count clock. (5) selector the selector selects one of the five signals generated by dividing the internal system clock as the count clock of tm1. chapter 9 timer 1 200 user s manual u11515ej3v0ud 9.3 timer 1 control register (1) timer unit mode register 0 (tum0) tum0 is a register that specifies the output mode of the timer output pins (to00, to02, and to10) of timers 0 and 1, controls the clear operation of the timer register 1 (tm1), and specifies the operations of the capture/compare registers (cc00 through cc03) of timer 0. this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 9-2 shows the format of tum0. when reset is input, the value of tum0 is cleared to 00h. figure 9-2. format of timer unit mode register 0 (tum0) tom10 clr1 tom02 tom00 cms03 cms02 cms01 cms00 76543210 tom10 0 1 specifies output mode of to10 pin toggle output set/reset output tum0 address : 0ff30h on reset : 00h r/w tom0n specifies output mode of to0n pin (n = 0, 2) (refer to figure 8-2 ). clr1 0 1 controls clear operation of tm1 by match with cm10 disabled (free running mode) enabled (interval timer mode) cms0n specifies operation of cc0n (n = 0 to 3) (refer to figure 8-2 ). chapter 9 timer 1 201 user s manual u11515ej3v0ud (2) timer mode control register (tmc) tmc is a register that controls the count operation of timer registers 0 and 1 (tm0 and tm1). this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 9-3 shows the format of tmc. when reset is input, the value of this register is cleared to 00h. figure 9-3. format of timer mode control register (tmc) (3) timer output control register 1 (toc1) toc1 is a register that specifies the operation and active level of the timer output pins (to10, to11) of timer 1. this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 9-4 shows the format of toc1. when reset is input, the value of this register is cleared to 00h. figure 9-4. format of timer output control register 1 (toc1) ce1 0 0 0 ce0 0 0 0 76543210 ce1 0 1 controls count operation of tm1 clears and stops counting enables counting operation tmc address : 0ff31h on reset : 00h r/w ce0 controls count operation of tm0 (refer to figure 8-3 ). 0000 ento11 alv11 ento10 alv10 76543210 ento1n 0 1 specifies operation of to1n pin (n = 0, 1) outputs alv1n enables pulse output toc1 address : 0ff33h on reset : 00h r/w alv1 n 0 1 specifies active level of to1n pin (n = 0, 1) low level high level chapter 9 timer 1 202 user s manual u11515ej3v0ud (4) prescaler mode register (prm) prm is a register that specifies the count clock of timer registers 0 and 1 (tm0, tm1). this register can be read or written by using an 8-bit manipulation instruction. figure 9-5 shows the format of prm. when reset is input, the value of this register is cleared to 00h. figure 9-5. format of prescaler mode register (prm) remark f clk : internal system clock address : 0ff38h on reset : 00h r/w 0 prm12 prm11 prm10 0 prm02 prm01 prm00 76543210 prm prm02 specifies count clock of tm0 (refer to figure 8-5 ). prm12 0 0 0 0 1 specifies count clock of tm1 f clk /8 f clk /16 f clk /32 f clk /64 f clk /128 setting prohibited prm01 prm00 prm11 0 0 1 1 0 prm10 0 1 0 1 0 count clock [hz] resolution [ s] 0.5 1.0 2.0 4.0 8.0 other (f clk = 16 mhz) chapter 9 timer 1 203 user s manual u11515ej3v0ud 9.4 operation of timer register 1 (tm1) 9.4.1 basic operation timer 1 counts up by using the count clock specified by the prescaler mode register (prm). counting is enabled or disabled by the ce1 bit of the timer mode control register (tmc). when the ce1 bit is set (1) by software, tm1 is set to 0001h at the first count clock, and starts counting up. when the ce1 bit is cleared (0) by software , tm1 is immediately cleared to 0000h, and stops the generation of the match signal. if the ce1 bit is set (1) while it has been already set (1), tm1 is not cleared but continues counting. if a count clock is input when tm1 reaches ffffh, tm1 is cleared to 0000h, and an overflow interrupt (intov1) occurs. when reset is input, tm1 is cleared to 0000h and stops counting. chapter 9 timer 1 204 user s manual u11515ej3v0ud figure 9-6. basic operation of timer register 1 (tm1) (a) count started count stopped count started (c) operation when tm1 = ffffh (b) when ??is written to the ce1 bit again after the count starts tm1 ce1 0h 1h 2h 3h ffh 100h 101h 1h 2h 0h count started ce1 1 count stopped ce1 0 count started ce1 1 count clock tm1 ce1 count started ce1 1 rewritten ce1 1 count clock 0h 1h 2h 3h 4h 5h 6h 7h tm1 intov1 interrupt request fffeh ffffh 0h count clock 1h chapter 9 timer 1 205 user s manual u11515ej3v0ud 9.4.2 clear operation (1) clear operation after match with compare register timer register 1 (tm1) can be cleared automatically after a match with the compare register (cm10). when a clearance source arises, tm1 is cleared to 000h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 9-7. tm1 clear operation by match with compare register (cm10) (2) clear operation by ce1 bit of timer mode control register (tmc) timer register 1 (tm1) is also cleared when the ce1 bit of tmc is cleared (0) by software. the clear operation is performed immediately after the clearance (0) of the ce1 bit. tm1 compare register (cm10) cleared here count clock n tm1 and cm10 match n01 n _ 1 chapter 9 timer 1 206 user s manual u11515ej3v0ud figure 9-8. tm1 clear operation when ce1 bit is cleared (0) (a) basic operation (b) restart before count clock is input after clearance (c) restart after count clock is input after clearance tm1 ce1 n count clock n _ 10 tm1 ce1 n0 count clock n _ 1 0 1 2 if the ce1 bit is set (1) from this count clock onward, the count clock starts counting from 1 after the ce1 bit is set (1). tm1 ce1 n count clock n _ 1 1 0 2 3 if the ce1 bit is set (1) before this count clock, this count clock starts counting from 1. chapter 9 timer 1 207 user s manual u11515ej3v0ud 9.5 operation of compare register timer 1 performs a compare operation by comparing the value set to a compare register (cm10, cm11) specified as a compare register with the count value of a timer register 1 (tm1). if the count value of tm1 matches with the value set in advance to cm1n (n = 0, 1) as a result of counting by tm1, the timer sends a match signal to the output control circuit, and at the same time, generates an interrupt request signal (intcm10, intcm11). after the value of tm1 has matched with the value of cm10, the count value of tm1 can be cleared, so that tm1 can be used as an interval timer that repeatedly counts the value set to cm10. table 9-2. interrupt request signal from compare register (timer 1) compare register interrupt request signal cm10 intcm10 cm11 intcm11 timer 1 has two timer output pins (to10, to11). table 9-3 shows the operation mode of each of these pins (for details, refer to 9.6 basic operation of output control circuit ). table 9-3. operation mode of timer output pin (timer 1) timer output pin output operation mode specification of operation mode to10 toggle set/reset tum10 bit of tum0 to11 toggle chapter 9 timer 1 208 user s manual u11515ej3v0ud figure 9-9. compare operation (timer 1) remark clr1 = 0 intcm10 interrupt request tm1 count value 0h ffffh count started ce1 1 cm10 value cm11 value ffffh cm10 value cm11 value intcm11 interrupt request to10 pin output ento10 = 1 alv10 = 1 intov1 interrupt request match match match match to11 pin output ento11 = 1 alv11 = 0 inactive level inactive level chapter 9 timer 1 209 user s manual u11515ej3v0ud figure 9-10. clearing tm1 after detection of match intcm11 interrupt request tm1 count value 0h ffffh count started ce1 1 clr1 0 intcm10 interrupt request to11 pin output ento11 1 alv11 1 intov1 interrupt request to10 pin output ento10 1 alv10 1 inactive level cm11 cm10 cm10 cm10 inactive level count disabled ce1 0 count started ce1 1 clr1 1 cleared cleared chapter 9 timer 1 210 user s manual u11515ej3v0ud 9.6 basic operation of output control circuit the output control circuit controls the levels of the timer output pins (to10, to11) by using the coincidence signals from the compare registers (cm10, cm11). the operation of the output control circuit is determined by the timer output control register 1 (toc1). note that the to11 pin output can be used for toggle operation only. the to10 pin output can be used for toggle or set/reset operation, according to the specification by the timer unit mode register 0 (tum0). to output the to10 and to11 signals to pins, the corresponding pins must be set in the control mode by using the port 3 mode control register (pmc3). table 9-4. toggle signal of timer output pin (timer 1) timer output toggle signal to10 intcm10 to11 intcm11 table 9-5. set/reset signal of timer output pin (timer 1) timer output set signal reset signal to10 intcm10 intcm11 figure 9-11. block diagram of timer output operation of timer 1 intcm10 intcm11 q t q s r q t selector to10 to11 chapter 9 timer 1 211 user s manual u11515ej3v0ud 9.6.1 basic operation by setting (1) the ento1n (n = 0, 1) bit of the timer output control register 1 (toc1), a pulse can be output from the to1n (n = 0, 1) pin. by clearing (0) the ento1n bit, the level of to1n is fixed. the level to which to1n is fixed is determined by the alv1n (n = 0, 1) bit of toc1. when the alv1n bit is 0, to1n is fixed to the high level; when alv1n bit is 1, it is fixed to the low level. 9.6.2 toggle output toggle output is an operation mode in which the output level is inverted each time the value of the compare register (cm10, cm11) matches with the value of timer register 1 (tm1). the output level of the timer output to10 is inverted when the value of cm10 matches with tm1, and the output level of to11 is inverted when the value of cm11 matches with the value of tm1. when timer 1 is stopped by clearing (0) the ce1 bit of the timer mode control register (tmc), the output level is retained as is. figure 9-12. operation of toggle output table 9-6. toggle output of to10 and to11 (f clk = 16 mhz) count clock minimum pulse width maximum pulse width f clk /8 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) f clk /16 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) f clk /32 32/f clk (2.0 s) 2 16 32/f clk (131 ms) f clk /64 64/f clk (4.0 s) 2 16 64/f clk (262 ms) f clk /128 128/f clk (8.0 s) 2 16 128/f clk (524 ms) ento10 tm1 count value 0h ffffh instruction execution cm10 value cm11 value ffffh cm10 value cm11 value ffffh cm10 value cm11 value ffffh cm10 value cm11 value ffffh to10 output (alv10 = 1) ento11 to11 output (alv11 = 0) instruction execution instruction execution instruction execution chapter 9 timer 1 212 user s manual u11515ej3v0ud 9.6.3 set/reset output the set/reset output is an operation mode in which the timer output is set or reset each time the value of the compare register (cm1n: n = 0, 1) matches with the value of timer register 1 (tm1). if cm10 = cm11, interrupt requests are simultaneously generated, and timer output (to10) is used as alv10. when timer 1 is stopped by clearing (0) the ce1 bit of the timer mode control register (tmc), the output level at which the timer stops is retained as is. figure 9-13. operation of set/reset output (timer 1) tm1 count value intcm10 interrupt request intcm11 interrupt request to10 pin ento10 alv10 tom10 1 1 1 cm10 cm11 ffffh ffffh cm10 cm11 cm10 count started ce1 1 0h chapter 9 timer 1 213 user s manual u11515ej3v0ud 9.7 examples of use 9.7.1 operation as interval timer (1) when timer register 1 (tm1) is made free-running and a fixed value is added to the compare register (cm1n: n = 0, 1) in the interrupt processing routine, tm1 operates as an interval timer with the added fixed value as the cycle (refer to figure 9-14 ). this interval timer can count in the range shown in table 9-1 (internal system clock f clk = 16 mhz). because tm1 has two compare registers, interval timers of two types of cycles can be created. figure 9-15 shows the set contents of the control registers, figure 9-16 shows how to set the registers, and figure 9- 17 shows the processing in an interrupt routine, where compare register cm10 is used. figure 9-14. timing of interval timer operation (1) remark interval time = n x/f clk y n ffffh x = 4, 8, 16, 32, 64 y is limited by the data transfer processing time. consider the processing time of the interrupt used or the macro service processing time (refer to table 16-11 interrupt acceptance processing time and table 16-12 macro service processing time ). mod(2n) intcm10 interrupt request tm1 count value 0h ffffh compare register (cm10) n timer started mod(3n) mod(4n) ffffh n mod(2n) mod(3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program chapter 9 timer 1 214 user s manual u11515ej3v0ud figure 9-15. control register settings for interval timer operation (1) (a) prescaler mode register (prm) (b) timer unit mode register 0 (tum0) 7 0 prm 6 prm12 5 prm11 4 prm10 3 0 2 1 0 specifies count clock (f clk /x ; x = 8, 16, 32, 64, 128) 00 76543210 tum0 disables tm1 clearing by match of cm10 and tm1 specifies to10 for toggle output : don t care chapter 9 timer 1 215 user s manual u11515ej3v0ud figure 9-16. setting procedure of interval timer operation (1) figure 9-17. interrupt request processing of interval timer operation (1) interval timer (1) set count value to cm10 cm10 n start count ce1 1 intcm10 interrupt ; set 1 to bit 7 of tmc set prm set tum0 intcm10 interrupt calculate timer value that will generate next interrupt cm10 cm10 + n other interrupt processing program reti chapter 9 timer 1 216 user s manual u11515ej3v0ud 9.7.2 operation as interval timer (2) tm1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (refer to figure 9-18 ). this interval timer can count in the range shown in table 9-1 (internal system clock f clk = 16 mhz) the control register settings are shown in figure 9-19, and the setting procedure in figure 9-20. figure 9-18. timing of interval timer operation (2) remark interval = (n+1) x/f clk 0 n ffffh x = 8, 16, 32, 64, 128 compare register (cm10) intcm10 interrupt request tm1 count value 0h n n n count started cleared cleared interval match match interrupt acknowledged interrupt acknowledged interval chapter 9 timer 1 217 user s manual u11515ej3v0ud figure 9-19. control register settings for interval timer operation (2) (a) prescaler mode register (prm) (b) timer unit mode register 0 (tum0) figure 9-20. setting procedure of interval timer operation (2) 7 0 prm 6 prm12 5 prm11 4 prm10 3 0 2 1 0 specifies count clock (f clk /x ; x = 8, 16, 32, 64, 128) 01 76543210 tum0 clears tm1 by match of cm10 and tm1 specifies to10 for toggle output : don t care interval timer (2) set count value to cm10 cm10 n intcm10 interrupt ; set 1 to bit 7 of tmc set prm start count ce1 1 set tum0 chapter 9 timer 1 218 user s manual u11515ej3v0ud 9.8 cautions (1) the prescaler uses one time base in common with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer 4). if one of the timers sets the ce bit to 1 , the time base starts counting. if another timer sets the ce bit to 1 while one timer operates, the first count clock of the timer may be shortened because the time base has already started counting. for example, when using timer/counter 1 as an interval timer, the first interval time is shortened by up to 1 count clock. the second and those that follow are at the specified interval. figure 9-21. operation when counting is started (2) while timer 1 is operating (while the ce1 bit of the timer mode control register (tmc) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. timer unit mode register 0 (tum0) timer output control register 1 (toc1) prescaler mode register (prm) count clock tm1 ce1 count start command (ce1 1) by software 1 0 234 chapter 9 timer 1 219 user s manual u11515ej3v0ud (3) if the contents of the compare register (cm1n: n = 0, 1) matches with those of tm1 when an instruction that stops timer register 1 (tm1) operation is executed, the counting operation of tm1 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm1, mask the interrupt in advance by using the interrupt mask register before stopping tm1. example program that may generate interrupt request program that does not generate interrupt request clr1 ce1 or mk0h, #0ch or mk0h, #0ch clr1 ce1 clr1 cmif10 clr1 cmif11 (4) a match between the timer register 1 (tm1) and compare register (cm1n: n = 0, 1) is detected only when tm1 is incremented. therefore, the interrupt request is not generated even if the same value as tm1 is written to cm1n, and the timer output (to1n: n = 0, 1) does not change. (5) when the compare register (cm10, cm11) is set to 0000h, the compare operation is performed after counting by tm1. therefore, the interrupt due to a match (intcm10, intcm11) does not occur immediately after counting has been started. if cm1n (n = 0, 1) is set to 0000h, tm1 counts up to ffffh, the timer overflows, and the interrupt due to a match intcm1n (n = 0, 1) occurs. interrupt request from timer 1 occurs between these instructions disables interrupt from timer 1 clears interrupt request flag from timer 1 chapter 9 timer 1 220 user? manual u11515ej3v0ud figure 9-22. operation when compare register (cm10, cm11) is set to 0000h (a) cm10 interrupt occurred count started match match match match cleared cleared cleared 0000h count clock tm1 ce1 cm10 intcm10 0h 1h 2h 3h 4h 5h ffffh 0h 0h 0h 0h (b) cm11 interrupt occurred count started match match 0000h count clock tm1 ce1 cm11 intcm11 0h 1h 2h ffffh 0h 2h ffffh 0h 1h interrupt occurred 1h (6) if the timer output is enabled when the active level is changed, the output level of pins may change momentarily. to prevent this, enable the timer output after the active level have been changed. (7) to change the active level specification (alv1n bit (n = 0, 1) of the timer output control register 1 (toc1)), change the active level specification after the timer output of the corresponding timer output pins has been disabled. 221 user? manual u11515ej3v0ud chapter 10 timers/counters 2 and 3 the function and configuration of timers/counters 2 and 3 are identical. in this chapter, therefore, timer/counter 2 is described as a representative unless otherwise specified. to use timer/counter 3, take the pin names, register names, and bit names of the control registers of timer/counter 2 as indicated in table 10-1. table 10-1. differences in name between timer/counter 2 and timer/counter 3 item timer/counter 2 timer/counter 3 pin name p10/to20 p12/to30 p11/to21 p13/to31 p26/intp5/ti2 p27/intp6/ti3 timer register tm2 tm3 compare register cm20 cm30 cm21 cm31 bit name in timer unit mode register 2 (tum2) tom21, tom20, clr21, tom31, tom30, clr31, clr20 clr30 bit name in timer mode control register 2 (tmc2) ce2, ovf2 ce3, ovf3 bit name in timer output control register 2 (toc2) ento21, alv21, ento20, ento31, alv31, ento30, alv20 alv30 bit name in prescaler mode register 2 (prm2) prm20-prm22 prm30-prm32 bit name in external interrupt mode register 1 (intm1) es51, es50 es61, es60 interrupt request name intp5 intp6 intcm20 intcm30 intcm21 intcm31 222 chapter 10 timers/counters 2 and 3 user? manual u11515ej3v0ud 10.1 function timer/counter 2 is a 16-bit timer/counter. this timer/counter functions as an interval timer, to output programmable square wave, and as an external event counter. (1) interval timer when timer/counter 2 is used as an interval timer, it generates an internal interrupt at interval set in advance. table 10-2. interval time of timer/counter 2 minimum interval time maximum interval time resolution 4/f clk (0.25 s) 2 16 4/f clk (16.4 ms) 4/f clk (0.25 s) 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) 8/f clk (0.5 s) 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) 16/f clk (1.0 s) 32/f clk (2.0 s) 2 16 32/f clk (131 ms) 32/f clk (2.0 s) 64/f clk (4.0 s) 2 16 64/f clk (262 ms) 64/f clk (4.0 s) ( ): f clk = 16 mhz (2) programmable square wave output timer/counter 2 can output square wave to timer output pins (to20, to21) independently. table 10-3. programmable square wave output range of timer/counter 2 minimum pulse width maximum pulse width 4/f clk (0.25 s) 2 16 4/f clk (16.4 ms) 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) 32/f clk (2.0 s) 2 16 32/f clk (131 ms) 64/f clk (4.0 s) 2 16 64/f clk (262 ms) ( ): f clk = 16 mhz caution the values in the above table are when the internal clock is used. 223 chapter 10 timers/counters 2 and 3 user? manual u11515ej3v0ud (3) external event counter when timer/counter 2 is used as an external event counter, it counts the clock pulse (ti2 pin input pulse) input from an external interrupt request input pin (intp5). table 10-4. clock that can be input to timer/counter 2 sampling clock maximum frequency minimum pulse width (high and low levels) f clk f clk /8 (2.0 mhz) 4/f clk (0.25 s) f clk /4 f clk /32 (0.5 mhz) 16/f clk (1.0 s) ( ): f clk = 16 mhz remarks 1. the clock that can be input is the same regardless of the edge to be counted (single edge or both edges). 2. the sampling clock is specified by using the noise protection control register (npc). 10.2 configuration timer/counter 2 consists of the following registers: timer register (tm2) 1 compare register (cm2n) 2 (n = 0, 1) figure 10-1 shows the block diagram of timer/counter 2. 224 chapter 10 timers/counters 2 and 3 user? manual u11515ej3v0ud figure 10-1. block diagram of timer/counter 2 internal bus internal bus 1/8 16 es51 es50 external interrupt mode register 1 (intm1) compare register 20 (cm20) 16 timer unit mode register 2 (tum2) tom21 tom20 clr21 clr20 1/8 timer output control register 2 (toc2) 1/8 ento21 alv21 ento20 alv20 intp5/ti2 edge detection circuit intp5 prescaler f clk f clk /64 f clk /32 f clk /16 f clk /8 f clk /4 selector 16 16 match 16 16 match compare register 21 (cm21) timer register 2 (tm2) clear overflow reset 1/8 16 prm22 prm21 prm20 prescaler mode register 2 (prm2) ce2 ovf2 timer mode control register 2 (tmc2) 1/8 output control circuit output control circuit to20 intcm20 to21 intcm21 toggle/pwm/ppg output control 225 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (1) timer register (tm2) tm2 is a timer register that counts up the count clock specified by the low-order 3 bits of the prescaler mode register 2 (prm2) (the count clock of tm3 is specified by bits 4 through 6 of prm2). counting of this timer register is enabled or disabled by the timer mode control register 2 (tmc2). the timer register can be only read by using a 16-bit manipulation instruction. when reset is input, tm2 is cleared to 0000h and stops counting. (2) compare registers (cm20, cm21) cm2n (n = 0 or 1) is a 16-bit register that holds the value determining the cycle of the interval timer operation. when the contents of cm2n matches with the contents of tm2, an interrupt request (intcm2n: n = 0, 1) and a timer output control signal are generated. the count value of tm2 can be cleared when its value matches with the contents of cm2n. these compare registers can be read or written by using 16-bit manipulation instructions. when reset is input, their contents are undefined. (3) edge detection circuit the edge detection circuit detects the valid edge of an external input. it detects the valid edge of the intp5/ti2 pin input, and generates an external interrupt request (intp5). the valid edge to be detected is specified by external interrupt mode register 1 (intm1) (for intm1, refer to figure 15-2 ). (4) output control circuit when the contents of cm2n (n = 0, 1) and the contents of tm2 matches, the timer output can be inverted. a square wave can be output from a timer output pin (to20, to21) if so specified by the timer output control register 2 (toc2). at this time, pwm/ppg output can also be specified by the timer unit mode register 2 (tum2). the timer output can be enabled or disabled by toc2. when the timer output is disabled, a fixed level is output to the to2n (n = 0, 1) pin (the output level is set by toc2). (5) prescaler the prescaler generates a count clock by dividing the internal system clock. the clock generated by the prescaler is selected by the selector, and tm2 performs the count operation by using this clock as a count clock. (6) selector the selector selects one of the five signals generated by dividing the internal system clock and ti2 pin input as the count clock of tm2. 226 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.3 timer/counter 2 control register (1) timer unit mode register 2 (tum2) tum2 is a register that specifies the output mode of the timer output pins (to20, to21, to30, and to31) of timers/ counters 2 and 3, and controls the clear operation of timer registers 2 and 3 (tm2, tm3). this register can be read or written by using an 8-bit manipulation instruction and a bit manipulation instruction. figure 10-2 shows the format of tum2. the value of this register is cleared to 00h when reset is input. figure 10-2. format of timer unit mode register 2 (tum2) tom31 tom30 clr31 clr30 tom21 tom20 clr21 clr20 76543210 tom31 0 0 0 0 0 1 1 1 specifies timer output mode toggle output tum2 address : 0ff34h on reset : 00h r/w tom30 0 0 0 1 1 0 0 1 clr31 0 0 1 0 1 0 0 0 clr30 0 1 0 0 0 0 1 0 to31 pin to30 pin tm3 clearing condition toggle output overflow other tom21 0 0 0 0 0 1 1 1 specifies timer output mode tom20 0 0 0 1 1 0 0 1 clr21 0 0 1 0 1 0 0 0 clr20 0 1 0 0 0 0 1 0 to21 pin to20 pin tm2 clearing condition other pwm output ppg output pwm output ppg output pwm output match with cm31 overflow overflow overflow match with cm30 match with cm31 match with cm30 setting prohibited toggle output toggle output toggle output pwm output pwm output ppg output pwm output toggle output pwm output ppg output pwm output overflow match with cm20 match with cm21 overflow overflow match with cm20 match with cm21 overflow setting prohibited 227 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (2) timer mode control register 2 (tmc2) tmc2 is a register that controls the counting operation of timer registers 2 and 3 (tm2, tm3) and indicates whether an overflow occurs or not. this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 10-3 shows the format of tmc2. the value of this register is cleared to 00h when reset is input. figure 10-3. format of timer mode control register 2 (tmc2) 0000ce3 ovf3 ce2 ovf2 76543210 cen 0 1 controls count operation of tmn (n = 2, 3) clears and stops counting enables counting tmc2 address : 0ff35h on reset : 00h r/w ovfn 0 1 overflow flag of tmn (n = 2, 3) no overflow overflow 228 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (3) timer output control register 2 (toc2) toc2 is a register that specifies the operation and active level of the timer output pins (to20, to21, to30, and to31) of timers/counters 2 and 3. this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 10-4 shows the format of toc2. the value of this register is cleared to 00h when reset is input. figure 10-4. format of timer output control register 2 (toc2) ento31 alv31 ento30 alv30 ento21 alv21 ento20 alv20 76543210 toc2 address : 0ff36h on reset : 00h r/w ento3n 0 1 specifies operation of to3n pin (n = 0, 1) outputs alv3n enables pulse output alv3n 0 1 specifies active level of to3n pin (n = 0, 1) low level high level high level low level with toggle output specified with pwm/ppg output specified ento2n 0 1 specifies operation of to2n pin (n = 0, 1) outputs alv2n enables pulse output alv2n 0 1 specifies active level of to2n pin (n = 0, 1) low level high level high level low level with toggle output specified with pwm/ppg output specified 229 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (4) prescaler mode register 2 (prm2) prm2 is a register that specifies the count clock of timer registers 2 and 3 (tm2 and tm3). this register can be read or written by using an 8-bit manipulation instruction. figure 10-5 shows the format of prm2. the value of this register is cleared to 00h when reset is input. figure 10-5. format of prescaler mode register 2 (prm2) remark f clk : internal system clock address : 0ff39h on reset : 00h r/w 0 prm32 prm31 prm30 0 prm22 prm21 prm20 76543210 prm2 prmn2 0 0 0 0 1 1 specifies count clock of tmn (n = 2, 3) f clk /4 f clk /8 f clk /16 f clk /32 f clk /64 external clock input (tin) setting prohibited prmn1 0 0 1 1 0 0 prmn0 0 1 0 1 0 1 count clock [hz] resolution [ s] 0.25 0.5 1.0 2.0 4.0 others (f clk = 16 mhz) 230 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.4 operation of timer register 2 (tm2) 10.4.1 basic operation timer/counter 2 counts up by using the count clock specified by the prescaler mode register 2 (prm2). counting is enabled or disabled by the ce2 bit of the timer mode control register 2 (tmc2). when the ce2 bit is set (1) by software, tm2 is set to 0001h at the first count clock, and starts counting up. when the ce2 bit is cleared (0) by software, tm2 is immediately cleared to 0000h, and generation of the match signal is stopped. if the ce2 bit is set (1) while it has been already set (1), tm2 is not cleared but continues counting. if a count clock is input when tm2 reaches ffffh, tm2 is cleared to 0000h, and the ovf2 flag of tmc2 is set (1). the ovf2 flag is cleared only by software. tm2 continues counting. when reset is input, tm2 is cleared to 0000h and stops counting. 231 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-6. basic operation of timer register 2 (tm2) (a) count started count stopped count started (c) operation when tm2 = ffffh (b) when ??is written to the ce2 bit again after the count starts tm2 ce2 0h 1h 2h 3h ffh 100h 101h 1h 2h 0h count started ce2 1 count started ce2 1 count stopped ce2 0 count clock tm2 ce2 0h 1h 2h 3h 4h 5h 6h 7h count started ce2 1 rewritten ce2 1 count clock tm2 ovf2 fffeh ffffh 0h cleared by software ovf2 0 count clock 1h 232 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.4.2 clear operation (1) clear operation after match with compare register timer register 2 (tm2) can be cleared automatically after a match with the compare register (cm2n: n = 0, 1). when a clearance source arises, tm2 is cleared to 0000h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 10-7. tm2 clear operation by match with compare register (cm20/cm21) remark n = 0 or 1 (2) clear operation by ce2 bit of timer mode control register 2 (tmc2) timer register 2 (tm2) is also cleared when the ce2 bit of the tmc2 is cleared (0) by software. the clear operation is performed immediately after clearance (0) of the ce2 bit. tm2 compare register (cm2n) n cleared here count clock 0 1 n 1 n tm2 and cm2n match 233 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-8. tm2 clear operation when ce2 bit is cleared (0) (a) basic operation (b) restart before count clock is input after clearance (c) restart after count clock is input after clearance tm2 ce2 n count clock n 10 tm2 ce2 n 0 count clock n 1 1 2 3 if the ce2 bit is set (1) before this count clock, this count clock starts counting from 1. tm2 ce2 n 0 count clock n 1 0 1 2 if the ce2 bit is set (1) from this count clock onward, the count starts from 1 on the count clock after the ce2 bit is set (1). 234 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.5 external event counter function timer/counter 2 can count clock pulses input from external interrupt request input pin (intp5/ti2). no special selection method is needed for the external event counter operating mode. when the timer register 2 (tm2) count clock is specified as external clock input by the setting of the high-order 4 bits of prescaler mode register 2 (prm2), tm2 operates as an external event counter. the maximum frequency of external clock pulses that can be counted by tm2 as the external event counter is 2.08 mhz (f clk = 12.5 mhz) irrespective of whether only one edge or both edges are counted on intp2/ci input. the pulse width of intp2/ci input must be at least 3 system clocks (0.24 s: f clk = 12.5 mhz) for both the high level and low level. if the pulse width is shorter than this, the pulse may not be counted. the timer/counter 2 external event count timing is shown in figure 10-11. figure 10-9. timing of timer/counter 2 external event count (1/2) (1) counting one edge (maximum frequency = f clk /8 note ) note when sampling clock is f clk . remark iti2: ti2 input signal after passing through edge detection circuit iti2 tm2 ti2 4/f clk (min.) 4/f clk (min.) 8/f clk (min.) dn+1 dn dn+2 dn+3 5-6/f clk 235 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-9. timing of timer/counter 2 external event count (2/2) (2) counting both edges (maximum frequency = f clk /8 note ) note when sampling clock is f clk . remark iti2: ti2 input signal after passing through edge detection circuit the tm2 count operation is controlled by the ce2 bit of the timer control register 2 (tmc2) in the same way as with the basic operation. when the ce2 bit is set (1) by software, the contents of tm2 are set to 0001h and the up-count operation is started on the initial count clock. when the ce2 bit is cleared (0) by software during a tm2 count operation, the contents of tm2 are set to 0000h immediately and the stopped state is entered. the tm2 count operation is not affected if the ce2 bit is set (1) by software again when it is already set (1). iti2 tm2 ti2 4/f clk (min.) 4/f clk (min.) 8/f clk (min.) dn+1 dn dn+2 dn+3 dn+4 dn+5 5-6/f clk 236 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.6 operation of compare register timer/counter 2 performs a compare operation by comparing the value set to a compare register (cm20, cm21) with the count value of a timer register 2 (tm2). if the count value of tm2 coincides with the value set in advance to cm2n (n = 0, 1) as a result of counting by tm2, the timer sends a coincidence signal to the output control circuit, and at the same time, generates an interrupt request signal (intcm2n: n = 0, 1). after the value of tm2 has coincided with the value of cm2n, the count value of tm2 can be cleared, so that tm2 can be used as an interval timer that repeatedly counts the value set to cm2n. table 10-5. interrupt request signal from compare register (timer/counter 2) compare register interrupt request signal cm20 intcm20 cm21 intcm21 table 10-6. interrupt request signal from compare register (timer/counter 3) compare register interrupt request signal cm30 intcm30 cm31 intcm31 timer 2 has two timer output pins (to20, to21). these pins can be used for toggle/pwm/ppg output as specified by the timer unit mode register 2 (tum2) (for details, refer to 10.7 basic operation of output control circuit ). 237 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-10. compare operation (timer/counter 2) remark clr20 = 0, clr21 = 0 intcm20 interrupt request tm2 count value 0h ffffh count started ce2 1 cm20 value cm21 value ffffh cm20 value cm21 value intcm21 interrupt request to20 pin output ento20 = 1 alv20 = 1 ovf2 match match match match to21 pin output ento21 = 1 alv21 = 0 cleared by software inactive level inactive level 238 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-11. tm2 clearance after match detection remark clr20 = 0 intcm20 interrupt request tm2 count value 0h ffffh count started ce2 1 clr21 0 intcm21 interrupt request to20 pin output ento20 1 alv20 1 ovf2 to21 pin output ento21 1 alv21 1 cleared by software cm20 cm21 cm21 cm21 inactive level inactive level count started ce2 1 clr21 1 count disabled ce2 0 cleared cleared 239 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.7 basic operation of output control circuit the output control circuit controls the timer output pins (to20, to21) level by means of match signals from the compare register (cm20, cm21). the operation of the output control circuit is determined by the timer output control register 2 (toc2) . as the operation of the to20 and to21 output pins, toggle output, pwm output, or ppg output can be selected by using the timer unit mode register 2 (tum2). to output the to20 and to21 signals to the pins, the corresponding pins must be set in the control mode by the port 1 mode control register (pmc1). 10.7.1 basic operation setting (1) the ento2n (n = 0, 1) bit of the timer output control register 2 (toc2) enables pulse output from to2n (n = 0, 1) pin. clearing (0) ento2n bit sets the to2n to a fixed level. the fixed level is determined by the alv2n (n = 0, 1) bit of the toc2. the level is high when alv2n bit is 0, and low when 1. 10.7.2 toggle output toggle output is an operating mode in which the output level is inverted each time the compare register (cm20/cm21) value matches with the timer register 2 (tm2) value. the output level of timer output (to20) is inverted by a match between cm20 and tm2, and the output level of timer output (to21) is inverted by a match between cm21 and tm2. when timer/counter 2 is stopped by clearing (0) the ce2 bit of the timer mode control register 2 (tmc2), the output level at the time it was stopped is retained. figure 10-12. operation of toggle output ento20 tm2 count value 0h ffffh instruction execution cm20 value cm21 value ffffh cm20 value cm21 value ffffh cm20 value cm21 value ffffh cm20 value cm21 value ffffh to20 output (alv20 = 1) ento21 to21 output (alv21 = 0) instruction execution instruction execution instruction execution 240 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud table 10-7. toggle output of to20 and to21 (f clk = 16 mhz) count clock minimum pulse width maximum pulse width f clk /4 4/f clk (0.25 s) 2 16 4/f clk (16.4 ms) f clk /8 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) f clk /16 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) f clk /32 32/f clk (2.0 s) 2 16 32/f clk (131 ms) f clk /64 64/f clk (4.0 s) 2 16 64/f clk (262 ms) 241 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.7.3 pwm output (1) basic operation of pwm output in this mode, a pwm signal whose cycle is equal to a period during which timer register 2 (tm2) completes its full count is output. the pulse width of timer output (to20) is determined by the value of a compare register (cm20), and the pulse width of timer output (to21) is determined by the value of compare register (cm21). to set the to2n (n = 0, 1) pin in the pwm output mode, set (1) the tom2n (n = 0, 1) bit of the timer unit mode register 2 (tum2), and reset (0) the clr20 and clr21 bits (refer to figure 10-2 ). the pulse cycle and pulse width are as follows: pwm cycle = 65536 x/f clk ; x = 4, 8, 16, 32, 64 pwm pulse width = cm2n note x/f clk ; n = 0, 1 duty = pwm pulse width = cm2n pwm cycle 65536 note cm2n cannot be set to 0. figure 10-13. pwm pulse output remark alv20 = 0 table 10-8. pwm cycle of to20 and to21 (f clk = 16 mhz) count clock minimum pulse width [ s] pwm cycle [s] pwm frequency [hz] f clk /4 0.25 0.016 61.0 f clk /8 0.5 0.033 30.5 f clk /16 1.0 0.066 15.3 f clk /32 2.0 0.13 7.63 f clk /64 4.0 0.26 3.81 cm20 interrupt tm2 count value 0h ffffh count started cm20 ffffh ffffh pulse width pulse cycle to20 cm20 pulse width pulse cycle 242 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-14 shows an example of 2-channel pwm output, and figure 10-15 shows the case where ffffh is set in the cm20. figure 10-14. example of pwm output using tm2 remark alv20 = 0, alv21 = 0 figure 10-15. example of pwm output when cm20 = ffffh remarks 1. alv20 = 0 2. t = x/f clk (x = 4, 8, 16, 32, 64) tm2 count value 0h cm20 ffffh intcm20 cm21 cm20 ffffh cm21 cm20 ffffh intcm21 to20 to21 tm2 count value ffffh intcm20 0 1 2 fffeh ffffh 0 1 2 fffeh count clock cycle t ffffh 0 pulse width t duty = 100 = 99.9 (%) . . 65535 65536 pulse cycle = 65536t ovf2 to20 243 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (2) rewriting compare registers (cm20, cm21) the output level of the timer output (to2n: n = 0, 1) is not inverted even if the cm2n (n = 0, 1) value matches the timer register 2 (tm2) value more than once during one pwm output cycle. however, the interrupt due to a match occurs. figure 10-16. example of compare register (cm20) rewrite remark alv20 = 1 cm20 to20 tm2 count value 0h t1 t1 t2 t1 t2 ffffh cm20 and tm2 values match, but to20 does not change here. cm20 rewritten ffffh t2 244 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud if a value smaller than that of the tm2 is set as the cm2n value, a 100 % duty pwm signal will be output. cr2n rewriting should be performed by the interrupt due to a match between tm2 and the cm2n on which the rewrite is performed. figure 10-17. example of 100 % duty with pwm output remark alv20 = 0 cm20 to20 tm2 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm2 value n3 is written to cm20 here, the duty of this period will be 100 %. ffffh ffffh ffffh ffffh n2 n2 n2 n1 245 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (3) stopping pwm output if timer/counter 2 is stopped by clearing (0) the ce2 bit of the timer mode control register 2 (tmc2) during pwm signal output, the output level at the time it was stopped is retained. figure 10-18. when timer/counter 2 is stopped during pwm signal output remark alv20 = 1 cautions 1. the output level of the to2n (n = 0, 1) pin when timer output is disabled (ento2n = 0: n = 0, 1) is the inverse of the value set in alv2n (n =0, 1) bits. therefore, the inactive level is output when timer output is disabled when the pwm output function has been selected. if timer/counter 2 is stopped and then started again while the active level is being output, the active level is continuously output until the next overflow occurs. to return the level to inactive, once disable the timer output (ento2n = 0: n = 0, 1) 2. if the timer output is enabled and the active level is changed at the same time, the output level of the pin may change momentarily. to prevent this, change the active level and then enable the timer output. 3. to change the active level specification(alv2n bit (n = 0, 1) of the timer output control register 2 (toc2)), change the active level specification after the timer output of the corresponding timer output pins has been disabled. to20 tm2 count value 0h cm20 cm20 ffffh ffffh 246 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.7.4 ppg output (1) basic operation of ppg output this function is to output a square wave whose pulse width is determined by the value of one compare register with the cycle of the wave determined by another compare register. in other words, the pwm cycle of the pwm output is varied. to use this function, the timer unit mode register 2 (tum2) must be set as shown in tables 10-9 and 10-10. tables 10-9 and 10-10 shows combinations between compare registers and timer outputs, and how to set the ppg output function. table 10-9. setting ppg output (timer/counter 2) pulse cycle pulse width timer output setting cm21 cm20 to20 set tom20 of tum2 to 1 and clr21 and clr20 to 10 (tm2 is cleared by match with cm21) (refer to figure 10-2 ). cm20 cm21 to21 set tom21 of tum2 to 1 and clr21 and clr20 to 01 (tm2 is cleared by match with cm20) (refer to figure 10-2 ). table 10-10. setting ppg output (timer/counter 3) pulse cycle pulse width timer output setting cm31 cm30 to30 set tom30 of tum2 to 1 and clr31 and clr30 to 10 (tm3 is cleared by match with cm31) (refer to figure 10-2 ). cm30 cm31 to31 set tom31 of tum2 to 1 and clr31 and clr30 to 01 (tm3 is cleared by match with cm30) (refer to figure 10-2 ). the pulse cycle and pulse width are as follows: (a) when pulse cycle is set to cm21, and pulse width, to cm20 ppg cycle = (cm21 + 1) x/f clk : x = 4, 8, 16, 32, 64 ppg pulse width = cm20 x/f clk where, 1 cm20 < cm21 note duty = ppg pulse width = cm20 ppg cycle cm21 + 1 note cm20 = cm21 is prohibited. (b) when pulse cycle is set to cm20, and pulse width, to cm21 ppg cycle = (cm20 + 1) x/f clk : x = 4, 8, 16, 32, 64 ppg pulse width = cm21 x/f clk where, 1 cm21 < cm20 note duty = ppg pulse width = cm21 ppg cycle cm20 + 1 note cm20 = cm21 is prohibited. 247 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-19 shows an example of ppg output by using timer register 2 (tm2) (pulse cycle: cm21, pulse width: cm20). figure 10-19. example of ppg output using tm2 remark alv20 = 0, alv21 = 0 table 10-11. ppg output of to20 and to21 (f clk = 16 mhz) count clock minimum pulse width ppg cycle ppg frequency f clk /4 0.25 s 0.75 s 16.4 ms 1333 khz 61.0 hz f clk /8 0.5 s 1.5 s 32.8 ms 666 khz 30.5 hz f clk /16 1.0 s 3.0 s 65.5 ms 333 khz 15.3 hz f clk /32 2.0 s 6.0 s 131 ms 166 khz 7.63 hz f clk /64 4.0 s 12.0 s 262 ms 83.3 khz 3.81 hz intcm21 tm2 count value 0h cm20 pulse cycle cm20 cm20 cm21 cm21 cm21 intcm20 to20 (ppg output) to21 (toggle output) pulse width count started 248 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (2) rewriting compare register (cm20 or cm21) to which pulse width is set even if the value of cm2n (n = 0, 1) (the compare register to which a pulse width has been set) matches with the value of timer register 2 (tm2) during a period of one cycle of ppg output, the output level of timer output (to2n: n = 0, 1) does not change. however, the interrupt due to a match occurs. an example where the pulse cycle is set by cm21 and pulse width is set by cm20 is shown below. figure 10-20. example of compare register (cm20) rewrite remark alv20 = 1 cm20 to20 tm2 count value 0h t1 t2 t1 t2 t1 t2 cm20 and tm2 values match, but to20 does not change here. cm20 rewritten cm21 t1 cm21 cm21 249 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud if a value equal to or less than the tm2 value is written to cm20 before the cm20 and tm2 match, the duty of that ppg cycle will be 100 %. cm20 rewriting should be performed by the interrupt due to a match between tm2 and cm20. figure 10-21. example of 100 % duty with ppg output remark alv20 = 0 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cm2n cannot be rewritten by interrupt processing that is performed on match between timer register 2 (tm2) and compare register (cm2n: n = 0, 1). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). cm20 to20 tm2 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm2 value n3 is written to cm20 here, the duty of this period will be 100 %. cm21 cm21 cm21 cm21 n2 n2 n2 n1 250 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (3) rewriting compare register (cm20, cm21) to which pulse cycle is set if the value of cm2n (n = 0, 1) (the compare register to which a pulse cycle has been set) is less than the value of timer register 2 (tm2) when the value of cm2n is changed to a value less than the current value, the ppg cycle is extended to the time during which tm2 completes its full count. an example where the pulse cycle is set by cm21 and pulse width is set by cm20 is given below. at this time, the output level is inactive until tm2 overflows if the value of cm21 is rewritten after the value of compare register (cm20) has matched with that of tm2, and then the normal ppg output is performed. if cm21 is rewritten before cm20 and tm2 match, the active level will be output until cm20 and tm2 match. if cm20 and tm2 match before tm2 overflows and becomes 0, the inactive level is output at that point. when tm2 overflows and becomes 0, the active level will be output, and normal ppg output will be restored. cm21 rewriting should be performed by the interrupt due to a match between tm2 and cm21, etc. figure 10-22. example of extended ppg output cycle remark alv20 = 1 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cm2n cannot be rewritten by interrupt processing that is performed on match between timer register 2 (tm2) and compare register (cm2n: n = 0, 1). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). cm20 to20 tm2 count value 0h n3 n4 n2 to20 becomes inactive level when cm20 and tm2 match, otherwise it remains at the active level. full count value n4 n2 n3 n1 n2 cm21 n5 n3 n1 n1 n1 when value n2 smaller than the tm2 value n5 is written to cm21 here, the ppg cycle is extended. ffffh 251 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (4) stopping ppg output if timer/counter 2 is stopped by clearing (0) the ce2 bit of the timer mode control register 2 (tmc2) during ppg signal output, the output level at the time timer/counter 2 was stopped is retained as is. figure 10-23. when timer/counter 2 is stopped during ppg signal output remark alv20 = 1 cautions 1. the output level of the to2n (n = 0, 1) pin when timer output is disabled (ento2n = 0: n = 0, 1) is the inverse value of the value set in alv2n (n = 0, 1) bits. therefore, the inactive level is output when timer output is disabled when the ppg output function has been selected. if timer/counter 2 is stopped and then started again while the active level is being output, the active level is continuously output until the next match and clearing occurs. to return the level to inactive, once disable the timer output (ento2n = 0: n = 0, 1) 2. if the timer output is enabled and the active level is changed at the same time, the output level of the pin may change momentarily. to prevent this, change the active level and then enable the timer output. 3. to change the active level specification(alv2n bit (n = 0, 1) of the timer output control register 2 (toc2)), change the active level specification after the timer output of the corresponding timer output pins has been disabled. to20 tm2 count value 0h cm20 cm21 cm21 cm20 252 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.8 examples of use 10.8.1 operation as interval timer (1) when timer register 2 (tm2) is made free-running and a fixed value is added to the compare register (cm2n: n = 0, 1) in the interrupt processing routine, tm2 operates as an interval timer with the added fixed value as the cycle (refer to figure 10-24 ). taking an example where the compare register cm20 is used, the control register settings are shown in figure 10-25, the setting procedure in figure 10-26, and the processing in the interrupt processing routine in figure 10-27. figure 10-24. timing of interval timer operation (1) remark interval time = n x/f clk y n ffffh x = 4, 8, 16, 32, 64 y is limited by the data transfer processing time. consider the processing time of the interrupt used or the macro service processing time (refer to table 16-11 interrupt acceptance processing time and table 16-12 macro service processing time ). mod(2n) intcm20 interrupt request tm2 count value 0h ffffh ffffh compare register (cm20) n timer started mod(3n) mod(4n) n mod(2n) mod(3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program 253 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-25. control register settings for interval timer operation (1) (a) prescaler mode register 2 (prm2) (b) timer unit mode register 2 (tum2) (c) timer mode control register 2 (tmc2) : dont t care 7 0 prm2 6 5 4 3 0 2 prm22 1 prm21 0 prm20 specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64 or external clock) 7 tum2 6 5 4 3 2 0 1 0 0 0 disables tm2 clearing specifies to20 for toggle outputs 7 0 tmc2 6 0 5 0 4 0 3 2 1 10 0 overflow flag enables count operation 254 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-26. setting procedure of interval timer operation (1) figure 10-27. interrupt request processing of interval timer operation (1) interval timer (1) intcm20 interrupt ; set 1 to bit 1 of tmc2 set prm2 set count value in cm20 cm20 n set tmc2 ce2 1 set tum2 intcm20 interrupt calculate timer value that will generate next interrupt cm20 cm20 + n other interrupt processing program reti 255 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.8.2 operation as interval timer (2) tm2 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 10-28 ). taking an example where the compare register cm21 is used, the control register settings are shown in figure 10-29, and the setting procedure in figure 10-30. figure 10-28. timing of interval timer operation (2) remark interval = (n+1) x/f clk 0 n ffffh, x = 4, 8, 16, 32, 64 compare register (cm21) intc21 interrupt request tm2 count value 0h n n n count started cleared cleared interval interrupt acknowledged interrupt acknowledged interval 256 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-29. control register settings for interval timer operation (2) (a) prescaler mode register 2 (prm2) (b) timer unit mode register 2 (tum2) (c) timer mode control register 2 (tmc2) : don t care 7 0 prm2 6 5 4 3 0 2 prm22 1 prm21 0 prm20 specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64 or external clock) 7 tum2 6 5 4 3 0 2 1 1 0 0 disables tm2 clearing by match of cm21 and tm2 specifies to21 for toggle outputs 7 0 tmc2 6 0 5 0 4 0 3 2 1 10 0 overflow flag enables count operation 257 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-30. setting procedure of interval timer operation (2) interval timer (2) set count value to cm21 cm21 n intcm21 interrupt ; set 1 to bit 1 of tmc2 set prm2 set tmc2 ce2 1 set tum2 258 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.8.3 operation as pwm output in pwm output, pulses with the duty ratio determined by the value set in the compare register (cm2n: n = 0, 1) are output (refer to figure 10-31 ). taking an example where to21 pin is used as a timer output pin, the control register settings are shown in figure 10- 32, the setting procedure in figure 10-33, and the procedure for varying the duty in figure 10-34. figure 10-31. example of timer/counter 2 pwm signal output remark alv21 = 0 ffffh ffffh ffffh tm2 count value 0h to21 timer started 259 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-32. control register settings for pwm output operation (a) timer mode control register 2 (tmc2) (d) timer output control register 2 (toc2) : don t care (e) port 1 mode control register (pmc1) (c) timer unit mode register 2 (tum2) (b) prescaler mode register 2 (prm2) 7 0 tmc2 6 0 5 0 4 0 3 2 1 10 0 overflow flag enables count operation 7 0 prm2 6 5 4 3 0 2 prm22 1 prm21 0 prm20 specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64 or external clock) 7 tum2 6 5 4 3 1 2 1 0 0 0 disables tm2 clearing specifies to21 as pwm outputs 7 toc2 6 5 4 3 1 2 0 1 0 to21 = active-high pmw signal output enables to21 pmw output 7 0 pmc1 6 0 5 0 4 0 3 2 1 1 0 sets p11 pin as to21 output 260 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-33. setting procedure of pwm output pwm output set tum2 set toc2 set p11 pin to control mode pmc1.1 1 start count ce2 1 ; set bit 1 of tmc2 set count clock to prm2 set initial value to cm21 261 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-34. changing pwm output duty duty change preprocessing clear intcm21 interrupt request flag cmif21 0 enable intcm21 interrupts cmmk21 0 ; clear bit 7 of cmic21 ; clear bit 6 of cmic21 (or bit 5 of mk0h) intcm21 interrupt duty change processing set duty value to cm21 disable intcm21 interrupts cmmk21 1 ; set bit 6 of cmic21 (or bit 5 of mk0h) reti 262 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.8.4 operation as ppg output in ppg output, pulses with the cycle and duty ratio determined by the value set in the compare register (cm2n: n = 0, 1) are output (refer to figure 10-35 ). taking an example where to20 pin is used as a timer output pin, the control register settings are shown in figure 10- 36, the setting procedure in figure 10-37, and the procedure for varying the duty in figure 10-38. figure 10-35. example of timer/counter 2 ppg signal output remark alv20 = 0 cm21 cm20 cm21 cm20 cm21 cm20 tm2 count value 0h to20 timer started 263 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-36. control register settings for ppg output operation (1/2) (a) timer mode control register 2 (tmc2) (b) prescaler mode register 2 (prm2) (d) timer output control register 2 (toc2) : don t care (c) timer unit mode register 2 (tum2) 7 0 tmc2 6 0 5 0 4 0 3 2 1 10 0 overflow flag enables count operation 7 0 prm2 6 5 4 3 0 2 prm22 1 prm21 0 prm20 specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64 or external clock) 7 tum2 6 5 4 3 0 2 1 1 1 0 0 clears by match of tm2 and cm21 specifies to20 as ppg output 7 toc2 6 5 4 3 2 1 10 0 to20 is active-high ppg signal output enables to20 ppg output 264 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-36. control register settings for ppg output operation (2/2) (e) port 1 mode control register (pmc1) : don t care 7 pmc1 6 5 4 3 2 1 1 0 sets p10 pin as to20 output 265 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-37. setting procedure of ppg output ppg output set tum2 set p10 pin to control mode pmc1.0 1 start count ce2 1 set toc2 ; set bit 1 of tmc2 set count clock to prm2 set cycle to cm21 set duty to cm20 266 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-38. changing ppg output duty duty change preprocessing clear intcm20 interrupt request flag cmif20 0 ; clear bit 7 of cmic20 enable intcm20 interrupts cmmk20 0 ; clear bit 6 of cmic20 (or bit 4 of mk0h) intcm20 interrupt duty change processing set duty value to cm20 disable intcm20 interrupts cmmk20 1 ; set bit 6 of cmic20 (or bit 4 of mk0h) reti 267 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.8.5 operation as external event counter an external event counter counts clock pulses (ti2 pin input pulses) input from off-chip. the operation of the external event counter is explained where the ti2 pin input valid edge is specified to be the rising edge. as shown in figure 10-39, the value of timer register 2 (tm2) is incremented in synchronization with a ti2 pin input valid edge. figure 10-39. external event counter operation remark the tm2 value is the same as the number of input clock pulses. the control register settings when tm2 operates as an external event counter are shown in figure 10-40, and the setting procedure in figure 10-41. ti2 pin input tm2 n+1 n+2 n 268 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud figure 10-40. control register settings for external event counter operation (a) prescaler mode register 2 (prm2) (b) external interrupt mode register 0 (intm1) (c) timer mode control register 2 (tmc2) : don t care figure 10-41. setting procedure of external event counter operation 7 0 prm2 6 5 4 3 0 2 1 1 0 0 1 specifies external clock input (ti2) 7 intm1 6 5 0 4 1 3 2 1 0 specifies rising edge as ti2 input valid edge 7 0 tmc2 6 0 5 0 4 0 3 2 1 10 0 overflow flag enables count operation event counter ; set 1 in bit 1 of tmc2 set prm2 start count ce2 1 specify ti2 pin input valid edge 269 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud 10.9 cautions (1) the prescaler uses one time base commonly with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer 4). if one of the timers sets the ce bit to 1 , the time base starts counting. if another timer sets the ce bit to 1 while one timer operates, the first count clock of the timer may be shortened because the time base has already started counting. for example, when using timer/counter 2 as an interval timer, the first interval time is shortened by up to 1 count clock. the second and those that follow are at the specified interval. figure 10-42. operation when counting is started disables interrupt from timer/ counter 2 clears interrupt request flag for timer/ counter 2 interrupt request from timer/counter 2 occurs between these instructions . . . . . . . . . . . . (2) while timer/counter 2 is operating (while the ce2 bit of the timer mode control register 2 (tmc2) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. timer unit mode register 2 (tum2) timer output control register 2 (toc2) prescaler mode register 2 (prm2) (3) if the contents of the compare register (cm2n: n = 0, 1) match with those of tm2 when an instruction that stops timer register 2 (tm2) operation is executed, the counting operation of tm2 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm2, mask the interrupt in advance by using the interrupt mask register before stopping tm2. example program that may generate interrupt request program that does not generate interrupt request clr1 ce2 or mk0h, #30h or mk0h, #30h clr1 ce2 clr1 cmif20 clr1 cmif21 count clock tm2 ce2 count start command (ce2 1) by software 1 0 234 270 chapter 10 timers/counters 2 and 3 user s manual u11515ej3v0ud (4) match between timer register 2 (tm2) and compare register (cm2n: n = 0, 1) is detected only when tm2 is incremented. therefore, the interrupt request is not generated and timer output (to2n: n = 0, 1) does not change even if the same value as tm2 is written to cm2n. (5) during ppg output, if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the compare register (cm2n: n = 0, 1) cannot be rewritten by interrupt processing that is performed on match between timer register (tm2) and compare register (cm2n). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (6) the output level of the to2n (n = 0, 1) when the timer output is disabled (ento2n = 0: n = 0, 1) is the reverse value of the value set to the alv2n (n = 0, 1) bit. therefore, an inactive level is output when the timer output is disabled with the pwm output function or ppg output function selected. if timer/counter 2 is stopped and then started again while the active level is output, the pwm output continuously output the active level until the next overflow occurs (in the case of the ppg output, until the next match and clearing). to return the level to inactive, once disable the timer output (ento2n = 0: n = 0, 1). (7) if the timer output is enabled and the active level is changed at the same time, the output level of the pin may change momentarily. to prevent this, change the active level and then enable the timer output. (8) to change the active level specification(alv2n bit (n = 0, 1) of the timer output control register 2 (toc2)), change the active level specification after the timer output of the corresponding timer output pins has been disabled. (9) if 0000h is set to a compare register (cm20, cm21), the comparison operation is performed after counting has been completed. therefore, the interrupt due to a match (intcm20, intcm21) does not occur immediately after counting has been started. if cm2n (n = 0, 1) is set to 0000h, the timer counts up to ffffh, overflows, and then the interrupt due to a match intcm2n (n = 0, 1) occurs. figure 10-43. operation when compare register (cm20, cm21) is set to 0000h remark n = 0, 1 remark cautions (1) through (9) above also applies to timer/counter 3. interrupt occurred count started match match match match cleared cleared cleared 0000h count clock tm2 ce2 cm2n intcm2n 0h 1h 2h 3h 4h 5h ffffh 0h 0h 0h 0h chapter 11 timer 4 271 user? manual u11515ej3v0ud chapter 11 timer 4 11.1 function timer 4 is a 16-bit timer. in addition to its function as an interval timer, this timer can be used to generate the output trigger of the real-time output port. when used as an interval timer, timer 4 generates an internal interrupt at a predetermined interval. table 11-1. interval time of timer 4 minimum interval time maximum interval time resolution 4/f clk (0.25 s) 2 16 4/f clk (16.4 ms) 4/f clk (0.25 s) 8/f clk (0.5 s) 2 16 8/f clk (32.8 ms) 8/f clk (0.5 s) 16/f clk (1.0 s) 2 16 16/f clk (65.5 ms) 16/f clk (1.0 s) 32/f clk (2.0 s) 2 16 32/f clk (131 ms) 32/f clk (2.0 s) 64/f clk (4.0 s) 2 16 64/f clk (262 ms) 64/f clk (4.0 s) ( ): at f clk = 16 mhz 11.2 configuration timer 4 consists of the following registers: timer register (tm4) 1 compare register (cm4n) 2 (n = 0, 1) figure 11-1 shows the block diagram of timer 4. 272 chapter 11 timer 4 user? manual u11515ej3v0ud figure 11-1. block diagram of timer 4 internal bus internal bus 16 compare register 40 (cm40) 16 16 match 16 compare register 41 (cm41) 16 16 match timer register 4 (tm4) clear overflow reset 1/8 clr41 ce4 clr40 timer mode control register 4 (tmc4) intcm40 real-time output port intcm41 intov4 1/8 16 prm41 prm42 prm40 selector f clk /64 f clk /32 f clk /16 f clk /8 f clk /4 f clk prescaler prescaler mode register 4 (prm4) chapter 11 timer 4 273 user s manual u11515ej3v0ud (1) timer register 4 (tm4) tm4 is a timer register that counts up the count clock specified by the prescaler mode register 4 (prm4). counting of this timer register is enabled or disabled by the timer mode control register 4 (tmc4). the timer register can be only read by using a 16-bit manipulation instruction. when reset is input, tm4 is cleared to 0000h and stops counting. (2) compare registers (cm40, cm41) cm4n (n = 0, 1) is a 16-bit register that holds the contents determining the cycle of the interval timer operation. when the contents of cm4n matches with the contents of tm4, an interrupt request (intcm4n: n = 0, 1) is generated. intcm40 also serves as the trigger signal of the real-time output port. the count value of tm4 can be cleared when its value matches with the contents of cm4n. these compare registers can be read or written by using 16-bit manipulation instructions. when reset is input, their contents are undefined. (3) prescaler the prescaler generates a count clock by dividing the internal system clock. the clock generated by the prescaler is selected by the selector, and tm4 performs the count operation by using this clock as a count clock. (4) selector the selector selects one of the five signals generated by dividing the internal system clock as the count clock of tm4. 274 chapter 11 timer 4 user s manual u11515ej3v0ud 11.3 timer 4 control register (1) timer mode control register 4 (tmc4) tmc 4 is a register that controls the count and clear operations of timer register 4 (tm4). this register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 11-2 shows the format of tmc4. when reset is input, the value of this register is cleared to 00h. figure 11-2. format of timer mode control register 4 (tmc4) 0000ce40 clr41 clr40 7654 210 ce4 0 1 controls count operation of tm4 clears and stops counting enables counting operation tmc4 address: 0ff37h on reset: 00h r/w clr41 0 1 clear operation of tm4 by match with cm41 disables (free running mode) enables (interval timer mode) clr40 0 1 clear operation of tm4 by match with cm40 disables (free running mode) enables (interval timer mode) 3 chapter 11 timer 4 275 user s manual u11515ej3v0ud (2) prescaler mode register 4 (prm4) prm4 is a register that specifies the count clock of timer register 4 (tm4). this register can be read or written by using an 8-bit manipulation instruction. figure 11-3 shows the format of prm4. when reset is input, the value of this register is cleared to 00h. figure 11-3. format of prescaler mode register 4 (prm4) remark f clk : internal system clock address: 0ff3ah on reset: 00h r/w 00000 prm42 prm41 prm40 76543210 prm4 prm42 0 0 0 0 1 specifies count clock of tm4. f clk /4 f clk /8 f clk /16 f clk /32 f clk /64 setting prohibited prm41 0 0 1 1 0 prm40 0 1 0 1 0 count clock [hz] resolution [ s] 0.25 0.5 1.0 2.0 4.0 other (f clk = 16 mhz) 276 chapter 11 timer 4 user s manual u11515ej3v0ud 11.4 operation of timer register 4 (tm4) 11.4.1 basic operation timer 4 counts up by using the count clock specified by the prescaler mode register 4 (prm4). counting is enabled or disabled by the ce4 bit of the timer mode control register 4 (tmc4). when the ce4 bit is set (1) by software, tm4 is set to 0001h at the first count clock, and starts counting up. when the ce4 bit is cleared (0) by software, tm4 is immediately cleared to 0000h, and stops generation of the match signal. if the ce4 bit is set (1) while it has been already set (1), tm4 is not cleared but continues counting. if a count clock is input when tm4 reaches ffffh, tm4 is cleared to 0000h, and an overflow interrupt (intov4) occurs. when reset is input, tm4 is cleared to 0000h and stops counting. chapter 11 timer 4 277 user s manual u11515ej3v0ud figure 11-4. basic operation of timer register 4 (tm4) (a) when counting starts, stops, and then starts again (c) operation when tm4 is ffffh (b) if ce4 bit is set to ??again after counting has been started tm4 ce4 0h 1h 2h 3h ffh 100h 101h 1h 2h 0h count started ce4 1 count stopped ce4 0 count started ce4 1 count clock tm4 ce4 0h 1h 2h 3h 4h 5h 6h 7h count started ce4 1 rewritten ce4 1 count clock tm4 intov4 interrupt request fffeh ffffh 0h count clock 1h 278 chapter 11 timer 4 user s manual u11515ej3v0ud 11.4.2 clear operation (1) clear operation by match with compare register timer register 4 (tm4) can be automatically cleared when its value matches with the value of a compare register (cm4n: n = 0, 1). when a clearance source arises, tm3 is cleared to 0000h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 11-5. tm4 clear operation by match with compare register (cm40, cm41) remark n = 0, 1 (2) clear operation by ce4 bit of timer mode control register 4 (tmc4) timer register 4 (tm4) is also cleared when the ce4 bit of tmc4 is cleared (0) by software. the clear operation is performed following clearance (0) of the ce4 bit in the same way. count clock tm4 n 0 1 n 1 compare register (cm4n) n tm4 and cm4n match cleared here chapter 11 timer 4 279 user s manual u11515ej3v0ud figure 11-6. clear operation of tm4 when ce4 bit is cleared (0) (a) basic operation (c) restart when count clock is input after clearance (b) restart before count clock is input after clearance count clock tm4 n 0 n 1 ce4 count clock tm4 n n 1 ce4 1 23 if the ce4 bit is set (1) before this count clock, the count starts from 1 on this count clock 0 count clock tm4 n 0 n 1 ce4 0 12 if the ce4 bit is set (1) from this count clock onward, the count starts from 1 on the count clock after the ce4 bit is set (1). 280 chapter 11 timer 4 user s manual u11515ej3v0ud 11.5 operation of compare register timer 4 performs a compare operation by comparing the value set to a compare register (cm40, cm41) with the count value of a timer register 4 (tm4). if the count value of tm4 matches with the value set in advance to cm4n (n = 0, 1) as a result of counting by tm4, an interrupt request (intcm4n: n = 0, 1) is generated. moreover, the contents of tm4 can be cleared after it has matched with the value of cm4n, so that tm4 can operate as an interval timer that repeatedly counts the value set to cm4n. table 11-2. interrupt request signal from compare register (timer 4) compare register interrupt request signal cm40 intcm40 cm41 intcm41 chapter 11 timer 4 281 user s manual u11515ej3v0ud figure 11-7. compare operation (timer 4) remark clr40 = 0, clr41 = 0 figure 11-8. tm4 clearance after match detection intcm40 interrupt request tm4 count value 0h ffffh count started ce4 1 cm40 value cm41 value ffffh cm40 value cm41 value intcm41 interrupt request intov4 interrupt request match match match match intcm40 interrupt request tm4 count value 0h cm41 count started ce4 1 clr40 0 clr41 1 ce4 0 clr40 1 clr41 0 intcm41 interrupt request cm40 cm40 cm40 count disabled ce4 0 count started cleared cleared cleared 282 chapter 11 timer 4 user s manual u11515ej3v0ud 11.6 example of use 11.6.1 operation as interval timer (1) by setting the timer register 4 (tm4) in the free running mode and adding a specific value to a compare register (cm4n: n = 0, 1) in an interrupt processing routine, tm4 can be used as an interval timer whose cycle is determined by the specific value to be added (refer to figure 11-9 ). figure 11-10 shows the set contents of the control registers, figure 11-11 shows how to set the control registers, and figure 11-12 shows the processing in the interrupt routine, where compare register cm40 is used. figure 11-9. timing of interval timer operation (1) remark interval time = n x/f clk y n ffffh x = 4, 8, 16, 32, 64 y is limited by the data transfer processing time. consider the processing time of the interrupt used or the macro service processing time (refer to table 16-11 interrupt acceptance processing time and table 16-12 macro service processing time ). mod(2n) intcm40 interrupt request tm4 count value 0h ffffh compare register (cm40) n timer started mod(3n) mod(4n) ffffh n mod(2n) mod(3n) interval time interval time interval time rewriting by interrupt program rewriting by interrupt program rewriting by interrupt program chapter 11 timer 4 283 user s manual u11515ej3v0ud figure 11-10. set contents of control registers for interval timer operation (1) (a) prescaler mode register 4 (prm4) (b) timer mode control register 4 (tmc4) 00000 prm42 prm41 prm40 76543210 prm4 specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64) 00001000 76543210 tmc4 disables tm4 clearing enables count operation 284 chapter 11 timer 4 user s manual u11515ej3v0ud figure 11-11. setting procedure of interval timer operation (1) figure 11-12. interrupt request processing of interval timer operation (1) interval timer (1) sets count value to cm40 cm40 n intcm40 interrupt sets prm4 sets tmc4 intcm40 interrupt calculates timer value at which interrupt occurs next cm40 cm40 + n other interrupt processing program reti chapter 11 timer 4 285 user s manual u11515ej3v0ud 11.6.2 operation as interval timer (2) tm4 can be used as an interval timer that repeatedly generates an interrupt at interval determined by the count value set in advance (refer to figure 11-13 ). figure 11-4 shows the set contents of the control registers, and figure 11-15 shows how to set the control registers, where compare register cm41 is used. figure 11-13. timing of interval timer operation (2) remark interval time = (n+1) x/f clk 0 n ffffh x = 4, 8, 16, 32, 64 compare register (cm41) intcm41 interrupt request tm4 count value 0h n n n count started cleared cleared interval time interrupt accepted interrupt accepted interval time 286 chapter 11 timer 4 user s manual u11515ej3v0ud figure 11-14. set contents of control register for interval timer operation (2) (a) prescaler mode register 4 (prm4) (b) timer mode control register 4 (tmc4) figure 11-15. setting procedure of interval timer operation (2) 00000 prm42 prm41 prm40 76543210 prm4 specifies count clock (f clk /x ; x = 4, 8, 16, 32, 64) 00001010 76543210 tmc4 tm4 clearing by match of cm41 and tm4 enables count operation interval timer (2) sets count value to cm41 cm41 n intcm41 interrupt sets prm4 sets tmc4 chapter 11 timer 4 287 user s manual u11515ej3v0ud 11.7 cautions (1) the prescaler uses one time base commonly with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer 4). if one of the timers sets the ce bit to 1 , the time base starts counting. if another timer sets the ce bit to 1 while one timer operates, the first count clock of the timer may be shortened because the time base has already started counting. for example, if a timer/counter is used as an interval timer, the first interval will be shortened by up to one count clock. the second and subsequent intervals will be as specified. figure 11-16. operation when count starts interrupt request gener- ated by timer 4 here disables interrupts from timer 4 clears timer 4 interrupt request flag . . . . . . (2) there is a possibility of misoperation if the next register contents are rewritten while the timer 4 is running (when the ce4 bit of the timer mode control register 4 (tmc4) is set). the misoperation occurs as there is no defined order of priority in the event of contention between the timings at which the hardware function changes due to a register rewrite and the status changes in the function prior to the rewrite. when the contents of following registers are rewritten, counter operations must be stopped first to ensure stability. clr40 and clr41 bits of timer mode control register 4 (tmc4) prescaler mode register 4 (prm4) (3) if the compare register (cm4n: n = 0, 1) and tm4 contents match when an instruction that stops timer register 4 (tm4) operation is executed, the tm4 count operation stops, but an interrupt request is generated. if you do not want an interrupt to be generated when tm4 operation is stopped, interrupts should be masked by means of interrupt the mask register before stopping the tm4. example program in which an interrupt request may be program in which an interrupt request is not generated generated clr1 ce4 or mk1l, #03h or mk1l, #03h clr1 ce4 clr1 cmif40 clr1 cmif41 . . . . . . count clock tm4 0 ce4 14 2 3 software count start directive (ce4 1) 288 chapter 11 timer 4 user s manual u11515ej3v0ud (4) match between timer register 4 (tm4) and compare register (cm4n: n = 0, 1) is detected only when tm4 is incremented. therefore, the interrupt request is not generated even if the same value as tm4 is written to cm4n. (5) if a compare register (cm40, cm41) is set to 0000h, the compare operation is performed after counting has been completed. therefore, the interrupt due to a match (intcm40, intcm41) does not occur immediately after counting has been started. if cm4n (n = 0, 1) is set to 0000h, tm4 counts up to ffffh, overflows, and then the interrupt due to a match intcm4n (n = 0, 1) occurs. figure 11-17. operation when compare register (cm40, cm41) is set to 0000h remark n = 0, 1 interrupt occurred count started match match match match cleared cleared cleared 0000h count clock tm4 ce4 cm4n intcm4n 0h 1h 2h 3h 4h 5h ffffh 0h 0h 0h 0h 289 user? manual u11515ej3v0ud chapter 12 watchdog timer function the watchdog timer is a timer that detects inadvertent program loops. watchdog timer interrupts are used to detect system or program errors. for this purpose, instructions that clear the watchdog timer (start the count) within a given period are inserted at various places in a program. if an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (intwdt) is generated and a program error is reported. 12.1 configuration the watchdog timer block diagram is shown in figure 12-1. figure 12-1. block diagram of watchdog timer watchdog timer (8-bit) overflow wdt clr f clk intwdt f clk /2 9 f clk /2 11 f clk /2 12 f clk /2 13 frequency divider selector 290 chapter 12 watchdog timer function user s manual u11515ej3v0ud 12.2 watchdog timer mode register (wdm) the wdm is an 8-bit register that controls the watchdog timer operation. to prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by a dedicated instruction. this dedicated instruction, mov wdm,#byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements. if the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (mov wdm, a, and wdm, #byte, set1 wdm.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. after a system reset (reset input), once the watchdog timer has been started (by setting (1) the run bit), the wdm contents cannot be changed. the watchdog timer can only be stopped by a reset, but can be cleared at any time with a dedicated instruction. the wdm can be read at any time by a data transfer instruction. reset input clears the wdm to 00h. the wdm format is shown in figure 12-2. 291 chapter 12 watchdog timer function user s manual u11515ej3v0ud figure 12-2. format of watchdog timer mode register (wdm) remark f clk : internal system clock cautions 1. the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). 2. the same value should be written each time in writes to the wdm to set (1) the run bit. the contents written the first time cannot be changed even if a different value is written. 3. once the run bit has been set (1), it cannot be reset (0) by software. run 0 0 prc 0 wdi2 wdi1 0 76543210 run 0 1 specifies operation of watchdog timer stops watchdog timer clears watchdog timer to start counting wdm address: 0ffc2h on reset: 00h r/w prc 0 1 priority of interrupt request of watchdog timer interrupt request of watchdog timer < interrupt request of nmi pin input interrupt request of watchdog timer > interrupt request of nmi pin input wdi2 0 0 1 1 overflow time [ms] f clk /2 9 f clk /2 11 f clk /2 12 f clk /2 13 wdi1 0 1 0 1 count clock f clk = 12.5 mhz f clk = 16.0 mhz 10.5 41.9 83.9 167.8 8.2 32.8 65.5 131.1 292 chapter 12 watchdog timer function user s manual u11515ej3v0ud 12.3 operation 12.3.1 count operation the watchdog timer is cleared, and the count started, by setting (1) the run bit of the watchdog timer mode register (wdm). when overflow time specified by the wdi2 and wdi1 bits of wdm has elapsed after the run bit has been set (1), a non-maskable interrupt (intwdt) is generated. if the run bit is set (1) again before the overflow time elapses, the watchdog timer is cleared and the count operation is started again. 12.3.2 interrupt priorities the watchdog timer interrupt (intwdt) is a non-maskable interrupt. other non-maskable interrupts are interrupts from the nmi pin (nmi). the order of acknowledgment when an intwdt interrupt and nmi interrupt are generated simultaneously can be specified by the setting of bit 4 of the watchdog timer mode register (wdm). even if intwdt is generated while the nmi processing program is executed when nmi acknowledgement is specified to take precedence, intwdt is not acknowledged until completion of execution of the nmi processing program. 293 chapter 12 watchdog timer function user s manual u11515ej3v0ud 12.4 cautions 12.4.1 general cautions on use of watchdog timer (1) the watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program loops. therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing to be performed that will restore the normal state or establish a stable state and then stop the operation. (2) the watchdog timer cannot detect inadvertent program loops in the following cases. <1> if watchdog timer clearance is performed in the timer interrupt processing program <2> if cases where an interrupt request or macro service is held pending (refer to 16.9 ) occur consecutively <3> if the watchdog timer is cleared periodically when the program is looping inadvertently due to an error in the program logic (if each module of the program functions normally but the overall program does not) <4> if the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program loop occurs <5> if the stop mode, halt mode, or idle mode is entered as the result of an inadvertent program loop <6> if an inadvertent program loop of watchdog timer also occurs in the event of cpu hang up due to external noise in cases <1>, <2> and <3> the program can be amended to allow detection to be performed. in case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. similarly, in case <5>, the stop mode, halt mode, or idle mode cannot be set unless a 4-byte dedicated instruction is used. for state <2> to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a specific pattern (e.g. bt pswl. bit, $$, etc.). therefore, the establishment of state <2> as the result of <4>, <5> or an inadvertent program loop is likely to be extremely rare. 12.4.2 cautions on pd784046 subseries watchdog timer (1) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). (2) the same value should be written each time in writes to the watchdog timer mode register (wdm) to set (1) the run bit. the contents written the first time cannot be changed even if a different value is written. (3) once the run bit has been set (1), it cannot be reset (0) by software. 294 user? manual u11515ej3v0ud chapter 13 a/d converter the pd784046 incorporates an analog/digital (a/d) converter with 16 multiplexed analog inputs (ani0 to ani15). the successive approximation conversion method is used, and the conversion result is held in the 10-bit a/d conversion result register (adcr0-adcr7). this allows fast, high-precision conversion to be performed (conversion time of 13 s when f clk = 16 mhz and high-speed conversion is used). there are two modes for starting a/d conversion, as follows: hardware start : conversion started by trigger input (intp4). software start : conversion started in accordance with a/d converter mode register (adm) bit setting. after start-up, there are two operating modes, as follows: scan mode : multiple analog inputs are selected in order, and conversion data is obtained from all pins. select mode : one pin is used as the analog input, and conversion values are obtained in succession. stoppage of all the above modes and conversion operations is specified by the adm register. in each mode, the conversion result is held in adcrn (n = 0 to 7) each time a/d conversion has been completed. when a/d conversion has been completed, an a/d conversion end interrupt request (intad) is generated. this interrupt can start a macro service that automatically transfers data by hardware. 13.1 configuration figure 13-1 shows the block diagram of the a/d converter. the high-order 8 channels (ani8 through ani15) and low-order 8 channels (ani0 through ani7) of the a/d converter are selected by using the a/d converter mode register (adm). 295 chapter 13 a/d converter user? manual u11515ej3v0ud figure 13-1. block diagram of a/d converter internal bus input selector ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 input selector ani8 ani9 ani10 ani11 ani12 ani13 ani14 ani15 sample & hold circuit voltage comparator edge detection circuit intp4 control circuit conversion trigger intad 10 trigger enable a/d converter mode register (adm) series resistor string r/2 r r/2 av ref av ss 8 10 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d conversion result register reset successive approximation register (sar) tap selector 296 chapter 13 a/d converter user s manual u11515ej3v0ud cautions 1. a capacitor should be connected between the analog input pins (ani0 to ani15) and av ss and between the reference voltage input pin (av ref ) and av ss to prevent misoperation due to noise. be sure to connect the capacitor as closely to ani0 through ani15 and av ref as possible. figure 13-2. example of capacitor connection on a/d converter pins 2. a voltage outside the range av ss to av ref should not be applied to pins used as a/d converter input pins. refer to 13.6 cautions for details. (1) input circuit the input circuit selects the analog input in accordance with the specification of the a/d converter mode register (adm), and sends the analog input to the sample & hold circuit according to the operating mode, (2) sample & hold circuit the sample & hold circuit samples the analog inputs arriving sequentially one by one and holds the analog input in the process of a/d conversion. (3) voltage comparator the voltage comparator determines the voltage difference between the analog input and the series resistor string value tap. (4) series resistor string the series resistor string is used to generate voltages that match the analog inputs. the series resistor string is connected between the a/d converter reference voltage pin (av ref ) and the a/d converter gnd pin (av ss ). to provide 1024 equal voltage steps between the two pins, it is made up of 1023 equal resistors and two resistors with half that resistance value. the series resistor string voltage tap is selected by a tap selector controlled by the successive approximation register (sar). analog input reference voltage input 100 to 500 pf ani0-ani15 av ref av ss pd784046 297 chapter 13 a/d converter user s manual u11515ej3v0ud (5) sar: successive approximation register the sar is an 10-bit register in which the data for which the series resistor string voltage tap value matches the analog input voltage value is set bit by bit starting from the most significant bit (msb). when data has been set up to the least significant bit (lsb) of the sar (when a/d conversion is completed), the sar contents (conversion result) are stored in the a/d conversion result register (adcrn: n = 0-7). (6) edge detection circuit the edge detection circuit detects a valid edge from the interrupt request input pin (intp4) input, and generates an external interrupt request signal (intp4) and a/d conversion operation external trigger. the intp4 pin input valid edge is specified by external interrupt mode register 1 (intm1) (refer to figure 15-2 ). external trigger enabling/disabling is set by means of the a/d converter mode register (adm) (refer to 13.2 a/d converter mode register (adm) ). 298 chapter 13 a/d converter user s manual u11515ej3v0ud 13.2 a/d converter mode register (adm) adm is an 8-bit register that controls a/d converter operations. the adm register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. its format is shown in figure 13-3. bits 0 through 2 (anis0 through anis2) select input analog signals to be converted. bit 3 (ps) selects whether ani0 through ani7 (low-order 8 channels) or ani8 through ani15 (high-order 8 channels) are used as analog input pins. the low-order 8 channels and high-order 8 channels have identical functions. bit 5 (am0) and bit 6 (am1) control the operation mode of a/d conversion. if the am0 and am1 bits are cleared (0), all conversion operations under execution are stopped. at this time, adcrn (n = 0 to 7) is not updated, nor is the intad interrupt request generated. moreover, power supply to the voltage comparator is stopped to reduce the current consumption of the a/d converter. bit 7 (trg) enables external synchronization of the a/d conversion operation. if the trg bit is set (1) when the am0 or am1 bits are set, the conversion operation is initialized each time the valid edge is input to the intp4 pin as an external trigger. if the trg bit is cleared (0), the conversion operation is performed regardless of the intp4 pin input. if data is written to adm during conversion, the conversion operation is initialized and started from the beginning again. when reset is input, the value of adm is reset to 00h. caution when the stop mode or idle mode is used, the consumption current should be reduced by clearing (0) the am0 bit and am1 bit before entering the stop or idle mode. if the am0 bit or am1 bit remains set (1), the conversion operation will be stopped by entering the stop or idle mode, but the power supply to the voltage comparator will not be stopped, and therefore the a/d converter consumption current will not be reduced. 299 chapter 13 a/d converter user s manual u11515ej3v0ud figure 13-3. format of a/d converter mode register (adm) remark f clk : internal system clock trg am1 am0 fr ps anis2 anis1 anis0 7654 210 trg 0 1 controls external trigger disables external trigger enables external trigger adm address: 0ff6eh on reset: 00h r/w am1 0 0 1 1 specifies a/d conversion operation mode stops conversion scan mode select mode am0 0 1 0 1 1-buffer mode 4-buffer mode fr 0 1 selects conversion time 208 clocks (f clk > 12.5 mhz) 169 clocks (f clk 12.5 mhz) anis2 0 0 0 0 1 1 1 1 selects analog input ani0/ani8 ani1/ani9 ani2/ani10 ani3/ani11 ani4/ani12 ani5/ani13 ani6/ani14 ani7/ani15 anis1 0 0 1 1 0 0 1 1 anis0 0 1 0 1 0 1 0 1 in select mode in scan mode ani0/ani8 ani0/ani8, ani1/ani9 ani0/ani8- ani2/ani10 ani0/ani8- ani3/ani11 ani0/ani8- ani4/ani12 ani0/ani8- ani5/ani13 ani0/ani8- ani6/ani14 ani0/ani8- ani7/ani15 ps 0 1 selects analog input pin ani0 through ani7 (port 7) ani8 through ani15 (port 8) 3 300 chapter 13 a/d converter user s manual u11515ej3v0ud table 13-1. conversion time set by fr bit internal system clock: f clk (mhz) 16 14 12.5 10 fr bit 0011 conversion time ( s) 13 14.9 13.5 16.9 caution once the a/d converter starts operating, conversion operations are performed repeatedly until the am0 bit and am1 bit of the a/d converter mode register (adm) is cleared (0). therefore, a superfluous interrupt may be generated if adm setting is performed after interrupt-related registers, etc., when a/ d converter mode conversion, etc., is performed. the result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. it is therefore recommended that a/d converter mode conversion be carried out using the following procedure. <1> write to the adm <2> interrupt request flag (adif) clearance (0) <3> interrupt mask flag setting operations <1> to <3> should not be divided by an interrupt or macro service. alternatively, the following procedure is recommended. <1> stop the a/d conversion operation by clearing (0) the am0 bit and am1 bit of the adm. <2> interrupt request flag (adif) clearance (0). <3> interrupt mask flag setting <4> write to the adm 301 chapter 13 a/d converter user s manual u11515ej3v0ud 13.3 a/d conversion result registers (adcr0 through adcr7) the pd784046 has eight 10-bit a/d conversion result registers (adcr0 through adcr7) that store the results of a/ d conversion. each adcrn (n = 0 to 7) can be only read by using a 16-bit manipulation instruction or an 8-bit manipulation instruction. the conversion result can be read from adcrn in the following two ways: (1) word access (by execution of 16-bit manipulation instruction) of the word data read, the low-order 10 bits are valid. the high-order 6 bits are always 0 when read. figure 13-4 illustrates word access to adcrn. figure 13-4. word access to a/d conversion result register symbol address on reset adcr0 0ff70h undefined adcr1 0ff72h adcr2 0ff74h adcr3 0ff76h adcr4 0ff78h adcr5 0ff7ah adcr6 0ff7ch adcr7 0ff7eh remark ad0-ad9: a/d conversion result symbol adcrn (n = 0-7) 0 15 0 14 0 13 0 12 0 11 0 10 ad9 9 ad8 8 ad7 7 ad6 6 ad5 5 ad4 4 ad3 3 ad2 2 ad1 1 ad0 0 r r/w 302 chapter 13 a/d converter user s manual u11515ej3v0ud (2) byte access (by execution of 8-bit manipulation instruction) of the 10-bit data of the a/d conversion result, the high-order 8 bits are read. figure 13-5 illustrates byte access to adcrn figure 13-5. byte access to a/d conversion result register symbol address on reset adcr0h 0ff71h undefined adcr1h 0ff73h adcr2h 0ff75h adcr3h 0ff77h adcr4h 0ff79h adcr5h 0ff7bh adcr6h 0ff7dh adcr7h 0ff7fh remark ad2 through ad9: a/d conversion result (high-order 8 bits of 10 bits) symbol adcrnh (n = 0-7) ad9 7 ad8 6 ad7 5 ad6 4 ad5 3 ad4 2 ad3 1 ad2 0 r r/w 303 chapter 13 a/d converter user s manual u11515ej3v0ud 13.4 operation 13.4.1 basic a/d converter operation (1) a/d conversion operation procedure a/d conversion is performed by means of the following procedure: (a) analog pin selection and operating mode specification are set with the a/d converter mode register (adm), and the a/d conversion is started. (b) when conversion starts, the msb (bit 9) of the successive approximation register (sar) is set (1) automatically. (c) when bit 9 of the sar is set (1), the tap selector sets the series resistor string voltage tap to av ref ( = 1/2 av ref ). (d) the voltage difference between the series resistor string voltage tap and the analog input is determined by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of the sar remains set (1), and if it is less than (1/2) av ref , the msb is cleared (0). (e) next, bit 8 of the sar is set (1) automatically, and the next comparison is performed. here, the series resistor string voltage tap is selected according to the value of bit 9 for which the result has already been set, as shown below. bit 9 = 1 ........ av ref = av ref bit 9 = 0 ........ av ref = av ref this voltage tap is compared with the analog input voltage, and bit 8 of the sar is manipulated as follows according to the result: analog input voltage voltage tap: bit 8 = 1 analog input voltage < voltage tap: bit 8 = 0 (f) the same kind of comparison is continued up to the lsb (bit 0) of the sar (binary search method). 1023 2048 1 4 3 4 1535 2048 511 2048 304 chapter 13 a/d converter user s manual u11515ej3v0ud (g) when comparison of the 10 bits is completed, a valid digital result is left in the sar, and that value is transferred to the a/d conversion result register (adcr0 through adcr7) and latched. an a/d conversion operation end interrupt request (intad) can be generated at the same time. figure 13-6. basic operation of a/d converter a/d conversion operations are performed successively until the am0 bit and am1 bit is cleared (0) by software. if a write operation is performed on the adm during an a/d conversion operation, the conversion operation is initialized, and if the am0 bit and am1 bit is set (1), conversion will be started from the beginning. the contents of the adcr n (n = 0 to 7) are undefined after reset input. conversion result conversion result undefined conversion time sampling time a/d converter operation sar adcrn (n = 0 to 7) intad a/d conversion sampling 200h 300h or 100h 305 chapter 13 a/d converter user s manual u11515ej3v0ud (2) input voltage and conversion result the relationship between the analog input voltage input to an analog input pin (ani0 to ani15) and the a/d conversion result (value stored in adcrn) is shown by the following expression: adcrn = int( 1024 + 0.5) or (adcrn 0.5) v in < (adcrn + 0.5) remark int( ) : function that returns the integer part of the value in ( ) v in : analog input voltage av ref : av ref pin voltage adcrn : adcr n (n = 0 to 7) value figure 13-7 shows the relationship between the analog input voltage and the a/d conversion result in graphic form. figure 13-7. relationship between analog input voltage and a/d conversion result v in av ref av ref 1024 av ref 1024 1023 1022 1021 3 2 1 0 input voltage/av ref 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion result (adcrn: n = 0 to 7) 306 chapter 13 a/d converter user s manual u11515ej3v0ud (3) a/d conversion time the a/d conversion time is determined by the system clock frequency (f clk ) and the fr bit of the a/d converter mode register (adm). the a/d conversion time includes the entire time required for one a/d conversion operation, and the sampling time is also included in the a/d conversion time. these values are shown in table 13-2. table 13-2. time of a/d conversion system clock (f clk ) range fr bit conversion time f clk > 12.5 mhz 0 208 clocks f clk 12.5 mhz 1 169 clocks (4) a/d converter operating modes there are two a/d converter operating modes, scan mode and select mode. these modes are selected according to the setting of bit 5 (am0) and bit 6 (am1) of the a/d converter mode register (adm). operation in either mode continues until the adm is rewritten. 307 chapter 13 a/d converter user s manual u11515ej3v0ud 13.4.2 select mode in the select mode, one analog input pin is selected by bits 0 through 2 (anis0 through anis2) of the a/d converter mode select register (adm), and the specified analog input is converted. the result of the conversion is stored to the a/d conversion result register corresponding to the analog input. in this mode, the following two modes can be selected depending on how the a/d conversion result is stored. 1-buffer mode 4-buffer mode (1) 1-buffer mode one analog input is converted once, and the result is stored to one a/d conversion result register. therefore, the analog input and a/d conversion result register correspond on a one-to-one basis (refer to table 13-3 ). each time the conversion has been completed once, an a/d conversion end interrupt request (intad) occurs. table 13-3. correspondence between analog input and a/d conversion result register (select mode: 1-buffer mode) analog input a/d conversion result register ani0/ani8 acdr0 ani1/ani9 adcr1 ani2/ani10 acdr2 ani3/ani11 adcr3 ani4/ani12 acdr4 ani5/ani13 adcr5 ani6/ani14 acdr6 ani7/ani15 adcr7 figure 13-8. operating timing in select mode (1-buffer mode) (1/2) (a) trg bit 0 conversion started conversion ended conversion ended conversion ended conversion ended conversion ended conversion ended ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 am1, am0 10 ps 0 anis2-anis0 011 intad a/d conversion adcr3 308 chapter 13 a/d converter user s manual u11515ej3v0ud figure 13-8. operation timing in select mode (1-buffer mode) (2/2) (b) trg bit 1 (2) 4-buffer mode one analog input is converted four times, and the result is stored to four a/d conversion result registers. when one of the analog inputs of ani0 through ani3 (ani8 through ani11) is selected, the conversion result is stored to a/ d conversion result registers adcr0 through adcr3. if one of the analog inputs of ani4 through ani7 (ani12 through ani15) is selected, the conversion result is stored to the a/d conversion result register adcr4 through adcr7 (refer to table 13-4 ). each time a/d conversion has been completed four times, a/d conversion end interrupt request (intad) is generated. table 13-4. correspondence between analog input and a/d conversion result register (select mode: 4-buffer mode) analog input a/d conversion result register ani0/ani8 adcr0-adcr3 ani1/ani9 ani2/ani10 ani3/ani11 ani4/ani12 adcr4-adcr7 ani5/ani13 ani6/ani14 ani7/ani15 conversion started conversion ended ani0 ani0 ani0 ani0 ani0 ani0 ani0 ani0 ani0 ani0 am1, am0 10 ps 0 anis2-anis0 000 intad a/d conversion adcr0 intp4 conversion ended conversion ended conversion ended conversion ended ani0 initialization initialization initialization 309 chapter 13 a/d converter user s manual u11515ej3v0ud figure 13-9. operation timing in select mode (4-buffer mode) (a) trg bit 0 (b) trg bit 1 13.4.3 scan mode in this mode, analog input pins specified by the anis0 through anis2 bits of the a/d converter mode register (adm) are sequentially selected, starting from ani0 pin, and a/d conversion is executed. the result of the conversion is stored to the a/d conversion result register that corresponds to an analog input on a one-to-one basis (refer to table 13-5 ). when all the analog inputs have been converted, the a/d conversion end interrupt request (intad) is generated. ani3 am1, am0 11 ps 0 anis2-anis0 011 intad a/d conversion adcr0- adcr3 ani3 (adcr0) ani3 ani3 ani3 ani3 ani3 ani3 ani3 conversion ended ani3 (adcr1) ani3 (adcr2) ani3 (adcr3) ani3 (adcr0) ani3 (adcr1) ani3 (adcr2) conversion ended conversion started conversion started ani3 am1, am0 11 ps 0 anis2-anis0 011 intad a/d conversion adcr0- adcr3 intp4 initialization initialization initialization ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 (adcr0) ani3 (adcr0) ani3 (adcr1) ani3 (adcr2) ani3 (adcr3) ani3 (adcr0) conversion ended 310 chapter 13 a/d converter user s manual u11515ej3v0ud table 13-5. correspondence between analog input and a/d conversion result register (scan mode) analog input a/d conversion result register ani0/ani8 adcr0 ani1/ani9 adcr1 ani2/ani10 adcr2 ani3/ani11 adcr3 ani4/ani12 adcr4 ani5/ani13 adcr5 ani6/ani14 adcr6 ani7/ani15 adcr7 figure 13-10. operation timing in scan mode (a) trg bit 0 (b) trg bit 1 ani0 am1, am0 01 ps 0 anis2-anis0 010 intad a/d conversion adcr0- adcr2 ani0 (adcr0) ani1 ani2 ani0 ani1 ani2 ani0 ani1 ani1 (adcr1) ani2 (adcr2) ani0 (adcr0) ani1 (adcr1) ani2 (adcr2) ani0 (adcr0) conversion started conversion ended conversion ended ani0 am1, am0 01 ps 0 anis2-anis0 010 intad a/d conversion adcr0- adcr2 intp4 initialization initialization initialization ani1 ani0 ani1 ani2 ani0 ani1 ani0 ani1 ani0 (adcr0) ani0 (adcr0) ani1 (adcr1) ani2 (adcr2) ani0 (adcr0) ani0 (adcr0) conversion started conversion ended 311 chapter 13 a/d converter user s manual u11515ej3v0ud 13.4.4 a/d conversion operation start by software an a/d conversion operation start by software is performed by writing a value to the a/d converter mode register (adm) that sets the trg bit of the adm register to 0 and the am0 bit or am1 bit to 1. if a value is written to the adm during an a/d conversion operation (am0 bit or am1 bit = 1) such that the trg bit is set to 0 and the am0 bit or am1 bit to 1 again, the a/d conversion operation being performed at that time is suspended, and a/d conversion is started immediately in accordance with the written value. once a/d conversion operation is started, as soon as one a/d conversion operation ends the next a/d conversion operation is started in accordance with the operating mode set by the adm, and conversion operations continue repeatedly until an instruction that writes to the adm is executed. when a/d conversion operation is started by software (trg bit = 0), intp4 pin (p25 pin) input does not affect the a/ d conversion operation. (1) a/d conversion in select mode (1-buffer mode) a/d conversion of the analog input set by the a/d converter mode register (adm) is started. when conversion has been completed, the same analog input is converted again. each time a/d conversion has been completed, the a/d conversion end interrupt request (intad) is generated. figure 13-11. a/d conversion in select mode (1-buffer mode) started by software (2) a/d conversion in select mode (4- buffer mode) the analog input set by the a/d converter mode register (adm) is converted. one analog input is converted four times. when a/d conversion has been executed four times, the same analog input is converted four times again. each time conversion has been executed four times, the a/d conversion end interrupt request (intad) is generated. adm written adm rewritten ani1 trg 0 am1, am0 10 ps 0 anis2-anis0 001 intad a/d conversion adcr1, adcr5 ani1 (adcr1) trg 0 am1, am0 10 ps 0 anis2-anis0 101 ani1 ani1 ani1 ani1 ani1 ani5 ani5 ani5 ani1 (adcr1) ani1 (adcr1) ani1 (adcr1) ani1 (adcr1) ani5 (adcr5) 312 chapter 13 a/d converter user s manual u11515ej3v0ud figure 13-12. a/d conversion in select mode (4-buffer mode) started by software (3) a/d conversion in scan mode when conversion is started, analog inputs selected by the anis0 through anis2 bits of the a/d converter mode register (adm) are sequentially converted, starting from the ani0 pin. when conversion of all the selected analog inputs has been completed, the same operation (conversion from the ani0 pin to the specified analog input pin) is repeated again. when a series of a/d conversion from the ani0 pin to the specified analog input has been completed, the a/d conversion end interrupt request (intad) is generated. figure 13-13. a/d conversion in scan mode started by software adm written adm rewritten ani3 trg 0 am1, am0 11 ps 0 anis2-anis0 011 intad a/d conversion adcr0- adcr7 ani3 (adcr0) trg 0 am1, am0 11 ps 0 anis2-anis0 101 ani3 ani3 ani3 ani3 ani3 ani5 ani5 ani5 ani3 (adcr1) ani3 (adcr2) ani3 (adcr3) ani3 (adcr0) ani5 (adcr4) adm written adm rewritten ani0 trg 0 am1, am0 01 ps 0 anis2-anis0 010 intad a/d conversion adcr0- adcr2 ani0 (adcr0) trg 0 am1, am0 01 ps 0 anis2-anis0 001 ani1 ani2 ani0 ani1 ani0 ani1 ani1 (adcr1) ani2 (adcr2) ani0 (adcr0) ani0 (adcr0) ani1 (adcr1) ani0 ani1 313 chapter 13 a/d converter user s manual u11515ej3v0ud 13.4.5 a/d conversion operation start by hardware an a/d conversion operation start by hardware is made possible by setting both the trg bit and the am0 bit or am1 bit of the a/d converter mode register (adm) to 1. when the trg bit and the am0 bit or am1 bit of the adm are both set to 1, external signals are placed in the standby state, and an a/d conversion operation is started when a valid edge is input to the intp4 pin (p25 pin). if another valid edge is input to the intp4 pin after the a/d conversion operation has been started by a valid edge input to the intp4 pin, the a/d conversion operation being performed at that time is suspended, and a/d conversion is performed from the beginning in accordance with the contents set in the adm. if a value is written to the adm during an a/d conversion operation (am0 bit or am1 = 1) such that the trg bit and am0 bit or am1 bit are both set to 1 again, the a/d conversion operation being performed at that time is suspended (the standby state is also suspended), and a state is entered in which the a/d converter waits for input of a valid edge to the intp4 pin in the a/d conversion operation mode in accordance with the written value, and a conversion operation is started when a valid edge is input. use of this function allows a/d conversion operations to be synchronized with external signals. once a/d conversion operation is started, as soon as one a/d conversion operation ends the next a/d conversion operation is started in accordance with the operating mode set by the adm (the a/d converter does not wait for intp4 pin input), and conversion operations continue repeatedly until an instruction that writes to the adm is executed, or a valid edge is input to the intp4 pin. (1) a/d conversion in select mode (1-buffer mode) a/d conversion of the analog input set by the a/d converter mode register (adm) is started. when conversion has been completed, the same analog input is converted again. each time a/d conversion has been completed, the a/d conversion end interrupt request (intad) is generated. if the valid edge is input to the intp4 pin during a/d conversion, the a/d conversion under execution is stopped once, and then conversion is newly started. figure 13-14. a/d conversion in select mode (1-buffer mode) started by hardware adm written adm rewritten standby state intad a/d conversion adcr1, adcr5 intp4 ani1 (adcr1) ani1 ani1 ani1 ani1 standby state ani5 ani5 ani1 (adcr1) ani5 (adcr5) trg 1 am1, am0 10 ps 0 anis2-anis0 001 trg 1 am1, am0 10 ps 0 anis2-anis0 101 314 chapter 13 a/d converter user s manual u11515ej3v0ud (2) a/d conversion in select mode (4-buffer mode) the analog input set by the a/d converter mode register (adm) is converted. one analog input is converted four times. when a/d conversion has been executed four times, the same analog input is converted four times again. each time conversion has been executed four times, the a/d conversion end interrupt request (intad) is generated. if the valid edge is input to the intp4 pin during a/d conversion, the a/d conversion under execution is stopped once, and then conversion is newly started. figure 13-15. a/d conversion in select mode (4-buffer mode) started by hardware adm written adm rewritten standby state intad a/d conversion adcr0- adcr7 intp4 ani3 (adcr0) trg 1 am1, am0 11 ps 0 anis2-anis0 011 trg 1 am1, am0 11 ps 0 anis2-anis0 101 ani3 (adcr1) ani3 (adcr2) ani3 (adcr3) ani3 (adcr0) ani3 ani3 ani3 ani3 ani3 ani5 ani3 standby state 315 chapter 13 a/d converter user s manual u11515ej3v0ud (3) a/d conversion in scan mode when conversion is started, analog inputs selected by the anis0 through anis2 bits of the a/d converter mode register are sequentially converted, starting from the ani0 pin. when conversion of all the selected analog inputs has been completed, the same operation (conversion from the ani0 pin to the specified analog input pin) is repeated again. when a series of a/d conversion from the ani0 pin to the specified analog input has been completed, the a/d conversion end interrupt request (intad) is generated. if the valid edge is input to the intp4 pin during a/d conversion, the a/d conversion under execution is stopped once, and then conversion is newly started. figure 13-16. a/d conversion in scan mode started by hardware adm written adm rewritten standby state intad a/d conversion adcr0- adcr2 intp4 ani0 (adcr0) trg 1 am1, am0 01 ps 0 anis2-anis0 010 trg 1 am1, am0 01 ps 0 anis2-anis0 001 ani0 ani1 ani2 ani0 ani0 standby state ani0 ani1 ani1 (adcr1) ani2 (adcr2) ani0 (adcr0) 316 chapter 13 a/d converter user s manual u11515ej3v0ud 13.5 external circuit of a/d converter the a/d converter is provided with a sample & hold circuit to stabilize its conversion operation. this sample & hold circuit outputs sampling noise during sampling immediately after an a/d conversion channel has been changed. to absorb this sampling noise, an external capacitor must be connected. if the impedance of the signal source is high, an error may occur in the conversion result due to the sampling noise. especially when the scan mode is used, the impedance of the signal source must be kept low because the channel whose signal is to be converted changes one after another. one way to absorb the sampling noise is to increase the capacitance of the capacitor. however, if the capacitance is increased too much, the sampling noise is accumulated. therefore, the most effective way is to reduce the resistance component. 13.6 cautions (1) range of voltages applied to analog input pins the following must be noted concerning a/d converter analog input pins ani0 to ani15 (p70 to p77, p80 to p87). a voltage outside the range av ss to av ref should not be applied to pins subject to a/d conversion during an a/ d conversion operation. if this restriction is not observed, the pd784046 may be damaged. (2) connecting capacitor to analog input pins a capacitor should be connected between the analog input pins (ani0 to ani15) and av ss and between the reference voltage input pin (av ref ) and av ss to prevent misoperation due to noise. be sure to connect the capacitor as close to ani0 through ani15 and av ref as possible. 317 chapter 13 a/d converter user s manual u11515ej3v0ud figure 13-17. example of capacitor connection on a/d converter pins (3) when the stop mode or idle mode is used, the consumption current should be reduced by clearing (0) the am0 bit and am1 bit before entering the stop or idle mode. if the am0 bit and am1 bit remains set (1), the conversion operation will be stopped by entering the stop or idle mode, but the power supply to the voltage comparator will not be stopped, and therefore the a/d converter consumption current will not be reduced. (4) once the a/d converter starts operating, conversion operations are performed repeatedly until the am0 bit and am1 bit of the a/d converter mode (adm) is cleared (0). therefore, a superfluous interrupt may be generated if adm setting is performed after interrupt-related registers, etc., are set when a/d converter mode conversion, etc., is performed. the result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. it is therefore recommended that a/d converter mode conversion be carried out using the following procedure. <1> write to the adm <2> interrupt request flag (adif) clearance (0) <3> interrupt mask flag setting operations <1> to <3> should not be divided by an interrupt or macro service. alternatively, the following procedure is recommended. <1> stop the a/d conversion operation by clearing (0) the am0 bit and am1 bit of the adm. <2> interrupt request flag (adif) clearance (0). <3> interrupt mask flag setting <4> write to the adm analog input reference voltage input 100 to 500 pf ani0-ani15 av ref av ss pd784046 318 user? manual u11515ej3v0ud chapter 14 asynchronous serial interface/3-wire serial i/o the pd784046 incorporates two serial interface channels for which asynchronous serial interface (uart) mode or 3-wire serial i/o (ioe) mode can be selected. the two uart/ioe channels have completely identical functions. in this chapter, therefore, unless stated otherwise, uart/ioe1 will be described as representative of both uart/ioes. when used as uart2/ioe2, the uart/ioe1 register names, bit names and pin names should be read as their uart2/ioe2 equivalents as shown in table 14-1. table 14-1. differences between uart/ioe1 and uart2/ioe2 names item uart/ioe1 uart2/ioe2 pin names p32/rxd/si1, p33/txd/so1, p35/rxd2/si2, p36/txd2/so2, p34/asck/sck1 p37/asck2/sck2 asynchronous serial interface mode register asim asim2 asynchronous serial interface mode register bit names txe, rxe, ps1, ps0, cl, sl, txe2, rxe2, ps21, ps20, cl2, isrm, sck sl2, isrm2, sck2 asynchronous serial interface status register asis asis2 asynchronous serial interface status register bit names pe, fe, ove pe2, fe2, ove2 clocked serial interface mode register csim1 csim2 clocked serial interface mode register bit names ctxe1, crxe1, dir1, csck1 ctxe2, crxe2, dir2, csck2 baud rate generator control register brgc brgc2 baud rate generator control register bit names tps0-tps3, mdl0-mdl3 tps20-tps23, mdl20-mdl23 interrupt request names intsr/itcsi1, intser, intst intsr2/intcsi2, intser2, intst2 interrupt control registers and bit names used in this sric, csiic1, seric, stic, sric2, csiic2, seric2, stic2, chapter srif, csiif1, serif, stif srif2, csiif2, serif2, stif2 319 chapter 14 asynchronous serial interface/3-wire serial i/o user? manual u11515ej3v0ud 14.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode the asynchronous serial interface mode and 3-wire serial i/o mode cannot be used simultaneously. switching between these modes is performed in accordance with the settings of the asynchronous serial interface mode register (asim/asim2) and the clocked serial interface mode register (csim1/csim2) as shown in figure 14-1. figure 14-1. switching between asynchronous serial interface mode and 3-wire serial i/o mode 7 txe asim 6 rxe 5 ps1 4 ps0 3 cl 2 sl 1 isrm 0 sck txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 sck2 asynchronous serial interface mode operation specification (refer to figure 14-3 ) on reset address address r/w r/w 00h 0ff88h asim2 r/w 00h 0ff89h txe txe2 rxe rxe2 ctxe1 ctxe2 crxe1 crxe2 operating mode setting prohibited other than the above operation-stopped mode 3-wire serial i/o mode asynchronous serial interface mode 0 0 0 0 00 00 0 0 1 1 1 0 0 1 01 10 11 0 0 0 0 0 0 7 ctxe1 csim1 6 crxe1 5 0 4 0 3 0 2 dir1 1 csck1 0 0 ctxe2 crxe2 0 0 0 dir2 csck2 0 on reset r/w r/w 00h 0ff84h csim2 r/w 00h 0ff85h 3-wire serial i/o mode operation specification (refer to figure 14-12 ) 320 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2 asynchronous serial interface mode a uart (universal asynchronous receiver transmitter) mode is incorporated as the asynchronous serial interface. with this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible. a baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates. also, the baud rate can be defined by scaling the clock input to the asck pin. 14.2.1 configuration in asynchronous serial interface mode the block diagram of the asynchronous serial interface is described in figure 14-2. refer to 14.4 baud rate generator for details of the baud rate generator. 321 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-2. block diagram of asynchronous serial interface remark m = 16 to 30, n = 0 to 11 internal bus 1/8 1/8 receive buffer shift register reception control parity check fe fe2 pe pe2 ove ove2 reset asis, asis2 txe txe2 rxe rxe2 ps21 ps0 ps20 cl cl2 sl sl2 isrm isrm2 sck sck2 rxb, rxb2 p32/r x d, p35/r x d2 p33/t x d, p36/t x d2 transmit shift register transmission control parity addition intser, intser2 intst, txs, txs2 intst2 1 m intsr, intsr2 1 m 1 2 n selector p34/asck, p37/asck2 f clk baud rate generator reset asim, asim2 1/8 ps1 322 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud (1) receive buffer (rxb/rxb2) this is the register that holds the receive data. each time one byte of data is received, the receive data is transferred from the shift register. if a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of rxb/rxb2, and the msb of rxb/rxb2 is always 0 . rxb/rxb2 can be read only by an 8-bit manipulation instruction. the contents of rxb/rxb2 are undefined after reset input. (2) transmit shift register (txs/txs2) this is the register in which the data to be transmitted is set. data written to the txs/txs2 is transmitted as serial data. if a 7-bit data length is specified, bits 0 to 6 of the data written in the txs/txs2 are treated as transmit data. a transmit operation starts when a write to the txs/txs2 is performed. the txs/txs2 cannot be written to during a transmit operation. txs/txs2 can be written to only by an 8-bit manipulation instruction. the contents of txs/txs2 are undefined after reset input. (3) shift register this is the shift register that converts the serial data input to the rxd, and rxd2 pin to parallel data. when one byte of data is received, the receive data is transferred to the receive buffer. the shift register cannot be manipulated directly by the cpu. (4) reception control parity check receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode register (asim/asim2). in addition, parity error and other error checks are performed during receive operations, and if an error is detected, a value is set in the asynchronous serial interface status register (asis/asis2) according to the type of error. (5) transmission control parity addition transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the transmit shift registers (txs and txs2) in accordance with the contents set to the asynchronous serial interface mode registers (asim and asim2). (6) selector selects the baud rate clock source. 323 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.2 asynchronous serial interface control registers (1) asynchronous serial interface mode register (asim), asynchronous serial interface mode register 2 (asim2) the asim and asim2 are 8-bit registers that specify the uart mode operation. these registers can be read or written to by an 8-bit manipulation instruction or bit manipulation instruction. the format of asim and asim is shown in figure 14-3. these registers are cleared to 00h by reset input. 324 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-3. formats of asynchronous serial interface mode register (asim) and asynchronous serial interface mode register 2 (asim2) remark f clk : internal system clock txe rxe ps1 ps0 cl sl isrm sck 543210 asim address: 0ff88h, 0ff89h on reset: 00h r/w 0 0 1 1 transmission/reception disables transmission/reception, or sets 3-wire serial i/o mode enables reception enables transmission enables transmission/reception asim2 txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 sck2 0 1 0 1 txe txe2 rxe rxe2 0 0 1 1 specifies parity bit no parity transmission: 0 parity appended reception: parity error does not occur odd parity even parity 0 1 0 1 ps1 ps21 ps0 ps20 0 1 specifies character length of data 7 bits 8 bits cl cl2 0 1 specifies stop bit length (transmission only) 1 bit 2 bits sl sl2 0 1 enables or disables occurrence of reception end interrupt in case of reception error note enables disables isrm isrm2 0 1 specifies input clock to baud rate generator external clock input (asck, asck2) internal clock (f clk ) sck sck2 6 7 325 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud note to disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs until the receive buffers (rxb, rxb2) are read. if the wait time is not inserted, the reception completion interrupt occurs even when it is disabled. the wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be calculated by the following expression: wait time = 2 n+2 f clk remark f clk : internal system clock frequency n : value of baud rate generator control registers (brgc, brgc2) to select tap of 12-bit prescaler (n = 0 to 11) caution an asynchronous serial interface mode register (asim/asim2) rewrite should not be performed during a transmit operation. if an asim/asim2 register rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst/intst2) or the interrupt request flag (stif/stif2) set by intst/intst2. (2) asynchronous serial interface status register (asis), asynchronous serial interface status register 2 (asis2) the asis and asis2 contain flags that indicate the error contents when a receive error occurs. flags are set (1) when a receive error occurs, and cleared (0) when data is read from the receive buffer (rxb/rxb2). if the next data is received before rxb/rxb2 is read, the overrun error flag (ove/ove2) is set (1), and the other error flags are cleared (0) (if there is an error in the next data, the corresponding error flag is set (1)). these registers can be read only by an 8-bit manipulation instruction or bit manipulation instruction. the format of asis and asis2 is shown in figure 14-4. these registers are cleared to 00h by reset input. 326 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-4. formats of asynchronous serial interface status register (asis) and asynchronous serial interface status register 2 (asis2) cautions 1. the receive buffer (rxb/rxb2) must be read even if there is a receive error. if rxb/rxb2 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 2. to disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs until the receive buffers (rxb, rxb2) are read. if the wait time is not inserted, the reception completion interrupt occurs even when it is disabled. the wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be calculated by the following expression: wait time = 2 n+2 f clk remark f clk : internal system clock frequency n : value of baud rate generator control registers (brgc, brgc2) to select tap of 12- bit prescaler (n = 0 to 11) 00000pefeove 76543210 asis address : 0ff8ah, 0ff8bh on reset : 00h r 00000pe2fe2 ove2 0 1 parity error flag parity error does not occur parity error occurs asis2 pe pe2 0 1 framing error flag framing error does not occur framing error occurs fe fe2 0 1 overrun error flag reception overrun error does not occur reception overrun error occurs ove ove2 327 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.3 data format serial data transmission/reception is performed in full-duplex asynchronous mode. the transmit/receive data format is shown in figure 14-5. one data frame is made up of a start bit, character bits, parity bit, and stop bit(s). character bit length specification, parity selection and stop bit length specification for one data frame are performed by means of the asynchronous serial interface mode register (asim). figure 14-5. data format of asynchronous serial interface transmit/receive 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit(s) start bit ................... 1 bit character bits ........ 7 bits/8 bits parity bit ................. even parity/odd parity/0 parity/no parity stop bit(s) ............... 1 bit/2 bits the serial transfer rate is selected in accordance with the asynchronous serial interface mode register and baud rate generator settings. if a serial data receive error occurs, the nature of the receive error can be determined by reading the asynchronous serial interface status register (asis) status. 328 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.4 parity types and operations the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmission side and the reception side. with even parity and odd parity, 1 bit (odd number) errors can be detected. with 0 parity and no parity, errors cannot be detected. even parity if the number of bits with a value of 1 in the transmit data is odd, the parity bit is set to 1 , and if the number of 1 bits is even, the parity bit is set to 0 . control is thus performed to make the number of 1 bits in the transmit data plus the parity bit an even number. in reception, the number of 1 bits in the receive data plus the parity bit is counted, and if this number is odd, a parity error is generated. odd parity conversely to the case of even parity, control is performed to make the number of 1 bits in the transmit data plus the parity bit an odd number. in reception, a parity error is generated if the number of 1 bits in the receive data plus the parity bit is even. 0 parity in transmission, the parity bit is set to 0 irrespective of the receive data. in reception, parity bit detection is not performed. therefore, no parity error is generated irrespective of whether the parity bit is 0 or 1 . no parity in transmission, a parity bit is not added. in reception, reception is performed on the assumption that there is no parity bit. since there is no parity bit, no parity error is generated. 329 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.5 transmission the pd784046 s asynchronous serial interface is set to the transmission enabled state when the txe bit of the asynchronous serial interface mode register (asim) is set (1). a transmit operation is started by writing transmit data to the transmit shift register (txs) when transmission is enabled. the start bit, parity bit and stop bit(s) are added automatica lly. when a transmit operation is started, the data in the txs is shifted out, and a transmission completion interrupt (intst) is generated when the txs is empty. if no more data is written to the txs, the transmit operation is discontinued. if the txe bit is cleared (0) during a transmit operation, the transmit operation is discontinued immediately. figure 14-6. interrupt timing of asynchronous serial interface transmission completion (a) stop bit length: 1 stop parity d0 start txd (output) intst d1 d2 d6 d7 (b) stop bit length: 2 parity d0 start txd (output) intst d1 d2 d6 d7 stop cautions 1. after reset input the transmit shift register (txs) is emptied but a transmission completion interrupt is not generated. a transmit operation can be started by writing transmit data to the txs. 2. an asynchronous serial interface mode register (asim) rewrite should not be performed during a transmit operation. if an asim rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by intst. 330 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.6 reception when the rxe bit of the asynchronous serial interface mode register (asim) is set (1), receive operations are enabled and sampling of the rxd input pin is performed. rxd input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by asim and band rate generator control register (brgc). when the rxd pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal is output on the m'th count. if the rxd pin input is low when sampled again by this start timing signal, the input is recogniz ed as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. when the character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends. when reception of one data frame ends, the receive data in the shift register is transferred to the receive buffer, rxb, and a reception completion interrupt (intsr) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb. if bit 1 (isrm) of the asim was cleared (0) when the error occurred, intsr is generated. if the isrm was set (1), intsr is not generated. if the rxe bit is cleared (0) during a receive operation, the receive operation is stopped immediately. in this case the contents of rxb and asis are not changed, and no intsr or intser interrupt is generated. figure 14-7. interrupt timing of asynchronous serial interface reception completion stop parity d0 start rxd (input) intsr d1 d2 d6 d7 cautions 1. the receive buffer (rxb) must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 2. to disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs until the receive buffers (rxb, rxb2) are read. if the wait time is not inserted, the reception completion interrupt occurs even when it is disabled. the wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be calculated by the following expression: wait time = 2 n+2 f clk remark f clk : internal system clock frequency n : value of baud rate generator control registers (brgc, brgc2) to select tap of 12-bit prescaler (n = 0 to 11) 331 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.7 receive errors three kinds of errors can occur in a receive operation: parity errors, framing errors and overrun errors. as the result of data reception, an error flag is raised in the asynchronous serial interface status register (asis) and a receive error interrupt (intser) is generated. receive error causes are shown in table 14-2. it is possible to detect the occurrence of any of the above errors during reception by reading the contents of the asis (refer to figures 14-4 and 14-8 ). the contents of the asis register are cleared (0) by reading the receive buffer (rxb) or by reception of the next data (if there is an error in the next data, the corresponding error flag is set). table 14-2. causes of receive error receive error cause parity error transmit data parity specification and receive data parity do not match framing error stop bit not detected overrun error reception of next data completed before data is read from receive buffer figure 14-8. timing of receive error note if a receive error occurs while the isrm bit is set (1), intsr is not generated. remark in the pd784046, a break signal cannot be detected by hardware. as a break signal is a low-level signal of two characters or more, a break signal may be judged to have been input if software detects the occurrence of two consecutive framing errors in which the receive data was 00h. the chance occurrence of two consecutive framing errors can be distinguished from a break signal by having the rxd pin level read by software (confirmation is possible by setting 1 in bit 2 of the port 3 mode register (pm3) and reading port 3 (p3)) and confirming that it is 0 . stop parity d0 start rxd (input) intsr note d1 d2 d6 d7 intser 332 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud cautions 1. the contents of the asynchronous serial interface status register (asis) are cleared (0) by reading the receive buffer (rxb) or by reception of the next data. if you want to find the details of an error, therefore, asis must be read before reading rxb. 2. the rxb must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 3. to disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs until the receive buffers (rxb, rxb2) are read. if the wait time is not inserted, the reception completion interrupt occurs even when it is disabled. the wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be calculated by the following expression: wait time = 2 n+2 f clk remark f clk : internal system clock frequency n : value of baud rate generator control registers (brgc, brgc2) to select tap of 12-bit prescaler (n = 0 to 11) 333 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.2.8 transmitting/receiving data with macro service when data is transmitted using a macro service, a vectored interrupt occurs two times. on the other hand, the interrupt occurs only once when data is received using the macro service. transmitting/receiving data by using macro service transmission is started by writing data to the transmit shift register (txs). if this is executed by using a macro service, data is written to txs and transmitted the specified number of times. the transmission end interrupt (intst) that occurs after completion of the transmission performs the macro service processing that writes the next data. when the last data has been written to txs, the macro service is completed (msc = 0), and a vectored interrupt request is generated (refer to <1> in figure 14-9 ). when data transmission is completed after that (when one frame has been transmitted), intst is generated again, and the vectored interrupt request is generated again ( <2> in figure 14-9 ). to start a macro service by intst in this way, therefore, a vectored interrupt is generated two times by the same interrupt request (intst in this case). when reception is executed, however, a vectored interrupt request is not generated two times. because macro service processing that transfers received data to memory is executed by the reception and interrupt (intsr) that occurs after reception has been completed, a vectored interrupt request is generated only once after the macro service has been completed. 334 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-9. transmission/reception with macro service (a) transmission (b) reception main routine ei macro service request (intst) last macro service request (intst) transmission end interrupt (intst) macro service processing macro service processing vectored interrupt processing after end of macro service ... <1> vectored interrupt processing after end of uart transmission ... <2> interrupt request is generated and accepted after end of macro service (msc = 0). main routine ei macro service request (intsr) last macro service request (intsr) macro service processing macro service processing vectored interrupt processing after end of macro service processing interrupt request is generated and accepted after end of macro service (msc = 0). 335 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.3 3-wire serial i/o mode the 3-wire serial i/o mode is used to communicate with devices that incorporate a conventional clocked serial interface. basically, communication is performed using three lines: the serial clock (sck), serial data output (so), and serial data input (si). handshaking lines are required when a number of devices are connected. figure 14-10. example of 3-wire serial i/o system configuration 3-wire serial i/o ? 3-wire serial i/o note handshaking lines 14.3.1 configuration in 3-wire serial i/o mode the block diagram in the 3-wire serial i/o mode is shown in figure 14-11. sck so si port (interrupt) port sck si so port interrupt (port) master cpu note slave cpu 336 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-11. block diagram of 3-wire serial i/o mode internal bus reset 8 dq shift register direction control circuit 8 serial clock counter interrupt signal generator intcsi1, intcsi2 p34/sck1, p37/sck2 serial clock control circuit selector baud rate generator p32/si1, p35/si2 p33/so1, p36/so2 n-ch open-drain output possible csck1, csck2 csck1, csck2 so latch 8 csck2 dir2 crxe2 ctxe2 csck1 dir1 crxe1 ctxe1 csim1, csim2 sio1, sio2 337 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud (1) shift register (sio1/sio2) the sio1 and sio2 converts 8-bit serial data to 8-bit parallel data, and vice versa. sio1/sio2 is used for both transmission and reception. actual transmit/receive operations are controlled by writing to/reading from sio1/sio2. reading/writing can be performed by 8-bit manipulation instruction. the contents of sio1/sio2 are undefined after reset input. (2) so latch the so latch holds the so1/so2 pin output level. (3) serial clock selector selects the serial clock to be used. (4) serial clock counter counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/ reception has been performed. (5) interrupt signal generator generates an interrupt request when 8 serial clocks have been counted by the serial clock counter. (6) serial clock control circuit controls the supply of the serial clock to the shift register, and also controls the clock output to the sck1/sck2 pins when the internal clock is used. (7) direction control circuit switches between msb-first and lsb-first modes. 338 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.3.2 clocked serial interface mode registers (csim1, csim2) the csim1 and csim2 are 8-bit registers that specify operations in the 3-wire serial i/o mode. these registers can be read or written to by an 8-bit manipulation instruction or bit manipulation instruction. the csim1 and csim2 format is shown in figure 14-12. these registers are cleared to 00h by reset input. figure 14-12. formats of clocked serial interface mode register 1 (csim1) and clocked serial interface mode register 2 (csim2) caution even if the dirn (n = 1, 2) bit is changed after writing to the shift register (sion: n = 1, 2), data is output with the setting before change. therefore, set the dirn bit before writing to sion. ctxe1 crxe1 000 dir1 csck1 0 543210 csim1 address : 0ff84h, 0ff85h on reset: 00h r/w ctxe2 crxe2 000 dir2 csck2 0 ctxen 0 0 1 1 transmission/reception disables transmission/reception, or asynchronous serial interface mode enables reception enables transmission enables transmission/reception csim2 crxen 0 1 0 1 dirn 0 1 specifies operation mode (transfer bit sequence) msb first lsb first csckn 0 1 serial clock select bit external input clock to sckn pin baud rate generator output source clock sckn (when ctxen, crxen = 1) input cmos output (n = 1, 2) 6 7 339 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.3.3 basic operation timing in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in msb-first or lsb-first order in synchronization with the serial clock. msb/lsb switching is specified by the dir1 bit of the clock serial interface mode register (csim1). transmit data is output in synchronization with the fall of sck1, and receive data is sampled on the rise of sck1. an interrupt request (intcsi1) is generated on the 8th rise of sck1. when the internal clock is used as sck1, sck1 output is stopped on the 8th rise of sck1 and sck1 remains high until the next data transmit or receive operation is started. 3-wire serial i/o mode timing is shown in figure 14-13. figure 14-13. timing of 3-wire serial i/o mode (1/2) (a) msb-first intcsi1 di7 di6 di5 di4 di3 di2 di1 di0 sck1 note si1 (input) so1 (output) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 transfer end interrupt generation start of transfer synchronized with fall of sck1 master cpu slave cpu execution of instruction that writes to sio1, etc. note : output : input 340 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-13. timing of 3-wire serial i/o mode (2/2) (b) lsb-first remark if the pd784046 is connected to a 2-wire serial i/o device, a buffer should be connected to the so1 pin as shown in figure 14-14. in the example shown in figure 14-14, the output level is inverted by the buffer, and therefore the inverse of the data to be output should be written to sio1. in addition, non-connection of the internal pull-up resistor should be specified for the p33/so1 pin. figure 14-14. example of connection to 2-wire serial i/o intcsi1 di0 di1 di2 di3 di4 di5 di6 di7 sck1 note si1 (input) so1 (output) 12345678 do0 do1 do2 do3 do4 do5 do6 do7 transfer end interrupt generation start of transfer synchronized with fall of sck1 master cpu slave cpu execution of instruction that writes to sio1, etc. : output : input note pd784046 sck1 si1 so1 2-wire serial i/o device sio sck 341 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.3.4 operation when transmission only is enabled a transmit operation is performed when the ctxe1 bit of clocked serial interface mode register (csim1) is set (1). the transmit operation starts when a write to the shift register (sio1) is performed while the ctxe1 bit is set (1). when the ctxe1 bit is cleared (0), the so1 pin is in the output high level. (1) when the internal clock is selected as the serial clock when transmission starts, the serial clock is output from the sck1 pin and data is output in sequence from sio1 to the so1 pin in synchronization with the fall of the serial clock, and si1 pin signals are shifted into sio1 in synchronization with the rise of the serial clock. there is a delay of up to one sck1 clock cycle between the start of transmission and the first fall of sck1. if transmission is disabled during the transmit operation (by clearing (0) the ctxe1 bit), sck1 clock output is stopped and the transmit operation is discontinued on the next rise of sck1. in this case an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. (2) when an external clock is selected as the serial clock when transmission starts, data is output in sequence from sio1 to the so1 pin in synchronization with the fall of the serial clock input to the sck1 pin after the start of transmission, and si1 pin signals are shifted into sio1 in synchronization with the rise of the sck1 pin input. if transmission has not started, shift operations are not performed and the so1 pin output level does not change even if the serial clock is input to the sck1 pin. if transmission is disabled during the transmit operation (by clearing (0) the ctxe1 bit), the transmit operation is discontinued and subsequent sck1 input is ignored. in this case an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. 342 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.3.5 operation when reception only is enabled a receive operation is performed when the crxe1 bit of the clocked serial interface mode register (csim1) is set (1). the receive operation starts when the crxe1 changes from 0 to 1 , or when a read from shift register (sio1) is performed. (1) when the internal clock is selected as the serial clock when reception starts, the serial clock is output from the sck1 pin and the si1 pin data is fetched in sequence into shift register (sio1) in synchronization with the rise of the serial clock. there is a delay of up to one sck1 clock cycle between the start of reception and the first fall of sck1. if reception is disabled during the receive operation (by clearing (0) the crxe1 bit), sck1 clock output is stopped and the receive operation is discontinued on the next rise of sck1. in this case an interrupt request (intcsi1) is not generated, and the contents of the sio1 are undefined. (2) when an external clock is selected as the serial clock when reception starts, the si1 pin data is fetched into shift register (sio1) in synchronization with the rise of the serial clock input to the sck1 pin after the start of reception. if reception has not started, shift operations are not performed even if the serial clock is input to the sck1 pin. if reception is disabled during the receive operation (by clearing (0) the crxe1 bit), the receive operation is discontinued and subsequent sck1 input is ignored. in this case an interrupt request (intcsi1) is not generated. 343 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.3.6 operation when transmission/reception is enabled when the ctxe1 bit and crxe1 bit of the clocked serial interface mode register (csim1) register are both set (1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). the transmit/ receive operation is started when the crxe1 bit is changed from 0 to 1 , or by performing a write to shift register (sio1). when a transmit/receive operation is started for the first time, the crxe1 bit always changes from 0 to 1 , and there is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. the first transmit data should therefore be written to sio1 beforehand when both transmission and reception are disabled (when the ctxe1 bit and crxe1 bit are both cleared (0)), before enabling transmission/reception. when transmission/reception is disabled (ctxe1 = crxe1 = 0), the so1 pin is in the output high level. (1) when the internal clock is selected as the serial clock when transmission/reception starts, the serial clock is output from the sck1 pin, data is output in sequence from shift register (sio1) to the (so1) pin in synchronization with the fall of the serial clock, and si1 pin data is shifted in order into sio1 in synchronization with the rise of the serial clock. there is a delay of up to one sck1 clock cycle between the start of transmission and the first fall of sck1. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the so1 pin becomes output high level. if reception only is disabled, the contents of the sio1 will be undefined. if transmission and reception are disabled simultaneously, sck1 clock output is stopped and the transmit and receive operations are discontinued on the next rise of sck1. when transmission and reception are disabled simultaneously, the contents of sio1 are undefined, an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. (2) when an external clock is selected as the serial clock when transmission/reception starts, data is output in sequence from shift register (sio1) to the so1 pin in synchronization with the fall of the serial clock input to the sck1 pin after the start of transmission/reception, and si1 pin data is shifted in order into sio1 in synchronization with the rise of the serial clock. if transmission/reception has not started, the sio1 shift operations are not performed and the so1 pin output level does not change even if the serial clock is input to the sck1 pin. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the so1 pin becomes output high level. if reception only is disabled, the contents of the sio1 will be undefined. if transmission and reception are disabled simultaneously, the transmit and receive operations are disconti-nued and subsequent sck1 input is ignored. when transmission and reception are disabled simultaneously, the contents of sio1 are undefined, an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. 14.3.7 corrective action in case of slippage of serial clock and shift operations when an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. in this case, since the serial clock counter is initialized by disabling both transmit ope rations and receive operations (by clearing (0) the ctxe1 bit and crxe1 bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock. 344 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.4 baud rate generator the baud rate generator is the circuit that generates the uart/ioe serial clock. two independent circuits are incorporated, one for each serial interface. 14.4.1 baud rate generator configuration the baud rate generator block diagram is shown in figure 14-15. 345 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-15. block diagram of baud rate generator internal bus 8 baud rate generator control register brgc, brgc2 reset asynchronous serial interface mode registers asim, asim2 1/8 sck, sck2 clocked serial interface mode registers csim1, csim2 1/8 csck1, csck2 5-bit counter 5-bit counter reset start bit detection 1/2 uart reception shift clock clear match match 1/2 selector selector selector shift clock for uart transmission & ioe frequency divider selector f prs f clk p34/asck/sck1, p37/asck2/sck2 brgc write csck1, csck2 start bit detection sampling clock reset 346 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud (1) 5-bit counter counter that counts the clock (f prs ) by which the output from the frequency divider is selected. generates a signal with the frequency selected by the low-order 4 bits of the baud rate generator control registers (brgc/brgc2). (2) frequency divider scales the internal clock (f clk ) or, in asynchronous serial interface mode, a clock that is twice the external baud rate input (asck/asck2), and selects f prs with the next-stage selector. (3) both-edge detection circuit detects both edges of the asck/asck2 pin input signal and generates a signal with a frequency twice that of the asck/asck2 input clock. 14.4.2 baud rate generator control register the brgc and brgc2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift clock in 3-wire serial i/o mode. these registers can be read or written to with an 8-bit manipulation instruction. the brgc and brgc2 format is shown in figure 14-16. reset input clears the brgc register to 00h. caution when a baud rate generator control register (brgc, brgc2) write instruction is executed, the 5-bit counter and 1/2 frequency divider operations are reset. consequently, if a write to the brgc and brgc2 is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. the brgc and brgc2 should therefore not be written to during communication. 347 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud figure 14-16. formats of baud rate generator control register (brgc) and baud rate generator control register 2 (brgc2) notes 1. this cannot be selected when k = 15 is selected by mdl3 through mdl0 (mdl23 through mdl20). 2. only f prs /16 can be selected when asck (asck2) input is used. 3. this can be used only in the 3-wire serial i/o mode. remark f asck : asck (asck2) input clock f clk : internal system clock f prs : selected clock of prescaler output tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 76543210 brgc tps23 tps22 tps21 tps20 mdl23 mdl22 mdl21 mdl20 0 0 0 0 0 0 0 0 1 1 1 1 selects prescaler output (f prs ) 0 1 2 3 4 5 6 7 8 9 10 11 brgc2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 tps3 tps23 tps2 tps22 tps1 tps21 tps0 tps20 f clk /2, f asck /2 note 1 f clk /4, f asck /4 f clk /8, f asck /8 f clk /16, f asck /16 f clk /32, f asck /32 f clk /64, f asck /64 f clk /128, f asck /128 f clk /256, f asck /256 f clk /512, f asck /512 f clk /1024, f asck /1024 f clk /2048, f asck /2048 f clk /4096, f asck /4096 n other 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 input clock of baud rate generator note 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mdl3 mdl23 mdl2 mdl22 mdl1 mdl21 mdl0 mdl20 f prs /16 f prs /17 f prs /18 f prs /19 f prs /20 f prs /21 f prs /22 f prs /23 f prs /24 f prs /25 f prs /26 f prs /27 f prs /28 f prs /29 f prs /30 f prs note 3 k address: 0ff90h, 0ff91h on reset: 00h r/w setting prohibited 348 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.4.3 baud rate generator operation the baud rate generator only operates when uart/ioe transmit/receive operations are enabled. the generated baud rate clock is a signal scaled from the internal clock (f clk ) or a signal scaled from the clock input from the external baud rate input (asck) pin. caution if a write to the baud rate generator control register (brgc) is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. the brgc should therefore not be written to during communication. (1) baud rate clock generation in uart mode (a) using internal clock (f clk ) this function is selected by setting (1) bit 0 (sck) of the asynchronous serial interface mode register (asim). the internal clock (f clk ) is scaled by the frequency divider, this signal (f prs ) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the baud rate. the baud rate is given by the following expression: (baud rate) = f clk : internal system clock frequency k : value set in bit mdl3 to bit mdl0 of brgc (k = 0 to 14) n : value set in bit tps3 to bit tps0 of brgc (n = 0 to 11) (b) using external baud rate input this function is selected by clearing (0) bit 0 (sck) of the asynchronous serial interface mode register (asim). when this function is used, bit mdl3 to bit mdl0 of the baud rate generator control register (brgc) must all be cleared (0) (k= 0). set p34 pin (when used with uart2, set p37 pin) in the control mode by using the port 3 mode control register (pmc3). the asck pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by 32 (f prs ) (division by 16 and division by 2) is used as the baud rate. the baud rate is given by the following expression: (baud rate) = f asck n 2 6 + f asck : asck pin input clock frequency n : value set in bit tps3 to bit tps0 of brgc (n = 0 to 11) when this function is used, a number of baud rates can be generated by one external input clock. f clk (k + 16) 2 n + 2 349 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud (3) serial clock generation in 3-wire serial i/o mode selected when the csck1 bit of the clocked serial interface mode register 1 (csim1) is set (1) and sck1 is output. (a) normal mode the internal clock (f clk ) is scaled by the frequency divider, this signal (f prs ) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the serial clock. the serial clock is given by the following expression: (serial clock) = f clk : internal system clock frequency k : value set in bit mdl3 to bit mdl0 of brgc (k = 0 to 14) n : value set in bit tps3 to bit tps0 of brgc (n = 0 to 11) (b) high-speed mode when this function is used, bit mdl3 to bit mdl0 of the baud rate generator control register (brgc) are all set (1) (k= 15). the internal clock (f clk ) is scaled by the frequency divider, and this signal (f prs ) divided by 2 is used as the serial clock. the serial clock is given by the following expression: (serial clock) = f clk : internal system clock frequency n : value set in bit tps3 to bit tps0 of brgc (n = 1 to 11) f clk (k + 16) 2 n + 2 f clk 2 n + 2 350 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.4.4 baud rate setting in asynchronous serial interface mode there are two methods of setting the baud rate, as shown in table 14-3. this table shows the range of baud rates that can be generated, the baud rate calculation expression and selection method for each case. table 14-3. methods of baud rate setting baud rate clock source selection method baud rate calculation baud rate range expression baud rate generator internal system clock sck in asim = 1 _ asck input sck in asim = 0 _ f clk : internal system clock frequency k : value set in bit mdl3 to bit mdl0 of brgc (k = 0 to 14; refer to figure 14-16 ) n : value set in bit tps3 to bit tps0 of brgc (n = 0 to 11; refer to figure 14-16 ) f asck : asck input clock frequency (0 ) note including f asck input range: (0 ) f clk (k + 16) 2 n + 2 f clk 245760 f clk 64 f asck 131072 f asck 64 f asck 2 n+6 note f clk 2 f clk 128 351 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud (1) examples of settings when baud rate generator is used examples of baud rate generator control register (brgc) settings when the baud rate generator is used are shown below. when the baud rate generator is used, the sck bit of the asynchronous serial interface mode register (asim) should be set (1). table 14-4. examples of brgc settings when baud rate generator is used internal system clock 16.0 mhz 12.5 mhz 10.0 mhz 8.0 mhz (f clk ) baud rate brgc baud rate error brgc baud rate error brgc baud rate error brgc baud rate error [bps] value (%) value (%) value (%) value (%) 75 bah 0.16 b4h 1.73 b0h 1.73 aah 0.16 110 b2h 1.36 ach 0.92 a6h 0.88 a2h 1.36 150 aah 0.16 a4h 1.73 a0h 1.73 9ah 0.16 300 9ah 0.16 94h 1.73 90h 1.73 8ah 0.16 600 8ah 0.16 84h 1.73 80h 1.73 7ah 0.16 1200 7ah 0.16 74h 1.73 70h 1.73 6ah 0.16 2400 6ah 0.16 64h 1.73 60h 1.73 5ah 0.16 4800 5ah 0.16 54h 1.73 50h 1.73 4ah 0.16 9600 4ah 0.16 44h 1.73 40h 1.73 3ah 0.16 19200 3ah 0.16 34h 1.73 30h 1.73 2ah 0.16 31520 30h 0.00 29h 0.00 24h 0.00 20h 0.00 38400 2ah 0.16 24h 1.73 20h 1.73 1ah 0.16 76800 1ah 0.16 14h 1.73 10h 1.73 0ah 0.16 352 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud (2) examples of settings when external baud rate input (asck) is used table 14-5 shows an example of setting when external baud rate input (asck) is used. when using the asck input, clear (0) the sck bit of the asynchronous serial interface mode register (asim), and set p34 pin (when used with uart2, set p37 pin) in the control mode by using port 3 mode control register (pmc3). table 14-5. examples of settings when external baud rate input (asck) is used f asck 153.6 khz 4.9152 mhz (asck input frequency) baud rate [bps] brgc value brgc value 75 50h a0h 150 40h 90h 300 30h 80h 600 20h 70h 1200 10h 60h 2400 00h 50h 4800 40h 9600 30h 19200 20h 38400 10h 76800 00h 353 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud 14.5 cautions (1) an asynchronous serial interface mode register (asim) rewrite should not be performed during a transmit operation. if an asim rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by intst. (2) after reset input the transmit shift register (txs) is emptied but a transmission completion interrupt is not generated. a transmit operation can be started by writing transmit data to the txs. (3) the receive buffer (rxb) must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. (4) to disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs until the receive buffers (rxb, rxb2) are read. if the wait time is not inserted, the reception completion interrupt occurs even when it is disabled. the wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be calculated by the following expression: wait time = 2 n+2 f clk remark f clk : internal system clock frequency n : value of baud rate generator control registers (brgc, brgc2) to select tap of 12-bit prescaler (n = 0 to 11) (5) the contents of the asynchronous serial interface status register (asis) are cleared (0) by reading the receive buffer (rxb) or by reception of the next data. if you want to find the details of an error, therefore, asis must be read before reading rxb. (6) in the 3-wire serial i/o mode, even if the dirn (n = 1, 2) bit of the clocked serial interface mode register (csimn: n = 1, 2) is changed after writing to the shift register (sion: n = 1, 2), data is output with the setting before change. therefore, set the dirn bit before writing to sion. (7) the baud rate generator control register (brgc) should not be written to during communication. if a write instruction is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock may be disrupted, preventing normal communication from continuing. 354 chapter 14 asynchronous serial interface/3-wire serial i/o user? manual u11515ej3v0ud (8) the start bit may not be output correctly if the timing at which the shift register shifts data conflicts with a write to the shift register in asynchronous serial interface mode. when writing data to the shift register, restart the baud rate generator to prevent the timing at which the uart shift register shifts data matching the timing of a write to the shift register is performed. at this time, disable acknowledgement of interrupt requests, as shown in the preventive program below, so that the uart transmission enable and the write processing to the shift register can be performed successively. at the same time, disable the activation and operation of the macro service during uart transmission. in addition, set the data to be transmitted next to the shift register after the time of 1/2 the bits of the baud rate has elapsed after the transmission end flag was set. [flowchart of preventive program] note that the relationship between the division ratio of the internal system clock to the oscillation frequency and the baud rate must satisfy the following expressions <1> to <4> when the above preventive program is used. transmission end flag = 1 wait for 1/2 bits of baud rate disable interrupts disable uart transmission (baud rate generator stopped) enable uart transmission (baud rate generator activated) write to the shift register enable interrupts interrupt servicing or transmission end flag check di clr1 txe set1 txe mov txs, #byte ei no yes 355 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud when high-speed fetch is selected (the ifch bit of the memory expansion mode register (mm) is set to 1) and the internal clock is specified as the clock to generate the baud rate clock: (k+15) 2 n+3 > 17 a ..... <1> when high-speed fetch is selected (the ifch bit of the memory expansion mode register (mm) is set to 1) and the clock input from the asck pin is specified as the clock to generate the baud rate clock: 15 2 n+2 /f asck > 17 a/f xx ..... <2> when normal fetch is selected (the ifch bit of the memory expansion mode register (mm) is set to 0) and the internal clock is specified as the clock to generate the baud rate clock: (k+15) 2 n+3 > {3 (3+b+c)+13} a ..... <3> when normal fetch is selected (the ifch bit of the memory expansion mode register (mm) is set to 0) and the clock input from the asck pin is specified as the clock to generate the baud rate clock: 15 2 n+2 /f asck > {3 (3+b+c)+13} a/f xx ..... <4> remark f xx : oscillation frequency or external clock input frequency f asck : frequency of clock input from asck pin a: division ratio of internal clock to oscillation frequency b: access wait value to read/write when external memory is accessed c: address wait value to address output when external memory is accessed k: set value of the mdl3 to mdl0 bits (mdl23 to mdl20) of the brgc (brgc2) register n: set value of the tps3 to tps0 bits (tps23 to tps20) of the brgc (brgc2) register 356 chapter 14 asynchronous serial interface/3-wire serial i/o user? manual u11515ej3v0ud 357 chapter 14 asynchronous serial interface/3-wire serial i/o user? manual u11515ej3v0ud [usage example for expression <3>] for example, assume that when normal fetch is selected and the internal clock is specified as the clock to generate the baud rate clock, no waits are set to the external memory (b = c = 0), and the highest baud rate is set (k = n = 0). under these conditions, the result of expression <3> is as follows. a < 5.45 this example shows that 1/2 or 1/4 of the oscillation frequency can be used for the internal system clock, but not for 1/ 8 or 1/16. [cautions on using preventive program] this bug also occurs if the timing at which the uart shift register shifts data matches a write to the shift register when the uart transmission is performed using a macro service. this bug, however, can be prevented if the following three methods are implemented (these methods eliminate the timing that causes this bug.) activate the macro service immediately after enabling uart transmission (set1 txe). set a longer cycle for the baud rate than the time from a macro service request to its termination. make sure that the macro service for uart transmission is not held pending by another macro service. (when uart transmission is performed using a macro service, disable the processing of other macro service requests with a higher priority.) the execution time from a macro service request to its termination is the sum of a, b, and c in the figure below. a: time for judging the interrupt priority after the interrupt request flag is set it takes 8 system clocks to judge the interrupt priority after the interrupt request flag is set. b: time from when the interrupt request flag is set until the instruction being executed is terminated the macro service is executed when the instruction that was being executed when the interrupt request flag was set is terminated. if the instruction being executed is an instruction to hold the macro service pending temporarily, the macro service is acknowledged when the instruction after instruction is terminated. interrupt request flag macro service instruction ab c 358 chapter 14 asynchronous serial interface/3-wire serial i/o user s manual u11515ej3v0ud [instruction to hold the macro service pending temporarily] ei retcsb !addr16 pop psw di reti popu post brk retb mov pswl,a brkcs location 0h mov pswl,#byte retcs location 0fh movg sp,#imm24 write and bit manipulation instructions for the interrupt control registers, mk0, mk1l, imc, ispr, snm inote 1 bit manipulation instruction of psw note 2 notes 1. except for the bt, bf instructions 2. except for the following instructions bt pswl.bit,$addr20 set1 cy bf pswl.bit,$addr20 not1 cy bt pswh.bit,$addr20 clr1 cy bf pswh.bit,$addr20 c: time for macro service processing the macro service processing time when data is transferred to the sfr is shown below. macro service processing type data area iram other memory to sfr block transfer mode: 24 (1 byte) : blktrs block transfer mode (with memory pointer) 30 32 : blktrs-p unit: clock = 1/f clk remarks 1. add the number of waits (number of clocks) at data access to the above value when using the data area as external memory or internal rom not specified for high-speed fetch (emem16, emem8). 2. iram: internal high-speed ram emem16: memory that is external memory or internal rom not specified for high-speed fetch, and is set to a 16-bit bus width. emem8: memory that is external memory or internal rom not specified for high-speed fetch, and is set to an 8-bit bus width. 359 user? manual u11515ej3v0ud chapter 15 edge detection function p20 to p27 have an edge detection function that allows a rising edge/falling edge to be set programmably, and the detected edge is sent to internal hardware. the relation between pins p20 to p27 and the use of the detected edge is shown in table 15-1. table 15-1. pins p20 to p27 and use of detected edge pin use detected edge specification register p20 nmi, standby circuit control intm0 p21 intp0, cc00 capture signal of timer 0 p22 intp1, cc01 capture signal of timer 0 p23 intp2, cc02 capture signal of timer 0 p24 intp3, cc03 capture signal of timer 0 intm1 p25 intp4, conversion start signal of a/d converter p26 intp5, ti2 (count clock signal of timer/counter 2) p27 intp6, ti3 (count clock signal of timer/counter 3) the edge detection function operates at all times except in stop mode and idle mode (although the edge detection function for pin p20 also operates in stop mode and idle mode). for pins p21 to p27, the noise elimination time when edge detection is performed can be selected by software. 15.1 edge detection function control registers 15.1.1 external interrupt mode registers (intm0, intm1) the intmn (n = 0, 1) specify the valid edge to be detected on pins p20 to p27. the intm0 specifies the valid edge for pins p20 to p23, and the intm1 specifies the valid edge for pins p24 to p27. the intmn can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of intm0 and intm1 are shown in figures 15-1 and 15-2 respectively. reset input clears these registers to 00h. 360 chapter 15 edge detection function user? manual u11515ej3v0ud figure 15-1. format of external interrupt mode register 0 (intm0) es21 es20 es11 es10 es01 es00 0 esnmi 76543210 es21 0 0 1 1 specifies edge to be detected of p23 (intp2, cc02 capture trigger) pin input falling edge rising edge setting prohibited both falling and rising edges intm0 address: 0ff3ch on reset: 00h r/w es20 0 1 0 1 es11 0 0 1 1 specifies edge to be detected of p22 (intp1, cc01 capture trigger) pin input falling edge rising edge setting prohibited both falling and rising edges es10 0 1 0 1 es01 0 0 1 1 specifies edge to be detected of p21 (intp0, cc00 capture trigger) pin input falling edge rising edge setting prohibited both falling and rising edges es00 0 1 0 1 esnmi 0 1 specifies edge to be detected of p20 (nmi) pin input falling edge rising edge 361 chapter 15 edge detection function user s manual u11515ej3v0ud figure 15-2. format of external interrupt mode register 1 (intm1) caution if the valid edge is changed by writing to the external interrupt mode register (intmn: n = 0, 1), the valid edge is not detected. if the edge is input while the valid edge is changed, whether the input edge is judged as the valid edge or not is undefined. es61 es60 es51 es50 es41 es40 es31 es30 76543210 es61 0 0 1 1 specifies edge to be detected of p27 (intp6, ti3) pin input falling edge rising edge setting prohibited both rising and falling edges intm1 address : 0ff3dh on reset : 00h r/w es60 0 1 0 1 es51 0 0 1 1 specifies edge to be detected of p26 (intp5, ti2) pin input falling edge rising edge setting prohibited both rising and falling edges es50 0 1 0 1 es41 0 0 1 1 specifies edge to be detected of p25 (intp4, a/d conversion start trigger) pin input falling edge rising edge setting prohibited both rising and falling edges es40 0 1 0 1 es31 0 0 1 1 specifies edge to be detected of p24 (intp3, cc03 capture trigger) pin input falling edge rising edge setting prohibited both rising and falling edges es30 0 1 0 1 362 chapter 15 edge detection function user s manual u11515ej3v0ud 15.1.2 interrupt valid edge flag registers (ief1, ief2) ief1 and ief2 are flag registers that indicate which of the rising or falling edge is generated when an edge is detected by the inpt0 through intp6 pin. by checking these flag registers, which of the rising or falling edge is generated can be determined if both the rising and falling edges are specified as the valid edge of an interrupt. these registers can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figures 15-3 and 15-4 show the formats of ief1 and ief2. the values of these registers are undefined when reset is input. figure 15-3. format of interrupt valid edge flag register 1 (ief1) iefh3 iefl3 iefh2 iefl2 iefh1 iefl1 iefh0 iefl0 iefhn 0 1 rising edge flag of intpn pin (n = 0 to 3) rising edge is not generated rising edge is generated ief1 address : 0ff3eh on reset : undefined r/w iefln 0 1 falling edge flag of intpn pin (n = 0 to 3) falling edge is not generated falling edge is generated 7654 210 3 363 chapter 15 edge detection function user s manual u11515ej3v0ud figure 15-4. format of interrupt valid edge flag register 2 (ief2) cautions 1. after checking the flag, clear the flag to ??by software. 2. the interrupt valid edge flag register (iefn: n = 1, 2) indicates that an edge has been generated, and has nothing to do with specification of a valid edge. for example, if the valid edge of the intp0 pin is specified to be the rising edge, and if the falling edge is generated, the interrupt request signal is not generated, but the iefl0 flag is set to ?? 3. if the intpn (n = 0 to 6) pin is ??after the reset signal has been deasserted, the rising edge is recognized, and the iefhn (n = 0 to 6) flag is set to ?? even when the iefhn flag is used as a digital port (p21 to p27), it may be set to 1. be sure to clear (0) the iefhn flag before checking the edge of an external interrupt. 0 0 iefh6 iefl6 iefh5 iefl5 iefh4 iefl4 iefhn 0 1 rising edge flag of intpn pin (n = 4 to 6) rising edge is not generated rising edge is generated ief2 address : 0ff3fh on reset : undefined r/w iefln 0 1 falling edge flag of intpn pin (n = 4 to 6) falling edge is not generated falling edge is generated 7654 210 3 364 chapter 15 edge detection function user s manual u11515ej3v0ud 15.1.3 noise protection control register (npc) npc is a register that specifies a sampling clock used to reject the digital noise on the p21/intp0 through p27/intp6/ ti3 pins. this register is read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. figure 15-5 shows the format of npc. the value of this register is cleared to 00h when reset is input. figure 15-5. format of noise protection control register (npc) remark f clk : internal system clock 0 ni6 ni5 ni4 ni3 ni2 ni1 ni0 76543210 nin 0 1 specifies sampling clock to reject noise on intpn pin (n = 0 to 6) f clk f clk /4 npc address : 0ff3bh on reset : undefined r/w pulse width rejected as noise minimum pulse width recognized as signal 3/f clk (0.19 s) 12/f clk (0.75 s) 4/f clk (0.25 s) 16/f clk (1.0 s) (f clk = 16 mhz) ? ? 365 chapter 15 edge detection function user s manual u11515ej3v0ud 15.2 edge detection for pin p20 on pin p20 noise elimination is performed by means of analog delay before edge detection. therefore, an edge cannot be detected unless the pulse width is a given time (10 s) or longer. figure 15-6. edge detection for pin p20 caution since analog delay noise elimination is performed on pin p20, an edge is detected up to 10 s after it is actually input. also, unlike pins p21 to p27, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. p20 input p20 input signal after noise elimination falling edge rising edge short pulse eliminated as noise falling edge detected since pulse is sufficiently wide short pulse eliminated as noise rising edge detected since pulse is sufficiently wide 10 s (min.) 10 s (max.) 10 s (max.) 366 chapter 15 edge detection function user s manual u11515ej3v0ud 15.3 pin edge detection for pins p21 to p27 edge detection for pins p21 to p27 is performed after digital noise elimination by means of clock sampling. the sampling clock is fixed to f clk . in digital noise elimination, input is sampled using the f clk clock, and if the input level is not the same at least four times in succession (if it is the same only three or fewer times in succession), it is eliminated as noise. therefore, the level mus t be maintained for at least 4 f clk clock cycles (0.25 s: f clk = 16 mhz, f clk = 1/2 f xx , f xx = 32 mhz) in order to be recognized as a valid edge. figure 15-7. edge detection for pins p21 to p27 cautions 1. since digital noise elimination is performed with the f clk clock, there is a delay of 4 f clk clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. if the input pulse width is 4 f clk clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 4 clocks. 3. if noise input to a pin is synchronized with the f clk clock in the pd784046, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. pins p21 to p27 f clk p21 to p27 input signal after noise elimination rising edge falling edge digital noise elimination with f clk clock 367 chapter 15 edge detection function user s manual u11515ej3v0ud 15.4 cautions (1) valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (intmn: n = 0, 1). also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge. (2) after checking the flag by using the interrupt valid edge flag register (iefn: n = 1, 2), clear the flag to 0 by software. (3) the interrupt valid edge flag register (iefn: n = 1, 2) indicates that an edge has been generated, and has nothing to do with specification of a valid edge. for example, if the valid edge of the intp0 pin is specified to be the rising edge, and if the falling edge is generated, the interrupt request signal is not generated, but the iefl0 flag is set to 1 . (4) if the intpn (n = 0 to 6) pin is 1 after the reset signal has been deasserted, the rising edge is recognized, and the iefhn (n = 0 to 6) flag of the interrupt valid edge flag register (iefn: n = 1, 2) is set to 1 . even when the iefhn flag is used as a digital port (p21 to p27), it may be set (1). be sure to clear (0) the iefhn flag before checking the edge of an external interrupt. (5) since analog delay noise elimination is performed on pin p20 an edge is detected up to 10 m s after it is actually input. also, unlike pins p21 to p27, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. (6) since digital noise elimination is performed on pins p21 to p27 with the f clk clock, there is a delay of 4 f clk clocks between input of an edge to the pin and the point at which the edge is actually detected. (7) if the input pulse width on pins p21 to p27 is 4 f clk clocks, it is uncertain whether a valid edge will be detected or not. therefore, to ensure reliable operation, the period of at least 4 clocks and the level must be fixed. (8) if noise input to pins p21 to p27 is synchronized with the f clk clock in the pd784046, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. 368 user? manual u11515ej3v0ud chapter 16 interrupt functions the pd784046 is provided with three interrupt request processing modes (refer to table 16-1 ). these three service modes can be set as required in the program. however interrupt processing by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in table 16-2. context switching cannot be selected for non-maskable interrupts or operand error interrupts. multi-processing control using 4 priority levels can easily be performed for maskable vectored interrupts. table 16-1. processing modes of interrupt request interrupt request processing performed pc & psw contents processing processing mode vectored interrupts software saving to & restoration executed by branching to service program at from stack address note specified by vector table context switching saving to & restoration executed by automatic switching to register from fixed area in bank specified by vector table and branching register bank to service program at address note specified by fixed area in register bank macro service hardware retained (however, psw execution of pre-set processing such as data (firmware) is 0x00h in cpu monitor transfers between memory and i/o mode 0) note the start addresses of all interrupt service programs must be in the base area. if the body of a service program cannot be located in the base area, a branch instruction to the service program should be written in the base area. 369 chapter 16 interrupt functions user? manual u11515ej3v0ud 16.1 interrupt request sources the pd784046 has the 29 interrupt request sources shown in table 16-2, with a vector table allocated to each. table 16-2. sources of interrupt request (1/2) interrupt macro type of default interrupt request generating control context macro service vector interrupt priority generating source unit register switching service control table request name word address address software none brk instruction execution not not 3eh possible possible brkcs instruction execution possible not possible operand none invalid operand in mov stbc, not not 3ch error #byte instruction or mov wdm, possible possible #byte instruction, and location instruction non- none nmi (pin input edge detection) edge not not 2h maskable detection possible possible intwdt (watchdog timer watchdog not not 4h overflow) timer possible possible 370 chapter 16 interrupt functions user? manual u11515ej3v0ud table 16-2. sources of interrupt request (2/2) interrupt macro type of default interrupt request generating control context macro service vector interrupt priority generating source unit register switching service control table request name word address address maskable 0 (highest) intov0 (overflow of timer 0) timer 0 ovic0 possible possible 0fe06h 6h 1 intov1 (overflow of timer 1) timer 1 ovic1 0fe08h 8h 2 intov4 (overflow of timer 4) timer 4 ovic4 0fe0ah 0ah 3 intp0 (pin input edge detection) edge detection pic0 0fe0ch 0ch intcc00 (tm0-cc00 match signal generation) timer 0 4 intp1 (pin input edge detection) edge detection p1c1 0fe0eh 0eh intcc01 (tm0-cc01 match signal generation) timer 0 5 intp2 (pin input edge detection) edge detection pic2 0fe10h 10h intcc002 (tm0-cc02 match signal generation) timer 0 6 intp3 (pin input edge detection) edge detection pic3 0fe12h 12h intcc03 (tm0-cc03 match signal generation) timer 0 7 intp4 (pin input edge detection) edge detection pic4 0fe14h 14h 8 intp5 (pin input edge detection) edge detection pic5 0fe16h 16h 9 intp6 (pin input edge detection) edge detection pic6 0fe18h 18h 10 intcm10 (tm1-cm10 match signal generation) timer 1 cmic10 0fe1ah 1ah 11 intcm11 (tm1-cm11 match signal generation) timer 1 cmic11 0fe1ch 1ch 12 intcm20 (tm2-cm20 match signal generation) timer/counter 2 cmic20 0fe1eh 1eh 13 intcm21 (tm2-cm21 match signal generation) timer/counter 2 cmic21 0fe20h 20h 14 intcm30 (tm3-cm30 match signal generation) timer/counter 3 cmic30 0fe22h 22h 15 intcm31 (tm3-cm31 match signal generation) timer/counter 3 cmic31 0fe24h 24h 16 intcm40 (tm4-cm40 match signal generation) timer 4 cmic40 0fe26h 26h 17 intcm41 (tm4-cm41 match signal generation) timer 4 cmic41 0fe28h 28h 18 intser (uart0 reception error) asynchronous seric 0fe2ah 2ah 19 intsr (uart0 reception end) serial interface 0 sric 0fe2ch 2ch intcsi1 (3-wire serial i/o1 transfer end) 3-wire serial i/o1 csiic1 20 intst (uart0 transmission end) asynchronous stic 0fe2eh 2eh serial interface 0 21 intser2 (uart2 reception error) asynchronous seric2 0fe30h 30h 22 intsr2 (uart2 reception end) serial interface 2 sric2 0fe32h 32h intcsi2 (3-wire serial i/o2 transfer end) 3-wire serial i/o2 csiic2 23 intst2 (uart2 transmission end) asynchronous stic2 0fe34h 34h serial interface 2 24 (lowest) intad (a/d conversion end) a/d converter adic 0fe36h 36h remarks 1. th e default priority is a fixed number. this indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously, 2. the intsr and intcsi1 interrupts are generated by the same hardware (they cannot both be used simultaneously). therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. the same applies to intsr2 and intcsi2. 371 chapter 16 interrupt functions user? manual u11515ej3v0ud 16.1.1 software interrupts interrupts by software consist of the brk instruction which generates a vectored interrupt and the brkcs instruction which performs context switching. software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 16.1.2 operand error interrupts these interrupts are generated if there is an illegal operand in an mov stbc, #byte instruction or mov wdm, #byte instruction, and location instruction. operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 16.1.3 non-maskable interrupts a non-maskable interrupt is generated by nmi pin input or the watchdog timer. non-maskable interrupts are acknowledged unconditionally note , even in the interrupt disabled state. they are not subject to interrupt priority control, and are of higher priority that any other interrupt. note except during execution of the service program for the same non-maskable interrupt, and during execution of the service program for a higher-priority non-maskable interrupt 16.1.4 maskable interrupts a maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. in addition, acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the ie flag in the program status word (psw). in addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro service. the priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined (default priority) as shown in table 16-2. also, multi-processing control can be performed with interrupt priorities divided into 4 levels. however, macro service requests are acknowledged without regard to priority control or the ie flag. 372 chapter 16 interrupt functions user? manual u11515ej3v0ud 16.2 interrupt processing modes there are three pd784046 interrupt processing modes, as follows: vectored interrupt processing macro service context switching 16.2.1 vectored interrupt processing when an interrupt is acknowledged, the program counter (pc) and program status word (psw) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt processing routine is executed. 16.2.2 macro service when an interrupt is acknowledged, cpu execution is temporarily suspended and a data transfer is performed by hardware. since macro service is performed without the intermediation of the cpu, it is not necessary to save or restore cpu statuses such as the program counter (pc) and program status word (psw) contents. this is therefore very effective in improving the cpu service time (refer to 16.8 macro service function ). 16.2.3 context switching when an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a pre- set vector address in the register bank, and at the same time the current program counter (pc) and program status word (psw) are saved in the register bank (refer to 16.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation and 16.7.2 context switching ). remark ?ontext?refers to the cpu registers that can be accessed by a program while that program is being executed. these registers include general registers, the program counter (pc), program status word (psw), and stack pointer (sp). 373 chapter 16 interrupt functions user? manual u11515ej3v0ud 16.3 interrupt processing control registers pd784046 interrupt processing is controlled for each interrupt request by various control registers that perform interrupt processing specification. the interrupt control registers are listed in table 16-3. table 16-3. control registers register name symbol function interrupt control registers ovic0, ovic1, ovic4, registers to record generation of interrupt request, control pic0, pic1, pic2, pic3, masking, specify vectored interrupt processing or macro pic4, pic5, pic6, cmic10, service processing, enable or disable context switching cmic11, cmic20, cmic21, function, and specify priority. cmic30, cmic31, cmic40, cmic41, seric, sric, csiic1, stic, seric2, sric2, csiic2, stic2, adic interrupt mask registers mk0 (mk0l, mk0h) control masking of maskable interrupt request. associated mk1 (mk1l, mk1h) with mask control flag in interrupt control register. can be accessed in word or byte units. in-service priority register ispr records priority of interrupt request currently accepted. interrupt mode control register imc controls nesting of maskable interrupt with priority specified to lowest level (level 3). watchdog timer mode register wdm specifies priorities of interrupt by nmi pin input and overflow of watchdog timer. program status word psw enables or disables accepting maskable interrupt. an interrupt control register is allocated to each interrupt source. the flags of each register perform control of the content s corresponding to the relevant bit position in the register. the interrupt control register flag names corresponding to each interrupt request signal are shown in table 16-4. 374 chapter 16 interrupt functions user? manual u11515ej3v0ud table 16-4. interrupt control register flags corresponding to interrupt sources (1/2) default interrupt interrupt control registers priority request interrupt interrupt macro service context switching priority speci- signal request flag mask flag enable flag enable flag fication flag 0 (highest) intov0 ovic0 ovif0 ovmk0 ovism0 ovcse0 ovpr00 ovpr01 1 intov1 ovic1 ovif1 ovmk1 ovism1 ovcse1 ovpr10 ovpr11 2 intov4 ovic4 ovif4 ovmk4 ovism4 ovcse4 ovpr40 ovpr41 3 intp0 pic0 pif0 pmk0 pism0 pcse0 ppr00 intcc00 ppr01 4 intp1 pic1 pif1 pmk1 pism1 pcse1 ppr10 intcc01 ppr11 5 intp2 pic2 pif2 pmk2 pism2 pcse2 ppr20 intcc02 ppr21 6 intp3 pic3 pif3 pmk3 pism3 pcse3 ppr30 intcc03 ppr31 7 intp4 pic4 pif4 pmk4 pism4 pcse4 ppr40 ppr41 8 intp5 pic5 pif5 pmk5 pism5 pcse5 ppr50 ppr51 9 intp6 pic6 pif6 pmk6 pism6 pcse6 ppr60 ppr61 10 intcm10 cmic10 cmif10 cmmk10 cmism10 cmcse10 cmpr100 cmpr101 11 intcm11 cmic11 cmif11 cmmk11 cmism11 cmcse11 cmpr110 cmpr111 12 intcm20 cmic20 cmif20 cmmk20 cmism20 cmcse20 cmpr200 cmpr201 13 intcm21 cmic21 cmif21 cmmk21 cmism21 cmcse21 cmpr210 cmpr211 14 intcm30 cmic30 cmif30 cmmk30 cmism30 cmcse30 cmpr300 cmpr301 15 intcm31 cmic31 cmif31 cmmk31 cmism31 cmcse31 cmpr310 cmpr311 16 intcm40 cmic40 cmif40 cmmk40 cmism40 cmcse40 cmpr400 cmpr401 17 intcm41 cmic41 cmif41 cmmk41 cmism41 cmcse41 cmpr410 cmpr411 18 intser seric serif sermk serism srcse serpr0 serpr1 19 intsr sric srif srmk srism srcse srpr0 srpr1 intcsi1 csiic1 csiif1 csimk1 csiism1 csicse1 csipr10 csipr11 375 chapter 16 interrupt functions user? manual u11515ej3v0ud table 16-4. interrupt control register flags corresponding to interrupt sources (2/2) default interrupt interrupt control registers priority request interrupt interrupt macro service context switching priority speci- signal request flag mask flag enable flag enable flag fication flag 20 intst stic stif stmk stism stcse stpr0 stpr1 21 intser2 seric2 serif2 sermk2 serism2 sercse2 serpr20 serpr21 22 intsr2 sric2 srif2 srmk2 srism2 srcse2 srpr20 srpr21 intcsi2 csiic2 csiif2 csimk2 csiism2 csicse2 csipr20 csipr21 23 intst2 stic2 stif2 stmk2 stism2 stcse2 stpr20 stpr21 24 (lowest) intad adic adif admk adism adcse adpr0 adpr1 16.3.1 interrupt control registers an interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for the corresponding interrupt request. the interrupt control register format is shown in figure 16-1. (1) priority specification flags ( pr1, pr0) the priority specification flags specify the priority on an individual interrupt source basis for the 25 maskable interrupts. up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. among maskable interrupt sources, level 0 is the highest priority. if multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they are acknowledged in default priority order. these flags can be manipulated bit-wise by software. reset input sets all bits to ?? (2) context switching enable flag ( cse) the context switching enable flag specifies that a maskable interrupt request is to be processed by context switching. in context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector address stored beforehand in the register bank, and at the same time the current contents of the program counter (pc) and program status word (psw) are saved in the register bank. context switching is suitable for real-time processing, since execution of interrupt processing can be started faster than with normal vectored interrupt processing. this flag can be manipulated bit-wise by software. reset input sets all bits to ?? 376 chapter 16 interrupt functions user? manual u11515ej3v0ud (3) macro service enable flag ( ism) the macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by vectored interruption or context switching, or by macro service. when macro service processing is selected, at the end of the macro service the macro service enable flag is automatically cleared (0) by hardware (vectored interrupt processing/context switching processing). this flag can be manipulated bit-wise by software. reset input sets all bits to ?? (4) interrupt mask flag ( mk) an interrupt mask flag specifies enabling/disabling of vectored interrupt processing and macro service processing for the interrupt request corresponding to that flag. the interrupt mask flag contents are not changed by the start of interrupt processing, etc., and are the same as the interrupt mask register contents (refer to 16.3.2 interrupt mask registers (mk0, mk1) ). macro service processing requests are also subject to mask control, and macro service requests can also be masked with this flag. this flag can be manipulated by software. reset input sets all bits to ?? (5) interrupt request flag ( if) an interrupt request flag is set (1) by generation of the interrupt request that corresponds to that flag. when the interrupt is acknowledged, the flag is automatically cleared (0) by hardware. this flag can be manipulated by software. reset input sets all bits to ?? 377 chapter 16 interrupt functions user? manual u11515ej3v0ud figure 16-1. interrupt control registers ( icn) (1/4) ovif0 ovmk0 ovism0 ovcse0 00 ovpr01 ovpr00 ovic0 address : 0ffe0h-0ffe6h on reset : 43h r/w ovif1 ovmk1 ovism1 ovcse1 00 ovpr11 ovpr10 ovic1 ovif4 ovmk4 ovism4 ovcse4 00 ovpr41 ovpr40 ovic4 pif0 pmk0 pism0 pcse0 00 ppr01 ppr00 pic0 pic1 pic2 pic3 pif1 pmk1 pism1 pcse1 00 ppr11 ppr10 pif2 pmk2 pism2 pcse2 00 ppr21 ppr20 pif3 pmk3 pism3 pcse3 00 ppr31 ppr30 ifn 0 1 generation of interrupt request no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) mkn 0 1 enables or disables interrupt processing enables interrupt processing disables interrupt processing ismn 0 1 specifies interrupt processing format vectored interrupt processing/context switching processing macro service processing csen 0 1 specifies context switching processing processed by vectored interrupt processed by context switching prn1 0 0 1 1 specifies priority of interrupt request priority 0 (highest priority) priority 1 priority 2 priority 3 prn0 0 1 0 1 7654 210 3 378 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-1. interrupt control registers ( icn) (2/4) address : 0ffe7h-0ffedh on reset : 43h r/w pif4 pmk4 pism4 pcse4 0 0 ppr41 ppr40 pic4 pic5 pic6 cmic10 pif5 pmk5 pism5 pcse5 0 0 ppr51 ppr50 pif6 pmk6 pism6 pcse6 0 0 ppr61 ppr60 cmif10 cmmk10 cmism10 cmcse10 00 cmpr101 cmpr100 cmic11 cmif11 cmmk11 cmism11 cmcse11 00 cmpr111 cmpr110 cmic20 cmif20 cmmk20 cmism20 cmcse20 00 cmpr201 cmpr200 cmic21 cmif21 cmmk21 cmism21 cmcse21 00 cmpr211 cmpr210 ifn 0 1 generation of interrupt request no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) mkn 0 1 enables or disables interrupt processing enables interrupt processing disables interrupt processing ismn 0 1 specifies interrupt processing format vectored interrupt processing/context switching processing macro service processing csen 0 1 specifies context switching processing processed by vectored interrupt processed by context switching prn1 0 0 1 1 specifies priority of interrupt request priority 0 (highest priority) priority 1 priority 2 priority 3 prn0 0 1 0 1 7654 210 3 379 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-1. interrupt control registers ( icn) (3/4) address : 0ffeeh-0fff3h on reset : 43h r/w cmic30 cmif30 cmmk30 cmism30 cmcse30 00 cmpr301 cmpr300 cmic31 cmif31 cmmk31 cmism31 cmcse31 00 cmpr311 cmpr310 cmic40 cmif40 cmmk40 cmism40 cmcse40 00 cmpr401 cmpr400 cmic41 cmif41 cmmk41 cmism41 cmcse41 00 cmpr411 cmpr410 seric serif sermk serism sercse 00 serpr1 serpr0 sric srif srmk srism srcse 0 0 srpr1 srpr0 csiic1 csiif1 csimk1 csiism1 csicse1 00 csipr11 csipr10 ifn 0 1 generation of interrupt request no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) mkn 0 1 enables or disables interrupt processing enables interrupt processing disables interrupt processing ismn 0 1 specifies interrupt processing format vectored interrupt processing/context switching processing macro service processing csen 0 1 specifies context switching processing processed by vectored interrupt processed by context switching prn1 0 0 1 1 specifies priority of interrupt request priority 0 (highest priority) priority 1 priority 2 priority 3 prn0 0 1 0 1 7654 210 3 380 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-1. interrupt control registers ( icn) (4/4) address : 0fff4h-0fff8h on reset : 43h r/w stic stif stmk stism stcse 0 0 stpr1 stpr0 seric2 serif2 sermk2 serism2 sercse2 00 serpr21 serpr20 sric2 srif2 srmk2 srism2 srcse2 00 srpr21 srpr20 csiic2 csiif2 csimk2 csiism2 csicse2 00 csipr21 csipr20 stic2 stif2 stmk2 stism2 stcse2 00 stpr21 stpr20 adic adif admk adism adcse 0 0 adpr1 adpr0 7654 210 3 ifn 0 1 generation of interrupt request no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) mkn 0 1 enables or disables interrupt processing enables interrupt processing disables interrupt processing ismn 0 1 specifies interrupt processing format vectored interrupt processing/context switching processing macro service processing csen 0 1 specifies context switching processing processed by vectored interrupt processed by context switching prn1 0 0 1 1 specifies priority of interrupt request priority 0 (highest priority) priority 1 priority 2 priority 3 prn0 0 1 0 1 381 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.3.2 interrupt mask registers (mk0, mk1) the mk0 and mk1 are composed of interrupt mask flags. mk0 and mk1 are 16-bit registers which can be manipulated as a 16-bit unit. mk0 can be manipulated in 8 bit units using mk0l and mk0h, and similarly mk1 can be manipulated using mk1l and mk1h. in addition, each bit of the mk0 and mk1l can be manipulated individually with a bit manipulation instruction. each interrupt mask flag controls enabling/disabling of the corresponding interrupt request. when an interrupt mask flag is set (1), acknowledgment of the corresponding interrupt request is disabled. when an interrupt mask flag is cleared (0), the corresponding interrupt request can be acknowledged as a vectored interrupt or macro service request. each interrupt mask flag in the mk0 and mk1 is the same flag as the interrupt mask flag in the interrupt control register. the mk0 and mk1 are provided for en bloc control of interrupt masking. after reset input, the mk0 and mk1 are set to ffffh, and all maskable interrupts are disabled. 382 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-2. format of interrupt mask registers (mk0, mk1) 383 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.3.3 in-service priority register (ispr) the ispr shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being processed. when a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (1), and remains set until the service program ends. when a non-maskable interrupt is acknowledged, the bit corresponding to the priority of that non-maskable interrupt is set (1), and remains set until the service program ends. when an reti instruction or retcs instruction is executed, the bit, among those set (1) in the ispr, that corresponds to the highest-priority interrupt request is automatically cleared (0) by hardware. the contents of the ispr are not changed by execution of an retb or retcsb instruction. reset input clears the ispr register to 00h. figure 16-3. format of in-service priority register (ispr) caution the in-service priority register (ispr) is a read-only register. the microcontroller may malfunction if this register is written. nmis wdts 0 0 ispr3 ispr2 ispr1 ispr0 76543210 nmis 0 1 nmi processing status nmi interrupt is not accepted. nmi interrupt is accepted ispr address : 0ffa8h on reset : 00h r wdts 0 1 watchdog timer interrupt processing status watchdog timer interrupt is not accepted. watchdog timer interrupt is accepted. isprn 0 1 priority level (n = 0 to 3) interrupt of priority level n is not accepted. interrupt of priority level n is accepted. 384 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.3.4 interrupt mode control register (imc) the imc contains the prsl flag. the prsl flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. when the imc is manipulated, the interrupt disabled state (di state) should be set first to prevent misoperation. the imc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. reset input sets the imc register to 80h. figure 16-4. format of interrupt mode control register (imc) prsl 0000000 76543210 prsl 0 1 controls nesting of maskable interrupt (lowest level) interrupts with level 3 (lowest level) can be nested. nesting of interrupts with level 3 (lowest level) is disabled. imc address : 0ffaah on reset : 80h r 385 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.3.5 watchdog timer mode register (wdm) the prc bit of the wdm specifies the priority of nmi pin input non-maskable interrupts and watchdog timer overflow non-maskable interrupts. the wdm can be written to only by a dedicated instruction. this dedicated instruction, mov wdm, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements. if the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (mov wdm, a, and wdm, #byte, set1 wdm.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. the wdm can be read at any time by a data transfer instruction. reset input clears the wdm register to 00h. figure 16-5. format of watchdog timer mode register (wdm) caution the watchdog timer mode register (wdm) can be written only by using a dedicated instruction (mov wdm, #byte). run 0 0 prc 0 wdi2 wdi1 0 76543210 run specifies operation of watchdog timer (refer to figure 12-2 ). wdm address : 0ffc2h on reset : 00h r/w prc 0 1 priority of watchdog timer interrupt request watchdog timer interrupt request < nmi pin input interrupt request watchdog timer interrupt request > nmi pin input interrupt request wdi2 specifies count clock of watchdog timer (refer to figure 12-2 ). wdi1 386 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.3.6 program status word (psw) the psw is a register that holds the current status regarding instruction execution results and interrupt requests. the ie flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the psw (pswl). pswl can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (ei/di). when a vectored interrupt is acknowledged or a brk instruction is executed, pswl is saved to the stack and the ie flag is cleared (0). pswl is also saved to the stack by the push psw instruction, and is restored from the stack by the reti, retb and pop psw instructions. when context switching or a brkcs instruction is executed, pswl is saved to a fixed area in the register bank, and the ie flag is cleared (0). pswl is restored from the fixed area in the register bank by an retcsi or retcsb instruction. reset input clears pswl to 00h. figure 16-6. format of program status word (pswl) s z rss ac ie p/v 0 cy 76543210 pswl on reset : 00h s z rss ac used for normal instruction execution ie 0 1 enables or disables accepting interrupt disables enables p/v cy used for normal instruction execution 387 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.4 software interrupt acknowledgment operations a software interrupt is acknowledged in response to execution of a brk or brkcs instruction. software interrupts cannot be disabled. 16.4.1 brk instruction software interrupt acknowledgment operation when a brk instruction is executed, the program status word (psw), program counter (pc) are saved in that order to the stack, the ie flag is cleared (0), the vector table (003eh/003fh) contents are loaded into the low-order 16 bits of the pc, and 0000b into the high-order 4 bits, and a branch is performed (the start of the service program must be in the base area). the retb instruction must be used to return from a brk instruction software interrupt. caution the reti instruction must not be used to return from a brk instruction software interrupt. 16.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation the context switching function can be initiated by executing a brkcs instruction. the register bank to be used after context switching is specified by the brkcs instruction operand. when a brkcs instruction is executed, the program branches to the start address of the interrupt service program (which must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word (psw) and program counter (pc) are saved in the register bank. figure 16-7. context switching operation by execution of a brkcs instruction the retcsb instruction is used to return from a software interrupt due to a brkcs instruction. the retcsb instruction must specify the start address of the interrupt service program for the next time context switching is performed by a brkcs instruction. this interrupt service program start address must be in the base area. caution the retcs instruction must not be used to return from a brkcs instruction software interrupt. register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 3 register bank switching (rbs0-rbs2 n) 4 rss 0 ( ie 0 ) 1 save 2 save (bits 8 to 11 of temporary register) 6 exchange 5 save pc 15-0 pc 19-16 0000b temporary register psw 388 chapter 16 interrupt functions user? manual u11515ej3v0ud figure 16-8. return from brkcs instruction software interrupt (retcsb instruction operation) 16.5 operand error interrupt acknowledgment operation an operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of an mov stbc, #byte instruction or location instruction or an mov wdm,#byte instruction does not match the 4th byte of the operand. operand error interrupts cannot be disabled. when an operand error interrupt is generated, the program status word (psw) and the start address of the instruction that caused the error are saved to the stack, the ie flag is cleared (0), the vector table value is loaded into the program cou nter (pc), and a branch is performed (within the base area only). as the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an retb instruction at the end of the operand error interrupt service program will result in generation of another operand error interrupt. you should therefore either process the address in the stack or initialize the program by referring to 16.12 restoring interrupt function to initial state . pc 19-16 pc 15-0 1 restoration 3 transfer 4 restoration (to original register bank) 2 restoration psw vvp uup te wl retcsb instruction operand register bank n (n = 0 to 7) a r5 r7 d h b x r4 r6 c 389 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.6 non-maskable interrupt acknowledgment operation non-maskable interrupts are acknowledged even in the interrupt disabled state. non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non- maskable interrupt of higher priority. the relative priorities of non-maskable interrupts are set by the prc bit of the watchdog timer mode register (wdm) (refer to 16.3.5 watchdog timer mode register (wdm) ). except in the cases described in 16.9 when interrupt request and macro service are temporarily held pending , a non-maskable interrupt request is acknowledged immediately. when a non-maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (0), the in-service priority register (ispr) bit corresponding to the acknowledged non-maskable interrupt is set (1), the vector table contents are loaded into the pc, and a branch is performed. the ispr bit that is set (1) is the nmis bit in the case of a non-maskable interrupt due to edge input to the nmi pin, and the wdts bit in the case of watchdog timer overflow. when the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable interrupt currently being executed are held pending. a pending non-maskable interrupt is acknowledge after completion of the non-maskable interrupt service program currently being executed (after execution of the reti instruction). however, even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service program. 390 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-9. operations of non-maskable interrupt request acknowledgment (1/2) (a) when a new nmi request is generated during nmi service program execution main routine nmi request nmi request (nmis = 1) nmi request held pending since nmis = 1 pending nmi request is serviced (b) when a watchdog timer interrupt request is generated during nmi service program execution (when the watchdog timer interrupt priority is higher (when prc in the wdm = 1)) main routine nmi request watchdog timer interrupt request 391 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-9. operations of non-maskable interrupt request acknowledgment (2/2) (c) when a watchdog timer interrupt request is generated during nmi service program execution (when the nmi interrupt priority is higher (when prc in the wdm = 0)) main routine nmi request watchdog timer interrupt request watchdog timer interrupt is kept pending because prc = 0 pending watchdog timer interrupt is processed (d) when an nmi request is generated twice during nmi service program execution main routine nmi request nmi request held pending since nmi service program is being executed nmi request held pending since nmi service program is being executed nmi request was generated more than once, but is only acknowledged once 392 chapter 16 interrupt functions user? manual u11515ej3v0ud cautions 1. macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. 2. the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 3. non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 16.9. therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (refer to table 3.6 in 3.9 special function registers (sfrs)), and the cpu becomes deadlocked, or an unexpected signal is output from a pin, or the pc and psw are written to an address in which ram is not mounted, with the result that the return from the non-maskable interrupt processing program is not performed normally and a software upset occurs. therefore, the program following reset release must be as shown below. cseg at 0 dw strt cseg base strt: location 0fh; or location 0h movg sp, #imm24 393 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.7 maskable interrupt acknowledgment operation a maskable interrupt can be acknowledged when the interrupt request flag is set (1) and the mask flag for that interrupt is cleared (0). when processing is performed by macro service, the interrupt is acknowledged and processed by macro service immediately. in the case of vectored interruption and context switching, an interrupt is acknowledged in the interrupt enabled state (when the ie flag is set (1)) if the priority of that interrupt is one for which acknowledgment is permitted. if maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by the priority specification flag is acknowledged. if the interrupts have the same priority specified, they are acknowledged in accordance with their default priorities. a pending interrupt is acknowledged when a state in which it can be acknowledged is established. the interrupt acknowledgment algorithm is shown in figure 16-10. 394 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-10. algorithm of interrupt acknowledgment processing no if = 1 mk = 0 ism = 1 cse = 1 ie = 1 higher priority than interrupt currently being serviced? higher priority than other existing interrupt requests? highest default priority among interrupt requests of same priority? vectored interrupt generation interrupt request? yes no interrupt mask released? yes no yes yes yes yes no no interrupt enabled state? macro service? no no no interrupt request held pending yes context switching? context switching generation yes highest default priority among macro service requests? macro service processing execution interrupt request held pending no yes 395 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.7.1 vectored interrupt when a vectored interrupt maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (0) (the interrupt disabled state is set), and the in - service priority register (ispr) bit corresponding to the priority of the acknowledged interrupt is set (1). also, data in the vector table predetermined for each interrupt request is loaded into the pc, and a branch is performed. the return from a vectored interrupt is performed by means of the reti instruction. caution when a maskable interrupt is acknowledged by vectored interrupt, the reti instruction must be used to return from the interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 16.7.2 context switching initiation of the context switching function is enabled by setting (1) the context switching enable flag of the interrupt contr ol register. when an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified by 3 bits of the lower address (even address) of the corresponding vector table address is selected. the vector address stored beforehand in the selected register bank is transferred to the program counter (pc), and at the same time the contents of the pc and program status word (psw) up to that time are saved in the register bank and a branch is made to the interrupt service program. figure 16-11. context switching operation by generation of an interrupt request register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 6 exchange 4 2 save (temporary register bit 8-11) 5 save 1 save pc 15-0 pc 19-16 0000b temporary register psw n 3 register bank switching (rbs0-rbs2 n) vector table rss 0 ( ie 0 ) 396 chapter 16 interrupt functions user s manual u11515ej3v0ud the retcs instruction is used to return from an interrupt that uses the context switching function. the retcs instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next. this interrupt service program start address must be in the base area. caution the retcs instruction must be used to return from an interrupt serviced by context switching. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. figure 16-12. return from interrupt that uses context switching by means of retcs instruction pc 19-16 pc 15-0 2 restoration 4 restoration (to original register bank) psw retcs instruction operand 3 transfer register bank n (n = 0 to 7) vvp uup tde wh l ax r5 r4 r7 r6 bc 1 restoration 397 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.7.3 maskable interrupt priority levels the pd784046 performs multiple interrupt processing in which an interrupt is acknowledged during processing of another interrupt. multiple interrupts can be controlled by priority levels. there are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag. in priority control by means of default priority, interrupt service is perform ed in accordance with the priority preassigned to each interrupt request (default priority) (refer to table 16-2 ). in programmable priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. interrupt requests for which multiple interruption is permitted are shown in table 16-5. since the ie flag is cleared (0) automatically when an interrupt is acknowledged, when multiple interruption is used, the ie flag should be set (1) to enable interrupts by executing an ei instruction in the interrupt processing program, etc. table 16-5. multiple interrupt processing priority of interrupt currently ispr value ie flag in psw prsl in acknowledgeable maskable interrupts being acknowledged imc register no interrupt being 00000000 0 all macro service only acknowledged 1 all maskable interrupts 3 00001000 0 all macro service only 10 all maskable interrupts 11 all macro service maskable interrupts specified as priority 0/1/2 2 0000 100 0 all macro service only 1 all macro service maskable interrupts specified as priority 0/1 1 0000 10 0 all macro service only 1 all macro service maskable interrupts specified as priority 0 0 0000 1 all macro service only non-maskable interrupts 1000 all macro service only 0100 1100 remark : don t care 398 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-13. examples of processing when another interrupt request is generated during interrupt processing (1/3 ) main routine ei ei ei interrupt request a (level 3) interrupt request b (level 2) interrupt request d (level 2) interrupt request e (level 2) interrupt request f (level 3) interrupt request g (level 1) a processing b processing c processing d processing e processing f processing g processing h processing since interrupt request b has a higher priority than interrupt request a, and interrupts are enabled, interrupt request b is acknowledged. the priority of interrupt request d is higher than that of interrupt request c, but since interrupts are disabled, interrupt request d is held pending. although interrupts are enabled, interrupt request f is held pending since it has a lower priority than interrupt request e. although interrupts are enabled, interrupt request h is held pending since it has the same priority as interrupt request g. interrupt request h (level 1) ei interrupt request c (level 3) 399 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-13. examples of processing when another interrupt request is generated during interrupt processing (2/3 ) main routine ei ei interrupt request i (level 1) interrupt request k (level 2) interrupt request n (level 2) macro service request j (level 2) i processing j macro service k processing l processing m processing n processing o processing p processing the macro service request is serviced irrespective of interrupt enabling/disabling and priority. the interrupt request is held pending since it has a lower priority than interrupt request k. interrupt request m generated after interrupt request l has a higher priority, and is therefore acknowledged first. since processing of interrupt request n performed in the interrupt disabled state, interrupt requests o and p are held pending. after interrupt request n processing, the pending interrupt requests are acknowledged. although interrupt request o was generated first, interrupt request p has a higher priority and is therefore acknowledged first. interrupt request l (level 3) interrupt request m (level 1) interrupt request o (level 3) interrupt request p (level 1) 400 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-13. examples of processing when another interrupt request is generated during interrupt processing (3/3 ) notes 1. low default priority 2. high default priority remarks 1. a to z in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. main routine ei ei ei ei ei ei interrupt request q level 3) interrupt request s (level 1) interrupt request u (level 0) interrupt request v (level 0) w macro service q processing r processing s processing t processing u processing v processing x processing y processing z processing interrupt request x (level 1) interrupt request r (level 2) interrupt request t (level 0) interrupt request y note 1 (level 2) interrupt request w (level 3) multiple acknowledgment of levels 3 to 0. if the prsl bit of the imc is set (1), only macro service requests and non-maskable interrupts generate nesting beyond this. if the prsl bit of the imc is cleared (0), level 3 interrupts can also be nested during level 3 interrupt processing (refer to figure 16-15 ). even though the interrupt enabled state is set during processing of level 0 interrupt request u, the interrupt request is not acknowledged but held pending even though its priority is 0. however, the macro service request is acknowledged and processed irrespective of its level and even though there is a pending interrupt with a higher priority level. pending interrupt requests y and z are acknowledged after servicing of interrupt request x. as interrupt requests y and z have the same priority level, interrupt request z which has the higher default priority is acknowledged first, irrespective of the order in which the interrupt requests were generated. interrupt request z note 2 (level 2) 401 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-14. examples of processing of simultaneously generated interrupts remark a to f in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. main routine ei interrupt request a (level 2) macro service request b (level 3) macro service request c (level 1) interrupt request d (level 1) interrupt request e (level 1) macro service request f (level 1) default priority order a > b > c > d > e > f macro service request b processing macro service request c processing macro service request f processing interrupt request d processing interrupt request e processing interrupt request a processing when requests are generated simultaneously, they are acknowledged in order starting with macro service. macro service requests are acknowledged in default priority order (b/c/f) (not dependent upon the programmable priority order). as interrupt requests are acknowledged in high-to-low priority level order, d and e are acknowledged first. as d and e have the same priority level, the interrupt request with the higher default priority, d, is acknowledged first. 402 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-15. differences in level 3 interrupt acknowledgment according to setting of interrupt mode control register (imc) notes 1. low default priority 2. high default priority remarks 1. a to f in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. main routine ei ei interrupt request a (level 3) interrupt request b (level 3) a processing b processing interrupt request c (level 3) interrupt request d (level 3) c processing d processing interrupt request e note 1 (level 3) interrupt request f note 2 (level 3) f processing e processing imc 80h ei main routine imc 00h ei main routine ei ei the prsl bit of the imc is set to 1, and nesting between level 3 interrupts is disabled. even though interrupts are enabled, interrupt request b is held pending since it has the same priority as interrupt request a. the prsl bit of the imc is set to 0, so that a level 3 interrupt is acknowledged even during level 3 interrupt processing (nesting is possible). since level 3 interrupt request c is being processed in the interrupt enabled state and prsl = 0, interrupt request d, which is also level 3, is acknowledged. as interrupt request 3 and f are both of the same level, the one with the higher default priority, f, is acknowledged first. when the interrupt enabled state is set during processing of interrupt request f, pending interrupt request e is acknowledged since prsl = 0. imc 00h bit 3 (ispr3) of the in-service priority register (ispr) is cleared by returning from processing d. 403 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.8 macro service function 16.8.1 outline of macro service function macro service is one method of processing interrupts. with a normal interrupt, the program counter (pc) and program status word (psw) are saved, and the start address of the interrupt service program is loaded into the pc, but with macro service, different processing (mainly data transfers) is performed instead of this processing. this enables interrupt requests to be responded to quickly, and moreover, since transfer processing is faster than processing by a program, the processing time can also be reduced. also, since a vectored interrupt is generated after processing has been performed the specified number of times, another advantage is that vectored interrupt programs can be simplified. figure 16-16. differences between vectored interrupt and macro service processing notes 1. when register bank switching is used, and an initial value has been set in the register beforehand 2. register bank switching by context switching, saving of pc and psw 3. register bank, pc and psw restoration by context switching 4. pc and psw saved to the stack, vector address loaded into pc 16.8.2 types of macro service macro service can be used with the 25 kinds of interrupt shown in table 16-6 (22 of which can be used simultaneously). there are seven kinds of operation mode, which can be used to suit the application. macro service context switching note 1 vectored interrupt note 1 vectored interrupt interrupt request generation main routine main routine main routine main routine macro service processing main routine note 2 note 4 note 4 note 3 interrupt processing main routine sel rbn interrupt processing restore pc, psw save general registers initialize general registers interrupt processing restore general registers main routine restore pc & psw main routine 404 chapter 16 interrupt functions user s manual u11515ej3v0ud table 16-6. interrupts for which macro service can be used default interrupt request generation source generating unit macro service control priority word address 0 (highest) intov0 (overflow of timer 0) timer 0 0fe06h 1 intov1 (overflow of timer 1) timer 1 0fe08h 2 intov4 (overflow of timer 4) timer 4 0fe0ah 3 intp0 (pin input edge detection) edge detection 0fe0ch intcc00 (tm0-cc00 match signal generation) timer 0 4 intp1 (pin input edge detection) edge detection 0fe0eh intcc01 (tm0-cc01 match signal generation) timer 0 5 intp2 (pin input edge detection) edge detection 0fe10h intcc002 (tm0-cc02 match signal generation) timer 0 6 intp3 (pin input edge detection) edge detection 0fe12h intcc03 (tm0-cc03 match signal generation) timer 0 7 intp4 (pin input edge detection) edge detection 0fe14h 8 intp5 (pin input edge detection) edge detection 0fe16h 9 intp6 (pin input edge detection) edge detection 0fe18h 10 intcm10 (tm1-cm10 match signal generation) timer 1 0fe1ah 11 intcm11 (tm1-cm11 match signal generation) timer 1 0fe1ch 12 intcm20 (tm2-cm20 match signal generation) timer/counter 2 0fe1eh 13 intcm21 (tm2-cm21 match signal generation) timer/counter 2 0fe20h 14 intcm30 (tm3-cm30 match signal generation) timer/counter 3 0fe22h 15 intcm31 (tm3-cm31 match signal generation) timer/counter 3 0fe24h 16 intcm40 (tm4-cm40 match signal generation) timer 4 0fe26h 17 intcm41 (tm4-cm41 match signal generation) timer 4 0fe28h 18 intser (uart0 reception error) asynchronous serial interface 0 0fe2ah 19 intsr (uart0 reception end) 0fe2ch intcsi1 (3-wire serial i/o1 transfer end) 3-wire serial i/o1 20 intst (uart0 transmission end) asynchronous serial interface 0 0fe2eh 21 intser2 (uart2 reception error) asynchronous serial interface 2 0fe30h 22 intsr2 (uart2 reception end) 0fe32h intcsi2 (3-wire serial i/o2 transfer end) 3-wire serial i/o2 23 intst2 (uart2 transmission end) asynchronous serial interface 2 0fe34h 24 (lowest) intad (a/d conversion end) a/d converter 0fe36h remarks 1. the default priority is a fixed number. this indicates the order of priority when macro service requests are generated simultaneously, 2. the intsr and intcsi1 interrupts are generated by the same hardware (they cannot both be used simultaneously). therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. the same applies to intsr2 and intcsi2. 405 chapter 16 interrupt functions user? manual u11515ej3v0ud the macro service operation is performed in the following seven modes: (1) counter mode: evtcnt in this mode, each time an interrupt request has been generated, the macro service counter (msc) is incremented (+1) or decremented (?). when msc reaches 00h, a vectored interrupt request is generated. this mode is used to divide the number of times an interrupt request is generated. (2) block transfer mode: blktrs each time an interrupt request has been generated, 1-byte or 1-word data is transferred between a special function register (sfr) pointed to by the sfr pointer (sfr.ptr) and buffer. when data has been transferred the specified number of times, a vectored interrupt request is generated. the buffer with which data is to be transferred is limited to the addresses 0fd00h through 0feffh note of the main ram. this mode is easy to specify and is used for high-speed transfer of a small amount of data. note when the location 0h instruction is executed. ffd00h through ffeffh when the location 0fh instruction is executed. (3) block transfer mode (with memory pointer): blktrs-p like the block transfer mode, 1-byte or 1-word data is transferred between an sfr specified by sfr.ptr and buffer each time an interrupt request has been generated, and a vectored interrupt request is generated when data has been transferred the specified number of times. the buffer with which data is to be transferred is specified by the memory pointer (mem.ptr) (data can be transferred with the entire 1m-byte memory). this mode is a general-purpose type of the block transfer mode and is used to transfer a large quantity of data. (4) data differential mode: dtadif each time an interrupt request has been generated, the difference between the current value of an sfr specified by sfr.prt and the ?alue immediately before?stored in memory is written to the buffer, and the current value is used as the ?alue immediately before? when data has been transferred the specified number of times, a vectored interrupt request is generated. the buffer with which data is to be transferred is limited to the main ram of the addresses 0fd00h through 0feffh note . this mode is used to measure the cycle of an input pulse, or width of a pulse by using a capture register. note when the location 0h instruction is executed. ffd00h through ffeffh when the location 0fh instruction is executed. (5) data differential mode (with memory pointer): dtadif-p like the data differential mode, each time an interrupt request has been generated, the difference between the current value of an sfr specified by sfr.ptr and the ?alue immediately before?stored in memory is written to the buffer, and the current value is used as the ?alue immediately before? when data has been transferred the specified number of times, a vectored interrupt request is generated. the buffer with which data is to be transferred is specified by the memory pointer (mem.ptr) (the entire 1m-byte memory can be specified). this mode is a general-purpose type of the data differential mode, and is used to transfer a large quantity of data. 406 chapter 16 interrupt functions user s manual u11515ej3v0ud (6) cpu monitor mode 0: self0 each time an interrupt request has been generated, the internal operation of the cpu is checked. if each block operates normally, a value resulting from subtracting 10 from the initial data is transferred to an sfr specified by sfr.ptr. this mode is used for self-check of the cpu at initialization. (7) cpu monitor mode 1: self1 each time an interrupt request has been generated, the internal operation of the cpu is checked. if each block operates normally, a value resulting from subtracting 8 from the initial data is transferred to an sfr specified by sfr.ptr. this mode is used for self-check of the cpu during normal operation. 407 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.8.3 basic operation of macro service (except cpu monitor modes 0 and 1) the macro service function is to transfer data between the special function register area and memory space by hardware, using an interrupt request. when a macro service request is generated, the cpu temporarily stops program execution, and automatically transfers 1/2-byte data between a special function register (sfr) and memory. when data transfer has been completed, an interrupt request flag is reset (0), and the cpu starts program execution again. data is transferred the number of times set to the macro service counter (msc) and then a vectored interrupt request is generated. figure 16-17. example of macro service processing sequence unlike other interrupt processing, processing using the macro service function is automatically performed without starting an interrupt processing program. therefore, operations such as branching to an interrupt service routine, saving/restoring registers, and returning from the interrupt service routine are not performed. this means that the service time of the cpu can be improved and that the number of program steps can be decreased. when macro service processing is executed, the status before execution of the macro service processing, such as the contents of the general-purpose registers and instruction queue of the cpu, are retained. the interrupt request that specifies the macro service processing is not affected by the status of the ie flag in the program status word (pswl). the macro service processing can be executed even in the interrupt disabled status or while an interrupt processing program is executed. it is disabled only when the corresponding bit in the interrupt mask registers (mk0, mk1) is set (1). if two or more macro service requests are issued at the same time, the sequence in which the macro service requests are processed is determined by the default priority. until all the macro service requests are processed, instructions are not executed. the pd784046 supports macro service processing for all the internal interrupt requests. basically, the macro service processing executes the following two operations: data transfer from memory to special function register (sfr) data transfer from special function register (sfr) to memory generation of interrupt request that executes mocro service processing executes macro service processing msc msc 1 ; transfers data, controls real-time output port ; decrements ( _ 1) macro service counter (msc) yes no msc = 0? macro service enable flag 0 interrupt request flag 0 generation of vectored interrupt request execution of next instruction 408 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.8.4 operation on completion of macro servicing (except cpu monitor modes 0 and 1) the macro service performs processing the number of times specified during other program is executed. when the processing has been performed the specified number of times (when the macro service counter (msc) has reached 0), the macro service is completed. figure 16-18. operation on completion of macro service caution if data is transmitted with uart by using the macro service, a vectored interrupt request is generated two times (refer to 14.2.8 transmitting/receiving data with macro service). main routine main routine macro service request last macro service request macro service processing macro service processing interrupt request service on completion of macro service other interrupt processing macro service processing interrupt request processing on completion of macro service other interrupt request ei ei interrupt request is generated and accepted after completion of macro service (msc = 0). if last macro service is executed on completion of macro service while other interrupt processing is under execution, last macro service is kept pending until interrupt request is accepted. last macro service request 409 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.8.5 macro service control register (1) macro service control word the macro service control word consists of a macro service mode register that controls the macro service function, and a macro service channel pointer. it is located in the address space from 0fe06h through 0fe37h note in the main ram area (refer to figure 16-20 ). figure 6-19 shows the basic configuration of the macro service control word. note when the location 0h instruction is executed. ffe06h through ffe37h when the location 0fh instruction is executed. figure 16-19. basic configuration of macro service control word the macro service mode register sets a macro service processing mode, and the macro service channel pointer specifies the address of the macro service channel. to perform macro service processing, a value must be set in advance to the macro service mode register and channel pointer corresponding to the interrupt request that can specify macro service processing. address msb lsb (fe +1)h macro service channel pointer fe h macro service mode register 410 chapter 16 interrupt functions user s manual u11515ej3v0ud figure 16-20. format of macro service control word channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register address adchp admmd stchp2 stmmd2 srchp2/csichp2 srmmd2/csimmd2 serchp2 sermmd2 stchp stmmd srchp/csichp1 srmmd/csimmd1 serchp sermmd cmchp41 cmmmd41 cmchp40 cmmmd40 cmchp31 cmmmd31 cmchp30 cmmmd30 cmchp21 cmmmd21 cmchp20 cmmmd20 cmchp11 cmmmd11 cmchp10 cmmmd10 pchp6 pmmd6 pchp5 pmmd5 pchp4 pmmd4 pchp3 pmmd3 pchp2 pmmd2 pchp1 pmmd1 pchp0 pmmd0 ovchp4 ovmmd4 ovchp1 ovmmd1 ovchp0 ovmmd0 reserved word intad intst2 intsr2/intcsi2 intser2 intst intsr/intcsi1 intser intcm41 intcm40 intcm31 intcm30 intcm21 intcm20 intcm11 intcm10 intp6 intp5 intp4 intp3 intp2 intp1 intp0 intov4 intov1 intov0 cause 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 f e d c b a 9 8 7 6 5 4 3 2 1 0 f e d c b a 9 8 7 6 5 4 3 2 1 0 f e d c b a 9 8 7 6 h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h 411 chapter 16 interrupt functions user s manual u11515ej3v0ud (2) macro service mode register the macro service mode register is an 8-bit register that specifies the operation of the macro service. this register is mapped to the main ram area as a part of the macro service control word (refer to figure 16-19 ) 16.8.6 macro service mode the operation of the macro service is specified by using the macro service mode register. the macro service mode is specified by the low-order 6 bits of the macro service mode register, and is divided into groups 0 to 2. group 0 ... type with only control word and without channel group 1 ... type with both control word and channel group 2 ... macro service for monitoring cpu the high-order 2 bits of the macro service mode register of groups 0 and 1 function as a subcommand (refer to table 16-7 ). 16.8.7 operation of macro service the operation of the macro service is performed in the following seven modes: table 16-7. classification of macro service mode group macro service mode register function group 0 cc000001 counter mode evtcnt group 1 cc010011 block transfer mode blktrs cc010100 block transfer mode (with memory pointer) blktrs-p 10011001 data differential mode dtadif 10011010 data differential mode (with memory pointer) dtadif-p group 2 10101011 cpu monitor mode 0 self0 10001011 cpu monitor mode 1 self1 the most significant bit (msb) c of the macro service mode registers for blktrs and blktrs-p indicates the length of the data to be handled. when c = 0: byte data when c = 1: word data blktrs and blktrs-p are expressed here in terms of byte buffers. when word data is specified, read byte buffer as word buffer. 412 chapter 16 interrupt functions user s manual u11515ej3v0ud (1) counter mode: evcnt [macro service control word] [operation] increments (+1) or decrements ( 1) the macro service counter (msc) each time a macro service has been generated. when the value of msc has reached 00h (overflow), a vectored interrupt request is generated. table 16-8. specifying operation of counter mode cc operation 00 increment 01 decrement 10 setting prohibited 11 in this mode, the macro service function serves as a counter that divides the number of times the interrupt request is generated. example to divide the number of times the intov0 interrupt request has been generated by five by using the macro service [usage] event counter, measurement of number of times of capture msb lsb msc cc000001 high-order address low-order address 05h 01000001 1 0fe07h 0fe06h 413 chapter 16 interrupt functions user s manual u11515ej3v0ud (2) block transfer mode: blktrs [macro service control word] [operation] specifies an sfr pointer (sfr.ptr) by using a channel pointer (ch.ptr). addresses a buffer by using ch.ptr and the macro service counter (msc). data is transferred between the sfr specified by sfr.ptr and buffer, starting from buffer 1. each time transfer has been completed, msc is decremented ( 1). when msc has reached 0, a vectored interrupt request is generated. table 16-9. specifying operation in block transfer mode cc operation transfer data buffer address 00 buffer sfr byte (contents of ch.ptr) (contents of msc) 1 01 sfr buffer 10 buffer sfr word (contents of ch.ptr) (contents of msc 2) 1 11 sfr buffer sfr. ptr msc buffer n buffer 2 buffer 1 ch. ptr cc010011 1 msc = 1 msc = n 1 msc = n msb lsb high-order address low-order address 414 chapter 16 interrupt functions user s manual u11515ej3v0ud example to transfer the contents of port 1 (p1) (0ff01h) to a buffer by using the intov1 interrupt request [usage] data transmission/reception with serial interface 01h 03h buffer 3 buffer 2 buffer 1 51h 00010011 1 0 0 0 0 0 0 0 f f f f f f f e e e e e e e 5 5 4 4 4 0 0 1 0 f e d 9 8 h h h h h h h 415 chapter 16 interrupt functions user s manual u11515ej3v0ud (3) block transfer mode (with memory pointer): blktrs-p [macro service control word] [operation] an sfr pointer (sfr.ptr) is specified by a channel pointer (ch.ptr). data is transferred between an sfr specified by the sfr.ptr and the buffer addressed by the memory pointer (mem.ptr), starting from buffer 1. on completion of transferring byte data, the mem.ptr is incremented (+1). on completion of transferring word data, the mem.ptr is incremented (+2). each time transfer has been completed, the macro service counter (msc) is decremented ( 1). when msc = 0, a vectored interrupt request is generated. table 16-10. specifying operation in block transfer mode (with memory pointer) cc operation transfer data 00 buffer sfr byte 01 sfr buffer 10 buffer sfr word 11 sfr buffer sfr. ptr msc mem. ptr ch. ptr cc010100 msb lsb high-order address low-order address buffer n buffer 2 buffer 1 msc = 1 msc = n 1 msc = n 416 chapter 16 interrupt functions user s manual u11515ej3v0ud example to transfer the contents of the serial receive buffer: uart0 (rxb) (0ff8ch) to a buffer by using the intsr interrupt request [usage] data transmission/reception with serial interface 8ch 03h 00h fch 80h 50h 00010100 1 +1 buffer 3 buffer 2 buffer 1 rxb 2nd time 1st time 3rd time 0 0 0 0 0 0 0 f f f f f f f e e e e e e e 5 4 4 4 4 2 2 0 f e d c d c h h h h h h h 0 0 0 f f f c c c 8 8 8 2 1 0 h h h 417 chapter 16 interrupt functions user s manual u11515ej3v0ud (4) data differential mode: dtadif [macro service control word] [operation] an sfr pointer (sfr.ptr) is specified by a channel pointer (ch.ptr), and a buffer is addressed by the ch.ptr and macro service counter (msc). the difference between the current value of the sfr (including capture registers) specified by the sfr.ptr and the value immediately before is written to the buffer. this current value of the sfr is used as the value immediately before . writing data is started from buffer 1. each time data has been written, the msc is decremented ( 1). when msc = 0, a vectored interrupt request is generated. the buffer address is determined as follows: (buffer address) = (contents of ch.ptr) (contents of msc 2) 3 sfr. ptr msc 1 msb lsb high-order address low-order address ch. ptr 10011001 buffer n buffer 2 buffer 1 msc = 1 msc = n _ 1 msc = n value immediately before 418 chapter 16 interrupt functions user s manual u11515ej3v0ud example to write the difference between the capture/compare register 00 (cc00) (0ff12h) and the value immediately before) to the buffer by using the intp0 input signal as a trigger. the cycle of the intp0 input signal is measured by using the difference in the vectored interrupt processing routine. [usage] to measure cycles and pulse widths by using a capture register cautions 1. do not clear the macro service counter (msc) to 00h. 2. initialize the value immediately before (with dummy data) in advance. 3. only a 16-bit sfr can be specified by the sfr pointer (sfr.ptr). 12h 03h 00h 00h 1 61h 10011001 buffer 3 buffer 2 buffer 1 0 0 0 0 0 0 0 0 0 0 0 0 f f f f f f f f f f f f e e e e e e e e e e e e 6 6 5 5 5 5 5 5 5 5 0 0 1 0 f e d c b a 9 8 d c h h h h h h h h h h h h 419 chapter 16 interrupt functions user s manual u11515ej3v0ud (5) data differential mode (with memory pointer): dtadif-p [macro service control word] [operation] an sfr pointer (sfr.ptr) is specified by a channel pointer (ch.ptr), and a buffer is addressed by the memory pointer (mem.ptr) and macro service counter (msc). the difference between the current value of the sfr (including capture registers) specified by the sfr.ptr and the value immediately before is written to the buffer. this current value of the sfr is used as the value immediately before . writing data is started from buffer 1. each time data has been written, the msc is decremented ( 1). when msc = 0, a vectored interrupt request is generated. the mem.ptr is not affected. the buffer address is determined as follows: (buffer address) = (contents of mem.ptr) (contents of msc 2) + 2 sfr. ptr msc mem. ptr msb lsb high-order address low-order address ch. ptr 10011010 buffer n buffer 2 buffer 1 msc = 1 msc = n 1 msc = n value immediately before 420 chapter 16 interrupt functions user s manual u11515ej3v0ud example to write the difference between the capture/compare register 00 (cc00) (0ff12h) and the value immediately before to the buffer by using the intp0 input signal as a trigger. the cycle of the intp0 input signal is measured by using the difference in the vectored interrupt routine. [usage] to measure cycles and pulse widths by using a capture register cautions 1. do not clear the macro service counter (msc) to 00h. 2. initialize the value immediately before (with dummy data) in advance. 3. only a 16-bit sfr can be specified by the sfr pointer (sfr.ptr). 1 12h 03h 00h 00h 00h fch 80h 61h 10011010 buffer 3 buffer 2 buffer 1 0 0 0 0 0 0 0 f f f f f f f e e e e e e e 6 6 5 5 5 5 5 1 0 f e d c b h h h h h h h 0 0 f f e e 0 0 d c h h 0 0 0 0 0 0 f f f f f f c c c c c c 8 8 7 7 7 7 1 0 f e d c h h h h h h 421 chapter 16 interrupt functions user s manual u11515ej3v0ud (6) cpu monitor mode 0: self0 [macro service control word] [operation] checks the internal operation of the cpu. the items to be checked are as follows: writing to program status word (psw) stack pointer (sp) main ram main ram addressing compare operation if the cpu is operating normally, the value resulting from subtracting 10 from the initial data is transferred to an sfr specified by the sfr pointer (sfr.ptr). if an abnormality of the cpu is detected, a value different from that transferred during normal operation is transferred. after completion of this macro service, the contents of the main ram and the value of sp are not destroyed, but the value of psw is set to 0x00h. therefore, this macro service must be executed when initialization is performed. after that, use cpu monitor mode 1 to be explained next. msb lsb high-order address low-order address ch. ptr 10101011 initial data sfr. ptr 422 chapter 16 interrupt functions user s manual u11515ej3v0ud (7) cpu monitor mode 1: self1 [macro service control word] [operation] checks the internal operation of the cpu. the items to be checked are as follows: stack pointer (sp) main ram main ram addressing compare operation if the cpu is operating normally, the value resulting from subtracting 8 from the initial data is transferred to an sfr specified by the sfr pointer (sfr.ptr). if an abnormality of the cpu is detected, a value different from that transferred during normal operation is transferred. after completion of this macro service, the contents of the main ram and the value of sp are not destroyed. msb lsb high-order address low-order address ch. ptr 10001011 initial data sfr. ptr 423 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.9 when interrupt request and macro service are temporarily held pending when the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for 8 system clock cycles. however, software interrupts are not deferred. ei di brk brkcs retcs retcsb !addr16 reti retb location 0h or location 0fh pop psw popu post mov pswl, a mov pswl, #byte movg sp, #imm24 write instruction and bit manipulation instruction to an interrupt control register note , or the mk0, mk1l, imc or ispr register (excluding bt and bf instructions) psw bit manipulation instruction (excluding the bt pswl. bit, $addr20, bf pswl. bit, $addr20, bt pswh. bit, $addr20, bf pswh. bit, $addr20, set1 cy, not1 cy, and clr1 cy instructions) note interrupt control registers: ovic0, ovic1, ovic4, pic0-pic6, cmic10, cmic11, cmic20, cmic21, cmic30, cmic31, cmic40, cmic41, seric, sric, csiic1, stic, seric2, sric2, csiic2, stic2, adic 424 chapter 16 interrupt functions user s manual u11515ej3v0ud cautions 1. when an interrupt related register is polled using a bf instruction, etc., the branch destination of that br instruction, etc., should not be that instruction. if a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. bad example loop : bf pic0.7, $loop all interrupts and macro service requests are held pending until pic0.7 is 1. interrupts and macro service requests are not serviced until after execution of the instruction following the bf instruction. good example (1) loop : nop bf pic0.7, $loop interrupts and macro service requests are serviced after execution of the nop instruction, so that interrupts are never held pending for a long period. good example (2) loop : bt pic0.7, $next using a btclr instruction instead of a bt instruction has the advantage that the flag is cleared (0) automatically. br $loop interrupts and macro service requests are serviced after next: execution of the br instruction, so that interrupts are never held pending for a long period. 2. for a similar reason, if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. . . . . . . . . . . . . . . . . . . 425 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.10 instructions whose execution is temporarily suspended by an interrupt or macro service execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. the suspended instruction is resumed after completion of the interrupt service program or macro service processing. temporarily suspended instructions: movm, xchm, movbk, xchbk cmpme, cmpmne, cmpmc, cmpmnc cmpbke, cmpbkne, cmpbkc, cmpbknc sacw 16.11 interrupt and macro service operation timing interrupt requests are generated by hardware. the generated interrupt request sets (1) an interrupt request flag. when the interrupt request flag is set (1), a time of 8 clocks (0.5 s: f clk = 16 mhz) is taken to determine the priority, etc. following this, if acknowledgment of that interrupt or macro service is enabled, interrupt request acknowledgment processing is performed when the instruction being executed ends. if the instruction being executed is one which temporarily defers interrupts and macro service, the interrupt request is acknowledged after the following instruction (refer to 16.9 when interrupt request and macro service are temporarily held pending for deferred instructions). figure 16-21. interrupt request generation and acknowledgment (unit: clocks) interrupt request flag 8 clocks instruction interrupt request acknowledgment processing/macro service processing 426 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.11.1 interrupt acceptance processing time to accept an interrupt, the time shown in table 16-11 is required. after this time has elapsed, the interrupt processing routine is executed. table 16-11. interrupt acceptance processing time (unit: clock) interrupt processing mode vectored interrupt context vector table irom, emem16 emem8 switching branch detection stack iram pram emem16 emem8 iram pram emem16 emem8 irom, pram 26 30 30+2n 38+4n 30 34 34+2n 42+4n 22 emem16, emem8 27 31 31+2n 39+4n 31 35 35+2n 43+4n 23 remarks 1. irom : internal rom (with high-speed fetch specified) iram : internal high-speed ram pram : peripheral ram (only when the location 0h instruction is executed in the case of branch destination) emem16 : external memory and internal rom not specified for high-speed fetch and set to 16-bit bus width emem8 : external memory and internal rom not specified for high-speed fetch and set to 8-bit bus width 2. n indicates the number of wait states per byte necessary for writing to the stack. 3. if the vector table is emem16 or emem8 and if wait states are inserted when reading the vector table, the processing time is extended. add 2m in the case of vector interrupt with emem8 or m in the case of context switching with emem16 to the values in the above table. m is the number of wait states per byte necessary for reading the vector table. 4. if the branch destination is emem16 or emem8, and if wait states are inserted when reading the instruction at the branch destination, add the number of wait states to the value in the above table. 5. if the stack is in pram and the value of the stack pointer (sp) is odd, add 8 to the value in the above table. if the value of sp is odd with emem16, add 8+2n to the value in the above table. 6. the number of wait states is the total number of address wait and access wait states. 427 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.11.2 processing time of macro service the processing time of the macro service differs depending on the type of the macro service, as shown in table 16-12. table 16-12. macro service processing time (unit: clock) type of macro service processing time iram other data area group 0 counter mode: evtcnt 18 group 1 block transfer mode: blktrs buffer sfr byte 24 word 25 sfr buffer byte 24 word 25 block transfer mode buffer sfr byte 30 32 (with memory pointer): blktrs-p word 31 33 sfr buffer byte 30 32 word 31 33 data differential mode: dtadif 28 data differential mode (with memory pointer): dtadif-p 33 35 group 2 cpu monitor mode 0: self0 78 cpu monitor mode 1: self1 60 remarks 1. add the number of clocks specified for each case in the following cases in the other data areas. if data size is word and data is located at an odd address in irom or pram: 8 clocks if data size is byte in emem16 or emem8, or if data size is word in emem16 and data is located at an even address: n (n is the number of wait states per byte) if data size is word in emem8, or if data size is word in emem16 and data is located at an odd address: 4 + 2n (n is the number of wait states per byte) 2. data is output to an sfr in the cpu monitor modes. 3. iram : internal high-speed ram irom : internal rom (with high-speed fetch specified) pram : peripheral ram emem16 : external memory and internal rom not specified for high-speed fetch and set to 16- bit bus width emem8 : external memory and internal rom not specified for high-speed fetch and set to 8- bit bus width 428 chapter 16 interrupt functions user s manual u11515ej3v0ud 16.12 restoring interrupt function to initial state if an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, nmi pin input, etc., the entire system must be restored to its initial state. in the pd784046, interrupt acknowledgment related priority control is performed by hardware. this interrupt acknowledgment related hardware must also be restored to its initial state, otherwise subsequent interrupt acknow-ledgment control may not be performed normally. a method of initializing interrupt acknowledgment related hardware in the program is shown below. the only way of performing initialization by hardware is by reset input. example movw mk0, #0ffffh ; mask all maskable interrupts mov mk1, #0ffffh iresl : cmp ispr, #0 ; no interrupt service programs running? bz $next movg sp, #retval ; forcibly change sp location reti ; forcibly terminate running interrupt service program, return address = iresl retval : dw loww (iresl) ; stack data to return to iresl with reti instruction db 0 db highw (iresl) ; loww & highw are assembler operators for calculating low-order 16 bits & high-order 16 bits respectively of symbol next next : it is necessary to ensure that a non-maskable interrupt request is not generated via the nmi pin during execution of this program. after this, on-chip peripheral hardware initialization and interrupt control register initialization are performed. when interrupt control register initialization is performed, the interrupt request flags must be cleared (0). 429 chapter 16 interrupt functions user? manual u11515ej3v0ud 16.13 cautions (1) the in-service priority register (ispr) is read-only. writing to this register may result in misoperation. (2) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm/#byte). (3) the reti instruction must not be used to return from a software interrupt caused by a brk instruction. (4) the retcs instruction must not be used to return from a software interrupt caused by a brkcs instruction. (5) macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. (6) the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. (7) non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execu- tion (except when a high non-maskable interrupt request is generated during execution of a low-priority non- maskable interrupt service program) and for a certain period after execution of the special instructions shown in 16.9. therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (refer to table 3-6 in 3.9 special function registers (sfr) ), and the cpu becomes deadlocked, or the pc and psw are written to an unexpected signal is output from a pin, or an address is which ram is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a software upsets occurs. therefore, the program following reset release must be as follows. cseg at 0 dw strt cseg base strt: location 0fh; or location 0h movg sp, #imm24 (8) when a maskable interrupt is acknowledged by vectored interruption, the reti instruction must be used to return from the interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (9) the retcs instruction must be used to return from a context switching interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (10) if data is transmitted with uart by using the macro service, a vectored interrupt is generated two times (refer to 14.2.8 transmitting/receiving data with macro service ). 430 chapter 16 interrupt functions user s manual u11515ej3v0ud (11) do not clear the macro service counter (msc) to 00h in the data differential mode and data differential mode (with memory pointer). (12) initialize the value immediately before (with dummy data) in advance in the data differential mode and data differential mode (with memory pointer). (13) only a 16-bit sfr can be specified by the sfr pointer (sfr.ptr) in the data differential mode and data differential mode (with memory pointer). (14) when an interrupt related register is polled using a bf instruction, etc., the branch destination of that br instruction, etc., should not be that instruction. if a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. bad example loop: bf pic0.7, $loop all interrupts and macro service requests are held pending until pic0.7 is 1. interrupts and macro service requests are not processed until after exe- cution of the instruction following the bf instruction. good example (1) loop: nop bf pic0.7, $loop interrupts and macro service requests are serviced after execution of the nop instruction, so that interrupts are never held pending for a long period. good example (2) loop: bt pic0.7, $next using a btclr instruction instead of a bt instruction has the advantage that the flag is cleared (0) automatically. br $loop interrupts and macro service requests are serviced after execution of the br instruction, so that interrupts are never held pending for a long period. next: (15) for a similar reason to that given in (14), if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. . . . . . . . . . . . . . . . . . . 431 user? manual u11515ej3v0ud chapter 17 local bus interface function the local bus interface function is provided for the connection of external memory (rom and ram) and i/os. external memory (rom and ram) and i/os are accessed using the rd, lwr, hwr and astb pin signals, with pins ad0 to ad15 used as the multiplexed address/data bus and pins a16 to a19 as the address bus. the basic bus interface timing is shown in figures 17-4 to 17-9. in addition, a wait function that is used to interface with a low-speed memory, and a bus sizing function that can change the external data bus width between 8 bits and 16 bits are also provided. 17.1 memory extension function with the pd784046, external memory and i/o extension can be performed by setting the memory extension mode register (mm). 17.1.1 memory extension mode register (mm) the mm is an 8-bit register that performs external extension memory control, address wait number specification, and internal fetch cycle control. the mm register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the mm format is shown in figure 17-1. reset input sets the mm register to 20h. 432 chapter 17 local bus interface function user? manual u11515ej3v0ud figure 17-1. format of memory expansion mode register (mm) notes 1. setting prohibited when external 16-bit bus is specified. 2. used as an address bus. ifch 0 aw 0 mm3 mm2 mm1 mm0 76543210 ifch 0 1 fetches internal rom fetches at same speed as external memory. all setting of wait control is valid. high-speed fetch. specification of wait control is invalid. mm address : 0ffc4h on reset : 20h r/w aw 0 1 specifies address wait disabled enabled mm3 0 0 0 0 0 0 1 1 mode single-chip mode 256-byte extension mode note 1 1k-byte extension mode note 1 4k-byte extension mode note 1 16k-byte extension mode note 1 64k-byte extension mode 256k-byte extension mode 1m-byte extension mode setting prohibited mm2 0 0 1 1 1 1 0 0 mm1 0 1 0 0 1 1 0 0 mm0 0 1 0 1 0 1 0 1 port 4 (p40 to p47) port 5 (p50 to p57) port 6 (p60 to p63) p90-p93 port ad0-ad7 ad8, ad9 note2 ad8- ad11 note2 ad8- ad13 note2 ad8-ad15 port port port a16, a17 a16-a19 port p90 : rd p91 : lwr p92 : hwr p93 : astb other 433 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.1.2 memory map with external memory extension the memory map when memory extension is used is shown in figures 17-2 to 17-3. external devices at the same addresses as the internal rom area, internal ram area and sfr area (excluding the external sfr area (0ffd0h to 0ffdfh)) cannot be accessed. if an access is made to these addresses, the memory or sfr in the pd784046 has access priority and no astb signal, rd signal, lwr, or hwr signal is output (these pins remain at the inactive level). the address bus output level remains at the level output prior to this, and the address/data bus output becomes high-impedance. except in 1m-byte extension mode, the address output externally is output with the upper part of the address specified by the program masked. example 1: in 256-byte extension mode, when address 54321h is accessed by the program, the output address is 21h. example 2: in 256-byte extension mode, when address 67821h is accessed by the program, the output address is 21h. figure 17-2. pd784044 memory map (1/2) (a) when location 0h instruction is executed sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1 m-byte extension mode 256-byte to 256 k-byte extension modes internal rom internal rom external memory external memory external memory note 1 external memory note 2 fffffh 0ffffh 0ffe0h 0ffcfh 0fb00h 07fffh 00000h 0f600h use prohibited use prohibited notes 1. any extension size area in unshaded part 2. external sfr area 434 chapter 17 local bus interface function user s manual u11515ej3v0ud sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1 m-byte extension mode 256-byte to 256 k-byte extension modes internal rom internal rom external memory note 1 external memory external memory note 2 fffffh fffe0h fffcfh ffb00h 07fffh 00000h ff600h use prohibited use prohibited figure 17-2. pd784044 memory map (2/2) (b) when location 0fh instruction is executed notes 1. any extension size area in unshaded part 2. external sfr area 435 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-3. pd784046 memory map (1/2) (a) when location 0h instruction is executed sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1 m-byte extension mode 256-byte to 256 k-byte extension modes internal rom internal rom external memory external memory note 1 external memory note 2 fffffh 0ffffh 0ffe0h 0ffcfh 0f700h 00000h 0f600h use prohibited use prohibited use prohibited notes 1. any extension size area in unshaded part 2. external sfr area 436 chapter 17 local bus interface function user s manual u11515ej3v0ud sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1 m-byte extension mode 256-byte to 256 k-byte extension modes internal rom internal rom external memory note 1 external memory external memory note 2 fffffh fffe0h fffcfh ff700h 0ffffh 00000h use prohibited use prohibited ff600h notes 1. any extension size area in unshaded part 2. external sfr area figure 17-3. pd784046 memory map (2/2) (b) when location 0fh instruction is executed 437 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.1.3 basic operation of local bus interface the local bus interface accesses external memory using astb, rd, lwr, hwr, an address/data bus (ad0 to ad15) and address bus (a8 to a19). when the local bus interface is used, port 4 and p90 to p93 automatically operate as ad0 to ad7, rd, lwr, hwr, and astb. in ports 5 and 6, only the pins that correspond to the extension memory size operate as address bus pins. an outline of the memory access timing is shown in figures 17-4 to 17-9. figure 17-4. read timing (8 bits) condition bus size : 8 bits bus cycle : no wait note the number of address bus pins used depends on the extension mode size. figure 17-5. write timing (8 bits) condition bus size : 8 bits bus cycle : no wait note the number of address bus pins used depends on the extension mode size. high-order address data (input) astb (output) rd (output) ad0 - ad7 ad8-ad15 note a16-a19 note (output) hi-z hi-z hi-z low-order address (output) high-order address astb (output) ad0 - ad7 (output) ad8-ad15 note a16-a19 note (output) hi-z hi-z hi-z lwr (output) data low-order address 438 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-6. read timing (16 bits, even address access) condition bus size : 16 bits low-order 8-bit data : even address bus cycle : no wait high-order 8-bit data : odd address note the number of address bus pins used depends on the extension mode size. figure 17-7. write timing (16 bits, even address access) condition bus size : 16 bits low-order 8-bit data : even address bus cycle : no wait high-order 8-bit data : odd address note the number of address bus pins used depends on the extension mode size. high-order address data (input) astb (output) rd (output) ad0 - ad15 a16-a19 note (output) hi-z hi-z hi-z low-order address (output) high-order address astb (output) ad0 - ad15 (output) a16 - a19 note (output) hi-z hi-z hi-z lwr, hwr (output) data low-order address 439 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-8. read timing (16 bits, odd address access) condition bus size : 16 bits low-order 8-bit data : odd address bus cycle : no wait high-order 8-bit data : even address note the number of address bus pins used depends on the extension mode size. note the number of address bus pins used depends on the extension mode size. figure 17-9. write timing (16 bits, odd address access) condition bus size : 16 bits low-order 8-bit data : odd address bus cycle : no wait high-order 8-bit data : even address a16-a19 note (output) ad0-ad15 astb (output) rd (output) hi-z hi-z hi-z hi-z hi-z high-order address low-order address : odd address (output) data (input) low-order address : even address (output) data (input) a16-a19 note (output) ad0-ad15 (output) astb (output) lwr (output) hi-z hi-z hi-z hi-z hi-z high-order address low-order address : odd address data low-order address : even address data hwr (output) 440 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.2 wait function when a low-speed memory or i/o is connected externally to the pd784046, waits can be inserted in the external memory access cycle. there are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing the access time. 17.2.1 wait function control registers (1) memory extension mode register (mm) the ifch bit of the mm performs wait control setting for internal rom accesses, and the aw bit performs address wait setting. the mm can be read or written to with an 8-bit manipulation instruction. the mm format is shown in figure 17-10. when reset is input, the mm register is set to 20h, the same cycle as for external memory is used for internal rom accesses, and the address wait function is validated. figure 17-10. format of memory extension mode register (mm) ifch 0 aw 0 mm3 mm2 mm1 mm0 76543210 ifch 0 1 fetches internal rom fetches at same speed as external memory. all setting of wait control is valid. high-speed fetch. specification of wait control is invalid. mm address : 0ffc4h on reset : 20h r/w aw 0 1 specifiess address wait disabled enabled mm3 sets memory extension mode (refer to figure 17-1 ). mm2 mm1 mm0 441 chapter 17 local bus interface function user s manual u11515ej3v0ud (2) programmable wait control registers (pwc1/pwc2) the pwc1 and pwc2 specify the number of waits. pwc1 is an 8-bit register that divides the space from 0 to ffffh into four, and specifies wait control for each of these four spaces. pwc2 is a 16-bit register that divides the space from 10000h to ffffh into four, and specifies wait control for each of these four spaces. the pwc1 can be read or written to with an 8-bit manipulation instruction, and the pwc2 with a 16-bit manipulation instruction. the pwc1 and pwc2 formats are shown in figures 17-11 and 17-12. the high-order 8 bits of the pwc2 are fixed at aah, and therefore ensure that the high-order 8 bits are set to aah. when reset is input, the pwc1 is set to aah, and the pwc2 to aaaah, and 2-wait insertion is performed on the entire space. 442 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-11. format of programmable wait control register 1 (pwc1) pw31 pw30 pw21 pw20 pw11 pw10 pw01 pw00 76543210 valid address inserted wait cycle time of low level input to wait pin pwc1 address : 0ffc7h on reset : aah r/w pw31 0 0 1 1 pw30 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 valid address inserted wait cycle time of low level input to wait pin pw21 0 0 1 1 pw20 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 valid address inserted wait cycle time of low level input to wait pin pw11 0 0 1 1 pw10 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 valid address inserted wait cycle time of low level input to wait pin pw01 0 0 1 1 pw00 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 0 0 0 0 c f 0 f 0 f 0 f h- h note 0 0 0 0 8 b 0 f 0 f 0 f h- h 0 0 0 0 4 7 0 f 0 f 0 f h- h 0 0 0 0 0 3 0 f 0 f 0 f h- h 443 chapter 17 local bus interface function user s manual u11515ej3v0ud note except the portion overlapping the internal data area. cautions 1. the above number of cycles is when no address cycle is appended. if an address cycle is appended, one cycle must be added. 2. no wait cycle is inserted when fetching instructions from the internal rom or peripheral ram area at high-speed. 3. do not insert a wait cycle in the internal rom area by using the wait pin. 444 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-12. format of programmable wait control register 2 (pwc2) pw71 pw70 pw61 pw60 pw51 pw50 pw41 pw40 76543210 valid address inserted wait cycle time of low level input to wait pin pw71 0 0 1 1 pw70 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 valid address inserted wait cycle time of low level input to wait pin pw61 0 0 1 1 pw60 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 valid address inserted wait cycle time of low level input to wait pin pw51 0 0 1 1 pw50 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 valid address inserted wait cycle time of low level input to wait pin pw41 0 0 1 1 pw40 0 1 0 1 data access cycle, fetch cycle 0 1 2 3 4 5 10101010 15 14 13 12 11 10 9 8 pwc2 address : 0ffc8h on reset : aaaah r/w 0 0 8 f 0 f 0 f 0 f 0 f h- h note 0 0 4 7 0 f 0 f 0 f 0 f h- h 0 0 2 3 0 f 0 f 0 f 0 f h- h 0 0 1 1 0 f 0 f 0 f 0 f h- h 445 chapter 17 local bus interface function user s manual u11515ej3v0ud note except the portion overlapping the internal data area. cautions 1. the above number of cycles is when no address cycle is appended. if an address cycle is appended, one cycle must be added. 2. no wait cycle is inserted when fetching instructions from the peripheral ram area. 446 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.2.2 address waits address waits are used to secure the address decoding time. if the aw bit of the memory extension mode register (mm) is set (1), waits are inserted in every memory access note . when an address wait is inserted, the high-level period of the astb signal is extended by one system clock cycle (62.5 ns: f clk = 16 mhz). note except for the internal ram, internal sfrs, and internal rom during high-speed fetch. if it is specified that the internal rom is accessed in the same cycle as the external rom, an address wait state is inserted even when the internal rom is accessed. figure 17-13. read/write timing of address wait function (1/3) (a) read timing with no address wait insertion note f clk : internal system clock frequency. this signal is present inside the pd784046 only. remark the above figure is an example of the 8-bit bus. f clk note high-order address astb ad0 - ad7 ad8-ad15, a16-a19 hi-z hi-z rd input data low-order address hi-z 447 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-13. read/write timing of address wait function (2/3) (b) read timing with address wait insertion note f clk : internal system clock frequency. this signal is present inside the pd784046 only. remark the above figure is an example of the 8-bit bus. f clk note astb ad0-ad7 ad8-ad15, a16-a19 hi-z hi-z rd hi-z low-order address input data high-order address 448 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-13. read/write timing of address wait function (3/3) (c) write timing with no address wait insertion note f clk : internal system clock frequency. this signal is present inside the pd784046 only. remark the above figure is an example of the 8-bit bus. (d) write timing with address wait insertion f clk note high-order address astb ad0-ad7 ad8-ad15 a16-a19 hi-z hi-z lwr output data low-order address hi-z f clk note high-order address astb ad0-ad7 ad8-ad15 a16-a19 hi-z hi-z lwr output data low-order address hi-z 449 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.2.3 access waits access waits are inserted in the rd, lwr, or hwr signal low-level period, and extend the low-level period by 1/f clk (62.5 ns: f clk = 16 mhz) per cycle. there are two wait insertion methods, using either the programmable wait function that automatically inserts the preset number of cycles, or the external wait function controlled by a wait signal from outside. for wait cycle insertion control, the 1 m-byte memory space is divided into eight as shown in figure 17-15, and control is specified for each space by means of the programmable wait control registers (pwc1/pwc2). waits are not inserted in accesses to internal rom or internal ram using high-speed fetches. in accesses to internal sfrs, waits are inserted at the necessary times regardless of this specification. if access operations are specified as being performed in the same number of cycles as for external rom, waits are inserted also in internal rom accesses in accordance with the pwc1 settings. the p94 pin functions as a wait input pin when the pmc94 bit of the port 9 mode control register (pmc9) is set (1). the p94 pin operates as a general-purpose i/o port pin when reset is input (refer to figure 17-14 ). bus timing in the case of access wait insertion is shown in figures 17-16 to 17-18. caution do not insert a wait cycle in the internal rom area by using the wait pin. figure 17-14. format of port 9 mode control register (pmc9) 000 pmc94 0000 76543210 pmc94 0 1 specifies control mode of pin p94 i/o port mode wait input mode pmc9 address : 0ff49h on reset : 00h r/w 450 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-15. wait control spaces 512k bytes 256k bytes 128k bytes 64k bytes 16k bytes 16k bytes 16k bytes 16k bytes fffffh 80000h 03fffh 7ffffh controlled by bits pw70 & pw71 controlled by bits pw60 & pw61 controlled by pwc2 controlled by pwc1 controlled by bits pw50 & pw51 controlled by bits pw40 & pw41 controlled by bits pw30 & pw31 controlled by bits pw20 & pw21 controlled by bits pw10 & pw11 controlled by bits pw00 & pw01 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 40000h 3ffffh 04000h 00000h 451 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-16. read timing of access wait function (1/2) (a) 0 wait cycles set (b) 1 wait cycle set note f clk : internal system clock frequency. this signal is only present inside the pd784046. remark the above figure is an example of the 8-bit bus. f clk note high-order address astb (output) ad0-ad7 ad8-ad15, a16-a19 (output) hi-z hi-z rd (output) data (input) low-order address hi-z f clk note high-order address astb (output) ad0-ad7 ad8-ad15, a16-a19 (output) hi-z hi-z rd (output) data (input) low-order address hi-z 452 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-16. read timing of access wait function (2/2) (c) 2 wait cycles set note f clk : internal system clock frequency. this signal is only present inside the pd784046. remark the above figure is an example of the 8-bit bus. high-order address astb (output) ad0-ad7 ad8-ad15, a16-a19 (output) hi-z rd (output) data (input) low-order address hi-z f clk note 453 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-17. write timing of access wait function (1/2) (a) 0 wait cycles set (b) 1 wait cycle set note f clk : internal system clock frequency. this signal is only present inside the pd784046. remark the above figure is an example of the 8-bit bus. f clk note high-order address astb (output) ad0-ad7 (output) ad8-ad15, a16-a19 (output) hi-z hi-z lwr (output) data low-order address hi-z f clk note high-order address astb (output) ad0-ad7 (output) ad8-ad15, a16-a19 (output) hi-z hi-z lwr (output) data low-order address hi-z 454 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-17. write timing of access wait function (2/2) (c) 2 wait cycles set note f clk : internal system clock frequency. this signal is only present inside the pd784046. remark the above figure is an example of the 8-bit bus. high-order address astb (output) ad0-ad7 (output) ad8-ad15, a16-a9 (output) hi-z lwr (output) data low-order address hi-z f clk note hi-z 455 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-18. timing with external wait signal (a) read timing note f clk : internal system clock frequency. this signal is only present inside the pd784046. remark the above figure is an example of the 8-bit bus. (b) write timing high-order address astb (output) ad0-ad7 ad8-ad15, a16-a9 (output) hi-z rd (output) data (input) low-order address hi-z f clk note wait (input) high-order address astb (output) ad0-ad7 (output) ad8-ad15, a16-a9 (output) hi-z lwr (output) data low-order address hi-z f clk note wait (input) 456 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.3 bus sizing function the pd784046 has a bus sizing function that changes the external data bus width between 8 bits and 16 bits when an external device is connected. by using this function, the 1m-byte memory space can be divided by eight, and the external bus width can be specified in each memory space by using the bus width specification register (bw). 17.3.1 bus width specification register (bw) bw is a 16-bit register that specifies the bus width when an external device is connected. this register cannot be accessed in 8-bit units. be sure to access it by using a 16-bit data manipulation instruction. figure 17-19 shows the format of bw the value of bw differs depending on the setting of the bwd pin after reset is input. when bwd = 0, the value of bw is 0000h; when bwd = 1, it is 00ffh. 457 chapter 17 local bus interface function user s manual u11515ej3v0ud figure 17-19. format of bus width specification register (bw) note the value of this register on reset differs depending on the setting of the bwd pin, as follows: bwd = 0: 0000h bwd = 1: 00ffh bw7 bw6 bw5 bw4 bw3 bw2 bw1 bw0 76543210 valid address specifies external data bus width 8-bit bus 16-bit bus bw7 00000000 15 14 13 12 11 10 9 8 bw address : 0ffcah on reset : note r/w valid address specifies external data bus width 8-bit bus 16-bit bus bw6 valid address specifies external data bus width 8-bit bus 16-bit bus bw5 valid address specifies external data bus width 8-bit bus 16-bit bus bw4 valid address specifies external data bus width 8-bit bus 16-bit bus bw3 valid address specifies external data bus width 8-bit bus 16-bit bus bw2 valid address specifies external data bus width 8-bit bus 16-bit bus bw1 valid address specifies external data bus width 8-bit bus 16-bit bus bw0 0 0 8 f 0 f 0 f 0 f 0 f h- h 0 0 4 7 0 f 0 f 0 f 0 f h- h 0 0 2 3 0 f 0 f 0 f 0 f h- h 0 0 1 1 0 f 0 f 0 f 0 f h- h 0 0 0 0 c f 0 f 0 f 0 f h- h 0 0 0 0 8 b 0 f 0 f 0 f h- h 0 0 0 0 4 7 0 f 0 f 0 f h- h 0 0 0 0 0 3 0 f 0 f 0 f h- h 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 458 chapter 17 local bus interface function user s manual u11515ej3v0ud 17.4 cautions (1) no wait cycle is inserted when instructions are fetched from the internal rom or peripheral ram area at high speeds. (2) do not insert a wait cycle in the internal rom area by using the wait pin. 459 user? manual u11515ej3v0ud chapter 18 standby function 18.1 configuration and function the pd784046 has a standby function that enables the system power consumption to be reduced. the standby function includes three modes as follows: halt mode in this mode the cpu operating clock is stopped. intermittent operation in combination with the normal operating mode enables the total system power consumption to be reduced. idle mode in this mode the oscillator continues operating while the entire remainder of the system is stopped. normal program operation can be restored at a low power consumption close to that of the stop mode and in a time equal to that of the halt mode. stop mode in this mode the oscillator is stopped and the entire system is stopped. ultra-low power consumption can be achieved, consisting of leakage current only. these modes are set by software. the diagram of the standby mode (stop/idle/halt mode) transition is shown in figure 18-1, and the block diagram of the standby function in figure 18-2. figure 18-1. diagram of standby mode transition note unmasked interrupt request only remark only external input is valid as nmi. the watchdog timer must not be used to release the standby mode (stop, halt, or idle mode). wait of oscillation stabilization program operation macro service macro service request end of 1st service end of macro service macro service request end of 1st service stop setting reset input nmi idle setting nmi interrupt request note halt setting masked interrupt request reset input halt (standby) idle (standby) stop (standby) end of oscillation stabilization time reset input 460 chapter 18 standby function user s manual u11515ej3v0ud figure 18-2. diagram of standby function block extc system clock oscillator frequency divider oscillation stabilization timer (19) osts0 osts1 osts2 extc nmi reset rising edge detection rising edge detection selector esnmi interrupt intc macro service request selector ram protect to peripheral circuit cpu clk hlt f/f idle f/f stp f/f2 stp f/f1 macro service request hlt bit setting stop bit setting q s r q q s r q q s r q q s r q f xx f xx /2 (f clk ) 461 chapter 18 standby function user s manual u11515ej3v0ud 18.2 control registers 18.2.1 standby control register (stbc) the stbc is a register used to control the standby mode. to prevent entry into the standby mode due to an inadvertent program loop, the stbc register can only be written to with a dedicated instruction. this dedicated instruction, mov stbc, #byte, has a special code configuration (4 bytes), and a write is only performed if the 3rd and 4th bytes of the operation code are mutual complements. if the 3rd and 4th bytes of the operation code are not mutual complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov stbc, #byte is written), system initialization should be performed by the program. other write instructions (mov stbc, a, and stbc, #byte, set1 stbc.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to the stbc, and an interrupt such as an operand error interrupt is not generated . the stbc can be read at any time by a data transfer instruction. reset input sets the stbc register to 30h. the format of the stbc is shown in figure 18-3. figure 18-3. standby control register (stbc) format caution if the stop mode is used when using external clock input, the extc bit of the oscillation stabilization time specification register (osts) must be set (1) before setting stop mode. if the stop mode is used with the extc bit cleared (0) when using external clock input, the pd784046 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock oscillator). 001100stphlt 76543210 stp 0 0 1 1 controls cpu operation control normal operating mode halt mode stop mode idle mode stbc address : 0ffc0h on reset : 30h r/w hlt 0 1 0 1 462 chapter 18 standby function user s manual u11515ej3v0ud 18.2.2 oscillation stabilization time specification register (osts) the osts specifies the oscillator operation and the oscillation stabilization time when stop mode is released. set the state of the clock oscillator operation to the extc bit of the osts. stop mode can be set when external clock input is used only when the extc bit is set (1). bits osts0 to osts2 of the osts select the oscillation stabilization time when stop mode is released. in general, an oscillation stabilization time of at least 40ms should be selected when a crystal resonator is used, and at least 4 ms when a ceramic oscillator is used. the time taken for oscillation stabilization is affected by the crystal resonator or ceramic resonator used, and the capacitance of the connected capacitor. therefore, if you want to set a short oscillation stabilization time, you should consu lt the crystal resonator or ceramic resonator manufacturer. the osts can be read/written only with an 8-bit manipulation instruction. reset input clears the osts register to 00h. the format of the osts is shown in figure 18-4. 463 chapter 18 standby function user s manual u11515ej3v0ud figure 18-4. format of oscillation stabilization time specification register (osts) remark f clk : internal system clock : don t care cautions 1. when crystal/ceramic oscillation is used, the extc bit of the oscillation stabilization time specification register (osts) must be cleared (0) before use. if the extc bit is set (1), oscillation will stop. 2. if the stop mode is used when using external clock input, the extc bit must be set (1) before setting stop mode. if the stop mode is used with the extc bit cleared (0) the pd784046 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock oscillator). extc 0000 osts2 osts1 osts0 76543210 extc 0 1 selects external clock x2 pin is open when crystal/ceramic oscillation is used or when external clock is used. input signal in reverse phase to that input to x1 pin to x2 pin when external clock is used. osts address : 0ffcfh on reset : 00h r/w extc 0 0 0 0 0 0 0 0 1 selects oscillation stabilization time 2 19 /f clk (32.8 ms) 2 18 /f clk (16.4 ms) 2 17 /f clk (8.19 ms) 2 16 /f clk (4.10 ms) 2 15 /f clk (2.05 ms) 2 14 /f clk (1.02 ms) 2 13 /f clk (512 s) 2 12 /f clk (256 s) 2 8 /f clk (16 s) osts2 0 0 0 0 1 1 1 1 osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 (f clk = 16 mhz) 464 chapter 18 standby function user s manual u11515ej3v0ud 18.3 halt mode 18.3.1 halt mode setting and operating states the halt mode is selected by setting (1) the hlt bit of the standby control (stbc) register or clearing (0) the stp bit. the only writes that can be performed on the stbc are 8-bit data writes by means of a dedicated instruction. halt mode setting is therefore performed by means of the mov stbc, #byte instruction. caution if a condition that releases the halt mode comes into effect when the halt mode is being set, the halt mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt service program is performed. before this branch execution, the instructions after the halt mode setting may be executed for 6 clocks. after restoring from the interrupt service, to execute an instruction after setting the halt mode, insert 3 nop instructions before the instruction. to be sure to set the halt mode, take the necessary precautions such as clearing the interrupt request before setting the halt mode. table 18-1. operating states in halt mode clock oscillator operating internal system clock operating cpu operation stopped note 1 i/o lines retain state prior to halt mode setting peripheral functions continue operating internal ram retained bus lines ad0 to ad7 high-impedance ad8 to ad15 retained note 2 a16-a19 rd, lwr, hwr output high level astb output low level notes 1. macro service processing is executed. 2. if the fetch address is an external memory address, and is 16-bits wide, ad8 through ad15 go into high- impedance after the macro service interrupt has been processed. 18.3.2 halt mode release halt mode can be released by the following three sources. non-maskable interrupt request maskable interrupt request (vectored interrupt/context switching/macro service) reset input release sources and an outline of operations after release are shown in table 18-2. 465 chapter 18 standby function user s manual u11515ej3v0ud table 18-2. halt mode release and operations after release release source mk note 1 ie note 2 state on release operation after release non-maskable non-maskable interrupt service program interrupt request acknowledgment interrupt request not being executed (nmi pin input low-priority non-maskable interrupt only. excluding service program being executed watchdog service program for same request being execution of instruction after mov stbc/ timer. note 5 ) executed #byte instruction (interrupt request that high-priority non-maskable interrupt released halt mode is held pending note 3 ) service program being executed maskable 0 1 interrupt service program not being interrupt request acknowledgment interrupt request executed (excluding macro low-priority maskable interrupt service service request) program being executed prsl bit note 4 cleared (0) during execution of priority level 3 interrupt service program same-priority maskable interrupt service execution of instruction after mov stbc/ program being executed #byte instruction (interrupt request that (if prsl bit note 4 is cleared (0), excluding released halt mode is held pending note 3 ) execution of priority level 3 interrupt service program) high-priority interrupt service program being executed 00 1 halt mode maintained macro service 0 macro service processing execution request end condition not established halt mode again end condition established same as release by maskable interrupt request 1 halt mode maintained reset input normal reset operation notes 1. interrupt mask bit in individual interrupt request source 2. interrupt enable flag in program status word (psw) 3. pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. bit in interrupt mode control register (imc) 5. the halt mode cannot be released by the watchdog timer. 466 chapter 18 standby function user s manual u11515ej3v0ud (1) release by non-maskable interrupt when a non-maskable interrupt is generated, the pd784046 is released from halt mode irrespective of whether the interrupt acknowledgment enabled state (ei) or disabled state (di) is in effect. when the pd784046 is released from halt mode, if the non-maskable interrupt that released halt mode can be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service program. if the interrupt cannot be acknowledged, the instruction following the instruction that set the halt mode (the mov stbc, #byte instruction) is executed, and the non-maskable interrupt that released the halt mode is acknowledged when acknowledgment becomes possible. refer to 16.6 non-maskable interrupt acknowledg- ment operation for details of non-maskable interrupt acknowledgment. (2) release by maskable interrupt request halt mode release by a maskable interrupt request can only be performed by an interrupt for which the interrupt mask flag is 0. when halt mode is released, if an interrupt can be acknowledged when the interrupt request enable flag (ie) is set (1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (0), execution is resumed from the instruction following the instruction that set the halt mode. refer to 16.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. with macro service, halt mode is released temporarily, service is performed once, then halt mode is restored. when macro service has been performed the specified number of times, halt mode is released. the operation after release in this case is the same as for release by a maskable interrupt described earlier. (3) release by reset input the program is executed after branching to the reset vector address, as in a normal reset operation. however, internal ram contents retain their value directly before halt mode was set. 467 chapter 18 standby function user s manual u11515ej3v0ud 18.4 stop mode 18.4.1 stop mode setting and operating states the stop mode is selected by setting (1) the stp bit of the standby control register (stbc) register or clearing (0) the hlt bit. the only writes that can be performed on the stbc register are 8-bit data writes by means of a dedicated instruction. stop mode setting is therefore performed by means of the mov stbc, #byte instruction, caution if a condition that releases the halt mode comes into effect when the stop mode is being set (refer to 18.3.2 halt mode release), the stop mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt service program is performed. before this branch execution, the instructions after the stop mode setting may be executed for 6 clocks. after restoring from the interrupt service, to execute an instruction after setting the stop mode, insert 3 nop instructions before the instruction. to be sure to set the stop mode, take the necessary precautions such as clearing the interrupt request before setting the stop mode. table 18-3. operating states in stop mode clock oscillator oscillation stopped internal system clock stopped cpu operation stopped i/o lines retain state prior to stop mode setting peripheral functions all operation stopped note internal ram retained bus lines ad0 to ad15 high-impedance a16 to a19 high-impedance rd, lwr, hwr output high-impedance astb output high-impedance note a/d converter operation is stopped, but if the am0 bit or am1 bit of the a/d converter mode register (adm) is set (1), the current consumption does not decrease. cautions 1. if the stop mode is set when the extc bit of the oscillation stabilization time specification (osts) register is cleared (0), the x1 pin is shorted internally to v ss (gnd potential) to suppress clock generator leakage. therefore, when the stop mode is used in a system that uses an external clock, the extc bit of the osts must be set (1). if stop mode setting is performed in a system to which an external clock is input when the extc bit of the osts is cleared (0), the pd784046 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock oscillator). 2. stop the a/d converter (by clearing (0) the am0 and am1 bits of the a/d converter mode register (adm)) before setting the stop mode. 468 chapter 18 standby function user s manual u11515ej3v0ud 18.4.2 stop mode release stop mode is released by nmi input, intp4 input, intp5 input, and reset input. table 18-4. stop mode release and operations after release release state after release operation after release source nmi pin input non-maskable interrupt service interrupt request acknowledgment program not being executed low-priority non-maskable interrupt service program being executed nmi pin input service program being execution of instruction after mov stbc/ executed #byte instruction (interrupt request that high-priority non-maskable interrupt released stop mode is held pending note ) service program being executed reset input normal reset operation note pending interrupt requests are acknowledged when acknowledgment becomes possible. (1) stop mode release by nmi input the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (intm0) is input to the nmi input. stop mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (osts) elapses. when the pd784046 is released from stop mode, if a non-maskable interrupt by nmi pin input can be acknowledged, a branch is made to the nmi interrupt service program. if the interrupt cannot be acknowledged (if the stop mode is set in an nmi interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the stop mode, and a branch is made to the nmi interrupt service program when acknowledgment becomes possible (by execution of an reti instruction, etc.). refer to 16.6 non-maskable interrupt acknowledgment operation for details of nmi interrupt acknowledgment. figure 18-5. stop mode release by nmi input (2) stop mode release by reset input when reset input falls from high to low and the reset state is established, the oscillator resumes oscillation. the oscillation stabilization time should be secured while reset is active. thereafter, normal operation is started when reset rises. unlike an ordinary reset operation, data memory retains its contents prior to stop mode setting. oscillator f clk stp f/f1 nmi input rising edge specified stp f/f2 oscillator stopped stop oscillation stabilization count time 469 chapter 18 standby function user s manual u11515ej3v0ud 18.5 idle mode 18.5.1 idle mode setting and operating states the idle mode is selected by setting (1) both the stp bit and the hlt bit of the standby control (stbc) register. the only writes that can be performed on the stbc are 8-bit data writes by means of a dedicated instruction. idle mode setting is therefore performed by means of the mov stbc, #byte instruction. caution if a condition that releases the halt mode comes into effect when the idle mode is being set (refer to 18.3.2 halt mode release), the idle mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt service program is performed. before this branch execution, the instructions after the idle mode setting may be executed for 6 clocks. after restoring from the interrupt service, to execute an instruction after setting the idle mode, insert 3 nop instructions before the instruction. to be sure to set the idle mode, take the necessary precautions such as clearing the interrupt request before setting the idle mode. table 18-5. operating states in idle mode clock oscillator oscillation continues internal system clock stopped cpu operation stopped i/o lines retain state prior to idle mode setting peripheral functions all operation stopped note internal ram retained bus lines ad0 to ad15 high-impedance a16 to a19 high-impedance rd, lwr, hwr output high-impedance astb output high-impedance note a/d converter operation is stopped, but if the am0 bit or am1 bit of the a/d converter mode register (adm) is set, the current consumption does not decrease. caution stop the a/d converter (by clearing (0) the am0 and am1 bits of the a/d converter mode register (adm)) before setting the idle mode. 470 chapter 18 standby function user s manual u11515ej3v0ud 18.5.2 idle mode release idle mode is released by nmi input, or reset input. table 18-6. idle mode release and operations after release release state after release operation after release source nmi pin input non-maskable interrupt service interrupt request acknowledgment program not being executed low-priority non-maskable interrupt service program being executed nmi pin input service program being execution of instruction after mov stbc/ executed #byte instruction (interrupt request that high-priority non-maskable interrupt released idle mode is held pending note ) service program being executed reset input normal reset operation note pending interrupt requests are acknowledged when acknowledgment becomes possible. (1) idle mode release by nmi input idle mode is released when the valid edge specified by external interrupt mode register 0 (intm0) is input to the nmi input. when the pd784046 is released from idle mode, if a non-maskable interrupt by nmi pin input can be acknowledged, a branch is made to the nmi interrupt service program. if the interrupt cannot be acknowledged (if the idle mode is set in an nmi interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the idle mode, and a branch is made to the nmi interrupt service program when acknowledgment becomes possible (by execution of an reti instruction, etc.). refer to 16.6 non-maskable interrupt acknowledgment operation for details of nmi interrupt acknowledgment. (2) idle mode release by reset input normal operation is started when reset rises after reset input falls from high to low. unlike an ordinary reset operation, data memory retains its contents prior to idle mode setting. caution when the execution of the idle mode instruction contends with the interrupt of release source of the idle mode, the stop mode is released after the stop mode has been executed, instead of the normal operation where the idle mode is released after the idle mode has been executed, because of a malfunction of the pd784054. therefore, when the idle mode is released, the wait operation for the oscillation stabilization time set by the oscillation stabilization time specification register (osts) may be executed even though the idle mode is set in software (usually, the pd784054 does not wait the oscillation stabilization time when the idle mode is released.) if there are problems with waiting for the oscillation stabilization time when the idle mode is released, set the value of the oscillation stabilization time set by the osts as short as possible. 471 chapter 18 standby function user s manual u11515ej3v0ud 18.6 check items when stop mode/idle mode is used check items required to reduce the current consumption when stop mode/idle mode is used are shown below. (1) is the output level of each output pin appropriate? the appropriate output level for each pin varies according to the next-stage circuit. you should select the output level that minimizes the current consumption. if high level is output when the input impedance of the next-stage circuit is low, a current will flow from the power supply to the port, resulting in an increased current consumption. this applies when the next-stage circuit is a cmos ic, etc. when the power supply is off, the input impedance of a cmos ic is low. in order to suppress the current consumption, or to prevent an adverse effect on the reliability of the cmos ic, low level should be output. if a high level is output, latchup may result when power is turned on again. depending on the next-stage circuit, inputting low level may increase the current consumption. in this case, high- level or high-impedance output should be used to reduce the current consumption. if the next-stage circuit is a cmos ic, the current consumption of the cmos ic may increase if the output is made high-impedance when power is supplied to it (the cmos ic may also be overheated and damaged). in this case you should output an appropriate level, or pull the output high or low with a resistor. the method of setting the output level depends on the port mode. when a port is in control mode, the output level is determined by the status of the on-chip hardware, and therefore the on-chip hardware status must be taken into consideration when setting the output level. in port mode, the output level can be set by writing to the port output latch and port mode register by software. when a port is in control mode, its output level can be set easily by changing to port mode. 472 chapter 18 standby function user? manual u11515ej3v0ud (2) is the input pin level appropriate? the voltage level input to each pin should be in the range between v ss potential and v dd potential. if a voltage outside this range is applied, the current consumption will increase and the reliability of the pd784046 may be adversely affected. also ensure that an intermediate potential is not applied. (3) are pull-up resistors necessary? an unnecessary pull-up resistor will increase the current consumption and cause a latchup of other devices. a mode should be specified in which pull-up resistors are used only for parts that require them. if there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pull- up resistor externally and specify a mode in which the on-chip pull-up resistor is not used. (4) is processing of the address bus, address/data bus, etc., appropriate? in stop mode and idle mode, the address bus, address/data bus, rd and lwr, hwr pins become high- impedance. normally, these pins are pulled high with a pull-up resistor. if this pull-up resistor is connected to the backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is low, a current will flow through the pull-up resistor, and the current consumption will increase. therefore, the pull- up resistor should be connected to the non-backed-up power supply side as shown in figure 18-6. also, in stop mode and idle mode the astb pin also becomes high impedance. countermeasures should be taken with reference to the points noted in (1). figure 18-6. example of address/data bus processing (5) a/d converter the current flowing to the av dd , av ref1 pins can be reduced by clearing (0) the am0 and am1 bits of the a/d converter mode register (adm). make sure that the av dd pin is not at the same potential as the v dd pin. unless power is supplied to the av dd pin in the stop mode, not only does the current consumption increase, but the reliability is also affected. v dd v dd in/out cmos ic, etc. v ss v ss non-backed-up power supply adn (n = 0-15) pd784046 backed-up power supply 473 chapter 18 standby function user s manual u11515ej3v0ud 18.7 cautions (1) if a condition that releases the halt mode comes into effect when the halt/stop/idle mode (hereafter referred to as standby mode) is being set (refer to 18.3.2 halt mode release ), the standby mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt service program is performed. before this branch execution, the instructions after the standby mode setting may be executed for 6 clocks. after restoring from the interrupt service, to execute an instruction after setting the standby mode, insert 3 nop instructions before the instruction. to be sure to set the standby mode, take the necessary precautions such as clearing the interrupt request before setting the standby mode. (2) when crystal/ceramic oscillation is used, the extc bit must be cleared (0) before use. if the extc bit is set (1), oscillation will stop. (3) if the stop mode is set when the extc bit of the oscillation stabilization time specification (osts) register is cleared (0), the x1 pin is shorted internally to v ss (gnd potential) to suppress clock generator leakage. therefore, when the stop mode is used in a system that uses an external clock, the extc bit of the osts must be set (1). if stop mode setting is performed in a system to which an external clock is input when the extc bit of the osts is cleared (0), the pd784046 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock oscillator ). (4) stop the a/d converter (by clearing (0) the am0 and am1 bits of the a/d converter mode register (adm)) before setting the stop or idle mode. (5) when the execution of the idle mode instruction contends with the interrupt of release source of the idle mode, the stop mode is released after the stop mode has been executed, instead of the normal operation where the idle mode is released after the idle mode has been executed, because of a malfunction of the pd784054. therefore, when the idle mode is released, the wait operation for the oscillation stabilization time set by the oscillation stabilization time specification register (osts) may be executed even though the idle mode is set in software (usually, the pd784054 does not wait the oscillation stabilization time when the idle mode is released.) if there are problems with waiting for the oscillation stabilization time when the idle mode is released, set the value of the oscillation stabilization time set by the osts as short as possible. 474 user? manual u11515ej3v0ud chapter 19 reset function 19.1 reset function when low level is input to the reset input pin, a system reset is affected, the various hardware units are set to the states shown in table 19-2, and all pins except the power supply pins and the x1 and x2 clkout pins are placed in the high- impedance state. table 19-1 shows the pin statuses on reset and after reset release. when the reset input changes from low to high level, the reset state is released, the contents of address 00000h of the reset vector table are set in bits 0 to 7 of the program counter (pc), the contents of address 00001h in bits 8 to 15, and 0000b in bits 16 to 19, a branch is made, and program execution is started at the branch destination address. a reset start can therefore be performed from any address in the base area. the contents of the various registers should be initialized as required in the program in the base area. to prevent misoperation due to noise, the reset input pin incorporates an analog delay noise elimination circuit (refer to figure 19-1 ). figure 19-1. acknowledgment of reset signal delay pc initialization, etc. execution of instruction at reset start address reset start delay delay reset end internal reset signal reset (input) in a reset operation upon powering on and stop mode release by reset, the reset signal must be kept active until the oscillation stabilization time has elapsed (approx. 40 ms, depending on the resonator used). figure 19-2. power-on reset operation oscillation stabilization time v dd delay pc initialization, etc. execution of instruction at reset start address internal reset signal reset end reset (input) 475 chapter 19 reset function user s manual u11515ej3v0ud table 19-1. pin status during reset input and after clearing reset pin name i/o during reset immediately after clearing reset p00-p03 i/o hi-z hi-z (input port mode) p10-p13 p20 input hi-z (input port) p21-p27 i/o hi-z (input port mode) p30-p37 p40-p47 p50-p57 p60-p63 p70-p77 input hi-z (input port) p80-p87 p90-p94 i/o hi-z (input port mode) clkout output clock output clock output figure 19-3. timing on reset input reset (input) clkout (output) other i/o ports hi-z reset period clearing reset - instruction execution time 476 chapter 19 reset function user s manual u11515ej3v0ud table 19-2. state of hardware after reset (1/2) hardware state after reset program counter (pc) contents of reset vector table (0000h, 0001h) are set stack pointer (sp) undefined note program status word (psw) 02h on-chip ram data memory undefined note general-purpose register port port 0 to port 9 undefined (high impedance) mode registers (pm0 to pm6, pm9) ffh mode control registers (pmc1 to pmc3, pmc9) 00h port read control register (prdc) pull-up resistor option register (puol, puoh) port 0 buffer register (p0l) undefined real-time output port control register (rtpc) 00h timer/counter timer registers (tm0 to tm4) 0000h capture/compare registers (cc00 to cc03) undefined compare registers (cm10, cm11, cm20, cm21, cm30, cm31, cm40, cm41) timer unit mode registers (tum0, tum2) 00h timer mode control registers (tmc, tmc2, tmc4) timer output control registers (toc0 to toc2) prescaler mode registers (prm, prm2, prm4) noise protection control register (npc) interrupt valid edge flag registers (ief1, ief2) undefined watchdog timer mode register (wdm) 00h a/d converter a/d converter mode register (adm) a/d conversion result registers (adcr0 to adcr7, adcr0h to adcr7h) undefined serial interface asynchronous serial interface mode registers (asim, asim2) 00h asynchronous serial interface status registers (asis, asis2) serial receive buffers (rxb, rxb2) undefined serial transmit shift registers (txs, txs2) clocked serial interface mode registers (csim1, csim2) 00h serial shift registers (sio1, sio2) undefined baud rate generator control registers (brgc, brgc2) 00h external interrupt mode registers (intm0, intm1) note if the halt, stop, or idle mode is released by using the reset input, the values immediately before each mode has been set are retained. 477 chapter 19 reset function user s manual u11515ej3v0ud table 19-2. state of hardware after reset (2/2) hardware state after reset interrupt interrupt control registers (ovic0, ovic1, ovic4, pic0 to pic6, 43h cmic10, cmic11, cmic20, cmic21, cmic30, cmic31, cmic40, cmic41, seric, sric, csiic1, stic, seric2, sric2, csiic2, stic2, adic) interrupt mask registers mk0, mk1 ffffh mk0l, mk0h, mk1l, mk1h ffh interrupt mode control register (imc) 80h in-service priority register (ispr) 00h memory extension mode register (mm) 20h programmable wait control register pwc1 aah pwc2 aaaah bus width specification register (bw) 0000h (bwd = 0) 00ffh (bwd = 1) standby control register (stbc) 30h oscillation stabilization time specification register (osts) 00h internal memory size switching register (ims) cdh ( pd784044) deh ( pd784046, 78f4046) 19.2 caution reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached the prescribed voltage. 478 user? manual u11515ej3v0ud chapter 20 programming pd78f4046 the flash memory can be written with the pd78f4046 mounted on the target system (on-board). connect a dedicated flash programmer (flashpro ii (part number: fl-pr2)/flashpro iii (part number: fl-pr3, pg-fp3)) to the host machine and target system to write the flash memory. the flash memory can also be written using the adapter for writing flash memory connected to flashpro ii/flashpro iii. remark flashpro ii and flashpro iii are products of naito densei machida mfg. co., ltd. 20.1 selecting communication mode the flash memory is written by using a flashpro ii/flashpro iii and by means of serial communication. select a communication mode from those listed in table 20-1. to select a communication mode, the format shown in figure 20- 1 is used. each communication mode is selected by the number of v pp pulses shown in table 20-1. table 20-1. communication modes communication mode number of channels pins used number of v pp pulses 3-wire serial i/o 2 p34/asck/sck1 0 p33/txd/so1 p32/rxd/si1 p37/asck2/sck2 1 p36/txd2/so2 p35/rxd2/si2 uart 2 p33/txd/so1 8 p32/rxd/si1 p36/txd2/so2 9 p35/rxd2/si2 caution be sure to select the communication mode with the number of v pp pulses as shown in table 20-1. figure 20-1. selecting format of communication mode 10v v dd mode/v pp v ss v dd v ss reset 12 n 479 chapter 20 programming pd78f4046 user s manual u11515ej3v0ud 20.2 function of flash memory programming by transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. table 20-2 shows the major functions of flash memory programming. table 20-2. major functions of flash memory programming. function description batch erase erases all contents of memory. block erase erases specified memory block with one block consisting of 16k bytes. batch blank check checks erased state of entire memory. block blank check checks erased state of specified block. data write writes to flash memory based on write start address and number of data written (number of bytes). batch verify compares all contents of memory with input data. block verify compares contents of specified memory block with input data. 20.3 connecting flashpro ii/flashpro iii how the flashpro ii/flashpro iii is connected to the pd78f4046 differs to the pd78f4046 depending on the communication mode (3-wire serial i/o or uart). figures 20-2 and 20-3 show the connections in the respective modes. figure 20-2. connecting flashpro ii/flashpro iii in 3-wire serial i/o mode flashpro ii/flashpro iii pd78f4046 vpp vdd reset so sck si gnd v pp v dd reset sck1 or sck2 si1 or si2 so1 or so2 v ss 480 chapter 20 programming pd78f4046 user? manual u11515ej3v0ud figure 20-3. connecting flashpro ii/flashpro iii in uart mode 20.4 cautions (1) number of rewrites number of guaranteed rewrites: 10 perform erasure and writing in area mode or chip mode. block mode cannot be used to write only a specific block. (2) operating ambient temperature operating ambient temperature: t a = ?0 to +70 c however, the temperature during rewrite is t prg = +10 to +40 c. (3) use of pre-writing pre-writing is required before erasure. when flashpro ii (ver. 2.50 or later) or flashpro iii (pg-fp3 ver. 3.040 or later) is used, use of the pre-write function can automatically be set by loading the parameter file. (4) use of ecc function write ecc data to the ecc area in the on-chip flash memory. convert the hex file into a hex file with ecc using the ecc generator included in the assembler package (pc version ver.1.20 or later). then download this hex file with ecc to flashpro ii or flashpro iii and execute writing. [how to create ecc data] <1> prepare a hex file created by the object converter in the assembler package. <2> convert the hex file into a hex file with ecc (program data + ecc data) using the ecc generator (eccgen.exe) included in the assembler package. example when converting the file ?ile.hex?into the hex file with ecc ?ile_ec.hex eccgen file.hex -ofile_ec.hex -a0ffffh, 1000h, 14000h, 14004h flashpro ii/flashpro iii pd78f4046 v pp v dd reset rxd or rxd2 txd or txd2 v ss vpp vdd reset so si gnd 481 chapter 20 programming pd78f4046 user s manual u11515ej3v0ud (5) how to set and write using flashpro ii or flashpro iii perform pre-writing and write to ecc using flashpro ii or flashpro iii. [how to write] <1> download the hex file with ecc to flashpro ii or flashpro iii. <2> set chip mode and execute writing using the e.p.v button. do not use the program command; otherwise ecc may not be written. when flashpro ii ver. 2.50 or earlier is used, the pre-write and ecc functions must be validated using the following procedure before executing a write. [how to set using flashpro ii ver.2.50 or earlier] <1> connect the pc and the fl-pr2 and activate the control software (flashpro.exe) <2> press the crtl, shift, grph (alt), and p keys at the same time <3> select pre-write set <4> click the ok button. <5> select setting <6> select option . <7> select ecc code area in the menu window. <8> input 14004 to the ecc end address field. <9> click the ok button. <10> click the type button. <11> input 14004 to the ecc address field <12> click the ok button. pre-write setting ecc write setting 482 user? manual u11515ej3v0ud chapter 21 instruction operations 21.1 legend (1) explanation of operand identifiers (1/2) identifier explanation r, r note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7, r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r1 note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7 r2 r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r3 v, u, t, w rp, rp note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5), de(rp6), hl(rp7) rp1 note 2 ax(rp0), bc(rp1), rp2, rp3 rp2 vp(rp4), up(rp5), de(rp6), hl(rp7) rg, rg vvp(rg4), uup(rg5), tde(rg6), whl(rg7) sfr special function register symbol sfrp special function register symbol (register for which 16-bit operation is possible) post note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5)/psw, de(rp6), hl(rp7) multiple descriptions are permissible. however, up is only used with push/pop instructions, and psw with pushu/popu instructions. mem [tde], [whl], [tde+], [whl+], [tde?, [whl?, [vvp], [uup]: register indirect addressing [tde+byte], [whl+byte], [sp+byte], [uup+byte], [vvp+byte]: based addressing imm24 [a], imm24 [b], imm24 [de], imm24 [hl]: indexed addressing [tde+a], [tde+b], [tde+c], [whl+a], [whl+b], [whl+c], [vvp+de], [vvp+hl]: based indexed addressing mem1 all mem except [whl+] and [whl? mem2 [tde], [whl] mem3 [ax], [bc], [rp2], [rp3], [vvp], [uup], [tde], [whl] notes 1. setting the rss bit to 1 enables r4 to r7 to be used as x, a, c and b, but this function should only be used when using a 78k/iii series program. 2. setting the rss bit to 1 enables rp2 and rp3 to be used as ax and bc, but this function should only be used when using a 78k/iii series program. 483 chapter 21 instruction operations user? manual u11515ej3v0ud (1) explanation of operand identifiers (2/2) identifier explanation note saddr, saddr fd20h to ff1fh immediate data or label saddr1 fe00h to feffh immediate data or label saddr2 fd20h to fdffh, ff00h to ff1fh immediate data or label saddrp fd20h to ff1eh immediate data or label (16-bit operation) saddrp1 fe00h to feffh immediate data or label (16-bit operation) saddrp2 fd20h to fdffh, ff00h to ff1eh immediate data or label (16-bit operation) saddrg fd20h to fefdh immediate data or label (24-bit operation) saddrg1 fe00h to fefdh immediate data or label (24-bit operation) saddrg2 fd20h to fdffh immediate data or label (24-bit operation) addr24 0h to ffffffh immediate data or label addr20 0h to fffffh immediate data or label addr16 0h to ffffh immediate data or label addr11 800h to fffh immediate data or label addr8 0fe00h to 0feffh * immediate data or label addr5 40h to 7eh immediate data or label imm24 24-bit immediate data or label word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label n 3-bit immediate data locaddr 0h or 0fh note the addresses shown here apply when 0h is specified by the location instruction. when 0fh is specified by the location instruction, f0000h should be added to the address values shown. 484 chapter 21 instruction operations user? manual u11515ej3v0ud (2) operand column symbols symbol explanation + auto-increment auto-decrement # immediate data ! 16-bit absolute address !! 24-bit/20-bit absolute address $ 8-bit relative address $! 16-bit relative address / bit inversion [ ] indirect addressing [%] 24-bit indirect addressing (3) flag column symbols symbol explanation (blank) no change 0 cleared to 0 1 set to 1 set or cleared depending on result p p/v flag operates as parity flag v p/v flag operates as overflow flag r previously saved value is restored (4) operation column symbols symbol explanation jdisp8 signed two? complement data (8 bits) indicating relative address distance between start address of next instruction and branch address jdisp16 signed two? complement data (16 bits) indicating relative address distance between start address of next instruction and branch address pc hw pc bits 16 to 19 pc lw pc bits 0 to 15 485 chapter 21 instruction operations user? manual u11515ej3v0ud (5) number of bytes of instruction that includes mem in operands mem mode register indirect addressing based indexed based indexed addressing addressing addressing number of bytes 1 2 note 352 note one-byte instruction only when [tde], [whl], [tde+], [tde-], [whl+] or [whl? is written as mem in an mov instruction. (6) number of bytes of instruction that includes saddr, saddrp, r or rp in operands for some instructions that include saddr, saddrp, r or rp in their operands, two ?ytes?entries are given, separated by a slash (??. the entry that applies is shown in the table below. identifier left-hand ?ytes?figure right-hand ?ytes?figure saddr saddr2 saddr1 saddrp saddrp2 saddrp1 rr1 r2 rp rp1 rp2 (7) code of instructions that include mem in operands and string instructions operands tde, whl, vvp and uup (24-bit registers) can also be written as de, hl, vp and up respectively. however, they are still treated as tde, whl, vvp and uup (24-bit registers) when written as de, hl, vp and up. 486 chapter 21 instruction operations user? manual u11515ej3v0ud 21.2 list of operations (1) 8-bit data transfer instruction: mov mnemonic operands bytes operation flags s z ac p/v cy mov r, #byte 2/3 r byte saddr, #byte 3/4 (saddr) byte sfr, #byte 3 sfr byte !addr16, #byte 5 (saddr16) byte !!addr24, #byte 6 (addr24) byte r, r 2/3 r r a, r 1/2 a r a, saddr2 2 a (saddr2) r, saddr 3 r (saddr) saddr2, a 2 (saddr2) a saddr, r 3 (saddr) r a, sfr 2 a sfr r, sfr 3 r sfr sfr, a 2 sfr a sfr, r 3 sfr r saddr, saddr 4 (saddr) (saddr? r, !addr16 4 r (addr16) !addr16, r 4 (addr16) r r, !!addr24 5 r (addr24) !!addr24, r 5 (addr24) r a, [saddrp] 2/3 a ((saddrp)) a, [%saddrg] 3/4 a ((saddrg)) a, mem 1-5 a (mem) [saddrp], a 2/3 ((saddrp)) a [%saddrg], a 3/4 ((saddrg)) a mem, a 1-5 (mem) a pswl, #byte 3 psw l byte pswh, #byte 3 psw h byte pswl, a 2 psw l a pswh, a 2 psw h a a, pswl 2 a psw l a, pswh 2 a psw h r3, #byte 3 r3 byte a, r3 2 a r3 r3, a 2 r3 a 487 chapter 21 instruction operations user? manual u11515ej3v0ud (2) 16-bit data transfer instruction: movw mnemonic operands bytes operation flags s z ac p/v cy movw rp, #word 3 rp word saddrp, #word 4/5 (saddrp) word sfrp, #word 4 sfrp word !addr16, #word 6 (addr16) word !!addr24, #word 7 (addr24) word rp, rp 2 rp rp ax, saddrp2 2 ax (saddrp2) rp, saddrp 3 rp (saddrp) saddrp2, ax 2 (saddrp2) ax saddrp, rp 3 (saddrp) rp ax, sfrp 2 ax sfrp rp, sfrp 3 rp sfrp sfrp, ax 2 sfrp ax sfrp, rp 3 sfrp rp saddrp, saddrp 4 (saddrp) (saddrp? rp, !addr16 4 rp (addr16) !addr16, rp 4 (addr16) rp rp, !!addr24 5 rp (addr24) !!addr24, rp 5 (addr24) rp ax, [saddrp] 3/4 ax ((saddrp)) ax, [%saddrg] 3/4 ax ((saddrg)) ax, mem 2-5 ax (mem) [saddrp], ax 3/4 ((saddrp)) ax [%saddrg], ax 3/4 ((saddrg)) ax mem, ax 2-5 (mem) ax 488 chapter 21 instruction operations user? manual u11515ej3v0ud (3) 24-bit data transfer instruction: movg mnemonic operands bytes operation flags s z ac p/v cy movg rg, #imm24 5 rg imm24 rg, rg 2 rg rg rg, !!addr24 5 rg (addr24) !!addr24, rg 5 (addr24) rg rg, saddrg 3 rg (saddrg) saddrg, rg 3 (saddrg) rg whl, [%saddrg] 3/4 whl ((saddrg)) [%saddrg], whl 3/4 ((saddrg)) whl whl, mem1 2-5 whl (mem1) mem1, whl 2-5 (mem1) whl (4) 8-bit data exchange instruction: xch mnemonic operands bytes operation flags s z ac p/v cy xch r, r 2/3 r ? r a, r 1/2 a ? r a, saddr2 2 a ? (saddr2) r, saddr 3 r ? (saddr) r, sfr 3 r ? sfr saddr, saddr 4 (saddr) ? (saddr? r, !addr16 4 r ? (addr16) r, !!addr24 5 r ? (addr24) a, [saddrp] 2/3 a ? ((saddrp)) a, [%saddrg] 3/4 a ? ((saddrg)) a, mem 2-5 a ? (mem) 489 chapter 21 instruction operations user? manual u11515ej3v0ud (5) 16-bit data exchange instruction: xchw mnemonic operands bytes operation flags s z ac p/v cy xchw rp, rp 2 rp ? rp ax, saddrp2 2 ax ? (saddrp2) rp, saddrp 3 rp ? (saddrp) rp, sfrp 3 rp ? sfrp ax, [saddrp] 3/4 ax ? ((saddrp)) ax, [%saddrg] 3/4 ax ? ((saddrg)) ax, !addr16 4 ax ? (addr16) ax, !!addr24 5 ax ? (addr24) saddrp, saddrp 4 (saddrp) ? (saddrp? ax, mem 2-5 ax ? (mem) (6) 8-bit operation instructions: add, addc, sub, subc, cmp, and, or, xor mnemonic operands bytes operation flags s z ac p/v cy add a, #byte 2 a, cy a + byte v r, #byte 3 r, cy r + byte v saddr, #byte 3/4 (saddr), cy (saddr) + byte v sfr, #byte 4 sfr, cy sfr + byte v r, r 2/3 r, cy r + r v a, saddr2 2 a, cy a + (saddr2) v r, saddr 3 r, cy r + (saddr) v saddr, r 3 (saddr), cy (saddr) + r v r, sfr 3 r, cy r + sfr v sfr, r 3 sfr, cy sfr + r v saddr, saddr 4 (saddr), cy (saddr) + (saddr? v a, [saddrp] 3/4 a, cy a + ((saddrp)) v a, [%saddrg] 3/4 a, cy a + ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a v a, !addr16 4 a, cy a + (addr16) v a, !!addr24 5 a, cy a + (addr24) v !addr16, a 4 (addr16), cy (addr16) + a v !!addr24, a 5 (addr24), cy (addr24) + a v a, mem 2-5 a, cy a + (mem) v mem, a 2-5 (mem), cy (mem) + a v 490 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy addc a, #byte 2 a, cy a + byte + cy v r, #byte 3 r, cy r + byte + cy v saddr, #byte 3/4 (saddr), cy (saddr) + byte + cy v sfr, #byte 4 sfr, cy sfr + byte + cy v r, r 2/3 r, cy r + r?+ cy v a, saddr2 2 a, cy a + (saddr2) + cy v r, saddr 3 r, cy r + (saddr) + cy v saddr, r 3 (saddr), cy (saddr) + r + cy v r, sfr 3 r, cy r + sfr + cy v sfr, r 3 sfr, cy sfr + r + cy v saddr, saddr 4 (saddr), cy (saddr) + (saddr? + cy v a, [saddrp] 3/4 a, cy a + ((saddrp)) + cy v a, [%saddrg] 3/4 a, cy a + ((saddrg)) + cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a + cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a + cy v a, !addr16 4 a, cy a + (addr16) + cy v a, !!addr24 5 a, cy a + (addr24) + cy v !addr16, a 4 (addr16), cy (addr16) + a + cy v !!addr24, a 5 (addr24), cy (addr24) + a + cy v a, mem 2-5 a, cy a + (mem) + cy v mem, a 2-5 (mem), cy (mem) + a + cy v 491 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy sub a, #byte 2 a, cy a ?byte v r, #byte 3 r, cy r ?byte v saddr, #byte 3/4 (saddr), cy (saddr) ?byte v sfr, #byte 4 sfr, cy sfr ?byte v r, r 2/3 r, cy r r v a, saddr2 2 a, cy a (saddr2) v r, saddr 3 r, cy r (saddr) v saddr, r 3 (saddr), cy (saddr) ?r v r, sfr 3 r, cy r sfr v sfr, r 3 sfr, cy sfr ?r v saddr, saddr 4 (saddr), cy (saddr) ?(saddr? v a, [saddrp] 3/4 a, cy a ?((saddrp)) v a, [%saddrg] 3/4 a, cy a ?((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) ?a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) ?a v a, !addr16 4 a, cy a ?(addr16) v a, !!addr24 5 a, cy a ?(addr24) v !addr16, a 4 (addr16), cy (addr16) ?a v !!addr24, a 5 (addr24), cy (addr24) ?a v a, mem 2-5 a, cy a ?(mem) v mem, a 2-5 (mem), cy (mem) a v 492 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy subc a, #byte 2 a, cy a ?byte ?cy v r, #byte 3 r, cy r ?byte ?cy v saddr, #byte 3/4 (saddr), cy (saddr) ?byte ?cy v sfr, #byte 4 sfr, cy sfr ?byte ?cy v r, r 2/3 r, cy r r??cy v a, saddr2 2 a, cy a (saddr2) ?cy v r, saddr 3 r, cy r (saddr) ?cy v saddr, r 3 (saddr), cy (saddr) ?r ?cy v r, sfr 3 r, cy r sfr ?cy v sfr, r 3 sfr, cy sfr ?r ?cy v saddr, saddr 4 (saddr), cy (saddr) ?(saddr? ?cy v a, [saddrp] 3/4 a, cy a ?((saddrp)) ?cy v a, [%saddrg] 3/4 a, cy a ?((saddrg)) ?cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) ?a ?cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) ?a ?cy v a, !addr16 4 a, cy a ?(addr16) ?cy v a, !!addr24 5 a, cy a ?(addr24) ?cy v !addr16, a 4 (addr16), cy (addr16) ?a ?cy v !!addr24, a 5 (addr24), cy (addr24) ?a ?cy v a, mem 2-5 a, cy a ?(mem) ?cy v mem, a 2-5 (mem), cy (mem) ?a ?cy v 493 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy cmp a, #byte 2 a ?byte v r, #byte 3 r ?byte v saddr, #byte 3/4 (saddr) ?byte v sfr, #byte 4 sfr ?byte v r, r 2/3 r r v a, saddr2 2 a ?(saddr2) v r, saddr 3 r (saddr) v saddr, r 3 (saddr) ?r v r, sfr 3 r sfr v sfr, r 3 sfr r v saddr, saddr 4 (saddr) ?(saddr? v a, [saddrp] 3/4 a ?((saddrp)) v a, [%saddrg] 3/4 a ?((saddrg)) v [saddrp], a 3/4 ((saddrp)) a v [%saddrg], a 3/4 ((saddrg)) a v a, !addr16 4 a ?(addr16) v a, !!addr24 5 a ?(addr24) v !addr16, a 4 (addr16) ?a v !!addr24, a 5 (addr24) ?a v a, mem 2-5 a ?(mem) v mem, a 2-5 (mem) a v 494 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy and a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr? p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p 495 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy or a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr? p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p 496 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy xor a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr? p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p 497 chapter 21 instruction operations user? manual u11515ej3v0ud (7) 16-bit operation instructions: addw, subw, cmpw mnemonic operands bytes operation flags s z ac p/v cy addw ax, #word 3 ax, cy ax + word v rp, #word 4 rp, cy rp + word v rp, rp 2 rp, cy rp + rp v ax, saddrp2 2 ax, cy ax + (saddrp2) v rp, saddrp 3 rp, cy rp + (saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) + rp v rp, sfrp 3 rp, cy rp + sfrp v sfrp, rp 3 sfrp, cy sfrp + rp v saddrp, #word 4/5 (saddrp), cy (saddrp) + word v sfrp, #word 5 sfrp, cy sfrp + word v saddrp, saddrp 4 (saddrp), cy (saddrp) + (saddrp? v subw ax, #word 3 ax, cy ax ?word v rp, #word 4 rp, cy rp ?word v rp, rp 2 rp, cy rp rp v ax, saddrp2 2 ax, cy ax ?(saddrp2) v rp, saddrp 3 rp, cy rp (saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) ?rp v rp, sfrp 3 rp, cy rp sfrp v sfrp, rp 3 sfrp, cy sfrp ?rp v saddrp, #word 4/5 (saddrp), cy (saddrp) ?word v sfrp, #word 5 sfrp, cy sfrp ?word v saddrp, saddrp 4 (saddrp), cy (saddrp) ?(saddrp? v cmpw ax, #word 3 ax ?word v rp, #word 4 rp ?word v rp, rp 2 rp rp v ax, saddrp2 2 ax ?(saddrp2) v rp, saddrp 3 rp (saddrp) v saddrp, rp 3 (saddrp) ?rp v rp, sfrp 3 rp sfrp v sfrp, rp 3 sfrp ?rp v saddrp, #word 4/5 (saddrp) ?word v sfrp, #word 5 sfrp ?word v saddrp, saddrp 4 (saddrp) ?(saddrp? v 498 chapter 21 instruction operations user? manual u11515ej3v0ud (8) 24-bit operation instructions: addg, subg mnemonic operands bytes operation flags s z ac p/v cy addg rg, rg 2 rg, cy rg + rg v rg, # imm24 5 rg, cy rg + # imm24 v whl, saddrg 3 whl, cy whl + (saddrg) v subg rg, rg 2 rg, cy rg rg v rg, # imm24 5 rg, cy rg imm24 v whl, saddrg 3 whl, cy whl (saddrg) v (9) multiplication instructions: mulu, muluw, mulw, divuw, divux mnemonic operands bytes operation flags s z ac p/v cy mulu r 2/3 ax a r muluw rp 2 ax (upper half), rp (lower half) ax rp mulw rp 2 ax (upper half), rp (lower half) ax rp divuw r 2/3 ax (quotient), r (remainder) ax r note 1 divux rp 2 axde (quotient), rp (remainder) axde rp note 2 notes 1. when r = 0, r x, ax ffffh 2. when rp = 0, pr de, axde ffffffffh (10) special operation instructions: macw, macsw, sacw mnemonic operands bytes operation flags s z ac p/v cy macw byte 3 axde (b) (c) + axde, b b + 2, v c c + 2, byte byte ?1 end if(byte = 0 or p/v = 1) macsw byte 3 axde (b) (c) + axde, b b + 2, v c c + 2, byte byte ?1 if byte = 0 then end if p/v = 1 then if overflow axde 7fffffffh, end if underflow axde 80000000h, end sacw [tde + ], [whl + ] 4 ax |(tde) ?(whl)| + ax, v tde tde + 2, whl whl + 2 c c ?1 end if(c = 0 or cy = 1) 499 chapter 21 instruction operations user? manual u11515ej3v0ud (11) increment/decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operands bytes operation flags s z ac p/v cy inc r 1/2 r r + 1 v saddr 2/3 (saddr) (saddr) + 1 v dec r 1/2 r r ? v saddr 2/3 (saddr) (saddr) ?1 v incw rp 2/1 rp rp + 1 saddrp 3/4 (saddrp) (saddrp) + 1 decw rp 2/1 rp rp 1 saddrp 3/4 (saddrp) (saddrp) ?1 incg rg 2 rg rg + 1 decg rg 2 rg rg 1 (12) adjustment instructions: adjba, adjbs, cvtbw mnemonic operands bytes operation flags s z ac p/v cy adjba 2 decimal adjust accumulator after addition p adjbs 2 decimal adjust accumulator after subtract p cvtbw 1 x a, a 00h if a 7 = 0 x a, a ffh if a 7 = 1 500 chapter 21 instruction operations user? manual u11515ej3v0ud (13) shift/rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operands bytes operation flags s z ac p/v cy ror r, n 2/3 (cy, r7 r0 , rm ?1 rm ) n times n = 0 ?7 p rol r, n 2/3 (cy, r0 r7 , rm + 1 rm ) n times n = 0 ?7 p rorc r, n 2/3 (cy r0 , r7 cy, rm ?1 rm ) n times n = 0 ?7 p rolc r, n 2/3 (cy r7 , r0 cy, rm + 1 rm ) n times n = 0 ?7 p shr r, n 2/3 (cy r0 , r7 0, rm ?1 rm ) n times n = 0 ?7 0p shl r, n 2/3 (cy r7 , r0 0, rm + 1 rm ) n times n = 0 ?7 0p shrw rp, n 2 (cy rp0 , rp15 0, rpm ?1 rpm) n times 0p n = 0 ?7 shlw rp, n 2 (cy rp15 , rp0 0, rpm + 1 rpm) n times 0p n = 0 ?7 ror4 mem3 2 a 3 ?0 (mem3) 3 ?0 , (mem3) 7 ?4 a 3 ?0 , (mem3) 3 ?0 (mem3) 7 ?4 rol4 mem3 2 a 3 ?0 (mem3) 7 ?4 , (mem3) 3 ?0 a 3 ?0 , (mem3) 7 ?4 (mem3) 3 ?0 (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 mnemonic operands bytes operation flags s z ac p/v cy mov1 cy, saddr. bit 3/4 cy (saddr. bit) cy, sfr. bit 3 cy sfr. bit cy, x. bit 2 cy x. bit cy, a. bit 2 cy a. bit cy, pswl. bit 2 cy pswl. bit cy, pswh. bit 2 cy pswh. bit cy, !addr16. bit 5 cy !addr16.bit cy, !!addr24. bit 2 cy !!addr24. bit cy, mem2. bit 2 cy mem2. bit saddr. bit, cy 3/4 (saddr. bit) cy sfr. bit, cy 3 sfr. bit cy x. bit, cy 2 x.bit cy a. bit, cy 2 a. bit cy pswl. bit, cy 2 pswl. bit cy pswh. bit, cy 2 pswh. bit cy !addr16. bit, cy 5 !addr16.bit cy !!addr24.bit, cy 6 !!addr24.bit cy mem2. bit, cy 2 mem2. bit cy 501 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy and1 cy, saddr. bit 3/4 cy cy (saddr. bit) cy, /saddr. bit 3/4 cy cy (saddr. bit) cy, sfr. bit 3 cy cy sfr. bit cy, /sfr. bit 3 cy cy sfr. bit cy, x. bit 2 cy cy x. bit cy, /x. bit 2 cy cy x. bit cy, a. bit 2 cy cy a. bit cy, /a. bit 2 cy cy a. bit cy, pswl. bit 2 cy cy psw l . bit cy, /pswl. bit 2 cy cy psw l . bit cy, pswh. bit 2 cy cy psw h . bit cy, /pswh. bit 2 cy cy psw h . bit cy, !addr16. bit 5 cy cy !addr16. bit cy, /!addr16. bit 5 cy cy !addr16. bit cy, !!addr24. bit 2 cy cy !!addr24. bit cy, /!!addr24. bit 6 cy cy !!addr24. bit cy, mem2. bit 2 cy cy mem2. bit cy, /mem2. bit 2 cy cy mem2. bit or1 cy, saddr. bit 3/4 cy cy (saddr. bit) cy, /saddr. bit 3/4 cy cy (saddr. bit) cy, sfr. bit 3 cy cy sfr. bit cy, /sfr. bit 3 cy cy sfr. bit cy, x. bit 2 cy cy x. bit cy, /x. bit 2 cy cy x. bit cy, a. bit 2 cy cy a. bit cy, /a. bit 2 cy cy a. bit cy, pswl. bit 2 cy cy psw l . bit cy, /pswl. bit 2 cy cy psw l . bit cy, pswh. bit 2 cy cy psw h . bit cy, /pswh. bit 2 cy cy psw h . bit cy, !addr16. bit 5 cy cy !addr16. bit cy, /!addr16. bit 5 cy cy !addr16. bit cy, !!addr24. bit 2 cy cy !!addr24. bit cy, /!!addr24. bit 6 cy cy !!addr24. bit cy, mem2. bit 2 cy cy mem2. bit cy, /mem2. bit 2 cy cy mem2. bit 502 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy xor1 cy, saddr. bit 3/4 cy cy (saddr. bit) cy, sfr. bit 3 cy cy sfr. bit cy, x. bit 2 cy cy x. bit cy, a. bit 2 cy cy a. bit cy, pswl. bit 2 cy cy pswl. bit cy, pswh. bit 2 cy cy pswh. bit cy, !addr16. bit 5 cy cy !addr16. bit cy, !!addr24. bit 2 cy cy !!addr24. bit cy, mem2. bit 2 cy cy mem2. bit not1 saddr. bit 3/4 (saddr. bit) (saddr. bit) sfr. bit 3 sfr. bit sfr. bit x. bit 2 x. bit x. bit a. bit 2 a. bit a. bit pswl. bit 2 pswl. bit psw l . bit pswh. bit 2 pswh. bit psw h . bit !addr16. bit 5 !addr16. bit !addr16. bit !!addr24. bit 2 !!addr24. bit !!addr24. bit mem2. bit 2 mem2. bit mem2. bit cy 1 cy cy set1 saddr. bit 2/3 (saddr. bit) 1 sfr. bit 3 sfr. bit 1 x. bit 2 x. bit 1 a. bit 2 a. bit 1 pswl. bit 2 pswl. bit 1 pswh. bit 2 pswh. bit 1 !addr16. bit 5 !addr16. bit 1 !!addr24. bit 2 !!addr24. bit 1 mem2. bit 2 mem2. bit 1 cy 1 cy 11 clr1 saddr. bit 2/3 (saddr. bit) 0 sfr. bit 3 sfr. bit 0 x. bit 2 x. bit 0 a. bit 2 a. bit 0 pswl. bit 2 pswl. bit 0 pswh. bit 2 pswh. bit 0 !addr16. bit 5 !addr16. bit 0 !!addr24. bit 2 !!addr24. bit 0 mem2. bit 2 mem2. bit 0 cy 1 cy 00 503 chapter 21 instruction operations user? manual u11515ej3v0ud (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operands bytes operation flags s z ac p/v cy push psw 1 (sp ?2) psw, sp sp ?2 sfrp 3 (sp ?2) sfrp, sp sp ?2 sfr 3 (sp ?1) sfr, sp sp ?1 post 2 {(sp ?2) post, sp sp ?2} m times note rg 2 (sp ?3) rg, sp sp ?3 pushu post 2 {(uup ?2) post, uup uup ?2} m times note pop psw 1 psw (sp), sp sp + 2 rrrrr sfrp 3 sfrp (sp), sp sp + 2 sfr 3 sfr (sp), sp sp + 1 post 2 {post (sp), sp sp + 2} m times note rg 2 rg (sp), sp sp + 3 popu post 2 {post (uup), uup uup + 2} m times note movg sp, # imm24 5 sp imm24 sp, whl 2 sp whl whl, sp 2 whl sp addwg sp, #word 4 sp sp + word subwg sp, #word 4 sp sp ?word incg sp 2 sp sp + 1 decg sp 2 sp sp ?1 note m = number of registers specified by ?ost 504 chapter 21 instruction operations user? manual u11515ej3v0ud (16) call/return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operands bytes operation flags s z ac p/v cy call !addr16 3 (sp ?3) (pc + 3), sp sp ?3, pc hw 0, pc lw addr16 !!addr20 4 (sp ?3) (pc + 4), sp sp ?3, pc addr20 rp 2 (sp ?3) (pc + 2), sp sp ?3, pc hw 0, pc lw rp rg 2 (sp ?3) (pc + 2), sp sp ?3, pc rg [rp] 2 (sp ?3) (pc + 2), sp sp ?3, pc hw 0, pc lw (rp) [rg] 2 (sp ?3) (pc + 2), sp sp ?3, pc (rg) $!addr20 3 (sp ?3) (pc + 3), sp sp ?3, pc pc + 3 + jdisp16 callf !addr11 2 (sp ?3) (pc + 2), sp sp ?3, pc 19 ?12 0, pc11 1, pc 10 ?0 addr11 callt [addr5] 1 (sp ?3) (pc + 1), sp sp ?3, pc hw 0, pc lw (addr5) brk 1 (sp ?2) psw, (sp ?1) 0 ?3 (pc + 1) hw , (sp ?4) (pc + 1) lw , sp sp ?4 pc hw 0, pc lw (003eh) brkcs rbn 2 pc lw rp2, rp3 psw, rbs2 ?0 n, rss 0, ie 0, rp3 8 ?11 pc hw , pc hw 0 ret 1 pc (sp), sp sp + 3 ret1 1 pc lw (sp), pc hw (sp + 3) 0 ?3 , rrrrr psw (sp + 2), sp sp + 4 clears to 0 flag with highest priority of flags of ispr that are set (1) retb 1 pc lw (sp), pc hw (sp + 3) 0 ?3 , rrrrr psw (sp + 2), sp sp + 4 retcs !addr16 3 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8 ?11 clears to 0 flag with highest priority of flags of ispr that are set (1) retcsb !addr16 4 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8 ?11 505 chapter 21 instruction operations user? manual u11515ej3v0ud (17) unconditional branch instruction: br mnemonic operands bytes operation flags s z ac p/v cy br !addr16 3 pc hw 0, pc lw addr16 !!addr20 4 pc addr20 rp 2 pc hw 0, pc lw rp rg 2 pc rg [rp] 2 pc hw 0, pc lw (rp) [rg] 2 pc (rg) $addr20 2 pc pc + 2 + jdisp8 $!addr20 3 pc pc + 3 + jdisp16 506 chapter 21 instruction operations user? manual u11515ej3v0ud (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz mnemonic operands bytes operation flags s z ac p/v cy bnz $addr20 2 pc pc + 2 + jdisp8 if z = 0 bne bz $addr20 2 pc pc + 2 + jdisp8 if z = 1 be bnc $addr20 2 pc pc + 2 + jdisp8 if cy = 0 bnl bc $addr20 2 pc pc + 2 + jdisp8 if cy = 1 bl bnv $addr20 2 pc pc + 2 + jdisp8 if p/v = 0 bpo bv $addr20 2 pc pc + 2 + jdisp8 if p/v = 1 bpe bp $addr20 2 pc pc + 2 + jdisp8 if s = 0 bn $addr20 2 pc pc + 2 + jdisp8 if s = 1 blt $addr20 3 pc pc + 3 + jdisp8 if p/v s = 1 bge $addr20 3 pc pc + 3 + jdisp8 if p/v s = 0 ble $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 1 bgt $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 0 bnh $addr20 3 pc pc + 3 + jdisp8 if z cy = 1 bh $addr20 3 pc pc + 3 + jdisp8 if z cy = 0 bf saddr. bit, $addr20 4/5 pc pc + 4 note + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr20 4 pc pc + 4 + jdisp8 if sfr. bit = 0 x. bit, $addr20 3 pc pc + 3 + jdisp8 if x. bit = 0 a. bit, $addr20 3 pc pc + 3 + jdisp8 if a. bit = 0 pswl. bit, $addr20 3 pc pc + 3 + jdisp8 if psw l . bit = 0 pswh. bit, $addr20 3 pc pc + 3 + jdisp8 if psw h . bit = 0 !addr16. bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16. bit = 0 !!addr24. bit, $addr20 3 pc pc + 3 + jdisp8 if !!addr24. bit = 0 mem2. bit, $addr20 3 pc pc + 3 + jdisp8 if mem2. bit = 0 note when the number of bytes is 4. when 5, the operation is: pc pc + 5 + jdisp8. 507 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy bt saddr. bit, $addr20 3/4 pc pc + 3 note 1 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr20 4 pc pc + 4 + jdisp8 if sfr. bit = 1 x. bit, $addr20 3 pc pc + 3 + jdisp8 if x. bit = 1 a. bit, $addr20 3 pc pc + 3 + jdisp8 if a. bit = 1 pswl. bit, $addr20 3 pc pc + 3 + jdisp8 if psw l . bit = 1 pswh. bit, $addr20 3 pc pc + 3 + jdisp8 if psw h . bit = 1 !addr16. bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16. bit = 1 !!addr24. bit, $addr20 3 pc pc + 3 + jdisp8 if !!addr24. bit = 1 mem2. bit, $addr20 3 pc pc + 3 + jdisp8 if mem2. bit = 1 btclr saddr. bit, $addr20 4/5 {pc pc + 4 note 2 + jdisp8, (saddr. bit) 0} if (saddr. bit) = 1 sfr. bit, $addr20 4 {pc pc + 4 + jdisp8, sfr. bit 0} if sfr. bit = 1 x. bit, $addr20 3 {pc pc + 3 + jdisp8, x. bit 0} if x. bit = 1 a. bit, $addr20 3 {pc pc + 3 + jdisp8, a. bit 0} if a. bit = 1 pswl. bit, $addr20 3 {pc pc + 3 + jdisp8, psw l . bit 0} if psw l . bit = 1 pswh. bit, $addr20 3 {pc pc + 3 + jdisp8, psw h . bit 0} if psw h . bit = 1 !addr16. bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16. bit 0} if !addr16. bit = 1 !!addr24. bit, $addr20 3 {pc pc + 3 + jdisp8, !!addr24. bit 0} if !!addr24. bit = 1 mem2. bit, $addr20 3 {pc pc + 3 + jdisp8, mem2. bit 0} if mem2. bit = 1 notes 1. when the number of bytes is 3. when 4, the operation is: pc pc + 4 + jdisp8. 2. when the number of bytes is 4. when 5, the operation is: pc pc + 5 + jdisp8. 508 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy bfset saddr. bit, $addr20 4/5 {pc pc + 4 note 2 + jdisp8, (saddr. bit) 1} if (saddr. bit) = 0 sfr. bit, $addr20 4 {pc pc + 4 + jdisp8, sfr. bit 1} if sfr. bit = 0 x. bit, $addr20 3 {pc pc + 3 + jdisp8, x. bit 1} if x. bit = 0 a. bit, $addr20 3 {pc pc + 3 + jdisp8, a. bit 1} if a. bit = 0 pswl. bit, $addr20 3 {pc pc + 3 + jdisp8, psw l . bit 1} if psw l . bit = 0 pswh. bit, $addr20 3 {pc pc + 3 + jdisp8, psw h . bit 1} if psw h . bit = 0 !addr16. bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16. bit 1} if !addr16. bit = 0 !!addr24. bit, $addr20 3 {pc pc + 3 + jdisp8, !!addr24. bit 1} if !!addr24. bit = 0 mem2. bit, $addr20 3 {pc pc + 3 + jdisp8, mem2. bit 1} if mem2. bit = 0 dbnz b, $addr20 2 b b ?1, pc pc + 2 + jdisp8 if b 0 c, $addr20 2 c c ?1, pc pc + 2 + jdisp8 if c 0 $addr, $addr20 3/4 (saddr) (saddr) ?1, pc pc + 3 note 1 = jdisp8 if (saddr) 0 notes 1. when the number of bytes is 3. when 4, the operation is: pc pc + 4 + jdisp8. 2. when the number of bytes is 4. when 5, the operation is: pc pc + 5 + jdisp8. (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operands bytes operation flags s z ac p/v cy mov stbc, #byte 4 stbc byte wdm, #byte 4 wdm byte location locaddr 4 sfr, internal data area location address upper word specification sel rbn 2 rss 0, rbs2 ?0 n rbn, alt 2 rss 1, rbs2 ?0 n swrs 2 rss rss nop 1 no operaton ei 1 ie 1 (enable interrupt) di 1 ie 0 (disable interrupt) 509 chapter 21 instruction operations user? manual u11515ej3v0ud (20) special instructions: chkl, chkla mnemonic operands bytes operation flags s z ac p/v cy chkl sfr 3 (pin level) (output latch) p chkla sfr 3 a (pin level) (output latch) p (21) string instructions: movtblw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, cmpbknc mnemonic operands bytes operation flags s z ac p/v cy movtblw !addr8, byte 4 (addr8 + 2) (addr8), byte byte ?1, addr8 addr8 ?2 end if byte = 0 movw [tde + ], a 2 (tde) a, tde tde + 1, c c ?1 end if c = 0 [tde ?], a 2 (tde) a, tde tde ?1, c c ?1 end if c = 0 xchm [tde + ], a 2 (tde) ? a, tde tde + 1, c c ?1 end if c = 0 [tde ?], a 2 (tde) ? a, tde tde ?1, c c ?1 end if c = 0 movbk [tde + ], [whl +] 2 (tde) (whl), tde tde + 1, whl whl + 1, c c ?1 end if c = 0 [tde ?], [whl ? 2 (tde) (whl), tde tde ?1, whl whl ?1, c c ?1 end if c = 0 xchbk [tde + ], [whl +] 2 (tde) ? (whl), tde tde +1, whl whl + 1, c c ?1 end if c = 0 [tde ?], [whl ? 2 (tde) ? (whl), tde tde ?1, whl whl ?1, c c ?1 end if c = 0 cmpme [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or z = 0 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or z = 0 v cmpmne [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or z = 1 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or z = 1 v cmpmc [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or cy = 0 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or cy = 0 v cmpmnc [tde + ], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or cy = 1 v [tde ?], a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or cy = 1 v cmpbke [tde + ], [whl +] 2 (tde) (whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or z = 0 [tde ?], [whl ? 2 (tde) (whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or z = 0 510 chapter 21 instruction operations user? manual u11515ej3v0ud mnemonic operands bytes operation flags s z ac p/v cy cmpbkne [tde + ], [whl +] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or z = 1 [tde ?], [whl ? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or z = 1 cmpbkc [tde + ], [whl +] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or cy = 0 [tde ?], [whl ? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or cy = 0 cmpbknc [tde + ], [whl +] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ?1 end if c = 0 or cy = 1 [tde ?], [whl ? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ?1 end if c = 0 or cy = 1 511 user? manual u11515ej3v0ud [memo] 512 chapter 21 instruction operations user? manual u11515ej3v0ud 21.3 instructions listed by type of addressing (1) 8-bit instructions (combinations expressed by writing a for r are shown in parentheses) mov, xch, add, addc, sub, subc, and or xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 21-1. list of instructions by 8-bit addressing (1/2) 2nd operand r saddr # byte a sfr 1st operand r saddr a (mov) (mov) mov (mov) note 6 mov add note 1 (xch) xch (xch) note 6 (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 r mov (mov) mov mov mov add note 1 (xch) xch xch xch (add) note 1 add note 1 add note 1 add note 1 saddr mov (mov) note 6 mov mov add note 1 (add) note 1 add note 1 xch add note 1 sfr mov mov mov add note 1 (add) note 1 add note 1 !addr16 mov mov mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 r3 mov mov pswl pswh b, c stbc, wdm mov [tde +] (mov) [tde ? (add) note 1 movm note 4 (see the following page for the explanation of note .) 513 chapter 21 instruction operations user? manual u11515ej3v0ud table 21-1. list of instructions by 8-bit addressing (2/2) 2nd operand !addr16 mem r3 [whl +] [saddrp] pswl n none note 2 1st operand !!addr24 [%saddrg] pswh [whl ? a (mov) mov mov (mov) (xch) xch (xch) add note 1 add note 1 (add) note 1 r mov ror note 3 mulu xch divuw inc dec saddr inc dec dbnz sfr push pop chkl chkla !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ror4 rol4 r3 pswl pswh b, c dbnz stbc, wdm [tde +] movbk note 5 [tde ? notes 1. addc, sub, subc, and, or, xor and cmp are the same as add. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. rol, rorc, rolc, shr and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc and cmpbkc are the same as movbk. 6. if saddr is saddr2 in this combination, there is a short code length instruction. 514 chapter 21 instruction operations user? manual u11515ej3v0ud (2) 16-bit instructions (combinations expressed by writing ax for rp are shown in parentheses) movm, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 21-2. list of instructions by 16-bit addressing (1/2) 2nd operand rp saddrp # word ax sfrp 1st operand rp saddrp ax (movw) (movw) (movw) (movw) note 3 movw addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw addw note 1 (xchw) xchw xchw xchw (addw) note 1 addw note 1 addw note 1 addw note 1 saddrp movw (movw) note 3 movw movw addw note 1 (addw) note 1 addw note 1 xchw addw note 1 sfrp movw movw movw addw note 1 (addw) note 1 addw note 1 !addr16 movw (movw) movw !!addr24 mem movw [saddrp] [%saddrg] psw sp addwg subwg post [tde +] (movw) byte (see the following page for the explanation of note .) 515 chapter 21 instruction operations user? manual u11515ej3v0ud table 21-2. list of instructions by 16-bit addressing (2/2) 2nd operand mem !!addr16 [saddrp] [whl +] byte n none note 2 1st operand !!addr24 [%saddrg] ax (movw) movw (movw) xchw xchw (xchw) rp movw shrw mulw note 4 shlw incw decw saddrp incw decw sfrp push pop !addr16 movtblw !!addr24 mem [saddrp] [%saddrg] psw push pop sp post push pop pushu popu [tde +] sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. if saddrp is saddrp2 in this combination, there is a short code length instruction. 4. muluw and divux are the same as mulw. 516 chapter 21 instruction operations user? manual u11515ej3v0ud (3) 24-bit instructions (combinations expressed by writing whl for rg are shown in parentheses) movg, addg, subg, incg, decg, push, pop table 21-3. list of instructions by 24-bit addressing 2nd operand rg # imm24 whl saddrg !!addr24 mem1 [%saddrg] sp none * 1st operand rg whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg) movg sp movg movg incg decg * there is no 2nd operand, or the 2nd operand is not an operand address. (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 21-4. list of instructions by bit manipulation instruction addressing 2nd operand saddr. bit sfr. bit /saddr.bit /sfr. bit a.bit x. bit /a. bit /x. bit cy pswl. bit pswh. bit /pswl. bit /pswh. bit none * mem2. bit /mem2. bit !addr16. bit /!addr16. bit 1st operand !!addr24. bit /!!addr24. bit cy mov1 and1 not and1 or1 set1 or1 clr1 xor1 saddr. bit mov1 not1 sfr. bit set1 a. bit clr1 x. bit bf pswl. bit bt pswh. bit btclr mem2. bit bfset !addr16. bit !!addr24. bit * there is no 2nd operand, or the 2nd operand is not an operand address. 517 chapter 21 instruction operations user? manual u11515ej3v0ud (5) call/return instructions / branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 21-5. list of instructions by call/return instruction / branch instruction addressing instruction address $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none operand basic bc * call call call call call call call callf callt brkcs brk instructions br br br br br br br br ret retcs reti retcsb retb compound bf instructions bt btclr bfset dbnz * bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs 518 user? manual u11515ej3v0ud chapter 22 electrical specifications ( pd784044, 784046) refer to chapter 27 timing charts for the timing charts. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.5 to +7.0 v av dd ?.5 to v dd + 0.5 v av ss ?.5 to +0.5 v input voltage v i note 1 ?.5 to v dd + 0.5 7.0 v output voltage v o ?.5 to v dd + 0.5 v output current, low i ol all output pins 15 ma total of all output pins 150 ma output current, high i oh all output pins ?0 ma total of all output pins ?00 ma analog input voltage v ian note 2 av dd > v dd ?.5 to v dd + 0.5 v v dd av dd ?.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd ?.5 to v dd + 0.5 v input voltage v dd av dd ?.5 to av dd + 0.5 operating ambient t a ?0 to +70 c temperature storage temperature t stg ?5 to +150 c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 32 mhz ?0 to +70 c 4.5 to 5.5 v capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 10 pf i/o capacitance c io 10 pf 519 chapter 22 electrical sepcifications ( pd784044, 784046) user? manual u11515ej3v0ud oscillator characteristics (t a = ?0 to +70 c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 32 mhz crystal resonator external clock x1 input frequency (f x ) 8 32 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to prevent an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter 520 chapter 22 electrical sepcifications ( pd784044, 784046) user? manual u11515ej3v0ud dc characteristics (t a = ?0 to +70 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il 0 0.8 v input voltage, high v ih1 note 1 2.2 v dd v v ih2 note 2 0.8v dd v dd output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, high v oh i oh = ?00 av dd ?1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 1 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 32 mhz) 50 80 ma i dd2 halt mode (f xx = 32 mhz) 30 60 ma i dd3 idle mode (f xx = 32 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 215 a v dddr = 5 v 10% 15 50 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in the note 2 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 used as analog inputs) 4. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 (pins used as analog input, only during the non- sampling operation) 521 chapter 22 electrical sepcifications ( user s manual u11515ej3v0ud ac characteristics (t a = 10 to +70 parameter symbol expression min. max. unit system clock cycle time t cyk 62.5 250 ns address setup time (to astb )t sast (0.5 + a) t 20 11.2 ns address hold time (from astb )t hsta 0.5t 20 11.2 ns astb high-level width t wsth (0.5 + a) t 17 14.2 ns rd delay time from address t dar (1 + a) t 15 47.5 ns address float time from rd t fra 0ns data input time from address t daid (2.5 + a + n) t 56 100.2 ns data input time from rd t drid (1.5 + n) t 48 45.7 ns rd delay time from astb t dstr 0.5t 16 15.3 ns data hold time (to rd )t hrid 0ns address active time from rd t dra 0.5t 14 17.2 ns rd low-level width t wrl (1.5 + n) t 30 63.7 ns lwr, hwr delay time from address t daw (1 + a) t 15 47.5 ns data output time from lwr, hwr t dwod 15 ns lwr, hwr delay time from astb t dstw 0.5t 16 15.3 ns data setup time (to lwr, hwr )t sodw (1.5 + n) t 25 68.7 ns data hold time (from lwr, hwr )t hwod 0.5t 14 17.2 ns astb delay time from lwr, hwr t dwst 1.5t 15 78.8 ns lwr, hwr low-level width t wwl (1.5 + n) t 36 57.7 ns wait input time from address t dawt (2 + a) t 50 75 ns wait input time from astb t dstwt 1.5t 40 53.7 ns wait hold time from astb t hstwt (1.5 + n) t + 5 98.8 ns wait delay time from astb t dstwth (2.5 + n) t 40 116.2 note ns wait input time from rd t drwt t 40 22.5 ns wait hold time from rd t hrwt (1 + n) t + 5 67.5 ns wait delay time from rd t drwth (1 + n) t 40 85 note ns wait input time from lwr, hwr t dwwt t 40 22.5 ns wait hold time from lwr, hwr t hwwt (1 + n) t + 5 67.5 ns wait delay time from lwr, hwr t dwwth (1 + n) t 40 85 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 62.5 ns. 522 chapter 22 electrical sepcifications ( user s manual u11515ej3v0ud (2) serial operation (t a = 10 to +70 parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 500 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 210 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 210 ns si1, si2 setup time t sssk 80 ns (to sck1, sck2 ) si1, si2 hold time t hssk 80 ns (from sck1, sck2 ) so1, so2 output t dsbsk r = 1 k ? , c = 100 pf 0 150 ns delay time from sck1, sck2 t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) (3) other operations (t a = 10 to +70 parameter symbol conditions min. max. unit nmi high-, low-level width t wnih , t wnil 10 s intp0 to intp6 high-, low-level width t with , t witl 4t cysmp ti2, ti3 high-, low-level width t wtih , t wtil 4t cysmp reset high-, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0 to 6) 523 chapter 22 electrical sepcifications ( pd784044, 784046) user? manual u11515ej3v0ud a/d converter characteristics (t a = ?0 to +70 c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd ?0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v av ref av dd 0.5 %fsr note 2 3.4 v av ref < 4.5 v 0.7 %fsr note 2 quantization error 1/2 lsb conversion time t conv 80 ns t cyk 250 ns 169 t cyk 62.5 ns t cyk < 80 ns 208 t cyk sampling time t samp 80 ns t cyk 250 ns 20 t cyk 62.5 ns t cyk < 80 ns 24 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb integral linearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian ?.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 1.0 3.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 10 a current mode av dddr = 5 v 10% 10 50 a notes 1. the quantization error is excluded. 2. indicated as a ratio (%fsr) to the full-scale value. remark t cyk = 1/f clk (f clk is internal system clock frequency). 524 user? manual u11515ej3v0ud chapter 23 electrical specifications ( pd784044(a), 784046(a)) refer to chapter 27 timing charts for the timing charts. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.5 to +7.0 v av dd ?.5 to v dd + 0.5 v av ss ?.5 to +0.5 v input voltage v i note 1 ?.5 to v dd + 0.5 7.0 v output voltage v o ?.5 to v dd + 0.5 v output current, low i ol all output pins 15 ma total of all output pins 150 ma output current, high i oh all output pins ?0 ma total of all output pins ?00 ma analog input voltage v ian note 2 av dd > v dd ?.5 to v dd + 0.5 v v dd av dd ?.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd ?.5 to v dd + 0.5 v input voltage v dd av dd ?.5 to av dd + 0.5 operating temperature t a ?0 to +85 c storage temperature t stg ?5 to +150 c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 25 mhz ?0 to +85 c 4.5 to 5.5 v capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 10 pf i/o capacitance c io 10 pf 525 chapter 23 electrical specifications ( pd784044(a), 784046(a)) user? manual u11515ej3v0ud oscillator characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 25 mhz crystal resonator external clock x1 input frequency (f x ) 8 25 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to prevent an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter 526 chapter 23 electrical specifications ( pd784044(a), 784046(a)) user s manual u11515ej3v0ud dc characteristics (t a = 40 to +85 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il 0 0.8 v input voltage, high v ih1 note 1 2.2 v dd v v ih2 note 2 0.8v dd v dd output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, high v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 1 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 25 mhz) 40 70 ma i dd2 halt mode (f xx = 25 mhz) 25 50 ma i dd3 idle mode (f xx = 25 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 215 a v dddr = 5 v 10 % 15 50 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in note 2 . 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 used as analog inputs) 4. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 (pins used as analog input, only during the non- sampling operation) 527 chapter 23 electrical specifications ( pd784044(a), 784046(a)) user? manual u11515ej3v0ud ac characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v, v ss = 0 v) (1) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 80 250 ns address setup time (to astb )t sast (0.5 + a) t ?20 20 ns address hold time (from astb )t hsta 0.5t ?20 20 ns astb high-level width t wsth (0.5 + a) t ?17 23 ns rd delay time from address t dar (1 + a) t ?15 65 ns address float time from rd t fra 0ns data input time from address t daid (2.5 + a + n) t ?56 144 ns data input time from rd t drid (1.5 + n) t ?48 72 ns rd delay time from astb t dstr 0.5t ?16 24 ns data hold time (to rd )t hrid 0ns address active time from rd t dra 0.5t ?14 26 ns rd low-level width t wrl (1.5 + n) t ?30 90 ns lwr, hwr delay time from address t daw (1 + a) t ?15 65 ns data output time from lwr, hwr t dwod 15 ns lwr, hwr delay time from astb t dstw 0.5t ?16 24 ns data setup time (to lwr, hwr )t sodw (1.5 + n) t ?25 95 ns data hold time (from lwr, hwr )t hwod 0.5t ?14 26 ns astb delay time from lwr, hwr t dwst 1.5t ?15 105 ns lwr, hwr low-level width t wwl (1.5 + n) t ?36 84 ns wait input time from address t dawt (2 + a) t ?50 110 ns wait input time from astb t dstwt 1.5t ?40 80 ns wait hold time from astb t hstwt (1.5 + n) t + 5 125 ns wait delay time from astb t dstwth (1.5 + n) t ?40 160 note ns wait input time from rd t drwt t ?40 40 ns wait hold time from rd t hrwt (1 + n) t + 5 85 ns wait delay time from rd t drwth (1 + n) t ?40 120 note ns wait input time from lwr, hwr t dwwt t ?40 40 ns wait hold time from lwr, hwr t hwwt (1 + n) t + 5 85 ns wait delay time from lwr, hwr t dwwth (1 + n) t ?40 120 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 80 ns. 528 chapter 23 electrical specifications ( pd784044(a), 784046(a)) user s manual u11515ej3v0ud (2) serial operation (t a = 40 to +85 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 640 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 280 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 280 ns si1, si2 setup time t sssk 80 ns (to sck1, sck2 ) si1, si2 hold time t hssk 80 ns (from sck1, sck2 ) so1, so2 output delay time t dsbsk r = 1 k ? , c = 100 pf 0 150 ns from sck1, sck2 remarks 1. t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) (3) other operations (t a = 40 to +85 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high, low-level width t wnih , t wnil 10 s intp0-intp6 high, low-level width t with , t witl 4t cysmp ti2, ti3 high, low-level width t wtih , t wtil 4t cysmp reset high, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0-6) 529 chapter 23 electrical specifications ( pd784044(a), 784046(a)) user? manual u11515ej3v0ud a/d converter characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd ?0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v av ref av dd 0.5 %fsr note 2 3.4 v av ref < 4.5 v 0.7 %fsr note 2 quantization error 1/2 lsb conversion time t conv 80 ns t cyk 250 ns 169 t cyk sampling time t samp 80 ns t cyk 250 ns 20 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb integral linearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian ?.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 1.0 3.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 10 a current mode av dddr = 5 v 10% 10 50 a notes 1. the quantization error is excluded. 2. indicated as a ratio (%fsr) to the full-scale value. remark t cyk = 1/f clk (f clk is internal system clock frequency). 530 user? manual u11515ej3v0ud chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) refer to chapter 27 timing charts for the timing charts. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.5 to +7.0 v av dd ?.5 to v dd + 0.5 v av ss ?.5 to +0.5 v input voltage v i note 1 ?.5 to v dd + 0.5 7.0 v output voltage v o ?.5 to v dd + 0.5 v output current, low i ol all output pins 15 ma total of all output pins 150 ma output current, high i oh all output pins ?0 ma total of all output pins ?00 ma analog input voltage v ian note 2 av dd > v dd ?.5 to v dd + 0.5 v v dd av dd ?.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd ?.5 to v dd + 0.5 v input voltage v dd av dd ?.5 to av dd + 0.5 operating temperature t a ?0 to +110 c storage temperature t stg ?5 to +150 c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 20 mhz ?0 to +110 c 4.5 to 5.5 v capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 10 pf i/o capacitance c io 10 pf 531 chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) user? manual u11515ej3v0ud oscillator characteristics (t a = ?0 to +110 c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 20 mhz crystal resonator external clock x1 input frequency (f x ) 8 20 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to prevent an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter 532 chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) user s manual u11515ej3v0ud dc characteristics (t a = 40 to +110 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il 0 0.8 v input voltage, high v ih1 note 1 2.2 v dd v v ih2 note 2 0.8v dd v dd output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, high v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 2 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 20 mhz) 30 60 ma i dd2 halt mode (f xx = 20 mhz) 15 30 ma i dd3 idle mode (f xx = 20 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 2 100 a v dddr = 5 v 10 % 15 1000 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in note 2 . 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 used as analog inputs) 4. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 (pins used as analog input, only during the non- sampling operation) 533 chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) user? manual u11515ej3v0ud ac characteristics (t a = ?0 to +110 c, v dd = 4.5 to 5.5 v, v ss = 0 v) (1) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 100 250 ns address setup time (to astb )t sast (0.5 + a) t ?20 30 ns address hold time (from astb )t hsta 0.5t ?20 30 ns astb high-level width t wsth (0.5 + a) t ?17 33 ns rd delay time from address t dar (1 + a) t ?15 85 ns address float time from rd t fra 0ns data input time from address t daid (2.5 + a + n) t ?56 194 ns data input time from rd t drid (1.5 + n) t ?53 97 ns rd delay time from astb t dstr 0.5t ?16 34 ns data hold time (to rd )t hrid 0ns address active time from rd t dra 0.5t ?14 36 ns rd low-level width t wrl (1.5 + n) t ?30 120 ns lwr, hwr delay time from address t daw (1 + a) t ?15 85 ns data output time from lwr, hwr t dwod 15 ns lwr, hwr delay time from astb t dstw 0.5t ?16 34 ns data setup time (to lwr, hwr )t sodw (1.5 + n) t ?25 125 ns data hold time (from lwr, hwr )t hwod 0.5t ?14 36 ns astb delay time from lwr, hwr t dwst 1.5t ?15 135 ns lwr, hwr low-level width t wwl (1.5 + n) t ?36 114 ns wait input time from address t dawt (2 + a) t ?50 150 ns wait input time from astb t dstwt 1.5t ?40 110 ns wait hold time from astb t hstwt (1.5 + n) t + 5 155 ns wait delay time from astb t dstwth (1.5 + n) t ?40 210 note ns wait input time from rd t drwt t ?40 60 ns wait hold time rd t hrwt (1 + n) t + 5 105 ns wait delay time from rd t drwth (1 + n) t ?40 160 note ns wait input time from lwr, hwr t dwwt t ?40 60 ns wait hold time from lwr, hwr t hwwt (1 + n) t + 5 105 ns wait delay time from lwr, hwr t dwwth (1 + n) t ?40 160 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 100 ns. 534 chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) user s manual u11515ej3v0ud (2) serial operation (t a = 40 to +110 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 800 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns si1, si2 setup time t sssk 80 ns (to sck1, sck2 ) si1, si2 hold time t hssk 80 ns (from sck1, sck2 ) so1, so2 output delay time t dsbsk r = 1 k ? , c = 100 pf 0 150 ns from sck1, sck2 remarks 1. t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) (3) other operations (t a = 40 to +110 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high, low-level width t wnih , t wnil 10 s intp0-intp6 high, low-level width t with , t witl 4t cysmp ti2, ti3 high, low-level width t wtih , t wtil 4t cysmp reset high, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0-6) 535 chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) user? manual u11515ej3v0ud a/d converter characteristics (t a = ?0 to +110 c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd ?0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v av ref av dd 0.5 %fsr note 2 3.4 v av ref < 4.5 v 0.7 %fsr note 2 quantization error 1/2 lsb conversion time t conv 169 t cyk sampling time t samp 20 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb integral linearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian ?.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 3.0 4.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 100 a current mode av dddr = 5 v 10% 10 1000 a notes 1. the quantization error is excluded. 2. indicated as a ratio (%fsr) to the full-scale value. remark t cyk = 1/f clk (f clk is internal system clock frequency). 536 user? manual u11515ej3v0ud chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) refer to chapter 27 timing charts for the timing charts. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.5 to +7.0 v av dd ?.5 to v dd + 0.5 v av ss ?.5 to +0.5 v input voltage v i note 1 ?.5 to v dd + 0.5 7.0 v output voltage v o ?.5 to v dd + 0.5 v output current, low i ol all output pins 15 ma total of all output pins 150 ma output current, low i oh all output pins ?0 ma total of all output pins ?00 ma analog input voltage v ian note 2 av dd > v dd ?.5 to v dd + 0.5 v v dd av dd ?.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd ?.5 to v dd + 0.5 v input voltage v dd av dd ?.5 to av dd + 0.5 operating temperature t a ?0 to +125 c storage temperature t stg ?5 to +150 c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 20 mhz ?0 to +125 c 4.5 to 5.5 v capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 10 pf i/o capacitance c io 10 pf 537 chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) user? manual u11515ej3v0ud oscillator characteristics (t a = ?0 to +125 c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 20 mhz crystal resonator external clock x1 input frequency (f x ) 8 20 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to prevent an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter 538 chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) user s manual u11515ej3v0ud dc characteristics (t a = 40 to +125 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il 0 0.8 v input voltage, high v ih1 note 1 2.2 v dd v v ih2 note 2 0.8v dd v dd output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, high v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 2 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 20 mhz) 30 60 ma i dd2 halt mode (f xx = 20 mhz) 15 30 ma i dd3 idle mode (f xx = 20 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 2 100 a v dddr = 5 v 10 % 15 1000 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in note 2 . 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 used as analog inputs) 4. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 (pins used as analog input, only during the non- sampling operation) 539 chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) user s manual u11515ej3v0ud ac characteristics (t a = 40 to +125 c, v dd = 4.5 to 5.5 v, v ss = 0 v) (1) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 100 250 ns address setup time (to astb )t sast (0.5 + a) t 20 30 ns address hold time (from astb )t hsta 0.5t 20 30 ns astb high-level width t wsth (0.5 + a) t 17 33 ns rd delay time from address t dar (1 + a) t 15 85 ns address float time from rd t fra 0ns data input time from address t daid (2.5 + a + n) t 56 194 ns data input time from rd t drid (1.5 + n) t 53 97 ns rd delay time from astb t dstr 0.5t 16 34 ns data hold time (to rd )t hrid 0ns address active time from rd t dra 0.5t 14 36 ns rd low-level width t wrl (1.5 + n) t 30 120 ns lwr, hwr delay time from address t daw (1 + a) t 15 85 ns data output time from lwr, hwr t dwod 15 ns lwr, hwr delay time from astb t dstw 0.5t 16 34 ns data setup time (to lwr, hwr )t sodw (1.5 + n) t 25 125 ns data hold time (from lwr, hwr )t hwod 0.5t 14 36 ns astb delay time from lwr, hwr t dwst 1.5t 15 135 ns lwr, hwr low-level width t wwl (1.5 + n) t 36 114 ns wait input time from address t dawt (2 + a) t 50 150 ns wait input time from astb t dstwt 1.5t 40 110 ns wait hold time from astb t hstwt (1.5 + n) t + 5 155 ns wait delay time from astb t dstwth (1.5 + n) t 40 210 note ns wait input time from rd t drwt t 40 60 ns wait hold time from rd t hrwt (1 + n) t + 5 105 ns wait delay time from rd t drwth (1 + n) t 40 160 note ns wait input time lwr, hwr t dwwt t 40 60 ns wait hold time lwr, hwr t hwwt (1 + n) t + 5 105 ns wait delay time from lwr, hwr t dwwth (1 + n) t 40 160 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 100 ns. 540 chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) user s manual u11515ej3v0ud (2) serial operation (t a = 40 to +125 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 800 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns si1, si2 setup time t sssk 80 ns (to sck1, sck2 ) si1, si2 hold time t hssk 80 ns (from sck1, sck2 ) so1, so2 output delay time t dsbsk r = 1 k ? , c = 100 pf 0 150 ns from sck1, sck2 remarks 1. t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) (3) other operations (t a = 40 to +125 c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high, low-level width t wnih , t wnil 10 s intp0-intp6 high, low-level width t with , t witl 4t cysmp ti2, ti3 high, low-level width t wtih , t wtil 4t cysmp reset high, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0-6) 541 chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) user? manual u11515ej3v0ud a/d converter characteristics (t a = ?0 to +125 c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd ?0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v av ref av dd 0.5 %fsr note 2 3.4 v av ref < 4.5 v 0.7 %fsr note 2 quantization error 1/2 lsb conversion time t conv 169 t cyk sampling time t samp 20 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb integral linearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian ?.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 3.0 4.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 100 a current mode av dddr = 5 v 10% 10 1000 a notes 1. the quantization error is excluded. 2. indicated as a ratio (%fsr) to the full-scale value. remark t cyk = 1/f clk (f clk is internal system clock frequency). 542 user? manual u11515ej3v0ud chapter 26 electrical specifications ( pd78f4046) refer to chapter 27 timing charts for the timing charts. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.5 to +7.0 v av dd ?.5 to v dd + 0.5 v av ss ?.5 to +0.5 v input voltage v i1 note 1 ?.5 to v dd + 0.5 7.0 v v i2 mode/v pp pin in the programming mode ?.5 to +11.0 v output voltage v o ?.5 to v dd + 0.5 v output current, low i ol all output pins 15 ma total of all output pins 150 ma output current, high i oh all output pins ?0 ma total of all output pins ?00 ma analog input voltage v ian note 2 av dd > v dd ?.5 to v dd + 0.5 v v dd av dd ?.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd ?.5 to v dd + 0.5 v input voltage v dd av dd ?.5 to av dd + 0.5 operating ambient t a ?0 to +70 c temperature storage temperature t stg ?0 to +125 c notes 1. pins other than the pins specified in note 2 . 2. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 32 mhz ?0 to +70 c 4.5 to 5.5 v capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 10 pf i/o capacitance c io 10 pf 543 chapter 26 electrical specifications ( pd78f4046) user? manual u11515ej3v0ud flash memory specifications (t a = +10 to +40 c (rewriting), t a = ?0 to +70?c (other than rewriting)) parameter symbol conditions min. typ. max. unit v dd supply voltage v dd 4.5 5.5 v v pp supply voltage v pp v pp high-voltage detection 9.7 10.0 10.3 v number of rewrites note 10 times note if the number of flash memory rewrites exceeds 10, operation is not guaranteed. oscillator characteristics (t a = ?0 to +70 c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit parameter min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 32 mhz crystal resonator external clock x1 input frequency (f x ) 8 32 mhz x1 input rise/fall time 0 5 ns x1 input high-/low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of pin x1 to pin x2 when the extc bit = 1. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter 544 chapter 26 electrical specifications ( user s manual u11515ej3v0ud dc characteristics (t a = 10 to +70 parameter symbol conditions min. typ. max. unit input voltage, low v il 0 0.8 v input voltage, high v ih1 note 1 2.2 v dd v v ih2 note 2 0.8v dd v dd output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, high v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 1 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 32 mhz) 50 80 ma i dd2 halt mode (f xx = 32 mhz) 30 60 ma i dd3 idle mode (f xx = 32 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 215 a v dddr = 5 v 10% 15 50 a pull-up resistor r l 15 40 80 k ? pins other than the pins specified in note 2 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 used as analog inputs) 4. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 (pins used as analog inputs, and only during a non-sampling operation) 545 chapter 26 electrical specifications ( pd78f4046) user? manual u11515ej3v0ud ac characteristics (t a = ?0 to +70 c, v dd = 4.5 to 5.5 v, v ss = 0 v) (1) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 62.5 250 ns address setup time (to astb )t sast (0.5 + a) t ?20 11.2 ns address hold time (from astb )t hsta 0.5t ?20 11.2 ns astb high-level width t wsth (0.5 + a) t ?17 14.2 ns rd delay time from address t dar (1 + a) t ?15 47.5 ns address float time from rd t fra 0ns data input time from address t daid (2.5 + a + n) t ?56 100.2 ns data input time from rd t drid (1.5 + n) t ?48 45.7 ns delay time from astb to rd t dstr 0.5t ?16 15.3 ns data hold time (from rd )t hrid 0ns address active time from rd t dra 0.5t ?14 17.2 ns rd low-level width t wrl (1.5 + n) t ?30 63.7 ns delay time from address to lwr, hwr t daw (1 + a) t ?15 47.5 ns data output time from lwr, hwr t dwod 15 ns delay time from astb to lwr, hwr t dstw 0.5t ?16 15.3 ns data setup time (to lwr, hwr )t sodw (1.5 + n) t ?25 68.7 ns data hold time (from lwr, hwr )t hwod 0.5t ?14 17.2 ns delay time from lwr, hwr to astb t dwst 1.5t ?15 78.8 ns lwr, hwr low-level width t wwl (1.5 + n) t ?36 57.7 ns wait input time from address t dawt (2 + a) t ?50 75 ns wait input time from astb t dstwt 1.5t ?40 53.7 ns wait hold time from astb t hstwt (1.5 + n) t + 5 98.8 ns delay time from astb to wait t dstwth (2.5 + n) t ?40 116.2 note ns wait input time from rd t drwt t ?40 22.5 ns wait hold time from rd t hrwt (1 + n) t + 5 67.5 ns delay time from rd to wait t drwth (1 + n) t ?40 85 note ns wait input time from lwr, hwr t dwwt t ?40 22.5 ns wait hold time from lwr, hwr t hwwt (1 + n) t + 5 67.5 ns delay time from lwr, hwr to wait t dwwth (1 + n) t ?40 85 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise 0. 3. n indicates the number of the wait cycles as specified by the external wait pin (wait) or programmable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 62.5 ns. 546 chapter 26 electrical specifications ( user s manual u11515ej3v0ud (2) serial operation (t a = 10 to +70 parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 500 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 210 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 210 ns si1, si2 setup time t sssk 80 ns (to sck1, sck2 ) si1, si2 hold time t hssk 80 ns (from sck1, sck2 ) delay time from sck1, sck2 t dsbsk r = 1 k ? , c = 100 pf 0 150 ns to so1, so2 output remarks 1. t sft is a value set by software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) (3) other operations (t a = 10 to +70 parameter symbol conditions min. max. unit nmi high-/low-level width t wnih , t wnil 10 s intp0 to intp6 high-/low-level width t with , t witl 4t cysmp ti2, ti3 high-/low-level width t wtih , t wtil 4t cysmp reset high-/low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set by software in the noise protection control register (npc). when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0 to 6) 547 chapter 26 electrical specifications ( pd78f4046) user? manual u11515ej3v0ud a/d converter characteristics (t a = ?0 to +70 c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd ?0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 1 4.5 v av ref av dd 0.5 %fsr note 2 3.4 v av ref < 4.5 v 0.7 %fsr note 2 quantization error 1/2 lsb conversion time t conv 80 ns t cyk 250 ns 169 t cyk 62.5 ns t cyk < 80 ns 208 t cyk sampling time t samp 80 ns t cyk 250 ns 20 t cyk 62.5 ns t cyk < 80 ns 24 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb integral linearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian ?.3 av ref + 0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 1.0 3.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 10 a current mode av dddr = 5 v 10% 10 50 a notes 1. excludes quantization error. 2. indicated as a ratio (%fsr) to the full-scale value. remark t cyk = 1/f clk (f clk is the internal system clock frequency) 548 user? manual u11515ej3v0ud chapter 27 timing charts ac timing test points read operation (8 bits) (clk) ad8 to ad15 (output) ad0 to ad7 (i/o) astb (output) rd (output) wait (input) higher address higher address lower address (output) data (input) lower address (output) t cyk t wsth t hsta t dstr t dar t wrl t dstwth t hstwt t dstwt t drwt t dawt t hrwt t drwth t drid t dra t fra t hrid t sast t daid hi-z hi-z hi-z hi-z v dd 0 v 0.8v dd or 2.2 v 0.8 v 0.8v dd or 2.2 v 0.8 v test points 549 chapter 27 timing charts user s manual u11515ej3v0ud write operation (8 bits) (clk) ad8 to ad15 (output) ad0 to ad7 (output) astb (output) lwr (output) wait (input) t cyk t dstwth t hstwt t dstwt t dwwt t dawt t hwwt t dwwth t dstw t hsta t wsth t sast t hwod t dwst t dwod t sodw t daw t wwl higher address higher address lower address (output) undefined data (output) lower address (output) 550 chapter 27 timing charts user s manual u11515ej3v0ud read operation (16 bits) (clk) t cyk address (output) data (input) address (output) t wsth t hsta t dstr t dar t wrl t dstwth t hstwt t dstwt t drwt t dawt t hrwt t drwth t drid t dra t fra t hrid t sast t daid hi-z hi-z hi-z hi-z ad8 to ad15 ad0 to ad7 (i/o) astb (output) rd (output) wait (input) 551 chapter 27 timing charts user s manual u11515ej3v0ud write operation (16 bits) (clk) ad8 to ad15 ad0 to ad7 (output) astb (output) hwr, lwr (output) wait (input) t cyk t dstwth t hstwt t dstwt t dwwt t dawt t hwwt t dwwth t dstw t hsta t wsth t sast t hwod t dwst t dwod t sodw t daw t wwl address (output) data (output) undefined address (output) 552 chapter 27 timing charts user s manual u11515ej3v0ud serial operation interrupt input timing reset input timing timer input timing sck1, sck2 so1, so2 si1, si2 t cysk t wskl t dsbsk t sssk t hssk t wskh t wnih t wnil 0.8v dd 0.8 v t with t witl 0.8v dd 0.8 v nmi intp0 to intp6 t wrsh t wrsl 0.8v dd 0.8 v reset t wtih t wtil 0.8v dd 0.8 v ti2, ti3 553 user? manual u11515ej3v0ud chapter 28 package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 ? 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h 554 user? manual u11515ej3v0ud chapter 29 recommended soldering conditions the pd784046 subseries should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) remark the recommended soldering conditions of the pd784046gc(a)-xxx-3b9 are undetermined. for details, contact an nec electronics sales representative. table 29-1. surface mounting type soldering conditions (1/2) (1) pd784044gc- -3b9: 80-pin plastic qfp (14 x 14) pd784044gc(a)- -3b9: 80-pin plastic qfp (14 x 14) pd784044gc(a1)- -3b9: 80-pin plastic qfp (14 x 14) pd784044gc(a2)- -3b9: 80-pin plastic qfp (14 x 14) pd784046gc(a1)- -3b9: 80-pin plastic qfp (14 x 14) pd784046gc(a2)- -3b9: 80-pin plastic qfp (14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), ir35-00-3 count: three times or less vps package peak temperature: 215 c, time: 40 sec. max. (at 200 c or higher), vp15-00-3 count: three times or less wave soldering solder bath temperature: 260 c max., time 10 sec. max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) caution do not use different soldering methods together (except for partial heating). (2) pd784046gc- -3b9: 80-pin plastic qfp (14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), ir35-00-2 count: twice or less vps package peak temperature: 215 c, time: 40 sec. max. vp15-00-2 (at 200 c or higher), count: twice or less wave soldering solder bath temperature: 260 c max., time 10 sec. max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) caution do not use different soldering methods together (except for partial heating). 555 chapter 29 recommended soldering conditions user? manual u11515ej3v0ud table 29-1. surface mounting type soldering conditions (2/2) (3) pd78f4046gc-3b9: 80-pin plastic qfp (14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or ir35-207-2 higher), count: twice or less, exposure limit: 7 days note (after 7 days, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or vp15-207-2 higher), count: twice or less, exposure limit: 7 days note (after 7 days, prebake at 125 c for 20 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: ws60-207-1 once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after 7 days, prebake at 125 c for 20 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 556 user? manual u11515ej3v0ud chapter 30 cautions on using development tools when developing a program by using in-circuit emulator ie-784000-r, note the following point. (1) setting of standby control register (stbc) include an instruction that sets the standby control register (stbc) to 00h following the location instruction and initialization of the stack pointer (sp) in the program after reset is cleared. program example: rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn mov stbc, #0h reason: the internal system clock of the pd784046 is fixed to f xx /2. however, the internal system clock of the in-circuit emulator is set to f xx /16 after reset has been cleared. therefore, the setting of the stbc must be changed as described above. even if the instruction that sets the stbc to 00h is executed, the operation is not affected because the stbc of the real chip is fixed to 30h. for the same reason, the value of the stbc of the real chip is always 30h when it is read. the value of the stbc on the in-circuit emulator, however, is changed to 00h when the above setting is made. therefore, note that the value of the stbc of the in-circuit emulator and that of the real chip differ when they are read. (2) output of clkout pin the clkout pin of the real chip always outputs the oscillation frequency (f xx ). however, in the case of the in-circuit emulator ie-784000-r, the internal system clock (f xx /2 or f xx /16 note ) is output. note that f xx is not output from the in-circuit emulator. note the clkout pin output of the in-circuit emulator is set to f xx /16 after the reset has been released, and set to f xx /2 when 00h is set to the standby control register (stbc). 557 user? manual u11515ej3v0ud appendix a development tools the following development tools are available for the development of systems that employ the pd784046 subseries. figure a-1 shows the development tool configuration. support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles can be used for pc98-nx series computers. when using pc98-nx series computers, refer to the description for ibm pc/at compatibles. windows unless otherwise specified, ?indows?means the following oss. ?windows 3.1 ?windows 95 ?windows 98 ?windows 2000 ?windows nt tm ver. 4.0 558 appendix a development tools user? manual u11515ej3v0ud figure a-1. development tool configuration (1/2) (1) when using the in-circuit emulator ie-78k4-ns assembler package c compiler package c library source file device file language processing software system simulator integrated debugger device file real-time os embedded software flash memory write adapter in-circuit emulator emulation probe conversion socket or conversion adapter target system host machine (pc) emulation board on-chip flash memory version flash programmer debugging tool power supply unit interface adapter, pc card interface, etc flash memory write environment 559 appendix a development tools user? manual u11515ej3v0ud figure a-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-784000-r remark items in broken line boxes differ according to the development environment. refer to a.3.1 hardware . assembler package c compiler package c library source file device file language processing software system simulator integrated debugger device file real-time os embedded software flash memory write adapter interface adapter emulation probe conversion socket or conversion adapter target system host machine (pc or ews) emulation board on-chip flash memory version flash programmer debugging tool interface board in-circuit emulator i/o emulation board probe board emulation probe conversion board flash memory write environment 560 appendix a development tools user? manual u11515ej3v0ud a.1 language processing software sp78k4 78k/iv series software package ra78k4 assembler package cc78k4 c compiler package df784046 note device file cc78k4-l c library source file development tools (software) common to the 78k/iv series are combined in this package. part number: s sp78k4 this assembler converts programs written in mnemonics into an object codes executable with a microcomputer. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optical device file (df784046). 561 appendix a development tools user? manual u11515ej3v0ud a.2 flash memory writing tools flashpro ii (part number: fl-pr2) flashpro iii (part number: fl-pr3, pg-fp3) flash programmer fa-80gc flash memory writing adapter remark flashpro ii, flashpro iii, and fa-80gc are products of naito densei machida mfg. co., ltd. phone: +81-45-475-4191 naito densei machida mfg. co., ltd. flash programmer dedicated to microcontrollers with on-chip flash memory. flash memory writing adapter used connected to the flashpro ii/flashpro iii. ? fa-80gc : 80-pin plastic qfp (gc-3b9 type) remark the part number differs depending on the host machine and operating system used. s sp78k4 host machine os supply medium ab17 pc-9800 series, japanese windows cd-rom bb17 ibm pc/at compatibles english windows s ra78k4 s cc78k4 host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at compatibles english windows ab17 japanese windows cd-rom bb17 english windows 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df784046 s cc78k4-l host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at compatibles english windows 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt 562 appendix a development tools user s manual u11515ej3v0ud a.3 debugging tools a.3.1 hardware (1/2) (1) when using the in-circuit emulator ie-78k4-ns ie-78k4-ns in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-784046-ns-em1 emulation board np-80gc-tq np-h80gc-tq emulation probe tgc-080sbp conversion socket (refer to figure a-3 ) remarks 1. np-80gc-tq and np-h80gc-tq are products made by naito densei machida mfg.co., ltd. for further information, contact naito densei machida mfg. co., ltd. (tel: +81-45-475-4191) 2. tgc-080sbp is a product made by tokyo eletech corporation. for further information, contact daimaru kogyo, ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) 3. the tgc-080sbp is sold individually. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/iv series product. it corresponds to integrated debugger (id78k4-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this adapter is used for supplying power from a receptacle of 100 v to 200 v ac. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78k4-ns host machine (c bus supported). this is pc card and interface cable required when using the pc-9800 series notebook-type computer as the ie-78k4-ns host machine. this adapter is required when using the ibm pc/at compatible computers as the ie-78k4-ns host machine (isa bus supported). interface adapter required when using a pc that incorporates pci bus as the host machine for the ie-78k4-ns this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for 80-pin plastic qfp (gc-3b9 type). this conversion socket connects the np-80gc-tq or np-h80gc-tq to the target system board designed to mount a 80-pin plastic qfp (gc-3b9 type). 563 appendix a development tools user s manual u11515ej3v0ud a.3.1 hardware (2/2) (2) when using the in-circuit emulator ie-784000-r ie-784000-r the ie-784000-r is an in-circuit emulator common to the 78k/iv series, and is used in in-circuit emulator combination with ie-784000-r-em and ie-784046-r-em1, which are sold separately. this in-circuit emulator debugs the connected host machine. an integrated debugger (id78k4) and device file (sold separately) are required to enable debugging in c language and structured assembly language at the source program level. more efficient debugging and program verification is possible with functions such as c0 coverage. connect to a host machine via ethernet tm or a dedicated bus. an interface adapter (sold separately) is required for connection. ie-70000-98-if-c interface adapter required when a pc-9800 series (except notebook type pc) is used interface adapter as the host machine for the ie-784000-r (c bus supported). ie-70000-pc-if-c interface adapter required when using an ibm pc/at compatible as the host machine interface adapter (isa bus supported). ie-78000-r-sv3 interface adapter and cable required when an ews is used as the host machine for interface adapter the ie-784000-r. connect to a board inside the ie-784000-r. note that 10base-5 is supported as the ethernet. a commercial conversion adapter is required for other systems. ie-784000-r-em emulation board common to 78k/iv series ie-784046-r-em1 board to emulate peripheral hardware specific to device emulation board ie-78k4-r-ex2 conversion board for 80-pin packages required when using the ie-784046-r-em1 on emulation probe conversion board ie-784000-r ep-78230gc-r probe to connect the in-circuit emulator and the target system. for 80-pin plastic qfp emulation probe (gc-3b9 type). ev-9200gc-80 conversion socket to connect the ep-78230gc-r and a target system board on which conversion socket an 80-pin plastic qfp (gc-3b9 type) can be mounted (refer to figures a-4 and a-5 ) remark ev-9200gc-80 is sold in five units. 564 appendix a development tools user s manual u11515ej3v0ud a.3.2 software sm78k4 this system simulator is used to perform debugging at c source level or assembler system simulator level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k4 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. the sm78k4 should be used in combination with the optional device file (df784046). part number: s sm78k4 id78k4-ns integrated debugger (supporting in-circuit emulator ie-78k4-ns) id78k4 integrated debugger (supporting in-circuit emulator ie-784000-r) remark in the part number differs depending on the host machine and os used. s sm78k4 s id78k4-ns s id78k4 host machine os supply medium ab13 ibm pc/at compatible japanese windows 3.5-inch 2hc fd bb13 english windows ab17 japanese windows cd-rom bb17 english windows this debugger is a control program to debug 78k/iv series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows. it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time oss can be improved. it should be used in combination with the optional device file (df784046). part number: s id78k4-ns, s id78k4 565 appendix a development tools user s manual u11515ej3v0ud a.4 cautions on designing target system the connection condition diagrams for the emulation probe and conversion socket are shown below. design the system considering the shape of components, etc. to be mounted on the target system in accordance with this configuration. figure a-2. distance between in-circuit emulator and conversion socket note 350 mm in case of the np-h80gc-tq. target system conversion socket tgc-080sbp emulation probe np-80gc-tq, np-h80gc-tq emulation board ie-784046-ns-em1 cn2 connection 150 mm note cn2 cn1 in-circuit emulator ie-78k4-ns 566 appendix a development tools user s manual u11515ej3v0ud figure a-3. target system connection conditions remark np-80gc-tq and np-h80gc-tq are products made by naito densei machida mfg. co., ltd. emulation board ie-784046-ns-em1 emulation probe np-80gc-tq, np-h80gc-tq 50 mm 25 mm 35 mm 35 mm 60 mm 10 mm 18.7 mm 10 mm conversion socket tgc-080sbp target system pin 1 567 appendix a development tools user s manual u11515ej3v0ud a.5 deminsions of conversion socket (ev-9200gc-80) and recommended board mounting pattern figure a-4. dimensions of ev-9200gc-80 (reference) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 568 appendix a development tools user? manual u11515ej3v0ud figure a-5. recommended board mounting pattern of ev-9200gc-80 (reference) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 ?.002 +0.003 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 +0.001 ?.002 caution dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mount manual" website (http://www.necel.com/pkg/en/mount/index.html). 569 user? manual u11515ej3v0ud appendix b embedded software for efficient development and maintenance of the pd784046 subseries, the following embedded products are available. rx78k4 rx78k4 is a real-time os conforming to the itron specifications. real-time os tool (configurator) for generating nucleus of rx78k4 and plural information tables is supplied. used in combination with an optional assembler package (ra78k4) and device file (df784046). 570 user? manual u11515ej3v0ud appendix c register index [a] adcr0 : a/d conversion result register 0 ............................................................................................ 301 adcr0h : a/d conversion result register 0h ......................................................................................... 302 adcr1 : a/d conversion result register 1 ............................................................................................ 301 adcr1h : a/d conversion result register 1h ......................................................................................... 302 adcr2 : a/d conversion result register 2 ............................................................................................ 301 adcr2h : a/d conversion result register 2h ......................................................................................... 302 adcr3 : a/d conversion result register 3 ............................................................................................ 301 adcr3h : a/d conversion result register 3h ......................................................................................... 302 adcr4 : a/d conversion result register 4 ............................................................................................ 301 adcr4h : a/d conversion result register 4h ......................................................................................... 302 adcr5 : a/d conversion result register 5 ............................................................................................ 301 adcr5h : a/d conversion result register 5h ......................................................................................... 302 adcr6 : a/d conversion result register 6 ............................................................................................ 301 adcr6h : a/d conversion result register 6h ......................................................................................... 302 adcr7 : a/d conversion result register 7 ............................................................................................ 301 adcr7h : a/d conversion result register 7h ......................................................................................... 302 adic : interrupt control register .......................................................................................................... 380 adm : a/d converter mode register ................................................................................................... 299 asim : asynchronous serial interface mode register ......................................................................... 324 asim2 : asynchronous serial interface mode register 2 ...................................................................... 324 asis : asynchronous serial interface status register ....................................................................... 326 asis2 : asynchronous serial interface status register 2 .................................................................... 326 [b] brgc : baud rate generator control register .................................................................................... 347 brgc2 : baud rate generator control register 2 ................................................................................. 347 bw : bus width specification register .............................................................................................. 457 [c] cc00 : capture/compare register 00 .................................................................................................. 173 cc01 : capture/compare register 01 .................................................................................................. 173 cc02 : capture/compare register 02 .................................................................................................. 173 cc03 : capture/compare register 03 .................................................................................................. 173 cm10 : compare register 10 ................................................................................................................ 199 cm11 : compare register 11 ................................................................................................................ 199 cm20 : compare register 20 ................................................................................................................ 225 cm21 : compare register 21 ................................................................................................................ 225 cm30 : compare register 30 ................................................................................................................ 219 cm31 : compare register 31 ................................................................................................................ 219 cm40 : compare register 40 ................................................................................................................ 273 cm41 : compare register 41 ................................................................................................................ 273 cmic10 : interrupt control register .......................................................................................................... 378 cmic11 : interrupt control register .......................................................................................................... 378 cmic20 : interrupt control register .......................................................................................................... 378 571 appendix c register index user? manual u11515ej3v0ud cmic21 : interrupt control register .......................................................................................................... 378 cmic30 : interrupt control register .......................................................................................................... 379 cmic31 : interrupt control register .......................................................................................................... 379 cmic40 : interrupt control register .......................................................................................................... 379 cmic41 : interrupt control register .......................................................................................................... 379 csiic1 : interrupt control register .......................................................................................................... 379 csiic2 : interrupt control register .......................................................................................................... 380 csim1 : clocked serial interface mode register 1 ................................................................................ 338 csim2 : clocked serial interface mode register 2 ................................................................................ 338 [i] ief1 : interrupt valid edge flag register 1 ........................................................................................ 362 ief2 : interrupt valid edge flag register 2 ........................................................................................ 363 imc : interrupt mode control register ................................................................................................ 384 ims : internal memory size select register ...................................................................................... 67 intm0 : external interrupt mode register 0 ........................................................................................... 360 intm1 : external interrupt mode register 1 ........................................................................................... 361 ispr : in-service priority register ....................................................................................................... 383 [m] mk0 : interrupt mask register 0 .......................................................................................................... 382 mk0h : interrupt mask register 0h ....................................................................................................... 382 mk0l : interrupt mask register 0l ........................................................................................................ 382 mk1 : interrupt mask register 1 .......................................................................................................... 382 mk1h : interrupt mask register 1h ....................................................................................................... 382 mk1l : interrupt mask register 1l ........................................................................................................ 382 mm : memory extension mode register ............................................................................................ 432, 440 [n] npc : noise protection control register ............................................................................................ 364 [o] osts : oscillation stabilization time specification register ............................................................... 92, 463 ovic0 : interrupt control register .......................................................................................................... 377 ovic1 : interrupt control register .......................................................................................................... 377 ovic4 : interrupt control register .......................................................................................................... 377 [p] p0 : port 0 ............................................................................................................................... ........... 100 p0l : port 0 buffer register ................................................................................................................ 160 p1 : port 1 ............................................................................................................................... ........... 106 p2 : port 2 ............................................................................................................................... ........... 112 p3 : port 3 ............................................................................................................................... ........... 119 p4 : port 4 ............................................................................................................................... ........... 127 p5 : port 5 ............................................................................................................................... ........... 133 p6 : port 6 ............................................................................................................................... ........... 139 p7 : port 7 ............................................................................................................................... ........... 145 p8 : port 8 ............................................................................................................................... ........... 146 572 appendix c register index user? manual u11515ej3v0ud p9 : port 9 ............................................................................................................................... ........... 147 pic0 : interrupt control register .......................................................................................................... 377 pic1 : interrupt control register .......................................................................................................... 377 pic2 : interrupt control register .......................................................................................................... 377 pic3 : interrupt control register .......................................................................................................... 377 pic4 : interrupt control register .......................................................................................................... 378 pic5 : interrupt control register .......................................................................................................... 378 pic6 : interrupt control register .......................................................................................................... 378 pm0 : port 0 mode register ................................................................................................................ 101 pm1 : port 1 mode register ................................................................................................................ 108 pm2 : port 2 mode register ................................................................................................................ 115 pm3 : port 3 mode register ................................................................................................................ 122 pm4 : port 4 mode register ................................................................................................................ 128 pm5 : port 5 mode register ................................................................................................................ 134 pm6 : port 6 mode register ................................................................................................................ 140 pm9 : port 9 mode register ................................................................................................................ 150 pmc1 : port 1 mode control register ................................................................................................... 108 pmc2 : port 2 mode control register ................................................................................................... 115 pmc3 : port 3 mode control register ................................................................................................... 123 pmc9 : port 9 mode control register ................................................................................................... 150, 449 prdc : port read control register ....................................................................................................... 155 prm : prescaler mode register ........................................................................................................... 176, 202 prm2 : prescaler mode register 2 ........................................................................................................ 229 prm4 : prescaler mode register 4 ........................................................................................................ 275 puoh : pull-up resistor option register h .......................................................................................... 153 puol : pull-up resistor option register l ........................................................................ 104, 131, 137, 143 pwc1 : programmable wait control register 1 .................................................................................... 442 pwc2 : programmable wait control register 2 .................................................................................... 444 [r] rtpc : real-time output port control register .................................................................................. 101, 161 rxb : serial receive buffer: uart0 ................................................................................................. 322 rxb2 : serial receive buffer: uart2 ................................................................................................. 322 [s] seric : interrupt control register .......................................................................................................... 379 seric2 : interrupt control register .......................................................................................................... 380 sio1 : serial shift register: ioe1 ....................................................................................................... 337 sio2 : serial shift register: ioe2 ....................................................................................................... 337 sric : interrupt control register .......................................................................................................... 379 sric2 : interrupt control register .......................................................................................................... 380 stbc : standby control register .......................................................................................................... 91, 461 stic : interrupt control register .......................................................................................................... 380 stic2 : interrupt control register .......................................................................................................... 380 [t] tm0 : timer register 0 ........................................................................................................................ 173 tm1 : timer register 1 ........................................................................................................................ 199 573 appendix c register index user? manual u11515ej3v0ud tm2 : timer register 2 ........................................................................................................................ 225 tm3 : timer register 3 ........................................................................................................................ 221 tm4 : timer register 4 ........................................................................................................................ 273 tmc : timer mode control register .................................................................................................... 175, 201 tmc2 : timer mode control register 2 ................................................................................................. 227 tmc4 : timer mode control register 4 ................................................................................................. 274 toc0 : timer output control register 0 ............................................................................................... 175 toc1 : timer output control register 1 ............................................................................................... 201 toc2 : timer output control register 2 ............................................................................................... 228 tum0 : timer unit mode register 0 ...................................................................................................... 174, 200 tum2 : timer unit mode register 2 ...................................................................................................... 226 txs : serial transmit shift register: uart0 .................................................................................... 322 txs2 : serial transmit shift register: uart2 .................................................................................... 322 [w] wdm : watchdog timer mode register ............................................................................................... 291, 385 574 user? manual u11515ej3v0ud appendix d revision history the revision history is described below. the ?pplied to?column indicates the chapters in each edition. (1/3) edition major revisions from previous edition applied to 2nd edition change of pd784044 from ?nder development?to ?evelopment completed? throughout addition of the following products to the relevant products: pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2) change of 78k/iv series product development diagram . chapter 1 general change of the minimum value of the supply voltage (v dd ) from 4.0 v to 4.5 v. addition of 1.3 quality grades . addition of 1.9 differences between pd784046 and pd784046(a) . addition of 1.10 differences between pd784046(a), 784046(a1), and 784046(a2) . addition of the functional description of the clkout pin. chapter 2 pin functions addition of description in (2) capture/compare registers (cc00 through cc03) . chapter 8 timer 0 addition of caution when the timer output is enabled while the active level is changed. addition of caution when the active level of the timer output is changed. addition of caution when the timer output is enabled while the active level is changed. chapter 9 timer 1 addition of caution when the active level of the timer output is changed. addition of caution when the active level of the timer output is changed. chapter 10 timers/ counters 2 and 3 change of the description of <5> in (2) of 12.4.1 general cautions on use of chapter 12 watchdog watchdog timer from ?f the stop mode or idle mode is entered as the result of an timer function inadvertent program loop?to ?f the stop mode, halt mode, or idle mode is entered as the result of an inadvertent program loop? addition of note and calculating method of the wait time if the reception completion chapter 14 asynchro- interrupt is disabled when a reception error occurs. nous serial interface/ 3-wire serial i/o change of instructions in 16.9 when interrupt request and macro service are chapter 16 interrupt temporarily held pending . functions change of description from ?he watchdog timer must not be used to release the chapter 18 standby standby mode (stop or idle mode)?to ?he watchdog timer must not be used to function release the standby mode (stop, halt, or idle mode)? addition of note of the operating status of bus lines (ad8 to ad15, a16 to a19) in halt mode. deletion of watchdog timer of ?on-maskable interrupt request (nmi pin input/ watchdog timer)? addition of caution concerning the malfunction that causes a wait for the oscillation stabilization time when the idle mode is released. addition of (2) output of clkout pin . chapter 22 cautions on using development tools general revision for supporting ie-78k4-ns. appendix a development tools change of target host machines. appendix b embedded change of versions of oss to be supported. software 575 appendix d revision history user? manual u11515ej3v0ud (2/3) edition major revisions from previous edition applied to 2nd edition change of pd784044 from ?nder development?to ?evelopment completed? throughout addition of the following products to the relevant products: pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2) change of 78k/iv series product development diagram . chapter 1 general change of the minimum value of the supply voltage (v dd ) from 4.0 v to 4.5 v. addition of 1.3 quality grades . addition of 1.9 differences between pd784046 and pd784046(a) . addition of 1.10 differences between pd784046(a), 784046(a1), and 784046(a2) . addition of the functional description of the clkout pin. chapter 2 pin functions addition of description in (2) capture/compare registers (cc00 through cc03) . chapter 8 timer 0 addition of caution when the timer output is enabled while the active level is changed. addition of caution when the active level of the timer output is changed. addition of caution when the timer output is enabled while the active level is changed. chapter 9 timer 1 addition of caution when the active level of the timer output is changed. addition of caution when the active level of the timer output is changed. chapter 10 timers/ counters 2 and 3 change of the description of <5> in (2) of 12.4.1 general cautions on use of chapter 12 watchdog watchdog timer from ?f the stop mode or idle mode is entered as the result of an timer function inadvertent program loop?to ?f the stop mode, halt mode, or idle mode is entered as the result of an inadvertent program loop? addition of note and calculating method of the wait time if the reception completion chapter 14 asynchro- interrupt is disabled when a reception error occurs. nous serial interface/ 3-wire serial i/o change of instructions in 16.9 when interrupt request and macro service are chapter 16 interrupt temporarily held pending . functions 3rd edition completion of development of the following products throughout pd784046, 78f4046, 784046(a), 784046(a1), 784046(a2) update of 78k/iv product lineup chapter 1 general addition of description on bwd pin in table 2-6 i/o circuit type of each pin and chapter 2 pin recommended processing of unused pins functions addition of cautions on start bit during uart transmission to 14.5 cautions chapter 14 asynchro- nous serial interface/ 3-wire serial i/o ?modification of figure 18-1 diagram of standby mode transition chapter 18 standby ?modification of description in 18.6 (5) a/d converter function ?addition of description on flashpro iii chapter 20 ?addition of 20.4 cautions programming pd78f4046 addition of chapter chapter 22 electrical specifications ( pd784044, 784046) addition of chapter chapter 23 electrical specifications ( pd784044(a), 784046(a)) 576 appendix d revision history user? manual u11515ej3v0ud (3/3) edition major revisions from previous edition applied to 3rd edition addition of chapter chapter 24 electrical specifications ( pd784044(a1), 784046(a1)) addition of chapter chapter 25 electrical specifications ( pd784044(a2), 784046(a2)) addition of chapter chapter 26 electrical specifications ( pd78f4046) addition of chapter chapter 27 timing charts addition of chapter addition of chapter 28 package drawing addition of chapter addition of chapter 29 recommended soldering conditions ?addition of description on host machines and oss appendix a development ?addition of sp78k4 to a.1 language processing software, modification of tools description in remark ?addition of description on flashpro iii in remark in a.2 flash memory writing tools ?addition and modification of description in a.3.1 hardware ?modification of description in remark in a.3.2 software ?addition of a.4 cautions on designing target system modification of description appendix b embedded software |
Price & Availability of UPD78F4046GC-3B9
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |