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kae00c400m revision 1.0 january 2003 - 1 - preliminary mcp memory document title multi-chip package memory 128m bit (16mx8) nand flash memory / 64m bit (4mx16) u t ram *2 revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 1.0 remark preliminary preliminary preliminary final history initial draft. revise - change u t ram output load(c l ) from 50pf to 80pf revise - change u t ram operating current(icc1) from 5ma to 7ma finalize draft date may 29, 2002 july 4, 2002 october 21, 2002 january 10, 2003
kae00c400m revision 1.0 january 2003 - 2 - preliminary mcp memory multi-chip package memory 128m bit (16mx8) nand flash memory / 64m bit (4mx16) utram *2 the kae00c400m is a multi chip package memory which com- bines 128mbit nand flash and two 64mbit unit transistor cmos ram. 128mbit flash memory is organized as 16m x8 bit and 64mbit u t ram is organized as 4m x16 bit. in 128mb nand flash a 528- byte page program can be typically achieved within 200us and an 16k-byte block erase can be typically achieved within 2ms. in serial read operation, a byte can be read by 50ns. even the write- intensive systems can take advantage of the flash s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. these algorithms have been implemented in many mass storage appli- cations and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ecc. the 64mbit u t ram is fabricated by samsung s advanced cmos technology using one transistor memory cell. the device supports partial refresh mode for low standby current. the kae00c400m is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. this device is available in 111-ball tbga type. features power supply voltage - flash : 2.7 ~ 3.6v - u t ram : 2.3 ~ 2.7v(in battery backup mode, max. vcc = 3.1v) organization - flash : (16m + 512k)bit x 8bit - u t ram : 4m x 16 bit(each component) access time - flash : random access : 10us(max.), serial page access : 50ns(min.) - u t ram : 80ns power consumption (typical value) - flash read current : 10 ma(@20mhz) program/erase current : 10 ma standby current : 10 m a - u t ram operating current : 35ma standby current : 80 m a(per 1 u t ram) flash automatic program and erase page program : (512 + 16)byte block erase : (16k + 512)byte flash fast write cycle time program time : 200us(typ.) block erase time : 2ms(typ.) u t ram support 16mb partial refresh flash endurance : 100,000 program/erase cycles minimum flash data retention : 10 years operating temperature : -25 c ~ 85 c package : 111 - ball tbga type - 10 x 11mm, 0.8 mm pitch general description samsung electronics co., ltd. reserves the right to change products and specifications without notice.
kae00c400m revision 1.0 january 2003 - 3 - preliminary mcp memory pin configuration 111-tbga: top view (ball down) dnu 1 2 3 4 5 6 a b c d e f g h dnu dnu dnu a12 a8 we u vccu1 a21 a7 a3 a1 dnu a13 a9 a20 vccu2 lb a6 a4 a2 a14 a10 a19 ub nc a5 vss a15 a11 pr 1 a18 dq0 f nc ale re wp dq2 f nc dq3 f vss ce cle nc dq4 f vcc f vcc f we f r/ b nc dq6 f nc a16 nc dq5u dq0u nc dq7 f dq7u dq13u nc dq11u dq3u dq8u a0 vss dnu dnu dnu dnu 7 8 10 9 j k l m dnu dq15u dq6u dq4u vccu2 vccqu2 dq1u cs 1u cs 2u dnu dnu vss dq14u dq12u vccu1 vccqu1 dq9u oe vss dnu dnu dnu dnu dnu dnu dnu 12 11 n dnu dnu dnu dnu a17 nc pr 2 dq1 f nc dq5 f nc nc nc dq2u dq10u
kae00c400m revision 1.0 january 2003 - 4 - preliminary mcp memory ordering information k a e 00 c 4 0 0 m - t gnn samsung mcp(3 chip) memory device type nand flash+u t ram+u t ram nor flash density , vcc , org. 00 : none sram density , vcc , org. 0 : none sdram density , vcc , org. 0 : none access time g : nand flash:50ns n : u t ram: 80ns n : u t ram: 80ns u t ram density , vcc , org. 4 : 64mbit + 64mbit, 2.5v, x16, partial refresh version m : 1st generation nand flash density , vcc , org. c : 128mbit, 3.0v, x8 package t : tbga pin description ball name description ball name description a 0 to a 21 address input balls (u t ram) cle command latch enable (flash memory) dq 0f to dq 7f command, address, data input/output balls (flash memory) r/ b ready/busy (flash memory) pr 1 partial refresh (u t ram1) dq 0u to dq 15u data input/output balls (u t ram) pr 2 partial refresh (u t ram2) wp write protection (flash memory) ce chip enable (flash memory) v ccf power supply (flash memory) cs 1u chip select (u t ram1) vccu1 power supply (u t ram1) cs 2u chip select (u t ram2) vccu2 power supply (u t ram2) we f write enable (flash memory) vccqu1 data out power (u t ram1) we u write enable (u t ram) vccqu2 data out power (u t ram2) oe output enable (u t ram) vss ground (common) re read enable (flash memory) ub upper byte enable (u t ram) nc no connection lb lower byte enable (u t ram) dnu do not use ale address latch enable (flash memory)
kae00c400m revision 1.0 january 2003 - 5 - preliminary mcp memory figure 1. functional block diagram ub cs 1 u vccu1 lb r/ b wp ce ale address(a0 to a21) 128m bit flash memory 64m bit u t ram cle we f re vcc f vss dq 0u to dq 15u dq 0u to dq 15u dq 0f to dq 7f vss vccqu1 vccu2 64m bit vss vccqu2 u t ram oe cs 2 u we u dq 0u to dq 15u pr 1 pr 2
kae00c400m revision 1.0 january 2003 - 6 - preliminary mcp memory 512bytes 16 bytes note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low" dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 *l 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 32k pages (=1,024 blocks) 512 bytes 8 bit 16 bytes 1 block =32 pages = (16k + 512) bytes dq 0 ~ dq 7 1 page = 528 bytes 1 block = 528 bytes x 32 pages = (16k + 512) bytes 1 device = 528 bytes x 32pages x 1024blocks = 132 mbits column address row address (page address) page register figure 2. flash array organization
kae00c400m revision 1.0 january 2003 - 7 - preliminary mcp memory nand flash product introduction table 1. command sets note: 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the start pointer is automatically moved to the 1st half register(00h) on the next cycle. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o the flash memory is a 132mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. spare 16 columns are located in 512 to 527 column address. a 528-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected like nand structure. each of the 16 cells resides in a different page. a block consists of the 32 pages f ormed by one nand structures, totaling 8448 nand structures of 16 cells. the array organization is shown in figure 2. program and rea d operations are executed on a page basis, while erase operation is executed on a block basis. the memory array consists of 1024 blocks, and a block is separately erasable by 16k-byte unit. it indicates that the bit by bit erase operation is prohibited o n the flash memory. the flash memory has addresses multiplexed with 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except page program command and block erase command which require two cycles: one cycle for setup and another for execution. the 16m byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. page read and page program need the same three address cycles following required command input. in block erase operation, however, only two row address cycles are used. device operations are selected by writing specific commands into command register. table 1 defines the specific commands of the flash memory.
kae00c400m revision 1.0 january 2003 - 8 - preliminary mcp memory table 2. flash memory operations table note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we f re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by table 3. u t ram operations table 1. x means don t care.(must be low or high state) 2. i = 1 or 2. when cs1 u is active, cs2 u must be standby. and when cs2 u is active, cs1 u must be standby. cs iu 2) pr i 2) oe we u lb ub dq 0~7 dq 8~15 mode power h h x 1) x 1) x 1) x 1) high-z high-z deselected standby l h x 1) x 1) h h high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected partial refresh l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active
kae00c400m revision 1.0 january 2003 - 9 - preliminary mcp memory flash memory operation page read upon initial device power up, the device status is initially read1 command(00h) latched. this operation is also initiated by wr iting 00h to the command register along with three address cycles. once the command is latched, it does not need to be written for the following page read operation. two types of operation are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are transferred to the data registers i n less than 10 m s(tr). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out by sequential re pulse of 50n period cycle. high to low transi- tions of the re clock take out the data from the selected column address up to the last column address. read1 and read2 commands determine pointer which selects either main area or spare area. the spare area(512 to 527 bytes) may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of spare area while addresses a 4 to a 7 are ignored. to move the pointer back to the main area, read1 command(00h/01h) is needed. figures 3 through 8 show typical sequence and timing for each read operation. figure 3,4 details the sequence. figure 3. read1 operation start add.(3cycle) 00h 01h a 0 ~ a 7 & a 9 ~ a 23 data output(sequential) (00h command) 1st half array 2nd half array data field spare field (01h command)* 1st half array 2nd half array data field spare field * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. ce cle ale r/ b we dq 0 ~ 7 re t r
kae00c400m revision 1.0 january 2003 - 10 - preliminary mcp memory page program the device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page program operation within the same page without intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. page program cycle consists of a serial data loading(up to 528 bytes of data) into the page register, and prog ram of loaded data into the appropriate cell. serial data loading can start in 2nd half array by moving pointer. about the pointer oper ation, please refer to the attached technical notes. serial data loading is executed by entering the serial data input command(80h) and three cycle address input and then serial data loading. the bytes except those to be programmed need not to be loaded. the page program confirm command(10h) initiates the programming process. writing 10h alone without previously entering 80h will not initi ate program process. the internal write controller automatically executes the algorithms and timings necessary for program and verif ica- tion, thereby freeing the cpu for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b out- put, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is completed, the write status bit(i/o 0) may be checked(figure 5). the internal write ver ifi- cation detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status co m- mand mode until another valid command is written to the command register. figure 5 details the sequence. figure 5. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 23 dq 0 ~ 7 r/ b address & data input dq 0 pass 528 byte data 10h 70h fail t prog figure 4. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 23 data output(sequential) spare field ce cle ale r/ b we 1st half array 2nd half array data field spare field start add.(3cycle) (a 4 ~ a 7 : don't care) dq 0 ~ 7 re t r
kae00c400m revision 1.0 january 2003 - 11 - preliminary mcp memory figure 6. block erase operation block erase the erase operation is done on a block(16k bytes) basis. block erase is executed by entering erase setup command(60h) and 2 cycle block addresses and erase confirm command(d0h). only address a14 to a23 is valid while a9 to a13 is ignored. this two- step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condition. at the rising edge of we after erase confirm command input, internal write controller handles erase and erase-veri- fication. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 6 details the sequence. 60h block add. : a 9 ~ a 23 dq 0 ~ 7 r/ b address input(2cycle) dq 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to command register, a read cycle takes out the content of the status register to the i/o pins on the falling edge of ce or re . this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be tog- gled for updated status. refer to table 4 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, a read command(00 h or 50h) should be given before sequential page read cycle. table4. read status register definition dq # status definition dq 0 program / erase "0" : successful program / erase "1" : error in program / erase dq 1 reserved for future use "0" dq 2 "0" dq 3 "0" dq 4 "0" dq 5 "0" dq 6 device operation "0" : busy "1" : ready dq 7 write protect "0" : protected "1" : not protected
kae00c400m revision 1.0 january 2003 - 12 - preliminary mcp memory figure 7. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (73h) respectively. the command regis- ter remains in read id mode until further commands are issued to it. figure 7 shows the operation sequence. figure 8. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device status after reset operation. if the device is already in reset state, new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. reset command is not necessary for normal operation. refer to figure 8 below. table5. device status after power-up after reset operation mode read 1 waiting for next command ffh dq 0 ~ 7 r/ b t rst ce cle dq 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar1 t rea 73h t whr
kae00c400m revision 1.0 january 2003 - 13 - preliminary mcp memory ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 9). its value ca n be determined by the following guidance. v cc r/ b open drain output device gnd where i l is the sum of the input currents of all devices tied to the r/ b pin. rp t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf 2.0v tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 96 tf 189 290 381 4.2 4.2 4.2 4.2 3.3 1.65 1.1 0.825 0.8v figure 9. rp vs tr ,tf & rp vs ibusy
kae00c400m revision 1.0 january 2003 - 14 - preliminary mcp memory the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.3v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences as shown in figure 10. the two step command sequence for program/erase provides additional software protection. figure 10. ac waveforms for power transition v ccf wp high ? ? we ~ 2.5v ~ 2.5v ? 10 m s data protection & powerup sequence
kae00c400m revision 1.0 january 2003 - 15 - preliminary mcp memory flash absolute maximum ratings note: 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in/out -0.6 to + 4.6 v v cc -0.6 to + 4.6 temperature under bias t bias -40 to +125 c operating temperature t a -25 to +85 c storage temperature t stg -65 to +150 c u t ram absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -25 to 85 c storage temperature t stg -65 to 150 c flash recommended operating conditions (voltage reference to gnd, t a =-25 to 85 c) parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 0 0 0 v u t ram recommended dc operating conditions ( t a =-25 to 85 c, otherwise specified.) 1. in battery backup mode, max. vcc = 3.1v item symbol min typ max unit supply voltage vcc 2.3 2.5 2.7 1) v ground vss 0 0 0 v
kae00c400m revision 1.0 january 2003 - 16 - preliminary mcp memory flash dc and operating characteristics (recommended operating conditions) parameter symbol test conditions min typ max unit input leakage current i li v in =0 to vcc(max) - - 10 m a output leakage current i lo v out =0 to vcc(max) - - 10 operating current sequential read i cc 1 trc=50ns, ce =v il i out =0ma - 10 20 ma program i cc 2 - - 10 20 erase i cc 3 - - 10 20 input high voltage v ih - 2.0 - v cc +0.3 v input low voltage, all inputs v il - -0.3 - 0.8 output high voltage level v oh i oh =-400 m a 2.4 - - output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 ma stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 m a u t ram dc and operating characteristics (each component) 1. typical values are tested at v cc =2.5v, t a =25 c and not guaranteed. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih, pr =v ih , oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, pr 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - 3 7 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs =v il , pr =v ih, v in =v il or v ih - 35 40 ma input high voltage v ih - 2.0 - vcc+0.3 2) v input low voltage v il - -0.3 3) - 0.6 v output high voltage v oh i oh =-0.5ma 2.0 - - v output low voltage v ol i ol =0.5ma - - 0.4 v standby current(cmos) i sb1 cs 3 vcc-0.2v, pr 3 vcc-0.2v, other inputs=vss to vcc - 80 100 m a partial refresh current i sbp pr 0.2v, other inputs=vss to vcc - 50 60 m a
kae00c400m revision 1.0 january 2003 - 17 - preliminary mcp memory capacitance (t a = 25 c, f = 1.0mhz) note: capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c dq v il =0v - 20 pf input capacitance c in v in =0v - 20 pf valid block(flash) note: 1. the flash memory may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not try to access these invalid blocks for program and erase. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correcti on. parameter symbol min typ. max unit valid block number n vb 1004 - 1024 blocks pr =v il cs =v ih pr =v il cs =v il , ub or/and lb =v il pr =v ih standby mode state machines(u t ram) read operation twice power on initial state (wait 200 m s) active standby mode partial refresh mode pr =v ih cs =v ih cs =v il , ub or/and lb =v il pr =v ih pr =v ih , cs=v ih standby mode characteristic(u t ram) power mode address memory cell data standby current( m m a) standby 00000h ~ 3fffffh valid 100 partial refresh 00000h ~ 0fffffh vaild 60
kae00c400m revision 1.0 january 2003 - 18 - preliminary mcp memory flash ac test condition parameter value input pulse levels 0.4v to 2.4v input rise and fall times 5ns input and output timing levels 1.5v output load 1 ttl gate and cl=50pf flash program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms flash ac timing characteristics for command / address / data input note: 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns
kae00c400m revision 1.0 january 2003 - 19 - preliminary mcp memory flash ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. to break the sequential read cycle, ce must be held high for longer time than tceh. 3. the time to ready depends on the value of the pull-up resistor tied r/ b pin. parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns ce access time t cea - 45 ns re access time t rea - 30 ns re high to output hi-z t rhz - 30 ns ce high to output hi-z t chz - 20 ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) m s
kae00c400m revision 1.0 january 2003 - 20 - preliminary mcp memory flash command latch cycle ce we cle ale dq 0 ~ 7 command t cls t cs t clh t ch t wp t als t alh t ds t dh flash address latch cycle ce we cle ale dq 0 ~ 7 a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 23 t wp t ds t dh t alh
kae00c400m revision 1.0 january 2003 - 21 - preliminary mcp memory flash input data latch cycle ce cle we dq 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp ? ? ? flash sequential out cycle after read (cle=l, we =h, ale=l) re ce r/ b dq 0 ~ 7 dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz* ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. t rp
kae00c400m revision 1.0 january 2003 - 22 - preliminary mcp memory flash status read cycle ce we cle re dq 0 ~ 7 70h status output t cls t clh t cs t wp t ch t ds t dh t rea t ir t rhz* t chz* t whr t cea t cls flash read1 operation (read one page) ce cle r/ b dq 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar2 t r t rc t rhz t chz dout 527 t wc t rr ? ? ?
kae00c400m revision 1.0 january 2003 - 23 - preliminary mcp memory flash read2 operation (read one page) ce cle r/ b dq 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout dout 527 m address a 0 ~ a 3 :valid address a 4 ~ a 7 :dont care 511+m dout 511+m+1 t ar2 t r t wb t rr ? ? ? selected row start address m 512 16 flash page program operation ce cle r/ b dq 0 ~ 7 we ale re 80h 70h dq 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 23 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data sequential input program command read status command dq 0 =0 successful program dq 0 =1 error in program t prog t wb t wc t wc t wc ? ? ?
kae00c400m revision 1.0 january 2003 - 24 - preliminary mcp memory flash manufacture & device id read operation ce cle dq 0 ~ 7 we ale re 90h read id command maker code device code 00h ech 73h t rea address 1st cycle flash block erase operation (erase one block) ce cle r/ b dq 0 ~ 7 we ale re 60h a 17 ~ a 23 a 9 ~ a 16 auto block erase erase command read status command dq 0 =1 error in erase doh 70h dq 0 busy t wb t bers dq 0 =0 successful erase page(row) address t wc ? setup command
kae00c400m revision 1.0 january 2003 - 25 - preliminary mcp memory u t ram ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.1v output load: c l =80pf u t ram ac characteristics (vcc=2.3~2.7v, t a =-25 to 85 c) 1. the limitation in continuous write operation is up to 50 times. if you want to write continuously over 50 times, please refer to the technical note. parameter list symbol speed units 80ns min max read read cycle time t rc 80 - ns address access time t aa - 80 ns chip select to output t co - 80 ns output enable to valid output t oe - 35 ns ub , lb access time t ba - 80 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 25 ns ub , lb disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 10 - ns write write cycle time t wc 80 - ns chip select to end of write t cw 70 - ns address set-up time t as 0 - ns address valid to end of write t aw 70 - ns ub , lb valid to end of write t bw 70 - ns write pulse width t wp 60 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 25 ns data to write time overlap t dw 35 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns
kae00c400m revision 1.0 january 2003 - 26 - preliminary mcp memory address data out previous data valid data valid u t ram timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , pr = we= v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( pr = we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. the minimum read cycle( t rc ) is determined by longer one of t rc1 and t rc2. 4. t oe (max) is met only when oe becomes enabled after t aa (max). data valid high-z t rc1 t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t rc2 t co address cs ub , lb oe data out
kae00c400m revision 1.0 january 2003 - 27 - preliminary mcp memory t as(3) timing waveform of write cycle(1) ( we controlled , pr =v ih ) timing waveform of write cycle(2) ( cs controlled , pr =v ih ) address data undefined ub , lb we data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) cs t wr(4)
kae00c400m revision 1.0 january 2003 - 28 - preliminary mcp memory timing waveform of write cycle(3) ( ub , lb controlled , pr =v ih ) (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs 200 m s read operation twice v cc cs timing waveform of power up(1) 200 m s v cc cs timing waveform of power up(2) (no dummy cycle) 300 m s ? ? ? (power up(1)) 1. after v cc reaches v cc (min.) following power application, wait 200 m s with cs high and then toggle cs low and commit read operation at least twice. then you get into the normal operation. 2. read operation should be executed by toggling cs pin low. 3. the read operation must satisfy the specified t rc . (power up(2)) 1. after v cc reaches v cc (min.) following power application, wait 200 m s and wait another 300 m s with cs high if you don?t want to commit dummy read cycle. after total 500 m s wait, toggle cs low, then you get into the normal mode. v cc(min) v cc(min) ? ? ?
kae00c400m revision 1.0 january 2003 - 29 - preliminary mcp memory nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perf or- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guar- anteed to be a valid block, does not require error correction. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte(x8 device) or 1st & 6th word(x16 device) in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffh(x8 device) or non-ffffh(x16 device) data at the column address of 517(x8 device) or 256 and 261(x16 device). since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on t he original invalid block information and create the invalid block table via the following suggested flow chart(figure 11). any int entional erasure of the original invalid block information is prohibited. * check "ffh" at the column address figure 11. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block 517(x8 device) or 256 and 261(x16 device)
kae00c400m revision 1.0 january 2003 - 30 - preliminary mcp memory nand flash technical notes figure 12. flash program flow chart start dq 6 = 1 ? write 00h dq 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status registe write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, so you can execute block replacement on a page basis with a page sized buffer. t o improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be recla imed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
kae00c400m revision 1.0 january 2003 - 31 - preliminary mcp memory nand flash technical notes figure 13. flash erase flow chart start dq 6 = 1 ? dq 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes figure 14. flash read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes figure 15. flash block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
kae00c400m revision 1.0 january 2003 - 32 - preliminary mcp memory samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command sets the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effec - tive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be input- ted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting from ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~512), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of nand flash table 6. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 16. block diagram of pointer operation nand flash technical notes
kae00c400m revision 1.0 january 2003 - 33 - preliminary mcp memory nand flash technical notes ce we t wp t ch t cs start add.(3cycle) 80h data input ce cle ale we dq 0 ~ 7 data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant saving in power consumption. start add.(3cycle) 00h ce cle ale we dq 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea ce re dq 0 ~ 7 figure 17. program operation with ce don?t-care. figure 18. read operation with ce don?t-care. system interface using ce don?t-care.
kae00c400m revision 1.0 january 2003 - 34 - preliminary mcp memory technical note u t ram usage and timing introduction u t ram is based on single-transistor dram cells. as with any other dram, the data in these cells must be periodically refreshed to prevent data loss. what makes the u t ram unique is that it offers a true sram style interface that hides all refresh operations from the memory controller. start with a dram technology the key point of u t ram is its high speed and low power. this high speed comes from the use of many small blocks such as 32kbits each to create u t ram arrays. the small blocks have short word lines thus with little capacitance eliminating a major factor of operating current dissipation in conventional dram blocks. each independent macro-cell on a u t ram device consists of a number of these blocks. each chip has one or more macro. the address decoding logic is also fast. u t ram performs a complete read operation in every trc, but u t ram needs power up sequence like dram. power up sequence and diagram 1. apply power. 2. maintain stable power for a minium 200 m s with cs =high. 3. issue read operation at least 2 times. design achieves sram specific operations the u t ram was designed to work just like an sram - without any waits or other overhead for precharging or refreshing its internal dram cells. samsung electronics(samsung) hides these operations inside with advanced design technology - those are not to be seen from outside. precharging takes place during every access, overlapped between the end of the cycle and the decoding portion of the next cycle. hiding refresh is more difficult. every row in every block must be refreshed at least once during the refresh interval to prevent data loss. samsung provides an internal refresh controller for devices. when all accesses within refresh interval are directed to one macro-cell, as can happen in signal processing applica- tions, a more sophisticated approach is required to hide refresh. the pseudo sram is sometimes used on these appli- cations, which requires a memory controller that can hold off accesses when a refresh operation is needed. samsung?s unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power con- sumption) is that the u t ram never need to hold off accesses, and indeed it has no hold off signal. the circuitry that gives samsung this advantage is fairly simple but has not previ- ously been disclosed. avoid timing following figures show you an abnormal timing which is not supported on u t ram and its solution. if your system has a timing which sustains invalid states over 4 m s at read mode like figure 1, there are some guide lines for proper operation of u t ram. when your system has multiple invalid address signals shorter than trc on the timing shown in figure 1, u t ram needs a nor- mal read timing(trc) during that cycle(figure 2) or needs to toggle cs once to ?high? for about ?trc?(figure 3). cs =v il , ub or/and lb =v il read operation(2 times) power on initial state (wait 200 m s) active cs =v ih cs we address less than trc over 4 m s cs we address trc over 4 m s figure 2. put on read operation every 4 m s figure 1.
kae00c400m revision 1.0 january 2003 - 35 - preliminary mcp memory figure 3. cs we address over 4 m s trc toggle cs to high every 4 m s cs we address twp over 4 m s twc write operation has similar restriction to read operation. if your system has a timing which sustains invalid states over 4 m s at write mode and has continuous write signals with length of min. twc over 4 m s like figure 4, you must toggle we once to high figure 5. figure 4. cs we address twp over 4 m s twc trc figure 6. cs we address twp over 4 m s twc trc and make it stay high at least for trc every 4 m s or toggle cs once to high for about trc. toggle cs to high every 4 m s toggle we to high and make it stay high at least for trc every 4 m s
kae00c400m revision 1.0 january 2003 - 36 - preliminary mcp memory 1 1 . 0 0 0 . 1 0 0 . 8 0 x 1 2 = 9 . 6 0 0 . 8 0 4 . 8 0 10.00 0.10 0.80 0.80 x 11 = 8.80 4.40 b 0.10 max 0.45 0.05 0.20 m a b 111 - ? 0.45 0.05 ? a b c d e f g h 7 5 4 3 2 1 6 8 9 10 11 j k l m n 12 a #a1 index mark(optional) 1 1 . 0 0 0 . 1 0 10.00 0.10 11.00 0.10 0 . 3 2 0 . 0 5 1 . 3 0 0 . 1 0 #a1 (datum a) (datum b) package dimension 111-ball tape ball grid array package (measured in millimeters) top view bottom view side view

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