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cat25256 ? catalyst semiconductor, inc. 1 doc. no. md-1127 rev. a characteristics subject to change without notice 256-kb spi serial cmos eeprom features ? 10 mhz spi compatible ? 1.8v to 5.5v supply voltage range ? spi modes (0,0) & (1,1) ? 64-byte page write buffer ? self-timed write cycle ? hardware and software protection ? block write protection ? protect 1/4, 1/2 or entire eeprom array ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature range ? rohs-compliant 8 lead pdip, soic, tssop and 8-pad tdfn packages ? 8-ball chip scale package (csp) pin configuration pdip (l) soic (v, x) tssop (y) tdfn (zd2) cs 1 8 v cc so 2 7 hold wp 3 6 sck v ss 4 5 si csp-8b (top view) v cc 18 cs hold 27so sck 3 6 wp si 4 5v ss pin function pin name function cs chip select so serial data output wp write protect v ss ground si serial data input sck serial clock hold hold transmission input v cc power supply description the cat25256 is a 256-kb serial cmos eeprom device internally organized as 32kx8 bits. this features a 64-byte page write buffer and supports the serial peripheral interface (spi) protocol. the device is enabled through a chip select (cs ) input. in addition, the required bus signals are clock input (sck), data input (si) and data output (so) lines. the hold input may be used to pause any serial communication with the cat25256 device. the device features software and hardware write protec? tion, including partial as well as full array protection. functional symbol for ordering information details, see page 16. cs wp hold si so cat25256 v cc v ss sck
cat25256 doc. no. md-1127 rev. a 2 ? catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units storage temperature ?65 to +150 oc voltage on any pin with respect to ground (2) ?0.5 to + 6.5 v reliability characteristics (3) symbol parameter min units n end (4) endurance 1,000,000 program/ erase cycles t dr data retention 100 years d.c. operating characteristics v cc = 1.8v to 5.5v, t a =-40c to +85c and v cc = 2.5v to +5.5v, t a =-40c to +125c, unless otherwise specified. symbol parameter test conditions min max units 10mhz / -40c to 85c 2 ma i ccr supply current ( read mode ) read, v cc = 5.5v, so open 5mhz / -40c to 125c 2 ma 10mhz / -40c to 85c 4 ma i ccw supply current (write mode) write, v cc = 5.5v, so open 5mhz / -40c to 125c 4 ma t a = -40c to +85c 1 a i sb1 standby current v in = gnd or v cc , cs = v cc , wp = v cc , hold = v cc , v cc = 5.5v t a = -40c to +125c 3 a t a = -40c to +85c 4 a i sb2 standby current v in = gnd or v cc , cs = v cc , wp = gnd, hold = gnd v cc = 5.5v t a = -40c to +125c 5 a i l input leakage current v in = gnd or v cc -2 2 a t a = -40c to +85c -1 1 a i lo output leakage current cs = v cc , v out = gnd or v cc t a = -40c to +125c -1 2 a v il input low voltage -0.5 0.3v cc v v ih input high voltage 0.7v cc v cc + 0.5 v v ol1 output low voltage v cc > 2.5v, i ol = 3.0ma 0.4 v v oh1 output high voltage v cc > 2.5v, i oh = -1.6ma v cc - 0.8v v v ol2 output low voltage v cc > 1.8v, i ol = 150a 0.2 v v oh2 output high voltage v cc > 1.8v, i oh = -100a v cc - 0.2v v pin capacitance (3) t a = 25 ? c, f = 1.0mhz, v cc = +5.0v symbol test conditions min typ max units c out output capacitance (so) v out = 0v 8 pf c in input capacitance (cs , sck, si, wp , hold ) v in = 0v 8 pf notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc + 0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc + 1.5v, for periods of less than 20ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropri ate aec-q100 and jedec test methods. (4) page mode, v cc = 5v, 25c
cat25256 ? catalyst semiconductor, inc. 3 doc. no. md-1127 rev. a characteristics subject to change without notice a.c. characteristics t a = -40c to +85c (industrial) and t a = -40c to +125c (extended). (1) v cc = 1.8v-5.5v / -40c to +85c v cc = 2.5v-5.5v / -40c to +125c v cc = 2.5v-5.5v -40c to +85c symbol parameter min. max. min. max. units f sck clock frequency dc 5 dc 10 mhz t su data setup time 30 20 ns t h data hold time 30 20 ns t wh sck high time 75 40 ns t wl sck low time 75 40 ns t lz hold to output low z 50 25 ns t ri (2) input rise time 2 2 s t fi (2) input fall time 2 2 s t hd hold setup time 0 0 ns t cd hold hold time 10 10 ns t v output valid from clock low 75 40 ns t ho output hold time 0 0 ns t dis output disable time 50 20 ns t hz hold to output high z 100 25 ns t cs cs high time 50 15 ns t css cs setup time 50 15 ns t csh cs hold time 50 15 ns t wps wp setup time 10 10 ns t wph wp hold time 10 10 ns t wc (4) write cycle time 5 5 ms power-up timing (2)(3) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms notes: (1) ac test conditions: input pulse voltages: 0.3v cc to 0.7v cc input rise and fall times: 10ns input and output reference voltages: 0.5v cc output load: current source i ol max /i oh max ; c l = 50pf (2) this parameter is tested initially and after a design or process change that affects the parameter. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. (4) t wc is the time from the rising edge of cs after a valid write sequence to the end of the internal write cycle.
cat25256 doc. no. md-1127 rev. a 4 ? catalyst semiconductor, inc. characteristics subject to change without notice pin description si: the serial data input pin accepts op-codes, addresses and data. in spi modes (0,0) and (1,1) input data is latched on the rising edge of the sck clock input. so: the serial data output pin is used to transfer data out of the device. in spi modes (0,0) and (1,1) data is shifted out on the falling edge of the sck clock. sck: the serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and cat25256. cs : the chip select input pin is used to enable/disable the cat25256. when cs is high, the so output is tri-stated (high impedance) and the device is in standby mode (unless an internal write operation is in progress). every communication session between host and cat25256 must be preceded by a high to low transition and concluded with a low to high transition of the cs input. wp : the write protect inpu t pin will allow all write operations to the device when held high. when wp pin is tied low and the wpen bit in the status register (refer to status r egister description, later in this data sheet) is set to ?1?, writing to the status register is disabled. hold : the hold input pin is used to pause trans? mission between host and cat25256, without having to retransmit the entire sequence at a later time. to pause, hold must be taken low and to resume it must be taken back high, with the sck input low during both transitions. when not used for pausing, it is recommended the hold input to be tied to v cc , either directly or through a resistor. functional description the cat25256 device supports the serial peripheral interface (spi) bus protocol, modes (0,0) and (1,1). the device contains an 8-bit instruction register. the instruction set and associated op-codes are listed in table 1. reading data stored in the cat25256 is accomplished by simply providing the read command and an address. writing to the cat25256, in addition to a write command, address and data, also requires enabling the device for writing by first setting certain bits in a status register, as will be explained later. after a high to low transition on the cs input pin, the cat25256 will accept any one of the six instruction op- codes listed in table 1 and will ignore all other possible 8-bit combinations. the communication protocol follows the timing from figure 1. table 1: instruction set instruction opcode operation wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory write 0000 0010 write data to memory figure 1. synchronous data timing note: dashed line = mode (1, 1) - - - - - - valid in v ih v il t css v ih v il v ih v il v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z cs sck si so t ri t fi
cat25256 ? catalyst semiconductor, inc. 5 doc. no. md-1127 rev. a characteristics subject to change without notice status register the status register, as shown in table 2, contains a number of status and control bits. the rdy (ready) bit indicates whether the device is busy with a write operation. this bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. for the host, this bit is read only. the wel (write enable latch) bit is set/reset by the wren/wrdi commands. when set to 1, the device is in a write enable state and when set to 0, the device is in a write disable state. the bp0 and bp1 (block protect) bits determine which blocks are currently write protected. they are set by the user with the wrsr command and are non-volatile. the user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to table 3. the protected blocks then become read-only. the wpen (write protect enable) bit acts as an enable for the wp pin. hardware write protection is enabled when the wp pin is low and the wpen bit is 1. this condition prevent s writing to the status register and to the block protected sections of memory. while hardware write protection is active, only the non-block protected memory can be written. hardware write protection is disabled when the wp pin is high or the wpen bit is 0. the wpen bit, wp pin and wel bit combine to either permit or inhibit write operations, as detailed in table 4. table 2. status register 7 6 5 4 3 2 1 0 wpen 0 0 0 bp1 bp0 wel rdy table 3. block protection bits status register bits bp1 bp0 array address protected protection 0 0 none no protection 0 1 6000-7fff quarter array protection 1 0 4000-7fff half array protection 1 1 0000-7fff full array protection table 4. write protect conditions wpen wp wel protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
cat25256 doc. no. md-1127 rev. a 6 ? catalyst semiconductor, inc. characteristics subject to change without notice write operations the cat25256 device powers up into a write disable state. the device contains a write enable latch (wel) which must be set before attempting to write to the memory array or to the status register. in addition, the address of the memory location(s) to be written must be outside the protected area, as defined by bp0 and bp1 bits from the status register. write enable and write disable the internal write enable latch and the correspon? ding status register wel bit are set by sending the wren instruction to the cat25256. care must be taken to take the cs input high after the wren instruction, as otherwise the write enable latch will not be properly set. wren timing is illustrated in figure 2. the wren instruction must be sent prior any write or wrsr instruction. the internal write enable latch is reset by sending the wrdi instruction as shown in figure 3. disabling write operations by resetting the wel bit, will protect the device against inadvertent writes. figure 2. wren timing note: dashed line = mode (1, 1) - - - - - - figure 3. wrdi timing note: dashed line = mode (1, 1) - - - - - - sck si cs so 00000 110 high impedance sck si cs so 00000 100 high impedance
cat25256 ? catalyst semiconductor, inc. 7 doc. no. md-1127 rev. a characteristics subject to change without notice sck si so 00 00 00 10 d7 d6 d5 d4 d3 d2 d1 d0 012345678 2122232425262728293031 cs opcode * please check the byte address table (table 5) data in high impedance byte address* a n a 0 byte write once the wel bit is set, the user may execute a write sequence, by sending a write instruction, a 16-bit address and data as shown in figure 4. only 15 significant address bits are used by the cat25256. the rest are don?t care bits, as shown in table 5. internal programming will start after the low to high cs transition. during an internal write cycle, all commands, except for rds r (read status register) will be ignored. the rdy bit will indicate if the internal write cycle is in progress (rdy high), or the the device is ready to accept commands (rdy low). page write after sending the first data byte to the cat25256, the host may continue sending data, up to a total of 64 bytes, according to timing shown in figure 5. after each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. if during this process the end of page is exceeded, then loading will ?roll over? to the first byte in the page, thus possibly overwriting previoualy loaded data. following completion of the write cycle, the cat25256 is automatically returned to the write disable state. table 5. byte address device address significant bits address don't care bits # address clock pulses cat25256 a14 - a0 a15 16 figure 4. byte write timing note: dashed line = mode (1, 1) - - - - - - figure 5. page write timing note: dashed line = mode (1, 1) - - - - - - sck si so 00 00 00 10 byte address* data byte 1 012345678 212223 24-31 32-39 data byte 2 data byte 3 data byte n cs opcode 7..1 0 24+(n-1)x8-1..24+(n-1)x8 24+nx8-1 data in high impedance a n a 0 *please check the byte address table. (table 5)
cat25256 doc. no. md-1127 rev. a 8 ? catalyst semiconductor, inc. characteristics subject to change without notice write status register the status register is written by sending a wrsr instruction according to timing shown in figure 6. only bits 2, 3 and 7 can be written using the wrsr command. write protection the write protect (wp ) pin can be used to protect the block protect bits bp0 and bp1 against being inadvertently altered. when wp is low and the wpen bit is set to ?1?, write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the stat us register. if the internal write cycle has already been initiated, wp going low will have no effect on any writ e operation to the status register. the wp pin function is blocked when the wpen bit is set to ?0?. the wp input timing is shown in figure 7. figure 6. wrsr timing note: dashed line = mode (1, 1) - - - - - - figure 7. wp timing note: dashed line = mode (1, 1) - - - - - - 01 23 45678 10 911121314 sck si msb high impedance data in 15 so cs 7 6 5 4 3 2 10 0000000 1 opcode cs sck wp wp t wps t wph
cat25256 ? catalyst semiconductor, inc. 9 doc. no. md-1127 rev. a characteristics subject to change without notice sck si so 0000001 1 byte address* 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 * please check the byte address table (table 5). cs data out msb high impedance a n a 0 opcode read operations read from memory array to read from memory, the host sends a read instruction followed by a 16-bit address (see table 5 for the number of significant address bits). after receiving the last ad dress bit, the cat25256 will respond by shifting out dat a on the so pin (as shown in figure 8). sequentially stored data can be read out by simply continuing to run the clock. the internal address pointer is automatically incremented to the next higher address as data is shifted out. after reaching the highest memory address, the address counter ?rolls over? to the lowest memory address, and the read cycle can be c ontinued indefinitely. the read operation is terminated by taking cs high. read status register to read the status register , the host simply sends a rdsr command. after receiving the last bit of the command, the cat25256 will shift out the contents of the status register on the so pin (figure 9). the status register may be read at any time, including during an internal write cycle. figure 8. read timing note: dashed line = mode (1, 1) - - - - - - figure 9. rdsr timing note: dashed line = mode (1, 1) - - - - - - 01 2345678 10 911121314 sck si data out msb high impedance opcode so 7 6 5 4 3 2 1 0 cs 00 0 00 1 01
cat25256 doc. no. md-1127 rev. a 10 ? catalyst semiconductor, inc. characteristics subject to change without notice hold operation the hold input can be used to pause communication between host and cat25256. to pause, hold must be taken low while sck is low (figure 10). during the hold condition the device must remain selected (cs low). during the pause, the data output pin (so) is tri- stated (high impedance) and si transitions are ignored. to resume communication, hold must be taken high while sck is low. design considerations the cat25256 device incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and w ill power down into reset mode when v cc drops below the por trigger level. this bi-directional por behavior protects the device against ?brown-out? failure following a temporary loss of power. the cat25256 device powers up in a write disable state and in a low power standby mode. a wren instruction must be issued prior any writes to the device. after power up, the cs pin must be brought low to enter a ready state and receive an instruction. after a successful byte/page write or status register write, the device goes into a write disable mode. the cs input must be set high after the proper number of clock cycles to start the internal write cycle. access to the memory array during an internal write cycle is ignored and programming is continued. any invalid op-code will be ignored and the seri al output pin (so) will remain in the high impedance state. figure 10. hold timing note: dashed line = mode (1, 1) - - - - - - cs sck hold so t cd t hd t hd t cd t lz t hz high impedance
cat25256 ? catalyst semiconductor, inc. 11 doc. no. md-1127 rev. a characteristics subject to change without notice package outline drawings pdip 8-lead 300mils (l) (1)(2) notes: (1) all dimensions are in millimeters. angels in degree. (2) complies with jedec standard ms-001. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification symbol min nom max a5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7.11 eb 7.87 10.92 l 2.92 3.30 3.80
cat25256 doc. no. md-1127 rev. a 12 ? catalyst semiconductor, inc. characteristics subject to change without notice soic 8-lead 150mils (v) (1)(2) notes: (1) all dimensions are in millimeters. angels in degree. (2) complies with jedec standard ms-012. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a1.35 1.75 a1 0.10 0.25 b0.33 0.51 c0.19 0.25 d4.80 5.00 e5.80 6.20 e1 3.80 4.00 e1.27 bsc h0.25 0.50 l0.40 1.27 0o 8o symbol min nom max
cat25256 ? catalyst semiconductor, inc. 13 doc. no. md-1127 rev. a characteristics subject to change without notice soic 8-lead eiaj (208mils) (x) (1)(2) notes: (1) all dimensions are in millimeters. angels in degree. (2) complies with eiaj standard edr-7320. e1 eb side view top view e d pin#1 identification end view a1 a l c symbol min nom max a2.03 a1 0.05 0.25 b0.36 0.48 c0.19 0.25 d5.13 5.33 e7.75 8.26 e1 5.13 5.38 e 1.27 bsc l0.51 0.76 0o 8o for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat25256 doc. no. md-1127 rev. a 14 ? catalyst semiconductor, inc. characteristics subject to change without notice tssop 8-lead (y) (1)(2) notes: (1) all dimensions are in millimeters. angels in degree. (2) complies with jedec standard mo-153. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. a2 e1 e a1 e b d c a top view side view end view 1 l1 l symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 0.90 1.05 b0.19 0.30 c0.09 0.20 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e1 4.30 4.40 4.50 e 0.65 bsc l 1.00 ref l1 0.50 0.60 0.75 10 8
cat25256 ? catalyst semiconductor, inc. 15 doc. no. md-1127 rev. a characteristics subject to change without notice tdfn 8-pad 3 x 4.9mm (zd2) (1)(2) notes: (1) all dimensions are in millimeters. (2) complies with jedec standard mo-229. e d pin #1 identification pin #1 identification dap size 2.6 x 3.3mm detail a d2 a2 a3 a1 a b l e e2 a a1 top view side view bottom view front view detail a symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 0.45 0.55 0.65 a3 0.20 ref b 0.25 0.30 0.35 d 2.90 3.00 3.10 d2 0.90 1.00 1.10 e 4.80 4.90 5.00 e2 0.90 1.00 1.10 e0.65typ l 0.50 0.60 0.70 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat25256 doc. no. md-1127 rev. a 16 ? catalyst semiconductor, inc. characteristics subject to change without notice example of ordering information (1) (2) (3) (5) notes: (1) all packages are rohs-comp liant (lead-free, halogen-free). (2) the standard lead finish is nipdau. (3) the device used in the above example is a cat25256vi-gt3 (soic, industrial temperature, nipdau, tape & reel). (4) the soic, eiaj (x) package is only available in 2000 pcs/reel and standard lead finish matte-tin, i.e., cat25256xi-t2. (5) the tdfn 3x4.9mm (zd2) package is only available in 2000 pcs/reel, i.e., cat25256zd2i-gt2. (6) for the chip scale package (csp) dimensions and ordering details, please contact factory. (7) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office. prefix device # suffix cat 25256 v i -g t3 company id product numbe r 25256 temperature range i = industrial (-40oc to 85oc) e = extended (-40oc to 125oc) lead finish blank: matte-tin g: nipdau package l: pdip v: soic, jedec x: soic, eiaj (4) y: tssop zd2: tdfn (3x4.9mm) (5) csa1: csp (6) tape & reel t: tape & reel 2: 2000 units/reel 3: 3000 units/reel
revision history date rev. comments 10/22/07 a initial issue copyrights, trademarks and patents ? catalyst semiconductor, inc. trademarks and register ed trademarks of catalyst semiconductor include each of the following: adaptive analog?, beyond memory?, dpp?, ezdim?, ldd?, minipot?, quad-mode? and quant um charge programmable? catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or gu arantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any ot her application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or se rvice described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: md-1127 fax: 408.542.1200 revision: a www.catsemi.com issue date: 10 / 22 / 07

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