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hm62v8512a series 524288-word 8-bit high speed cmos static ram ade-203-642 (z) preliminary rev. 0.0 sep. 30, 1996 description the hitachi hm62v8512a is a 4-mbit static ram organized 512-kword 8-bit. it realizes higher density, higher performance and low power consumption by employing 0.5 m m hi-cmos process technology. the device, packaged in a 525-mil sop (foot print pitch width) or 400-mil tsop type ii is available for high density mounting. the hm62v8512a is suitable for battery backup system. features single 3 v supply access time: 85/100 ns (max) power dissipation ? active: 36 mw/mhz (max) ? standby: 3 m w (typ) completely static memory. no clock or timing strobe required equal access and cycle times common data input and output: three state output directly lv-ttl compatible: all inputs and outputs battery backup operation
hm62v8512a series 2 ordering information type no. access time package hm62v8512alfp-8 hm62v8512alfp-10 85 ns 100 ns 525-mil 32-pin plastic sop (fp-32d) hm62v8512alfp-8sl hm62v8512ALFP-10SL 85 ns 100 ns 525-mil 32-pin plastic sop (fp-32d) hm62v8512altt-8 hm62v8512altt-10 85 ns 100 ns 400-mil 32-pin plastic tsop ii (ttp-32d) hm62v8512altt-8sl hm62v8512altt-10sl 85 ns 100 ns 400-mil 32-pin plastic tsop ii (ttp-32d) hm62v8512alrr-8 hm62v8512alrr-10 85 ns 100 ns 400-mil 32-pin plastic tsop ii reverse (ttp-32dr) hm62v8512alrr-8sl hm62v8512alrr-10sl 85 ns 100 ns 400-mil 32-pin plastic tsop ii reverse (ttp-32dr)
hm62v8512a series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v v a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ss v a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc (top view) hm62v8512alfp series hm62v8512altt series hm62v8512alrr series (top view) (top view)
hm62v8512a series 4 pin description pin name function a0 to a18 address input i/o0 to i/o7 data input/output cs chip select oe output enable we write enable v cc power supply v ss ground
hm62v8512a series 5 block diagram i/o0 i/o7 cs we oe a13 a17 a15 a8 a10 a11 v v cc ss row decoder memory matrix 1,024 4,096 column i/o column decoder input data control timing pulse generator read/write control a16 a9 a14 a12 a7 a1 a0 a2 a5 a6 a3 a4 a18 function table we cs oe mode v cc current dout pin ref. cycle h not selected i sb , i sb1 high-z h l h output disable i cc high-z h l l read i cc dout read cycle l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: : h or l
hm62v8512a series 6 absolute maximum ratings parameter symbol value unit power supply voltage v cc C0.5 to +4.6 v voltage on any pin relative to v ss v t C0.5* 1 to v cc + 0.5* 2 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c storage temperature under bias tbias C10 to +85 c notes: 1. C3.0 v for pulse half-width 30 ns 2. maximum voltage is 4.6 v recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc 2.7 3.0 3.6 v supply voltage v ss 000v input high voltage v ih 0.7 v cc v cc + 0.3 v input low voltage v il C0.3* 1 0.2 v cc v note: 1. C3.0 v for pulse half-width 30 ns
hm62v8512a series 7 dc characteristics (ta = 0 to +70 c, v cc = 2.7 v to 3.6 v, v ss = 0 v) parameter symbol min typ* 1 max unit test conditions input leakage current |i li | 1 m a vin = v ss to v cc output leakage current |i lo | 1 m a cs = v ih or oe = v ih or we = v il , v i/o = v ss to v cc operating power supply current: dc i cc 10 ma cs = v il , others = v ih /v il , i i/o = 0 ma operating power supply current (hm62v8512a-8) i cc1 27 ma min cycle, duty = 100%, cs = v il , others = v ih /v il, i i/o = 0 ma operating power supply current (hm62v8512a-10) i cc1 24 ma operating power supply current i cc2 10 ma cycle time = 1 m s, duty = 100%, i i/o = 0 ma, cs 0.2 v, v ih 3 v cc C 0.2 v, v il 0.2 v standby power supply current: dc i sb 0.1 0.3 ma cs = v ih standby power supply current (1): dc i sb1 1* 2 70* 2 m a vin 3 0 v, cs 3 v cc C 0.2 v 1* 3 30* 3 m a output low voltage v ol 0.2 v i ol = 100 m a output high voltage v oh v cc C 0.2 v i oh = C100 m a notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and specified loading, and not guaranteed. 2. this characteristics is guaranteed only for l version. 3. this characteristics is guaranteed only for l-sl version. capacitance (ta = 25 c, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance* 1 cin 8 pf vin = 0 v input/output capacitance* 1 c i/o 10pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62v8512a series 8 ac characteristics (ta = 0 to +70 c, v cc = 2.7 v to 3.6 v, unless otherwise noted.) test conditions input pulse levels: 0.4 v to 2.4 v input rise and fall time: 5 ns input and output timing reference levels: 1.4 v output load (including scope & jig) dout 11.5 k 1.4 v 50 pf w read cycle hm62v8512a -8 -10 parameter symbol min max min max unit notes read cycle time t rc 85 100 ns address access time t aa 85 100 ns chip select access time t co 85 100 ns output enable to output valid t oe 45 50 ns chip selection to output in low-z t lz 10 10 ns 2 output enable to output in low-z t olz 5 5 ns 2 chip deselection to output in high-z t hz 0 35 0 40 ns 1, 2 output disable to output in high-z t ohz 0 35 0 40 ns 1, 2 output hold from address change t oh 10 10 ns
hm62v8512a series 9 write cycle hm62v8512 a -8 -10 parameter symbol min max min max unit notes write cycle time t wc 85 100 ns chip selection to end of write t cw 75 80 ns 4 address setup time t as 0 0 ns 5 address valid to end of write t aw 75 80 ns write pulse width t wp 55 60 ns 3, 12 write recovery time t wr 0 0 ns 6 we to output in high-z t whz 0 35 0 40 ns 1, 2, 7 data to write time overlap t dw 35 40 ns data hold from write time t dh 00ns output active from output in high-z t ow 5 5 ns 2 output disable to output in high-z t ohz 0 35 0 40 ns 1, 2, 7 notes: 1. t hz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs and a low we . a write begins at the later transition of cs going low or we going low. a write ends at the earlier transition of cs going high or we going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we or cs going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. if the cs low transition occurs simultaneously with the we low transition or after the we transition, the output remain in a high impedance state. 9. dout is the same phase of the write data of this write cycle. 10. dout is the read data of next address. 11. if cs is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention. t wp 3 t dw min + t whz max
hm62v8512a series 10 timing waveforms read timing waveform ( we = v ih ) t aa t co t rc t lz t oe t olz t hz t ohz valid data address cs oe dout t oh write timing waveform (1) ( oe clock)
hm62v8512a series 11 t wc t cw t wp t as t ohz t dw t dh t aw t wr *8 address oe cs we dout din valid data
hm62v8512a series 12 write timing waveform (2) ( oe low fixed) address cs we dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *11 *9 *10 *8 valid data low v cc data retention characteristics (ta = 0 to +70 c) parameter symbol min typ max unit test conditions* 3 v cc for data retention v dr 2v cs 3 v cc C 0.2 v, vin 3 0 v data retention current i ccdr 1* 4 50* 1 m av cc = 3.0 v, vin 3 0 v cs 3 v cc C 0.2 v 1* 4 15* 2 m a chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 5ms notes: 1. for l-version and 20 m a (max.) at ta = 0 to 40 c. 2. for sl-version and 3 m a (max.) at ta = 0 to 40 c. 3. cs controls address buffer, we buffer, oe buffer, and din buffer. in data retention mode, vin levels (address, we , oe , i/o) can be in the high impedance state. 4. typical values are at v cc = 3.0 v, ta = 25 c and specified loading, and not guaranteed.
hm62v8512a series 13 low v cc data retention timing waveform ( cs controlled) cc cc v 2.7 v 0.7 v 0 v cs t cdr t r cs v ?0.2 v cc 3 dr v data retention mode package dimensions hm62v8512alfp series (fp-32d) unit: mm 0.15 m 0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max 0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 hitachi code jedec code eiaj code weight fp-32d 1.3 g 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04
hm62v8512a series 14 hm62v8512altt series (ttp-32d) unit: mm 1.27 0.21 m 0.42 0.08 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.13 0.05 0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 hitachi code jedec code eiaj code weight ttp-32d mo-133ca 0.51 g 0.40 0.06 0.125 0.04
hm62v8512a series 15 hm62v8512alrr series (ttp-32dr) unit: mm 1.27 0.21 m 0.42 0.08 0.10 10.16 20.95 21.35 max 16 17 1 32 1.20 max 0 ?5 0.13 0.05 0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 hitachi code jedec code eiaj code weight ttp-32dr mo-133ca 0.51 g 0.40 0.06 0.125 0.04
hm62v8512a series 16 disclaimer when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. address hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071
hm62v8512a series 17 revision record rev. date contents of modification drawn by approved by 0.0 sep. 30, 1996 initial issue

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