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kaj000a30m revision 1.0 september 2003 - 1 - preliminary mcp memory document title multi-chip package memory 64m bit (4mx16) u t ram / 64m bit (4mx16) u t ram / 8m bit ( 512kx16 ) sram revision history revision no. 0.0 0.1 1.0 remark preliminary preliminary final history initial draft. revised - changed ball name from vccqs to vccs in pin configuration. finalized - changed tpc from max 25ns to min 25ns in the ac characteristics. draft date may 12, 2003 july 11, 2003 september 22, 2003 the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. note : for more detailed features and specifications including faq, please refer to samsung?s web site. http://samsungelectronics.com/semiconductors/products/products_index.html
kaj000a30m revision 1.0 september 2003 - 2 - preliminary mcp memory multi-chip package memory 64m bit (4mx16) u t ram / 64m bit (4mx16) u t ram / 8m bit ( 512kx16 ) sram features operating temperature : -25 c ~ 85 c package : 111 - ball fbga type - 10 x 11mm, 0.8 mm pitch power supply voltage: 2.7~3.1v organization: 4m x16 bit three state outputs compatible with low power sram support 4 page mode (read only) deep power down: memory cell data hold invalid process technology: full cmos organization: 512k x16 power supply voltage: 2.7~3.3v low data retention voltage: 1.5v(min) three state outputs general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. the kaj000a30m is a multi chip package memory which com- bines two 64mbit unit transistor cmos ram and 8mbit sram. 64mbit u t ram is organized as 4m x16 bit and 8mbit sram is organized as 512k x16 bit. the 64mbit u t ram is fabricated by samsung s advanced cmos technology using one transistor memory cell. the device support page mode operation. the device also supports deep power down mode for low standby current. the 8mbit sram is fabricated by samsung s advanced full cmos process technology. the device supports low data reten- tion voltage for battery back-up operation with low data retention current. the kaj000a30m is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. this device is available in 111-ball fbga type.
kaj000a30m revision 1.0 september 2003 - 3 - preliminary mcp memory pin configuration 111-fbga: top view (ball down) dnu 1 2 3 4 5 6 a b c d e f g h dnu dnu dnu a12 a8 we vccu a19 a7 a3 a1 dnu a13 a9 a20 vccs lb a6 a4 a2 a14 a10 a21 ub nc a5 vss a15 a11 zz 1 a18 nc nc nc nc nc nc nc nc vss nc nc nc nc nc nc nc nc nc nc nc a16 nc dq5 dq0 nc nc dq7 dq13 nc dq11 dq3 dq8 a0 vss dnu dnu dnu dnu 7 8 10 9 j k l m dnu dq15 dq6 dq4 vccs vccs dq1 cs u1 cs 1s dnu dnu vss dq14 dq12 vccu vccqu dq9 oe vss dnu dnu dnu dnu dnu dnu dnu 12 11 n dnu dnu dnu dnu a17 zz 2 cs2s nc nc nc nc cs u2 nc dq2 dq10
kaj000a30m revision 1.0 september 2003 - 4 - preliminary mcp memory ordering information k a j 00 0 a 3 0 m - f lll samsung mcp(3 chip) memory device type u t ram+u t ram+sram nor flash density , vcc , org. 00 : none sram density , vcc , org. 3 : 8mbit, 3.0v, x16 sdram density , vcc , org. 0 : none access time l : u t ram : 70ns l : u t ram : 70ns l : sram : 70ns u t ram density , vcc , org. a : 64mbit + 64mbit, 3.0v, x16(page) version m : 1st generation nand flash density , vcc , org. 0 : none package f : fbga ball name description ball name description a 0 to a 18 address input balls (utram,sram) zz 2 deep power down (utram2) a 19 to a 21 address input balls (utram) cs u1 chip select (utram1) dq 0 to dq 15 data input/output balls (utram, sram) cs u2 chip select (utram2) vccu power supply (utram) cs 1s chip select (sram) vccs power supply (sram) cs2s chip select (sram) vccqu data out power (utram) we write enable (utram, sram) vss ground (common) oe output enable (utram, sram) ub upper byte enable (utram, sram) nc no connection lb lower byte enable (utram, sram) dnu do not use zz 1 deep power down (utram1) pin description
kaj000a30m revision 1.0 september 2003 - 5 - preliminary mcp memory figure 1. functional block diagram ub cs u1 vccu lb address(a0 to a18) 64m bit utram dq 0 to dq 15 dq 0 to dq 15 vss vccqu vccs 8m bit vss sram oe cs 1 s we dq 0 to dq 15 zz 1 cs2s address(a19 to a21) vccu 64m bit vss vccqu utram dq 0 to dq 15 zz 2 cs u2
kaj000a30m revision 1.0 september 2003 - 6 - preliminary mcp memory 64m bit(4mx16) page mode utram for each device
kaj000a30m revision 1.0 september 2003 - 7 - preliminary mcp memory functional description 1. x means don t care.(must be low or high state) cs zz oe we lb ub dq 0~7 dq 8~15 mode power h h x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected deep power down l h x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active min. 200 m s v cc zz cs timing waveform of power up ? (power up) 1. after v cc reaches v cc (min.), wait 200 m s with cs and zz high. then you get into the normal operation. v cc(min) ? ? normal operation power up sequence 1. apply power. 2. maintain stable power(vcc min.=2.7v) for a minimum 200 m s with cs and zz high. min. 0ns power up mode
kaj000a30m revision 1.0 september 2003 - 8 - preliminary mcp memory absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.2 to 3.6v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -25 to 85 c standby mode characteristic power mode memory cell data standby current( m m a) wait time( m m s) standby valid 120 0 deep power down invaild 20 200 zz =v il cs =v ih zz =v il cs =v il , ub or/and lb =v il zz =v ih cs =v ih , zz =v ih standby mode state machines power on initial state (wait 200 m s) active standby mode deep power down mode zz =v ih cs =v ih and zz =v ih
kaj000a30m revision 1.0 september 2003 - 9 - preliminary mcp memory dc and operating characteristics 1. typical values are tested at v cc =2.9v, t a =25 c and not guaranteed. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih, zz =v ih , oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, zz 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - - 15 ma i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs =v il , zz =v ih, v in =v il or v ih - - 45 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(cmos) i sb1 cs 3 vcc-0.2v, zz 3 vcc-0.2v, other inputs=vss to vcc - - 120 m a deep power down i sbd zz 0.2v, other inputs=vss to vcc - - 20 m a recommended dc operating conditions 1) 1. t a =-25 to 85 c, otherwise specified. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 2.7 2.9 3.1 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.2 2) v input low voltage v il -0.2 3) - 0.6 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf
kaj000a30m revision 1.0 september 2003 - 10 - preliminary mcp memory ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load: c l =50pf ac characteristics (v cc =2.7~3.1v, t a =-25 to 85 c) 1. t wp (min)=70ns for continuous write operation over 50 times. parameter list symbol speed bins units 70ns min max read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co - 70 ns output enable to valid output t oe - 35 ns ub , lb access time t ba - 70 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 25 ns ub , lb disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 5 - ns page cycle t pc 25 - ns page access time t pa - 20 ns write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 55 1) - ns write recovery time t wr 0 - ns write to output high-z t whz 0 25 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns
kaj000a30m revision 1.0 september 2003 - 11 - preliminary mcp memory address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , zz = we= v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( zz = we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. t oe (max) is met only when oe becomes enabled after t aa (max). 4. if invalid address signals shorter than min. t rc are continuously repeated for over 4us, the device needs a normal read timing(t rc ) or needs to sustain standby state for min. t rc at least once in every 4us. data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t co address cs ub , lb oe data out timing waveform of page cycle(read only) data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa high z a21~a2 a1~a0 cs oe t ohz t oe t co t aa data out
kaj000a30m revision 1.0 september 2003 - 12 - preliminary mcp memory t as(3) timing waveform of write cycle(1) ( we controlled , zz =v ih ) timing waveform of write cycle(2) ( cs controlled , zz =v ih ) address data undefined ub , lb we data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) cs t wr(4)
kaj000a30m revision 1.0 september 2003 - 13 - preliminary mcp memory timing waveform of write cycle(3) ( ub , lb controlled , zz =v ih ) (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs zz mode deep power down mode normal operation 0.5 m s 200 m s normal operation suspend wake up timing waveform of deep power down mode entry and exit ? ? cs (deep power down mode) 1. when you toggle zz pin low, the device gets into the deep power down mode after 0.5 m s suspend period. 2. to return to normal operation, the device needs wake up period. 3. wake up sequence is just the same as power up sequence.
kaj000a30m revision 1.0 september 2003 - 14 - preliminary mcp memory 8m bit( 512kx16) sram
kaj000a30m revision 1.0 september 2003 - 15 - preliminary mcp memory absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions over 1 second may af fect reliability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v(max. 3.6v) v voltage on vcc supply relative to vss v cc -0.2 to 3.6 v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -25 to 85 c functional description 1. x means don t care. (must be low or high state) cs 1 cs 2 oe we lb ub dq 0~7 dq 8~15 mode power h x 1) x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active
kaj000a30m revision 1.0 september 2003 - 16 - preliminary mcp memory recommended dc operating conditions 1) note: 1. t a =-25 to 85 c, otherwise specified. 2. overshoot: v cc +2.0v in case of pulse width 20ns. 3. undershoot: -2.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 2.7 3.0 3.3 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.2 2) v input low voltage v il -0.2 3) - 0.6 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristic 1. typical values are measured at v cc =3.0v, t a =25 c and not 100% tested. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il or lb = ub =v ih , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, lb 0.2v or/and ub 0.2v, cs 2 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - - 5 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs 1 =v il , cs 2 =v ih , lb =v il or/and ub =v il , v in =v il or v ih 70ns - - 30 ma output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v standby current(cmos) i sb1 other input =0~vcc 1) cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or 2) 0v cs 2 0.2v(cs 2 controlled) - - 25 m a
kaj000a30m revision 1.0 september 2003 - 17 - preliminary mcp memory ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load(see right): c l =100pf+1ttl data retention characteristics 1. 1) cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or 2) 0 cs 2 0.2v(cs 2 controlled) 2. typical values are measured at t a =25 c and not 100% tested. item symbol test condition min typ 2) max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 1.5 - 3.3 v data retention current i dr vcc=1.5v, cs 1 3 vcc-0.2v 1) - - 15 m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr trc - - ac characteristics (vcc=2.7~3.3v, industrial product: t a =-25 to 85 c) parameter list symbol speed bins units 70ns min max read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co - 70 ns output enable to valid output t oe - 35 ns ub , lb access time t ba - 70 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 25 ns ub , lb disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 10 - ns write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 50 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.8v
kaj000a30m revision 1.0 september 2003 - 18 - preliminary mcp memory address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , cs 2 = we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs 1 address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2
kaj000a30m revision 1.0 september 2003 - 19 - preliminary mcp memory timing waveform of write cycle(2) ( cs 1 controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs 1 cs 2 timing waveform of write cycle(1) ( we controlled) address cs 1 data undefined ub , lb we data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs 2
kaj000a30m revision 1.0 september 2003 - 20 - preliminary mcp memory address data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs 1 or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs 1 controlled v cc 2.7v 2.2v v dr cs 1 gnd data retention mode cs 1 3 v cc - 0.2v t sdr t rdr t as(3) cs 1 cs 2 cs 2 controlled v cc 2.7v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
kaj000a30m revision 1.0 september 2003 - 21 - preliminary mcp memory package dimension 111-ball fine pitch bga package (measured in millimeters) 1 1 . 0 0 0 . 1 0 0 . 8 0 x 1 2 = 9 . 6 0 0 . 8 0 4 . 8 0 10.00 0.10 0.80 0.80 x 11 = 8.80 4.40 b 0.10 max 0 . 4 5 0 . 0 5 0.2 m a b 111 - ? 0.45 0.05 ? bottom view top view a b c d e f g h 7 5 4 3 2 1 6 8 9 10 11 j k l m n 12 a #a1 index mark(optional) 1 1 . 0 0 0 . 1 0 10.00 0.10 1 1 . 0 0 0 . 1 0 0.32 0.05 1.30 0.10 #a1 (datum a) (datum b)

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